1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, v.1, (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://opensource.org/licenses/CDDL-1.0. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2014-2017 Cavium, Inc. 24 * The contents of this file are subject to the terms of the Common Development 25 * and Distribution License, v.1, (the "License"). 26 27 * You may not use this file except in compliance with the License. 28 29 * You can obtain a copy of the License at available 30 * at http://opensource.org/licenses/CDDL-1.0 31 32 * See the License for the specific language governing permissions and 33 * limitations under the License. 34 */ 35 36 #ifndef _INIT_FW_FUNCS_H 37 #define _INIT_FW_FUNCS_H 38 /* Forward declarations */ 39 40 struct init_qm_pq_params; 41 42 /** 43 * @brief ecore_qm_pf_mem_size - Prepare QM ILT sizes 44 * 45 * Returns the required host memory size in 4KB units. 46 * Must be called before all QM init HSI functions. 47 * 48 * @param pf_id - physical function ID 49 * @param num_pf_cids - number of connections used by this PF 50 * @param num_vf_cids - number of connections used by VFs of this PF 51 * @param num_tids - number of tasks used by this PF 52 * @param num_pf_pqs - number of PQs used by this PF 53 * @param num_vf_pqs - number of PQs used by VFs of this PF 54 * 55 * @return The required host memory size in 4KB units. 56 */ 57 u32 ecore_qm_pf_mem_size(u8 pf_id, 58 u32 num_pf_cids, 59 u32 num_vf_cids, 60 u32 num_tids, 61 u16 num_pf_pqs, 62 u16 num_vf_pqs); 63 64 /** 65 * @brief ecore_qm_common_rt_init - Prepare QM runtime init values for the 66 * engine phase. 67 * 68 * @param p_hwfn - HW device data 69 * @param max_ports_per_engine - max number of ports per engine in HW 70 * @param max_phys_tcs_per_port - max number of physical TCs per port in HW 71 * @param pf_rl_en - enable per-PF rate limiters 72 * @param pf_wfq_en - enable per-PF WFQ 73 * @param vport_rl_en - enable per-VPORT rate limiters 74 * @param vport_wfq_en - enable per-VPORT WFQ 75 * @param port_params - array of size MAX_NUM_PORTS with parameters 76 * for each port 77 * 78 * @return 0 on success, -1 on error. 79 */ 80 int ecore_qm_common_rt_init(struct ecore_hwfn *p_hwfn, 81 u8 max_ports_per_engine, 82 u8 max_phys_tcs_per_port, 83 bool pf_rl_en, 84 bool pf_wfq_en, 85 bool vport_rl_en, 86 bool vport_wfq_en, 87 struct init_qm_port_params port_params[MAX_NUM_PORTS]); 88 89 /** 90 * @brief ecore_qm_pf_rt_init - Prepare QM runtime init values for the PF phase 91 * 92 * @param p_hwfn - HW device data 93 * @param p_ptt - ptt window used for writing the registers 94 * @param port_id - port ID 95 * @param pf_id - PF ID 96 * @param max_phys_tcs_per_port - max number of physical TCs per port in HW 97 * @param is_first_pf - 1 = first PF in engine, 0 = othwerwise 98 * @param num_pf_cids - number of connections used by this PF 99 * @param num_vf_cids - number of connections used by VFs of this PF 100 * @param num_tids - number of tasks used by this PF 101 * @param start_pq - first Tx PQ ID associated with this PF 102 * @param num_pf_pqs - number of Tx PQs associated with this PF 103 * (non-VF) 104 * @param num_vf_pqs - number of Tx PQs associated with a VF 105 * @param start_vport - first VPORT ID associated with this PF 106 * @param num_vports - number of VPORTs associated with this PF 107 * @param pf_wfq - WFQ weight. if PF WFQ is globally disabled, 108 * the weight must be 0. otherwise, the weight 109 * must be non-zero. 110 * @param pf_rl - rate limit in Mb/sec units. a value of 0 111 * means don't configure. ignored if PF RL is 112 * globally disabled. 113 * @param pq_params - array of size (num_pf_pqs + num_vf_pqs) with 114 * parameters for each Tx PQ associated with the 115 * specified PF. 116 * @param vport_params - array of size num_vports with parameters for 117 * each associated VPORT. 118 * 119 * @return 0 on success, -1 on error. 120 */ 121 int ecore_qm_pf_rt_init(struct ecore_hwfn *p_hwfn, 122 struct ecore_ptt *p_ptt, 123 u8 port_id, 124 u8 pf_id, 125 u8 max_phys_tcs_per_port, 126 bool is_first_pf, 127 u32 num_pf_cids, 128 u32 num_vf_cids, 129 u32 num_tids, 130 u16 start_pq, 131 u16 num_pf_pqs, 132 u16 num_vf_pqs, 133 u8 start_vport, 134 u8 num_vports, 135 u16 pf_wfq, 136 u32 pf_rl, 137 struct init_qm_pq_params *pq_params, 138 struct init_qm_vport_params *vport_params); 139 140 /** 141 * @brief ecore_init_pf_wfq - Initializes the WFQ weight of the specified PF 142 * 143 * @param p_hwfn - HW device data 144 * @param p_ptt - ptt window used for writing the registers 145 * @param pf_id - PF ID 146 * @param pf_wfq - WFQ weight. Must be non-zero. 147 * 148 * @return 0 on success, -1 on error. 149 */ 150 int ecore_init_pf_wfq(struct ecore_hwfn *p_hwfn, 151 struct ecore_ptt *p_ptt, 152 u8 pf_id, 153 u16 pf_wfq); 154 155 /** 156 * @brief ecore_init_pf_rl - Initializes the rate limit of the specified PF 157 * 158 * @param p_hwfn 159 * @param p_ptt - ptt window used for writing the registers 160 * @param pf_id - PF ID 161 * @param pf_rl - rate limit in Mb/sec units 162 * 163 * @return 0 on success, -1 on error. 164 */ 165 int ecore_init_pf_rl(struct ecore_hwfn *p_hwfn, 166 struct ecore_ptt *p_ptt, 167 u8 pf_id, 168 u32 pf_rl); 169 170 /** 171 * @brief ecore_init_vport_wfq - Initializes the WFQ weight of the specified VPORT 172 * 173 * @param p_hwfn - HW device data 174 * @param p_ptt - ptt window used for writing the registers 175 * @param first_tx_pq_id - An array containing the first Tx PQ ID associated 176 * with the VPORT for each TC. This array is filled by 177 * ecore_qm_pf_rt_init 178 * @param vport_wfq - WFQ weight. Must be non-zero. 179 * 180 * @return 0 on success, -1 on error. 181 */ 182 int ecore_init_vport_wfq(struct ecore_hwfn *p_hwfn, 183 struct ecore_ptt *p_ptt, 184 u16 first_tx_pq_id[NUM_OF_TCS], 185 u16 vport_wfq); 186 187 /** 188 * @brief ecore_init_vport_rl - Initializes the rate limit of the specified 189 * VPORT. 190 * 191 * @param p_hwfn - HW device data 192 * @param p_ptt - ptt window used for writing the registers 193 * @param vport_id - VPORT ID 194 * @param vport_rl - rate limit in Mb/sec units 195 * 196 * @return 0 on success, -1 on error. 197 */ 198 int ecore_init_vport_rl(struct ecore_hwfn *p_hwfn, 199 struct ecore_ptt *p_ptt, 200 u8 vport_id, 201 u32 vport_rl); 202 203 /** 204 * @brief ecore_send_qm_stop_cmd - Sends a stop command to the QM 205 * 206 * @param p_hwfn - HW device data 207 * @param p_ptt - ptt window used for writing the registers 208 * @param is_release_cmd - true for release, false for stop. 209 * @param is_tx_pq - true for Tx PQs, false for Other PQs. 210 * @param start_pq - first PQ ID to stop 211 * @param num_pqs - Number of PQs to stop, starting from start_pq. 212 * 213 * @return bool, true if successful, false if timeout occured while waiting for 214 * QM command done. 215 */ 216 bool ecore_send_qm_stop_cmd(struct ecore_hwfn *p_hwfn, 217 struct ecore_ptt *p_ptt, 218 bool is_release_cmd, 219 bool is_tx_pq, 220 u16 start_pq, 221 u16 num_pqs); 222 223 #ifndef UNUSED_HSI_FUNC 224 225 /** 226 * @brief ecore_init_nig_ets - Initializes the NIG ETS arbiter 227 * 228 * Based on weight/priority requirements per-TC. 229 * 230 * @param p_hwfn - HW device data 231 * @param p_ptt - ptt window used for writing the registers. 232 * @param req - the NIG ETS initialization requirements. 233 * @param is_lb - if set, the loopback port arbiter is initialized, otherwise 234 * the physical port arbiter is initialized. The pure-LB TC 235 * requirements are ignored when is_lb is cleared. 236 */ 237 void ecore_init_nig_ets(struct ecore_hwfn *p_hwfn, 238 struct ecore_ptt *p_ptt, 239 struct init_ets_req* req, 240 bool is_lb); 241 242 /** 243 * @brief ecore_init_nig_lb_rl - Initializes the NIG LB RLs 244 * 245 * Based on global and per-TC rate requirements 246 * 247 * @param p_hwfn - HW device data 248 * @param p_ptt - ptt window used for writing the registers. 249 * @param req - the NIG LB RLs initialization requirements. 250 */ 251 void ecore_init_nig_lb_rl(struct ecore_hwfn *p_hwfn, 252 struct ecore_ptt *p_ptt, 253 struct init_nig_lb_rl_req* req); 254 255 #endif /* UNUSED_HSI_FUNC */ 256 257 /** 258 * @brief ecore_init_nig_pri_tc_map - Initializes the NIG priority to TC map. 259 * 260 * Assumes valid arguments. 261 * 262 * @param p_hwfn - HW device data 263 * @param p_ptt - ptt window used for writing the registers. 264 * @param req - required mapping from prioirties to TCs. 265 */ 266 void ecore_init_nig_pri_tc_map(struct ecore_hwfn *p_hwfn, 267 struct ecore_ptt *p_ptt, 268 struct init_nig_pri_tc_map_req* req); 269 270 #ifndef UNUSED_HSI_FUNC 271 272 /** 273 * @brief ecore_init_prs_ets - Initializes the PRS Rx ETS arbiter 274 * 275 * Based on weight/priority requirements per-TC. 276 * 277 * @param p_hwfn - HW device data 278 * @param p_ptt - ptt window used for writing the registers. 279 * @param req - the PRS ETS initialization requirements. 280 */ 281 void ecore_init_prs_ets(struct ecore_hwfn *p_hwfn, 282 struct ecore_ptt *p_ptt, 283 struct init_ets_req* req); 284 285 #endif /* UNUSED_HSI_FUNC */ 286 #ifndef UNUSED_HSI_FUNC 287 288 /** 289 * @brief ecore_init_brb_ram - Initializes BRB RAM sizes per TC. 290 * 291 * Based on weight/priority requirements per-TC. 292 * 293 * @param p_hwfn - HW device data 294 * @param p_ptt - ptt window used for writing the registers. 295 * @param req - the BRB RAM initialization requirements. 296 */ 297 void ecore_init_brb_ram(struct ecore_hwfn *p_hwfn, 298 struct ecore_ptt *p_ptt, 299 struct init_brb_ram_req* req); 300 301 #endif /* UNUSED_HSI_FUNC */ 302 #ifndef UNUSED_HSI_FUNC 303 304 /** 305 * @brief ecore_set_engine_mf_ovlan_eth_type - Initializes Nig,Prs,Pbf and llh 306 * ethType Regs to input ethType. Should Be called once per engine if engine 307 * is in BD mode. 308 * 309 * @param p_hwfn - HW device data 310 * @param p_ptt - ptt window used for writing the registers. 311 * @param ethType - etherType to configure 312 */ 313 void ecore_set_engine_mf_ovlan_eth_type(struct ecore_hwfn *p_hwfn, 314 struct ecore_ptt *p_ptt, 315 u32 ethType); 316 317 /** 318 * @brief ecore_set_port_mf_ovlan_eth_type - initializes DORQ ethType Regs to 319 * input ethType. should Be called once per port. 320 * 321 * @param p_hwfn - HW device data 322 * @param p_ptt - ptt window used for writing the registers. 323 * @param ethType - etherType to configure 324 */ 325 void ecore_set_port_mf_ovlan_eth_type(struct ecore_hwfn *p_hwfn, 326 struct ecore_ptt *p_ptt, 327 u32 ethType); 328 329 #endif /* UNUSED_HSI_FUNC */ 330 331 /** 332 * @brief ecore_set_vxlan_dest_port - Initializes vxlan tunnel destination udp 333 * port. 334 * 335 * @param p_hwfn - HW device data 336 * @param p_ptt - ptt window used for writing the registers. 337 * @param dest_port - vxlan destination udp port. 338 */ 339 void ecore_set_vxlan_dest_port(struct ecore_hwfn *p_hwfn, 340 struct ecore_ptt *p_ptt, 341 u16 dest_port); 342 343 /** 344 * @brief ecore_set_vxlan_enable - Enable or disable VXLAN tunnel in HW 345 * 346 * @param p_hwfn - HW device data 347 * @param p_ptt - ptt window used for writing the registers. 348 * @param vxlan_enable - vxlan enable flag. 349 */ 350 void ecore_set_vxlan_enable(struct ecore_hwfn *p_hwfn, 351 struct ecore_ptt *p_ptt, 352 bool vxlan_enable); 353 354 /** 355 * @brief ecore_set_gre_enable - Enable or disable GRE tunnel in HW 356 * 357 * @param p_hwfn - HW device data 358 * @param p_ptt - ptt window used for writing the registers. 359 * @param eth_gre_enable - eth GRE enable enable flag. 360 * @param ip_gre_enable - IP GRE enable enable flag. 361 */ 362 void ecore_set_gre_enable(struct ecore_hwfn *p_hwfn, 363 struct ecore_ptt *p_ptt, 364 bool eth_gre_enable, 365 bool ip_gre_enable); 366 367 /** 368 * @brief ecore_set_geneve_dest_port - Initializes geneve tunnel destination 369 * udp port. 370 * 371 * @param p_hwfn - HW device data 372 * @param p_ptt - ptt window used for writing the registers. 373 * @param dest_port - geneve destination udp port. 374 */ 375 void ecore_set_geneve_dest_port(struct ecore_hwfn *p_hwfn, 376 struct ecore_ptt *p_ptt, 377 u16 dest_port); 378 379 /** 380 * @brief ecore_set_geneve_enable - Enable or disable GRE tunnel in HW 381 * 382 * @param p_hwfn - HW device data 383 * @param p_ptt - ptt window used for writing the registers. 384 * @param eth_geneve_enable - eth GENEVE enable enable flag. 385 * @param ip_geneve_enable - IP GENEVE enable enable flag. 386 */ 387 void ecore_set_geneve_enable(struct ecore_hwfn *p_hwfn, 388 struct ecore_ptt *p_ptt, 389 bool eth_geneve_enable, 390 bool ip_geneve_enable); 391 392 #ifndef UNUSED_HSI_FUNC 393 394 /** 395 * @brief ecore_set_gft_event_id_cm_hdr - Configure GFT event id and cm header 396 * 397 * @param p_hwfn - HW device data 398 * @param p_ptt - ptt window used for writing the registers. 399 */ 400 void ecore_set_gft_event_id_cm_hdr(struct ecore_hwfn *p_hwfn, 401 struct ecore_ptt *p_ptt); 402 403 /** 404 * @brief ecore_set_rfs_mode_disable - Disable and configure HW for RFS 405 * 406 * @param p_hwfn - HW device data 407 * @param p_ptt - ptt window used for writing the registers. 408 * @param pf_id - pf on which to disable RFS. 409 */ 410 void ecore_set_rfs_mode_disable(struct ecore_hwfn *p_hwfn, 411 struct ecore_ptt *p_ptt, 412 u16 pf_id); 413 414 /** 415 * @brief ecore_set_rfs_mode_enable - Enable and configure HW for RFS 416 * 417 * @param p_hwfn - HW device data 418 * @param p_ptt - ptt window used for writing the registers. 419 * @param pf_id - pf on which to enable RFS. 420 * @param tcp - set profile tcp packets. 421 * @param udp - set profile udp packet. 422 * @param ipv4 - set profile ipv4 packet. 423 * @param ipv6 - set profile ipv6 packet. 424 */ 425 void ecore_set_rfs_mode_enable(struct ecore_hwfn *p_hwfn, 426 struct ecore_ptt *p_ptt, 427 u16 pf_id, 428 bool tcp, 429 bool udp, 430 bool ipv4, 431 bool ipv6); 432 433 #endif /* UNUSED_HSI_FUNC */ 434 435 /** 436 * @brief ecore_config_vf_zone_size_mode - Configure VF zone size mode. Must be 437 * used before first ETH queue started. 438 * 439 * @param p_hwfn - HW device data 440 * @param p_ptt - ptt window used for writing the registers. Don't care 441 * if runtime_init used. 442 * @param mode - VF zone size mode. Use enum vf_zone_size_mode. 443 * @param runtime_init - Set 1 to init runtime registers in engine phase. 444 * Set 0 if VF zone size mode configured after engine 445 * phase. 446 */ 447 void ecore_config_vf_zone_size_mode(struct ecore_hwfn *p_hwfn, 448 struct ecore_ptt *p_ptt, 449 u16 mode, 450 bool runtime_init); 451 452 /** 453 * @brief ecore_get_mstorm_queue_stat_offset - Get mstorm statistics offset by 454 * VF zone size mode. 455 * 456 * @param p_hwfn - HW device data 457 * @param stat_cnt_id - statistic counter id 458 * @param vf_zone_size_mode - VF zone size mode. Use enum vf_zone_size_mode. 459 */ 460 u32 ecore_get_mstorm_queue_stat_offset(struct ecore_hwfn *p_hwfn, 461 u16 stat_cnt_id, 462 u16 vf_zone_size_mode); 463 464 /** 465 * @brief ecore_get_mstorm_eth_vf_prods_offset - VF producer offset by VF zone 466 * size mode. 467 * 468 * @param p_hwfn - HW device data 469 * @param vf_id - vf id. 470 * @param vf_queue_id - per VF rx queue id. 471 * @param vf_zone_size_mode - vf zone size mode. Use enum vf_zone_size_mode. 472 */ 473 u32 ecore_get_mstorm_eth_vf_prods_offset(struct ecore_hwfn *p_hwfn, 474 u8 vf_id, 475 u8 vf_queue_id, 476 u16 vf_zone_size_mode); 477 478 /** 479 * @brief ecore_enable_context_validation - Enable and configure context 480 * validation. 481 * 482 * @param p_hwfn - HW device data 483 * @param p_ptt - ptt window used for writing the registers. 484 */ 485 void ecore_enable_context_validation(struct ecore_hwfn *p_hwfn, 486 struct ecore_ptt *p_ptt); 487 488 /** 489 * @brief ecore_calc_session_ctx_validation - Calcualte validation byte for 490 * session context. 491 * 492 * @param p_ctx_mem - pointer to context memory. 493 * @param ctx_size - context size. 494 * @param ctx_type - context type. 495 * @param cid - context cid. 496 */ 497 void ecore_calc_session_ctx_validation(struct ecore_hwfn * p_hwfn, 498 void *p_ctx_mem, 499 u16 ctx_size, 500 u8 ctx_type, 501 u32 cid); 502 503 /** 504 * @brief ecore_calc_task_ctx_validation - Calcualte validation byte for task 505 * context. 506 * 507 * @param p_hwfn - HW device data 508 * @param p_ctx_mem - pointer to context memory. 509 * @param ctx_size - context size. 510 * @param ctx_type - context type. 511 * @param tid - context tid. 512 */ 513 void ecore_calc_task_ctx_validation(struct ecore_hwfn * p_hwfn, 514 void *p_ctx_mem, 515 u16 ctx_size, 516 u8 ctx_type, 517 u32 tid); 518 519 /** 520 * @brief ecore_memset_session_ctx - Memset session context to 0 while 521 * preserving validation bytes. 522 * 523 * @param p_hwfn - HW device data 524 * @param p_ctx_mem - pointer to context memory. 525 * @param ctx_size - size to initialzie. 526 * @param ctx_type - context type. 527 */ 528 void ecore_memset_session_ctx(void *p_ctx_mem, 529 u32 ctx_size, 530 u8 ctx_type); 531 532 /** 533 * @brief ecore_memset_task_ctx - Memset task context to 0 while preserving 534 * validation bytes. 535 * 536 * @param p_ctx_mem - pointer to context memory. 537 * @param ctx_size - size to initialzie. 538 * @param ctx_type - context type. 539 */ 540 void ecore_memset_task_ctx(void *p_ctx_mem, 541 u32 ctx_size, 542 u8 ctx_type); 543 544 #endif 545