1*14b24e2bSVaishali Kulkarni /* 2*14b24e2bSVaishali Kulkarni * CDDL HEADER START 3*14b24e2bSVaishali Kulkarni * 4*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the 5*14b24e2bSVaishali Kulkarni * Common Development and Distribution License, v.1, (the "License"). 6*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License. 7*14b24e2bSVaishali Kulkarni * 8*14b24e2bSVaishali Kulkarni * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*14b24e2bSVaishali Kulkarni * or http://opensource.org/licenses/CDDL-1.0. 10*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions 11*14b24e2bSVaishali Kulkarni * and limitations under the License. 12*14b24e2bSVaishali Kulkarni * 13*14b24e2bSVaishali Kulkarni * When distributing Covered Code, include this CDDL HEADER in each 14*14b24e2bSVaishali Kulkarni * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*14b24e2bSVaishali Kulkarni * If applicable, add the following below this CDDL HEADER, with the 16*14b24e2bSVaishali Kulkarni * fields enclosed by brackets "[]" replaced with your own identifying 17*14b24e2bSVaishali Kulkarni * information: Portions Copyright [yyyy] [name of copyright owner] 18*14b24e2bSVaishali Kulkarni * 19*14b24e2bSVaishali Kulkarni * CDDL HEADER END 20*14b24e2bSVaishali Kulkarni */ 21*14b24e2bSVaishali Kulkarni 22*14b24e2bSVaishali Kulkarni /* 23*14b24e2bSVaishali Kulkarni * Copyright 2014-2017 Cavium, Inc. 24*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the Common Development 25*14b24e2bSVaishali Kulkarni * and Distribution License, v.1, (the "License"). 26*14b24e2bSVaishali Kulkarni 27*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License. 28*14b24e2bSVaishali Kulkarni 29*14b24e2bSVaishali Kulkarni * You can obtain a copy of the License at available 30*14b24e2bSVaishali Kulkarni * at http://opensource.org/licenses/CDDL-1.0 31*14b24e2bSVaishali Kulkarni 32*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions and 33*14b24e2bSVaishali Kulkarni * limitations under the License. 34*14b24e2bSVaishali Kulkarni */ 35*14b24e2bSVaishali Kulkarni 36*14b24e2bSVaishali Kulkarni #ifndef __ECORE_HSI_DEBUG_TOOLS__ 37*14b24e2bSVaishali Kulkarni #define __ECORE_HSI_DEBUG_TOOLS__ 38*14b24e2bSVaishali Kulkarni /****************************************/ 39*14b24e2bSVaishali Kulkarni /* Debug Tools HSI constants and macros */ 40*14b24e2bSVaishali Kulkarni /****************************************/ 41*14b24e2bSVaishali Kulkarni 42*14b24e2bSVaishali Kulkarni 43*14b24e2bSVaishali Kulkarni enum block_addr 44*14b24e2bSVaishali Kulkarni { 45*14b24e2bSVaishali Kulkarni GRCBASE_GRC = 0x50000, 46*14b24e2bSVaishali Kulkarni GRCBASE_MISCS = 0x9000, 47*14b24e2bSVaishali Kulkarni GRCBASE_MISC = 0x8000, 48*14b24e2bSVaishali Kulkarni GRCBASE_DBU = 0xa000, 49*14b24e2bSVaishali Kulkarni GRCBASE_PGLUE_B = 0x2a8000, 50*14b24e2bSVaishali Kulkarni GRCBASE_CNIG = 0x218000, 51*14b24e2bSVaishali Kulkarni GRCBASE_CPMU = 0x30000, 52*14b24e2bSVaishali Kulkarni GRCBASE_NCSI = 0x40000, 53*14b24e2bSVaishali Kulkarni GRCBASE_OPTE = 0x53000, 54*14b24e2bSVaishali Kulkarni GRCBASE_BMB = 0x540000, 55*14b24e2bSVaishali Kulkarni GRCBASE_PCIE = 0x54000, 56*14b24e2bSVaishali Kulkarni GRCBASE_MCP = 0xe00000, 57*14b24e2bSVaishali Kulkarni GRCBASE_MCP2 = 0x52000, 58*14b24e2bSVaishali Kulkarni GRCBASE_PSWHST = 0x2a0000, 59*14b24e2bSVaishali Kulkarni GRCBASE_PSWHST2 = 0x29e000, 60*14b24e2bSVaishali Kulkarni GRCBASE_PSWRD = 0x29c000, 61*14b24e2bSVaishali Kulkarni GRCBASE_PSWRD2 = 0x29d000, 62*14b24e2bSVaishali Kulkarni GRCBASE_PSWWR = 0x29a000, 63*14b24e2bSVaishali Kulkarni GRCBASE_PSWWR2 = 0x29b000, 64*14b24e2bSVaishali Kulkarni GRCBASE_PSWRQ = 0x280000, 65*14b24e2bSVaishali Kulkarni GRCBASE_PSWRQ2 = 0x240000, 66*14b24e2bSVaishali Kulkarni GRCBASE_PGLCS = 0x0, 67*14b24e2bSVaishali Kulkarni GRCBASE_DMAE = 0xc000, 68*14b24e2bSVaishali Kulkarni GRCBASE_PTU = 0x560000, 69*14b24e2bSVaishali Kulkarni GRCBASE_TCM = 0x1180000, 70*14b24e2bSVaishali Kulkarni GRCBASE_MCM = 0x1200000, 71*14b24e2bSVaishali Kulkarni GRCBASE_UCM = 0x1280000, 72*14b24e2bSVaishali Kulkarni GRCBASE_XCM = 0x1000000, 73*14b24e2bSVaishali Kulkarni GRCBASE_YCM = 0x1080000, 74*14b24e2bSVaishali Kulkarni GRCBASE_PCM = 0x1100000, 75*14b24e2bSVaishali Kulkarni GRCBASE_QM = 0x2f0000, 76*14b24e2bSVaishali Kulkarni GRCBASE_TM = 0x2c0000, 77*14b24e2bSVaishali Kulkarni GRCBASE_DORQ = 0x100000, 78*14b24e2bSVaishali Kulkarni GRCBASE_BRB = 0x340000, 79*14b24e2bSVaishali Kulkarni GRCBASE_SRC = 0x238000, 80*14b24e2bSVaishali Kulkarni GRCBASE_PRS = 0x1f0000, 81*14b24e2bSVaishali Kulkarni GRCBASE_TSDM = 0xfb0000, 82*14b24e2bSVaishali Kulkarni GRCBASE_MSDM = 0xfc0000, 83*14b24e2bSVaishali Kulkarni GRCBASE_USDM = 0xfd0000, 84*14b24e2bSVaishali Kulkarni GRCBASE_XSDM = 0xf80000, 85*14b24e2bSVaishali Kulkarni GRCBASE_YSDM = 0xf90000, 86*14b24e2bSVaishali Kulkarni GRCBASE_PSDM = 0xfa0000, 87*14b24e2bSVaishali Kulkarni GRCBASE_TSEM = 0x1700000, 88*14b24e2bSVaishali Kulkarni GRCBASE_MSEM = 0x1800000, 89*14b24e2bSVaishali Kulkarni GRCBASE_USEM = 0x1900000, 90*14b24e2bSVaishali Kulkarni GRCBASE_XSEM = 0x1400000, 91*14b24e2bSVaishali Kulkarni GRCBASE_YSEM = 0x1500000, 92*14b24e2bSVaishali Kulkarni GRCBASE_PSEM = 0x1600000, 93*14b24e2bSVaishali Kulkarni GRCBASE_RSS = 0x238800, 94*14b24e2bSVaishali Kulkarni GRCBASE_TMLD = 0x4d0000, 95*14b24e2bSVaishali Kulkarni GRCBASE_MULD = 0x4e0000, 96*14b24e2bSVaishali Kulkarni GRCBASE_YULD = 0x4c8000, 97*14b24e2bSVaishali Kulkarni GRCBASE_XYLD = 0x4c0000, 98*14b24e2bSVaishali Kulkarni GRCBASE_PTLD = 0x590000, 99*14b24e2bSVaishali Kulkarni GRCBASE_YPLD = 0x5b0000, 100*14b24e2bSVaishali Kulkarni GRCBASE_PRM = 0x230000, 101*14b24e2bSVaishali Kulkarni GRCBASE_PBF_PB1 = 0xda0000, 102*14b24e2bSVaishali Kulkarni GRCBASE_PBF_PB2 = 0xda4000, 103*14b24e2bSVaishali Kulkarni GRCBASE_RPB = 0x23c000, 104*14b24e2bSVaishali Kulkarni GRCBASE_BTB = 0xdb0000, 105*14b24e2bSVaishali Kulkarni GRCBASE_PBF = 0xd80000, 106*14b24e2bSVaishali Kulkarni GRCBASE_RDIF = 0x300000, 107*14b24e2bSVaishali Kulkarni GRCBASE_TDIF = 0x310000, 108*14b24e2bSVaishali Kulkarni GRCBASE_CDU = 0x580000, 109*14b24e2bSVaishali Kulkarni GRCBASE_CCFC = 0x2e0000, 110*14b24e2bSVaishali Kulkarni GRCBASE_TCFC = 0x2d0000, 111*14b24e2bSVaishali Kulkarni GRCBASE_IGU = 0x180000, 112*14b24e2bSVaishali Kulkarni GRCBASE_CAU = 0x1c0000, 113*14b24e2bSVaishali Kulkarni GRCBASE_RGFS = 0xf00000, 114*14b24e2bSVaishali Kulkarni GRCBASE_RGSRC = 0x320000, 115*14b24e2bSVaishali Kulkarni GRCBASE_TGFS = 0xd00000, 116*14b24e2bSVaishali Kulkarni GRCBASE_TGSRC = 0x322000, 117*14b24e2bSVaishali Kulkarni GRCBASE_UMAC = 0x51000, 118*14b24e2bSVaishali Kulkarni GRCBASE_XMAC = 0x210000, 119*14b24e2bSVaishali Kulkarni GRCBASE_DBG = 0x10000, 120*14b24e2bSVaishali Kulkarni GRCBASE_NIG = 0x500000, 121*14b24e2bSVaishali Kulkarni GRCBASE_WOL = 0x600000, 122*14b24e2bSVaishali Kulkarni GRCBASE_BMBN = 0x610000, 123*14b24e2bSVaishali Kulkarni GRCBASE_IPC = 0x20000, 124*14b24e2bSVaishali Kulkarni GRCBASE_NWM = 0x800000, 125*14b24e2bSVaishali Kulkarni GRCBASE_NWS = 0x700000, 126*14b24e2bSVaishali Kulkarni GRCBASE_MS = 0x6a0000, 127*14b24e2bSVaishali Kulkarni GRCBASE_PHY_PCIE = 0x620000, 128*14b24e2bSVaishali Kulkarni GRCBASE_LED = 0x6b8000, 129*14b24e2bSVaishali Kulkarni GRCBASE_AVS_WRAP = 0x6b0000, 130*14b24e2bSVaishali Kulkarni GRCBASE_MISC_AEU = 0x8000, 131*14b24e2bSVaishali Kulkarni GRCBASE_BAR0_MAP = 0x1c00000, 132*14b24e2bSVaishali Kulkarni MAX_BLOCK_ADDR 133*14b24e2bSVaishali Kulkarni }; 134*14b24e2bSVaishali Kulkarni 135*14b24e2bSVaishali Kulkarni 136*14b24e2bSVaishali Kulkarni enum block_id 137*14b24e2bSVaishali Kulkarni { 138*14b24e2bSVaishali Kulkarni BLOCK_GRC, 139*14b24e2bSVaishali Kulkarni BLOCK_MISCS, 140*14b24e2bSVaishali Kulkarni BLOCK_MISC, 141*14b24e2bSVaishali Kulkarni BLOCK_DBU, 142*14b24e2bSVaishali Kulkarni BLOCK_PGLUE_B, 143*14b24e2bSVaishali Kulkarni BLOCK_CNIG, 144*14b24e2bSVaishali Kulkarni BLOCK_CPMU, 145*14b24e2bSVaishali Kulkarni BLOCK_NCSI, 146*14b24e2bSVaishali Kulkarni BLOCK_OPTE, 147*14b24e2bSVaishali Kulkarni BLOCK_BMB, 148*14b24e2bSVaishali Kulkarni BLOCK_PCIE, 149*14b24e2bSVaishali Kulkarni BLOCK_MCP, 150*14b24e2bSVaishali Kulkarni BLOCK_MCP2, 151*14b24e2bSVaishali Kulkarni BLOCK_PSWHST, 152*14b24e2bSVaishali Kulkarni BLOCK_PSWHST2, 153*14b24e2bSVaishali Kulkarni BLOCK_PSWRD, 154*14b24e2bSVaishali Kulkarni BLOCK_PSWRD2, 155*14b24e2bSVaishali Kulkarni BLOCK_PSWWR, 156*14b24e2bSVaishali Kulkarni BLOCK_PSWWR2, 157*14b24e2bSVaishali Kulkarni BLOCK_PSWRQ, 158*14b24e2bSVaishali Kulkarni BLOCK_PSWRQ2, 159*14b24e2bSVaishali Kulkarni BLOCK_PGLCS, 160*14b24e2bSVaishali Kulkarni BLOCK_DMAE, 161*14b24e2bSVaishali Kulkarni BLOCK_PTU, 162*14b24e2bSVaishali Kulkarni BLOCK_TCM, 163*14b24e2bSVaishali Kulkarni BLOCK_MCM, 164*14b24e2bSVaishali Kulkarni BLOCK_UCM, 165*14b24e2bSVaishali Kulkarni BLOCK_XCM, 166*14b24e2bSVaishali Kulkarni BLOCK_YCM, 167*14b24e2bSVaishali Kulkarni BLOCK_PCM, 168*14b24e2bSVaishali Kulkarni BLOCK_QM, 169*14b24e2bSVaishali Kulkarni BLOCK_TM, 170*14b24e2bSVaishali Kulkarni BLOCK_DORQ, 171*14b24e2bSVaishali Kulkarni BLOCK_BRB, 172*14b24e2bSVaishali Kulkarni BLOCK_SRC, 173*14b24e2bSVaishali Kulkarni BLOCK_PRS, 174*14b24e2bSVaishali Kulkarni BLOCK_TSDM, 175*14b24e2bSVaishali Kulkarni BLOCK_MSDM, 176*14b24e2bSVaishali Kulkarni BLOCK_USDM, 177*14b24e2bSVaishali Kulkarni BLOCK_XSDM, 178*14b24e2bSVaishali Kulkarni BLOCK_YSDM, 179*14b24e2bSVaishali Kulkarni BLOCK_PSDM, 180*14b24e2bSVaishali Kulkarni BLOCK_TSEM, 181*14b24e2bSVaishali Kulkarni BLOCK_MSEM, 182*14b24e2bSVaishali Kulkarni BLOCK_USEM, 183*14b24e2bSVaishali Kulkarni BLOCK_XSEM, 184*14b24e2bSVaishali Kulkarni BLOCK_YSEM, 185*14b24e2bSVaishali Kulkarni BLOCK_PSEM, 186*14b24e2bSVaishali Kulkarni BLOCK_RSS, 187*14b24e2bSVaishali Kulkarni BLOCK_TMLD, 188*14b24e2bSVaishali Kulkarni BLOCK_MULD, 189*14b24e2bSVaishali Kulkarni BLOCK_YULD, 190*14b24e2bSVaishali Kulkarni BLOCK_XYLD, 191*14b24e2bSVaishali Kulkarni BLOCK_PTLD, 192*14b24e2bSVaishali Kulkarni BLOCK_YPLD, 193*14b24e2bSVaishali Kulkarni BLOCK_PRM, 194*14b24e2bSVaishali Kulkarni BLOCK_PBF_PB1, 195*14b24e2bSVaishali Kulkarni BLOCK_PBF_PB2, 196*14b24e2bSVaishali Kulkarni BLOCK_RPB, 197*14b24e2bSVaishali Kulkarni BLOCK_BTB, 198*14b24e2bSVaishali Kulkarni BLOCK_PBF, 199*14b24e2bSVaishali Kulkarni BLOCK_RDIF, 200*14b24e2bSVaishali Kulkarni BLOCK_TDIF, 201*14b24e2bSVaishali Kulkarni BLOCK_CDU, 202*14b24e2bSVaishali Kulkarni BLOCK_CCFC, 203*14b24e2bSVaishali Kulkarni BLOCK_TCFC, 204*14b24e2bSVaishali Kulkarni BLOCK_IGU, 205*14b24e2bSVaishali Kulkarni BLOCK_CAU, 206*14b24e2bSVaishali Kulkarni BLOCK_RGFS, 207*14b24e2bSVaishali Kulkarni BLOCK_RGSRC, 208*14b24e2bSVaishali Kulkarni BLOCK_TGFS, 209*14b24e2bSVaishali Kulkarni BLOCK_TGSRC, 210*14b24e2bSVaishali Kulkarni BLOCK_UMAC, 211*14b24e2bSVaishali Kulkarni BLOCK_XMAC, 212*14b24e2bSVaishali Kulkarni BLOCK_DBG, 213*14b24e2bSVaishali Kulkarni BLOCK_NIG, 214*14b24e2bSVaishali Kulkarni BLOCK_WOL, 215*14b24e2bSVaishali Kulkarni BLOCK_BMBN, 216*14b24e2bSVaishali Kulkarni BLOCK_IPC, 217*14b24e2bSVaishali Kulkarni BLOCK_NWM, 218*14b24e2bSVaishali Kulkarni BLOCK_NWS, 219*14b24e2bSVaishali Kulkarni BLOCK_MS, 220*14b24e2bSVaishali Kulkarni BLOCK_PHY_PCIE, 221*14b24e2bSVaishali Kulkarni BLOCK_LED, 222*14b24e2bSVaishali Kulkarni BLOCK_AVS_WRAP, 223*14b24e2bSVaishali Kulkarni BLOCK_MISC_AEU, 224*14b24e2bSVaishali Kulkarni BLOCK_BAR0_MAP, 225*14b24e2bSVaishali Kulkarni MAX_BLOCK_ID 226*14b24e2bSVaishali Kulkarni }; 227*14b24e2bSVaishali Kulkarni 228*14b24e2bSVaishali Kulkarni 229*14b24e2bSVaishali Kulkarni /* 230*14b24e2bSVaishali Kulkarni * binary debug buffer types 231*14b24e2bSVaishali Kulkarni */ 232*14b24e2bSVaishali Kulkarni enum bin_dbg_buffer_type 233*14b24e2bSVaishali Kulkarni { 234*14b24e2bSVaishali Kulkarni BIN_BUF_DBG_MODE_TREE /* init modes tree */, 235*14b24e2bSVaishali Kulkarni BIN_BUF_DBG_DUMP_REG /* GRC Dump registers */, 236*14b24e2bSVaishali Kulkarni BIN_BUF_DBG_DUMP_MEM /* GRC Dump memories */, 237*14b24e2bSVaishali Kulkarni BIN_BUF_DBG_IDLE_CHK_REGS /* Idle Check registers */, 238*14b24e2bSVaishali Kulkarni BIN_BUF_DBG_IDLE_CHK_IMMS /* Idle Check immediates */, 239*14b24e2bSVaishali Kulkarni BIN_BUF_DBG_IDLE_CHK_RULES /* Idle Check rules */, 240*14b24e2bSVaishali Kulkarni BIN_BUF_DBG_IDLE_CHK_PARSING_DATA /* Idle Check parsing data */, 241*14b24e2bSVaishali Kulkarni BIN_BUF_DBG_ATTN_BLOCKS /* Attention blocks */, 242*14b24e2bSVaishali Kulkarni BIN_BUF_DBG_ATTN_REGS /* Attention registers */, 243*14b24e2bSVaishali Kulkarni BIN_BUF_DBG_ATTN_INDEXES /* Attention indexes */, 244*14b24e2bSVaishali Kulkarni BIN_BUF_DBG_ATTN_NAME_OFFSETS /* Attention name offsets */, 245*14b24e2bSVaishali Kulkarni BIN_BUF_DBG_BUS_BLOCKS /* Debug Bus blocks */, 246*14b24e2bSVaishali Kulkarni BIN_BUF_DBG_BUS_LINES /* Debug Bus lines */, 247*14b24e2bSVaishali Kulkarni BIN_BUF_DBG_BUS_BLOCKS_USER_DATA /* Debug Bus blocks user data */, 248*14b24e2bSVaishali Kulkarni BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS /* Debug Bus line name offsets */, 249*14b24e2bSVaishali Kulkarni BIN_BUF_DBG_PARSING_STRINGS /* Debug Tools parsing strings */, 250*14b24e2bSVaishali Kulkarni MAX_BIN_DBG_BUFFER_TYPE 251*14b24e2bSVaishali Kulkarni }; 252*14b24e2bSVaishali Kulkarni 253*14b24e2bSVaishali Kulkarni 254*14b24e2bSVaishali Kulkarni /* 255*14b24e2bSVaishali Kulkarni * Attention bit mapping 256*14b24e2bSVaishali Kulkarni */ 257*14b24e2bSVaishali Kulkarni struct dbg_attn_bit_mapping 258*14b24e2bSVaishali Kulkarni { 259*14b24e2bSVaishali Kulkarni __le16 data; 260*14b24e2bSVaishali Kulkarni #define DBG_ATTN_BIT_MAPPING_VAL_MASK 0x7FFF /* The index of an attention in the blocks attentions list (if is_unused_bit_cnt=0), or a number of consecutive unused attention bits (if is_unused_bit_cnt=1) */ 261*14b24e2bSVaishali Kulkarni #define DBG_ATTN_BIT_MAPPING_VAL_SHIFT 0 262*14b24e2bSVaishali Kulkarni #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK 0x1 /* if set, the val field indicates the number of consecutive unused attention bits */ 263*14b24e2bSVaishali Kulkarni #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT 15 264*14b24e2bSVaishali Kulkarni }; 265*14b24e2bSVaishali Kulkarni 266*14b24e2bSVaishali Kulkarni 267*14b24e2bSVaishali Kulkarni /* 268*14b24e2bSVaishali Kulkarni * Attention block per-type data 269*14b24e2bSVaishali Kulkarni */ 270*14b24e2bSVaishali Kulkarni struct dbg_attn_block_type_data 271*14b24e2bSVaishali Kulkarni { 272*14b24e2bSVaishali Kulkarni __le16 names_offset /* Offset of this block attention names in the debug attention name offsets array */; 273*14b24e2bSVaishali Kulkarni __le16 reserved1; 274*14b24e2bSVaishali Kulkarni u8 num_regs /* Number of attention registers in this block */; 275*14b24e2bSVaishali Kulkarni u8 reserved2; 276*14b24e2bSVaishali Kulkarni __le16 regs_offset /* Offset of this blocks attention registers in the attention registers array (in dbg_attn_reg units) */; 277*14b24e2bSVaishali Kulkarni }; 278*14b24e2bSVaishali Kulkarni 279*14b24e2bSVaishali Kulkarni /* 280*14b24e2bSVaishali Kulkarni * Block attentions 281*14b24e2bSVaishali Kulkarni */ 282*14b24e2bSVaishali Kulkarni struct dbg_attn_block 283*14b24e2bSVaishali Kulkarni { 284*14b24e2bSVaishali Kulkarni struct dbg_attn_block_type_data per_type_data[2] /* attention block per-type data. Count must match the number of elements in dbg_attn_type. */; 285*14b24e2bSVaishali Kulkarni }; 286*14b24e2bSVaishali Kulkarni 287*14b24e2bSVaishali Kulkarni 288*14b24e2bSVaishali Kulkarni /* 289*14b24e2bSVaishali Kulkarni * Attention register result 290*14b24e2bSVaishali Kulkarni */ 291*14b24e2bSVaishali Kulkarni struct dbg_attn_reg_result 292*14b24e2bSVaishali Kulkarni { 293*14b24e2bSVaishali Kulkarni __le32 data; 294*14b24e2bSVaishali Kulkarni #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK 0xFFFFFF /* STS attention register GRC address (in dwords) */ 295*14b24e2bSVaishali Kulkarni #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT 0 296*14b24e2bSVaishali Kulkarni #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK 0xFF /* Number of attention indexes in this register */ 297*14b24e2bSVaishali Kulkarni #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_SHIFT 24 298*14b24e2bSVaishali Kulkarni __le16 block_attn_offset /* The offset of this registers attentions within the blocks attentions list (a value in the range 0..number of block attentions-1) */; 299*14b24e2bSVaishali Kulkarni __le16 reserved; 300*14b24e2bSVaishali Kulkarni __le32 sts_val /* Value read from the STS attention register */; 301*14b24e2bSVaishali Kulkarni __le32 mask_val /* Value read from the MASK attention register */; 302*14b24e2bSVaishali Kulkarni }; 303*14b24e2bSVaishali Kulkarni 304*14b24e2bSVaishali Kulkarni /* 305*14b24e2bSVaishali Kulkarni * Attention block result 306*14b24e2bSVaishali Kulkarni */ 307*14b24e2bSVaishali Kulkarni struct dbg_attn_block_result 308*14b24e2bSVaishali Kulkarni { 309*14b24e2bSVaishali Kulkarni u8 block_id /* Registers block ID */; 310*14b24e2bSVaishali Kulkarni u8 data; 311*14b24e2bSVaishali Kulkarni #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK 0x3 /* Value from dbg_attn_type enum */ 312*14b24e2bSVaishali Kulkarni #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT 0 313*14b24e2bSVaishali Kulkarni #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK 0x3F /* Number of registers in the block in which at least one attention bit is set */ 314*14b24e2bSVaishali Kulkarni #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT 2 315*14b24e2bSVaishali Kulkarni __le16 names_offset /* Offset of this registers block attention names in the attention name offsets array */; 316*14b24e2bSVaishali Kulkarni struct dbg_attn_reg_result reg_results[15] /* result data for each register in the block in which at least one attention bit is set */; 317*14b24e2bSVaishali Kulkarni }; 318*14b24e2bSVaishali Kulkarni 319*14b24e2bSVaishali Kulkarni 320*14b24e2bSVaishali Kulkarni 321*14b24e2bSVaishali Kulkarni /* 322*14b24e2bSVaishali Kulkarni * mode header 323*14b24e2bSVaishali Kulkarni */ 324*14b24e2bSVaishali Kulkarni struct dbg_mode_hdr 325*14b24e2bSVaishali Kulkarni { 326*14b24e2bSVaishali Kulkarni __le16 data; 327*14b24e2bSVaishali Kulkarni #define DBG_MODE_HDR_EVAL_MODE_MASK 0x1 /* indicates if a mode expression should be evaluated (0/1) */ 328*14b24e2bSVaishali Kulkarni #define DBG_MODE_HDR_EVAL_MODE_SHIFT 0 329*14b24e2bSVaishali Kulkarni #define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK 0x7FFF /* offset (in bytes) in modes expression buffer. valid only if eval_mode is set. */ 330*14b24e2bSVaishali Kulkarni #define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT 1 331*14b24e2bSVaishali Kulkarni }; 332*14b24e2bSVaishali Kulkarni 333*14b24e2bSVaishali Kulkarni /* 334*14b24e2bSVaishali Kulkarni * Attention register 335*14b24e2bSVaishali Kulkarni */ 336*14b24e2bSVaishali Kulkarni struct dbg_attn_reg 337*14b24e2bSVaishali Kulkarni { 338*14b24e2bSVaishali Kulkarni struct dbg_mode_hdr mode /* Mode header */; 339*14b24e2bSVaishali Kulkarni __le16 block_attn_offset /* The offset of this registers attentions within the blocks attentions list (a value in the range 0..number of block attentions-1) */; 340*14b24e2bSVaishali Kulkarni __le32 data; 341*14b24e2bSVaishali Kulkarni #define DBG_ATTN_REG_STS_ADDRESS_MASK 0xFFFFFF /* STS attention register GRC address (in dwords) */ 342*14b24e2bSVaishali Kulkarni #define DBG_ATTN_REG_STS_ADDRESS_SHIFT 0 343*14b24e2bSVaishali Kulkarni #define DBG_ATTN_REG_NUM_REG_ATTN_MASK 0xFF /* Number of attention in this register */ 344*14b24e2bSVaishali Kulkarni #define DBG_ATTN_REG_NUM_REG_ATTN_SHIFT 24 345*14b24e2bSVaishali Kulkarni __le32 sts_clr_address /* STS_CLR attention register GRC address (in dwords) */; 346*14b24e2bSVaishali Kulkarni __le32 mask_address /* MASK attention register GRC address (in dwords) */; 347*14b24e2bSVaishali Kulkarni }; 348*14b24e2bSVaishali Kulkarni 349*14b24e2bSVaishali Kulkarni 350*14b24e2bSVaishali Kulkarni 351*14b24e2bSVaishali Kulkarni /* 352*14b24e2bSVaishali Kulkarni * attention types 353*14b24e2bSVaishali Kulkarni */ 354*14b24e2bSVaishali Kulkarni enum dbg_attn_type 355*14b24e2bSVaishali Kulkarni { 356*14b24e2bSVaishali Kulkarni ATTN_TYPE_INTERRUPT, 357*14b24e2bSVaishali Kulkarni ATTN_TYPE_PARITY, 358*14b24e2bSVaishali Kulkarni MAX_DBG_ATTN_TYPE 359*14b24e2bSVaishali Kulkarni }; 360*14b24e2bSVaishali Kulkarni 361*14b24e2bSVaishali Kulkarni 362*14b24e2bSVaishali Kulkarni /* 363*14b24e2bSVaishali Kulkarni * Debug Bus block data 364*14b24e2bSVaishali Kulkarni */ 365*14b24e2bSVaishali Kulkarni struct dbg_bus_block 366*14b24e2bSVaishali Kulkarni { 367*14b24e2bSVaishali Kulkarni u8 num_of_lines /* Number of debug lines in this block (excluding signature and latency events). */; 368*14b24e2bSVaishali Kulkarni u8 has_latency_events /* Indicates if this block has a latency events debug line (0/1). */; 369*14b24e2bSVaishali Kulkarni __le16 lines_offset /* Offset of this blocks lines in the Debug Bus lines array. */; 370*14b24e2bSVaishali Kulkarni }; 371*14b24e2bSVaishali Kulkarni 372*14b24e2bSVaishali Kulkarni 373*14b24e2bSVaishali Kulkarni /* 374*14b24e2bSVaishali Kulkarni * Debug Bus block user data 375*14b24e2bSVaishali Kulkarni */ 376*14b24e2bSVaishali Kulkarni struct dbg_bus_block_user_data 377*14b24e2bSVaishali Kulkarni { 378*14b24e2bSVaishali Kulkarni u8 num_of_lines /* Number of debug lines in this block (excluding signature and latency events). */; 379*14b24e2bSVaishali Kulkarni u8 has_latency_events /* Indicates if this block has a latency events debug line (0/1). */; 380*14b24e2bSVaishali Kulkarni __le16 names_offset /* Offset of this blocks lines in the debug bus line name offsets array. */; 381*14b24e2bSVaishali Kulkarni }; 382*14b24e2bSVaishali Kulkarni 383*14b24e2bSVaishali Kulkarni 384*14b24e2bSVaishali Kulkarni /* 385*14b24e2bSVaishali Kulkarni * Block Debug line data 386*14b24e2bSVaishali Kulkarni */ 387*14b24e2bSVaishali Kulkarni struct dbg_bus_line 388*14b24e2bSVaishali Kulkarni { 389*14b24e2bSVaishali Kulkarni u8 data; 390*14b24e2bSVaishali Kulkarni #define DBG_BUS_LINE_NUM_OF_GROUPS_MASK 0xF /* Number of groups in the line (0-3) */ 391*14b24e2bSVaishali Kulkarni #define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT 0 392*14b24e2bSVaishali Kulkarni #define DBG_BUS_LINE_IS_256B_MASK 0x1 /* Indicates if this is a 128b line (0) or a 256b line (1). */ 393*14b24e2bSVaishali Kulkarni #define DBG_BUS_LINE_IS_256B_SHIFT 4 394*14b24e2bSVaishali Kulkarni #define DBG_BUS_LINE_RESERVED_MASK 0x7 395*14b24e2bSVaishali Kulkarni #define DBG_BUS_LINE_RESERVED_SHIFT 5 396*14b24e2bSVaishali Kulkarni u8 group_sizes /* Four 2-bit values, indicating the size of each group minus 1 (i.e. value=0 means size=1, value=1 means size=2, etc), starting from lsb. The sizes are in dwords (if is_256b=0) or in qwords (if is_256b=1). */; 397*14b24e2bSVaishali Kulkarni }; 398*14b24e2bSVaishali Kulkarni 399*14b24e2bSVaishali Kulkarni 400*14b24e2bSVaishali Kulkarni /* 401*14b24e2bSVaishali Kulkarni * condition header for registers dump 402*14b24e2bSVaishali Kulkarni */ 403*14b24e2bSVaishali Kulkarni struct dbg_dump_cond_hdr 404*14b24e2bSVaishali Kulkarni { 405*14b24e2bSVaishali Kulkarni struct dbg_mode_hdr mode /* Mode header */; 406*14b24e2bSVaishali Kulkarni u8 block_id /* block ID */; 407*14b24e2bSVaishali Kulkarni u8 data_size /* size in dwords of the data following this header */; 408*14b24e2bSVaishali Kulkarni }; 409*14b24e2bSVaishali Kulkarni 410*14b24e2bSVaishali Kulkarni 411*14b24e2bSVaishali Kulkarni /* 412*14b24e2bSVaishali Kulkarni * memory data for registers dump 413*14b24e2bSVaishali Kulkarni */ 414*14b24e2bSVaishali Kulkarni struct dbg_dump_mem 415*14b24e2bSVaishali Kulkarni { 416*14b24e2bSVaishali Kulkarni __le32 dword0; 417*14b24e2bSVaishali Kulkarni #define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF /* register address (in dwords) */ 418*14b24e2bSVaishali Kulkarni #define DBG_DUMP_MEM_ADDRESS_SHIFT 0 419*14b24e2bSVaishali Kulkarni #define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF /* memory group ID */ 420*14b24e2bSVaishali Kulkarni #define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24 421*14b24e2bSVaishali Kulkarni __le32 dword1; 422*14b24e2bSVaishali Kulkarni #define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF /* register size (in dwords) */ 423*14b24e2bSVaishali Kulkarni #define DBG_DUMP_MEM_LENGTH_SHIFT 0 424*14b24e2bSVaishali Kulkarni #define DBG_DUMP_MEM_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 425*14b24e2bSVaishali Kulkarni #define DBG_DUMP_MEM_WIDE_BUS_SHIFT 24 426*14b24e2bSVaishali Kulkarni #define DBG_DUMP_MEM_RESERVED_MASK 0x7F 427*14b24e2bSVaishali Kulkarni #define DBG_DUMP_MEM_RESERVED_SHIFT 25 428*14b24e2bSVaishali Kulkarni }; 429*14b24e2bSVaishali Kulkarni 430*14b24e2bSVaishali Kulkarni 431*14b24e2bSVaishali Kulkarni /* 432*14b24e2bSVaishali Kulkarni * register data for registers dump 433*14b24e2bSVaishali Kulkarni */ 434*14b24e2bSVaishali Kulkarni struct dbg_dump_reg 435*14b24e2bSVaishali Kulkarni { 436*14b24e2bSVaishali Kulkarni __le32 data; 437*14b24e2bSVaishali Kulkarni #define DBG_DUMP_REG_ADDRESS_MASK 0x7FFFFF /* register address (in dwords) */ 438*14b24e2bSVaishali Kulkarni #define DBG_DUMP_REG_ADDRESS_SHIFT 0 439*14b24e2bSVaishali Kulkarni #define DBG_DUMP_REG_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 440*14b24e2bSVaishali Kulkarni #define DBG_DUMP_REG_WIDE_BUS_SHIFT 23 441*14b24e2bSVaishali Kulkarni #define DBG_DUMP_REG_LENGTH_MASK 0xFF /* register size (in dwords) */ 442*14b24e2bSVaishali Kulkarni #define DBG_DUMP_REG_LENGTH_SHIFT 24 443*14b24e2bSVaishali Kulkarni }; 444*14b24e2bSVaishali Kulkarni 445*14b24e2bSVaishali Kulkarni 446*14b24e2bSVaishali Kulkarni /* 447*14b24e2bSVaishali Kulkarni * split header for registers dump 448*14b24e2bSVaishali Kulkarni */ 449*14b24e2bSVaishali Kulkarni struct dbg_dump_split_hdr 450*14b24e2bSVaishali Kulkarni { 451*14b24e2bSVaishali Kulkarni __le32 hdr; 452*14b24e2bSVaishali Kulkarni #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF /* size in dwords of the data following this header */ 453*14b24e2bSVaishali Kulkarni #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0 454*14b24e2bSVaishali Kulkarni #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF /* split type ID */ 455*14b24e2bSVaishali Kulkarni #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24 456*14b24e2bSVaishali Kulkarni }; 457*14b24e2bSVaishali Kulkarni 458*14b24e2bSVaishali Kulkarni 459*14b24e2bSVaishali Kulkarni /* 460*14b24e2bSVaishali Kulkarni * condition header for idle check 461*14b24e2bSVaishali Kulkarni */ 462*14b24e2bSVaishali Kulkarni struct dbg_idle_chk_cond_hdr 463*14b24e2bSVaishali Kulkarni { 464*14b24e2bSVaishali Kulkarni struct dbg_mode_hdr mode /* Mode header */; 465*14b24e2bSVaishali Kulkarni __le16 data_size /* size in dwords of the data following this header */; 466*14b24e2bSVaishali Kulkarni }; 467*14b24e2bSVaishali Kulkarni 468*14b24e2bSVaishali Kulkarni 469*14b24e2bSVaishali Kulkarni /* 470*14b24e2bSVaishali Kulkarni * Idle Check condition register 471*14b24e2bSVaishali Kulkarni */ 472*14b24e2bSVaishali Kulkarni struct dbg_idle_chk_cond_reg 473*14b24e2bSVaishali Kulkarni { 474*14b24e2bSVaishali Kulkarni __le32 data; 475*14b24e2bSVaishali Kulkarni #define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0x7FFFFF /* Register GRC address (in dwords) */ 476*14b24e2bSVaishali Kulkarni #define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0 477*14b24e2bSVaishali Kulkarni #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 478*14b24e2bSVaishali Kulkarni #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT 23 479*14b24e2bSVaishali Kulkarni #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF /* value from block_id enum */ 480*14b24e2bSVaishali Kulkarni #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24 481*14b24e2bSVaishali Kulkarni __le16 num_entries /* number of registers entries to check */; 482*14b24e2bSVaishali Kulkarni u8 entry_size /* size of registers entry (in dwords) */; 483*14b24e2bSVaishali Kulkarni u8 start_entry /* index of the first entry to check */; 484*14b24e2bSVaishali Kulkarni }; 485*14b24e2bSVaishali Kulkarni 486*14b24e2bSVaishali Kulkarni 487*14b24e2bSVaishali Kulkarni /* 488*14b24e2bSVaishali Kulkarni * Idle Check info register 489*14b24e2bSVaishali Kulkarni */ 490*14b24e2bSVaishali Kulkarni struct dbg_idle_chk_info_reg 491*14b24e2bSVaishali Kulkarni { 492*14b24e2bSVaishali Kulkarni __le32 data; 493*14b24e2bSVaishali Kulkarni #define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0x7FFFFF /* Register GRC address (in dwords) */ 494*14b24e2bSVaishali Kulkarni #define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0 495*14b24e2bSVaishali Kulkarni #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 496*14b24e2bSVaishali Kulkarni #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT 23 497*14b24e2bSVaishali Kulkarni #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF /* value from block_id enum */ 498*14b24e2bSVaishali Kulkarni #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24 499*14b24e2bSVaishali Kulkarni __le16 size /* register size in dwords */; 500*14b24e2bSVaishali Kulkarni struct dbg_mode_hdr mode /* Mode header */; 501*14b24e2bSVaishali Kulkarni }; 502*14b24e2bSVaishali Kulkarni 503*14b24e2bSVaishali Kulkarni 504*14b24e2bSVaishali Kulkarni /* 505*14b24e2bSVaishali Kulkarni * Idle Check register 506*14b24e2bSVaishali Kulkarni */ 507*14b24e2bSVaishali Kulkarni union dbg_idle_chk_reg 508*14b24e2bSVaishali Kulkarni { 509*14b24e2bSVaishali Kulkarni struct dbg_idle_chk_cond_reg cond_reg /* condition register */; 510*14b24e2bSVaishali Kulkarni struct dbg_idle_chk_info_reg info_reg /* info register */; 511*14b24e2bSVaishali Kulkarni }; 512*14b24e2bSVaishali Kulkarni 513*14b24e2bSVaishali Kulkarni 514*14b24e2bSVaishali Kulkarni /* 515*14b24e2bSVaishali Kulkarni * Idle Check result header 516*14b24e2bSVaishali Kulkarni */ 517*14b24e2bSVaishali Kulkarni struct dbg_idle_chk_result_hdr 518*14b24e2bSVaishali Kulkarni { 519*14b24e2bSVaishali Kulkarni __le16 rule_id /* Failing rule index */; 520*14b24e2bSVaishali Kulkarni __le16 mem_entry_id /* Failing memory entry index */; 521*14b24e2bSVaishali Kulkarni u8 num_dumped_cond_regs /* number of dumped condition registers */; 522*14b24e2bSVaishali Kulkarni u8 num_dumped_info_regs /* number of dumped condition registers */; 523*14b24e2bSVaishali Kulkarni u8 severity /* from dbg_idle_chk_severity_types enum */; 524*14b24e2bSVaishali Kulkarni u8 reserved; 525*14b24e2bSVaishali Kulkarni }; 526*14b24e2bSVaishali Kulkarni 527*14b24e2bSVaishali Kulkarni 528*14b24e2bSVaishali Kulkarni /* 529*14b24e2bSVaishali Kulkarni * Idle Check result register header 530*14b24e2bSVaishali Kulkarni */ 531*14b24e2bSVaishali Kulkarni struct dbg_idle_chk_result_reg_hdr 532*14b24e2bSVaishali Kulkarni { 533*14b24e2bSVaishali Kulkarni u8 data; 534*14b24e2bSVaishali Kulkarni #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK 0x1 /* indicates if this register is a memory */ 535*14b24e2bSVaishali Kulkarni #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0 536*14b24e2bSVaishali Kulkarni #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK 0x7F /* register index within the failing rule */ 537*14b24e2bSVaishali Kulkarni #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1 538*14b24e2bSVaishali Kulkarni u8 start_entry /* index of the first checked entry */; 539*14b24e2bSVaishali Kulkarni __le16 size /* register size in dwords */; 540*14b24e2bSVaishali Kulkarni }; 541*14b24e2bSVaishali Kulkarni 542*14b24e2bSVaishali Kulkarni 543*14b24e2bSVaishali Kulkarni /* 544*14b24e2bSVaishali Kulkarni * Idle Check rule 545*14b24e2bSVaishali Kulkarni */ 546*14b24e2bSVaishali Kulkarni struct dbg_idle_chk_rule 547*14b24e2bSVaishali Kulkarni { 548*14b24e2bSVaishali Kulkarni __le16 rule_id /* Idle Check rule ID */; 549*14b24e2bSVaishali Kulkarni u8 severity /* value from dbg_idle_chk_severity_types enum */; 550*14b24e2bSVaishali Kulkarni u8 cond_id /* Condition ID */; 551*14b24e2bSVaishali Kulkarni u8 num_cond_regs /* number of condition registers */; 552*14b24e2bSVaishali Kulkarni u8 num_info_regs /* number of info registers */; 553*14b24e2bSVaishali Kulkarni u8 num_imms /* number of immediates in the condition */; 554*14b24e2bSVaishali Kulkarni u8 reserved1; 555*14b24e2bSVaishali Kulkarni __le16 reg_offset /* offset of this rules registers in the idle check register array (in dbg_idle_chk_reg units) */; 556*14b24e2bSVaishali Kulkarni __le16 imm_offset /* offset of this rules immediate values in the immediate values array (in dwords) */; 557*14b24e2bSVaishali Kulkarni }; 558*14b24e2bSVaishali Kulkarni 559*14b24e2bSVaishali Kulkarni 560*14b24e2bSVaishali Kulkarni /* 561*14b24e2bSVaishali Kulkarni * Idle Check rule parsing data 562*14b24e2bSVaishali Kulkarni */ 563*14b24e2bSVaishali Kulkarni struct dbg_idle_chk_rule_parsing_data 564*14b24e2bSVaishali Kulkarni { 565*14b24e2bSVaishali Kulkarni __le32 data; 566*14b24e2bSVaishali Kulkarni #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1 /* indicates if this register has a FW message */ 567*14b24e2bSVaishali Kulkarni #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0 568*14b24e2bSVaishali Kulkarni #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF /* Offset of this rules strings in the debug strings array (in bytes) */ 569*14b24e2bSVaishali Kulkarni #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1 570*14b24e2bSVaishali Kulkarni }; 571*14b24e2bSVaishali Kulkarni 572*14b24e2bSVaishali Kulkarni 573*14b24e2bSVaishali Kulkarni /* 574*14b24e2bSVaishali Kulkarni * idle check severity types 575*14b24e2bSVaishali Kulkarni */ 576*14b24e2bSVaishali Kulkarni enum dbg_idle_chk_severity_types 577*14b24e2bSVaishali Kulkarni { 578*14b24e2bSVaishali Kulkarni IDLE_CHK_SEVERITY_ERROR /* idle check failure should cause an error */, 579*14b24e2bSVaishali Kulkarni IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC /* idle check failure should cause an error only if theres no traffic */, 580*14b24e2bSVaishali Kulkarni IDLE_CHK_SEVERITY_WARNING /* idle check failure should cause a warning */, 581*14b24e2bSVaishali Kulkarni MAX_DBG_IDLE_CHK_SEVERITY_TYPES 582*14b24e2bSVaishali Kulkarni }; 583*14b24e2bSVaishali Kulkarni 584*14b24e2bSVaishali Kulkarni 585*14b24e2bSVaishali Kulkarni 586*14b24e2bSVaishali Kulkarni /* 587*14b24e2bSVaishali Kulkarni * Debug Bus block data 588*14b24e2bSVaishali Kulkarni */ 589*14b24e2bSVaishali Kulkarni struct dbg_bus_block_data 590*14b24e2bSVaishali Kulkarni { 591*14b24e2bSVaishali Kulkarni __le16 data; 592*14b24e2bSVaishali Kulkarni #define DBG_BUS_BLOCK_DATA_ENABLE_MASK_MASK 0xF /* 4-bit value: bit i set -> dword/qword i is enabled. */ 593*14b24e2bSVaishali Kulkarni #define DBG_BUS_BLOCK_DATA_ENABLE_MASK_SHIFT 0 594*14b24e2bSVaishali Kulkarni #define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_MASK 0xF /* Number of dwords/qwords to shift right the debug data (0-3) */ 595*14b24e2bSVaishali Kulkarni #define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_SHIFT 4 596*14b24e2bSVaishali Kulkarni #define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_MASK 0xF /* 4-bit value: bit i set -> dword/qword i is forced valid. */ 597*14b24e2bSVaishali Kulkarni #define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_SHIFT 8 598*14b24e2bSVaishali Kulkarni #define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_MASK 0xF /* 4-bit value: bit i set -> dword/qword i frame bit is forced. */ 599*14b24e2bSVaishali Kulkarni #define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_SHIFT 12 600*14b24e2bSVaishali Kulkarni u8 line_num /* Debug line number to select */; 601*14b24e2bSVaishali Kulkarni u8 hw_id /* HW ID associated with the block */; 602*14b24e2bSVaishali Kulkarni }; 603*14b24e2bSVaishali Kulkarni 604*14b24e2bSVaishali Kulkarni 605*14b24e2bSVaishali Kulkarni /* 606*14b24e2bSVaishali Kulkarni * Debug Bus Clients 607*14b24e2bSVaishali Kulkarni */ 608*14b24e2bSVaishali Kulkarni enum dbg_bus_clients 609*14b24e2bSVaishali Kulkarni { 610*14b24e2bSVaishali Kulkarni DBG_BUS_CLIENT_RBCN, 611*14b24e2bSVaishali Kulkarni DBG_BUS_CLIENT_RBCP, 612*14b24e2bSVaishali Kulkarni DBG_BUS_CLIENT_RBCR, 613*14b24e2bSVaishali Kulkarni DBG_BUS_CLIENT_RBCT, 614*14b24e2bSVaishali Kulkarni DBG_BUS_CLIENT_RBCU, 615*14b24e2bSVaishali Kulkarni DBG_BUS_CLIENT_RBCF, 616*14b24e2bSVaishali Kulkarni DBG_BUS_CLIENT_RBCX, 617*14b24e2bSVaishali Kulkarni DBG_BUS_CLIENT_RBCS, 618*14b24e2bSVaishali Kulkarni DBG_BUS_CLIENT_RBCH, 619*14b24e2bSVaishali Kulkarni DBG_BUS_CLIENT_RBCZ, 620*14b24e2bSVaishali Kulkarni DBG_BUS_CLIENT_OTHER_ENGINE, 621*14b24e2bSVaishali Kulkarni DBG_BUS_CLIENT_TIMESTAMP, 622*14b24e2bSVaishali Kulkarni DBG_BUS_CLIENT_CPU, 623*14b24e2bSVaishali Kulkarni DBG_BUS_CLIENT_RBCY, 624*14b24e2bSVaishali Kulkarni DBG_BUS_CLIENT_RBCQ, 625*14b24e2bSVaishali Kulkarni DBG_BUS_CLIENT_RBCM, 626*14b24e2bSVaishali Kulkarni DBG_BUS_CLIENT_RBCB, 627*14b24e2bSVaishali Kulkarni DBG_BUS_CLIENT_RBCW, 628*14b24e2bSVaishali Kulkarni DBG_BUS_CLIENT_RBCV, 629*14b24e2bSVaishali Kulkarni MAX_DBG_BUS_CLIENTS 630*14b24e2bSVaishali Kulkarni }; 631*14b24e2bSVaishali Kulkarni 632*14b24e2bSVaishali Kulkarni 633*14b24e2bSVaishali Kulkarni /* 634*14b24e2bSVaishali Kulkarni * Debug Bus constraint operation types 635*14b24e2bSVaishali Kulkarni */ 636*14b24e2bSVaishali Kulkarni enum dbg_bus_constraint_ops 637*14b24e2bSVaishali Kulkarni { 638*14b24e2bSVaishali Kulkarni DBG_BUS_CONSTRAINT_OP_EQ /* equal */, 639*14b24e2bSVaishali Kulkarni DBG_BUS_CONSTRAINT_OP_NE /* not equal */, 640*14b24e2bSVaishali Kulkarni DBG_BUS_CONSTRAINT_OP_LT /* less than */, 641*14b24e2bSVaishali Kulkarni DBG_BUS_CONSTRAINT_OP_LTC /* less than (cyclic) */, 642*14b24e2bSVaishali Kulkarni DBG_BUS_CONSTRAINT_OP_LE /* less than or equal */, 643*14b24e2bSVaishali Kulkarni DBG_BUS_CONSTRAINT_OP_LEC /* less than or equal (cyclic) */, 644*14b24e2bSVaishali Kulkarni DBG_BUS_CONSTRAINT_OP_GT /* greater than */, 645*14b24e2bSVaishali Kulkarni DBG_BUS_CONSTRAINT_OP_GTC /* greater than (cyclic) */, 646*14b24e2bSVaishali Kulkarni DBG_BUS_CONSTRAINT_OP_GE /* greater than or equal */, 647*14b24e2bSVaishali Kulkarni DBG_BUS_CONSTRAINT_OP_GEC /* greater than or equal (cyclic) */, 648*14b24e2bSVaishali Kulkarni MAX_DBG_BUS_CONSTRAINT_OPS 649*14b24e2bSVaishali Kulkarni }; 650*14b24e2bSVaishali Kulkarni 651*14b24e2bSVaishali Kulkarni 652*14b24e2bSVaishali Kulkarni /* 653*14b24e2bSVaishali Kulkarni * Debug Bus trigger state data 654*14b24e2bSVaishali Kulkarni */ 655*14b24e2bSVaishali Kulkarni struct dbg_bus_trigger_state_data 656*14b24e2bSVaishali Kulkarni { 657*14b24e2bSVaishali Kulkarni u8 data; 658*14b24e2bSVaishali Kulkarni #define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_MASK 0xF /* 4-bit value: bit i set -> dword i of the trigger state block (after right shift) is enabled. */ 659*14b24e2bSVaishali Kulkarni #define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_SHIFT 0 660*14b24e2bSVaishali Kulkarni #define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_MASK 0xF /* 4-bit value: bit i set -> dword i is compared by a constraint */ 661*14b24e2bSVaishali Kulkarni #define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_SHIFT 4 662*14b24e2bSVaishali Kulkarni }; 663*14b24e2bSVaishali Kulkarni 664*14b24e2bSVaishali Kulkarni /* 665*14b24e2bSVaishali Kulkarni * Debug Bus memory address 666*14b24e2bSVaishali Kulkarni */ 667*14b24e2bSVaishali Kulkarni struct dbg_bus_mem_addr 668*14b24e2bSVaishali Kulkarni { 669*14b24e2bSVaishali Kulkarni __le32 lo; 670*14b24e2bSVaishali Kulkarni __le32 hi; 671*14b24e2bSVaishali Kulkarni }; 672*14b24e2bSVaishali Kulkarni 673*14b24e2bSVaishali Kulkarni /* 674*14b24e2bSVaishali Kulkarni * Debug Bus PCI buffer data 675*14b24e2bSVaishali Kulkarni */ 676*14b24e2bSVaishali Kulkarni struct dbg_bus_pci_buf_data 677*14b24e2bSVaishali Kulkarni { 678*14b24e2bSVaishali Kulkarni struct dbg_bus_mem_addr phys_addr /* PCI buffer physical address */; 679*14b24e2bSVaishali Kulkarni struct dbg_bus_mem_addr virt_addr /* PCI buffer virtual address */; 680*14b24e2bSVaishali Kulkarni __le32 size /* PCI buffer size in bytes */; 681*14b24e2bSVaishali Kulkarni }; 682*14b24e2bSVaishali Kulkarni 683*14b24e2bSVaishali Kulkarni /* 684*14b24e2bSVaishali Kulkarni * Debug Bus Storm EID range filter params 685*14b24e2bSVaishali Kulkarni */ 686*14b24e2bSVaishali Kulkarni struct dbg_bus_storm_eid_range_params 687*14b24e2bSVaishali Kulkarni { 688*14b24e2bSVaishali Kulkarni u8 min /* Minimal event ID to filter on */; 689*14b24e2bSVaishali Kulkarni u8 max /* Maximal event ID to filter on */; 690*14b24e2bSVaishali Kulkarni }; 691*14b24e2bSVaishali Kulkarni 692*14b24e2bSVaishali Kulkarni /* 693*14b24e2bSVaishali Kulkarni * Debug Bus Storm EID mask filter params 694*14b24e2bSVaishali Kulkarni */ 695*14b24e2bSVaishali Kulkarni struct dbg_bus_storm_eid_mask_params 696*14b24e2bSVaishali Kulkarni { 697*14b24e2bSVaishali Kulkarni u8 val /* Event ID value */; 698*14b24e2bSVaishali Kulkarni u8 mask /* Event ID mask. 1s in the mask = dont care bits. */; 699*14b24e2bSVaishali Kulkarni }; 700*14b24e2bSVaishali Kulkarni 701*14b24e2bSVaishali Kulkarni /* 702*14b24e2bSVaishali Kulkarni * Debug Bus Storm EID filter params 703*14b24e2bSVaishali Kulkarni */ 704*14b24e2bSVaishali Kulkarni union dbg_bus_storm_eid_params 705*14b24e2bSVaishali Kulkarni { 706*14b24e2bSVaishali Kulkarni struct dbg_bus_storm_eid_range_params range /* EID range filter params */; 707*14b24e2bSVaishali Kulkarni struct dbg_bus_storm_eid_mask_params mask /* EID mask filter params */; 708*14b24e2bSVaishali Kulkarni }; 709*14b24e2bSVaishali Kulkarni 710*14b24e2bSVaishali Kulkarni /* 711*14b24e2bSVaishali Kulkarni * Debug Bus Storm data 712*14b24e2bSVaishali Kulkarni */ 713*14b24e2bSVaishali Kulkarni struct dbg_bus_storm_data 714*14b24e2bSVaishali Kulkarni { 715*14b24e2bSVaishali Kulkarni u8 enabled /* indicates if the Storm is enabled for recording */; 716*14b24e2bSVaishali Kulkarni u8 mode /* Storm debug mode, valid only if the Storm is enabled */; 717*14b24e2bSVaishali Kulkarni u8 hw_id /* HW ID associated with the Storm */; 718*14b24e2bSVaishali Kulkarni u8 eid_filter_en /* Indicates if EID filtering is performed (0/1) */; 719*14b24e2bSVaishali Kulkarni u8 eid_range_not_mask /* 1 = EID range filter, 0 = EID mask filter. Valid only if eid_filter_en is set, */; 720*14b24e2bSVaishali Kulkarni u8 cid_filter_en /* Indicates if CID filtering is performed (0/1) */; 721*14b24e2bSVaishali Kulkarni union dbg_bus_storm_eid_params eid_filter_params /* EID filter params to filter on. Valid only if eid_filter_en is set. */; 722*14b24e2bSVaishali Kulkarni __le32 cid /* CID to filter on. Valid only if cid_filter_en is set. */; 723*14b24e2bSVaishali Kulkarni }; 724*14b24e2bSVaishali Kulkarni 725*14b24e2bSVaishali Kulkarni /* 726*14b24e2bSVaishali Kulkarni * Debug Bus data 727*14b24e2bSVaishali Kulkarni */ 728*14b24e2bSVaishali Kulkarni struct dbg_bus_data 729*14b24e2bSVaishali Kulkarni { 730*14b24e2bSVaishali Kulkarni __le32 app_version /* The tools version number of the application */; 731*14b24e2bSVaishali Kulkarni u8 state /* The current debug bus state */; 732*14b24e2bSVaishali Kulkarni u8 hw_dwords /* HW dwords per cycle */; 733*14b24e2bSVaishali Kulkarni __le16 hw_id_mask /* The HW IDs of the recorded HW blocks, where bits i*3..i*3+2 contain the HW ID of dword/qword i */; 734*14b24e2bSVaishali Kulkarni u8 num_enabled_blocks /* Number of blocks enabled for recording */; 735*14b24e2bSVaishali Kulkarni u8 num_enabled_storms /* Number of Storms enabled for recording */; 736*14b24e2bSVaishali Kulkarni u8 target /* Output target */; 737*14b24e2bSVaishali Kulkarni u8 one_shot_en /* Indicates if one-shot mode is enabled (0/1) */; 738*14b24e2bSVaishali Kulkarni u8 grc_input_en /* Indicates if GRC recording is enabled (0/1) */; 739*14b24e2bSVaishali Kulkarni u8 timestamp_input_en /* Indicates if timestamp recording is enabled (0/1) */; 740*14b24e2bSVaishali Kulkarni u8 filter_en /* Indicates if the recording filter is enabled (0/1) */; 741*14b24e2bSVaishali Kulkarni u8 adding_filter /* If true, the next added constraint belong to the filter. Otherwise, it belongs to the last added trigger state. Valid only if either filter or triggers are enabled. */; 742*14b24e2bSVaishali Kulkarni u8 filter_pre_trigger /* Indicates if the recording filter should be applied before the trigger. Valid only if both filter and trigger are enabled (0/1) */; 743*14b24e2bSVaishali Kulkarni u8 filter_post_trigger /* Indicates if the recording filter should be applied after the trigger. Valid only if both filter and trigger are enabled (0/1) */; 744*14b24e2bSVaishali Kulkarni __le16 reserved; 745*14b24e2bSVaishali Kulkarni u8 trigger_en /* Indicates if the recording trigger is enabled (0/1) */; 746*14b24e2bSVaishali Kulkarni struct dbg_bus_trigger_state_data trigger_states[3] /* trigger states data */; 747*14b24e2bSVaishali Kulkarni u8 next_trigger_state /* ID of next trigger state to be added */; 748*14b24e2bSVaishali Kulkarni u8 next_constraint_id /* ID of next filter/trigger constraint to be added */; 749*14b24e2bSVaishali Kulkarni u8 unify_inputs /* If true, all inputs are associated with HW ID 0. Otherwise, each input is assigned a different HW ID (0/1) */; 750*14b24e2bSVaishali Kulkarni u8 rcv_from_other_engine /* Indicates if the other engine sends it NW recording to this engine (0/1) */; 751*14b24e2bSVaishali Kulkarni struct dbg_bus_pci_buf_data pci_buf /* Debug Bus PCI buffer data. Valid only when the target is DBG_BUS_TARGET_ID_PCI. */; 752*14b24e2bSVaishali Kulkarni struct dbg_bus_block_data blocks[88] /* Debug Bus data for each block */; 753*14b24e2bSVaishali Kulkarni struct dbg_bus_storm_data storms[6] /* Debug Bus data for each block */; 754*14b24e2bSVaishali Kulkarni }; 755*14b24e2bSVaishali Kulkarni 756*14b24e2bSVaishali Kulkarni 757*14b24e2bSVaishali Kulkarni /* 758*14b24e2bSVaishali Kulkarni * Debug bus filter types 759*14b24e2bSVaishali Kulkarni */ 760*14b24e2bSVaishali Kulkarni enum dbg_bus_filter_types 761*14b24e2bSVaishali Kulkarni { 762*14b24e2bSVaishali Kulkarni DBG_BUS_FILTER_TYPE_OFF /* filter always off */, 763*14b24e2bSVaishali Kulkarni DBG_BUS_FILTER_TYPE_PRE /* filter before trigger only */, 764*14b24e2bSVaishali Kulkarni DBG_BUS_FILTER_TYPE_POST /* filter after trigger only */, 765*14b24e2bSVaishali Kulkarni DBG_BUS_FILTER_TYPE_ON /* filter always on */, 766*14b24e2bSVaishali Kulkarni MAX_DBG_BUS_FILTER_TYPES 767*14b24e2bSVaishali Kulkarni }; 768*14b24e2bSVaishali Kulkarni 769*14b24e2bSVaishali Kulkarni 770*14b24e2bSVaishali Kulkarni /* 771*14b24e2bSVaishali Kulkarni * Debug bus frame modes 772*14b24e2bSVaishali Kulkarni */ 773*14b24e2bSVaishali Kulkarni enum dbg_bus_frame_modes 774*14b24e2bSVaishali Kulkarni { 775*14b24e2bSVaishali Kulkarni DBG_BUS_FRAME_MODE_0HW_4ST=0 /* 0 HW dwords, 4 Storm dwords */, 776*14b24e2bSVaishali Kulkarni DBG_BUS_FRAME_MODE_4HW_0ST=3 /* 4 HW dwords, 0 Storm dwords */, 777*14b24e2bSVaishali Kulkarni DBG_BUS_FRAME_MODE_8HW_0ST=4 /* 8 HW dwords, 0 Storm dwords */, 778*14b24e2bSVaishali Kulkarni MAX_DBG_BUS_FRAME_MODES 779*14b24e2bSVaishali Kulkarni }; 780*14b24e2bSVaishali Kulkarni 781*14b24e2bSVaishali Kulkarni 782*14b24e2bSVaishali Kulkarni 783*14b24e2bSVaishali Kulkarni /* 784*14b24e2bSVaishali Kulkarni * Debug bus other engine mode 785*14b24e2bSVaishali Kulkarni */ 786*14b24e2bSVaishali Kulkarni enum dbg_bus_other_engine_modes 787*14b24e2bSVaishali Kulkarni { 788*14b24e2bSVaishali Kulkarni DBG_BUS_OTHER_ENGINE_MODE_NONE, 789*14b24e2bSVaishali Kulkarni DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX, 790*14b24e2bSVaishali Kulkarni DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_RX, 791*14b24e2bSVaishali Kulkarni DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX, 792*14b24e2bSVaishali Kulkarni DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX, 793*14b24e2bSVaishali Kulkarni MAX_DBG_BUS_OTHER_ENGINE_MODES 794*14b24e2bSVaishali Kulkarni }; 795*14b24e2bSVaishali Kulkarni 796*14b24e2bSVaishali Kulkarni 797*14b24e2bSVaishali Kulkarni 798*14b24e2bSVaishali Kulkarni /* 799*14b24e2bSVaishali Kulkarni * Debug bus post-trigger recording types 800*14b24e2bSVaishali Kulkarni */ 801*14b24e2bSVaishali Kulkarni enum dbg_bus_post_trigger_types 802*14b24e2bSVaishali Kulkarni { 803*14b24e2bSVaishali Kulkarni DBG_BUS_POST_TRIGGER_RECORD /* start recording after trigger */, 804*14b24e2bSVaishali Kulkarni DBG_BUS_POST_TRIGGER_DROP /* drop data after trigger */, 805*14b24e2bSVaishali Kulkarni MAX_DBG_BUS_POST_TRIGGER_TYPES 806*14b24e2bSVaishali Kulkarni }; 807*14b24e2bSVaishali Kulkarni 808*14b24e2bSVaishali Kulkarni 809*14b24e2bSVaishali Kulkarni /* 810*14b24e2bSVaishali Kulkarni * Debug bus pre-trigger recording types 811*14b24e2bSVaishali Kulkarni */ 812*14b24e2bSVaishali Kulkarni enum dbg_bus_pre_trigger_types 813*14b24e2bSVaishali Kulkarni { 814*14b24e2bSVaishali Kulkarni DBG_BUS_PRE_TRIGGER_START_FROM_ZERO /* start recording from time 0 */, 815*14b24e2bSVaishali Kulkarni DBG_BUS_PRE_TRIGGER_NUM_CHUNKS /* start recording some chunks before trigger */, 816*14b24e2bSVaishali Kulkarni DBG_BUS_PRE_TRIGGER_DROP /* drop data before trigger */, 817*14b24e2bSVaishali Kulkarni MAX_DBG_BUS_PRE_TRIGGER_TYPES 818*14b24e2bSVaishali Kulkarni }; 819*14b24e2bSVaishali Kulkarni 820*14b24e2bSVaishali Kulkarni 821*14b24e2bSVaishali Kulkarni /* 822*14b24e2bSVaishali Kulkarni * Debug bus SEMI frame modes 823*14b24e2bSVaishali Kulkarni */ 824*14b24e2bSVaishali Kulkarni enum dbg_bus_semi_frame_modes 825*14b24e2bSVaishali Kulkarni { 826*14b24e2bSVaishali Kulkarni DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST=0 /* 0 slow dwords, 4 fast dwords */, 827*14b24e2bSVaishali Kulkarni DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST=3 /* 4 slow dwords, 0 fast dwords */, 828*14b24e2bSVaishali Kulkarni MAX_DBG_BUS_SEMI_FRAME_MODES 829*14b24e2bSVaishali Kulkarni }; 830*14b24e2bSVaishali Kulkarni 831*14b24e2bSVaishali Kulkarni 832*14b24e2bSVaishali Kulkarni /* 833*14b24e2bSVaishali Kulkarni * Debug bus states 834*14b24e2bSVaishali Kulkarni */ 835*14b24e2bSVaishali Kulkarni enum dbg_bus_states 836*14b24e2bSVaishali Kulkarni { 837*14b24e2bSVaishali Kulkarni DBG_BUS_STATE_IDLE /* debug bus idle state (not recording) */, 838*14b24e2bSVaishali Kulkarni DBG_BUS_STATE_READY /* debug bus is ready for configuration and recording */, 839*14b24e2bSVaishali Kulkarni DBG_BUS_STATE_RECORDING /* debug bus is currently recording */, 840*14b24e2bSVaishali Kulkarni DBG_BUS_STATE_STOPPED /* debug bus recording has stopped */, 841*14b24e2bSVaishali Kulkarni MAX_DBG_BUS_STATES 842*14b24e2bSVaishali Kulkarni }; 843*14b24e2bSVaishali Kulkarni 844*14b24e2bSVaishali Kulkarni 845*14b24e2bSVaishali Kulkarni 846*14b24e2bSVaishali Kulkarni 847*14b24e2bSVaishali Kulkarni 848*14b24e2bSVaishali Kulkarni 849*14b24e2bSVaishali Kulkarni /* 850*14b24e2bSVaishali Kulkarni * Debug Bus Storm modes 851*14b24e2bSVaishali Kulkarni */ 852*14b24e2bSVaishali Kulkarni enum dbg_bus_storm_modes 853*14b24e2bSVaishali Kulkarni { 854*14b24e2bSVaishali Kulkarni DBG_BUS_STORM_MODE_PRINTF /* store data (fast debug) */, 855*14b24e2bSVaishali Kulkarni DBG_BUS_STORM_MODE_PRAM_ADDR /* pram address (fast debug) */, 856*14b24e2bSVaishali Kulkarni DBG_BUS_STORM_MODE_DRA_RW /* DRA read/write data (fast debug) */, 857*14b24e2bSVaishali Kulkarni DBG_BUS_STORM_MODE_DRA_W /* DRA write data (fast debug) */, 858*14b24e2bSVaishali Kulkarni DBG_BUS_STORM_MODE_LD_ST_ADDR /* load/store address (fast debug) */, 859*14b24e2bSVaishali Kulkarni DBG_BUS_STORM_MODE_DRA_FSM /* DRA state machines (fast debug) */, 860*14b24e2bSVaishali Kulkarni DBG_BUS_STORM_MODE_RH /* recording handlers (fast debug) */, 861*14b24e2bSVaishali Kulkarni DBG_BUS_STORM_MODE_FOC /* FOC: FIN + DRA Rd (slow debug) */, 862*14b24e2bSVaishali Kulkarni DBG_BUS_STORM_MODE_EXT_STORE /* FOC: External Store (slow) */, 863*14b24e2bSVaishali Kulkarni MAX_DBG_BUS_STORM_MODES 864*14b24e2bSVaishali Kulkarni }; 865*14b24e2bSVaishali Kulkarni 866*14b24e2bSVaishali Kulkarni 867*14b24e2bSVaishali Kulkarni /* 868*14b24e2bSVaishali Kulkarni * Debug bus target IDs 869*14b24e2bSVaishali Kulkarni */ 870*14b24e2bSVaishali Kulkarni enum dbg_bus_targets 871*14b24e2bSVaishali Kulkarni { 872*14b24e2bSVaishali Kulkarni DBG_BUS_TARGET_ID_INT_BUF /* records debug bus to DBG block internal buffer */, 873*14b24e2bSVaishali Kulkarni DBG_BUS_TARGET_ID_NIG /* records debug bus to the NW */, 874*14b24e2bSVaishali Kulkarni DBG_BUS_TARGET_ID_PCI /* records debug bus to a PCI buffer */, 875*14b24e2bSVaishali Kulkarni MAX_DBG_BUS_TARGETS 876*14b24e2bSVaishali Kulkarni }; 877*14b24e2bSVaishali Kulkarni 878*14b24e2bSVaishali Kulkarni 879*14b24e2bSVaishali Kulkarni 880*14b24e2bSVaishali Kulkarni /* 881*14b24e2bSVaishali Kulkarni * GRC Dump data 882*14b24e2bSVaishali Kulkarni */ 883*14b24e2bSVaishali Kulkarni struct dbg_grc_data 884*14b24e2bSVaishali Kulkarni { 885*14b24e2bSVaishali Kulkarni u8 params_initialized /* Indicates if the GRC parameters were initialized */; 886*14b24e2bSVaishali Kulkarni u8 reserved1; 887*14b24e2bSVaishali Kulkarni __le16 reserved2; 888*14b24e2bSVaishali Kulkarni __le32 param_val[48] /* Value of each GRC parameter. Array size must match the enum dbg_grc_params. */; 889*14b24e2bSVaishali Kulkarni }; 890*14b24e2bSVaishali Kulkarni 891*14b24e2bSVaishali Kulkarni 892*14b24e2bSVaishali Kulkarni /* 893*14b24e2bSVaishali Kulkarni * Debug GRC params 894*14b24e2bSVaishali Kulkarni */ 895*14b24e2bSVaishali Kulkarni enum dbg_grc_params 896*14b24e2bSVaishali Kulkarni { 897*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_TSTORM /* dump Tstorm memories (0/1) */, 898*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_MSTORM /* dump Mstorm memories (0/1) */, 899*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_USTORM /* dump Ustorm memories (0/1) */, 900*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_XSTORM /* dump Xstorm memories (0/1) */, 901*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_YSTORM /* dump Ystorm memories (0/1) */, 902*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_PSTORM /* dump Pstorm memories (0/1) */, 903*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_REGS /* dump non-memory registers (0/1) */, 904*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_RAM /* dump Storm internal RAMs (0/1) */, 905*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_PBUF /* dump Storm passive buffer (0/1) */, 906*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_IOR /* dump Storm IORs (0/1) */, 907*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_VFC /* dump VFC memories (0/1) */, 908*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_CM_CTX /* dump CM contexts (0/1) */, 909*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_PXP /* dump PXP memories (0/1) */, 910*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_RSS /* dump RSS memories (0/1) */, 911*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_CAU /* dump CAU memories (0/1) */, 912*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_QM /* dump QM memories (0/1) */, 913*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_MCP /* dump MCP memories (0/1) */, 914*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_RESERVED /* reserved */, 915*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_CFC /* dump CFC memories (0/1) */, 916*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_IGU /* dump IGU memories (0/1) */, 917*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_BRB /* dump BRB memories (0/1) */, 918*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_BTB /* dump BTB memories (0/1) */, 919*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_BMB /* dump BMB memories (0/1) */, 920*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_NIG /* dump NIG memories (0/1) */, 921*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_MULD /* dump MULD memories (0/1) */, 922*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_PRS /* dump PRS memories (0/1) */, 923*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_DMAE /* dump PRS memories (0/1) */, 924*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_TM /* dump TM (timers) memories (0/1) */, 925*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_SDM /* dump SDM memories (0/1) */, 926*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_DIF /* dump DIF memories (0/1) */, 927*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_STATIC /* dump static debug data (0/1) */, 928*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_UNSTALL /* un-stall Storms after dump (0/1) */, 929*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_NUM_LCIDS /* number of LCIDs (0..320) */, 930*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_NUM_LTIDS /* number of LTIDs (0..320) */, 931*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_EXCLUDE_ALL /* preset: exclude all memories from dump (1 only) */, 932*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_CRASH /* preset: include memories for crash dump (1 only) */, 933*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_PARITY_SAFE /* perform dump only if MFW is responding (0/1) */, 934*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_CM /* dump CM memories (0/1) */, 935*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_DUMP_PHY /* dump PHY memories (0/1) */, 936*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_NO_MCP /* dont perform MCP commands (0/1) */, 937*14b24e2bSVaishali Kulkarni DBG_GRC_PARAM_NO_FW_VER /* dont read FW/MFW version (0/1) */, 938*14b24e2bSVaishali Kulkarni MAX_DBG_GRC_PARAMS 939*14b24e2bSVaishali Kulkarni }; 940*14b24e2bSVaishali Kulkarni 941*14b24e2bSVaishali Kulkarni 942*14b24e2bSVaishali Kulkarni /* 943*14b24e2bSVaishali Kulkarni * Debug reset registers 944*14b24e2bSVaishali Kulkarni */ 945*14b24e2bSVaishali Kulkarni enum dbg_reset_regs 946*14b24e2bSVaishali Kulkarni { 947*14b24e2bSVaishali Kulkarni DBG_RESET_REG_MISCS_PL_UA, 948*14b24e2bSVaishali Kulkarni DBG_RESET_REG_MISCS_PL_HV, 949*14b24e2bSVaishali Kulkarni DBG_RESET_REG_MISCS_PL_HV_2, 950*14b24e2bSVaishali Kulkarni DBG_RESET_REG_MISC_PL_UA, 951*14b24e2bSVaishali Kulkarni DBG_RESET_REG_MISC_PL_HV, 952*14b24e2bSVaishali Kulkarni DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 953*14b24e2bSVaishali Kulkarni DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 954*14b24e2bSVaishali Kulkarni DBG_RESET_REG_MISC_PL_PDA_VAUX, 955*14b24e2bSVaishali Kulkarni MAX_DBG_RESET_REGS 956*14b24e2bSVaishali Kulkarni }; 957*14b24e2bSVaishali Kulkarni 958*14b24e2bSVaishali Kulkarni 959*14b24e2bSVaishali Kulkarni /* 960*14b24e2bSVaishali Kulkarni * Debug status codes 961*14b24e2bSVaishali Kulkarni */ 962*14b24e2bSVaishali Kulkarni enum dbg_status 963*14b24e2bSVaishali Kulkarni { 964*14b24e2bSVaishali Kulkarni DBG_STATUS_OK, 965*14b24e2bSVaishali Kulkarni DBG_STATUS_APP_VERSION_NOT_SET, 966*14b24e2bSVaishali Kulkarni DBG_STATUS_UNSUPPORTED_APP_VERSION, 967*14b24e2bSVaishali Kulkarni DBG_STATUS_DBG_BLOCK_NOT_RESET, 968*14b24e2bSVaishali Kulkarni DBG_STATUS_INVALID_ARGS, 969*14b24e2bSVaishali Kulkarni DBG_STATUS_OUTPUT_ALREADY_SET, 970*14b24e2bSVaishali Kulkarni DBG_STATUS_INVALID_PCI_BUF_SIZE, 971*14b24e2bSVaishali Kulkarni DBG_STATUS_PCI_BUF_ALLOC_FAILED, 972*14b24e2bSVaishali Kulkarni DBG_STATUS_PCI_BUF_NOT_ALLOCATED, 973*14b24e2bSVaishali Kulkarni DBG_STATUS_TOO_MANY_INPUTS, 974*14b24e2bSVaishali Kulkarni DBG_STATUS_INPUT_OVERLAP, 975*14b24e2bSVaishali Kulkarni DBG_STATUS_HW_ONLY_RECORDING, 976*14b24e2bSVaishali Kulkarni DBG_STATUS_STORM_ALREADY_ENABLED, 977*14b24e2bSVaishali Kulkarni DBG_STATUS_STORM_NOT_ENABLED, 978*14b24e2bSVaishali Kulkarni DBG_STATUS_BLOCK_ALREADY_ENABLED, 979*14b24e2bSVaishali Kulkarni DBG_STATUS_BLOCK_NOT_ENABLED, 980*14b24e2bSVaishali Kulkarni DBG_STATUS_NO_INPUT_ENABLED, 981*14b24e2bSVaishali Kulkarni DBG_STATUS_NO_FILTER_TRIGGER_64B, 982*14b24e2bSVaishali Kulkarni DBG_STATUS_FILTER_ALREADY_ENABLED, 983*14b24e2bSVaishali Kulkarni DBG_STATUS_TRIGGER_ALREADY_ENABLED, 984*14b24e2bSVaishali Kulkarni DBG_STATUS_TRIGGER_NOT_ENABLED, 985*14b24e2bSVaishali Kulkarni DBG_STATUS_CANT_ADD_CONSTRAINT, 986*14b24e2bSVaishali Kulkarni DBG_STATUS_TOO_MANY_TRIGGER_STATES, 987*14b24e2bSVaishali Kulkarni DBG_STATUS_TOO_MANY_CONSTRAINTS, 988*14b24e2bSVaishali Kulkarni DBG_STATUS_RECORDING_NOT_STARTED, 989*14b24e2bSVaishali Kulkarni DBG_STATUS_DATA_DIDNT_TRIGGER, 990*14b24e2bSVaishali Kulkarni DBG_STATUS_NO_DATA_RECORDED, 991*14b24e2bSVaishali Kulkarni DBG_STATUS_DUMP_BUF_TOO_SMALL, 992*14b24e2bSVaishali Kulkarni DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED, 993*14b24e2bSVaishali Kulkarni DBG_STATUS_UNKNOWN_CHIP, 994*14b24e2bSVaishali Kulkarni DBG_STATUS_VIRT_MEM_ALLOC_FAILED, 995*14b24e2bSVaishali Kulkarni DBG_STATUS_BLOCK_IN_RESET, 996*14b24e2bSVaishali Kulkarni DBG_STATUS_INVALID_TRACE_SIGNATURE, 997*14b24e2bSVaishali Kulkarni DBG_STATUS_INVALID_NVRAM_BUNDLE, 998*14b24e2bSVaishali Kulkarni DBG_STATUS_NVRAM_GET_IMAGE_FAILED, 999*14b24e2bSVaishali Kulkarni DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE, 1000*14b24e2bSVaishali Kulkarni DBG_STATUS_NVRAM_READ_FAILED, 1001*14b24e2bSVaishali Kulkarni DBG_STATUS_IDLE_CHK_PARSE_FAILED, 1002*14b24e2bSVaishali Kulkarni DBG_STATUS_MCP_TRACE_BAD_DATA, 1003*14b24e2bSVaishali Kulkarni DBG_STATUS_MCP_TRACE_NO_META, 1004*14b24e2bSVaishali Kulkarni DBG_STATUS_MCP_COULD_NOT_HALT, 1005*14b24e2bSVaishali Kulkarni DBG_STATUS_MCP_COULD_NOT_RESUME, 1006*14b24e2bSVaishali Kulkarni DBG_STATUS_DMAE_FAILED, 1007*14b24e2bSVaishali Kulkarni DBG_STATUS_SEMI_FIFO_NOT_EMPTY, 1008*14b24e2bSVaishali Kulkarni DBG_STATUS_IGU_FIFO_BAD_DATA, 1009*14b24e2bSVaishali Kulkarni DBG_STATUS_MCP_COULD_NOT_MASK_PRTY, 1010*14b24e2bSVaishali Kulkarni DBG_STATUS_FW_ASSERTS_PARSE_FAILED, 1011*14b24e2bSVaishali Kulkarni DBG_STATUS_REG_FIFO_BAD_DATA, 1012*14b24e2bSVaishali Kulkarni DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA, 1013*14b24e2bSVaishali Kulkarni DBG_STATUS_DBG_ARRAY_NOT_SET, 1014*14b24e2bSVaishali Kulkarni DBG_STATUS_FILTER_BUG, 1015*14b24e2bSVaishali Kulkarni DBG_STATUS_NON_MATCHING_LINES, 1016*14b24e2bSVaishali Kulkarni DBG_STATUS_INVALID_TRIGGER_DWORD_OFFSET, 1017*14b24e2bSVaishali Kulkarni DBG_STATUS_DBG_BUS_IN_USE, 1018*14b24e2bSVaishali Kulkarni MAX_DBG_STATUS 1019*14b24e2bSVaishali Kulkarni }; 1020*14b24e2bSVaishali Kulkarni 1021*14b24e2bSVaishali Kulkarni 1022*14b24e2bSVaishali Kulkarni /* 1023*14b24e2bSVaishali Kulkarni * Debug Storms IDs 1024*14b24e2bSVaishali Kulkarni */ 1025*14b24e2bSVaishali Kulkarni enum dbg_storms 1026*14b24e2bSVaishali Kulkarni { 1027*14b24e2bSVaishali Kulkarni DBG_TSTORM_ID, 1028*14b24e2bSVaishali Kulkarni DBG_MSTORM_ID, 1029*14b24e2bSVaishali Kulkarni DBG_USTORM_ID, 1030*14b24e2bSVaishali Kulkarni DBG_XSTORM_ID, 1031*14b24e2bSVaishali Kulkarni DBG_YSTORM_ID, 1032*14b24e2bSVaishali Kulkarni DBG_PSTORM_ID, 1033*14b24e2bSVaishali Kulkarni MAX_DBG_STORMS 1034*14b24e2bSVaishali Kulkarni }; 1035*14b24e2bSVaishali Kulkarni 1036*14b24e2bSVaishali Kulkarni 1037*14b24e2bSVaishali Kulkarni /* 1038*14b24e2bSVaishali Kulkarni * Idle Check data 1039*14b24e2bSVaishali Kulkarni */ 1040*14b24e2bSVaishali Kulkarni struct idle_chk_data 1041*14b24e2bSVaishali Kulkarni { 1042*14b24e2bSVaishali Kulkarni __le32 buf_size /* Idle check buffer size in dwords */; 1043*14b24e2bSVaishali Kulkarni u8 buf_size_set /* Indicates if the idle check buffer size was set (0/1) */; 1044*14b24e2bSVaishali Kulkarni u8 reserved1; 1045*14b24e2bSVaishali Kulkarni __le16 reserved2; 1046*14b24e2bSVaishali Kulkarni }; 1047*14b24e2bSVaishali Kulkarni 1048*14b24e2bSVaishali Kulkarni /* 1049*14b24e2bSVaishali Kulkarni * Debug Tools data (per HW function) 1050*14b24e2bSVaishali Kulkarni */ 1051*14b24e2bSVaishali Kulkarni struct dbg_tools_data 1052*14b24e2bSVaishali Kulkarni { 1053*14b24e2bSVaishali Kulkarni struct dbg_grc_data grc /* GRC Dump data */; 1054*14b24e2bSVaishali Kulkarni struct dbg_bus_data bus /* Debug Bus data */; 1055*14b24e2bSVaishali Kulkarni struct idle_chk_data idle_chk /* Idle Check data */; 1056*14b24e2bSVaishali Kulkarni u8 mode_enable[40] /* Indicates if a mode is enabled (0/1) */; 1057*14b24e2bSVaishali Kulkarni u8 block_in_reset[88] /* Indicates if a block is in reset state (0/1) */; 1058*14b24e2bSVaishali Kulkarni u8 chip_id /* Chip ID (from enum chip_ids) */; 1059*14b24e2bSVaishali Kulkarni u8 platform_id /* Platform ID */; 1060*14b24e2bSVaishali Kulkarni u8 initialized /* Indicates if the data was initialized */; 1061*14b24e2bSVaishali Kulkarni u8 reserved; 1062*14b24e2bSVaishali Kulkarni }; 1063*14b24e2bSVaishali Kulkarni 1064*14b24e2bSVaishali Kulkarni 1065*14b24e2bSVaishali Kulkarni #endif /* __ECORE_HSI_DEBUG_TOOLS__ */ 1066