xref: /illumos-gate/usr/src/uts/common/io/pcic.c (revision ae5a8bed)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  * Copyright (c) 2016 by Delphix. All rights reserved.
26  */
27 
28 /*
29  * PCIC device/interrupt handler
30  *	The "pcic" driver handles the Intel 82365SL, Cirrus Logic
31  *	and Toshiba (and possibly other clones) PCMCIA adapter chip
32  *	sets.  It implements a subset of Socket Services as defined
33  *	in the Solaris PCMCIA design documents
34  */
35 
36 /*
37  * currently defined "properties"
38  *
39  * clock-frequency		bus clock frequency
40  * smi				system management interrupt override
41  * need-mult-irq		need status IRQ for each pair of sockets
42  * disable-audio		don't route audio signal to speaker
43  */
44 
45 
46 #include <sys/types.h>
47 #include <sys/inttypes.h>
48 #include <sys/param.h>
49 #include <sys/systm.h>
50 #include <sys/user.h>
51 #include <sys/buf.h>
52 #include <sys/file.h>
53 #include <sys/uio.h>
54 #include <sys/conf.h>
55 #include <sys/stat.h>
56 #include <sys/autoconf.h>
57 #include <sys/vtoc.h>
58 #include <sys/dkio.h>
59 #include <sys/ddi.h>
60 #include <sys/sunddi.h>
61 #include <sys/sunndi.h>
62 #include <sys/var.h>
63 #include <sys/callb.h>
64 #include <sys/open.h>
65 #include <sys/ddidmareq.h>
66 #include <sys/dma_engine.h>
67 #include <sys/kstat.h>
68 #include <sys/kmem.h>
69 #include <sys/modctl.h>
70 #include <sys/pci.h>
71 #include <sys/pci_impl.h>
72 
73 #include <sys/pctypes.h>
74 #include <sys/pcmcia.h>
75 #include <sys/sservice.h>
76 
77 #include <sys/note.h>
78 
79 #include <sys/pcic_reg.h>
80 #include <sys/pcic_var.h>
81 
82 #if defined(__x86)
83 #include <sys/pci_cfgspace.h>
84 #endif
85 
86 #if defined(__sparc)
87 #include <sys/pci/pci_nexus.h>
88 #endif
89 
90 #include <sys/hotplug/hpcsvc.h>
91 #include "cardbus/cardbus.h"
92 
93 #define	SOFTC_SIZE	(sizeof (anp_t))
94 
95 static int pcic_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **);
96 static int pcic_attach(dev_info_t *, ddi_attach_cmd_t);
97 static int pcic_detach(dev_info_t *, ddi_detach_cmd_t);
98 static int32_t pcic_quiesce(dev_info_t *);
99 static uint_t pcic_intr(caddr_t, caddr_t);
100 static int pcic_do_io_intr(pcicdev_t *, uint32_t);
101 static int pcic_probe(dev_info_t *);
102 
103 static int pcic_open(dev_t *, int, int, cred_t *);
104 static int pcic_close(dev_t, int, int, cred_t *);
105 static int pcic_ioctl(dev_t, int, intptr_t, int, cred_t *, int *);
106 
107 typedef struct pcm_regs pcm_regs_t;
108 
109 static void pcic_init_assigned(dev_info_t *);
110 static int pcic_apply_avail_ranges(dev_info_t *, pcm_regs_t *,
111 	pci_regspec_t *, int);
112 int pci_resource_setup_avail(dev_info_t *, pci_regspec_t *, int);
113 
114 /*
115  * On x86 platforms the ddi_iobp_alloc(9F) and ddi_mem_alloc(9F) calls
116  * are xlated into DMA ctlops. To make this nexus work on x86, we
117  * need to have the default ddi_dma_mctl ctlops in the bus_ops
118  * structure, just to pass the request to the parent. The correct
119  * ctlops should be ddi_no_dma_mctl because so far we don't do DMA.
120  */
121 static
122 struct bus_ops pcmciabus_ops = {
123 	BUSO_REV,
124 	pcmcia_bus_map,
125 	NULL,
126 	NULL,
127 	NULL,
128 	i_ddi_map_fault,
129 	ddi_no_dma_map,
130 	ddi_no_dma_allochdl,
131 	ddi_no_dma_freehdl,
132 	ddi_no_dma_bindhdl,
133 	ddi_no_dma_unbindhdl,
134 	ddi_no_dma_flush,
135 	ddi_no_dma_win,
136 	ddi_dma_mctl,
137 	pcmcia_ctlops,
138 	pcmcia_prop_op,
139 	NULL,				/* (*bus_get_eventcookie)();	*/
140 	NULL,				/* (*bus_add_eventcall)();	*/
141 	NULL,				/* (*bus_remove_eventcall)();	*/
142 	NULL,				/* (*bus_post_event)();		*/
143 	NULL,				/* (*bus_intr_ctl)();		*/
144 	NULL,				/* (*bus_config)();		*/
145 	NULL,				/* (*bus_unconfig)();		*/
146 	NULL,				/* (*bus_fm_init)();		*/
147 	NULL,				/* (*bus_fm_fini)();		*/
148 	NULL,				/* (*bus_enter)()		*/
149 	NULL,				/* (*bus_exit)()		*/
150 	NULL,				/* (*bus_power)()		*/
151 	pcmcia_intr_ops			/* (*bus_intr_op)();		*/
152 };
153 
154 static struct cb_ops pcic_cbops = {
155 	pcic_open,
156 	pcic_close,
157 	nodev,
158 	nodev,
159 	nodev,
160 	nodev,
161 	nodev,
162 	pcic_ioctl,
163 	nodev,
164 	nodev,
165 	nodev,
166 	nochpoll,
167 	ddi_prop_op,
168 	NULL,
169 #ifdef CARDBUS
170 	D_NEW | D_MP | D_HOTPLUG
171 #else
172 	D_NEW | D_MP
173 #endif
174 };
175 
176 static struct dev_ops pcic_devops = {
177 	DEVO_REV,
178 	0,
179 	pcic_getinfo,
180 	nulldev,
181 	pcic_probe,
182 	pcic_attach,
183 	pcic_detach,
184 	nulldev,
185 	&pcic_cbops,
186 	&pcmciabus_ops,
187 	NULL,
188 	pcic_quiesce,	/* devo_quiesce */
189 };
190 
191 void *pcic_soft_state_p = NULL;
192 static int pcic_maxinst = -1;
193 
194 int pcic_do_insertion = 1;
195 int pcic_do_removal = 1;
196 
197 struct irqmap {
198 	int irq;
199 	int count;
200 } pcic_irq_map[16];
201 
202 
203 int pcic_debug = 0x0;
204 static  void    pcic_err(dev_info_t *dip, int level, const char *fmt, ...);
205 extern void cardbus_dump_pci_config(dev_info_t *dip);
206 extern void cardbus_dump_socket(dev_info_t *dip);
207 extern int cardbus_validate_iline(dev_info_t *dip, ddi_acc_handle_t handle);
208 static void pcic_dump_debqueue(char *msg);
209 
210 #if defined(PCIC_DEBUG)
211 static void xxdmp_all_regs(pcicdev_t *, int, uint32_t);
212 
213 #define	pcic_mutex_enter(a)	\
214 	{ \
215 		pcic_err(NULL, 10, "Set lock at %d\n", __LINE__); \
216 		mutex_enter(a); \
217 	};
218 
219 #define	pcic_mutex_exit(a)	\
220 	{ \
221 		pcic_err(NULL, 10, "Clear lock at %d\n", __LINE__); \
222 		mutex_exit(a); \
223 	};
224 
225 #else
226 #define	pcic_mutex_enter(a)	mutex_enter(a)
227 #define	pcic_mutex_exit(a)	mutex_exit(a)
228 #endif
229 
230 #define	PCIC_VCC_3VLEVEL	1
231 #define	PCIC_VCC_5VLEVEL	2
232 #define	PCIC_VCC_12LEVEL	3
233 
234 /* bit patterns to select voltage levels */
235 int pcic_vpp_levels[13] = {
236 	0, 0, 0,
237 	1,	/* 3.3V */
238 	0,
239 	1,	/* 5V */
240 	0, 0, 0, 0, 0, 0,
241 	2	/* 12V */
242 };
243 
244 uint8_t pcic_cbv_levels[13] = {
245 	0, 0, 0,
246 	3,			/* 3.3V */
247 	0,
248 	2,			/* 5V */
249 	0, 0, 0, 0, 0, 0,
250 	1			/* 12V */
251 };
252 
253 struct power_entry pcic_power[4] = {
254 	{
255 		0, VCC|VPP1|VPP2
256 	},
257 	{
258 		33,		/* 3.3Volt */
259 		VCC|VPP1|VPP2
260 	},
261 	{
262 		5*10,		/* 5Volt */
263 		VCC|VPP1|VPP2	/* currently only know about this */
264 	},
265 	{
266 		12*10,		/* 12Volt */
267 		VPP1|VPP2
268 	}
269 };
270 
271 /*
272  * Base used to allocate ranges of PCI memory on x86 systems
273  * Each instance gets a chunk above the base that is used to map
274  * in the memory and I/O windows for that device.
275  * Pages below the base are also allocated for the EXCA registers,
276  * one per instance.
277  */
278 #define	PCIC_PCI_MEMCHUNK	0x1000000
279 
280 static int pcic_wait_insert_time = 5000000;	/* In micro-seconds */
281 static int pcic_debounce_time = 200000; /* In micro-seconds */
282 
283 struct debounce {
284 	pcic_socket_t *pcs;
285 	clock_t expire;
286 	struct debounce *next;
287 };
288 
289 static struct debounce *pcic_deb_queue = NULL;
290 static kmutex_t pcic_deb_mtx;
291 static kcondvar_t pcic_deb_cv;
292 static kthread_t *pcic_deb_threadid;
293 
294 static inthandler_t *pcic_handlers;
295 
296 static void pcic_setup_adapter(pcicdev_t *);
297 static int pcic_change(pcicdev_t *, int);
298 static int pcic_ll_reset(pcicdev_t *, int);
299 static void pcic_mswait(pcicdev_t *, int, int);
300 static boolean_t pcic_check_ready(pcicdev_t *, int);
301 static void pcic_set_cdtimers(pcicdev_t *, int, uint32_t, int);
302 static void pcic_ready_wait(pcicdev_t *, int);
303 extern int pcmcia_get_intr(dev_info_t *, int);
304 extern int pcmcia_return_intr(dev_info_t *, int);
305 extern void pcmcia_cb_suspended(int);
306 extern void pcmcia_cb_resumed(int);
307 
308 static int pcic_callback(dev_info_t *, int (*)(), int);
309 static int pcic_inquire_adapter(dev_info_t *, inquire_adapter_t *);
310 static int pcic_get_adapter(dev_info_t *, get_adapter_t *);
311 static int pcic_get_page(dev_info_t *, get_page_t *);
312 static int pcic_get_socket(dev_info_t *, get_socket_t *);
313 static int pcic_get_status(dev_info_t *, get_ss_status_t *);
314 static int pcic_get_window(dev_info_t *, get_window_t *);
315 static int pcic_inquire_socket(dev_info_t *, inquire_socket_t *);
316 static int pcic_inquire_window(dev_info_t *, inquire_window_t *);
317 static int pcic_reset_socket(dev_info_t *, int, int);
318 static int pcic_set_page(dev_info_t *, set_page_t *);
319 static int pcic_set_window(dev_info_t *, set_window_t *);
320 static int pcic_set_socket(dev_info_t *, set_socket_t *);
321 static int pcic_set_interrupt(dev_info_t *, set_irq_handler_t *);
322 static int pcic_clear_interrupt(dev_info_t *, clear_irq_handler_t *);
323 static void pcic_pm_detection(void *);
324 static void pcic_iomem_pci_ctl(ddi_acc_handle_t, uchar_t *, unsigned);
325 static int clext_reg_read(pcicdev_t *, int, uchar_t);
326 static void clext_reg_write(pcicdev_t *, int, uchar_t, uchar_t);
327 static int pcic_calc_speed(pcicdev_t *, uint32_t);
328 static int pcic_card_state(pcicdev_t *, pcic_socket_t *);
329 static int pcic_find_pci_type(pcicdev_t *);
330 static void pcic_82092_smiirq_ctl(pcicdev_t *, int, int, int);
331 static void pcic_handle_cd_change(pcicdev_t *, pcic_socket_t *, uint8_t);
332 static uint_t pcic_cd_softint(caddr_t, caddr_t);
333 static uint8_t pcic_getb(pcicdev_t *, int, int);
334 static void pcic_putb(pcicdev_t *, int, int, int8_t);
335 static int pcic_set_vcc_level(pcicdev_t *, set_socket_t *);
336 static uint_t pcic_softintr(caddr_t, caddr_t);
337 
338 static void pcic_debounce(pcic_socket_t *);
339 static void pcic_do_resume(pcicdev_t *);
340 static void *pcic_add_debqueue(pcic_socket_t *, int);
341 static void pcic_rm_debqueue(void *);
342 static void pcic_deb_thread();
343 
344 static boolean_t pcic_load_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp);
345 static void pcic_unload_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp);
346 static uint32_t pcic_getcb(pcicdev_t *pcic, int reg);
347 static void pcic_putcb(pcicdev_t *pcic, int reg, uint32_t value);
348 static void pcic_cb_enable_intr(dev_info_t *);
349 static void pcic_cb_disable_intr(dev_info_t *);
350 static void pcic_enable_io_intr(pcicdev_t *pcic, int socket, int irq);
351 static void pcic_disable_io_intr(pcicdev_t *pcic, int socket);
352 
353 static cb_nexus_cb_t pcic_cbnexus_ops = {
354 	pcic_cb_enable_intr,
355 	pcic_cb_disable_intr
356 };
357 
358 static int pcic_exca_powerctl(pcicdev_t *pcic, int socket, int powerlevel);
359 static int pcic_cbus_powerctl(pcicdev_t *pcic, int socket);
360 
361 #if defined(__sparc)
362 static int pcic_fault(enum pci_fault_ops op, void *arg);
363 #endif
364 
365 
366 /*
367  * pcmcia interface operations structure
368  * this is the private interface that is exported to the nexus
369  */
370 pcmcia_if_t pcic_if_ops = {
371 	PCIF_MAGIC,
372 	PCIF_VERSION,
373 	pcic_callback,
374 	pcic_get_adapter,
375 	pcic_get_page,
376 	pcic_get_socket,
377 	pcic_get_status,
378 	pcic_get_window,
379 	pcic_inquire_adapter,
380 	pcic_inquire_socket,
381 	pcic_inquire_window,
382 	pcic_reset_socket,
383 	pcic_set_page,
384 	pcic_set_window,
385 	pcic_set_socket,
386 	pcic_set_interrupt,
387 	pcic_clear_interrupt,
388 	NULL,
389 };
390 
391 /*
392  * chip type identification routines
393  * this list of functions is searched until one of them succeeds
394  * or all fail.  i82365SL is assumed if failed.
395  */
396 static int pcic_ci_cirrus(pcicdev_t *);
397 static int pcic_ci_vadem(pcicdev_t *);
398 static int pcic_ci_ricoh(pcicdev_t *);
399 
400 int (*pcic_ci_funcs[])(pcicdev_t *) = {
401 	pcic_ci_cirrus,
402 	pcic_ci_vadem,
403 	pcic_ci_ricoh,
404 	NULL
405 };
406 
407 static struct modldrv modldrv = {
408 	&mod_driverops,		/* Type of module. This one is a driver */
409 	"PCIC PCMCIA adapter driver",	/* Name of the module. */
410 	&pcic_devops,		/* driver ops */
411 };
412 
413 static struct modlinkage modlinkage = {
414 	MODREV_1, (void *)&modldrv, NULL
415 };
416 
417 int
_init()418 _init()
419 {
420 	int stat;
421 
422 	/* Allocate soft state */
423 	if ((stat = ddi_soft_state_init(&pcic_soft_state_p,
424 	    SOFTC_SIZE, 2)) != DDI_SUCCESS)
425 		return (stat);
426 
427 	if ((stat = mod_install(&modlinkage)) != 0)
428 		ddi_soft_state_fini(&pcic_soft_state_p);
429 
430 	return (stat);
431 }
432 
433 int
_fini()434 _fini()
435 {
436 	int stat = 0;
437 
438 	if ((stat = mod_remove(&modlinkage)) != 0)
439 		return (stat);
440 
441 	if (pcic_deb_threadid) {
442 		mutex_enter(&pcic_deb_mtx);
443 		pcic_deb_threadid = 0;
444 		while (!pcic_deb_threadid)
445 			cv_wait(&pcic_deb_cv, &pcic_deb_mtx);
446 		pcic_deb_threadid = 0;
447 		mutex_exit(&pcic_deb_mtx);
448 
449 		mutex_destroy(&pcic_deb_mtx);
450 		cv_destroy(&pcic_deb_cv);
451 	}
452 
453 	ddi_soft_state_fini(&pcic_soft_state_p);
454 
455 	return (stat);
456 }
457 
458 int
_info(struct modinfo * modinfop)459 _info(struct modinfo *modinfop)
460 {
461 	return (mod_info(&modlinkage, modinfop));
462 }
463 
464 /*
465  * pcic_getinfo()
466  *	provide instance/device information about driver
467  */
468 /*ARGSUSED*/
469 static int
pcic_getinfo(dev_info_t * dip,ddi_info_cmd_t cmd,void * arg,void ** result)470 pcic_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **result)
471 {
472 	anp_t *anp;
473 	int error = DDI_SUCCESS;
474 	minor_t minor;
475 
476 	switch (cmd) {
477 		case DDI_INFO_DEVT2DEVINFO:
478 		minor = getminor((dev_t)arg);
479 		minor &= 0x7f;
480 		if (!(anp = ddi_get_soft_state(pcic_soft_state_p, minor)))
481 			*result = NULL;
482 		else
483 			*result = anp->an_dip;
484 		break;
485 		case DDI_INFO_DEVT2INSTANCE:
486 		minor = getminor((dev_t)arg);
487 		minor &= 0x7f;
488 		*result = (void *)((long)minor);
489 		break;
490 		default:
491 		error = DDI_FAILURE;
492 		break;
493 	}
494 	return (error);
495 }
496 
497 static int
pcic_probe(dev_info_t * dip)498 pcic_probe(dev_info_t *dip)
499 {
500 	int value;
501 	ddi_device_acc_attr_t attr;
502 	ddi_acc_handle_t handle;
503 	uchar_t *index, *data;
504 
505 	if (ddi_dev_is_sid(dip) == DDI_SUCCESS)
506 		return (DDI_PROBE_DONTCARE);
507 
508 	/*
509 	 * find a PCIC device (any vendor)
510 	 * while there can be up to 4 such devices in
511 	 * a system, we currently only look for 1
512 	 * per probe.  There will be up to 2 chips per
513 	 * instance since they share I/O space
514 	 */
515 	attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
516 	attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC;
517 	attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
518 
519 	if (ddi_regs_map_setup(dip, PCIC_ISA_CONTROL_REG_NUM,
520 	    (caddr_t *)&index,
521 	    PCIC_ISA_CONTROL_REG_OFFSET,
522 	    PCIC_ISA_CONTROL_REG_LENGTH,
523 	    &attr, &handle) != DDI_SUCCESS)
524 		return (DDI_PROBE_FAILURE);
525 
526 	data = index + 1;
527 
528 #if defined(PCIC_DEBUG)
529 	if (pcic_debug)
530 		cmn_err(CE_CONT, "pcic_probe: entered\n");
531 	if (pcic_debug)
532 		cmn_err(CE_CONT, "\tindex=%p\n", (void *)index);
533 #endif
534 	ddi_put8(handle, index, PCIC_CHIP_REVISION);
535 	ddi_put8(handle, data, 0);
536 	value = ddi_get8(handle, data);
537 #if defined(PCIC_DEBUG)
538 	if (pcic_debug)
539 		cmn_err(CE_CONT, "\tchip revision register = %x\n", value);
540 #endif
541 	if ((value & PCIC_REV_MASK) >= PCIC_REV_LEVEL_LOW &&
542 	    (value & 0x30) == 0) {
543 		/*
544 		 * we probably have a PCIC chip in the system
545 		 * do a little more checking.  If we find one,
546 		 * reset everything in case of softboot
547 		 */
548 		ddi_put8(handle, index, PCIC_MAPPING_ENABLE);
549 		ddi_put8(handle, data, 0);
550 		value = ddi_get8(handle, data);
551 #if defined(PCIC_DEBUG)
552 		if (pcic_debug)
553 			cmn_err(CE_CONT, "\tzero test = %x\n", value);
554 #endif
555 		/* should read back as zero */
556 		if (value == 0) {
557 			/*
558 			 * we do have one and it is off the bus
559 			 */
560 #if defined(PCIC_DEBUG)
561 			if (pcic_debug)
562 				cmn_err(CE_CONT, "pcic_probe: success\n");
563 #endif
564 			ddi_regs_map_free(&handle);
565 			return (DDI_PROBE_SUCCESS);
566 		}
567 	}
568 #if defined(PCIC_DEBUG)
569 	if (pcic_debug)
570 		cmn_err(CE_CONT, "pcic_probe: failed\n");
571 #endif
572 	ddi_regs_map_free(&handle);
573 	return (DDI_PROBE_FAILURE);
574 }
575 
576 /*
577  * These are just defaults they can also be changed via a property in the
578  * conf file.
579  */
580 static int pci_config_reg_num = PCIC_PCI_CONFIG_REG_NUM;
581 static int pci_control_reg_num = PCIC_PCI_CONTROL_REG_NUM;
582 static int pcic_do_pcmcia_sr = 1;
583 static int pcic_use_cbpwrctl = PCF_CBPWRCTL;
584 
585 /*
586  * enable insertion/removal interrupt for 32bit cards
587  */
588 static int
cardbus_enable_cd_intr(dev_info_t * dip)589 cardbus_enable_cd_intr(dev_info_t *dip)
590 {
591 	ddi_acc_handle_t	iohandle;
592 	caddr_t	ioaddr;
593 	ddi_device_acc_attr_t attr;
594 	attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
595 	attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
596 	attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
597 	(void) ddi_regs_map_setup(dip, 1,
598 	    (caddr_t *)&ioaddr,
599 	    0,
600 	    4096,
601 	    &attr, &iohandle);
602 
603 	/* CSC Interrupt: Card detect interrupt on */
604 	ddi_put32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_MASK),
605 	    ddi_get32(iohandle,
606 	    (uint32_t *)(ioaddr+CB_STATUS_MASK)) | CB_SE_CCDMASK);
607 
608 	ddi_put32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_EVENT),
609 	    ddi_get32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_EVENT)));
610 
611 	ddi_regs_map_free(&iohandle);
612 	return (1);
613 }
614 
615 /*
616  * quiesce(9E) entry point.
617  *
618  * This function is called when the system is single-threaded at high
619  * PIL with preemption disabled. Therefore, this function must not be
620  * blocked.
621  *
622  * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
623  * DDI_FAILURE indicates an error condition and should almost never happen.
624  */
625 static int32_t
pcic_quiesce(dev_info_t * dip)626 pcic_quiesce(dev_info_t *dip)
627 {
628 	anp_t *anp = ddi_get_driver_private(dip);
629 	pcicdev_t *pcic = anp->an_private;
630 	int i;
631 
632 	for (i = 0; i < pcic->pc_numsockets; i++) {
633 		pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0);
634 		pcic_putb(pcic, i, PCIC_CARD_DETECT, 0);
635 		pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0);
636 		/* disable interrupts and put card into RESET */
637 		pcic_putb(pcic, i, PCIC_INTERRUPT, 0);
638 		/* poweroff socket */
639 		pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0);
640 		pcic_putcb(pcic, CB_CONTROL, 0);
641 	}
642 
643 	return (DDI_SUCCESS);
644 }
645 
646 /*
647  * pcic_attach()
648  *	attach the PCIC (Intel 82365SL/CirrusLogic/Toshiba) driver
649  *	to the system.  This is a child of "sysbus" since that is where
650  *	the hardware lives, but it provides services to the "pcmcia"
651  *	nexus driver.  It gives a pointer back via its private data
652  *	structure which contains both the dip and socket services entry
653  *	points
654  */
655 static int
pcic_attach(dev_info_t * dip,ddi_attach_cmd_t cmd)656 pcic_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
657 {
658 	anp_t *pcic_nexus;
659 	pcicdev_t *pcic;
660 	int irqlevel, value;
661 	int pci_cfrn, pci_ctrn;
662 	int i, j, smi, actual;
663 	char *typename;
664 	char bus_type[16] = "(unknown)";
665 	int len = sizeof (bus_type);
666 	ddi_device_acc_attr_t attr;
667 	anp_t *anp = ddi_get_driver_private(dip);
668 	uint_t	pri;
669 
670 #if defined(PCIC_DEBUG)
671 	if (pcic_debug) {
672 		cmn_err(CE_CONT, "pcic_attach: entered\n");
673 	}
674 #endif
675 	switch (cmd) {
676 	case DDI_ATTACH:
677 		break;
678 	case DDI_RESUME:
679 		pcic = anp->an_private;
680 		/*
681 		 * for now, this is a simulated resume.
682 		 * a real one may need different things.
683 		 */
684 		if (pcic != NULL && pcic->pc_flags & PCF_SUSPENDED) {
685 			mutex_enter(&pcic->pc_lock);
686 			/* should probe for new sockets showing up */
687 			pcic_setup_adapter(pcic);
688 			pcic->pc_flags &= ~PCF_SUSPENDED;
689 			mutex_exit(&pcic->pc_lock);
690 			(void) pcmcia_begin_resume(dip);
691 
692 			pcic_do_resume(pcic);
693 #ifdef CARDBUS
694 			cardbus_restore_children(ddi_get_child(dip));
695 #endif
696 
697 			/*
698 			 * for complete implementation need END_RESUME (later)
699 			 */
700 			return (DDI_SUCCESS);
701 
702 		}
703 		return (DDI_SUCCESS);
704 	default:
705 		return (DDI_FAILURE);
706 	}
707 
708 	/*
709 	 * Allocate soft state associated with this instance.
710 	 */
711 	if (ddi_soft_state_zalloc(pcic_soft_state_p,
712 	    ddi_get_instance(dip)) != DDI_SUCCESS) {
713 		cmn_err(CE_CONT, "pcic%d: Unable to alloc state\n",
714 		    ddi_get_instance(dip));
715 		return (DDI_FAILURE);
716 	}
717 
718 	pcic_nexus = ddi_get_soft_state(pcic_soft_state_p,
719 	    ddi_get_instance(dip));
720 
721 	pcic = kmem_zalloc(sizeof (pcicdev_t), KM_SLEEP);
722 
723 	pcic->dip = dip;
724 	pcic_nexus->an_dip = dip;
725 	pcic_nexus->an_if = &pcic_if_ops;
726 	pcic_nexus->an_private = pcic;
727 	pcic->pc_numpower = sizeof (pcic_power)/sizeof (pcic_power[0]);
728 	pcic->pc_power = pcic_power;
729 
730 	pci_ctrn = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP,
731 	    "pci-control-reg-number", pci_control_reg_num);
732 	pci_cfrn = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP,
733 	    "pci-config-reg-number", pci_config_reg_num);
734 
735 	ddi_set_driver_private(dip, pcic_nexus);
736 
737 	/*
738 	 * pcic->pc_irq is really the IPL level we want to run at
739 	 * set the default values here and override from intr spec
740 	 */
741 	pcic->pc_irq = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP,
742 	    "interrupt-priorities", -1);
743 
744 	if (pcic->pc_irq == -1) {
745 		int			actual;
746 		uint_t			pri;
747 		ddi_intr_handle_t	hdl;
748 
749 		/* see if intrspec tells us different */
750 		if (ddi_intr_alloc(dip, &hdl, DDI_INTR_TYPE_FIXED,
751 		    0, 1, &actual, DDI_INTR_ALLOC_NORMAL) == DDI_SUCCESS) {
752 			if (ddi_intr_get_pri(hdl, &pri) == DDI_SUCCESS)
753 				pcic->pc_irq = pri;
754 			else
755 				pcic->pc_irq = LOCK_LEVEL + 1;
756 			(void) ddi_intr_free(hdl);
757 		}
758 	}
759 	pcic_nexus->an_ipl = pcic->pc_irq;
760 
761 	/*
762 	 * Check our parent bus type. We do different things based on which
763 	 * bus we're on.
764 	 */
765 	if (ddi_prop_op(DDI_DEV_T_ANY, ddi_get_parent(dip),
766 	    PROP_LEN_AND_VAL_BUF, DDI_PROP_CANSLEEP,
767 	    "device_type", (caddr_t)&bus_type[0], &len) !=
768 	    DDI_PROP_SUCCESS) {
769 		if (ddi_prop_op(DDI_DEV_T_ANY, ddi_get_parent(dip),
770 		    PROP_LEN_AND_VAL_BUF, DDI_PROP_CANSLEEP,
771 		    "bus-type", (caddr_t)&bus_type[0], &len) !=
772 		    DDI_PROP_SUCCESS) {
773 
774 			cmn_err(CE_CONT,
775 			    "pcic%d: can't find parent bus type\n",
776 			    ddi_get_instance(dip));
777 
778 			kmem_free(pcic, sizeof (pcicdev_t));
779 			ddi_soft_state_free(pcic_soft_state_p,
780 			    ddi_get_instance(dip));
781 			return (DDI_FAILURE);
782 		}
783 	} /* ddi_prop_op("device_type") */
784 
785 	if (strcmp(bus_type, DEVI_PCI_NEXNAME) == 0 ||
786 	    strcmp(bus_type, DEVI_PCIEX_NEXNAME) == 0) {
787 		pcic->pc_flags = PCF_PCIBUS;
788 	} else {
789 		cmn_err(CE_WARN, "!pcic%d: non-pci mode (%s) not supported, "
790 		    "set BIOS to yenta mode if applicable\n",
791 		    ddi_get_instance(dip), bus_type);
792 		kmem_free(pcic, sizeof (pcicdev_t));
793 		ddi_soft_state_free(pcic_soft_state_p,
794 		    ddi_get_instance(dip));
795 		return (DDI_FAILURE);
796 	}
797 
798 	if ((pcic->bus_speed = ddi_getprop(DDI_DEV_T_ANY, ddi_get_parent(dip),
799 	    DDI_PROP_CANSLEEP,
800 	    "clock-frequency", 0)) == 0) {
801 		if (pcic->pc_flags & PCF_PCIBUS)
802 			pcic->bus_speed = PCIC_PCI_DEF_SYSCLK;
803 		else
804 			pcic->bus_speed = PCIC_ISA_DEF_SYSCLK;
805 	} else {
806 		/*
807 		 * OBP can declare the speed in Hz...
808 		 */
809 		if (pcic->bus_speed > 1000000)
810 			pcic->bus_speed /= 1000000;
811 	} /* ddi_prop_op("clock-frequency") */
812 
813 	pcic->pc_io_type = PCIC_IO_TYPE_82365SL; /* default mode */
814 
815 #ifdef	PCIC_DEBUG
816 	if (pcic_debug) {
817 		cmn_err(CE_CONT,
818 		    "pcic%d: parent bus type = [%s], speed = %d MHz\n",
819 		    ddi_get_instance(dip),
820 		    bus_type, pcic->bus_speed);
821 	}
822 #endif
823 
824 	/*
825 	 * The reg properties on a PCI node are different than those
826 	 *	on a non-PCI node. Handle that difference here.
827 	 *	If it turns out to be a CardBus chip, we have even more
828 	 *	differences.
829 	 */
830 	if (pcic->pc_flags & PCF_PCIBUS) {
831 		int class_code;
832 #if defined(__x86)
833 		pcic->pc_base = 0x1000000;
834 		pcic->pc_bound = (uint32_t)~0;
835 		pcic->pc_iobase = 0x1000;
836 		pcic->pc_iobound = 0xefff;
837 #elif defined(__sparc)
838 		pcic->pc_base = 0x0;
839 		pcic->pc_bound = (uint32_t)~0;
840 		pcic->pc_iobase = 0x00000;
841 		pcic->pc_iobound = 0xffff;
842 #endif
843 
844 		/* usually need to get at config space so map first */
845 		attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
846 		attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
847 		attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
848 
849 		if (ddi_regs_map_setup(dip, pci_cfrn,
850 		    (caddr_t *)&pcic->cfgaddr,
851 		    PCIC_PCI_CONFIG_REG_OFFSET,
852 		    PCIC_PCI_CONFIG_REG_LENGTH,
853 		    &attr,
854 		    &pcic->cfg_handle) !=
855 		    DDI_SUCCESS) {
856 			cmn_err(CE_CONT,
857 			    "pcic%d: unable to map config space"
858 			    "regs\n",
859 			    ddi_get_instance(dip));
860 
861 			kmem_free(pcic, sizeof (pcicdev_t));
862 			return (DDI_FAILURE);
863 		} /* ddi_regs_map_setup */
864 
865 		class_code = ddi_getprop(DDI_DEV_T_ANY, dip,
866 		    DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS,
867 		    "class-code", -1);
868 #ifdef  PCIC_DEBUG
869 		if (pcic_debug) {
870 			cmn_err(CE_CONT, "pcic_attach class_code=%x\n",
871 			    class_code);
872 		}
873 #endif
874 
875 		switch (class_code) {
876 		case PCIC_PCI_CARDBUS:
877 			pcic->pc_flags |= PCF_CARDBUS;
878 			pcic->pc_io_type = PCIC_IO_TYPE_YENTA;
879 			/*
880 			 * Get access to the adapter registers on the
881 			 * PCI bus.  A 4K memory page
882 			 */
883 #if defined(PCIC_DEBUG)
884 			pcic_err(dip, 8, "Is Cardbus device\n");
885 			if (pcic_debug) {
886 				int nr;
887 				long rs;
888 				(void) ddi_dev_nregs(dip, &nr);
889 				pcic_err(dip, 9, "\tdev, cfgaddr 0x%p,"
890 				    "cfghndl 0x%p nregs %d",
891 				    (void *)pcic->cfgaddr,
892 				    (void *)pcic->cfg_handle, nr);
893 
894 				(void) ddi_dev_regsize(dip,
895 				    PCIC_PCI_CONTROL_REG_NUM, &rs);
896 
897 				pcic_err(dip, 9, "\tsize of reg %d is 0x%x\n",
898 				    PCIC_PCI_CONTROL_REG_NUM, (int)rs);
899 			}
900 #endif
901 			attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
902 			attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
903 			attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
904 
905 			if (ddi_regs_map_setup(dip, pci_ctrn,
906 			    (caddr_t *)&pcic->ioaddr,
907 			    PCIC_PCI_CONTROL_REG_OFFSET,
908 			    PCIC_CB_CONTROL_REG_LENGTH,
909 			    &attr, &pcic->handle) !=
910 			    DDI_SUCCESS) {
911 				cmn_err(CE_CONT,
912 				    "pcic%d: unable to map PCI regs\n",
913 				    ddi_get_instance(dip));
914 				ddi_regs_map_free(&pcic->cfg_handle);
915 				kmem_free(pcic, sizeof (pcicdev_t));
916 				return (DDI_FAILURE);
917 			} /* ddi_regs_map_setup */
918 
919 			/*
920 			 * Find out the chip type - If we're on a PCI bus,
921 			 *	the adapter has that information in the PCI
922 			 *	config space.
923 			 * Note that we call pcic_find_pci_type here since
924 			 *	it needs a valid mapped pcic->handle to
925 			 *	access some of the adapter registers in
926 			 *	some cases.
927 			 */
928 			if (pcic_find_pci_type(pcic) != DDI_SUCCESS) {
929 				ddi_regs_map_free(&pcic->handle);
930 				ddi_regs_map_free(&pcic->cfg_handle);
931 				kmem_free(pcic, sizeof (pcicdev_t));
932 				cmn_err(CE_WARN, "pcic: %s: unsupported "
933 				    "bridge\n", ddi_get_name_addr(dip));
934 				return (DDI_FAILURE);
935 			}
936 			break;
937 
938 		default:
939 		case PCIC_PCI_PCMCIA:
940 			/*
941 			 * Get access to the adapter IO registers on the
942 			 * PCI bus config space.
943 			 */
944 			attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
945 			attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
946 			attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
947 
948 			/*
949 			 * We need a default mapping to the adapter's IO
950 			 *	control register space. For most adapters
951 			 *	that are of class PCIC_PCI_PCMCIA (or of
952 			 *	a default class) the control registers
953 			 *	will be using the 82365-type control/data
954 			 *	format.
955 			 */
956 			if (ddi_regs_map_setup(dip, pci_ctrn,
957 			    (caddr_t *)&pcic->ioaddr,
958 			    PCIC_PCI_CONTROL_REG_OFFSET,
959 			    PCIC_PCI_CONTROL_REG_LENGTH,
960 			    &attr,
961 			    &pcic->handle) != DDI_SUCCESS) {
962 				cmn_err(CE_CONT,
963 				    "pcic%d: unable to map PCI regs\n",
964 				    ddi_get_instance(dip));
965 				ddi_regs_map_free(&pcic->cfg_handle);
966 				kmem_free(pcic, sizeof (pcicdev_t));
967 				return (DDI_FAILURE);
968 			} /* ddi_regs_map_setup */
969 
970 			/*
971 			 * Find out the chip type - If we're on a PCI bus,
972 			 *	the adapter has that information in the PCI
973 			 *	config space.
974 			 * Note that we call pcic_find_pci_type here since
975 			 *	it needs a valid mapped pcic->handle to
976 			 *	access some of the adapter registers in
977 			 *	some cases.
978 			 */
979 			if (pcic_find_pci_type(pcic) != DDI_SUCCESS) {
980 				ddi_regs_map_free(&pcic->handle);
981 				ddi_regs_map_free(&pcic->cfg_handle);
982 				kmem_free(pcic, sizeof (pcicdev_t));
983 				cmn_err(CE_WARN, "pcic: %s: unsupported "
984 				    "bridge\n",
985 				    ddi_get_name_addr(dip));
986 				return (DDI_FAILURE);
987 			}
988 
989 			/*
990 			 * Some PCI-PCMCIA(R2) adapters are Yenta-compliant
991 			 *	for extended registers even though they are
992 			 *	not CardBus adapters. For those adapters,
993 			 *	re-map pcic->handle to be large enough to
994 			 *	encompass the Yenta registers.
995 			 */
996 			switch (pcic->pc_type) {
997 				case PCIC_TI_PCI1031:
998 				ddi_regs_map_free(&pcic->handle);
999 
1000 				if (ddi_regs_map_setup(dip,
1001 				    PCIC_PCI_CONTROL_REG_NUM,
1002 				    (caddr_t *)&pcic->ioaddr,
1003 				    PCIC_PCI_CONTROL_REG_OFFSET,
1004 				    PCIC_CB_CONTROL_REG_LENGTH,
1005 				    &attr,
1006 				    &pcic->handle) != DDI_SUCCESS) {
1007 					cmn_err(CE_CONT,
1008 					    "pcic%d: unable to map "
1009 					"PCI regs\n",
1010 					    ddi_get_instance(dip));
1011 					ddi_regs_map_free(&pcic->cfg_handle);
1012 					kmem_free(pcic, sizeof (pcicdev_t));
1013 					return (DDI_FAILURE);
1014 				} /* ddi_regs_map_setup */
1015 				break;
1016 				default:
1017 				break;
1018 			} /* switch (pcic->pc_type) */
1019 			break;
1020 		} /* switch (class_code) */
1021 	} else {
1022 		/*
1023 		 * We're not on a PCI bus, so assume an ISA bus type
1024 		 * register property. Get access to the adapter IO
1025 		 * registers on a non-PCI bus.
1026 		 */
1027 		attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
1028 		attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC;
1029 		attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
1030 		pcic->mem_reg_num = PCIC_ISA_MEM_REG_NUM;
1031 		pcic->io_reg_num = PCIC_ISA_IO_REG_NUM;
1032 
1033 		if (ddi_regs_map_setup(dip, PCIC_ISA_CONTROL_REG_NUM,
1034 		    (caddr_t *)&pcic->ioaddr,
1035 		    PCIC_ISA_CONTROL_REG_OFFSET,
1036 		    PCIC_ISA_CONTROL_REG_LENGTH,
1037 		    &attr,
1038 		    &pcic->handle) != DDI_SUCCESS) {
1039 			cmn_err(CE_CONT,
1040 			    "pcic%d: unable to map ISA registers\n",
1041 			    ddi_get_instance(dip));
1042 
1043 			kmem_free(pcic, sizeof (pcicdev_t));
1044 			return (DDI_FAILURE);
1045 		} /* ddi_regs_map_setup */
1046 
1047 		/* ISA bus is limited to 24-bits, but not first 640K */
1048 		pcic->pc_base = 0xd0000;
1049 		pcic->pc_bound = (uint32_t)~0;
1050 		pcic->pc_iobase = 0x1000;
1051 		pcic->pc_iobound = 0xefff;
1052 	} /* !PCF_PCIBUS */
1053 
1054 #ifdef  PCIC_DEBUG
1055 	if (pcic_debug) {
1056 		cmn_err(CE_CONT, "pcic_attach pc_flags=%x pc_type=%x\n",
1057 		    pcic->pc_flags, pcic->pc_type);
1058 	}
1059 #endif
1060 
1061 	/*
1062 	 * Setup various adapter registers for the PCI case. For the
1063 	 * non-PCI case, find out the chip type.
1064 	 */
1065 	if (pcic->pc_flags & PCF_PCIBUS) {
1066 		int iline;
1067 #if defined(__sparc)
1068 		iline = 0;
1069 #else
1070 		iline = cardbus_validate_iline(dip, pcic->cfg_handle);
1071 #endif
1072 
1073 		/* set flags and socket counts based on chip type */
1074 		switch (pcic->pc_type) {
1075 			uint32_t cfg;
1076 		case PCIC_INTEL_i82092:
1077 			cfg = ddi_get8(pcic->cfg_handle,
1078 			    pcic->cfgaddr + PCIC_82092_PCICON);
1079 			/* we can only support 4 Socket version */
1080 			if (cfg & PCIC_82092_4_SOCKETS) {
1081 				pcic->pc_numsockets = 4;
1082 				pcic->pc_type = PCIC_INTEL_i82092;
1083 				if (iline != 0xFF)
1084 					pcic->pc_intr_mode =
1085 					    PCIC_INTR_MODE_PCI_1;
1086 				else
1087 					pcic->pc_intr_mode = PCIC_INTR_MODE_ISA;
1088 			} else {
1089 				cmn_err(CE_CONT,
1090 				    "pcic%d: Intel 82092 adapter "
1091 				    "in unsupported configuration: 0x%x",
1092 				    ddi_get_instance(pcic->dip), cfg);
1093 				pcic->pc_numsockets = 0;
1094 			} /* PCIC_82092_4_SOCKETS */
1095 			break;
1096 		case PCIC_CL_PD6730:
1097 		case PCIC_CL_PD6729:
1098 			pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1;
1099 			cfg = ddi_getprop(DDI_DEV_T_ANY, dip,
1100 			    DDI_PROP_CANSLEEP,
1101 			    "interrupts", 0);
1102 			/* if not interrupt pin then must use ISA style IRQs */
1103 			if (cfg == 0 || iline == 0xFF)
1104 				pcic->pc_intr_mode = PCIC_INTR_MODE_ISA;
1105 			else {
1106 				/*
1107 				 * we have the option to use PCI interrupts.
1108 				 * this might not be optimal but in some cases
1109 				 * is the only thing possible (sparc case).
1110 				 * we now deterine what is possible.
1111 				 */
1112 				pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1;
1113 			}
1114 			pcic->pc_numsockets = 2;
1115 			pcic->pc_flags |= PCF_IO_REMAP;
1116 			break;
1117 		case PCIC_TI_PCI1031:
1118 			/* this chip doesn't do CardBus but looks like one */
1119 			pcic->pc_flags &= ~PCF_CARDBUS;
1120 			/* FALLTHROUGH */
1121 		default:
1122 			pcic->pc_flags |= PCF_IO_REMAP;
1123 			/* FALLTHROUGH */
1124 			/* indicate feature even if not supported */
1125 			pcic->pc_flags |= PCF_DMA | PCF_ZV;
1126 			/* Not sure if these apply to all these chips */
1127 			pcic->pc_flags |= (PCF_VPPX|PCF_33VCAP);
1128 			pcic->pc_flags |= pcic_use_cbpwrctl;
1129 
1130 			pcic->pc_numsockets = 1; /* one per function */
1131 			if (iline != 0xFF) {
1132 				uint8_t cfg;
1133 				pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1;
1134 
1135 				cfg = ddi_get8(pcic->cfg_handle,
1136 				    (pcic->cfgaddr + PCIC_BRIDGE_CTL_REG));
1137 				cfg &= (~PCIC_FUN_INT_MOD_ISA);
1138 				ddi_put8(pcic->cfg_handle, (pcic->cfgaddr +
1139 				    PCIC_BRIDGE_CTL_REG), cfg);
1140 			}
1141 			else
1142 				pcic->pc_intr_mode = PCIC_INTR_MODE_ISA;
1143 			pcic->pc_io_type = PCIC_IOTYPE_YENTA;
1144 			break;
1145 		}
1146 	} else {
1147 		/*
1148 		 * We're not on a PCI bus so do some more
1149 		 *	checking for adapter type here.
1150 		 * For the non-PCI bus case:
1151 		 * It could be any one of a number of different chips
1152 		 * If we can't determine anything else, it is assumed
1153 		 * to be an Intel 82365SL.  The Cirrus Logic PD6710
1154 		 * has an extension register that provides unique
1155 		 * identification. Toshiba chip isn't detailed as yet.
1156 		 */
1157 
1158 		/* Init the CL id mode */
1159 		pcic_putb(pcic, 0, PCIC_CHIP_INFO, 0);
1160 		value = pcic_getb(pcic, 0, PCIC_CHIP_INFO);
1161 
1162 		/* default to Intel i82365SL and then refine */
1163 		pcic->pc_type = PCIC_I82365SL;
1164 		pcic->pc_chipname = PCIC_TYPE_I82365SL;
1165 		for (value = 0; pcic_ci_funcs[value] != NULL; value++) {
1166 			/* go until one succeeds or none left */
1167 			if (pcic_ci_funcs[value](pcic))
1168 				break;
1169 		}
1170 
1171 		/* any chip specific flags get set here */
1172 		switch (pcic->pc_type) {
1173 		case PCIC_CL_PD6722:
1174 			pcic->pc_flags |= PCF_DMA;
1175 		}
1176 
1177 		for (i = 0; i < PCIC_MAX_SOCKETS; i++) {
1178 			/*
1179 			 * look for total number of sockets.
1180 			 * basically check each possible socket for
1181 			 * presence like in probe
1182 			 */
1183 
1184 			/* turn all windows off */
1185 			pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0);
1186 			value = pcic_getb(pcic, i, PCIC_MAPPING_ENABLE);
1187 
1188 			/*
1189 			 * if a zero is read back, then this socket
1190 			 * might be present. It would be except for
1191 			 * some systems that map the secondary PCIC
1192 			 * chip space back to the first.
1193 			 */
1194 			if (value != 0) {
1195 				/* definitely not so skip */
1196 				/* note: this is for Compaq support */
1197 				continue;
1198 			}
1199 
1200 			/* further tests */
1201 			value = pcic_getb(pcic, i, PCIC_CHIP_REVISION) &
1202 			    PCIC_REV_MASK;
1203 			if (!(value >= PCIC_REV_LEVEL_LOW &&
1204 			    value <= PCIC_REV_LEVEL_HI))
1205 				break;
1206 
1207 			pcic_putb(pcic, i, PCIC_SYSMEM_0_STARTLOW, 0xaa);
1208 			pcic_putb(pcic, i, PCIC_SYSMEM_1_STARTLOW, 0x55);
1209 			value = pcic_getb(pcic, i, PCIC_SYSMEM_0_STARTLOW);
1210 
1211 			j = pcic_getb(pcic, i, PCIC_SYSMEM_1_STARTLOW);
1212 			if (value != 0xaa || j != 0x55)
1213 				break;
1214 
1215 			/*
1216 			 * at this point we know if we have hardware
1217 			 * of some type and not just the bus holding
1218 			 * a pattern for us. We still have to determine
1219 			 * the case where more than 2 sockets are
1220 			 * really the same due to peculiar mappings of
1221 			 * hardware.
1222 			 */
1223 			j = pcic->pc_numsockets++;
1224 			pcic->pc_sockets[j].pcs_flags = 0;
1225 			pcic->pc_sockets[j].pcs_io = pcic->ioaddr;
1226 			pcic->pc_sockets[j].pcs_socket = i;
1227 
1228 			/* put PC Card into RESET, just in case */
1229 			value = pcic_getb(pcic, i, PCIC_INTERRUPT);
1230 			pcic_putb(pcic, i, PCIC_INTERRUPT,
1231 			    value & ~PCIC_RESET);
1232 		}
1233 
1234 #if defined(PCIC_DEBUG)
1235 		if (pcic_debug)
1236 			cmn_err(CE_CONT, "num sockets = %d\n",
1237 			    pcic->pc_numsockets);
1238 #endif
1239 		if (pcic->pc_numsockets == 0) {
1240 			ddi_regs_map_free(&pcic->handle);
1241 			kmem_free(pcic, sizeof (pcicdev_t));
1242 			return (DDI_FAILURE);
1243 		}
1244 
1245 		/*
1246 		 * need to think this through again in light of
1247 		 * Compaq not following the model that all the
1248 		 * chip vendors recommend.  IBM 755 seems to be
1249 		 * afflicted as well.  Basically, if the vendor
1250 		 * wired things wrong, socket 0 responds for socket 2
1251 		 * accesses, etc.
1252 		 */
1253 		if (pcic->pc_numsockets > 2) {
1254 			int count = pcic->pc_numsockets / 4;
1255 			for (i = 0; i < count; i++) {
1256 				/* put pattern into socket 0 */
1257 				pcic_putb(pcic, i,
1258 				    PCIC_SYSMEM_0_STARTLOW, 0x11);
1259 
1260 				/* put pattern into socket 2 */
1261 				pcic_putb(pcic, i + 2,
1262 				    PCIC_SYSMEM_0_STARTLOW, 0x33);
1263 
1264 				/* read back socket 0 */
1265 				value = pcic_getb(pcic, i,
1266 				    PCIC_SYSMEM_0_STARTLOW);
1267 
1268 				/* read back chip 1 socket 0 */
1269 				j = pcic_getb(pcic, i + 2,
1270 				    PCIC_SYSMEM_0_STARTLOW);
1271 				if (j == value) {
1272 					pcic->pc_numsockets -= 2;
1273 				}
1274 			}
1275 		}
1276 
1277 		smi = 0xff;	/* no more override */
1278 
1279 		if (ddi_getprop(DDI_DEV_T_NONE, dip,
1280 		    DDI_PROP_DONTPASS, "need-mult-irq",
1281 		    0xffff) != 0xffff)
1282 			pcic->pc_flags |= PCF_MULT_IRQ;
1283 
1284 	} /* !PCF_PCIBUS */
1285 
1286 	/*
1287 	 * some platforms/busses need to have resources setup
1288 	 * this is temporary until a real resource allocator is
1289 	 * implemented.
1290 	 */
1291 
1292 	pcic_init_assigned(dip);
1293 
1294 	typename = pcic->pc_chipname;
1295 
1296 #ifdef	PCIC_DEBUG
1297 	if (pcic_debug) {
1298 		int nregs, nintrs;
1299 
1300 		if (ddi_dev_nregs(dip, &nregs) != DDI_SUCCESS)
1301 			nregs = 0;
1302 
1303 		if (ddi_dev_nintrs(dip, &nintrs) != DDI_SUCCESS)
1304 			nintrs = 0;
1305 
1306 		cmn_err(CE_CONT,
1307 		    "pcic%d: %d register sets, %d interrupts\n",
1308 		    ddi_get_instance(dip), nregs, nintrs);
1309 
1310 		nintrs = 0;
1311 		while (nregs--) {
1312 			off_t size;
1313 
1314 			if (ddi_dev_regsize(dip, nintrs, &size) ==
1315 			    DDI_SUCCESS) {
1316 				cmn_err(CE_CONT,
1317 				    "\tregnum %d size %ld (0x%lx)"
1318 				    "bytes",
1319 				    nintrs, size, size);
1320 				if (nintrs ==
1321 				    (pcic->pc_io_type == PCIC_IO_TYPE_82365SL ?
1322 				    PCIC_ISA_CONTROL_REG_NUM :
1323 				    PCIC_PCI_CONTROL_REG_NUM))
1324 					cmn_err(CE_CONT,
1325 					    " mapped at: 0x%p\n",
1326 					    (void *)pcic->ioaddr);
1327 				else
1328 					cmn_err(CE_CONT, "\n");
1329 			} else {
1330 				cmn_err(CE_CONT,
1331 				    "\tddi_dev_regsize(rnumber"
1332 				    "= %d) returns DDI_FAILURE\n",
1333 				    nintrs);
1334 			}
1335 			nintrs++;
1336 		} /* while */
1337 	} /* if (pcic_debug) */
1338 #endif
1339 
1340 	cv_init(&pcic->pm_cv, NULL, CV_DRIVER, NULL);
1341 
1342 	if (!ddi_getprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS,
1343 	    "disable-audio", 0))
1344 		pcic->pc_flags |= PCF_AUDIO;
1345 
1346 	if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP,
1347 	    "disable-cardbus", 0))
1348 		pcic->pc_flags &= ~PCF_CARDBUS;
1349 
1350 	(void) ddi_prop_update_string(DDI_DEV_T_NONE, dip, PCICPROP_CTL,
1351 	    typename);
1352 
1353 	/*
1354 	 * Init all socket SMI levels to 0 (no SMI)
1355 	 */
1356 	for (i = 0; i < PCIC_MAX_SOCKETS; i++) {
1357 		pcic->pc_sockets[i].pcs_smi = 0;
1358 		pcic->pc_sockets[i].pcs_debounce_id = 0;
1359 		pcic->pc_sockets[i].pcs_pcic = pcic;
1360 	}
1361 	pcic->pc_lastreg = -1; /* just to make sure we are in sync */
1362 
1363 	/*
1364 	 * Setup the IRQ handler(s)
1365 	 */
1366 	switch (pcic->pc_intr_mode) {
1367 		int xx;
1368 	case PCIC_INTR_MODE_ISA:
1369 	/*
1370 	 * On a non-PCI bus, we just use whatever SMI IRQ level was
1371 	 *	specified above, and the IO IRQ levels are allocated
1372 	 *	dynamically.
1373 	 */
1374 		for (xx = 15, smi = 0; xx >= 0; xx--) {
1375 			if (PCIC_IRQ(xx) &
1376 			    PCIC_AVAIL_IRQS) {
1377 				smi = pcmcia_get_intr(dip, xx);
1378 				if (smi >= 0)
1379 					break;
1380 			}
1381 		}
1382 #if defined(PCIC_DEBUG)
1383 		if (pcic_debug)
1384 			cmn_err(CE_NOTE, "\tselected IRQ %d as SMI\n", smi);
1385 #endif
1386 		/* init to same so share is easy */
1387 		for (i = 0; i < pcic->pc_numsockets; i++)
1388 			pcic->pc_sockets[i].pcs_smi = smi;
1389 		/* any special handling of IRQ levels */
1390 		if (pcic->pc_flags & PCF_MULT_IRQ) {
1391 			for (i = 2; i < pcic->pc_numsockets; i++) {
1392 				if ((i & 1) == 0) {
1393 					int xx;
1394 					for (xx = 15, smi = 0; xx >= 0; xx--) {
1395 						if (PCIC_IRQ(xx) &
1396 						    PCIC_AVAIL_IRQS) {
1397 							smi =
1398 							    pcmcia_get_intr(dip,
1399 							    xx);
1400 							if (smi >= 0)
1401 								break;
1402 						}
1403 					}
1404 				}
1405 				if (smi >= 0)
1406 					pcic->pc_sockets[i].pcs_smi = smi;
1407 			}
1408 		}
1409 		pcic->pc_intr_htblp = kmem_alloc(pcic->pc_numsockets *
1410 		    sizeof (ddi_intr_handle_t), KM_SLEEP);
1411 		for (i = 0, irqlevel = -1; i < pcic->pc_numsockets; i++) {
1412 			struct intrspec *ispecp;
1413 			struct ddi_parent_private_data *pdp;
1414 
1415 			if (irqlevel == pcic->pc_sockets[i].pcs_smi)
1416 				continue;
1417 			else {
1418 				irqlevel = pcic->pc_sockets[i].pcs_smi;
1419 			}
1420 			/*
1421 			 * now convert the allocated IRQ into an intrspec
1422 			 * and ask our parent to add it.  Don't use
1423 			 * the ddi_add_intr since we don't have a
1424 			 * default intrspec in all cases.
1425 			 *
1426 			 * note: this sort of violates DDI but we don't
1427 			 *	 get hardware intrspecs for many of the devices.
1428 			 *	 at the same time, we know how to allocate them
1429 			 *	 so we do the right thing.
1430 			 */
1431 			if (ddi_intr_alloc(dip, &pcic->pc_intr_htblp[i],
1432 			    DDI_INTR_TYPE_FIXED, 0, 1, &actual,
1433 			    DDI_INTR_ALLOC_NORMAL) != DDI_SUCCESS) {
1434 				cmn_err(CE_WARN, "%s: ddi_intr_alloc failed",
1435 				    ddi_get_name(dip));
1436 				goto isa_exit1;
1437 			}
1438 
1439 			/*
1440 			 * See earlier note:
1441 			 * Since some devices don't have 'intrspec'
1442 			 * we make one up in rootnex.
1443 			 *
1444 			 * However, it is not properly initialized as
1445 			 * the data it needs is present in this driver
1446 			 * and there is no interface to pass that up.
1447 			 * Specially 'irqlevel' is very important and
1448 			 * it is part of pcic struct.
1449 			 *
1450 			 * Set 'intrspec' up here; otherwise adding the
1451 			 * interrupt will fail.
1452 			 */
1453 			pdp = ddi_get_parent_data(dip);
1454 			ispecp = (struct intrspec *)&pdp->par_intr[0];
1455 			ispecp->intrspec_vec = irqlevel;
1456 			ispecp->intrspec_pri = pcic->pc_irq;
1457 
1458 			/* Stay compatible w/ PCMCIA */
1459 			pcic->pc_pri = (ddi_iblock_cookie_t)
1460 			    (uintptr_t)pcic->pc_irq;
1461 			pcic->pc_dcookie.idev_priority =
1462 			    (uintptr_t)pcic->pc_pri;
1463 			pcic->pc_dcookie.idev_vector = (ushort_t)irqlevel;
1464 
1465 			(void) ddi_intr_set_pri(pcic->pc_intr_htblp[i],
1466 			    pcic->pc_irq);
1467 
1468 			if (i == 0) {
1469 				mutex_init(&pcic->intr_lock, NULL, MUTEX_DRIVER,
1470 				    DDI_INTR_PRI(pcic->pc_irq));
1471 				mutex_init(&pcic->pc_lock, NULL, MUTEX_DRIVER,
1472 				    NULL);
1473 			}
1474 
1475 			if (ddi_intr_add_handler(pcic->pc_intr_htblp[i],
1476 			    pcic_intr, (caddr_t)pcic, NULL)) {
1477 				cmn_err(CE_WARN,
1478 				    "%s: ddi_intr_add_handler failed",
1479 				    ddi_get_name(dip));
1480 				goto isa_exit2;
1481 			}
1482 
1483 			if (ddi_intr_enable(pcic->pc_intr_htblp[i])) {
1484 				cmn_err(CE_WARN, "%s: ddi_intr_enable failed",
1485 				    ddi_get_name(dip));
1486 				for (j = i; j < 0; j--)
1487 					(void) ddi_intr_remove_handler(
1488 					    pcic->pc_intr_htblp[j]);
1489 				goto isa_exit2;
1490 			}
1491 		}
1492 		break;
1493 	case PCIC_INTR_MODE_PCI_1:
1494 	case PCIC_INTR_MODE_PCI:
1495 		/*
1496 		 * If we're on a PCI bus, we route all interrupts, both SMI
1497 		 * and IO interrupts, through a single interrupt line.
1498 		 * Assign the SMI IRQ level to the IO IRQ level here.
1499 		 */
1500 		pcic->pc_pci_intr_hdlp = kmem_alloc(sizeof (ddi_intr_handle_t),
1501 		    KM_SLEEP);
1502 		if (ddi_intr_alloc(dip, pcic->pc_pci_intr_hdlp,
1503 		    DDI_INTR_TYPE_FIXED, 0, 1, &actual,
1504 		    DDI_INTR_ALLOC_NORMAL) != DDI_SUCCESS)
1505 			goto pci_exit1;
1506 
1507 		if (ddi_intr_get_pri(pcic->pc_pci_intr_hdlp[0],
1508 		    &pri) != DDI_SUCCESS) {
1509 			(void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]);
1510 			goto pci_exit1;
1511 		}
1512 
1513 		pcic->pc_pri = (void *)(uintptr_t)pri;
1514 		mutex_init(&pcic->intr_lock, NULL, MUTEX_DRIVER, pcic->pc_pri);
1515 		mutex_init(&pcic->pc_lock, NULL, MUTEX_DRIVER, NULL);
1516 
1517 		if (ddi_intr_add_handler(pcic->pc_pci_intr_hdlp[0],
1518 		    pcic_intr, (caddr_t)pcic, NULL))
1519 			goto pci_exit2;
1520 
1521 		if (ddi_intr_enable(pcic->pc_pci_intr_hdlp[0])) {
1522 			(void) ddi_intr_remove_handler(
1523 			    pcic->pc_pci_intr_hdlp[0]);
1524 			goto pci_exit2;
1525 		}
1526 
1527 		/* Stay compatible w/ PCMCIA */
1528 		pcic->pc_dcookie.idev_priority = (ushort_t)pri;
1529 
1530 		/* init to same (PCI) so share is easy */
1531 		for (i = 0; i < pcic->pc_numsockets; i++)
1532 			pcic->pc_sockets[i].pcs_smi = 0xF; /* any valid */
1533 		break;
1534 	}
1535 
1536 	/*
1537 	 * Setup the adapter hardware to some reasonable defaults.
1538 	 */
1539 	mutex_enter(&pcic->pc_lock);
1540 	/* mark the driver state as attached */
1541 	pcic->pc_flags |= PCF_ATTACHED;
1542 	pcic_setup_adapter(pcic);
1543 
1544 	for (j = 0; j < pcic->pc_numsockets; j++)
1545 		if (ddi_intr_add_softint(dip,
1546 		    &pcic->pc_sockets[j].pcs_cd_softint_hdl,
1547 		    PCIC_SOFTINT_PRI_VAL, pcic_cd_softint,
1548 		    (caddr_t)&pcic->pc_sockets[j]) != DDI_SUCCESS)
1549 			goto pci_exit2;
1550 
1551 #if defined(PCIC_DEBUG)
1552 	if (pcic_debug)
1553 		cmn_err(CE_CONT, "type = %s sockets = %d\n", typename,
1554 		    pcic->pc_numsockets);
1555 #endif
1556 
1557 	pcic_nexus->an_iblock = &pcic->pc_pri;
1558 	pcic_nexus->an_idev = &pcic->pc_dcookie;
1559 
1560 	mutex_exit(&pcic->pc_lock);
1561 
1562 #ifdef CARDBUS
1563 	(void) cardbus_enable_cd_intr(dip);
1564 	if (pcic_debug) {
1565 
1566 		cardbus_dump_pci_config(dip);
1567 		cardbus_dump_socket(dip);
1568 	}
1569 
1570 	/*
1571 	 * Give the Cardbus misc module a chance to do it's per-adapter
1572 	 * instance setup. Note that there is no corresponding detach()
1573 	 * call.
1574 	 */
1575 	if (pcic->pc_flags & PCF_CARDBUS)
1576 		if (cardbus_attach(dip, &pcic_cbnexus_ops) != DDI_SUCCESS) {
1577 			cmn_err(CE_CONT,
1578 			    "pcic_attach: cardbus_attach failed\n");
1579 			goto pci_exit2;
1580 		}
1581 #endif
1582 
1583 	/*
1584 	 * Give the PCMCIA misc module a chance to do it's per-adapter
1585 	 *	instance setup.
1586 	 */
1587 	if ((i = pcmcia_attach(dip, pcic_nexus)) != DDI_SUCCESS)
1588 		goto pci_exit2;
1589 
1590 	if (pcic_maxinst == -1) {
1591 		/* This assumes that all instances run at the same IPL. */
1592 		mutex_init(&pcic_deb_mtx, NULL, MUTEX_DRIVER, NULL);
1593 		cv_init(&pcic_deb_cv, NULL, CV_DRIVER, NULL);
1594 		pcic_deb_threadid = thread_create((caddr_t)NULL, 0,
1595 		    pcic_deb_thread, (caddr_t)NULL, 0, &p0, TS_RUN,
1596 		    v.v_maxsyspri - 2);
1597 	}
1598 	pcic_maxinst = max(pcic_maxinst, ddi_get_instance(dip));
1599 	/*
1600 	 * Setup a debounce timeout to do an initial card detect
1601 	 * and enable interrupts.
1602 	 */
1603 	for (j = 0; j < pcic->pc_numsockets; j++) {
1604 		pcic->pc_sockets[j].pcs_debounce_id =
1605 		    pcic_add_debqueue(&pcic->pc_sockets[j],
1606 		    drv_usectohz(pcic_debounce_time));
1607 	}
1608 
1609 	return (i);
1610 
1611 isa_exit2:
1612 	mutex_destroy(&pcic->intr_lock);
1613 	mutex_destroy(&pcic->pc_lock);
1614 	for (j = i; j < 0; j--)
1615 		(void) ddi_intr_free(pcic->pc_intr_htblp[j]);
1616 isa_exit1:
1617 	(void) pcmcia_return_intr(dip, pcic->pc_sockets[i].pcs_smi);
1618 	ddi_regs_map_free(&pcic->handle);
1619 	if (pcic->pc_flags & PCF_PCIBUS)
1620 		ddi_regs_map_free(&pcic->cfg_handle);
1621 	kmem_free(pcic->pc_intr_htblp, pcic->pc_numsockets *
1622 	    sizeof (ddi_intr_handle_t));
1623 	kmem_free(pcic, sizeof (pcicdev_t));
1624 		return (DDI_FAILURE);
1625 
1626 pci_exit2:
1627 	mutex_destroy(&pcic->intr_lock);
1628 	mutex_destroy(&pcic->pc_lock);
1629 	(void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]);
1630 pci_exit1:
1631 	ddi_regs_map_free(&pcic->handle);
1632 	if (pcic->pc_flags & PCF_PCIBUS)
1633 		ddi_regs_map_free(&pcic->cfg_handle);
1634 	kmem_free(pcic->pc_pci_intr_hdlp, sizeof (ddi_intr_handle_t));
1635 	kmem_free(pcic, sizeof (pcicdev_t));
1636 	return (DDI_FAILURE);
1637 }
1638 
1639 /*
1640  * pcic_detach()
1641  *	request to detach from the system
1642  */
1643 static int
pcic_detach(dev_info_t * dip,ddi_detach_cmd_t cmd)1644 pcic_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
1645 {
1646 	anp_t *anp = ddi_get_driver_private(dip);
1647 	pcicdev_t *pcic = anp->an_private;
1648 	int i;
1649 
1650 	switch (cmd) {
1651 	case DDI_DETACH:
1652 		/* don't detach if the nexus still talks to us */
1653 		if (pcic->pc_callback != NULL)
1654 			return (DDI_FAILURE);
1655 
1656 		/* kill off the pm simulation */
1657 		if (pcic->pc_pmtimer)
1658 			(void) untimeout(pcic->pc_pmtimer);
1659 
1660 		/* turn everything off for all sockets and chips */
1661 		for (i = 0; i < pcic->pc_numsockets; i++) {
1662 			if (pcic->pc_sockets[i].pcs_debounce_id)
1663 				pcic_rm_debqueue(
1664 				    pcic->pc_sockets[i].pcs_debounce_id);
1665 			pcic->pc_sockets[i].pcs_debounce_id = 0;
1666 
1667 			pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0);
1668 			pcic_putb(pcic, i, PCIC_CARD_DETECT, 0);
1669 			pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0);
1670 			/* disable interrupts and put card into RESET */
1671 			pcic_putb(pcic, i, PCIC_INTERRUPT, 0);
1672 		}
1673 		(void) ddi_intr_disable(pcic->pc_pci_intr_hdlp[0]);
1674 		(void) ddi_intr_remove_handler(pcic->pc_pci_intr_hdlp[0]);
1675 		(void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]);
1676 		kmem_free(pcic->pc_pci_intr_hdlp, sizeof (ddi_intr_handle_t));
1677 		pcic->pc_flags = 0;
1678 		mutex_destroy(&pcic->pc_lock);
1679 		mutex_destroy(&pcic->intr_lock);
1680 		cv_destroy(&pcic->pm_cv);
1681 		if (pcic->pc_flags & PCF_PCIBUS)
1682 			ddi_regs_map_free(&pcic->cfg_handle);
1683 		if (pcic->handle)
1684 			ddi_regs_map_free(&pcic->handle);
1685 		kmem_free(pcic, sizeof (pcicdev_t));
1686 		ddi_soft_state_free(pcic_soft_state_p, ddi_get_instance(dip));
1687 		return (DDI_SUCCESS);
1688 
1689 	case DDI_SUSPEND:
1690 	case DDI_PM_SUSPEND:
1691 		/*
1692 		 * we got a suspend event (either real or imagined)
1693 		 * so notify the nexus proper that all existing cards
1694 		 * should go away.
1695 		 */
1696 		mutex_enter(&pcic->pc_lock);
1697 #ifdef CARDBUS
1698 		if (pcic->pc_flags & PCF_CARDBUS) {
1699 			for (i = 0; i < pcic->pc_numsockets; i++) {
1700 				if ((pcic->pc_sockets[i].pcs_flags &
1701 				    (PCS_CARD_PRESENT|PCS_CARD_ISCARDBUS)) ==
1702 				    (PCS_CARD_PRESENT|PCS_CARD_ISCARDBUS)) {
1703 
1704 					pcmcia_cb_suspended(
1705 					    pcic->pc_sockets[i].pcs_socket);
1706 				}
1707 			}
1708 
1709 			cardbus_save_children(ddi_get_child(dip));
1710 		}
1711 #endif
1712 		/* turn everything off for all sockets and chips */
1713 		for (i = 0; i < pcic->pc_numsockets; i++) {
1714 			if (pcic->pc_sockets[i].pcs_debounce_id)
1715 				pcic_rm_debqueue(
1716 				    pcic->pc_sockets[i].pcs_debounce_id);
1717 			pcic->pc_sockets[i].pcs_debounce_id = 0;
1718 
1719 			pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0);
1720 			pcic_putb(pcic, i, PCIC_CARD_DETECT, 0);
1721 			pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0);
1722 			/* disable interrupts and put card into RESET */
1723 			pcic_putb(pcic, i, PCIC_INTERRUPT, 0);
1724 			pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0);
1725 			if (pcic->pc_flags & PCF_CBPWRCTL)
1726 				pcic_putcb(pcic, CB_CONTROL, 0);
1727 
1728 			if (pcic->pc_sockets[i].pcs_flags & PCS_CARD_PRESENT) {
1729 				pcic->pc_sockets[i].pcs_flags = PCS_STARTING;
1730 				/*
1731 				 * Because we are half way through a save
1732 				 * all this does is schedule a removal event
1733 				 * to cs for when the system comes back.
1734 				 * This doesn't actually matter.
1735 				 */
1736 				if (!pcic_do_pcmcia_sr && pcic_do_removal &&
1737 				    pcic->pc_callback) {
1738 					PC_CALLBACK(pcic->dip, pcic->pc_cb_arg,
1739 					    PCE_CARD_REMOVAL,
1740 					    pcic->pc_sockets[i].pcs_socket);
1741 				}
1742 			}
1743 		}
1744 
1745 		pcic->pc_flags |= PCF_SUSPENDED;
1746 		mutex_exit(&pcic->pc_lock);
1747 
1748 		/*
1749 		 * when true power management exists, save the adapter
1750 		 * state here to enable a recovery.  For the emulation
1751 		 * condition, the state is gone
1752 		 */
1753 		return (DDI_SUCCESS);
1754 
1755 	default:
1756 		return (EINVAL);
1757 	}
1758 }
1759 
1760 static uint32_t pcic_tisysctl_onbits = ((1<<27) | (1<<15) | (1<<14));
1761 static uint32_t pcic_tisysctl_offbits = 0;
1762 static uint32_t pcic_default_latency = 0x40;
1763 
1764 static void
pcic_setup_adapter(pcicdev_t * pcic)1765 pcic_setup_adapter(pcicdev_t *pcic)
1766 {
1767 	int i;
1768 	int value, flags;
1769 
1770 #if defined(__x86)
1771 	pci_regspec_t *reg;
1772 	uchar_t bus, dev, func;
1773 	uint_t classcode;
1774 	int length;
1775 #endif
1776 
1777 	if (pcic->pc_flags & PCF_PCIBUS) {
1778 		/*
1779 		 * all PCI-to-PCMCIA bus bridges need memory and I/O enabled
1780 		 */
1781 		flags = (PCIC_ENABLE_IO | PCIC_ENABLE_MEM);
1782 		pcic_iomem_pci_ctl(pcic->cfg_handle, pcic->cfgaddr, flags);
1783 	}
1784 	/* enable each socket */
1785 	for (i = 0; i < pcic->pc_numsockets; i++) {
1786 		pcic->pc_sockets[i].pcs_flags = 0;
1787 		/* find out the socket capabilities (I/O vs memory) */
1788 		value = pcic_getb(pcic, i,
1789 		    PCIC_CHIP_REVISION) & PCIC_REV_ID_MASK;
1790 		if (value == PCIC_REV_ID_IO || value == PCIC_REV_ID_BOTH)
1791 			pcic->pc_sockets[i].pcs_flags |= PCS_SOCKET_IO;
1792 
1793 		/* disable all windows just in case */
1794 		pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0);
1795 
1796 		switch (pcic->pc_type) {
1797 			uint32_t cfg32;
1798 			uint16_t cfg16;
1799 			uint8_t cfg;
1800 
1801 		    /* enable extended registers for Vadem */
1802 			case PCIC_VADEM_VG469:
1803 			case PCIC_VADEM:
1804 
1805 			/* enable card status change interrupt for socket */
1806 			break;
1807 
1808 			case PCIC_I82365SL:
1809 			break;
1810 
1811 			case PCIC_CL_PD6710:
1812 			pcic_putb(pcic, 0, PCIC_MISC_CTL_2, PCIC_LED_ENABLE);
1813 			break;
1814 
1815 			/*
1816 			 * On the CL_6730, we need to set up the interrupt
1817 			 * signalling mode (PCI mode) and set the SMI and
1818 			 * IRQ interrupt lines to PCI/level-mode.
1819 			 */
1820 			case PCIC_CL_PD6730:
1821 			switch (pcic->pc_intr_mode) {
1822 			case PCIC_INTR_MODE_PCI_1:
1823 				clext_reg_write(pcic, i, PCIC_CLEXT_MISC_CTL_3,
1824 				    ((clext_reg_read(pcic, i,
1825 				    PCIC_CLEXT_MISC_CTL_3) &
1826 				    ~PCIC_CLEXT_INT_PCI) |
1827 				    PCIC_CLEXT_INT_PCI));
1828 				clext_reg_write(pcic, i, PCIC_CLEXT_EXT_CTL_1,
1829 				    (PCIC_CLEXT_IRQ_LVL_MODE |
1830 				    PCIC_CLEXT_SMI_LVL_MODE));
1831 				cfg = PCIC_CL_LP_DYN_MODE;
1832 				pcic_putb(pcic, i, PCIC_MISC_CTL_2, cfg);
1833 				break;
1834 			case PCIC_INTR_MODE_ISA:
1835 				break;
1836 			}
1837 			break;
1838 			/*
1839 			 * On the CL_6729, we set the SMI and IRQ interrupt
1840 			 *	lines to PCI/level-mode. as well as program the
1841 			 *	correct clock speed divider bit.
1842 			 */
1843 			case PCIC_CL_PD6729:
1844 			switch (pcic->pc_intr_mode) {
1845 			case PCIC_INTR_MODE_PCI_1:
1846 				clext_reg_write(pcic, i, PCIC_CLEXT_EXT_CTL_1,
1847 				    (PCIC_CLEXT_IRQ_LVL_MODE |
1848 				    PCIC_CLEXT_SMI_LVL_MODE));
1849 
1850 				break;
1851 			case PCIC_INTR_MODE_ISA:
1852 				break;
1853 			}
1854 			if (pcic->bus_speed > PCIC_PCI_25MHZ && i == 0) {
1855 				cfg = 0;
1856 				cfg |= PCIC_CL_TIMER_CLK_DIV;
1857 				pcic_putb(pcic, i, PCIC_MISC_CTL_2, cfg);
1858 			}
1859 			break;
1860 			case PCIC_INTEL_i82092:
1861 			cfg = PCIC_82092_EN_TIMING;
1862 			if (pcic->bus_speed < PCIC_SYSCLK_33MHZ)
1863 				cfg |= PCIC_82092_PCICLK_25MHZ;
1864 			ddi_put8(pcic->cfg_handle, pcic->cfgaddr +
1865 			    PCIC_82092_PCICON, cfg);
1866 			break;
1867 			case PCIC_TI_PCI1130:
1868 			case PCIC_TI_PCI1131:
1869 			case PCIC_TI_PCI1250:
1870 			case PCIC_TI_PCI1031:
1871 			cfg = ddi_get8(pcic->cfg_handle,
1872 			    pcic->cfgaddr + PCIC_DEVCTL_REG);
1873 			cfg &= ~PCIC_DEVCTL_INTR_MASK;
1874 			switch (pcic->pc_intr_mode) {
1875 			case PCIC_INTR_MODE_ISA:
1876 				cfg |= PCIC_DEVCTL_INTR_ISA;
1877 				break;
1878 			}
1879 #ifdef PCIC_DEBUG
1880 			if (pcic_debug) {
1881 				cmn_err(CE_CONT, "pcic_setup_adapter: "
1882 				    "write reg 0x%x=%x \n",
1883 				    PCIC_DEVCTL_REG, cfg);
1884 			}
1885 #endif
1886 			ddi_put8(pcic->cfg_handle,
1887 			    pcic->cfgaddr + PCIC_DEVCTL_REG,
1888 			    cfg);
1889 
1890 			cfg = ddi_get8(pcic->cfg_handle,
1891 			    pcic->cfgaddr + PCIC_CRDCTL_REG);
1892 			cfg &= ~(PCIC_CRDCTL_PCIINTR|PCIC_CRDCTL_PCICSC|
1893 			    PCIC_CRDCTL_PCIFUNC);
1894 			switch (pcic->pc_intr_mode) {
1895 			case PCIC_INTR_MODE_PCI_1:
1896 				cfg |= PCIC_CRDCTL_PCIINTR |
1897 				    PCIC_CRDCTL_PCICSC |
1898 				    PCIC_CRDCTL_PCIFUNC;
1899 				pcic->pc_flags |= PCF_USE_SMI;
1900 				break;
1901 			}
1902 #ifdef PCIC_DEBUG
1903 			if (pcic_debug) {
1904 				cmn_err(CE_CONT, "pcic_setup_adapter: "
1905 				    " write reg 0x%x=%x \n",
1906 				    PCIC_CRDCTL_REG, cfg);
1907 			}
1908 #endif
1909 			ddi_put8(pcic->cfg_handle,
1910 			    pcic->cfgaddr + PCIC_CRDCTL_REG,
1911 			    cfg);
1912 			break;
1913 			case PCIC_TI_PCI1221:
1914 			case PCIC_TI_PCI1225:
1915 			cfg = ddi_get8(pcic->cfg_handle,
1916 			    pcic->cfgaddr + PCIC_DEVCTL_REG);
1917 			cfg |= (PCIC_DEVCTL_INTR_DFLT | PCIC_DEVCTL_3VCAPABLE);
1918 #ifdef PCIC_DEBUG
1919 			if (pcic_debug) {
1920 				cmn_err(CE_CONT, "pcic_setup_adapter: "
1921 				    " write reg 0x%x=%x \n",
1922 				    PCIC_DEVCTL_REG, cfg);
1923 			}
1924 #endif
1925 			ddi_put8(pcic->cfg_handle,
1926 			    pcic->cfgaddr + PCIC_DEVCTL_REG, cfg);
1927 
1928 			cfg = ddi_get8(pcic->cfg_handle,
1929 			    pcic->cfgaddr + PCIC_DIAG_REG);
1930 			if (pcic->pc_type == PCIC_TI_PCI1225) {
1931 				cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC);
1932 			} else {
1933 				cfg |= PCIC_DIAG_ASYNC;
1934 			}
1935 			pcic->pc_flags |= PCF_USE_SMI;
1936 #ifdef PCIC_DEBUG
1937 			if (pcic_debug) {
1938 				cmn_err(CE_CONT, "pcic_setup_adapter: "
1939 				    " write reg 0x%x=%x \n",
1940 				    PCIC_DIAG_REG, cfg);
1941 			}
1942 #endif
1943 			ddi_put8(pcic->cfg_handle,
1944 			    pcic->cfgaddr + PCIC_DIAG_REG, cfg);
1945 			break;
1946 			case PCIC_TI_PCI1520:
1947 			case PCIC_TI_PCI1510:
1948 			case PCIC_TI_VENDOR:
1949 			if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) {
1950 				/* functional intr routed by ExCA register */
1951 				cfg = ddi_get8(pcic->cfg_handle,
1952 				    pcic->cfgaddr + PCIC_BRIDGE_CTL_REG);
1953 				cfg |= PCIC_FUN_INT_MOD_ISA;
1954 				ddi_put8(pcic->cfg_handle,
1955 				    pcic->cfgaddr + PCIC_BRIDGE_CTL_REG,
1956 				    cfg);
1957 
1958 				/* IRQ serialized interrupts */
1959 				cfg = ddi_get8(pcic->cfg_handle,
1960 				    pcic->cfgaddr + PCIC_DEVCTL_REG);
1961 				cfg &= ~PCIC_DEVCTL_INTR_MASK;
1962 				cfg |= PCIC_DEVCTL_INTR_ISA;
1963 				ddi_put8(pcic->cfg_handle,
1964 				    pcic->cfgaddr + PCIC_DEVCTL_REG,
1965 				    cfg);
1966 				break;
1967 			}
1968 
1969 			/* CSC interrupt routed to PCI */
1970 			cfg = ddi_get8(pcic->cfg_handle,
1971 			    pcic->cfgaddr + PCIC_DIAG_REG);
1972 			cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC);
1973 			ddi_put8(pcic->cfg_handle,
1974 			    pcic->cfgaddr + PCIC_DIAG_REG, cfg);
1975 
1976 #if defined(__x86)
1977 			/*
1978 			 * Some TI chips have 2 cardbus slots(function0 and
1979 			 * function1), and others may have just 1 cardbus slot.
1980 			 * The interrupt routing register is shared between the
1981 			 * 2 functions and can only be accessed through
1982 			 * function0. Here we check the presence of the second
1983 			 * cardbus slot and do the right thing.
1984 			 */
1985 
1986 			if (ddi_getlongprop(DDI_DEV_T_ANY, pcic->dip,
1987 			    DDI_PROP_DONTPASS, "reg", (caddr_t)&reg,
1988 			    &length) != DDI_PROP_SUCCESS) {
1989 				cmn_err(CE_WARN,
1990 				    "pcic_setup_adapter(), failed to"
1991 				    " read reg property\n");
1992 				break;
1993 			}
1994 
1995 			bus = PCI_REG_BUS_G(reg->pci_phys_hi);
1996 			dev = PCI_REG_DEV_G(reg->pci_phys_hi);
1997 			func = PCI_REG_FUNC_G(reg->pci_phys_hi);
1998 			kmem_free((caddr_t)reg, length);
1999 
2000 			if (func != 0) {
2001 				break;
2002 			}
2003 
2004 			classcode = (*pci_getl_func)(bus, dev, 1,
2005 			    PCI_CONF_REVID);
2006 			classcode >>= 8;
2007 			if (classcode != 0x060700 &&
2008 			    classcode != 0x060500) {
2009 				break;
2010 			}
2011 
2012 			/* Parallel PCI interrupts only */
2013 			cfg = ddi_get8(pcic->cfg_handle,
2014 			    pcic->cfgaddr + PCIC_DEVCTL_REG);
2015 			cfg &= ~PCIC_DEVCTL_INTR_MASK;
2016 			ddi_put8(pcic->cfg_handle,
2017 			    pcic->cfgaddr + PCIC_DEVCTL_REG,
2018 			    cfg);
2019 
2020 			/* tie INTA and INTB together */
2021 			cfg = ddi_get8(pcic->cfg_handle,
2022 			    (pcic->cfgaddr + PCIC_SYSCTL_REG + 3));
2023 			cfg |= PCIC_SYSCTL_INTRTIE;
2024 			ddi_put8(pcic->cfg_handle, (pcic->cfgaddr +
2025 			    PCIC_SYSCTL_REG + 3), cfg);
2026 #endif
2027 
2028 			break;
2029 			case PCIC_TI_PCI1410:
2030 			cfg = ddi_get8(pcic->cfg_handle,
2031 			    pcic->cfgaddr + PCIC_DIAG_REG);
2032 			cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC);
2033 			ddi_put8(pcic->cfg_handle,
2034 			    pcic->cfgaddr + PCIC_DIAG_REG, cfg);
2035 			break;
2036 			case PCIC_TOSHIBA_TOPIC100:
2037 			case PCIC_TOSHIBA_TOPIC95:
2038 			case PCIC_TOSHIBA_VENDOR:
2039 			cfg = ddi_get8(pcic->cfg_handle, pcic->cfgaddr +
2040 			    PCIC_TOSHIBA_SLOT_CTL_REG);
2041 			cfg |= (PCIC_TOSHIBA_SCR_SLOTON |
2042 			    PCIC_TOSHIBA_SCR_SLOTEN);
2043 			cfg &= (~PCIC_TOSHIBA_SCR_PRT_MASK);
2044 			cfg |= PCIC_TOSHIBA_SCR_PRT_3E2;
2045 			ddi_put8(pcic->cfg_handle, pcic->cfgaddr +
2046 			    PCIC_TOSHIBA_SLOT_CTL_REG, cfg);
2047 			cfg = ddi_get8(pcic->cfg_handle, pcic->cfgaddr +
2048 			    PCIC_TOSHIBA_INTR_CTL_REG);
2049 			switch (pcic->pc_intr_mode) {
2050 			case PCIC_INTR_MODE_ISA:
2051 				cfg &= ~PCIC_TOSHIBA_ICR_SRC;
2052 				ddi_put8(pcic->cfg_handle,
2053 				    pcic->cfgaddr +
2054 				    PCIC_TOSHIBA_INTR_CTL_REG, cfg);
2055 
2056 				cfg = ddi_get8(pcic->cfg_handle,
2057 				    pcic->cfgaddr + PCIC_BRIDGE_CTL_REG);
2058 				cfg |= PCIC_FUN_INT_MOD_ISA;
2059 				ddi_put8(pcic->cfg_handle,
2060 				    pcic->cfgaddr + PCIC_BRIDGE_CTL_REG,
2061 				    cfg);
2062 				break;
2063 			case PCIC_INTR_MODE_PCI_1:
2064 				cfg |= PCIC_TOSHIBA_ICR_SRC;
2065 				cfg &= (~PCIC_TOSHIBA_ICR_PIN_MASK);
2066 				cfg |= PCIC_TOSHIBA_ICR_PIN_INTA;
2067 				ddi_put8(pcic->cfg_handle,
2068 				    pcic->cfgaddr +
2069 				    PCIC_TOSHIBA_INTR_CTL_REG, cfg);
2070 				break;
2071 			}
2072 			break;
2073 			case PCIC_O2MICRO_VENDOR:
2074 			cfg32 = ddi_get32(pcic->cfg_handle,
2075 			    (uint32_t *)(pcic->cfgaddr +
2076 			    PCIC_O2MICRO_MISC_CTL));
2077 			switch (pcic->pc_intr_mode) {
2078 			case PCIC_INTR_MODE_ISA:
2079 				cfg32 |= (PCIC_O2MICRO_ISA_LEGACY |
2080 				    PCIC_O2MICRO_INT_MOD_PCI);
2081 				ddi_put32(pcic->cfg_handle,
2082 				    (uint32_t *)(pcic->cfgaddr +
2083 				    PCIC_O2MICRO_MISC_CTL),
2084 				    cfg32);
2085 				cfg = ddi_get8(pcic->cfg_handle,
2086 				    pcic->cfgaddr + PCIC_BRIDGE_CTL_REG);
2087 				cfg |= PCIC_FUN_INT_MOD_ISA;
2088 				ddi_put8(pcic->cfg_handle,
2089 				    pcic->cfgaddr + PCIC_BRIDGE_CTL_REG,
2090 				    cfg);
2091 				break;
2092 			case PCIC_INTR_MODE_PCI_1:
2093 				cfg32 &= ~PCIC_O2MICRO_ISA_LEGACY;
2094 				cfg32 |= PCIC_O2MICRO_INT_MOD_PCI;
2095 				ddi_put32(pcic->cfg_handle,
2096 				    (uint32_t *)(pcic->cfgaddr +
2097 				    PCIC_O2MICRO_MISC_CTL),
2098 				    cfg32);
2099 				break;
2100 			}
2101 			break;
2102 			case PCIC_RICOH_VENDOR:
2103 			if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) {
2104 				cfg16 = ddi_get16(pcic->cfg_handle,
2105 				    (uint16_t *)(pcic->cfgaddr +
2106 				    PCIC_RICOH_MISC_CTL_2));
2107 				cfg16 |= (PCIC_RICOH_CSC_INT_MOD |
2108 				    PCIC_RICOH_FUN_INT_MOD);
2109 				ddi_put16(pcic->cfg_handle,
2110 				    (uint16_t *)(pcic->cfgaddr +
2111 				    PCIC_RICOH_MISC_CTL_2),
2112 				    cfg16);
2113 
2114 				cfg16 = ddi_get16(pcic->cfg_handle,
2115 				    (uint16_t *)(pcic->cfgaddr +
2116 				    PCIC_RICOH_MISC_CTL));
2117 				cfg16 |= PCIC_RICOH_SIRQ_EN;
2118 				ddi_put16(pcic->cfg_handle,
2119 				    (uint16_t *)(pcic->cfgaddr +
2120 				    PCIC_RICOH_MISC_CTL),
2121 				    cfg16);
2122 
2123 				cfg = ddi_get8(pcic->cfg_handle,
2124 				    pcic->cfgaddr + PCIC_BRIDGE_CTL_REG);
2125 				cfg |= PCIC_FUN_INT_MOD_ISA;
2126 				ddi_put8(pcic->cfg_handle,
2127 				    pcic->cfgaddr + PCIC_BRIDGE_CTL_REG,
2128 				    cfg);
2129 			}
2130 			break;
2131 			default:
2132 			break;
2133 		} /* switch */
2134 
2135 		/*
2136 		 * The default value in the EEPROM (loaded on reset) for
2137 		 * MFUNC0/MFUNC1 may be incorrect. Here we make sure that
2138 		 * MFUNC0 is connected to INTA, and MFUNC1 is connected to
2139 		 * INTB. This applies to all TI CardBus controllers.
2140 		 */
2141 		if ((pcic->pc_type >> 16) == PCIC_TI_VENDORID &&
2142 		    pcic->pc_intr_mode == PCIC_INTR_MODE_PCI_1) {
2143 			value = ddi_get32(pcic->cfg_handle,
2144 			    (uint32_t *)(pcic->cfgaddr + PCIC_MFROUTE_REG));
2145 			value &= ~0xff;
2146 			ddi_put32(pcic->cfg_handle, (uint32_t *)(pcic->cfgaddr +
2147 			    PCIC_MFROUTE_REG), value|PCIC_TI_MFUNC_SEL);
2148 		}
2149 
2150 		/* setup general card status change interrupt */
2151 		switch (pcic->pc_type) {
2152 			case PCIC_TI_PCI1225:
2153 			case PCIC_TI_PCI1221:
2154 			case PCIC_TI_PCI1031:
2155 			case PCIC_TI_PCI1520:
2156 			case PCIC_TI_PCI1410:
2157 				pcic_putb(pcic, i, PCIC_MANAGEMENT_INT,
2158 				    PCIC_CHANGE_DEFAULT);
2159 				break;
2160 			default:
2161 				if (pcic->pc_intr_mode ==
2162 				    PCIC_INTR_MODE_PCI_1) {
2163 					pcic_putb(pcic, i, PCIC_MANAGEMENT_INT,
2164 					    PCIC_CHANGE_DEFAULT);
2165 					break;
2166 				} else {
2167 					pcic_putb(pcic, i, PCIC_MANAGEMENT_INT,
2168 					    PCIC_CHANGE_DEFAULT |
2169 					    (pcic->pc_sockets[i].pcs_smi << 4));
2170 					break;
2171 				}
2172 		}
2173 
2174 		pcic->pc_flags |= PCF_INTRENAB;
2175 
2176 		/* take card out of RESET */
2177 		pcic_putb(pcic, i, PCIC_INTERRUPT, PCIC_RESET);
2178 		/* turn power off and let CS do this */
2179 		pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0);
2180 
2181 		/* final chip specific initialization */
2182 		switch (pcic->pc_type) {
2183 			case PCIC_VADEM:
2184 			pcic_putb(pcic, i, PCIC_VG_CONTROL,
2185 			    PCIC_VC_DELAYENABLE);
2186 			pcic->pc_flags |= PCF_DEBOUNCE;
2187 			/* FALLTHROUGH */
2188 			case PCIC_I82365SL:
2189 			pcic_putb(pcic, i, PCIC_GLOBAL_CONTROL,
2190 			    PCIC_GC_CSC_WRITE);
2191 			/* clear any pending interrupts */
2192 			value = pcic_getb(pcic, i, PCIC_CARD_STATUS_CHANGE);
2193 			pcic_putb(pcic, i, PCIC_CARD_STATUS_CHANGE, value);
2194 			break;
2195 		    /* The 82092 uses PCI config space to enable interrupts */
2196 			case PCIC_INTEL_i82092:
2197 			pcic_82092_smiirq_ctl(pcic, i, PCIC_82092_CTL_SMI,
2198 			    PCIC_82092_INT_ENABLE);
2199 			break;
2200 			case PCIC_CL_PD6729:
2201 			if (pcic->bus_speed >= PCIC_PCI_DEF_SYSCLK && i == 0) {
2202 				value = pcic_getb(pcic, i, PCIC_MISC_CTL_2);
2203 				pcic_putb(pcic, i, PCIC_MISC_CTL_2,
2204 				    value | PCIC_CL_TIMER_CLK_DIV);
2205 			}
2206 			break;
2207 		} /* switch */
2208 
2209 #if defined(PCIC_DEBUG)
2210 		if (pcic_debug)
2211 			cmn_err(CE_CONT,
2212 			    "socket %d value=%x, flags = %x (%s)\n",
2213 			    i, value, pcic->pc_sockets[i].pcs_flags,
2214 			    (pcic->pc_sockets[i].pcs_flags &
2215 			    PCS_CARD_PRESENT) ?
2216 			"card present" : "no card");
2217 #endif
2218 	}
2219 }
2220 
2221 /*
2222  * pcic_intr(caddr_t, caddr_t)
2223  *	interrupt handler for the PCIC style adapter
2224  *	handles all basic interrupts and also checks
2225  *	for status changes and notifies the nexus if
2226  *	necessary
2227  *
2228  *	On PCI bus adapters, also handles all card
2229  *	IO interrupts.
2230  */
2231 /*ARGSUSED*/
2232 uint32_t
pcic_intr(caddr_t arg1,caddr_t arg2)2233 pcic_intr(caddr_t arg1, caddr_t arg2)
2234 {
2235 	pcicdev_t *pcic = (pcicdev_t *)arg1;
2236 	int value = 0, i, ret = DDI_INTR_UNCLAIMED;
2237 	uint8_t status;
2238 	uint_t io_ints;
2239 
2240 #if defined(PCIC_DEBUG)
2241 	pcic_err(pcic->dip, 0xf,
2242 	    "pcic_intr: enter pc_flags=0x%x PCF_ATTACHED=0x%x"
2243 	    " pc_numsockets=%d \n",
2244 	    pcic->pc_flags, PCF_ATTACHED, pcic->pc_numsockets);
2245 #endif
2246 
2247 	if (!(pcic->pc_flags & PCF_ATTACHED))
2248 		return (DDI_INTR_UNCLAIMED);
2249 
2250 	mutex_enter(&pcic->intr_lock);
2251 
2252 	if (pcic->pc_flags & PCF_SUSPENDED) {
2253 		mutex_exit(&pcic->intr_lock);
2254 		return (ret);
2255 	}
2256 
2257 	/*
2258 	 * need to change to only ACK and touch the slot that
2259 	 * actually caused the interrupt.  Currently everything
2260 	 * is acked
2261 	 *
2262 	 * we need to look at all known sockets to determine
2263 	 * what might have happened, so step through the list
2264 	 * of them
2265 	 */
2266 
2267 	/*
2268 	 * Set the bitmask for IO interrupts to initially include all sockets
2269 	 */
2270 	io_ints = (1 << pcic->pc_numsockets) - 1;
2271 
2272 	for (i = 0; i < pcic->pc_numsockets; i++) {
2273 		int card_type;
2274 		pcic_socket_t *sockp;
2275 		int value_cb = 0;
2276 
2277 		sockp = &pcic->pc_sockets[i];
2278 		/* get the socket's I/O addresses */
2279 
2280 		if (sockp->pcs_flags & PCS_WAITING) {
2281 			io_ints &= ~(1 << i);
2282 			continue;
2283 		}
2284 
2285 		if (sockp->pcs_flags & PCS_CARD_IO)
2286 			card_type = IF_IO;
2287 		else
2288 			card_type = IF_MEMORY;
2289 
2290 		if (pcic->pc_io_type == PCIC_IO_TYPE_YENTA)
2291 			value_cb = pcic_getcb(pcic, CB_STATUS_EVENT);
2292 
2293 		value = pcic_change(pcic, i);
2294 
2295 		if ((value != 0) || (value_cb != 0)) {
2296 			int x = pcic->pc_cb_arg;
2297 
2298 			ret = DDI_INTR_CLAIMED;
2299 
2300 #if defined(PCIC_DEBUG)
2301 			pcic_err(pcic->dip, 0x9,
2302 			    "card_type = %d, value_cb = 0x%x\n",
2303 			    card_type,
2304 			    value_cb ? value_cb :
2305 			    pcic_getcb(pcic, CB_STATUS_EVENT));
2306 			if (pcic_debug)
2307 				cmn_err(CE_CONT,
2308 				    "\tchange on socket %d (%x)\n", i,
2309 				    value);
2310 #endif
2311 			/* find out what happened */
2312 			status = pcic_getb(pcic, i, PCIC_INTERFACE_STATUS);
2313 
2314 			/* acknowledge the interrupt */
2315 			if (value_cb)
2316 				pcic_putcb(pcic, CB_STATUS_EVENT, value_cb);
2317 
2318 			if (value)
2319 				pcic_putb(pcic, i, PCIC_CARD_STATUS_CHANGE,
2320 				    value);
2321 
2322 			if (pcic->pc_callback == NULL) {
2323 				/* if not callback handler, nothing to do */
2324 				continue;
2325 			}
2326 
2327 			/* Card Detect */
2328 			if (value & PCIC_CD_DETECT ||
2329 			    value_cb & CB_PS_CCDMASK) {
2330 				uint8_t irq;
2331 #if defined(PCIC_DEBUG)
2332 				if (pcic_debug)
2333 					cmn_err(CE_CONT,
2334 					    "\tcd_detect: status=%x,"
2335 					    " flags=%x\n",
2336 					    status, sockp->pcs_flags);
2337 #else
2338 #ifdef lint
2339 				if (status == 0)
2340 					status++;
2341 #endif
2342 #endif
2343 				/*
2344 				 * Turn off all interrupts for this socket here.
2345 				 */
2346 				irq = pcic_getb(pcic, sockp->pcs_socket,
2347 				    PCIC_MANAGEMENT_INT);
2348 				irq &= ~PCIC_CHANGE_MASK;
2349 				pcic_putb(pcic, sockp->pcs_socket,
2350 				    PCIC_MANAGEMENT_INT, irq);
2351 
2352 				pcic_putcb(pcic, CB_STATUS_MASK, 0x0);
2353 
2354 				/*
2355 				 * Put the socket in debouncing state so that
2356 				 * the leaf driver won't receive interrupts.
2357 				 * Crucial for handling surprise-removal.
2358 				 */
2359 				sockp->pcs_flags |= PCS_DEBOUNCING;
2360 
2361 				if (!sockp->pcs_cd_softint_flg) {
2362 					sockp->pcs_cd_softint_flg = 1;
2363 					(void) ddi_intr_trigger_softint(
2364 					    sockp->pcs_cd_softint_hdl, NULL);
2365 				}
2366 
2367 				io_ints &= ~(1 << i);
2368 			} /* PCIC_CD_DETECT */
2369 
2370 			/* Ready/Change Detect */
2371 			sockp->pcs_state ^= SBM_RDYBSY;
2372 			if (card_type == IF_MEMORY && value & PCIC_RD_DETECT) {
2373 				sockp->pcs_flags |= PCS_READY;
2374 				PC_CALLBACK(pcic->dip, x, PCE_CARD_READY, i);
2375 			}
2376 
2377 			/* Battery Warn Detect */
2378 			if (card_type == IF_MEMORY &&
2379 			    value & PCIC_BW_DETECT &&
2380 			    !(sockp->pcs_state & SBM_BVD2)) {
2381 				sockp->pcs_state |= SBM_BVD2;
2382 				PC_CALLBACK(pcic->dip, x,
2383 				    PCE_CARD_BATTERY_WARN, i);
2384 			}
2385 
2386 			/* Battery Dead Detect */
2387 			if (value & PCIC_BD_DETECT) {
2388 				/*
2389 				 * need to work out event if RI not enabled
2390 				 * and card_type == IF_IO
2391 				 */
2392 				if (card_type == IF_MEMORY &&
2393 				    !(sockp->pcs_state & SBM_BVD1)) {
2394 					sockp->pcs_state |= SBM_BVD1;
2395 					PC_CALLBACK(pcic->dip, x,
2396 					    PCE_CARD_BATTERY_DEAD,
2397 					    i);
2398 				} else {
2399 					/*
2400 					 * information in pin replacement
2401 					 * register if one is available
2402 					 */
2403 					PC_CALLBACK(pcic->dip, x,
2404 					    PCE_CARD_STATUS_CHANGE,
2405 					    i);
2406 				} /* IF_MEMORY */
2407 			} /* PCIC_BD_DETECT */
2408 		} /* if pcic_change */
2409 		/*
2410 		 * for any controllers that we can detect whether a socket
2411 		 * had an interrupt for the PC Card, we should sort that out
2412 		 * here.
2413 		 */
2414 	} /* for pc_numsockets */
2415 
2416 	/*
2417 	 * If we're on a PCI bus, we may need to cycle through each IO
2418 	 *	interrupt handler that is registered since they all
2419 	 *	share the same interrupt line.
2420 	 */
2421 
2422 
2423 #if defined(PCIC_DEBUG)
2424 	pcic_err(pcic->dip, 0xf,
2425 	    "pcic_intr: pc_intr_mode=%d pc_type=%x io_ints=0x%x\n",
2426 	    pcic->pc_intr_mode, pcic->pc_type, io_ints);
2427 #endif
2428 
2429 	if (io_ints) {
2430 		if (pcic_do_io_intr(pcic, io_ints) == DDI_INTR_CLAIMED)
2431 			ret = DDI_INTR_CLAIMED;
2432 	}
2433 
2434 	mutex_exit(&pcic->intr_lock);
2435 
2436 #if defined(PCIC_DEBUG)
2437 	pcic_err(pcic->dip, 0xf,
2438 	    "pcic_intr: ret=%d value=%d DDI_INTR_CLAIMED=%d\n",
2439 	    ret, value, DDI_INTR_CLAIMED);
2440 #endif
2441 
2442 	return (ret);
2443 }
2444 
2445 /*
2446  * pcic_change()
2447  *	check to see if this socket had a change in state
2448  *	by checking the status change register
2449  */
2450 static int
pcic_change(pcicdev_t * pcic,int socket)2451 pcic_change(pcicdev_t *pcic, int socket)
2452 {
2453 	return (pcic_getb(pcic, socket, PCIC_CARD_STATUS_CHANGE));
2454 }
2455 
2456 /*
2457  * pcic_do_io_intr - calls client interrupt handlers
2458  */
2459 static int
pcic_do_io_intr(pcicdev_t * pcic,uint32_t sockets)2460 pcic_do_io_intr(pcicdev_t *pcic, uint32_t sockets)
2461 {
2462 	inthandler_t *tmp;
2463 	int ret = DDI_INTR_UNCLAIMED;
2464 
2465 #if defined(PCIC_DEBUG)
2466 	pcic_err(pcic->dip, 0xf,
2467 	    "pcic_do_io_intr: pcic=%p sockets=%d irq_top=%p\n",
2468 	    (void *)pcic, (int)sockets, (void *)pcic->irq_top);
2469 #endif
2470 
2471 	if (pcic->irq_top != NULL) {
2472 		tmp = pcic->irq_current;
2473 
2474 		do {
2475 		int cur = pcic->irq_current->socket;
2476 		pcic_socket_t *sockp =
2477 		    &pcic->pc_sockets[cur];
2478 
2479 #if defined(PCIC_DEBUG)
2480 		pcic_err(pcic->dip, 0xf,
2481 		    "\t pcs_flags=0x%x PCS_CARD_PRESENT=0x%x\n",
2482 		    sockp->pcs_flags, PCS_CARD_PRESENT);
2483 		pcic_err(pcic->dip, 0xf,
2484 		    "\t sockets=%d cur=%d intr=%p arg1=%p "
2485 		    "arg2=%p\n",
2486 		    sockets, cur, (void *)pcic->irq_current->intr,
2487 		    pcic->irq_current->arg1,
2488 		    pcic->irq_current->arg2);
2489 #endif
2490 		if ((sockp->pcs_flags & PCS_CARD_PRESENT) &&
2491 		    !(sockp->pcs_flags & PCS_DEBOUNCING) &&
2492 		    (sockets & (1 << cur))) {
2493 
2494 			if ((*pcic->irq_current->intr)(pcic->irq_current->arg1,
2495 			    pcic->irq_current->arg2) == DDI_INTR_CLAIMED)
2496 				ret = DDI_INTR_CLAIMED;
2497 
2498 #if defined(PCIC_DEBUG)
2499 			pcic_err(pcic->dip, 0xf,
2500 			    "\t ret=%d DDI_INTR_CLAIMED=%d\n",
2501 			    ret, DDI_INTR_CLAIMED);
2502 #endif
2503 		}
2504 
2505 
2506 		if ((pcic->irq_current = pcic->irq_current->next) == NULL)
2507 					pcic->irq_current = pcic->irq_top;
2508 
2509 		} while (pcic->irq_current != tmp);
2510 
2511 		if ((pcic->irq_current = pcic->irq_current->next) == NULL)
2512 					pcic->irq_current = pcic->irq_top;
2513 
2514 	} else {
2515 		ret = DDI_INTR_UNCLAIMED;
2516 	}
2517 
2518 #if defined(PCIC_DEBUG)
2519 	pcic_err(pcic->dip, 0xf,
2520 	    "pcic_do_io_intr: exit ret=%d DDI_INTR_CLAIMED=%d\n",
2521 	    ret, DDI_INTR_CLAIMED);
2522 #endif
2523 
2524 	return (ret);
2525 
2526 }
2527 
2528 /*
2529  * pcic_inquire_adapter()
2530  *	SocketServices InquireAdapter function
2531  *	get characteristics of the physical adapter
2532  */
2533 /*ARGSUSED*/
2534 static int
pcic_inquire_adapter(dev_info_t * dip,inquire_adapter_t * config)2535 pcic_inquire_adapter(dev_info_t *dip, inquire_adapter_t *config)
2536 {
2537 	anp_t *anp = ddi_get_driver_private(dip);
2538 	pcicdev_t *pcic = anp->an_private;
2539 
2540 	config->NumSockets = pcic->pc_numsockets;
2541 	config->NumWindows = pcic->pc_numsockets * PCIC_NUMWINSOCK;
2542 	config->NumEDCs = 0;
2543 	config->AdpCaps = 0;
2544 	config->ActiveHigh = 0;
2545 	config->ActiveLow = PCIC_AVAIL_IRQS;
2546 	config->NumPower = pcic->pc_numpower;
2547 	config->power_entry = pcic->pc_power; /* until we resolve this */
2548 #if defined(PCIC_DEBUG)
2549 	if (pcic_debug) {
2550 		cmn_err(CE_CONT, "pcic_inquire_adapter:\n");
2551 		cmn_err(CE_CONT, "\tNumSockets=%d\n", config->NumSockets);
2552 		cmn_err(CE_CONT, "\tNumWindows=%d\n", config->NumWindows);
2553 	}
2554 #endif
2555 	config->ResourceFlags = 0;
2556 	switch (pcic->pc_intr_mode) {
2557 	case PCIC_INTR_MODE_PCI_1:
2558 		config->ResourceFlags |= RES_OWN_IRQ | RES_IRQ_NEXUS |
2559 		    RES_IRQ_SHAREABLE;
2560 		break;
2561 	}
2562 	return (SUCCESS);
2563 }
2564 
2565 /*
2566  * pcic_callback()
2567  *	The PCMCIA nexus calls us via this function
2568  *	in order to set the callback function we are
2569  *	to call the nexus with
2570  */
2571 /*ARGSUSED*/
2572 static int
pcic_callback(dev_info_t * dip,int (* handler)(),int arg)2573 pcic_callback(dev_info_t *dip, int (*handler)(), int arg)
2574 {
2575 	anp_t *anp = ddi_get_driver_private(dip);
2576 	pcicdev_t *pcic = anp->an_private;
2577 
2578 	if (handler != NULL) {
2579 		pcic->pc_callback = handler;
2580 		pcic->pc_cb_arg  = arg;
2581 		pcic->pc_flags |= PCF_CALLBACK;
2582 	} else {
2583 		pcic->pc_callback = NULL;
2584 		pcic->pc_cb_arg = 0;
2585 		pcic->pc_flags &= ~PCF_CALLBACK;
2586 	}
2587 	/*
2588 	 * we're now registered with the nexus
2589 	 * it is acceptable to do callbacks at this point.
2590 	 * don't call back from here though since it could block
2591 	 */
2592 	return (PC_SUCCESS);
2593 }
2594 
2595 /*
2596  * pcic_calc_speed (pcicdev_t *pcic, uint32_t speed)
2597  *	calculate the speed bits from the specified memory speed
2598  *	there may be more to do here
2599  */
2600 
2601 static int
pcic_calc_speed(pcicdev_t * pcic,uint32_t speed)2602 pcic_calc_speed(pcicdev_t *pcic, uint32_t speed)
2603 {
2604 	uint32_t wspeed = 1;	/* assume 1 wait state when unknown */
2605 	uint32_t bspeed = PCIC_ISA_DEF_SYSCLK;
2606 
2607 	switch (pcic->pc_type) {
2608 		case PCIC_I82365SL:
2609 		case PCIC_VADEM:
2610 		case PCIC_VADEM_VG469:
2611 		default:
2612 		/* Intel chip wants it in waitstates */
2613 		wspeed = mhztons(PCIC_ISA_DEF_SYSCLK) * 3;
2614 		if (speed <= wspeed)
2615 			wspeed = 0;
2616 		else if (speed <= (wspeed += mhztons(bspeed)))
2617 			wspeed = 1;
2618 		else if (speed <= (wspeed += mhztons(bspeed)))
2619 			wspeed = 2;
2620 		else
2621 			wspeed = 3;
2622 		wspeed <<= 6; /* put in right bit positions */
2623 		break;
2624 
2625 		case PCIC_INTEL_i82092:
2626 		wspeed = SYSMEM_82092_80NS;
2627 		if (speed > 80)
2628 			wspeed = SYSMEM_82092_100NS;
2629 		if (speed > 100)
2630 			wspeed = SYSMEM_82092_150NS;
2631 		if (speed > 150)
2632 			wspeed = SYSMEM_82092_200NS;
2633 		if (speed > 200)
2634 			wspeed = SYSMEM_82092_250NS;
2635 		if (speed > 250)
2636 			wspeed = SYSMEM_82092_600NS;
2637 		wspeed <<= 5;	/* put in right bit positions */
2638 		break;
2639 
2640 	} /* switch */
2641 
2642 	return (wspeed);
2643 }
2644 
2645 /*
2646  * These values are taken from the PC Card Standard Electrical Specification.
2647  * Generally the larger value is taken if 2 are possible.
2648  */
2649 static struct pcic_card_times {
2650 	uint16_t cycle;	/* Speed as found in the atribute space of the card. */
2651 	uint16_t setup;	/* Corresponding address setup time. */
2652 	uint16_t width;	/* Corresponding width, OE or WE. */
2653 	uint16_t hold;	/* Corresponding data or address hold time. */
2654 } pcic_card_times[] = {
2655 
2656 /*
2657  * Note: The rounded up times for 250, 200 & 150 have been increased
2658  * due to problems with the 3-Com ethernet cards (pcelx) on UBIIi.
2659  * See BugID 00663.
2660  */
2661 
2662 /*
2663  * Rounded up times           Original times from
2664  * that add up to the         the PCMCIA Spec.
2665  * cycle time.
2666  */
2667 	{600, 180, 370, 140},	/* 100, 300,  70 */
2668 	{400, 120, 300, 90},	/* Made this one up */
2669 	{250, 100, 190, 70},	/*  30, 150,  30 */
2670 	{200, 80, 170, 70},	/*  20, 120,  30 */
2671 	{150, 50, 110, 40},	/*  20,  80,  20 */
2672 	{100, 40, 80, 40},	/*  10,  60,  15 */
2673 	{0, 10, 60, 15}		/*  10,  60,  15 */
2674 };
2675 
2676 /*
2677  * pcic_set_cdtimers
2678  *	This is specific to several Cirrus Logic chips
2679  */
2680 static void
pcic_set_cdtimers(pcicdev_t * pcic,int socket,uint32_t speed,int tset)2681 pcic_set_cdtimers(pcicdev_t *pcic, int socket, uint32_t speed, int tset)
2682 {
2683 	int cmd, set, rec, offset, clk_pulse;
2684 	struct pcic_card_times *ctp;
2685 
2686 	if ((tset == IOMEM_CLTIMER_SET_1) || (tset == SYSMEM_CLTIMER_SET_1))
2687 		offset = 3;
2688 	else
2689 		offset = 0;
2690 
2691 	clk_pulse = mhztons(pcic->bus_speed);
2692 	for (ctp = pcic_card_times; speed < ctp->cycle; ctp++)
2693 		;
2694 
2695 	/*
2696 	 * Add (clk_pulse/2) and an extra 1 to account for rounding errors.
2697 	 */
2698 	set = ((ctp->setup + 10 + 1 + (clk_pulse/2))/clk_pulse) - 1;
2699 	if (set < 0)
2700 		set = 0;
2701 
2702 	cmd = ((ctp->width + 10 + 1 + (clk_pulse/2))/clk_pulse) - 1;
2703 	if (cmd < 0)
2704 		cmd = 0;
2705 
2706 	rec = ((ctp->hold + 10 + 1 + (clk_pulse/2))/clk_pulse) - 2;
2707 	if (rec < 0)
2708 		rec = 0;
2709 
2710 #if defined(PCIC_DEBUG)
2711 	pcic_err(pcic->dip, 8, "pcic_set_cdtimers(%d, Timer Set %d)\n"
2712 	    "ct=%d, cp=%d, cmd=0x%x, setup=0x%x, rec=0x%x\n",
2713 	    (unsigned)speed, offset == 3 ? 1 : 0,
2714 	    ctp->cycle, clk_pulse, cmd, set, rec);
2715 #endif
2716 
2717 	pcic_putb(pcic, socket, PCIC_TIME_COMMAND_0 + offset, cmd);
2718 	pcic_putb(pcic, socket, PCIC_TIME_SETUP_0 + offset, set);
2719 	pcic_putb(pcic, socket, PCIC_TIME_RECOVER_0 + offset, rec);
2720 }
2721 
2722 /*
2723  * pcic_set_window
2724  *	essentially the same as the Socket Services specification
2725  *	We use socket and not adapter since they are identifiable
2726  *	but the rest is the same
2727  *
2728  *	dip	pcic driver's device information
2729  *	window	parameters for the request
2730  */
2731 static int
pcic_set_window(dev_info_t * dip,set_window_t * window)2732 pcic_set_window(dev_info_t *dip, set_window_t *window)
2733 {
2734 	anp_t *anp = ddi_get_driver_private(dip);
2735 	pcicdev_t *pcic = anp->an_private;
2736 	int select;
2737 	int socket, pages, which, ret;
2738 	pcic_socket_t *sockp = &pcic->pc_sockets[window->socket];
2739 	ra_return_t res;
2740 	ndi_ra_request_t req;
2741 	uint32_t base = window->base;
2742 
2743 #if defined(PCIC_DEBUG)
2744 	if (pcic_debug) {
2745 		cmn_err(CE_CONT, "pcic_set_window: entered\n");
2746 		cmn_err(CE_CONT,
2747 		    "\twindow=%d, socket=%d, WindowSize=%d, speed=%d\n",
2748 		    window->window, window->socket, window->WindowSize,
2749 		    window->speed);
2750 		cmn_err(CE_CONT,
2751 		    "\tbase=%x, state=%x\n", (unsigned)window->base,
2752 		    (unsigned)window->state);
2753 	}
2754 #endif
2755 
2756 	/*
2757 	 * do some basic sanity checking on what we support
2758 	 * we don't do paged mode
2759 	 */
2760 	if (window->state & WS_PAGED) {
2761 		cmn_err(CE_WARN, "pcic_set_window: BAD_ATTRIBUTE\n");
2762 		return (BAD_ATTRIBUTE);
2763 	}
2764 
2765 	/*
2766 	 * we don't care about previous mappings.
2767 	 * Card Services will deal with that so don't
2768 	 * even check
2769 	 */
2770 
2771 	socket = window->socket;
2772 
2773 	if (!(window->state & WS_IO)) {
2774 		int win, tmp;
2775 		pcs_memwin_t *memp;
2776 #if defined(PCIC_DEBUG)
2777 		if (pcic_debug)
2778 			cmn_err(CE_CONT, "\twindow type is memory\n");
2779 #endif
2780 		/* this is memory window mapping */
2781 		win = window->window % PCIC_NUMWINSOCK;
2782 		tmp = window->window / PCIC_NUMWINSOCK;
2783 
2784 		/* only windows 2-6 can do memory mapping */
2785 		if (tmp != window->socket || win < PCIC_IOWINDOWS) {
2786 			cmn_err(CE_CONT,
2787 			    "\tattempt to map to non-mem window\n");
2788 			return (BAD_WINDOW);
2789 		}
2790 
2791 		if (window->WindowSize == 0)
2792 			window->WindowSize = MEM_MIN;
2793 		else if ((window->WindowSize & (PCIC_PAGE-1)) != 0) {
2794 			cmn_err(CE_WARN, "pcic_set_window: BAD_SIZE\n");
2795 			return (BAD_SIZE);
2796 		}
2797 
2798 		mutex_enter(&pcic->pc_lock); /* protect the registers */
2799 
2800 		memp = &sockp->pcs_windows[win].mem;
2801 		memp->pcw_speed = window->speed;
2802 
2803 		win -= PCIC_IOWINDOWS; /* put in right range */
2804 
2805 		if (window->WindowSize != memp->pcw_len)
2806 			which = memp->pcw_len;
2807 		else
2808 			which = 0;
2809 
2810 		if (window->state & WS_ENABLED) {
2811 			uint32_t wspeed;
2812 #if defined(PCIC_DEBUG)
2813 			if (pcic_debug) {
2814 				cmn_err(CE_CONT,
2815 				    "\tbase=%x, win=%d\n", (unsigned)base,
2816 				    win);
2817 				if (which)
2818 					cmn_err(CE_CONT,
2819 					    "\tneed to remap window\n");
2820 			}
2821 #endif
2822 
2823 			if (which && (memp->pcw_status & PCW_MAPPED)) {
2824 				ddi_regs_map_free(&memp->pcw_handle);
2825 				res.ra_addr_lo = memp->pcw_base;
2826 				res.ra_len = memp->pcw_len;
2827 				(void) pcmcia_free_mem(memp->res_dip, &res);
2828 				memp->pcw_status &= ~(PCW_MAPPED|PCW_ENABLED);
2829 				memp->pcw_hostmem = NULL;
2830 				memp->pcw_base = 0;
2831 				memp->pcw_len = 0;
2832 			}
2833 
2834 			which = window->WindowSize >> PAGE_SHIFT;
2835 
2836 			if (!(memp->pcw_status & PCW_MAPPED)) {
2837 				ret = 0;
2838 
2839 				memp->pcw_base = base;
2840 				bzero(&req, sizeof (req));
2841 				req.ra_len = which << PAGE_SHIFT;
2842 				req.ra_addr = (uint64_t)memp->pcw_base;
2843 				req.ra_boundbase = pcic->pc_base;
2844 				req.ra_boundlen  = pcic->pc_bound;
2845 				req.ra_flags = (memp->pcw_base ?
2846 				    NDI_RA_ALLOC_SPECIFIED : 0) |
2847 				    NDI_RA_ALLOC_BOUNDED;
2848 				req.ra_align_mask =
2849 				    (PAGESIZE - 1) | (PCIC_PAGE - 1);
2850 #if defined(PCIC_DEBUG)
2851 					pcic_err(dip, 8,
2852 					    "\tlen 0x%"PRIx64
2853 					    "addr 0x%"PRIx64"bbase 0x%"PRIx64
2854 					    " blen 0x%"PRIx64" flags 0x%x"
2855 					    " algn 0x%"PRIx64"\n",
2856 					    req.ra_len, req.ra_addr,
2857 					    req.ra_boundbase,
2858 					    req.ra_boundlen, req.ra_flags,
2859 					    req.ra_align_mask);
2860 #endif
2861 
2862 				ret = pcmcia_alloc_mem(dip, &req, &res,
2863 				    &memp->res_dip);
2864 				if (ret == DDI_FAILURE) {
2865 					mutex_exit(&pcic->pc_lock);
2866 					cmn_err(CE_WARN,
2867 					"\tpcmcia_alloc_mem() failed\n");
2868 					return (BAD_SIZE);
2869 				}
2870 				memp->pcw_base = res.ra_addr_lo;
2871 				base = memp->pcw_base;
2872 
2873 #if defined(PCIC_DEBUG)
2874 				if (pcic_debug)
2875 					cmn_err(CE_CONT,
2876 					    "\tsetwindow: new base=%x\n",
2877 					    (unsigned)memp->pcw_base);
2878 #endif
2879 				memp->pcw_len = window->WindowSize;
2880 
2881 				which = pcmcia_map_reg(pcic->dip,
2882 				    window->child,
2883 				    &res,
2884 				    (uint32_t)(window->state &
2885 				    0xffff) |
2886 				    (window->socket << 16),
2887 				    (caddr_t *)&memp->pcw_hostmem,
2888 				    &memp->pcw_handle,
2889 				    &window->attr, 0);
2890 
2891 				if (which != DDI_SUCCESS) {
2892 
2893 					cmn_err(CE_WARN, "\tpcmcia_map_reg() "
2894 					    "failed\n");
2895 
2896 					res.ra_addr_lo = memp->pcw_base;
2897 					res.ra_len = memp->pcw_len;
2898 					(void) pcmcia_free_mem(memp->res_dip,
2899 					    &res);
2900 
2901 					mutex_exit(&pcic->pc_lock);
2902 
2903 					return (BAD_WINDOW);
2904 				}
2905 				memp->pcw_status |= PCW_MAPPED;
2906 #if defined(PCIC_DEBUG)
2907 				if (pcic_debug)
2908 					cmn_err(CE_CONT,
2909 					    "\tmap=%x, hostmem=%p\n",
2910 					    which,
2911 					    (void *)memp->pcw_hostmem);
2912 #endif
2913 			} else {
2914 				base = memp->pcw_base;
2915 			}
2916 
2917 			/* report the handle back to caller */
2918 			window->handle = memp->pcw_handle;
2919 
2920 #if defined(PCIC_DEBUG)
2921 			if (pcic_debug) {
2922 				cmn_err(CE_CONT,
2923 				    "\twindow mapped to %x@%x len=%d\n",
2924 				    (unsigned)window->base,
2925 				    (unsigned)memp->pcw_base,
2926 				    memp->pcw_len);
2927 			}
2928 #endif
2929 
2930 			/* find the register set offset */
2931 			select = win * PCIC_MEM_1_OFFSET;
2932 #if defined(PCIC_DEBUG)
2933 			if (pcic_debug)
2934 				cmn_err(CE_CONT, "\tselect=%x\n", select);
2935 #endif
2936 
2937 			/*
2938 			 * at this point, the register window indicator has
2939 			 * been converted to be an offset from the first
2940 			 * set of registers that are used for programming
2941 			 * the window mapping and the offset used to select
2942 			 * the correct set of registers to access the
2943 			 * specified socket.  This allows basing everything
2944 			 * off the _0 window
2945 			 */
2946 
2947 			/* map the physical page base address */
2948 			which = (window->state & WS_16BIT) ? SYSMEM_DATA_16 : 0;
2949 			which |= (window->speed <= MEM_SPEED_MIN) ?
2950 			    SYSMEM_ZERO_WAIT : 0;
2951 
2952 			/* need to select register set */
2953 			select = PCIC_MEM_1_OFFSET * win;
2954 
2955 			pcic_putb(pcic, socket,
2956 			    PCIC_SYSMEM_0_STARTLOW + select,
2957 			    SYSMEM_LOW(base));
2958 			pcic_putb(pcic, socket,
2959 			    PCIC_SYSMEM_0_STARTHI + select,
2960 			    SYSMEM_HIGH(base) | which);
2961 
2962 			/*
2963 			 * Some adapters can decode window addresses greater
2964 			 * than 16-bits worth, so handle them here.
2965 			 */
2966 			switch (pcic->pc_type) {
2967 			case PCIC_INTEL_i82092:
2968 				pcic_putb(pcic, socket,
2969 				    PCIC_82092_CPAGE,
2970 				    SYSMEM_EXT(base));
2971 				break;
2972 			case PCIC_CL_PD6729:
2973 			case PCIC_CL_PD6730:
2974 				clext_reg_write(pcic, socket,
2975 				    PCIC_CLEXT_MMAP0_UA + win,
2976 				    SYSMEM_EXT(base));
2977 				break;
2978 			case PCIC_TI_PCI1130:
2979 				/*
2980 				 * Note that the TI chip has one upper byte
2981 				 * per socket so all windows get bound to a
2982 				 * 16MB segment.  This must be detected and
2983 				 * handled appropriately.  We can detect that
2984 				 * it is done by seeing if the pc_base has
2985 				 * changed and changing when the register
2986 				 * is first set.  This will force the bounds
2987 				 * to be correct.
2988 				 */
2989 				if (pcic->pc_bound == 0xffffffff) {
2990 					pcic_putb(pcic, socket,
2991 					    PCIC_TI_WINDOW_PAGE_PCI,
2992 					    SYSMEM_EXT(base));
2993 					pcic->pc_base = SYSMEM_EXT(base) << 24;
2994 					pcic->pc_bound = 0x1000000;
2995 				}
2996 				break;
2997 			case PCIC_TI_PCI1031:
2998 			case PCIC_TI_PCI1131:
2999 			case PCIC_TI_PCI1250:
3000 			case PCIC_TI_PCI1225:
3001 			case PCIC_TI_PCI1221:
3002 			case PCIC_SMC_34C90:
3003 			case PCIC_CL_PD6832:
3004 			case PCIC_RICOH_RL5C466:
3005 			case PCIC_TI_PCI1410:
3006 			case PCIC_ENE_1410:
3007 			case PCIC_TI_PCI1510:
3008 			case PCIC_TI_PCI1520:
3009 			case PCIC_O2_OZ6912:
3010 			case PCIC_TI_PCI1420:
3011 			case PCIC_ENE_1420:
3012 			case PCIC_TI_VENDOR:
3013 			case PCIC_TOSHIBA_TOPIC100:
3014 			case PCIC_TOSHIBA_TOPIC95:
3015 			case PCIC_TOSHIBA_VENDOR:
3016 			case PCIC_RICOH_VENDOR:
3017 			case PCIC_O2MICRO_VENDOR:
3018 				pcic_putb(pcic, socket,
3019 				    PCIC_YENTA_MEM_PAGE + win,
3020 				    SYSMEM_EXT(base));
3021 				break;
3022 			default:
3023 				cmn_err(CE_NOTE, "pcic_set_window: unknown "
3024 				    "cardbus vendor:0x%X\n",
3025 				    pcic->pc_type);
3026 				pcic_putb(pcic, socket,
3027 				    PCIC_YENTA_MEM_PAGE + win,
3028 				    SYSMEM_EXT(base));
3029 
3030 				break;
3031 			} /* switch */
3032 
3033 			/*
3034 			 * specify the length of the mapped range
3035 			 * we convert to pages (rounding up) so that
3036 			 * the hardware gets the right thing
3037 			 */
3038 			pages = (window->WindowSize+PCIC_PAGE-1)/PCIC_PAGE;
3039 
3040 			/*
3041 			 * Setup this window's timing.
3042 			 */
3043 			switch (pcic->pc_type) {
3044 			case PCIC_CL_PD6729:
3045 			case PCIC_CL_PD6730:
3046 			case PCIC_CL_PD6710:
3047 			case PCIC_CL_PD6722:
3048 				wspeed = SYSMEM_CLTIMER_SET_0;
3049 				pcic_set_cdtimers(pcic, socket,
3050 				    window->speed,
3051 				    wspeed);
3052 				break;
3053 
3054 			case PCIC_INTEL_i82092:
3055 			default:
3056 				wspeed = pcic_calc_speed(pcic, window->speed);
3057 				break;
3058 			} /* switch */
3059 
3060 #if defined(PCIC_DEBUG)
3061 			if (pcic_debug)
3062 				cmn_err(CE_CONT,
3063 				    "\twindow %d speed bits = %x for "
3064 				    "%dns\n",
3065 				    win, (unsigned)wspeed, window->speed);
3066 #endif
3067 
3068 			pcic_putb(pcic, socket, PCIC_SYSMEM_0_STOPLOW + select,
3069 			    SYSMEM_LOW(base +
3070 			    (pages * PCIC_PAGE)-1));
3071 
3072 			wspeed |= SYSMEM_HIGH(base + (pages * PCIC_PAGE)-1);
3073 			pcic_putb(pcic, socket, PCIC_SYSMEM_0_STOPHI + select,
3074 			    wspeed);
3075 
3076 			/*
3077 			 * now map the card's memory pages - we start with page
3078 			 * 0
3079 			 * we also default to AM -- set page might change it
3080 			 */
3081 			base = memp->pcw_base;
3082 			pcic_putb(pcic, socket,
3083 			    PCIC_CARDMEM_0_LOW + select,
3084 			    CARDMEM_LOW(0 - (uint32_t)base));
3085 
3086 			pcic_putb(pcic, socket,
3087 			    PCIC_CARDMEM_0_HI + select,
3088 			    CARDMEM_HIGH(0 - (uint32_t)base) |
3089 			    CARDMEM_REG_ACTIVE);
3090 
3091 			/*
3092 			 * enable the window even though redundant
3093 			 * and SetPage may do it again.
3094 			 */
3095 			select = pcic_getb(pcic, socket,
3096 			    PCIC_MAPPING_ENABLE);
3097 			select |= SYSMEM_WINDOW(win);
3098 			pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, select);
3099 			memp->pcw_offset = 0;
3100 			memp->pcw_status |= PCW_ENABLED;
3101 		} else {
3102 			/*
3103 			 * not only do we unmap the memory, the
3104 			 * window has been turned off.
3105 			 */
3106 			if (which && memp->pcw_status & PCW_MAPPED) {
3107 				ddi_regs_map_free(&memp->pcw_handle);
3108 				res.ra_addr_lo = memp->pcw_base;
3109 				res.ra_len = memp->pcw_len;
3110 				(void) pcmcia_free_mem(memp->res_dip, &res);
3111 				memp->pcw_hostmem = NULL;
3112 				memp->pcw_status &= ~PCW_MAPPED;
3113 			}
3114 
3115 			/* disable current mapping */
3116 			select = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE);
3117 			select &= ~SYSMEM_WINDOW(win);
3118 			pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, select);
3119 			memp->pcw_status &= ~PCW_ENABLED;
3120 		}
3121 		memp->pcw_len = window->WindowSize;
3122 		window->handle = memp->pcw_handle;
3123 #if defined(PCIC_DEBUG)
3124 		if (pcic_debug)
3125 			xxdmp_all_regs(pcic, window->socket, -1);
3126 #endif
3127 	} else {
3128 		/*
3129 		 * This is a request for an IO window
3130 		 */
3131 		int win, tmp;
3132 		pcs_iowin_t *winp;
3133 				/* I/O windows */
3134 #if defined(PCIC_DEBUG)
3135 		if (pcic_debug)
3136 			cmn_err(CE_CONT, "\twindow type is I/O\n");
3137 #endif
3138 
3139 		/* only windows 0 and 1 can do I/O */
3140 		win = window->window % PCIC_NUMWINSOCK;
3141 		tmp = window->window / PCIC_NUMWINSOCK;
3142 
3143 		if (win >= PCIC_IOWINDOWS || tmp != window->socket) {
3144 			cmn_err(CE_WARN,
3145 			    "\twindow is out of range (%d)\n",
3146 			    window->window);
3147 			return (BAD_WINDOW);
3148 		}
3149 
3150 		mutex_enter(&pcic->pc_lock); /* protect the registers */
3151 
3152 		winp = &sockp->pcs_windows[win].io;
3153 		winp->pcw_speed = window->speed;
3154 		if (window->WindowSize != 1 && window->WindowSize & 1) {
3155 			/* we don't want an odd-size window */
3156 			window->WindowSize++;
3157 		}
3158 		winp->pcw_len = window->WindowSize;
3159 
3160 		if (window->state & WS_ENABLED) {
3161 			if (winp->pcw_status & PCW_MAPPED) {
3162 				ddi_regs_map_free(&winp->pcw_handle);
3163 				res.ra_addr_lo = winp->pcw_base;
3164 				res.ra_len = winp->pcw_len;
3165 				(void) pcmcia_free_io(winp->res_dip, &res);
3166 				winp->pcw_status &= ~(PCW_MAPPED|PCW_ENABLED);
3167 			}
3168 
3169 			/*
3170 			 * if the I/O address wasn't allocated, allocate
3171 			 *	it now. If it was allocated, it better
3172 			 *	be free to use.
3173 			 * The winp->pcw_offset value is set and used
3174 			 *	later on if the particular adapter
3175 			 *	that we're running on has the ability
3176 			 *	to translate IO accesses to the card
3177 			 *	(such as some adapters  in the Cirrus
3178 			 *	Logic family).
3179 			 */
3180 			winp->pcw_offset = 0;
3181 
3182 			/*
3183 			 * Setup the request parameters for the
3184 			 *	requested base and length. If
3185 			 *	we're on an adapter that has
3186 			 *	IO window offset registers, then
3187 			 *	we don't need a specific base
3188 			 *	address, just a length, and then
3189 			 *	we'll cause the correct IO address
3190 			 *	to be generated on the socket by
3191 			 *	setting up the IO window offset
3192 			 *	registers.
3193 			 * For adapters that support this capability, we
3194 			 *	always use the IO window offset registers,
3195 			 *	even if the passed base/length would be in
3196 			 *	range.
3197 			 */
3198 			base = window->base;
3199 			bzero(&req, sizeof (req));
3200 			req.ra_len = window->WindowSize;
3201 
3202 			req.ra_addr = (uint64_t)
3203 			    ((pcic->pc_flags & PCF_IO_REMAP) ? 0 : base);
3204 			req.ra_flags = (req.ra_addr) ?
3205 			    NDI_RA_ALLOC_SPECIFIED : 0;
3206 
3207 			req.ra_flags |= NDI_RA_ALIGN_SIZE;
3208 			/* need to rethink this */
3209 			req.ra_boundbase = pcic->pc_iobase;
3210 			req.ra_boundlen = pcic->pc_iobound;
3211 			req.ra_flags |= NDI_RA_ALLOC_BOUNDED;
3212 
3213 #if defined(PCIC_DEBUG)
3214 				pcic_err(dip, 8,
3215 				    "\tlen 0x%"PRIx64" addr 0x%"PRIx64
3216 				    "bbase 0x%"PRIx64
3217 				    "blen 0x%"PRIx64" flags 0x%x algn 0x%"
3218 				    PRIx64"\n",
3219 				    req.ra_len, (uint64_t)req.ra_addr,
3220 				    req.ra_boundbase,
3221 				    req.ra_boundlen, req.ra_flags,
3222 				    req.ra_align_mask);
3223 #endif
3224 
3225 			/*
3226 			 * Try to allocate the space. If we fail this,
3227 			 *	return the appropriate error depending
3228 			 *	on whether the caller specified a
3229 			 *	specific base address or not.
3230 			 */
3231 			if (pcmcia_alloc_io(dip, &req, &res,
3232 			    &winp->res_dip) == DDI_FAILURE) {
3233 				winp->pcw_status &= ~PCW_ENABLED;
3234 				mutex_exit(&pcic->pc_lock);
3235 				cmn_err(CE_WARN, "Failed to alloc I/O:\n"
3236 				    "\tlen 0x%" PRIx64 " addr 0x%" PRIx64
3237 				    "bbase 0x%" PRIx64
3238 				    "blen 0x%" PRIx64 "flags 0x%x"
3239 				    "algn 0x%" PRIx64 "\n",
3240 				    req.ra_len, req.ra_addr,
3241 				    req.ra_boundbase,
3242 				    req.ra_boundlen, req.ra_flags,
3243 				    req.ra_align_mask);
3244 
3245 				return (base?BAD_BASE:BAD_SIZE);
3246 			} /* pcmcia_alloc_io */
3247 
3248 			/*
3249 			 * Don't change the original base. Either we use
3250 			 * the offset registers below (PCF_IO_REMAP is set)
3251 			 * or it was allocated correctly anyway.
3252 			 */
3253 			winp->pcw_base = res.ra_addr_lo;
3254 
3255 #if defined(PCIC_DEBUG)
3256 				pcic_err(dip, 8,
3257 				    "\tsetwindow: new base=%x orig base 0x%x\n",
3258 				    (unsigned)winp->pcw_base, base);
3259 #endif
3260 
3261 			if ((which = pcmcia_map_reg(pcic->dip,
3262 			    window->child,
3263 			    &res,
3264 			    (uint32_t)(window->state &
3265 			    0xffff) |
3266 			    (window->socket << 16),
3267 			    (caddr_t *)&winp->pcw_hostmem,
3268 			    &winp->pcw_handle,
3269 			    &window->attr,
3270 			    base)) != DDI_SUCCESS) {
3271 
3272 				cmn_err(CE_WARN, "pcmcia_map_reg()"
3273 				    "failed\n");
3274 
3275 					res.ra_addr_lo = winp->pcw_base;
3276 					res.ra_len = winp->pcw_len;
3277 					(void) pcmcia_free_io(winp->res_dip,
3278 					    &res);
3279 
3280 					mutex_exit(&pcic->pc_lock);
3281 					return (BAD_WINDOW);
3282 			}
3283 
3284 			window->handle = winp->pcw_handle;
3285 			winp->pcw_status |= PCW_MAPPED;
3286 
3287 			/* find the register set offset */
3288 			select = win * PCIC_IO_OFFSET;
3289 
3290 #if defined(PCIC_DEBUG)
3291 			if (pcic_debug) {
3292 				cmn_err(CE_CONT,
3293 				    "\tenable: window=%d, select=%x, "
3294 				    "base=%x, handle=%p\n",
3295 				    win, select,
3296 				    (unsigned)window->base,
3297 				    (void *)window->handle);
3298 			}
3299 #endif
3300 			/*
3301 			 * at this point, the register window indicator has
3302 			 * been converted to be an offset from the first
3303 			 * set of registers that are used for programming
3304 			 * the window mapping and the offset used to select
3305 			 * the correct set of registers to access the
3306 			 * specified socket.  This allows basing everything
3307 			 * off the _0 window
3308 			 */
3309 
3310 			/* map the I/O base in */
3311 			pcic_putb(pcic, socket,
3312 			    PCIC_IO_ADDR_0_STARTLOW + select,
3313 			    LOW_BYTE((uint32_t)winp->pcw_base));
3314 			pcic_putb(pcic, socket,
3315 			    PCIC_IO_ADDR_0_STARTHI + select,
3316 			    HIGH_BYTE((uint32_t)winp->pcw_base));
3317 
3318 			pcic_putb(pcic, socket,
3319 			    PCIC_IO_ADDR_0_STOPLOW + select,
3320 			    LOW_BYTE((uint32_t)winp->pcw_base +
3321 			    window->WindowSize - 1));
3322 			pcic_putb(pcic, socket,
3323 			    PCIC_IO_ADDR_0_STOPHI + select,
3324 			    HIGH_BYTE((uint32_t)winp->pcw_base +
3325 			    window->WindowSize - 1));
3326 
3327 			/*
3328 			 * We've got the requested IO space, now see if we
3329 			 *	need to adjust the IO window offset registers
3330 			 *	so that the correct IO address is generated
3331 			 *	at the socket. If this window doesn't have
3332 			 *	this capability, then we're all done setting
3333 			 *	up the IO resources.
3334 			 */
3335 			if (pcic->pc_flags & PCF_IO_REMAP) {
3336 
3337 
3338 				/*
3339 				 * Note that only 16 bits are used to program
3340 				 * the registers but leave 32 bits on pcw_offset
3341 				 * so that we can generate the original base
3342 				 * in get_window()
3343 				 */
3344 				winp->pcw_offset = (base - winp->pcw_base);
3345 
3346 				pcic_putb(pcic, socket,
3347 				    PCIC_IO_OFFSET_LOW +
3348 				    (win * PCIC_IO_OFFSET_OFFSET),
3349 				    winp->pcw_offset & 0x0ff);
3350 				pcic_putb(pcic, socket,
3351 				    PCIC_IO_OFFSET_HI +
3352 				    (win * PCIC_IO_OFFSET_OFFSET),
3353 				    (winp->pcw_offset >> 8) & 0x0ff);
3354 
3355 			} /* PCF_IO_REMAP */
3356 
3357 			/* now get the other details (size, etc) right */
3358 
3359 			/*
3360 			 * Set the data size control bits here. Most of the
3361 			 *	adapters will ignore IOMEM_16BIT when
3362 			 *	IOMEM_IOCS16 is set, except for the Intel
3363 			 *	82092, which only pays attention to the
3364 			 *	IOMEM_16BIT bit. Sigh... Intel can't even
3365 			 *	make a proper clone of their own chip.
3366 			 * The 82092 also apparently can't set the timing
3367 			 *	of I/O windows.
3368 			 */
3369 			which = (window->state & WS_16BIT) ?
3370 			    (IOMEM_16BIT | IOMEM_IOCS16) : 0;
3371 
3372 			switch (pcic->pc_type) {
3373 			case PCIC_CL_PD6729:
3374 			case PCIC_CL_PD6730:
3375 			case PCIC_CL_PD6710:
3376 			case PCIC_CL_PD6722:
3377 			case PCIC_CL_PD6832:
3378 				/*
3379 				 * Select Timer Set 1 - this will take
3380 				 *	effect when the PCIC_IO_CONTROL
3381 				 *	register is written to later on;
3382 				 *	the call to pcic_set_cdtimers
3383 				 *	just sets up the timer itself.
3384 				 */
3385 				which |= IOMEM_CLTIMER_SET_1;
3386 				pcic_set_cdtimers(pcic, socket,
3387 				    window->speed,
3388 				    IOMEM_CLTIMER_SET_1);
3389 				which |= IOMEM_IOCS16;
3390 				break;
3391 			case PCIC_TI_PCI1031:
3392 
3393 				if (window->state & WS_16BIT)
3394 					which |= IOMEM_WAIT16;
3395 
3396 				break;
3397 			case PCIC_TI_PCI1130:
3398 
3399 				if (window->state & WS_16BIT)
3400 					which |= IOMEM_WAIT16;
3401 
3402 				break;
3403 			case PCIC_INTEL_i82092:
3404 				break;
3405 			default:
3406 				if (window->speed >
3407 				    mhztons(pcic->bus_speed) * 3)
3408 					which |= IOMEM_WAIT16;
3409 #ifdef notdef
3410 				if (window->speed <
3411 				    mhztons(pcic->bus_speed) * 6)
3412 					which |= IOMEM_ZERO_WAIT;
3413 #endif
3414 				break;
3415 			} /* switch (pc_type) */
3416 
3417 			/*
3418 			 * Setup the data width and timing
3419 			 */
3420 			select = pcic_getb(pcic, socket, PCIC_IO_CONTROL);
3421 			select &= ~(PCIC_IO_WIN_MASK << (win * 4));
3422 			select |= IOMEM_SETWIN(win, which);
3423 			pcic_putb(pcic, socket, PCIC_IO_CONTROL, select);
3424 
3425 			/*
3426 			 * Enable the IO window
3427 			 */
3428 			select = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE);
3429 			pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE,
3430 			    select | IOMEM_WINDOW(win));
3431 
3432 			winp->pcw_status |= PCW_ENABLED;
3433 
3434 #if defined(PCIC_DEBUG)
3435 			if (pcic_debug) {
3436 				cmn_err(CE_CONT,
3437 				    "\twhich = %x, select = %x (%x)\n",
3438 				    which, select,
3439 				    IOMEM_SETWIN(win, which));
3440 				xxdmp_all_regs(pcic, window->socket * 0x40, 24);
3441 			}
3442 #endif
3443 		} else {
3444 			/*
3445 			 * not only do we unmap the IO space, the
3446 			 * window has been turned off.
3447 			 */
3448 			if (winp->pcw_status & PCW_MAPPED) {
3449 				ddi_regs_map_free(&winp->pcw_handle);
3450 				res.ra_addr_lo = winp->pcw_base;
3451 				res.ra_len = winp->pcw_len;
3452 				(void) pcmcia_free_io(winp->res_dip, &res);
3453 				winp->pcw_status &= ~PCW_MAPPED;
3454 			}
3455 
3456 			/* disable current mapping */
3457 			select = pcic_getb(pcic, socket,
3458 			    PCIC_MAPPING_ENABLE);
3459 			pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE,
3460 			    select &= ~IOMEM_WINDOW(win));
3461 			winp->pcw_status &= ~PCW_ENABLED;
3462 
3463 			winp->pcw_base = 0;
3464 			winp->pcw_len = 0;
3465 			winp->pcw_offset = 0;
3466 			window->base = 0;
3467 			/* now make sure we don't accidentally re-enable */
3468 			/* find the register set offset */
3469 			select = win * PCIC_IO_OFFSET;
3470 			pcic_putb(pcic, socket,
3471 			    PCIC_IO_ADDR_0_STARTLOW + select, 0);
3472 			pcic_putb(pcic, socket,
3473 			    PCIC_IO_ADDR_0_STARTHI + select, 0);
3474 			pcic_putb(pcic, socket,
3475 			    PCIC_IO_ADDR_0_STOPLOW + select, 0);
3476 			pcic_putb(pcic, socket,
3477 			    PCIC_IO_ADDR_0_STOPHI + select, 0);
3478 		}
3479 	}
3480 	mutex_exit(&pcic->pc_lock);
3481 
3482 	return (SUCCESS);
3483 }
3484 
3485 /*
3486  * pcic_card_state()
3487  *	compute the instantaneous Card State information
3488  */
3489 static int
pcic_card_state(pcicdev_t * pcic,pcic_socket_t * sockp)3490 pcic_card_state(pcicdev_t *pcic, pcic_socket_t *sockp)
3491 {
3492 	int value, result;
3493 #if defined(PCIC_DEBUG)
3494 	int orig_value;
3495 #endif
3496 
3497 	mutex_enter(&pcic->pc_lock); /* protect the registers */
3498 
3499 	value = pcic_getb(pcic, sockp->pcs_socket, PCIC_INTERFACE_STATUS);
3500 
3501 #if defined(PCIC_DEBUG)
3502 	orig_value = value;
3503 	if (pcic_debug >= 8)
3504 		cmn_err(CE_CONT, "pcic_card_state(%p) if status = %b for %d\n",
3505 		    (void *)sockp,
3506 		    value,
3507 		    "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI",
3508 		    sockp->pcs_socket);
3509 #endif
3510 	/*
3511 	 * Lie to socket services if we are not ready.
3512 	 * This is when we are starting up or during debounce timeouts
3513 	 * or if the card is a cardbus card.
3514 	 */
3515 	if (!(sockp->pcs_flags & (PCS_STARTING|PCS_CARD_ISCARDBUS)) &&
3516 	    !sockp->pcs_debounce_id &&
3517 	    (value & PCIC_ISTAT_CD_MASK) == PCIC_CD_PRESENT_OK) {
3518 		result = SBM_CD;
3519 
3520 		if (value & PCIC_WRITE_PROTECT || !(value & PCIC_POWER_ON))
3521 			result |= SBM_WP;
3522 		if (value & PCIC_POWER_ON) {
3523 			if (value & PCIC_READY)
3524 				result |= SBM_RDYBSY;
3525 			value = (~value) & (PCIC_BVD1 | PCIC_BVD2);
3526 			if (value & PCIC_BVD1)
3527 				result |= SBM_BVD1;
3528 			if (value & PCIC_BVD2)
3529 				result |= SBM_BVD2;
3530 		}