1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #pragma ident	"%Z%%M%	%I%	%E% SMI"
27 
28 #include <sys/nxge/nxge_impl.h>
29 #include <sys/nxge/nxge_mac.h>
30 
31 static void nxge_get_niu_property(dev_info_t *, niu_type_t *);
32 static nxge_status_t nxge_get_mac_addr_properties(p_nxge_t);
33 static nxge_status_t nxge_use_cfg_n2niu_properties(p_nxge_t);
34 static void nxge_use_cfg_neptune_properties(p_nxge_t);
35 static void nxge_use_cfg_dma_config(p_nxge_t);
36 static void nxge_use_cfg_vlan_class_config(p_nxge_t);
37 static void nxge_use_cfg_mac_class_config(p_nxge_t);
38 static void nxge_use_cfg_class_config(p_nxge_t);
39 static void nxge_use_cfg_link_cfg(p_nxge_t);
40 static void nxge_set_hw_dma_config(p_nxge_t);
41 static void nxge_set_hw_vlan_class_config(p_nxge_t);
42 static void nxge_set_hw_mac_class_config(p_nxge_t);
43 static void nxge_set_hw_class_config(p_nxge_t);
44 static nxge_status_t nxge_use_default_dma_config_n2(p_nxge_t);
45 static void nxge_ldgv_setup(p_nxge_ldg_t *, p_nxge_ldv_t *, uint8_t,
46 	uint8_t, int *);
47 static void nxge_init_mmac(p_nxge_t, boolean_t);
48 
49 uint32_t nxge_use_hw_property = 1;
50 uint32_t nxge_groups_per_port = 2;
51 
52 extern uint32_t nxge_use_partition;
53 extern uint32_t nxge_dma_obp_props_only;
54 
55 extern uint16_t nxge_rcr_timeout;
56 extern uint16_t nxge_rcr_threshold;
57 
58 extern uint_t nxge_rx_intr(void *, void *);
59 extern uint_t nxge_tx_intr(void *, void *);
60 extern uint_t nxge_mif_intr(void *, void *);
61 extern uint_t nxge_mac_intr(void *, void *);
62 extern uint_t nxge_syserr_intr(void *, void *);
63 extern void *nxge_list;
64 
65 #define	NXGE_SHARED_REG_SW_SIM
66 
67 #ifdef NXGE_SHARED_REG_SW_SIM
68 uint64_t global_dev_ctrl = 0;
69 #endif
70 
71 #define	MAX_SIBLINGS	NXGE_MAX_PORTS
72 
73 extern uint32_t nxge_rbr_size;
74 extern uint32_t nxge_rcr_size;
75 extern uint32_t nxge_tx_ring_size;
76 extern uint32_t nxge_rbr_spare_size;
77 
78 extern npi_status_t npi_mac_altaddr_disable(npi_handle_t, uint8_t, uint8_t);
79 
80 static uint8_t p2_tx_fair[2] = {12, 12};
81 static uint8_t p2_tx_equal[2] = {12, 12};
82 static uint8_t p4_tx_fair[4] = {6, 6, 6, 6};
83 static uint8_t p4_tx_equal[4] = {6, 6, 6, 6};
84 static uint8_t p2_rx_fair[2] = {8, 8};
85 static uint8_t p2_rx_equal[2] = {8, 8};
86 static uint8_t p4_rx_fair[4] = {4, 4, 4, 4};
87 static uint8_t p4_rx_equal[4] = {4, 4, 4, 4};
88 
89 static uint8_t p2_rdcgrp_fair[2] = {4, 4};
90 static uint8_t p2_rdcgrp_equal[2] = {4, 4};
91 static uint8_t p4_rdcgrp_fair[4] = {2, 2, 1, 1};
92 static uint8_t p4_rdcgrp_equal[4] = {2, 2, 2, 2};
93 static uint8_t p2_rdcgrp_cls[2] = {1, 1};
94 static uint8_t p4_rdcgrp_cls[4] = {1, 1, 1, 1};
95 
96 static uint8_t rx_4_1G[4] = {4, 4, 4, 4};
97 static uint8_t rx_2_10G[2] = {8, 8};
98 static uint8_t rx_2_10G_2_1G[4] = {6, 6, 2, 2};
99 static uint8_t rx_1_10G_3_1G[4] = {10, 2, 2, 2};
100 static uint8_t rx_1_1G_1_10G_2_1G[4] = {2, 10, 2, 2};
101 
102 static uint8_t tx_4_1G[4] = {6, 6, 6, 6};
103 static uint8_t tx_2_10G[2] = {12, 12};
104 static uint8_t tx_2_10G_2_1G[4] = {10, 10, 2, 2};
105 static uint8_t tx_1_10G_3_1G[4] = {12, 4, 4, 4};
106 static uint8_t tx_1_1G_1_10G_2_1G[4] = {4, 12, 4, 4};
107 
108 typedef enum {
109 	DEFAULT = 0,
110 	EQUAL,
111 	FAIR,
112 	CUSTOM,
113 	CLASSIFY,
114 	L2_CLASSIFY,
115 	L3_DISTRIBUTE,
116 	L3_CLASSIFY,
117 	L3_TCAM,
118 	CONFIG_TOKEN_NONE
119 } config_token_t;
120 
121 static char *token_names[] = {
122 	"default",
123 	"equal",
124 	"fair",
125 	"custom",
126 	"classify",
127 	"l2_classify",
128 	"l3_distribute",
129 	"l3_classify",
130 	"l3_tcam",
131 	"none",
132 };
133 
134 void nxge_virint_regs_dump(p_nxge_t nxgep);
135 
136 void
137 nxge_virint_regs_dump(p_nxge_t nxgep)
138 {
139 	npi_handle_t handle;
140 
141 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_virint_regs_dump"));
142 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
143 	(void) npi_vir_dump_pio_fzc_regs_one(handle);
144 	(void) npi_vir_dump_ldgnum(handle);
145 	(void) npi_vir_dump_ldsv(handle);
146 	(void) npi_vir_dump_imask0(handle);
147 	(void) npi_vir_dump_sid(handle);
148 	(void) npi_mac_dump_regs(handle, nxgep->function_num);
149 	(void) npi_ipp_dump_regs(handle, nxgep->function_num);
150 	(void) npi_fflp_dump_regs(handle);
151 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_virint_regs_dump"));
152 }
153 
154 /*
155  * For now: we hard coded the DMA configurations.
156  *	    and assume for one partition only.
157  *
158  *       OBP. Then OBP will pass this partition's
159  *	 Neptune configurations to fcode to create
160  *	 properties for them.
161  *
162  *	Since Neptune(PCI-E) and NIU (Niagara-2) has
163  *	different bus interfaces, the driver needs
164  *	to know which bus it is connected to.
165  *  	Ravinder suggested: create a device property.
166  *	In partitioning environment, we cannot
167  *	use .conf file (need to check). If conf changes,
168  *	need to reboot the system.
169  *	The following function assumes that we will
170  *	retrieve its properties from a virtualized nexus driver.
171  */
172 
173 nxge_status_t
174 nxge_cntlops(dev_info_t *dip, nxge_ctl_enum_t ctlop, void *arg, void *result)
175 {
176 	nxge_status_t status = NXGE_OK;
177 	int instance;
178 	p_nxge_t nxgep;
179 
180 #ifndef NXGE_SHARED_REG_SW_SIM
181 	npi_handle_t handle;
182 	uint16_t sr16, cr16;
183 #endif
184 	instance = ddi_get_instance(dip);
185 	NXGE_DEBUG_MSG((NULL, VIR_CTL, "Instance %d ", instance));
186 
187 	if (nxge_list == NULL) {
188 		NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL,
189 				"nxge_cntlops: nxge_list null"));
190 		return (NXGE_ERROR);
191 	}
192 	nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance);
193 	if (nxgep == NULL) {
194 		NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL,
195 				"nxge_cntlops: nxgep null"));
196 		return (NXGE_ERROR);
197 	}
198 #ifndef NXGE_SHARED_REG_SW_SIM
199 	handle = nxgep->npi_reg_handle;
200 #endif
201 	switch (ctlop) {
202 	case NXGE_CTLOPS_NIUTYPE:
203 		nxge_get_niu_property(dip, (niu_type_t *)result);
204 		return (status);
205 
206 	case NXGE_CTLOPS_GET_SHARED_REG:
207 #ifdef NXGE_SHARED_REG_SW_SIM
208 		*(uint64_t *)result = global_dev_ctrl;
209 		return (0);
210 #else
211 		status = npi_dev_func_sr_sr_get(handle, &sr16);
212 		*(uint16_t *)result = sr16;
213 		NXGE_DEBUG_MSG((NULL, VIR_CTL,
214 			"nxge_cntlops: NXGE_CTLOPS_GET_SHARED_REG"));
215 		return (0);
216 #endif
217 
218 	case NXGE_CTLOPS_SET_SHARED_REG_LOCK:
219 #ifdef NXGE_SHARED_REG_SW_SIM
220 		global_dev_ctrl = *(uint64_t *)arg;
221 		return (0);
222 #else
223 		status = NPI_FAILURE;
224 		while (status != NPI_SUCCESS)
225 			status = npi_dev_func_sr_lock_enter(handle);
226 
227 		sr16 = *(uint16_t *)arg;
228 		status = npi_dev_func_sr_sr_set_only(handle, &sr16);
229 		status = npi_dev_func_sr_lock_free(handle);
230 		NXGE_DEBUG_MSG((NULL, VIR_CTL,
231 			"nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG"));
232 		return (0);
233 #endif
234 
235 	case NXGE_CTLOPS_UPDATE_SHARED_REG:
236 #ifdef NXGE_SHARED_REG_SW_SIM
237 		global_dev_ctrl |= *(uint64_t *)arg;
238 		return (0);
239 #else
240 		status = NPI_FAILURE;
241 		while (status != NPI_SUCCESS)
242 			status = npi_dev_func_sr_lock_enter(handle);
243 		status = npi_dev_func_sr_sr_get(handle, &sr16);
244 		sr16 |= *(uint16_t *)arg;
245 		status = npi_dev_func_sr_sr_set_only(handle, &sr16);
246 		status = npi_dev_func_sr_lock_free(handle);
247 		NXGE_DEBUG_MSG((NULL, VIR_CTL,
248 			"nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG"));
249 		return (0);
250 #endif
251 
252 	case NXGE_CTLOPS_CLEAR_BIT_SHARED_REG_UL:
253 #ifdef NXGE_SHARED_REG_SW_SIM
254 		global_dev_ctrl |= *(uint64_t *)arg;
255 		return (0);
256 #else
257 		status = npi_dev_func_sr_sr_get(handle, &sr16);
258 		cr16 = *(uint16_t *)arg;
259 		sr16 &= ~cr16;
260 		status = npi_dev_func_sr_sr_set_only(handle, &sr16);
261 		NXGE_DEBUG_MSG((NULL, VIR_CTL,
262 			"nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG"));
263 		return (0);
264 #endif
265 
266 	case NXGE_CTLOPS_CLEAR_BIT_SHARED_REG:
267 #ifdef NXGE_SHARED_REG_SW_SIM
268 		global_dev_ctrl |= *(uint64_t *)arg;
269 		return (0);
270 #else
271 		status = NPI_FAILURE;
272 		while (status != NPI_SUCCESS)
273 			status = npi_dev_func_sr_lock_enter(handle);
274 		status = npi_dev_func_sr_sr_get(handle, &sr16);
275 		cr16 = *(uint16_t *)arg;
276 		sr16 &= ~cr16;
277 		status = npi_dev_func_sr_sr_set_only(handle, &sr16);
278 		status = npi_dev_func_sr_lock_free(handle);
279 		NXGE_DEBUG_MSG((NULL, VIR_CTL,
280 			"nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG"));
281 		return (0);
282 #endif
283 
284 	case NXGE_CTLOPS_GET_LOCK_BLOCK:
285 #ifdef NXGE_SHARED_REG_SW_SIM
286 		global_dev_ctrl |= *(uint64_t *)arg;
287 		return (0);
288 #else
289 		status = NPI_FAILURE;
290 		while (status != NPI_SUCCESS)
291 			status = npi_dev_func_sr_lock_enter(handle);
292 		NXGE_DEBUG_MSG((NULL, VIR_CTL,
293 			"nxge_cntlops: NXGE_CTLOPS_GET_LOCK_BLOCK"));
294 		return (0);
295 #endif
296 	case NXGE_CTLOPS_GET_LOCK_TRY:
297 #ifdef NXGE_SHARED_REG_SW_SIM
298 		global_dev_ctrl |= *(uint64_t *)arg;
299 		return (0);
300 #else
301 		status = npi_dev_func_sr_lock_enter(handle);
302 		NXGE_DEBUG_MSG((NULL, VIR_CTL,
303 			"nxge_cntlops: NXGE_CTLOPS_GET_LOCK_TRY"));
304 		if (status == NPI_SUCCESS)
305 			return (NXGE_OK);
306 		else
307 			return (NXGE_ERROR);
308 #endif
309 	case NXGE_CTLOPS_FREE_LOCK:
310 #ifdef NXGE_SHARED_REG_SW_SIM
311 		global_dev_ctrl |= *(uint64_t *)arg;
312 		return (0);
313 #else
314 		status = npi_dev_func_sr_lock_free(handle);
315 		NXGE_DEBUG_MSG((NULL, VIR_CTL,
316 			"nxge_cntlops: NXGE_CTLOPS_GET_LOCK_FREE"));
317 		if (status == NPI_SUCCESS)
318 			return (NXGE_OK);
319 		else
320 			return (NXGE_ERROR);
321 #endif
322 
323 	default:
324 		status = NXGE_ERROR;
325 	}
326 
327 	return (status);
328 }
329 
330 void
331 nxge_common_lock_get(p_nxge_t nxgep)
332 {
333 	uint32_t status = NPI_FAILURE;
334 	npi_handle_t handle;
335 
336 #if	defined(NXGE_SHARE_REG_SW_SIM)
337 	return;
338 #endif
339 	handle = nxgep->npi_reg_handle;
340 	while (status != NPI_SUCCESS)
341 		status = npi_dev_func_sr_lock_enter(handle);
342 }
343 
344 void
345 nxge_common_lock_free(p_nxge_t nxgep)
346 {
347 	npi_handle_t handle;
348 
349 #if	defined(NXGE_SHARE_REG_SW_SIM)
350 	return;
351 #endif
352 	handle = nxgep->npi_reg_handle;
353 	(void) npi_dev_func_sr_lock_free(handle);
354 }
355 
356 
357 static void
358 nxge_get_niu_property(dev_info_t *dip, niu_type_t *niu_type)
359 {
360 	uchar_t *prop_val;
361 	uint_t prop_len;
362 
363 	*niu_type = NIU_TYPE_NONE;
364 	if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0,
365 			"niu-type", (uchar_t **)&prop_val,
366 			&prop_len) == DDI_PROP_SUCCESS) {
367 		if (strncmp("niu", (caddr_t)prop_val, (size_t)prop_len) == 0) {
368 			*niu_type = N2_NIU;
369 		}
370 		ddi_prop_free(prop_val);
371 	}
372 }
373 
374 static config_token_t
375 nxge_get_config_token(char *prop)
376 {
377 	config_token_t token = DEFAULT;
378 
379 	while (token < CONFIG_TOKEN_NONE) {
380 		if (strncmp(prop, token_names[token], 4) == 0)
381 			break;
382 		token++;
383 	}
384 	return (token);
385 }
386 
387 /* per port */
388 
389 static nxge_status_t
390 nxge_update_rxdma_grp_properties(p_nxge_t nxgep, config_token_t token,
391 	dev_info_t *s_dip[])
392 {
393 	nxge_status_t status = NXGE_OK;
394 	int ddi_status;
395 	int num_ports = nxgep->nports;
396 	int port, bits, j;
397 	uint8_t start_grp = 0, num_grps = 0;
398 	p_nxge_param_t param_arr;
399 	uint32_t grp_bitmap[MAX_SIBLINGS];
400 	int custom_start_grp[MAX_SIBLINGS];
401 	int custom_num_grp[MAX_SIBLINGS];
402 	uint8_t bad_config = B_FALSE;
403 	char *start_prop, *num_prop, *cfg_prop;
404 
405 	start_grp = 0;
406 	param_arr = nxgep->param_arr;
407 	start_prop = param_arr[param_rdc_grps_start].fcode_name;
408 	num_prop = param_arr[param_rx_rdc_grps].fcode_name;
409 
410 	switch (token) {
411 	case FAIR:
412 		cfg_prop = "fair";
413 		for (port = 0; port < num_ports; port++) {
414 			custom_num_grp[port] =
415 				(num_ports == 4) ?
416 				p4_rdcgrp_fair[port] :
417 				p2_rdcgrp_fair[port];
418 			custom_start_grp[port] = start_grp;
419 			start_grp += custom_num_grp[port];
420 		}
421 		break;
422 
423 	case EQUAL:
424 		cfg_prop = "equal";
425 		for (port = 0; port < num_ports; port++) {
426 			custom_num_grp[port] =
427 				(num_ports == 4) ?
428 				p4_rdcgrp_equal[port] :
429 				p2_rdcgrp_equal[port];
430 			custom_start_grp[port] = start_grp;
431 			start_grp += custom_num_grp[port];
432 		}
433 		break;
434 
435 
436 	case CLASSIFY:
437 		cfg_prop = "classify";
438 		for (port = 0; port < num_ports; port++) {
439 			custom_num_grp[port] = (num_ports == 4) ?
440 				p4_rdcgrp_cls[port] : p2_rdcgrp_cls[port];
441 			custom_start_grp[port] = start_grp;
442 			start_grp += custom_num_grp[port];
443 		}
444 		break;
445 
446 	case CUSTOM:
447 		cfg_prop = "custom";
448 		/* See if it is good config */
449 		num_grps = 0;
450 		for (port = 0; port < num_ports; port++) {
451 			custom_start_grp[port] =
452 				ddi_prop_get_int(DDI_DEV_T_NONE, s_dip[port],
453 				DDI_PROP_DONTPASS, start_prop, -1);
454 			if ((custom_start_grp[port] == -1) ||
455 				(custom_start_grp[port] >=
456 					NXGE_MAX_RDC_GRPS)) {
457 				bad_config = B_TRUE;
458 				break;
459 			}
460 			custom_num_grp[port] = ddi_prop_get_int(
461 				DDI_DEV_T_NONE,
462 				s_dip[port],
463 				DDI_PROP_DONTPASS,
464 				num_prop, -1);
465 
466 			if ((custom_num_grp[port] == -1) ||
467 				(custom_num_grp[port] >
468 					NXGE_MAX_RDC_GRPS) ||
469 				((custom_num_grp[port] +
470 						custom_start_grp[port]) >=
471 					NXGE_MAX_RDC_GRPS)) {
472 				bad_config = B_TRUE;
473 				break;
474 			}
475 			num_grps += custom_num_grp[port];
476 			if (num_grps > NXGE_MAX_RDC_GRPS) {
477 				bad_config = B_TRUE;
478 				break;
479 			}
480 			grp_bitmap[port] = 0;
481 			for (bits = 0;
482 				bits < custom_num_grp[port];
483 				bits++) {
484 				grp_bitmap[port] |=
485 					(1 << (bits + custom_start_grp[port]));
486 			}
487 
488 		}
489 
490 		if (bad_config == B_FALSE) {
491 			/* check for overlap */
492 			for (port = 0; port < num_ports - 1; port++) {
493 				for (j = port + 1; j < num_ports; j++) {
494 					if (grp_bitmap[port] &
495 						grp_bitmap[j]) {
496 						bad_config = B_TRUE;
497 						break;
498 					}
499 				}
500 				if (bad_config == B_TRUE)
501 					break;
502 			}
503 		}
504 		if (bad_config == B_TRUE) {
505 			/* use default config */
506 			for (port = 0; port < num_ports; port++) {
507 				custom_num_grp[port] =
508 					(num_ports == 4) ?
509 					p4_rx_fair[port] : p2_rx_fair[port];
510 				custom_start_grp[port] = start_grp;
511 				start_grp += custom_num_grp[port];
512 			}
513 		}
514 		break;
515 
516 	default:
517 		/* use default config */
518 		cfg_prop = "fair";
519 		for (port = 0; port < num_ports; port++) {
520 			custom_num_grp[port] = (num_ports == 4) ?
521 				p4_rx_fair[port] : p2_rx_fair[port];
522 			custom_start_grp[port] = start_grp;
523 			start_grp += custom_num_grp[port];
524 		}
525 		break;
526 	}
527 
528 	/* Now Update the rx properties */
529 	for (port = 0; port < num_ports; port++) {
530 		ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port],
531 			"rxdma-grp-cfg", cfg_prop);
532 		if (ddi_status != DDI_PROP_SUCCESS) {
533 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
534 					" property %s not updating",
535 					cfg_prop));
536 			status |= NXGE_DDI_FAILED;
537 		}
538 		ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
539 			num_prop, custom_num_grp[port]);
540 
541 		if (ddi_status != DDI_PROP_SUCCESS) {
542 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
543 					" property %s not updating",
544 					num_prop));
545 			status |= NXGE_DDI_FAILED;
546 		}
547 		ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
548 			start_prop, custom_start_grp[port]);
549 
550 		if (ddi_status != DDI_PROP_SUCCESS) {
551 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
552 					" property %s not updating",
553 					start_prop));
554 			status |= NXGE_DDI_FAILED;
555 		}
556 	}
557 	if (status & NXGE_DDI_FAILED)
558 		status |= NXGE_ERROR;
559 
560 	return (status);
561 }
562 
563 static nxge_status_t
564 nxge_update_rxdma_properties(p_nxge_t nxgep, config_token_t token,
565 	dev_info_t *s_dip[])
566 {
567 	nxge_status_t status = NXGE_OK;
568 	int ddi_status;
569 	int num_ports = nxgep->nports;
570 	int port, bits, j;
571 	uint8_t start_rdc = 0, num_rdc = 0;
572 	p_nxge_param_t param_arr;
573 	uint32_t rdc_bitmap[MAX_SIBLINGS];
574 	int custom_start_rdc[MAX_SIBLINGS];
575 	int custom_num_rdc[MAX_SIBLINGS];
576 	uint8_t bad_config = B_FALSE;
577 	int *prop_val;
578 	uint_t prop_len;
579 	char *start_rdc_prop, *num_rdc_prop, *cfg_prop;
580 
581 	start_rdc = 0;
582 	param_arr = nxgep->param_arr;
583 	start_rdc_prop = param_arr[param_rxdma_channels_begin].fcode_name;
584 	num_rdc_prop = param_arr[param_rxdma_channels].fcode_name;
585 
586 	switch (token) {
587 	case FAIR:
588 		cfg_prop = "fair";
589 		for (port = 0; port < num_ports; port++) {
590 			custom_num_rdc[port] = (num_ports == 4) ?
591 				p4_rx_fair[port] : p2_rx_fair[port];
592 			custom_start_rdc[port] = start_rdc;
593 			start_rdc += custom_num_rdc[port];
594 		}
595 		break;
596 
597 	case EQUAL:
598 		cfg_prop = "equal";
599 		for (port = 0; port < num_ports; port++) {
600 			custom_num_rdc[port] = (num_ports == 4) ?
601 				p4_rx_equal[port] :
602 				p2_rx_equal[port];
603 			custom_start_rdc[port] = start_rdc;
604 			start_rdc += custom_num_rdc[port];
605 		}
606 		break;
607 
608 	case CUSTOM:
609 		cfg_prop = "custom";
610 		/* See if it is good config */
611 		num_rdc = 0;
612 		for (port = 0; port < num_ports; port++) {
613 			ddi_status = ddi_prop_lookup_int_array(
614 				DDI_DEV_T_ANY,
615 				s_dip[port], 0,
616 				start_rdc_prop,
617 				&prop_val,
618 				&prop_len);
619 			if (ddi_status == DDI_SUCCESS)
620 				custom_start_rdc[port] = *prop_val;
621 			else {
622 				NXGE_DEBUG_MSG((nxgep, CFG_CTL,
623 						" %s custom start port %d"
624 						" read failed ",
625 						" rxdma-cfg", port));
626 				bad_config = B_TRUE;
627 				status |= NXGE_DDI_FAILED;
628 			}
629 			if ((custom_start_rdc[port] == -1) ||
630 				(custom_start_rdc[port] >=
631 					NXGE_MAX_RDCS)) {
632 				NXGE_DEBUG_MSG((nxgep, CFG_CTL,
633 						" %s custom start %d"
634 						" out of range %x ",
635 						" rxdma-cfg",
636 						port,
637 						custom_start_rdc[port]));
638 				bad_config = B_TRUE;
639 				break;
640 			}
641 			ddi_status = ddi_prop_lookup_int_array(
642 				DDI_DEV_T_ANY,
643 				s_dip[port],
644 				0,
645 				num_rdc_prop,
646 				&prop_val,
647 				&prop_len);
648 
649 			if (ddi_status == DDI_SUCCESS)
650 				custom_num_rdc[port] = *prop_val;
651 			else {
652 				NXGE_DEBUG_MSG((nxgep, CFG_CTL,
653 					" %s custom num port %d"
654 					" read failed ",
655 					"rxdma-cfg", port));
656 				bad_config = B_TRUE;
657 				status |= NXGE_DDI_FAILED;
658 			}
659 
660 			if ((custom_num_rdc[port] == -1) ||
661 					(custom_num_rdc[port] >
662 						NXGE_MAX_RDCS) ||
663 					((custom_num_rdc[port] +
664 						custom_start_rdc[port]) >
665 					NXGE_MAX_RDCS)) {
666 				NXGE_DEBUG_MSG((nxgep, CFG_CTL,
667 					" %s custom num %d"
668 					" out of range %x ",
669 					" rxdma-cfg",
670 					port, custom_num_rdc[port]));
671 				bad_config = B_TRUE;
672 				break;
673 			}
674 			num_rdc += custom_num_rdc[port];
675 			if (num_rdc > NXGE_MAX_RDCS) {
676 				bad_config = B_TRUE;
677 				break;
678 			}
679 			rdc_bitmap[port] = 0;
680 			for (bits = 0;
681 				bits < custom_num_rdc[port]; bits++) {
682 				rdc_bitmap[port] |=
683 					(1 << (bits + custom_start_rdc[port]));
684 			}
685 		}
686 
687 		if (bad_config == B_FALSE) {
688 			/* check for overlap */
689 			for (port = 0; port < num_ports - 1; port++) {
690 				for (j = port + 1; j < num_ports; j++) {
691 					if (rdc_bitmap[port] &
692 						rdc_bitmap[j]) {
693 						NXGE_DEBUG_MSG((nxgep,
694 							CFG_CTL,
695 							" rxdma-cfg"
696 							" property custom"
697 							" bit overlap"
698 							" %d %d ",
699 							port, j));
700 						bad_config = B_TRUE;
701 						break;
702 					}
703 				}
704 				if (bad_config == B_TRUE)
705 					break;
706 			}
707 		}
708 		if (bad_config == B_TRUE) {
709 			/* use default config */
710 			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
711 				" rxdma-cfg property:"
712 				" bad custom config:"
713 				" use default"));
714 			for (port = 0; port < num_ports; port++) {
715 				custom_num_rdc[port] =
716 					(num_ports == 4) ?
717 					p4_rx_fair[port] :
718 					p2_rx_fair[port];
719 				custom_start_rdc[port] = start_rdc;
720 				start_rdc += custom_num_rdc[port];
721 			}
722 		}
723 		break;
724 
725 	default:
726 		/* use default config */
727 		cfg_prop = "fair";
728 		for (port = 0; port < num_ports; port++) {
729 			custom_num_rdc[port] = (num_ports == 4) ?
730 				p4_rx_fair[port] : p2_rx_fair[port];
731 			custom_start_rdc[port] = start_rdc;
732 			start_rdc += custom_num_rdc[port];
733 		}
734 		break;
735 	}
736 
737 	/* Now Update the rx properties */
738 	for (port = 0; port < num_ports; port++) {
739 		NXGE_DEBUG_MSG((nxgep, CFG_CTL,
740 			" update property rxdma-cfg with %s ", cfg_prop));
741 		ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port],
742 			"rxdma-cfg", cfg_prop);
743 		if (ddi_status != DDI_PROP_SUCCESS) {
744 			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
745 				" property rxdma-cfg is not updating to %s",
746 				cfg_prop));
747 			status |= NXGE_DDI_FAILED;
748 		}
749 		NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
750 			num_rdc_prop, custom_num_rdc[port]));
751 
752 		ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
753 			num_rdc_prop, custom_num_rdc[port]);
754 
755 		if (ddi_status != DDI_PROP_SUCCESS) {
756 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
757 				" property %s not updating with %d",
758 				num_rdc_prop, custom_num_rdc[port]));
759 			status |= NXGE_DDI_FAILED;
760 		}
761 		NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
762 			start_rdc_prop, custom_start_rdc[port]));
763 		ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
764 			start_rdc_prop, custom_start_rdc[port]);
765 
766 		if (ddi_status != DDI_PROP_SUCCESS) {
767 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
768 				" property %s not updating with %d ",
769 				start_rdc_prop, custom_start_rdc[port]));
770 			status |= NXGE_DDI_FAILED;
771 		}
772 	}
773 	if (status & NXGE_DDI_FAILED)
774 		status |= NXGE_ERROR;
775 	return (status);
776 }
777 
778 static nxge_status_t
779 nxge_update_txdma_properties(p_nxge_t nxgep, config_token_t token,
780 	dev_info_t *s_dip[])
781 {
782 	nxge_status_t status = NXGE_OK;
783 	int ddi_status = DDI_SUCCESS;
784 	int num_ports = nxgep->nports;
785 	int port, bits, j;
786 	uint8_t start_tdc = 0, num_tdc = 0;
787 	p_nxge_param_t param_arr;
788 	uint32_t tdc_bitmap[MAX_SIBLINGS];
789 	int custom_start_tdc[MAX_SIBLINGS];
790 	int custom_num_tdc[MAX_SIBLINGS];
791 	uint8_t bad_config = B_FALSE;
792 	int *prop_val;
793 	uint_t prop_len;
794 	char *start_tdc_prop, *num_tdc_prop, *cfg_prop;
795 
796 	start_tdc = 0;
797 	param_arr = nxgep->param_arr;
798 	start_tdc_prop = param_arr[param_txdma_channels_begin].fcode_name;
799 	num_tdc_prop = param_arr[param_txdma_channels].fcode_name;
800 
801 	switch (token) {
802 	case FAIR:
803 		cfg_prop = "fair";
804 		for (port = 0; port < num_ports; port++) {
805 			custom_num_tdc[port] = (num_ports == 4) ?
806 				p4_tx_fair[port] : p2_tx_fair[port];
807 			custom_start_tdc[port] = start_tdc;
808 			start_tdc += custom_num_tdc[port];
809 		}
810 		break;
811 
812 	case EQUAL:
813 		cfg_prop = "equal";
814 		for (port = 0; port < num_ports; port++) {
815 			custom_num_tdc[port] = (num_ports == 4) ?
816 				p4_tx_equal[port] : p2_tx_equal[port];
817 			custom_start_tdc[port] = start_tdc;
818 			start_tdc += custom_num_tdc[port];
819 		}
820 		break;
821 
822 	case CUSTOM:
823 		cfg_prop = "custom";
824 		/* See if it is good config */
825 		num_tdc = 0;
826 		for (port = 0; port < num_ports; port++) {
827 			ddi_status = ddi_prop_lookup_int_array(
828 				DDI_DEV_T_ANY, s_dip[port], 0, start_tdc_prop,
829 				&prop_val, &prop_len);
830 			if (ddi_status == DDI_SUCCESS)
831 				custom_start_tdc[port] = *prop_val;
832 			else {
833 				NXGE_DEBUG_MSG((nxgep, CFG_CTL,
834 					" %s custom start port %d"
835 					" read failed ", " txdma-cfg", port));
836 				bad_config = B_TRUE;
837 				status |= NXGE_DDI_FAILED;
838 			}
839 
840 			if ((custom_start_tdc[port] == -1) ||
841 					(custom_start_tdc[port] >=
842 					NXGE_MAX_RDCS)) {
843 				NXGE_DEBUG_MSG((nxgep, CFG_CTL,
844 					" %s custom start %d"
845 					" out of range %x ", " txdma-cfg",
846 					port, custom_start_tdc[port]));
847 				bad_config = B_TRUE;
848 				break;
849 			}
850 
851 			ddi_status = ddi_prop_lookup_int_array(
852 				DDI_DEV_T_ANY, s_dip[port], 0, num_tdc_prop,
853 				&prop_val, &prop_len);
854 			if (ddi_status == DDI_SUCCESS)
855 				custom_num_tdc[port] = *prop_val;
856 			else {
857 				NXGE_DEBUG_MSG((nxgep, CFG_CTL,
858 					" %s custom num port %d"
859 					" read failed ", " txdma-cfg", port));
860 				bad_config = B_TRUE;
861 				status |= NXGE_DDI_FAILED;
862 			}
863 
864 			if ((custom_num_tdc[port] == -1) ||
865 					(custom_num_tdc[port] >
866 						NXGE_MAX_TDCS) ||
867 					((custom_num_tdc[port] +
868 						custom_start_tdc[port]) >
869 					NXGE_MAX_TDCS)) {
870 				NXGE_DEBUG_MSG((nxgep, CFG_CTL,
871 					" %s custom num %d"
872 					" out of range %x ", " rxdma-cfg",
873 					port, custom_num_tdc[port]));
874 				bad_config = B_TRUE;
875 				break;
876 			}
877 			num_tdc += custom_num_tdc[port];
878 			if (num_tdc > NXGE_MAX_TDCS) {
879 				bad_config = B_TRUE;
880 				break;
881 			}
882 			tdc_bitmap[port] = 0;
883 			for (bits = 0;
884 				bits < custom_num_tdc[port]; bits++) {
885 				tdc_bitmap[port] |=
886 					(1 <<
887 					(bits + custom_start_tdc[port]));
888 			}
889 
890 		}
891 
892 		if (bad_config == B_FALSE) {
893 			/* check for overlap */
894 			for (port = 0; port < num_ports - 1; port++) {
895 				for (j = port + 1; j < num_ports; j++) {
896 					if (tdc_bitmap[port] &
897 						tdc_bitmap[j]) {
898 						NXGE_DEBUG_MSG((nxgep, CFG_CTL,
899 							" rxdma-cfg"
900 							" property custom"
901 							" bit overlap"
902 							" %d %d ",
903 							port, j));
904 						bad_config = B_TRUE;
905 						break;
906 					}
907 				}
908 				if (bad_config == B_TRUE)
909 					break;
910 			}
911 		}
912 		if (bad_config == B_TRUE) {
913 			/* use default config */
914 			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
915 				" txdma-cfg property:"
916 				" bad custom config:" " use default"));
917 
918 			for (port = 0; port < num_ports; port++) {
919 				custom_num_tdc[port] = (num_ports == 4) ?
920 					p4_tx_fair[port] : p2_tx_fair[port];
921 				custom_start_tdc[port] = start_tdc;
922 				start_tdc += custom_num_tdc[port];
923 			}
924 		}
925 		break;
926 
927 	default:
928 		/* use default config */
929 		cfg_prop = "fair";
930 		for (port = 0; port < num_ports; port++) {
931 			custom_num_tdc[port] = (num_ports == 4) ?
932 				p4_tx_fair[port] : p2_tx_fair[port];
933 			custom_start_tdc[port] = start_tdc;
934 			start_tdc += custom_num_tdc[port];
935 		}
936 		break;
937 	}
938 
939 	/* Now Update the tx properties */
940 	for (port = 0; port < num_ports; port++) {
941 		NXGE_DEBUG_MSG((nxgep, CFG_CTL,
942 			" update property txdma-cfg with %s ", cfg_prop));
943 		ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port],
944 			"txdma-cfg", cfg_prop);
945 		if (ddi_status != DDI_PROP_SUCCESS) {
946 			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
947 				" property txdma-cfg is not updating to %s",
948 				cfg_prop));
949 			status |= NXGE_DDI_FAILED;
950 		}
951 		NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
952 			num_tdc_prop, custom_num_tdc[port]));
953 
954 		ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
955 			num_tdc_prop, custom_num_tdc[port]);
956 
957 		if (ddi_status != DDI_PROP_SUCCESS) {
958 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
959 				" property %s not updating with %d",
960 				num_tdc_prop,
961 				custom_num_tdc[port]));
962 			status |= NXGE_DDI_FAILED;
963 		}
964 
965 		NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
966 			start_tdc_prop, custom_start_tdc[port]));
967 
968 		ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
969 			start_tdc_prop, custom_start_tdc[port]);
970 		if (ddi_status != DDI_PROP_SUCCESS) {
971 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
972 				" property %s not updating with %d ",
973 				start_tdc_prop, custom_start_tdc[port]));
974 			status |= NXGE_DDI_FAILED;
975 		}
976 	}
977 	if (status & NXGE_DDI_FAILED)
978 		status |= NXGE_ERROR;
979 	return (status);
980 }
981 
982 static nxge_status_t
983 nxge_update_cfg_properties(p_nxge_t nxgep, uint32_t flags,
984 	config_token_t token, dev_info_t *s_dip[])
985 {
986 	nxge_status_t status = NXGE_OK;
987 
988 	switch (flags) {
989 	case COMMON_TXDMA_CFG:
990 		if (nxge_dma_obp_props_only == 0)
991 			status = nxge_update_txdma_properties(nxgep,
992 				token, s_dip);
993 		break;
994 	case COMMON_RXDMA_CFG:
995 		if (nxge_dma_obp_props_only == 0)
996 			status = nxge_update_rxdma_properties(nxgep,
997 				token, s_dip);
998 
999 		break;
1000 	case COMMON_RXDMA_GRP_CFG:
1001 		status = nxge_update_rxdma_grp_properties(nxgep,
1002 			token, s_dip);
1003 		break;
1004 	default:
1005 		return (NXGE_ERROR);
1006 	}
1007 	return (status);
1008 }
1009 
1010 /*
1011  * verify consistence.
1012  * (May require publishing the properties on all the ports.
1013  *
1014  * What if properties are published on function 0 device only?
1015  *
1016  *
1017  * rxdma-cfg, txdma-cfg, rxdma-grp-cfg (required )
1018  * What about class configs?
1019  *
1020  * If consistent, update the property on all the siblings.
1021  * set  a flag on hardware shared register
1022  * The rest of the siblings will check the flag
1023  * if the flag is set, they will use the updated property
1024  * without doing any validation.
1025  */
1026 
1027 nxge_status_t
1028 nxge_cfg_verify_set_classify_prop(p_nxge_t nxgep, char *prop,
1029 	uint64_t known_cfg, uint32_t override, dev_info_t *c_dip[])
1030 {
1031 	nxge_status_t status = NXGE_OK;
1032 	int ddi_status = DDI_SUCCESS;
1033 	int i = 0, found = 0, update_prop = B_TRUE;
1034 	int *cfg_val;
1035 	uint_t new_value, cfg_value[MAX_SIBLINGS];
1036 	uint_t prop_len;
1037 	uint_t known_cfg_value;
1038 
1039 	known_cfg_value = (uint_t)known_cfg;
1040 
1041 	if (override == B_TRUE) {
1042 		new_value = known_cfg_value;
1043 		for (i = 0; i < nxgep->nports; i++) {
1044 			ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE,
1045 				c_dip[i], prop, new_value);
1046 #ifdef NXGE_DEBUG_ERROR
1047 			if (ddi_status != DDI_PROP_SUCCESS)
1048 				NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1049 					" property %s failed update ", prop));
1050 #endif
1051 		}
1052 		if (ddi_status != DDI_PROP_SUCCESS)
1053 			return (NXGE_ERROR | NXGE_DDI_FAILED);
1054 	}
1055 	for (i = 0; i < nxgep->nports; i++) {
1056 		cfg_value[i] = known_cfg_value;
1057 		if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, c_dip[i], 0,
1058 				prop, &cfg_val,
1059 				&prop_len) == DDI_PROP_SUCCESS) {
1060 			cfg_value[i] = *cfg_val;
1061 			ddi_prop_free(cfg_val);
1062 			found++;
1063 		}
1064 	}
1065 
1066 	if (found != i) {
1067 		NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1068 			" property %s not specified on all ports", prop));
1069 		if (found == 0) {
1070 			/* not specified: Use default */
1071 			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1072 				" property %s not specified on any port:"
1073 				" Using default", prop));
1074 			new_value = known_cfg_value;
1075 		} else {
1076 			/* specified on some */
1077 			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1078 				" property %s not specified"
1079 				" on some ports: Using default", prop));
1080 			/* ? use p0 value instead ? */
1081 			new_value = known_cfg_value;
1082 		}
1083 	} else {
1084 		/* check type and consistence */
1085 		/* found on all devices */
1086 		for (i = 1; i < found; i++) {
1087 			if (cfg_value[i] != cfg_value[i - 1]) {
1088 				NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1089 					" property %s inconsistent:"
1090 					" Using default", prop));
1091 				new_value = known_cfg_value;
1092 				break;
1093 			}
1094 			/*
1095 			 * Found on all the ports and consistent. Nothing to
1096 			 * do.
1097 			 */
1098 			update_prop = B_FALSE;
1099 		}
1100 	}
1101 
1102 	if (update_prop == B_TRUE) {
1103 		for (i = 0; i < nxgep->nports; i++) {
1104 			ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE,
1105 				c_dip[i], prop, new_value);
1106 #ifdef NXGE_DEBUG_ERROR
1107 			if (ddi_status != DDI_SUCCESS)
1108 				NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1109 					" property %s not updating with %d"
1110 					" Using default",
1111 					prop, new_value));
1112 #endif
1113 			if (ddi_status != DDI_PROP_SUCCESS)
1114 				status |= NXGE_DDI_FAILED;
1115 		}
1116 	}
1117 	if (status & NXGE_DDI_FAILED)
1118 		status |= NXGE_ERROR;
1119 
1120 	return (status);
1121 }
1122 
1123 static uint64_t
1124 nxge_class_get_known_cfg(p_nxge_t nxgep, int class_prop, int rx_quick_cfg)
1125 {
1126 	int start_prop;
1127 	uint64_t cfg_value;
1128 	p_nxge_param_t param_arr;
1129 
1130 	param_arr = nxgep->param_arr;
1131 	cfg_value = param_arr[class_prop].value;
1132 	start_prop = param_h1_init_value;
1133 
1134 	/* update the properties per quick config */
1135 	switch (rx_quick_cfg) {
1136 	case CFG_L3_WEB:
1137 	case CFG_L3_DISTRIBUTE:
1138 		cfg_value = nxge_classify_get_cfg_value(nxgep,
1139 			rx_quick_cfg, class_prop - start_prop);
1140 		break;
1141 	default:
1142 		cfg_value = param_arr[class_prop].value;
1143 		break;
1144 	}
1145 	return (cfg_value);
1146 }
1147 
1148 static nxge_status_t
1149 nxge_cfg_verify_set_classify(p_nxge_t nxgep, dev_info_t *c_dip[])
1150 {
1151 	nxge_status_t status = NXGE_OK;
1152 	int rx_quick_cfg, class_prop, start_prop, end_prop;
1153 	char *prop_name;
1154 	int override = B_TRUE;
1155 	uint64_t cfg_value;
1156 	p_nxge_param_t param_arr;
1157 
1158 	param_arr = nxgep->param_arr;
1159 	rx_quick_cfg = param_arr[param_rx_quick_cfg].value;
1160 	start_prop = param_h1_init_value;
1161 	end_prop = param_class_opt_ipv6_sctp;
1162 
1163 	/* update the properties per quick config */
1164 	if (rx_quick_cfg == CFG_NOT_SPECIFIED)
1165 		override = B_FALSE;
1166 
1167 	/*
1168 	 * these parameter affect the classification outcome.
1169 	 * these parameters are used to configure the Flow key and
1170 	 * the TCAM key for each of the IP classes.
1171 	 * Included here are also the H1 and H2 initial values
1172 	 * which affect the distribution as well as final hash value
1173 	 * (hence the offset into RDC table and FCRAM bucket location)
1174 	 *
1175 	 */
1176 	for (class_prop = start_prop; class_prop <= end_prop; class_prop++) {
1177 		prop_name = param_arr[class_prop].fcode_name;
1178 		cfg_value = nxge_class_get_known_cfg(nxgep,
1179 			class_prop, rx_quick_cfg);
1180 		status = nxge_cfg_verify_set_classify_prop(nxgep, prop_name,
1181 			cfg_value, override, c_dip);
1182 	}
1183 
1184 	/*
1185 	 * these properties do not affect the actual classification outcome.
1186 	 * used to enable/disable or tune the fflp hardware
1187 	 *
1188 	 * fcram_access_ratio, tcam_access_ratio, tcam_enable, llc_snap_enable
1189 	 *
1190 	 */
1191 	override = B_FALSE;
1192 	for (class_prop = param_fcram_access_ratio;
1193 			class_prop <= param_llc_snap_enable; class_prop++) {
1194 		prop_name = param_arr[class_prop].fcode_name;
1195 		cfg_value = param_arr[class_prop].value;
1196 		status = nxge_cfg_verify_set_classify_prop(nxgep, prop_name,
1197 			cfg_value, override, c_dip);
1198 	}
1199 
1200 	return (status);
1201 }
1202 
1203 nxge_status_t
1204 nxge_cfg_verify_set(p_nxge_t nxgep, uint32_t flag)
1205 {
1206 	nxge_status_t status = NXGE_OK;
1207 	int i = 0, found = 0;
1208 	int num_siblings;
1209 	dev_info_t *c_dip[MAX_SIBLINGS + 1];
1210 	char *prop_val[MAX_SIBLINGS];
1211 	config_token_t c_token[MAX_SIBLINGS];
1212 	char *prop;
1213 
1214 	if (nxge_dma_obp_props_only)
1215 		return (NXGE_OK);
1216 
1217 	num_siblings = 0;
1218 	c_dip[num_siblings] = ddi_get_child(nxgep->p_dip);
1219 	while (c_dip[num_siblings]) {
1220 		c_dip[num_siblings + 1] =
1221 			ddi_get_next_sibling(c_dip[num_siblings]);
1222 		num_siblings++;
1223 	}
1224 
1225 	switch (flag) {
1226 	case COMMON_TXDMA_CFG:
1227 		prop = "txdma-cfg";
1228 		break;
1229 	case COMMON_RXDMA_CFG:
1230 		prop = "rxdma-cfg";
1231 		break;
1232 	case COMMON_RXDMA_GRP_CFG:
1233 		prop = "rxdma-grp-cfg";
1234 		break;
1235 	case COMMON_CLASS_CFG:
1236 		status = nxge_cfg_verify_set_classify(nxgep, c_dip);
1237 		return (status);
1238 	default:
1239 		return (NXGE_ERROR);
1240 	}
1241 
1242 	i = 0;
1243 	while (i < num_siblings) {
1244 		if (ddi_prop_lookup_string(DDI_DEV_T_ANY, c_dip[i], 0, prop,
1245 				(char **)&prop_val[i]) == DDI_PROP_SUCCESS) {
1246 			c_token[i] = nxge_get_config_token(prop_val[i]);
1247 			ddi_prop_free(prop_val[i]);
1248 			found++;
1249 		} else
1250 			c_token[i] = CONFIG_TOKEN_NONE;
1251 		i++;
1252 	}
1253 
1254 	if (found != i) {
1255 		if (found == 0) {
1256 			/* not specified: Use default */
1257 			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1258 				" property %s not specified on any port:"
1259 					" Using default", prop));
1260 
1261 			status = nxge_update_cfg_properties(nxgep,
1262 				flag, FAIR, c_dip);
1263 			return (status);
1264 		} else {
1265 			/*
1266 			 * if  the convention is to use function 0 device then
1267 			 * populate the other devices with this configuration.
1268 			 *
1269 			 * The other alternative is to use the default config.
1270 			 */
1271 			/* not specified: Use default */
1272 			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1273 				" property %s not specified on some ports:"
1274 				" Using default", prop));
1275 			status = nxge_update_cfg_properties(nxgep,
1276 				flag, FAIR, c_dip);
1277 			return (status);
1278 		}
1279 	}
1280 
1281 	/* check type and consistence */
1282 	/* found on all devices */
1283 	for (i = 1; i < found; i++) {
1284 		if (c_token[i] != c_token[i - 1]) {
1285 			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1286 				" property %s inconsistent:"
1287 				" Using default", prop));
1288 			status = nxge_update_cfg_properties(nxgep,
1289 				flag, FAIR, c_dip);
1290 			return (status);
1291 		}
1292 	}
1293 
1294 	/*
1295 	 * Found on all the ports check if it is custom configuration. if
1296 	 * custom, then verify consistence
1297 	 *
1298 	 * finally create soft properties
1299 	 */
1300 	status = nxge_update_cfg_properties(nxgep, flag, c_token[0], c_dip);
1301 	return (status);
1302 }
1303 
1304 nxge_status_t
1305 nxge_cfg_verify_set_quick_config(p_nxge_t nxgep)
1306 {
1307 	nxge_status_t status = NXGE_OK;
1308 	int ddi_status = DDI_SUCCESS;
1309 	char *prop_val;
1310 	char *rx_prop;
1311 	char *prop;
1312 	uint32_t cfg_value = CFG_NOT_SPECIFIED;
1313 	p_nxge_param_t param_arr;
1314 
1315 	param_arr = nxgep->param_arr;
1316 	rx_prop = param_arr[param_rx_quick_cfg].fcode_name;
1317 
1318 	prop = "rx-quick-cfg";
1319 
1320 	/*
1321 	 * good value are
1322 	 *
1323 	 * "web-server" "generic-server" "l3-classify" "flow-classify"
1324 	 */
1325 	if (ddi_prop_lookup_string(DDI_DEV_T_ANY, nxgep->dip, 0,
1326 			prop, (char **)&prop_val) != DDI_PROP_SUCCESS) {
1327 		NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1328 			" property %s not specified: using default ", prop));
1329 		cfg_value = CFG_NOT_SPECIFIED;
1330 	} else {
1331 		cfg_value = CFG_L3_DISTRIBUTE;
1332 		if (strncmp("web-server", (caddr_t)prop_val, 8) == 0) {
1333 			cfg_value = CFG_L3_WEB;
1334 			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1335 				" %s: web server ", prop));
1336 		}
1337 		if (strncmp("generic-server", (caddr_t)prop_val, 8) == 0) {
1338 			cfg_value = CFG_L3_DISTRIBUTE;
1339 			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1340 				" %s: distribute ", prop));
1341 		}
1342 		/* more */
1343 		ddi_prop_free(prop_val);
1344 	}
1345 
1346 	ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
1347 		rx_prop, cfg_value);
1348 	if (ddi_status != DDI_PROP_SUCCESS)
1349 		status |= NXGE_DDI_FAILED;
1350 
1351 	/* now handle specified cases: */
1352 	if (status & NXGE_DDI_FAILED)
1353 		status |= NXGE_ERROR;
1354 	return (status);
1355 }
1356 
1357 static void
1358 nxge_use_cfg_link_cfg(p_nxge_t nxgep)
1359 {
1360 	int *prop_val;
1361 	uint_t prop_len;
1362 	dev_info_t *dip;
1363 	int speed;
1364 	int duplex;
1365 	int adv_autoneg_cap;
1366 	int adv_10gfdx_cap;
1367 	int adv_10ghdx_cap;
1368 	int adv_1000fdx_cap;
1369 	int adv_1000hdx_cap;
1370 	int adv_100fdx_cap;
1371 	int adv_100hdx_cap;
1372 	int adv_10fdx_cap;
1373 	int adv_10hdx_cap;
1374 	int status = DDI_SUCCESS;
1375 
1376 	dip = nxgep->dip;
1377 
1378 	/*
1379 	 * first find out the card type and the supported link speeds and
1380 	 * features
1381 	 */
1382 	/* add code for card type */
1383 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-autoneg-cap",
1384 			&prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1385 		ddi_prop_free(prop_val);
1386 		return;
1387 	}
1388 
1389 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10gfdx-cap",
1390 			&prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1391 		ddi_prop_free(prop_val);
1392 		return;
1393 	}
1394 
1395 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-1000hdx-cap",
1396 			&prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1397 		ddi_prop_free(prop_val);
1398 		return;
1399 	}
1400 
1401 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-1000fdx-cap",
1402 			&prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1403 		ddi_prop_free(prop_val);
1404 		return;
1405 	}
1406 
1407 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-100fdx-cap",
1408 			&prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1409 		ddi_prop_free(prop_val);
1410 		return;
1411 	}
1412 
1413 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-100hdx-cap",
1414 			&prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1415 		ddi_prop_free(prop_val);
1416 		return;
1417 	}
1418 
1419 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10fdx-cap",
1420 			&prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1421 		ddi_prop_free(prop_val);
1422 		return;
1423 	}
1424 
1425 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10hdx-cap",
1426 			&prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1427 		ddi_prop_free(prop_val);
1428 		return;
1429 	}
1430 
1431 	if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0, "speed",
1432 			(uchar_t **)&prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1433 		if (strncmp("10000", (caddr_t)prop_val,
1434 				(size_t)prop_len) == 0) {
1435 			speed = 10000;
1436 		} else if (strncmp("1000", (caddr_t)prop_val,
1437 				(size_t)prop_len) == 0) {
1438 			speed = 1000;
1439 		} else if (strncmp("100", (caddr_t)prop_val,
1440 				(size_t)prop_len) == 0) {
1441 			speed = 100;
1442 		} else if (strncmp("10", (caddr_t)prop_val,
1443 				(size_t)prop_len) == 0) {
1444 			speed = 10;
1445 		} else if (strncmp("auto", (caddr_t)prop_val,
1446 				(size_t)prop_len) == 0) {
1447 			speed = 0;
1448 		} else {
1449 			NXGE_ERROR_MSG((nxgep, NXGE_NOTE,
1450 				"speed property is invalid reverting to auto"));
1451 			speed = 0;
1452 		}
1453 		ddi_prop_free(prop_val);
1454 	} else
1455 		speed = 0;
1456 
1457 	if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0, "duplex",
1458 			(uchar_t **)&prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1459 		if (strncmp("full", (caddr_t)prop_val,
1460 				(size_t)prop_len) == 0) {
1461 			duplex = 2;
1462 		} else if (strncmp("half", (caddr_t)prop_val,
1463 				(size_t)prop_len) == 0) {
1464 			duplex = 1;
1465 		} else if (strncmp("auto", (caddr_t)prop_val,
1466 				(size_t)prop_len) == 0) {
1467 			duplex = 0;
1468 		} else {
1469 			NXGE_ERROR_MSG((nxgep, NXGE_NOTE,
1470 				"duplex property is invalid"
1471 				" reverting to auto"));
1472 			duplex = 0;
1473 		}
1474 		ddi_prop_free(prop_val);
1475 	} else
1476 		duplex = 0;
1477 
1478 	adv_autoneg_cap = (speed == 0) || (duplex == 0);
1479 	if (adv_autoneg_cap == 0) {
1480 		adv_10gfdx_cap = ((speed == 10000) && (duplex == 2));
1481 		adv_10ghdx_cap = adv_10gfdx_cap;
1482 		adv_10ghdx_cap |= ((speed == 10000) && (duplex == 1));
1483 		adv_1000fdx_cap = adv_10ghdx_cap;
1484 		adv_1000fdx_cap |= ((speed == 1000) && (duplex == 2));
1485 		adv_1000hdx_cap = adv_1000fdx_cap;
1486 		adv_1000hdx_cap |= ((speed == 1000) && (duplex == 1));
1487 		adv_100fdx_cap = adv_1000hdx_cap;
1488 		adv_100fdx_cap |= ((speed == 100) && (duplex == 2));
1489 		adv_100hdx_cap = adv_100fdx_cap;
1490 		adv_100hdx_cap |= ((speed == 100) && (duplex == 1));
1491 		adv_10fdx_cap = adv_100hdx_cap;
1492 		adv_10fdx_cap |= ((speed == 10) && (duplex == 2));
1493 		adv_10hdx_cap = adv_10fdx_cap;
1494 		adv_10hdx_cap |= ((speed == 10) && (duplex == 1));
1495 	} else if (speed == 0) {
1496 		adv_10gfdx_cap = (duplex == 2);
1497 		adv_10ghdx_cap = (duplex == 1);
1498 		adv_1000fdx_cap = (duplex == 2);
1499 		adv_1000hdx_cap = (duplex == 1);
1500 		adv_100fdx_cap = (duplex == 2);
1501 		adv_100hdx_cap = (duplex == 1);
1502 		adv_10fdx_cap = (duplex == 2);
1503 		adv_10hdx_cap = (duplex == 1);
1504 	}
1505 	if (duplex == 0) {
1506 		adv_10gfdx_cap = (speed == 0);
1507 		adv_10gfdx_cap |= (speed == 10000);
1508 		adv_10ghdx_cap = adv_10gfdx_cap;
1509 		adv_10ghdx_cap |= (speed == 10000);
1510 		adv_1000fdx_cap = adv_10ghdx_cap;
1511 		adv_1000fdx_cap |= (speed == 1000);
1512 		adv_1000hdx_cap = adv_1000fdx_cap;
1513 		adv_1000hdx_cap |= (speed == 1000);
1514 		adv_100fdx_cap = adv_1000hdx_cap;
1515 		adv_100fdx_cap |= (speed == 100);
1516 		adv_100hdx_cap = adv_100fdx_cap;
1517 		adv_100hdx_cap |= (speed == 100);
1518 		adv_10fdx_cap = adv_100hdx_cap;
1519 		adv_10fdx_cap |= (speed == 10);
1520 		adv_10hdx_cap = adv_10fdx_cap;
1521 		adv_10hdx_cap |= (speed == 10);
1522 	}
1523 	status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1524 		"adv-autoneg-cap", &adv_autoneg_cap, 1);
1525 	if (status)
1526 		return;
1527 
1528 	status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1529 		"adv-10gfdx-cap", &adv_10gfdx_cap, 1);
1530 	if (status)
1531 		goto nxge_map_myargs_to_gmii_fail1;
1532 
1533 	status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1534 		"adv-10ghdx-cap", &adv_10ghdx_cap, 1);
1535 	if (status)
1536 		goto nxge_map_myargs_to_gmii_fail2;
1537 
1538 	status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1539 		"adv-1000fdx-cap", &adv_1000fdx_cap, 1);
1540 	if (status)
1541 		goto nxge_map_myargs_to_gmii_fail3;
1542 
1543 	status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1544 		"adv-1000hdx-cap", &adv_1000hdx_cap, 1);
1545 	if (status)
1546 		goto nxge_map_myargs_to_gmii_fail4;
1547 
1548 	status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1549 		"adv-100fdx-cap", &adv_100fdx_cap, 1);
1550 	if (status)
1551 		goto nxge_map_myargs_to_gmii_fail5;
1552 
1553 	status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1554 		"adv-100hdx-cap", &adv_100hdx_cap, 1);
1555 	if (status)
1556 		goto nxge_map_myargs_to_gmii_fail6;
1557 
1558 	status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1559 		"adv-10fdx-cap", &adv_10fdx_cap, 1);
1560 	if (status)
1561 		goto nxge_map_myargs_to_gmii_fail7;
1562 
1563 	status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1564 		"adv-10hdx-cap", &adv_10hdx_cap, 1);
1565 	if (status)
1566 		goto nxge_map_myargs_to_gmii_fail8;
1567 
1568 	return;
1569 
1570 nxge_map_myargs_to_gmii_fail9:
1571 	(void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10hdx-cap");
1572 
1573 nxge_map_myargs_to_gmii_fail8:
1574 	(void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10fdx-cap");
1575 
1576 nxge_map_myargs_to_gmii_fail7:
1577 	(void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-100hdx-cap");
1578 
1579 nxge_map_myargs_to_gmii_fail6:
1580 	(void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-100fdx-cap");
1581 
1582 nxge_map_myargs_to_gmii_fail5:
1583 	(void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-1000hdx-cap");
1584 
1585 nxge_map_myargs_to_gmii_fail4:
1586 	(void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-1000fdx-cap");
1587 
1588 nxge_map_myargs_to_gmii_fail3:
1589 	(void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10ghdx-cap");
1590 
1591 nxge_map_myargs_to_gmii_fail2:
1592 	(void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10gfdx-cap");
1593 
1594 nxge_map_myargs_to_gmii_fail1:
1595 	(void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-autoneg-cap");
1596 }
1597 
1598 nxge_status_t
1599 nxge_get_config_properties(p_nxge_t nxgep)
1600 {
1601 	nxge_status_t status = NXGE_OK;
1602 	p_nxge_hw_list_t hw_p;
1603 
1604 	NXGE_DEBUG_MSG((nxgep, VPD_CTL, " ==> nxge_get_config_properties"));
1605 
1606 	if ((hw_p = nxgep->nxge_hw_p) == NULL) {
1607 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1608 			" nxge_get_config_properties:"
1609 			" common hardware not set", nxgep->niu_type));
1610 		return (NXGE_ERROR);
1611 	}
1612 
1613 	/*
1614 	 * Get info on how many ports Neptune card has.
1615 	 */
1616 	nxgep->nports = nxge_get_nports(nxgep);
1617 	if (nxgep->nports <= 0) {
1618 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1619 		    "<==nxge_get_config_properties: Invalid Neptune type 0x%x",
1620 		    nxgep->niu_type));
1621 		return (NXGE_ERROR);
1622 	}
1623 	nxgep->classifier.tcam_size = TCAM_NIU_TCAM_MAX_ENTRY;
1624 	if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
1625 		nxgep->classifier.tcam_size = TCAM_NXGE_TCAM_MAX_ENTRY;
1626 	}
1627 	if (nxgep->function_num >= nxgep->nports) {
1628 		return (NXGE_ERROR);
1629 	}
1630 
1631 	status = nxge_get_mac_addr_properties(nxgep);
1632 	if (status != NXGE_OK)
1633 		return (NXGE_ERROR);
1634 
1635 	/*
1636 	 * read the configuration type. If none is specified, used default.
1637 	 * Config types: equal: (default) DMA channels, RDC groups, TCAM, FCRAM
1638 	 * are shared equally across all the ports.
1639 	 *
1640 	 * Fair: DMA channels, RDC groups, TCAM, FCRAM are shared proportional
1641 	 * to the port speed.
1642 	 *
1643 	 *
1644 	 * custom: DMA channels, RDC groups, TCAM, FCRAM partition is
1645 	 * specified in nxge.conf. Need to read each parameter and set
1646 	 * up the parameters in nxge structures.
1647 	 *
1648 	 */
1649 	switch (nxgep->niu_type) {
1650 	case N2_NIU:
1651 		NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1652 			" ==> nxge_get_config_properties: N2"));
1653 		MUTEX_ENTER(&hw_p->nxge_cfg_lock);
1654 		if ((hw_p->flags & COMMON_CFG_VALID) !=
1655 			COMMON_CFG_VALID) {
1656 			status = nxge_cfg_verify_set(nxgep,
1657 				COMMON_RXDMA_GRP_CFG);
1658 			status = nxge_cfg_verify_set(nxgep,
1659 				COMMON_CLASS_CFG);
1660 			hw_p->flags |= COMMON_CFG_VALID;
1661 		}
1662 		MUTEX_EXIT(&hw_p->nxge_cfg_lock);
1663 		status = nxge_use_cfg_n2niu_properties(nxgep);
1664 		break;
1665 	default:
1666 		if (!NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
1667 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1668 			    " nxge_get_config_properties:"
1669 			    " unknown NIU type 0x%x", nxgep->niu_type));
1670 			return (NXGE_ERROR);
1671 		}
1672 
1673 		NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1674 			" ==> nxge_get_config_properties: Neptune"));
1675 		status = nxge_cfg_verify_set_quick_config(nxgep);
1676 		MUTEX_ENTER(&hw_p->nxge_cfg_lock);
1677 		if ((hw_p->flags & COMMON_CFG_VALID) !=
1678 			COMMON_CFG_VALID) {
1679 			status = nxge_cfg_verify_set(nxgep,
1680 				COMMON_TXDMA_CFG);
1681 			status = nxge_cfg_verify_set(nxgep,
1682 				COMMON_RXDMA_CFG);
1683 			status = nxge_cfg_verify_set(nxgep,
1684 				COMMON_RXDMA_GRP_CFG);
1685 			status = nxge_cfg_verify_set(nxgep,
1686 				COMMON_CLASS_CFG);
1687 			hw_p->flags |= COMMON_CFG_VALID;
1688 		}
1689 		MUTEX_EXIT(&hw_p->nxge_cfg_lock);
1690 		nxge_use_cfg_neptune_properties(nxgep);
1691 		status = NXGE_OK;
1692 		break;
1693 	}
1694 
1695 	NXGE_DEBUG_MSG((nxgep, VPD_CTL, " <== nxge_get_config_properties"));
1696 	return (status);
1697 }
1698 
1699 static nxge_status_t
1700 nxge_use_cfg_n2niu_properties(p_nxge_t nxgep)
1701 {
1702 	nxge_status_t status = NXGE_OK;
1703 
1704 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_n2niu_properties"));
1705 
1706 	status = nxge_use_default_dma_config_n2(nxgep);
1707 	if (status != NXGE_OK) {
1708 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1709 			" ==> nxge_use_cfg_n2niu_properties (err 0x%x)",
1710 			status));
1711 		return (status | NXGE_ERROR);
1712 	}
1713 
1714 	(void) nxge_use_cfg_vlan_class_config(nxgep);
1715 	(void) nxge_use_cfg_mac_class_config(nxgep);
1716 	(void) nxge_use_cfg_class_config(nxgep);
1717 	(void) nxge_use_cfg_link_cfg(nxgep);
1718 
1719 	/*
1720 	 * Read in the hardware (fcode) properties. Use the ndd array to read
1721 	 * each property.
1722 	 */
1723 	(void) nxge_get_param_soft_properties(nxgep);
1724 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_n2niu_properties"));
1725 
1726 	return (status);
1727 }
1728 
1729 static void
1730 nxge_use_cfg_neptune_properties(p_nxge_t nxgep)
1731 {
1732 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_neptune_properties"));
1733 
1734 	(void) nxge_use_cfg_dma_config(nxgep);
1735 	(void) nxge_use_cfg_vlan_class_config(nxgep);
1736 	(void) nxge_use_cfg_mac_class_config(nxgep);
1737 	(void) nxge_use_cfg_class_config(nxgep);
1738 	(void) nxge_use_cfg_link_cfg(nxgep);
1739 
1740 	/*
1741 	 * Read in the hardware (fcode) properties. Use the ndd array to read
1742 	 * each property.
1743 	 */
1744 	(void) nxge_get_param_soft_properties(nxgep);
1745 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_neptune_properties"));
1746 }
1747 
1748 /*
1749  * FWARC 2006/556
1750  */
1751 
1752 static nxge_status_t
1753 nxge_use_default_dma_config_n2(p_nxge_t nxgep)
1754 {
1755 	int ndmas;
1756 	int nrxgp;
1757 	uint8_t func;
1758 	p_nxge_dma_pt_cfg_t p_dma_cfgp;
1759 	p_nxge_hw_pt_cfg_t p_cfgp;
1760 	int *prop_val;
1761 	uint_t prop_len;
1762 	int i;
1763 	nxge_status_t status = NXGE_OK;
1764 
1765 	NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2"));
1766 
1767 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1768 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
1769 
1770 	func = nxgep->function_num;
1771 	p_cfgp->function_number = func;
1772 	ndmas = NXGE_TDMA_PER_NIU_PORT;
1773 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1774 			"tx-dma-channels", (int **)&prop_val,
1775 			&prop_len) == DDI_PROP_SUCCESS) {
1776 		p_cfgp->start_tdc = prop_val[0];
1777 		NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1778 			"==> nxge_use_default_dma_config_n2: tdc starts %d "
1779 			"(#%d)", p_cfgp->start_tdc, prop_len));
1780 
1781 		ndmas = prop_val[1];
1782 		NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1783 			"==> nxge_use_default_dma_config_n2: #tdc %d (#%d)",
1784 			ndmas, prop_len));
1785 		ddi_prop_free(prop_val);
1786 	} else {
1787 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1788 			"==> nxge_use_default_dma_config_n2: "
1789 			"get tx-dma-channels failed"));
1790 		return (NXGE_DDI_FAILED);
1791 	}
1792 
1793 	p_cfgp->max_tdcs = nxgep->max_tdcs = ndmas;
1794 	nxgep->tdc_mask = (ndmas - 1);
1795 
1796 	NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: "
1797 		"p_cfgp 0x%llx max_tdcs %d nxgep->max_tdcs %d start %d",
1798 		p_cfgp, p_cfgp->max_tdcs, nxgep->max_tdcs, p_cfgp->start_tdc));
1799 
1800 	/* Receive DMA */
1801 	ndmas = NXGE_RDMA_PER_NIU_PORT;
1802 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1803 			"rx-dma-channels", (int **)&prop_val,
1804 			&prop_len) == DDI_PROP_SUCCESS) {
1805 		p_cfgp->start_rdc = prop_val[0];
1806 		NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1807 			"==> nxge_use_default_dma_config_n2(obp): rdc start %d"
1808 			" (#%d)", p_cfgp->start_rdc, prop_len));
1809 		ndmas = prop_val[1];
1810 		NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1811 			"==> nxge_use_default_dma_config_n2(obp):#rdc %d (#%d)",
1812 			ndmas, prop_len));
1813 		ddi_prop_free(prop_val);
1814 	} else {
1815 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1816 			"==> nxge_use_default_dma_config_n2: "
1817 			"get rx-dma-channel failed"));
1818 		return (NXGE_DDI_FAILED);
1819 	}
1820 
1821 	p_cfgp->max_rdcs = nxgep->max_rdcs = ndmas;
1822 	nxgep->rdc_mask = (ndmas - 1);
1823 
1824 	/* Hypervisor: rdc # and group # use the same # !! */
1825 	p_cfgp->max_grpids = p_cfgp->max_rdcs + p_cfgp->max_tdcs;
1826 	p_cfgp->start_grpid = 0;
1827 	p_cfgp->mif_ldvid = p_cfgp->mac_ldvid = p_cfgp->ser_ldvid = 0;
1828 
1829 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1830 			"interrupts", (int **)&prop_val,
1831 			&prop_len) == DDI_PROP_SUCCESS) {
1832 		/*
1833 		 * For each device assigned, the content of each interrupts
1834 		 * property is its logical device group.
1835 		 *
1836 		 * Assignment of interrupts property is in the the following
1837 		 * order:
1838 		 *
1839 		 * MAC MIF (if configured) SYSTEM ERROR (if configured) first
1840 		 * receive channel next channel...... last receive channel
1841 		 * first transmit channel next channel...... last transmit
1842 		 * channel
1843 		 *
1844 		 * prop_len should be at least for one mac and total # of rx and
1845 		 * tx channels. Function 0 owns MIF and ERROR
1846 		 */
1847 		NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1848 			"==> nxge_use_default_dma_config_n2(obp): "
1849 			"# interrupts %d", prop_len));
1850 
1851 		switch (func) {
1852 		case 0:
1853 			p_cfgp->ldg_chn_start = 3;
1854 			p_cfgp->mac_ldvid = NXGE_MAC_LD_PORT0;
1855 			p_cfgp->mif_ldvid = NXGE_MIF_LD;
1856 			p_cfgp->ser_ldvid = NXGE_SYS_ERROR_LD;
1857 
1858 			break;
1859 		case 1:
1860 			p_cfgp->ldg_chn_start = 1;
1861 			p_cfgp->mac_ldvid = NXGE_MAC_LD_PORT1;
1862 
1863 			break;
1864 		default:
1865 			status = NXGE_DDI_FAILED;
1866 			break;
1867 		}
1868 
1869 		if (status != NXGE_OK)
1870 			return (status);
1871 
1872 		for (i = 0; i < prop_len; i++) {
1873 			p_cfgp->ldg[i] = prop_val[i];
1874 			NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1875 				"==> nxge_use_default_dma_config_n2(obp): "
1876 				"interrupt #%d, ldg %d",
1877 				i, p_cfgp->ldg[i]));
1878 		}
1879 
1880 		p_cfgp->max_grpids = prop_len;
1881 		NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1882 			"==> nxge_use_default_dma_config_n2(obp): %d "
1883 			"(#%d) maxgrpids %d channel starts %d",
1884 			p_cfgp->mac_ldvid, i, p_cfgp->max_grpids,
1885 			p_cfgp->ldg_chn_start));
1886 		ddi_prop_free(prop_val);
1887 	} else {
1888 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1889 			"==> nxge_use_default_dma_config_n2: "
1890 			"get interrupts failed"));
1891 		return (NXGE_DDI_FAILED);
1892 	}
1893 
1894 	p_cfgp->max_ldgs = p_cfgp->max_grpids;
1895 	NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1896 		"==> nxge_use_default_dma_config_n2: "
1897 		"p_cfgp 0x%llx max_rdcs %d nxgep->max_rdcs %d max_grpids %d"
1898 		"start_grpid %d macid %d mifid %d serrid %d",
1899 		p_cfgp, p_cfgp->max_rdcs, nxgep->max_rdcs, p_cfgp->max_grpids,
1900 		p_cfgp->start_grpid,
1901 		p_cfgp->mac_ldvid, p_cfgp->mif_ldvid, p_cfgp->ser_ldvid));
1902 
1903 	NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: "
1904 		"p_cfgp p%p start_ldg %d nxgep->max_ldgs %d",
1905 		p_cfgp, p_cfgp->start_ldg, p_cfgp->max_ldgs));
1906 
1907 	/*
1908 	 * RDC groups and the beginning RDC group assigned to this function.
1909 	 */
1910 	nrxgp = 2;
1911 	p_cfgp->max_rdc_grpids = nrxgp;
1912 	p_cfgp->start_rdc_grpid = (nxgep->function_num * nrxgp);
1913 
1914 	status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
1915 		"rx-rdc-grps", nrxgp);
1916 	if (status) {
1917 		return (NXGE_DDI_FAILED);
1918 	}
1919 	status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
1920 		"rx-rdc-grps-begin", p_cfgp->start_rdc_grpid);
1921 	if (status) {
1922 		(void) ddi_prop_remove(DDI_DEV_T_NONE, nxgep->dip,
1923 			"rx-rdc-grps");
1924 		return (NXGE_DDI_FAILED);
1925 	}
1926 	NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: "
1927 		"p_cfgp $%p # rdc groups %d start rdc group id %d",
1928 		p_cfgp, p_cfgp->max_rdc_grpids,
1929 		p_cfgp->start_rdc_grpid));
1930 
1931 	nxge_set_hw_dma_config(nxgep);
1932 	NXGE_DEBUG_MSG((nxgep, OBP_CTL, "<== nxge_use_default_dma_config_n2"));
1933 	return (status);
1934 }
1935 
1936 static void
1937 nxge_use_cfg_dma_config(p_nxge_t nxgep)
1938 {
1939 	int tx_ndmas, rx_ndmas, nrxgp, st_txdma, st_rxdma;
1940 	p_nxge_dma_pt_cfg_t p_dma_cfgp;
1941 	p_nxge_hw_pt_cfg_t p_cfgp;
1942 	dev_info_t *dip;
1943 	p_nxge_param_t param_arr;
1944 	char *prop;
1945 	int *prop_val;
1946 	uint_t prop_len;
1947 	int i;
1948 	uint8_t *ch_arr_p;
1949 
1950 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_dma_config"));
1951 	param_arr = nxgep->param_arr;
1952 
1953 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1954 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
1955 	dip = nxgep->dip;
1956 	p_cfgp->function_number = nxgep->function_num;
1957 	prop = param_arr[param_txdma_channels_begin].fcode_name;
1958 
1959 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
1960 			&prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1961 		p_cfgp->start_tdc = *prop_val;
1962 		ddi_prop_free(prop_val);
1963 	} else {
1964 		switch (nxgep->niu_type) {
1965 		case NEPTUNE_4_1GC:
1966 			ch_arr_p = &tx_4_1G[0];
1967 			break;
1968 		case NEPTUNE_2_10GF:
1969 			ch_arr_p = &tx_2_10G[0];
1970 			break;
1971 		case NEPTUNE_2_10GF_2_1GC:
1972 			ch_arr_p = &tx_2_10G_2_1G[0];
1973 			break;
1974 		case NEPTUNE_1_10GF_3_1GC:
1975 			ch_arr_p = &tx_1_10G_3_1G[0];
1976 			break;
1977 		case NEPTUNE_1_1GC_1_10GF_2_1GC:
1978 			ch_arr_p = &tx_1_1G_1_10G_2_1G[0];
1979 			break;
1980 		default:
1981 			ch_arr_p = &p4_tx_equal[0];
1982 			break;
1983 		}
1984 		st_txdma = 0;
1985 		for (i = 0; i < nxgep->function_num; i++, ch_arr_p++)
1986 			st_txdma += *ch_arr_p;
1987 
1988 		(void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
1989 		    prop, st_txdma);
1990 		p_cfgp->start_tdc = st_txdma;
1991 	}
1992 
1993 	prop = param_arr[param_txdma_channels].fcode_name;
1994 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
1995 			&prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1996 		tx_ndmas = *prop_val;
1997 		ddi_prop_free(prop_val);
1998 	} else {
1999 		switch (nxgep->niu_type) {
2000 		case NEPTUNE_4_1GC:
2001 			tx_ndmas = tx_4_1G[nxgep->function_num];
2002 			break;
2003 		case NEPTUNE_2_10GF:
2004 			tx_ndmas = tx_2_10G[nxgep->function_num];
2005 			break;
2006 		case NEPTUNE_2_10GF_2_1GC:
2007 			tx_ndmas = tx_2_10G_2_1G[nxgep->function_num];
2008 			break;
2009 		case NEPTUNE_1_10GF_3_1GC:
2010 			tx_ndmas = tx_1_10G_3_1G[nxgep->function_num];
2011 			break;
2012 		case NEPTUNE_1_1GC_1_10GF_2_1GC:
2013 			tx_ndmas = tx_1_1G_1_10G_2_1G[nxgep->function_num];
2014 			break;
2015 		default:
2016 			tx_ndmas = p4_tx_equal[nxgep->function_num];
2017 			break;
2018 		}
2019 		(void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
2020 			prop, tx_ndmas);
2021 	}
2022 
2023 	p_cfgp->max_tdcs = nxgep->max_tdcs = tx_ndmas;
2024 	nxgep->tdc_mask = (tx_ndmas - 1);
2025 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_dma_config: "
2026 		"p_cfgp 0x%llx max_tdcs %d nxgep->max_tdcs %d",
2027 		p_cfgp, p_cfgp->max_tdcs, nxgep->max_tdcs));
2028 
2029 	prop = param_arr[param_rxdma_channels_begin].fcode_name;
2030 
2031 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
2032 			&prop_val, &prop_len) == DDI_PROP_SUCCESS) {
2033 		p_cfgp->start_rdc = *prop_val;
2034 		ddi_prop_free(prop_val);
2035 	} else {
2036 		switch (nxgep->niu_type) {
2037 		case NEPTUNE_4_1GC:
2038 			ch_arr_p = &rx_4_1G[0];
2039 			break;
2040 		case NEPTUNE_2_10GF:
2041 			ch_arr_p = &rx_2_10G[0];
2042 			break;
2043 		case NEPTUNE_2_10GF_2_1GC:
2044 			ch_arr_p = &rx_2_10G_2_1G[0];
2045 			break;
2046 		case NEPTUNE_1_10GF_3_1GC:
2047 			ch_arr_p = &rx_1_10G_3_1G[0];
2048 			break;
2049 		case NEPTUNE_1_1GC_1_10GF_2_1GC:
2050 			ch_arr_p = &rx_1_1G_1_10G_2_1G[0];
2051 			break;
2052 		default:
2053 			ch_arr_p = &p4_rx_equal[0];
2054 			break;
2055 		}
2056 		st_rxdma = 0;
2057 		for (i = 0; i < nxgep->function_num; i++, ch_arr_p++)
2058 			st_rxdma += *ch_arr_p;
2059 
2060 		(void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
2061 		    prop, st_rxdma);
2062 		p_cfgp->start_rdc = st_rxdma;
2063 	}
2064 
2065 	prop = param_arr[param_rxdma_channels].fcode_name;
2066 
2067 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
2068 			&prop_val, &prop_len) == DDI_PROP_SUCCESS) {
2069 		rx_ndmas = *prop_val;
2070 		ddi_prop_free(prop_val);
2071 	} else {
2072 		switch (nxgep->niu_type) {
2073 		case NEPTUNE_4_1GC:
2074 			rx_ndmas = rx_4_1G[nxgep->function_num];
2075 			break;
2076 		case NEPTUNE_2_10GF:
2077 			rx_ndmas = rx_2_10G[nxgep->function_num];
2078 			break;
2079 		case NEPTUNE_2_10GF_2_1GC:
2080 			rx_ndmas = rx_2_10G_2_1G[nxgep->function_num];
2081 			break;
2082 		case NEPTUNE_1_10GF_3_1GC:
2083 			rx_ndmas = rx_1_10G_3_1G[nxgep->function_num];
2084 			break;
2085 		case NEPTUNE_1_1GC_1_10GF_2_1GC:
2086 			rx_ndmas = rx_1_1G_1_10G_2_1G[nxgep->function_num];
2087 			break;
2088 		default:
2089 			rx_ndmas = p4_rx_equal[nxgep->function_num];
2090 			break;
2091 		}
2092 		(void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
2093 			prop, rx_ndmas);
2094 	}
2095 
2096 	p_cfgp->max_rdcs = nxgep->max_rdcs = rx_ndmas;
2097 
2098 	prop = param_arr[param_rdc_grps_start].fcode_name;
2099 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
2100 			&prop_val, &prop_len) == DDI_PROP_SUCCESS) {
2101 		p_cfgp->start_rdc_grpid = *prop_val;
2102 		ddi_prop_free(prop_val);
2103 		NXGE_DEBUG_MSG((nxgep, CFG_CTL,
2104 			"==> nxge_use_default_dma_config: "
2105 			"use property " "start_grpid %d ",
2106 			p_cfgp->start_grpid));
2107 	} else {
2108 		p_cfgp->start_rdc_grpid = nxgep->function_num;
2109 		(void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
2110 			prop, p_cfgp->start_rdc_grpid);
2111 
2112 		NXGE_DEBUG_MSG((nxgep, CFG_CTL,
2113 			"==> nxge_use_default_dma_config: "
2114 			"use default "
2115 			"start_grpid %d (same as function #)",
2116 			p_cfgp->start_grpid));
2117 	}
2118 
2119 	prop = param_arr[param_rx_rdc_grps].fcode_name;
2120 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
2121 			&prop_val, &prop_len) == DDI_PROP_SUCCESS) {
2122 		nrxgp = *prop_val;
2123 		ddi_prop_free(prop_val);
2124 	} else {
2125 		nrxgp = 1;
2126 		(void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
2127 			prop, nrxgp);
2128 		NXGE_DEBUG_MSG((nxgep, CFG_CTL,
2129 			"==> nxge_use_default_dma_config: "
2130 			"num_rdc_grpid not found: use def:# of "
2131 			"rdc groups %d\n", nrxgp));
2132 	}
2133 
2134 	p_cfgp->max_rdc_grpids = nrxgp;
2135 
2136 	/*
2137 	 * 2/4 ports have the same hard-wired logical groups assigned.
2138 	 */
2139 	p_cfgp->start_ldg = nxgep->function_num * NXGE_LDGRP_PER_4PORTS;
2140 	p_cfgp->max_ldgs = NXGE_LDGRP_PER_4PORTS;
2141 
2142 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_default_dma_config: "
2143 		"p_cfgp 0x%llx max_rdcs %d nxgep->max_rdcs %d max_grpids %d"
2144 		"start_grpid %d",
2145 		p_cfgp, p_cfgp->max_rdcs, nxgep->max_rdcs, p_cfgp->max_grpids,
2146 		p_cfgp->start_grpid));
2147 
2148 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_dma_config: "
2149 		"p_cfgp 0x%016llx start_ldg %d nxgep->max_ldgs %d "
2150 		"start_rdc_grpid %d",
2151 		p_cfgp, p_cfgp->start_ldg, p_cfgp->max_ldgs,
2152 		p_cfgp->start_rdc_grpid));
2153 
2154 	prop = param_arr[param_rxdma_intr_time].fcode_name;
2155 
2156 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
2157 			&prop_val, &prop_len) == DDI_PROP_SUCCESS) {
2158 		if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) {
2159 			(void) ddi_prop_update_int_array(DDI_DEV_T_NONE,
2160 				nxgep->dip, prop, prop_val, prop_len);
2161 		}
2162 		ddi_prop_free(prop_val);
2163 	}
2164 	prop = param_arr[param_rxdma_intr_pkts].fcode_name;
2165 
2166 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
2167 			&prop_val, &prop_len) == DDI_PROP_SUCCESS) {
2168 		if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) {
2169 			(void) ddi_prop_update_int_array(DDI_DEV_T_NONE,
2170 				nxgep->dip, prop, prop_val, prop_len);
2171 		}
2172 		ddi_prop_free(prop_val);
2173 	}
2174 	nxge_set_hw_dma_config(nxgep);
2175 
2176 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_dma_config: "
2177 	    "sTDC[%d] nTDC[%d] sRDC[%d] nRDC[%d]",
2178 	    p_cfgp->start_tdc, p_cfgp->max_tdcs,
2179 	    p_cfgp->start_rdc, p_cfgp->max_rdcs));
2180 
2181 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_dma_config"));
2182 }
2183 
2184 static void
2185 nxge_use_cfg_vlan_class_config(p_nxge_t nxgep)
2186 {
2187 	uint_t vlan_cnt;
2188 	int *vlan_cfg_val;
2189 	int status;
2190 	p_nxge_param_t param_arr;
2191 	char *prop;
2192 
2193 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_vlan_config"));
2194 	param_arr = nxgep->param_arr;
2195 	prop = param_arr[param_vlan_2rdc_grp].fcode_name;
2196 
2197 	status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
2198 		&vlan_cfg_val, &vlan_cnt);
2199 	if (status == DDI_PROP_SUCCESS) {
2200 		status = ddi_prop_update_int_array(DDI_DEV_T_NONE,
2201 			nxgep->dip, prop, vlan_cfg_val, vlan_cnt);
2202 		ddi_prop_free(vlan_cfg_val);
2203 	}
2204 	nxge_set_hw_vlan_class_config(nxgep);
2205 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_vlan_config"));
2206 }
2207 
2208 static void
2209 nxge_use_cfg_mac_class_config(p_nxge_t nxgep)
2210 {
2211 	p_nxge_dma_pt_cfg_t p_dma_cfgp;
2212 	p_nxge_hw_pt_cfg_t p_cfgp;
2213 	uint_t mac_cnt;
2214 	int *mac_cfg_val;
2215 	int status;
2216 	p_nxge_param_t param_arr;
2217 	char *prop;
2218 
2219 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_mac_class_config"));
2220 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2221 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2222 	p_cfgp->start_mac_entry = 0;
2223 	param_arr = nxgep->param_arr;
2224 	prop = param_arr[param_mac_2rdc_grp].fcode_name;
2225 
2226 	switch (nxgep->function_num) {
2227 	case 0:
2228 	case 1:
2229 		/* 10G ports */
2230 		p_cfgp->max_macs = NXGE_MAX_MACS_XMACS;
2231 		break;
2232 	case 2:
2233 	case 3:
2234 		/* 1G ports */
2235 	default:
2236 		p_cfgp->max_macs = NXGE_MAX_MACS_BMACS;
2237 		break;
2238 	}
2239 
2240 	p_cfgp->mac_pref = 1;
2241 	p_cfgp->def_mac_rxdma_grpid = p_cfgp->start_rdc_grpid;
2242 
2243 	NXGE_DEBUG_MSG((nxgep, OBP_CTL,
2244 		"== nxge_use_cfg_mac_class_config: "
2245 		" mac_pref bit set def_mac_rxdma_grpid %d",
2246 		p_cfgp->def_mac_rxdma_grpid));
2247 
2248 	status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
2249 		&mac_cfg_val, &mac_cnt);
2250 	if (status == DDI_PROP_SUCCESS) {
2251 		if (mac_cnt <= p_cfgp->max_macs)
2252 			status = ddi_prop_update_int_array(DDI_DEV_T_NONE,
2253 				nxgep->dip, prop, mac_cfg_val, mac_cnt);
2254 		ddi_prop_free(mac_cfg_val);
2255 	}
2256 	nxge_set_hw_mac_class_config(nxgep);
2257 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_mac_class_config"));
2258 }
2259 
2260 static void
2261 nxge_use_cfg_class_config(p_nxge_t nxgep)
2262 {
2263 	nxge_set_hw_class_config(nxgep);
2264 }
2265 
2266 static void
2267 nxge_set_rdc_intr_property(p_nxge_t nxgep)
2268 {
2269 	int i;
2270 	p_nxge_dma_pt_cfg_t p_dma_cfgp;
2271 
2272 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_rdc_intr_property"));
2273 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2274 
2275 	for (i = 0; i < NXGE_MAX_RDCS; i++) {
2276 		p_dma_cfgp->rcr_timeout[i] = nxge_rcr_timeout;
2277 		p_dma_cfgp->rcr_threshold[i] = nxge_rcr_threshold;
2278 	}
2279 
2280 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_rdc_intr_property"));
2281 }
2282 
2283 static void
2284 nxge_set_hw_dma_config(p_nxge_t nxgep)
2285 {
2286 	int i, j, rdc, ndmas, ngrps, bitmap, end, st_rdc;
2287 	int32_t status;
2288 	uint8_t rdcs_per_grp;
2289 	p_nxge_dma_pt_cfg_t p_dma_cfgp;
2290 	p_nxge_hw_pt_cfg_t p_cfgp;
2291 	p_nxge_rdc_grp_t rdc_grp_p;
2292 	int rdcgrp_cfg = CFG_NOT_SPECIFIED, rx_quick_cfg;
2293 	char *prop, *prop_val;
2294 	p_nxge_param_t param_arr;
2295 	config_token_t token;
2296 
2297 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_set_hw_dma_config"));
2298 
2299 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2300 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2301 	rdc_grp_p = p_dma_cfgp->rdc_grps;
2302 
2303 	/* Transmit DMA Channels */
2304 	bitmap = 0;
2305 	end = p_cfgp->start_tdc + p_cfgp->max_tdcs;
2306 	nxgep->ntdc = p_cfgp->max_tdcs;
2307 	p_dma_cfgp->tx_dma_map = 0;
2308 	for (i = p_cfgp->start_tdc; i < end; i++) {
2309 		bitmap |= (1 << i);
2310 		nxgep->tdc[i - p_cfgp->start_tdc] = (uint8_t)i;
2311 	}
2312 
2313 	p_dma_cfgp->tx_dma_map = bitmap;
2314 	param_arr = nxgep->param_arr;
2315 
2316 	/* Assume RDCs are evenly distributed */
2317 	rx_quick_cfg = param_arr[param_rx_quick_cfg].value;
2318 	switch (rx_quick_cfg) {
2319 	case CFG_NOT_SPECIFIED:
2320 		prop = "rxdma-grp-cfg";
2321 		status = ddi_prop_lookup_string(DDI_DEV_T_NONE,
2322 			nxgep->dip, 0, prop, (char **)&prop_val);
2323 		if (status != DDI_PROP_SUCCESS) {
2324 			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
2325 				" property %s not found", prop));
2326 			rdcgrp_cfg = CFG_L3_DISTRIBUTE;
2327 		} else {
2328 			token = nxge_get_config_token(prop_val);
2329 			switch (token) {
2330 			case L2_CLASSIFY:
2331 				break;
2332 			case CLASSIFY:
2333 			case L3_CLASSIFY:
2334 			case L3_DISTRIBUTE:
2335 			case L3_TCAM:
2336 				rdcgrp_cfg = CFG_L3_DISTRIBUTE;
2337 				break;
2338 			default:
2339 				rdcgrp_cfg = CFG_L3_DISTRIBUTE;
2340 				break;
2341 			}
2342 			ddi_prop_free(prop_val);
2343 		}
2344 		break;
2345 	case CFG_L3_WEB:
2346 	case CFG_L3_DISTRIBUTE:
2347 	case CFG_L2_CLASSIFY:
2348 	case CFG_L3_TCAM:
2349 		rdcgrp_cfg = rx_quick_cfg;
2350 		break;
2351 	default:
2352 		rdcgrp_cfg = CFG_L3_DISTRIBUTE;
2353 		break;
2354 	}
2355 
2356 	/* Receive DMA Channels */
2357 	st_rdc = p_cfgp->start_rdc;
2358 	nxgep->nrdc = p_cfgp->max_rdcs;
2359 
2360 	for (i = 0; i < p_cfgp->max_rdcs; i++) {
2361 		nxgep->rdc[i] = i + p_cfgp->start_rdc;
2362 	}
2363 
2364 	switch (rdcgrp_cfg) {
2365 	case CFG_L3_DISTRIBUTE:
2366 	case CFG_L3_WEB:
2367 	case CFG_L3_TCAM:
2368 		ndmas = p_cfgp->max_rdcs;
2369 		ngrps = 1;
2370 		rdcs_per_grp = ndmas / ngrps;
2371 		break;
2372 	case CFG_L2_CLASSIFY:
2373 		ndmas = p_cfgp->max_rdcs / 2;
2374 		if (p_cfgp->max_rdcs < 2)
2375 			ndmas = 1;
2376 		ngrps = 1;
2377 		rdcs_per_grp = ndmas / ngrps;
2378 		break;
2379 	default:
2380 		ngrps = p_cfgp->max_rdc_grpids;
2381 		ndmas = p_cfgp->max_rdcs;
2382 		rdcs_per_grp = ndmas / ngrps;
2383 		break;
2384 	}
2385 
2386 	for (i = 0; i < ngrps; i++) {
2387 		rdc_grp_p = &p_dma_cfgp->rdc_grps[i];
2388 		rdc_grp_p->start_rdc = st_rdc + i * rdcs_per_grp;
2389 		rdc_grp_p->max_rdcs = rdcs_per_grp;
2390 
2391 		/* default to: 0, 1, 2, 3, ...., 0, 1, 2, 3.... */
2392 		rdc_grp_p->config_method = RDC_TABLE_ENTRY_METHOD_SEQ;
2393 		rdc = rdc_grp_p->start_rdc;
2394 		for (j = 0; j < NXGE_MAX_RDCS; j++) {
2395 			rdc_grp_p->rdc[j] = rdc++;
2396 			if (rdc == (rdc_grp_p->start_rdc + rdcs_per_grp)) {
2397 				rdc = rdc_grp_p->start_rdc;
2398 			}
2399 		}
2400 		rdc_grp_p->def_rdc = rdc_grp_p->rdc[0];
2401 		rdc_grp_p->flag = 1;	/* configured */
2402 	}
2403 
2404 	/* default RDC */
2405 	p_cfgp->def_rdc = p_cfgp->start_rdc;
2406 	nxgep->def_rdc = p_cfgp->start_rdc;
2407 
2408 	/* full 18 byte header ? */
2409 	p_dma_cfgp->rcr_full_header = NXGE_RCR_FULL_HEADER;
2410 	p_dma_cfgp->rx_drr_weight = PT_DRR_WT_DEFAULT_10G;
2411 	if (nxgep->function_num > 1)
2412 		p_dma_cfgp->rx_drr_weight = PT_DRR_WT_DEFAULT_1G;
2413 	p_dma_cfgp->rbr_size = nxge_rbr_size;
2414 	p_dma_cfgp->rcr_size = nxge_rcr_size;
2415 
2416 	nxge_set_rdc_intr_property(nxgep);
2417 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_hw_dma_config"));
2418 }
2419 
2420 boolean_t
2421 nxge_check_rxdma_port_member(p_nxge_t nxgep, uint8_t rdc)
2422 {
2423 	p_nxge_dma_pt_cfg_t p_dma_cfgp;
2424 	p_nxge_hw_pt_cfg_t p_cfgp;
2425 	int status = B_TRUE;
2426 
2427 	NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_rxdma_port_member"));
2428 
2429 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2430 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2431 
2432 	/* Receive DMA Channels */
2433 	if (rdc < p_cfgp->max_rdcs)
2434 		status = B_TRUE;
2435 	NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_rxdma_port_member"));
2436 	return (status);
2437 }
2438 
2439 boolean_t
2440 nxge_check_txdma_port_member(p_nxge_t nxgep, uint8_t tdc)
2441 {
2442 	p_nxge_dma_pt_cfg_t p_dma_cfgp;
2443 	p_nxge_hw_pt_cfg_t p_cfgp;
2444 	int status = B_FALSE;
2445 
2446 	NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_rxdma_port_member"));
2447 
2448 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2449 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2450 
2451 	/* Receive DMA Channels */
2452 	if (tdc < p_cfgp->max_tdcs)
2453 		status = B_TRUE;
2454 	NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_rxdma_port_member"));
2455 	return (status);
2456 }
2457 
2458 boolean_t
2459 nxge_check_rxdma_rdcgrp_member(p_nxge_t nxgep, uint8_t rdc_grp, uint8_t rdc)
2460 {
2461 	p_nxge_dma_pt_cfg_t p_dma_cfgp;
2462 	int status = B_TRUE;
2463 	p_nxge_rdc_grp_t rdc_grp_p;
2464 
2465 	NXGE_DEBUG_MSG((nxgep, CFG2_CTL,
2466 		" ==> nxge_check_rxdma_rdcgrp_member"));
2467 	NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "  nxge_check_rxdma_rdcgrp_member"
2468 		" rdc  %d group %d", rdc, rdc_grp));
2469 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2470 
2471 	rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp];
2472 	NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "  max  %d ", rdc_grp_p->max_rdcs));
2473 	if (rdc >= rdc_grp_p->max_rdcs) {
2474 		status = B_FALSE;
2475 	}
2476 	NXGE_DEBUG_MSG((nxgep, CFG2_CTL,
2477 		" <== nxge_check_rxdma_rdcgrp_member"));
2478 	return (status);
2479 }
2480 
2481 boolean_t
2482 nxge_check_rdcgrp_port_member(p_nxge_t nxgep, uint8_t rdc_grp)
2483 {
2484 	p_nxge_dma_pt_cfg_t p_dma_cfgp;
2485 	p_nxge_hw_pt_cfg_t p_cfgp;
2486 	int status = B_TRUE;
2487 
2488 	NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_rdcgrp_port_member"));
2489 
2490 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2491 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2492 
2493 	if (rdc_grp >= p_cfgp->max_rdc_grpids)
2494 		status = B_FALSE;
2495 	NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_rdcgrp_port_member"));
2496 	return (status);
2497 }
2498 
2499 static void
2500 nxge_set_hw_vlan_class_config(p_nxge_t nxgep)
2501 {
2502 	int i;
2503 	p_nxge_dma_pt_cfg_t p_dma_cfgp;
2504 	p_nxge_hw_pt_cfg_t p_cfgp;
2505 	p_nxge_param_t param_arr;
2506 	uint_t vlan_cnt;
2507 	int *vlan_cfg_val;
2508 	nxge_param_map_t *vmap;
2509 	char *prop;
2510 	p_nxge_class_pt_cfg_t p_class_cfgp;
2511 	uint32_t good_cfg[32];
2512 	int good_count = 0;
2513 	nxge_mv_cfg_t *vlan_tbl;
2514 
2515 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_hw_vlan_config"));
2516 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2517 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2518 	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
2519 
2520 	param_arr = nxgep->param_arr;
2521 	prop = param_arr[param_vlan_2rdc_grp].fcode_name;
2522 
2523 	/*
2524 	 * By default, VLAN to RDC group mapping is disabled Need to read HW or
2525 	 * .conf properties to find out if mapping is required
2526 	 *
2527 	 * Format
2528 	 *
2529 	 * uint32_t array, each array entry specifying the VLAN id and the
2530 	 * mapping
2531 	 *
2532 	 * bit[30] = add bit[29] = remove bit[28]  = preference bits[23-16] =
2533 	 * rdcgrp bits[15-0] = VLAN ID ( )
2534 	 */
2535 
2536 	for (i = 0; i < NXGE_MAX_VLANS; i++) {
2537 		p_class_cfgp->vlan_tbl[i].flag = 0;
2538 	}
2539 
2540 	vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0];
2541 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
2542 			&vlan_cfg_val, &vlan_cnt) == DDI_PROP_SUCCESS) {
2543 		for (i = 0; i < vlan_cnt; i++) {
2544 			vmap = (nxge_param_map_t *)&vlan_cfg_val[i];
2545 			if ((vmap->param_id) &&
2546 					(vmap->param_id < NXGE_MAX_VLANS) &&
2547 					(vmap->map_to <
2548 						p_cfgp->max_rdc_grpids) &&
2549 					(vmap->map_to >= (uint8_t)0)) {
2550 				NXGE_DEBUG_MSG((nxgep, CFG2_CTL,
2551 					" nxge_vlan_config mapping"
2552 					" id %d grp %d",
2553 					vmap->param_id, vmap->map_to));
2554 				good_cfg[good_count] = vlan_cfg_val[i];
2555 				if (vlan_tbl[vmap->param_id].flag == 0)
2556 					good_count++;
2557 				vlan_tbl[vmap->param_id].flag = 1;
2558 				vlan_tbl[vmap->param_id].rdctbl =
2559 					vmap->map_to + p_cfgp->start_rdc_grpid;
2560 				vlan_tbl[vmap->param_id].mpr_npr = vmap->pref;
2561 			}
2562 		}
2563 		ddi_prop_free(vlan_cfg_val);
2564 		if (good_count != vlan_cnt) {
2565 			(void) ddi_prop_update_int_array(DDI_DEV_T_NONE,
2566 				nxgep->dip, prop, (int *)good_cfg, good_count);
2567 		}
2568 	}
2569 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_set_hw_vlan_config"));
2570 }
2571 
2572 static void
2573 nxge_set_hw_mac_class_config(p_nxge_t nxgep)
2574 {
2575 	int i;
2576 	p_nxge_dma_pt_cfg_t p_dma_cfgp;
2577 	p_nxge_hw_pt_cfg_t p_cfgp;
2578 	p_nxge_param_t param_arr;
2579 	uint_t mac_cnt;
2580 	int *mac_cfg_val;
2581 	nxge_param_map_t *mac_map;
2582 	char *prop;
2583 	p_nxge_class_pt_cfg_t p_class_cfgp;
2584 	int good_count = 0;
2585 	int good_cfg[NXGE_MAX_MACS];
2586 	nxge_mv_cfg_t *mac_host_info;
2587 
2588 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_set_hw_mac_config"));
2589 
2590 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2591 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2592 	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
2593 	mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0];
2594 
2595 	param_arr = nxgep->param_arr;
2596 	prop = param_arr[param_mac_2rdc_grp].fcode_name;
2597 
2598 	for (i = 0; i < NXGE_MAX_MACS; i++) {
2599 		p_class_cfgp->mac_host_info[i].flag = 0;
2600 		p_class_cfgp->mac_host_info[i].rdctbl =
2601 		    p_cfgp->def_mac_rxdma_grpid;
2602 	}
2603 
2604 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
2605 			&mac_cfg_val, &mac_cnt) == DDI_PROP_SUCCESS) {
2606 		for (i = 0; i < mac_cnt; i++) {
2607 			mac_map = (nxge_param_map_t *)&mac_cfg_val[i];
2608 			if ((mac_map->param_id < p_cfgp->max_macs) &&
2609 					(mac_map->map_to <
2610 						p_cfgp->max_rdc_grpids) &&
2611 					(mac_map->map_to >= (uint8_t)0)) {
2612 				NXGE_DEBUG_MSG((nxgep, CFG2_CTL,
2613 					" nxge_mac_config mapping"
2614 					" id %d grp %d",
2615 					mac_map->param_id, mac_map->map_to));
2616 				mac_host_info[mac_map->param_id].mpr_npr =
2617 					mac_map->pref;
2618 				mac_host_info[mac_map->param_id].rdctbl =
2619 					mac_map->map_to +
2620 					p_cfgp->start_rdc_grpid;
2621 				good_cfg[good_count] = mac_cfg_val[i];
2622 				if (mac_host_info[mac_map->param_id].flag == 0)
2623 					good_count++;
2624 				mac_host_info[mac_map->param_id].flag = 1;
2625 			}
2626 		}
2627 		ddi_prop_free(mac_cfg_val);
2628 		if (good_count != mac_cnt) {
2629 			(void) ddi_prop_update_int_array(DDI_DEV_T_NONE,
2630 				nxgep->dip, prop, good_cfg, good_count);
2631 		}
2632 	}
2633 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_set_hw_mac_config"));
2634 }
2635 
2636 static void
2637 nxge_set_hw_class_config(p_nxge_t nxgep)
2638 {
2639 	int i;
2640 	p_nxge_param_t param_arr;
2641 	int *int_prop_val;
2642 	uint32_t cfg_value;
2643 	char *prop;
2644 	p_nxge_class_pt_cfg_t p_class_cfgp;
2645 	int start_prop, end_prop;
2646 	uint_t prop_cnt;
2647 
2648 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_hw_class_config"));
2649 
2650 	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
2651 	param_arr = nxgep->param_arr;
2652 	start_prop = param_class_opt_ip_usr4;
2653 	end_prop = param_class_opt_ipv6_sctp;
2654 
2655 	for (i = start_prop; i <= end_prop; i++) {
2656 		prop = param_arr[i].fcode_name;
2657 		if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip,
2658 				0, prop, &int_prop_val,
2659 				&prop_cnt) == DDI_PROP_SUCCESS) {
2660 			cfg_value = (uint32_t)*int_prop_val;
2661 			ddi_prop_free(int_prop_val);
2662 		} else {
2663 			cfg_value = (uint32_t)param_arr[i].value;
2664 		}
2665 		p_class_cfgp->class_cfg[i - start_prop] = cfg_value;
2666 	}
2667 
2668 	prop = param_arr[param_h1_init_value].fcode_name;
2669 
2670 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
2671 			&int_prop_val, &prop_cnt) == DDI_PROP_SUCCESS) {
2672 		cfg_value = (uint32_t)*int_prop_val;
2673 		ddi_prop_free(int_prop_val);
2674 	} else {
2675 		cfg_value = (uint32_t)param_arr[param_h1_init_value].value;
2676 	}
2677 
2678 	p_class_cfgp->init_h1 = (uint32_t)cfg_value;
2679 	prop = param_arr[param_h2_init_value].fcode_name;
2680 
2681 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
2682 			&int_prop_val, &prop_cnt) == DDI_PROP_SUCCESS) {
2683 		cfg_value = (uint32_t)*int_prop_val;
2684 		ddi_prop_free(int_prop_val);
2685 	} else {
2686 		cfg_value = (uint32_t)param_arr[param_h2_init_value].value;
2687 	}
2688 
2689 	p_class_cfgp->init_h2 = (uint16_t)cfg_value;
2690 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_hw_class_config"));
2691 }
2692 
2693 nxge_status_t
2694 nxge_ldgv_init_n2(p_nxge_t nxgep, int *navail_p, int *nrequired_p)
2695 {
2696 	int i, maxldvs, maxldgs, start, end, nldvs;
2697 	int ldv, endldg;
2698 	uint8_t func;
2699 	uint8_t channel;
2700 	uint8_t chn_start;
2701 	boolean_t own_sys_err = B_FALSE, own_fzc = B_FALSE;
2702 	p_nxge_dma_pt_cfg_t p_dma_cfgp;
2703 	p_nxge_hw_pt_cfg_t p_cfgp;
2704 	p_nxge_ldgv_t ldgvp;
2705 	p_nxge_ldg_t ldgp, ptr;
2706 	p_nxge_ldv_t ldvp;
2707 	nxge_status_t status = NXGE_OK;
2708 
2709 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2"));
2710 	if (!*navail_p) {
2711 		*nrequired_p = 0;
2712 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2713 			"<== nxge_ldgv_init:no avail"));
2714 		return (NXGE_ERROR);
2715 	}
2716 	/*
2717 	 * N2/NIU: one logical device owns one logical group. and each
2718 	 * device/group will be assigned one vector by Hypervisor.
2719 	 */
2720 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2721 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2722 	maxldgs = p_cfgp->max_ldgs;
2723 	if (!maxldgs) {
2724 		/* No devices configured. */
2725 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_init_n2: "
2726 			"no logical groups configured."));
2727 		return (NXGE_ERROR);
2728 	} else {
2729 		maxldvs = maxldgs + 1;
2730 	}
2731 
2732 	/*
2733 	 * If function zero instance, it needs to handle the system and MIF
2734 	 * error interrupts. MIF interrupt may not be needed for N2/NIU.
2735 	 */
2736 	func = nxgep->function_num;
2737 	if (func == 0) {
2738 		own_sys_err = B_TRUE;
2739 		if (!p_cfgp->ser_ldvid) {
2740 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2741 				"nxge_ldgv_init_n2: func 0, ERR ID not set!"));
2742 		}
2743 		/* MIF interrupt */
2744 		if (!p_cfgp->mif_ldvid) {
2745 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2746 				"nxge_ldgv_init_n2: func 0, MIF ID not set!"));
2747 		}
2748 	}
2749 
2750 	/*
2751 	 * Assume single partition, each function owns mac.
2752 	 */
2753 	if (!nxge_use_partition)
2754 		own_fzc = B_TRUE;
2755 
2756 	ldgvp = nxgep->ldgvp;
2757 	if (ldgvp == NULL) {
2758 		ldgvp = KMEM_ZALLOC(sizeof (nxge_ldgv_t), KM_SLEEP);
2759 		nxgep->ldgvp = ldgvp;
2760 		ldgvp->maxldgs = (uint8_t)maxldgs;
2761 		ldgvp->maxldvs = (uint8_t)maxldvs;
2762 		ldgp = ldgvp->ldgp = KMEM_ZALLOC(sizeof (nxge_ldg_t) * maxldgs,
2763 			KM_SLEEP);
2764 		ldvp = ldgvp->ldvp = KMEM_ZALLOC(sizeof (nxge_ldv_t) * maxldvs,
2765 			KM_SLEEP);
2766 	} else {
2767 		ldgp = ldgvp->ldgp;
2768 		ldvp = ldgvp->ldvp;
2769 	}
2770 
2771 	ldgvp->ndma_ldvs = p_cfgp->max_tdcs + p_cfgp->max_rdcs;
2772 	ldgvp->tmres = NXGE_TIMER_RESO;
2773 
2774 	NXGE_DEBUG_MSG((nxgep, INT_CTL,
2775 		"==> nxge_ldgv_init_n2: maxldvs %d maxldgs %d",
2776 		maxldvs, maxldgs));
2777 
2778 	/* logical start_ldg is ldv */
2779 	ptr = ldgp;
2780 	for (i = 0; i < maxldgs; i++) {
2781 		ptr->func = func;
2782 		ptr->arm = B_TRUE;
2783 		ptr->vldg_index = (uint8_t)i;
2784 		ptr->ldg_timer = NXGE_TIMER_LDG;
2785 		ptr->ldg = p_cfgp->ldg[i];
2786 		ptr->sys_intr_handler = nxge_intr;
2787 		ptr->nldvs = 0;
2788 		ptr->ldvp = NULL;
2789 		ptr->nxgep = nxgep;
2790 		NXGE_DEBUG_MSG((nxgep, INT_CTL,
2791 			"==> nxge_ldgv_init_n2: maxldvs %d maxldgs %d "
2792 			"ldg %d ldgptr $%p",
2793 			maxldvs, maxldgs, ptr->ldg, ptr));
2794 		ptr++;
2795 	}
2796 
2797 	endldg = NXGE_INT_MAX_LDG;
2798 	nldvs = 0;
2799 	ldgvp->nldvs = 0;
2800 	ldgp->ldvp = NULL;
2801 	*nrequired_p = 0;
2802 
2803 	/*
2804 	 * logical device group table is organized in the following order (same
2805 	 * as what interrupt property has). function 0: owns MAC, MIF, error,
2806 	 * rx, tx. function 1: owns MAC, rx, tx.
2807 	 */
2808 
2809 	if (own_fzc && p_cfgp->mac_ldvid) {
2810 		/* Each function should own MAC interrupt */
2811 		ldv = p_cfgp->mac_ldvid;
2812 		ldvp->ldv = (uint8_t)ldv;
2813 		ldvp->is_mac = B_TRUE;
2814 		ldvp->ldv_intr_handler = nxge_mac_intr;
2815 		ldvp->ldv_ldf_masks = 0;
2816 		ldvp->nxgep = nxgep;
2817 		NXGE_DEBUG_MSG((nxgep, INT_CTL,
2818 			"==> nxge_ldgv_init_n2(mac): maxldvs %d ldv %d "
2819 			"ldg %d ldgptr $%p ldvptr $%p",
2820 			maxldvs, ldv, ldgp->ldg, ldgp, ldvp));
2821 		nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
2822 		nldvs++;
2823 	}
2824 
2825 	if (own_fzc && p_cfgp->mif_ldvid) {
2826 		ldv = p_cfgp->mif_ldvid;
2827 		ldvp->ldv = (uint8_t)ldv;
2828 		ldvp->is_mif = B_TRUE;
2829 		ldvp->ldv_intr_handler = nxge_mif_intr;
2830 		ldvp->ldv_ldf_masks = 0;
2831 		ldvp->nxgep = nxgep;
2832 		NXGE_DEBUG_MSG((nxgep, INT_CTL,
2833 			"==> nxge_ldgv_init_n2(mif): maxldvs %d ldv %d "
2834 			"ldg %d ldgptr $%p ldvptr $%p",
2835 			maxldvs, ldv, ldgp->ldg, ldgp, ldvp));
2836 		nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
2837 		nldvs++;
2838 	}
2839 
2840 	ldv = NXGE_SYS_ERROR_LD;
2841 	ldvp->use_timer = B_TRUE;
2842 	if (own_sys_err && p_cfgp->ser_ldvid) {
2843 		ldv = p_cfgp->ser_ldvid;
2844 		/*
2845 		 * Unmask the system interrupt states.
2846 		 */
2847 		(void) nxge_fzc_sys_err_mask_set(nxgep, SYS_ERR_SMX_MASK |
2848 			SYS_ERR_IPP_MASK | SYS_ERR_TXC_MASK |
2849 			SYS_ERR_ZCP_MASK);
2850 	}
2851 	ldvp->ldv = (uint8_t)ldv;
2852 	ldvp->is_syserr = B_TRUE;
2853 	ldvp->ldv_intr_handler = nxge_syserr_intr;
2854 	ldvp->ldv_ldf_masks = 0;
2855 	ldvp->nxgep = nxgep;
2856 	ldgvp->ldvp_syserr = ldvp;
2857 
2858 	NXGE_DEBUG_MSG((nxgep, INT_CTL,
2859 		"==> nxge_ldgv_init_n2(syserr): maxldvs %d ldv %d "
2860 		"ldg %d ldgptr $%p ldvptr p%p",
2861 		maxldvs, ldv, ldgp->ldg, ldgp, ldvp));
2862 
2863 	if (own_sys_err && p_cfgp->ser_ldvid) {
2864 		(void) nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
2865 	} else {
2866 		ldvp++;
2867 	}
2868 
2869 	nldvs++;
2870 
2871 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: "
2872 		"(before rx) func %d nldvs %d navail %d nrequired %d",
2873 		func, nldvs, *navail_p, *nrequired_p));
2874 
2875 	/*
2876 	 * Receive DMA channels.
2877 	 */
2878 	channel = p_cfgp->start_rdc;
2879 	start = p_cfgp->start_rdc + NXGE_RDMA_LD_START;
2880 	end = start + p_cfgp->max_rdcs;
2881 	chn_start = p_cfgp->ldg_chn_start;
2882 	/*
2883 	 * Start with RDC to configure logical devices for each group.
2884 	 */
2885 	for (i = 0, ldv = start; ldv < end; i++, ldv++, chn_start++) {
2886 		ldvp->is_rxdma = B_TRUE;
2887 		ldvp->ldv = (uint8_t)ldv;
2888 		ldvp->channel = channel++;
2889 		ldvp->vdma_index = (uint8_t)i;
2890 		ldvp->ldv_intr_handler = nxge_rx_intr;
2891 		ldvp->ldv_ldf_masks = 0;
2892 		ldvp->nxgep = nxgep;
2893 		ldgp->ldg = p_cfgp->ldg[chn_start];
2894 
2895 		NXGE_DEBUG_MSG((nxgep, INT_CTL,
2896 			"==> nxge_ldgv_init_n2(rx%d): maxldvs %d ldv %d "
2897 			"ldg %d ldgptr 0x%016llx ldvptr 0x%016llx",
2898 			i, maxldvs, ldv, ldgp->ldg, ldgp, ldvp));
2899 		nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
2900 		nldvs++;
2901 	}
2902 
2903 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: "
2904 		"func %d nldvs %d navail %d nrequired %d",
2905 		func, nldvs, *navail_p, *nrequired_p));
2906 
2907 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: "
2908 		"func %d nldvs %d navail %d nrequired %d ldgp 0x%llx "
2909 		"ldvp 0x%llx",
2910 		func, nldvs, *navail_p, *nrequired_p, ldgp, ldvp));
2911 	/*
2912 	 * Transmit DMA channels.
2913 	 */
2914 	channel = p_cfgp->start_tdc;
2915 	start = p_cfgp->start_tdc + NXGE_TDMA_LD_START;
2916 	end = start + p_cfgp->max_tdcs;
2917 	for (i = 0, ldv = start; ldv < end; i++, ldv++, chn_start++) {
2918 		ldvp->is_txdma = B_TRUE;
2919 		ldvp->ldv = (uint8_t)ldv;
2920 		ldvp->channel = channel++;
2921 		ldvp->vdma_index = (uint8_t)i;
2922 		ldvp->ldv_intr_handler = nxge_tx_intr;
2923 		ldvp->ldv_ldf_masks = 0;
2924 		ldgp->ldg = p_cfgp->ldg[chn_start];
2925 		ldvp->nxgep = nxgep;
2926 		NXGE_DEBUG_MSG((nxgep, INT_CTL,
2927 			"==> nxge_ldgv_init_n2(tx%d): maxldvs %d ldv %d "
2928 			"ldg %d ldgptr 0x%016llx ldvptr 0x%016llx",
2929 			i, maxldvs, ldv, ldgp->ldg, ldgp, ldvp));
2930 		nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
2931 		nldvs++;
2932 	}
2933 
2934 	ldgvp->ldg_intrs = *nrequired_p;
2935 	ldgvp->nldvs = (uint8_t)nldvs;
2936 
2937 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: "
2938 		"func %d nldvs %d maxgrps %d navail %d nrequired %d",
2939 		func, nldvs, maxldgs, *navail_p, *nrequired_p));
2940 
2941 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_init_n2"));
2942 	return (status);
2943 }
2944 
2945 /*
2946  * Interrupts related interface functions.
2947  */
2948 
2949 nxge_status_t
2950 nxge_ldgv_init(p_nxge_t nxgep, int *navail_p, int *nrequired_p)
2951 {
2952 	int i, maxldvs, maxldgs, start, end, nldvs;
2953 	int ldv, ldg, endldg, ngrps;
2954 	uint8_t func;
2955 	uint8_t channel;
2956 	boolean_t own_sys_err = B_FALSE, own_fzc = B_FALSE;
2957 	p_nxge_dma_pt_cfg_t p_dma_cfgp;
2958 	p_nxge_hw_pt_cfg_t p_cfgp;
2959 	p_nxge_ldgv_t ldgvp;
2960 	p_nxge_ldg_t ldgp, ptr;
2961 	p_nxge_ldv_t ldvp;
2962 	nxge_status_t status = NXGE_OK;
2963 
2964 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init"));
2965 	if (!*navail_p) {
2966 		*nrequired_p = 0;
2967 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2968 			"<== nxge_ldgv_init:no avail"));
2969 		return (NXGE_ERROR);
2970 	}
2971 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2972 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2973 
2974 	nldvs = p_cfgp->max_tdcs + p_cfgp->max_rdcs;
2975 
2976 	/*
2977 	 * If function zero instance, it needs to handle the system error
2978 	 * interrupts.
2979 	 */
2980 	func = nxgep->function_num;
2981 	if (func == 0) {
2982 		nldvs++;
2983 		own_sys_err = B_TRUE;
2984 	} else {
2985 		/* use timer */
2986 		nldvs++;
2987 	}
2988 
2989 	/*
2990 	 * Assume single partition, each function owns mac.
2991 	 */
2992 	if (!nxge_use_partition) {
2993 		/* mac */
2994 		nldvs++;
2995 		/* MIF */
2996 		nldvs++;
2997 		own_fzc = B_TRUE;
2998 	}
2999 	maxldvs = nldvs;
3000 	maxldgs = p_cfgp->max_ldgs;
3001 	if (!maxldvs || !maxldgs) {
3002 		/* No devices configured. */
3003 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_init: "
3004 			"no logical devices or groups configured."));
3005 		return (NXGE_ERROR);
3006 	}
3007 	ldgvp = nxgep->ldgvp;
3008 	if (ldgvp == NULL) {
3009 		ldgvp = KMEM_ZALLOC(sizeof (nxge_ldgv_t), KM_SLEEP);
3010 		nxgep->ldgvp = ldgvp;
3011 		ldgvp->maxldgs = (uint8_t)maxldgs;
3012 		ldgvp->maxldvs = (uint8_t)maxldvs;
3013 		ldgp = ldgvp->ldgp = KMEM_ZALLOC(sizeof (nxge_ldg_t) * maxldgs,
3014 			KM_SLEEP);
3015 		ldvp = ldgvp->ldvp = KMEM_ZALLOC(sizeof (nxge_ldv_t) * maxldvs,
3016 			KM_SLEEP);
3017 	}
3018 	ldgvp->ndma_ldvs = p_cfgp->max_tdcs + p_cfgp->max_rdcs;
3019 	ldgvp->tmres = NXGE_TIMER_RESO;
3020 
3021 	NXGE_DEBUG_MSG((nxgep, INT_CTL,
3022 		"==> nxge_ldgv_init: maxldvs %d maxldgs %d nldvs %d",
3023 		maxldvs, maxldgs, nldvs));
3024 	ldg = p_cfgp->start_ldg;
3025 	ptr = ldgp;
3026 	for (i = 0; i < maxldgs; i++) {
3027 		ptr->func = func;
3028 		ptr->arm = B_TRUE;
3029 		ptr->vldg_index = (uint8_t)i;
3030 		ptr->ldg_timer = NXGE_TIMER_LDG;
3031 		ptr->ldg = ldg++;
3032 		ptr->sys_intr_handler = nxge_intr;
3033 		ptr->nldvs = 0;
3034 		ptr->nxgep = nxgep;
3035 		NXGE_DEBUG_MSG((nxgep, INT_CTL,
3036 			"==> nxge_ldgv_init: maxldvs %d maxldgs %d ldg %d",
3037 			maxldvs, maxldgs, ptr->ldg));
3038 		ptr++;
3039 	}
3040 
3041 	ldg = p_cfgp->start_ldg;
3042 	if (maxldgs > *navail_p) {
3043 		ngrps = *navail_p;
3044 	} else {
3045 		ngrps = maxldgs;
3046 	}
3047 	endldg = ldg + ngrps;
3048 
3049 	/*
3050 	 * Receive DMA channels.
3051 	 */
3052 	channel = p_cfgp->start_rdc;
3053 	start = p_cfgp->start_rdc + NXGE_RDMA_LD_START;
3054 	end = start + p_cfgp->max_rdcs;
3055 	nldvs = 0;
3056 	ldgvp->nldvs = 0;
3057 	ldgp->ldvp = NULL;
3058 	*nrequired_p = 0;
3059 
3060 	/*
3061 	 * Start with RDC to configure logical devices for each group.
3062 	 */
3063 	for (i = 0, ldv = start; ldv < end; i++, ldv++) {
3064 		ldvp->is_rxdma = B_TRUE;
3065 		ldvp->ldv = (uint8_t)ldv;
3066 		/* If non-seq needs to change the following code */
3067 		ldvp->channel = channel++;
3068 		ldvp->vdma_index = (uint8_t)i;
3069 		ldvp->ldv_intr_handler = nxge_rx_intr;
3070 		ldvp->ldv_ldf_masks = 0;
3071 		ldvp->use_timer = B_FALSE;
3072 		ldvp->nxgep = nxgep;
3073 		nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
3074 		nldvs++;
3075 	}
3076 
3077 	/*
3078 	 * Transmit DMA channels.
3079 	 */
3080 	channel = p_cfgp->start_tdc;
3081 	start = p_cfgp->start_tdc + NXGE_TDMA_LD_START;
3082 	end = start + p_cfgp->max_tdcs;
3083 	for (i = 0, ldv = start; ldv < end; i++, ldv++) {
3084 		ldvp->is_txdma = B_TRUE;
3085 		ldvp->ldv = (uint8_t)ldv;
3086 		ldvp->channel = channel++;
3087 		ldvp->vdma_index = (uint8_t)i;
3088 		ldvp->ldv_intr_handler = nxge_tx_intr;
3089 		ldvp->ldv_ldf_masks = 0;
3090 		ldvp->use_timer = B_FALSE;
3091 		ldvp->nxgep = nxgep;
3092 		nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
3093 		nldvs++;
3094 	}
3095 
3096 	if (own_fzc) {
3097 		ldv = NXGE_MIF_LD;
3098 		ldvp->ldv = (uint8_t)ldv;
3099 		ldvp->is_mif = B_TRUE;
3100 		ldvp->ldv_intr_handler = nxge_mif_intr;
3101 		ldvp->ldv_ldf_masks = 0;
3102 		ldvp->use_timer = B_FALSE;
3103 		ldvp->nxgep = nxgep;
3104 		nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
3105 		nldvs++;
3106 	}
3107 	/*
3108 	 * MAC port (function zero control)
3109 	 */
3110 	if (own_fzc) {
3111 		ldvp->is_mac = B_TRUE;
3112 		ldvp->ldv_intr_handler = nxge_mac_intr;
3113 		ldvp->ldv_ldf_masks = 0;
3114 		ldv = func + NXGE_MAC_LD_START;
3115 		ldvp->ldv = (uint8_t)ldv;
3116 		ldvp->use_timer = B_FALSE;
3117 		ldvp->nxgep = nxgep;
3118 		nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
3119 		nldvs++;
3120 	}
3121 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init: "
3122 		"func %d nldvs %d navail %d nrequired %d",
3123 		func, nldvs, *navail_p, *nrequired_p));
3124 	/*
3125 	 * Function 0 owns system error interrupts.
3126 	 */
3127 	ldvp->use_timer = B_TRUE;
3128 	if (own_sys_err) {
3129 		ldv = NXGE_SYS_ERROR_LD;
3130 		ldvp->ldv = (uint8_t)ldv;
3131 		ldvp->is_syserr = B_TRUE;
3132 		ldvp->ldv_intr_handler = nxge_syserr_intr;
3133 		ldvp->ldv_ldf_masks = 0;
3134 		ldvp->nxgep = nxgep;
3135 		ldgvp->ldvp_syserr = ldvp;
3136 		/*
3137 		 * Unmask the system interrupt states.
3138 		 */
3139 		(void) nxge_fzc_sys_err_mask_set(nxgep, SYS_ERR_SMX_MASK |
3140 			SYS_ERR_IPP_MASK | SYS_ERR_TXC_MASK |
3141 			SYS_ERR_ZCP_MASK);
3142 
3143 		(void) nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
3144 		nldvs++;
3145 	} else {
3146 		ldv = NXGE_SYS_ERROR_LD;
3147 		ldvp->ldv = (uint8_t)ldv;
3148 		ldvp->is_syserr = B_TRUE;
3149 		ldvp->ldv_intr_handler = nxge_syserr_intr;
3150 		ldvp->nxgep = nxgep;
3151 		ldvp->ldv_ldf_masks = 0;
3152 		ldgvp->ldvp_syserr = ldvp;
3153 	}
3154 
3155 	ldgvp->ldg_intrs = *nrequired_p;
3156 
3157 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init: "
3158 		"func %d nldvs %d navail %d nrequired %d",
3159 		func, nldvs, *navail_p, *nrequired_p));
3160 
3161 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_init"));
3162 	return (status);
3163 }
3164 
3165 nxge_status_t
3166 nxge_ldgv_uninit(p_nxge_t nxgep)
3167 {
3168 	p_nxge_ldgv_t ldgvp;
3169 
3170 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_uninit"));
3171 	ldgvp = nxgep->ldgvp;
3172 	if (ldgvp == NULL) {
3173 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_uninit: "
3174 				"no logical group configured."));
3175 		return (NXGE_OK);
3176 	}
3177 	if (ldgvp->ldgp) {
3178 		KMEM_FREE(ldgvp->ldgp, sizeof (nxge_ldg_t) * ldgvp->maxldgs);
3179 	}
3180 	if (ldgvp->ldvp) {
3181 		KMEM_FREE(ldgvp->ldvp, sizeof (nxge_ldv_t) * ldgvp->maxldvs);
3182 	}
3183 	KMEM_FREE(ldgvp, sizeof (nxge_ldgv_t));
3184 	nxgep->ldgvp = NULL;
3185 
3186 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_uninit"));
3187 	return (NXGE_OK);
3188 }
3189 
3190 nxge_status_t
3191 nxge_intr_ldgv_init(p_nxge_t nxgep)
3192 {
3193 	nxge_status_t status = NXGE_OK;
3194 
3195 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_ldgv_init"));
3196 	/*
3197 	 * Configure the logical device group numbers, state vectors and
3198 	 * interrupt masks for each logical device.
3199 	 */
3200 	status = nxge_fzc_intr_init(nxgep);
3201 
3202 	/*
3203 	 * Configure logical device masks and timers.
3204 	 */
3205 	status = nxge_intr_mask_mgmt(nxgep);
3206 
3207 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_ldgv_init"));
3208 	return (status);
3209 }
3210 
3211 nxge_status_t
3212 nxge_intr_mask_mgmt(p_nxge_t nxgep)
3213 {
3214 	p_nxge_ldgv_t ldgvp;
3215 	p_nxge_ldg_t ldgp;
3216 	p_nxge_ldv_t ldvp;
3217 	npi_handle_t handle;
3218 	int i, j;
3219 	npi_status_t rs = NPI_SUCCESS;
3220 
3221 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_mask_mgmt"));
3222 
3223 	if ((ldgvp = nxgep->ldgvp) == NULL) {
3224 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3225 			"<== nxge_intr_mask_mgmt: Null ldgvp"));
3226 		return (NXGE_ERROR);
3227 	}
3228 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
3229 	ldgp = ldgvp->ldgp;
3230 	ldvp = ldgvp->ldvp;
3231 	if (ldgp == NULL || ldvp == NULL) {
3232 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3233 			"<== nxge_intr_mask_mgmt: Null ldgp or ldvp"));
3234 		return (NXGE_ERROR);
3235 	}
3236 	NXGE_DEBUG_MSG((nxgep, INT_CTL,
3237 		"==> nxge_intr_mask_mgmt: # of intrs %d ", ldgvp->ldg_intrs));
3238 	/* Initialize masks. */
3239 	if (nxgep->niu_type != N2_NIU) {
3240 		NXGE_DEBUG_MSG((nxgep, INT_CTL,
3241 			"==> nxge_intr_mask_mgmt(Neptune): # intrs %d ",
3242 			ldgvp->ldg_intrs));
3243 		for (i = 0; i < ldgvp->ldg_intrs; i++, ldgp++) {
3244 			NXGE_DEBUG_MSG((nxgep, INT_CTL,
3245 				"==> nxge_intr_mask_mgmt(Neptune): # ldv %d "
3246 				"in group %d", ldgp->nldvs, ldgp->ldg));
3247 			for (j = 0; j < ldgp->nldvs; j++, ldvp++) {
3248 				NXGE_DEBUG_MSG((nxgep, INT_CTL,
3249 					"==> nxge_intr_mask_mgmt: set ldv # %d "
3250 					"for ldg %d", ldvp->ldv, ldgp->ldg));
3251 				rs = npi_intr_mask_set(handle, ldvp->ldv,
3252 					ldvp->ldv_ldf_masks);
3253 				if (rs != NPI_SUCCESS) {
3254 					NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3255 						"<== nxge_intr_mask_mgmt: "
3256 						"set mask failed "
3257 						" rs 0x%x ldv %d mask 0x%x",
3258 						rs, ldvp->ldv,
3259 						ldvp->ldv_ldf_masks));
3260 					return (NXGE_ERROR | rs);
3261 				}
3262 				NXGE_DEBUG_MSG((nxgep, INT_CTL,
3263 					"==> nxge_intr_mask_mgmt: "
3264 					"set mask OK "
3265 					" rs 0x%x ldv %d mask 0x%x",
3266 					rs, ldvp->ldv,
3267 					ldvp->ldv_ldf_masks));
3268 			}
3269 		}
3270 	}
3271 	ldgp = ldgvp->ldgp;
3272 	/* Configure timer and arm bit */
3273 	for (i = 0; i < nxgep->ldgvp->ldg_intrs; i++, ldgp++) {
3274 		rs = npi_intr_ldg_mgmt_set(handle, ldgp->ldg,
3275 			ldgp->arm, ldgp->ldg_timer);
3276 		if (rs != NPI_SUCCESS) {
3277 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3278 				"<== nxge_intr_mask_mgmt: "
3279 				"set timer failed "
3280 				" rs 0x%x dg %d timer 0x%x",
3281 				rs, ldgp->ldg, ldgp->ldg_timer));
3282 			return (NXGE_ERROR | rs);
3283 		}
3284 		NXGE_DEBUG_MSG((nxgep, INT_CTL,
3285 			"==> nxge_intr_mask_mgmt: "
3286 			"set timer OK "
3287 			" rs 0x%x ldg %d timer 0x%x",
3288 			rs, ldgp->ldg, ldgp->ldg_timer));
3289 	}
3290 
3291 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_fzc_intr_mask_mgmt"));
3292 	return (NXGE_OK);
3293 }
3294 
3295 nxge_status_t
3296 nxge_intr_mask_mgmt_set(p_nxge_t nxgep, boolean_t on)
3297 {
3298 	p_nxge_ldgv_t ldgvp;
3299 	p_nxge_ldg_t ldgp;
3300 	p_nxge_ldv_t ldvp;
3301 	npi_handle_t handle;
3302 	int i, j;
3303 	npi_status_t rs = NPI_SUCCESS;
3304 
3305 	NXGE_DEBUG_MSG((nxgep, INT_CTL,
3306 		"==> nxge_intr_mask_mgmt_set (%d)", on));
3307 
3308 	if (nxgep->niu_type == N2_NIU) {
3309 		NXGE_DEBUG_MSG((nxgep, INT_CTL,
3310 			"<== nxge_intr_mask_mgmt_set (%d) not set (N2/NIU)",
3311 			on));
3312 		return (NXGE_ERROR);
3313 	}
3314 
3315 	if ((ldgvp = nxgep->ldgvp) == NULL) {
3316 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3317 			"==> nxge_intr_mask_mgmt_set: Null ldgvp"));
3318 		return (NXGE_ERROR);
3319 	}
3320 
3321 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
3322 	ldgp = ldgvp->ldgp;
3323 	ldvp = ldgvp->ldvp;
3324 	if (ldgp == NULL || ldvp == NULL) {
3325 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3326 			"<== nxge_intr_mask_mgmt_set: Null ldgp or ldvp"));
3327 		return (NXGE_ERROR);
3328 	}
3329 	/* set masks. */
3330 	for (i = 0; i < ldgvp->ldg_intrs; i++, ldgp++) {
3331 		NXGE_DEBUG_MSG((nxgep, INT_CTL,
3332 			"==> nxge_intr_mask_mgmt_set: flag %d ldg %d"
3333 			"set mask nldvs %d", on, ldgp->ldg, ldgp->nldvs));
3334 		for (j = 0; j < ldgp->nldvs; j++, ldvp++) {
3335 			NXGE_DEBUG_MSG((nxgep, INT_CTL,
3336 				"==> nxge_intr_mask_mgmt_set: "
3337 				"for %d %d flag %d", i, j, on));
3338 			if (on) {
3339 				ldvp->ldv_ldf_masks = 0;
3340 				NXGE_DEBUG_MSG((nxgep, INT_CTL,
3341 					"==> nxge_intr_mask_mgmt_set: "
3342 					"ON mask off"));
3343 			} else if (!on) {
3344 				ldvp->ldv_ldf_masks = (uint8_t)LD_IM1_MASK;
3345 				NXGE_DEBUG_MSG((nxgep, INT_CTL,
3346 					"==> nxge_intr_mask_mgmt_set:mask on"));
3347 			}
3348 			rs = npi_intr_mask_set(handle, ldvp->ldv,
3349 				ldvp->ldv_ldf_masks);
3350 			if (rs != NPI_SUCCESS) {
3351 				NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3352 					"==> nxge_intr_mask_mgmt_set: "
3353 					"set mask failed "
3354 					" rs 0x%x ldv %d mask 0x%x",
3355 					rs, ldvp->ldv, ldvp->ldv_ldf_masks));
3356 				return (NXGE_ERROR | rs);
3357 			}
3358 			NXGE_DEBUG_MSG((nxgep, INT_CTL,
3359 				"==> nxge_intr_mask_mgmt_set: flag %d"
3360 				"set mask OK "
3361 				" ldv %d mask 0x%x",
3362 				on, ldvp->ldv, ldvp->ldv_ldf_masks));
3363 		}
3364 	}
3365 
3366 	ldgp = ldgvp->ldgp;
3367 	/* set the arm bit */
3368 	for (i = 0; i < nxgep->ldgvp->ldg_intrs; i++, ldgp++) {
3369 		if (on && !ldgp->arm) {
3370 			ldgp->arm = B_TRUE;
3371 		} else if (!on && ldgp->arm) {
3372 			ldgp->arm = B_FALSE;
3373 		}
3374 		rs = npi_intr_ldg_mgmt_set(handle, ldgp->ldg,
3375 			ldgp->arm, ldgp->ldg_timer);
3376 		if (rs != NPI_SUCCESS) {
3377 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3378 				"<== nxge_intr_mask_mgmt_set: "
3379 				"set timer failed "
3380 				" rs 0x%x ldg %d timer 0x%x",
3381 				rs, ldgp->ldg, ldgp->ldg_timer));
3382 			return (NXGE_ERROR | rs);
3383 		}
3384 		NXGE_DEBUG_MSG((nxgep, INT_CTL,
3385 			"==> nxge_intr_mask_mgmt_set: OK (flag %d) "
3386 			"set timer "
3387 			" ldg %d timer 0x%x",
3388 			on, ldgp->ldg, ldgp->ldg_timer));
3389 	}
3390 
3391 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_mask_mgmt_set"));
3392 	return (NXGE_OK);
3393 }
3394 
3395 static nxge_status_t
3396 nxge_get_mac_addr_properties(p_nxge_t nxgep)
3397 {
3398 #if defined(_BIG_ENDIAN)
3399 	uchar_t *prop_val;
3400 	uint_t prop_len;
3401 	uint_t j;
3402 #endif
3403 	uint_t i;
3404 	uint8_t func_num;
3405 	boolean_t compute_macs = B_TRUE;
3406 
3407 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_get_mac_addr_properties "));
3408 
3409 #if defined(_BIG_ENDIAN)
3410 	/*
3411 	 * Get the ethernet address.
3412 	 */
3413 	(void) localetheraddr((struct ether_addr *)NULL, &nxgep->ouraddr);
3414 
3415 	/*
3416 	 * Check if it is an adapter with its own local mac address If it is
3417 	 * present, override the system mac address.
3418 	 */
3419 	if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
3420 			"local-mac-address", &prop_val,
3421 			&prop_len) == DDI_PROP_SUCCESS) {
3422 		if (prop_len == ETHERADDRL) {
3423 			nxgep->factaddr = *(p_ether_addr_t)prop_val;
3424 			NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Local mac address = "
3425 				"%02x:%02x:%02x:%02x:%02x:%02x",
3426 				prop_val[0], prop_val[1], prop_val[2],
3427 				prop_val[3], prop_val[4], prop_val[5]));
3428 		}
3429 		ddi_prop_free(prop_val);
3430 	}
3431 	if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
3432 			"local-mac-address?", &prop_val,
3433 			&prop_len) == DDI_PROP_SUCCESS) {
3434 		if (strncmp("true", (caddr_t)prop_val, (size_t)prop_len) == 0) {
3435 			nxgep->ouraddr = nxgep->factaddr;
3436 			NXGE_DEBUG_MSG((nxgep, DDI_CTL,
3437 				"Using local MAC address"));
3438 		}
3439 		ddi_prop_free(prop_val);
3440 	} else {
3441 		nxgep->ouraddr = nxgep->factaddr;
3442 	}
3443 
3444 	if ((!nxgep->vpd_info.present) ||
3445 	    (nxge_is_valid_local_mac(nxgep->factaddr)))
3446 		goto got_mac_addr;
3447 
3448 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "nxge_get_mac_addr_properties: "
3449 	    "MAC address from properties is not valid...reading from PROM"));
3450 
3451 #endif
3452 	if (!nxgep->vpd_info.ver_valid) {
3453 		(void) nxge_espc_mac_addrs_get(nxgep);
3454 		if (!nxge_is_valid_local_mac(nxgep->factaddr)) {
3455 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Failed to get "
3456 			    "MAC address"));
3457 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "EEPROM version "
3458 			    "[%s] invalid...please update",
3459 			    nxgep->vpd_info.ver));
3460 			return (NXGE_ERROR);
3461 		}
3462 		nxgep->ouraddr = nxgep->factaddr;
3463 		goto got_mac_addr;
3464 	}
3465 	/*
3466 	 * First get the MAC address from the info in the VPD data read
3467 	 * from the EEPROM.
3468 	 */
3469 	nxge_espc_get_next_mac_addr(nxgep->vpd_info.mac_addr,
3470 	    nxgep->function_num, &nxgep->factaddr);
3471 
3472 	if (!nxge_is_valid_local_mac(nxgep->factaddr)) {
3473 		NXGE_DEBUG_MSG((nxgep, DDI_CTL,
3474 		    "nxge_get_mac_addr_properties: "
3475 		    "MAC address in EEPROM VPD data not valid"
3476 		    "...reading from NCR registers"));
3477 		(void) nxge_espc_mac_addrs_get(nxgep);
3478 		if (!nxge_is_valid_local_mac(nxgep->factaddr)) {
3479 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Failed to get "
3480 			    "MAC address"));
3481 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "EEPROM version "
3482 			    "[%s] invalid...please update",
3483 			    nxgep->vpd_info.ver));
3484 			return (NXGE_ERROR);
3485 		}
3486 	}
3487 
3488 	nxgep->ouraddr = nxgep->factaddr;
3489 
3490 got_mac_addr:
3491 	func_num = nxgep->function_num;
3492 
3493 	/*
3494 	 * Note: mac-addresses property is the list of mac addresses for a
3495 	 * port. NXGE_MAX_MMAC_ADDRS is the total number of MAC addresses
3496 	 * allocated for a board.
3497 	 */
3498 	nxgep->nxge_mmac_info.total_factory_macs = NXGE_MAX_MMAC_ADDRS;
3499 
3500 #if defined(_BIG_ENDIAN)
3501 	if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
3502 	    "mac-addresses", &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
3503 		/*
3504 		 * XAUI may have up to 18 MACs, more than the XMAC can
3505 		 * use (1 unique MAC plus 16 alternate MACs)
3506 		 */
3507 		nxgep->nxge_mmac_info.num_factory_mmac =
3508 		    prop_len / ETHERADDRL - 1;
3509 		if (nxgep->nxge_mmac_info.num_factory_mmac >
3510 		    XMAC_MAX_ALT_ADDR_ENTRY) {
3511 			nxgep->nxge_mmac_info.num_factory_mmac =
3512 			    XMAC_MAX_ALT_ADDR_ENTRY;
3513 		}
3514 
3515 		for (i = 1; i <= nxgep->nxge_mmac_info.num_factory_mmac; i++) {
3516 			for (j = 0; j < ETHERADDRL; j++) {
3517 				nxgep->nxge_mmac_info.factory_mac_pool[i][j] =
3518 				    *(prop_val + (i * ETHERADDRL) + j);
3519 			}
3520 			NXGE_DEBUG_MSG((nxgep, DDI_CTL,
3521 			    "nxge_get_mac_addr_properties: Alt mac[%d] from "
3522 			    "mac-addresses property[%2x:%2x:%2x:%2x:%2x:%2x]",
3523 			    i, nxgep->nxge_mmac_info.factory_mac_pool[i][0],
3524 			    nxgep->nxge_mmac_info.factory_mac_pool[i][1],
3525 			    nxgep->nxge_mmac_info.factory_mac_pool[i][2],
3526 			    nxgep->nxge_mmac_info.factory_mac_pool[i][3],
3527 			    nxgep->nxge_mmac_info.factory_mac_pool[i][4],
3528 			    nxgep->nxge_mmac_info.factory_mac_pool[i][5]));
3529 		}
3530 
3531 		compute_macs = B_FALSE;
3532 		ddi_prop_free(prop_val);
3533 		goto got_mmac_info;
3534 	}
3535 #endif
3536 	/*
3537 	 * total_factory_macs = 32
3538 	 * num_factory_mmac = (32 >> (nports/2)) - 1
3539 	 * So if nports = 4, then num_factory_mmac =  7
3540 	 *    if nports = 2, then num_factory_mmac = 15
3541 	 */
3542 	nxgep->nxge_mmac_info.num_factory_mmac =
3543 	    ((nxgep->nxge_mmac_info.total_factory_macs >>
3544 	    (nxgep->nports >> 1))) - 1;
3545 
3546 got_mmac_info:
3547 
3548 	if ((nxgep->function_num < 2) &&
3549 	    (nxgep->nxge_mmac_info.num_factory_mmac >
3550 	    XMAC_MAX_ALT_ADDR_ENTRY)) {
3551 		nxgep->nxge_mmac_info.num_factory_mmac =
3552 		    XMAC_MAX_ALT_ADDR_ENTRY;
3553 	} else if ((nxgep->function_num > 1) &&
3554 	    (nxgep->nxge_mmac_info.num_factory_mmac >
3555 	    BMAC_MAX_ALT_ADDR_ENTRY)) {
3556 		nxgep->nxge_mmac_info.num_factory_mmac =
3557 		    BMAC_MAX_ALT_ADDR_ENTRY;
3558 	}
3559 
3560 	for (i = 0; i <= nxgep->nxge_mmac_info.num_mmac; i++) {
3561 		(void) npi_mac_altaddr_disable(nxgep->npi_handle,
3562 			NXGE_GET_PORT_NUM(func_num), i);
3563 	}
3564 
3565 	(void) nxge_init_mmac(nxgep, compute_macs);
3566 	return (NXGE_OK);
3567 }
3568 
3569 void
3570 nxge_get_xcvr_properties(p_nxge_t nxgep)
3571 {
3572 	uchar_t *prop_val;
3573 	uint_t prop_len;
3574 
3575 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_get_xcvr_properties"));
3576 
3577 	/*
3578 	 * Read the type of physical layer interface being used.
3579 	 */
3580 	nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR;
3581 	if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
3582 			"phy-type", &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
3583 		if (strncmp("pcs", (caddr_t)prop_val,
3584 				(size_t)prop_len) == 0) {
3585 			nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR;
3586 		} else {
3587 			nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR;
3588 		}
3589 		ddi_prop_free(prop_val);
3590 	} else if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
3591 			"phy-interface", &prop_val,
3592 			&prop_len) == DDI_PROP_SUCCESS) {
3593 		if (strncmp("pcs", (caddr_t)prop_val, (size_t)prop_len) == 0) {
3594 			nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR;
3595 		} else {
3596 			nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR;
3597 		}
3598 		ddi_prop_free(prop_val);
3599 	}
3600 }
3601 
3602 /*
3603  * Static functions start here.
3604  */
3605 
3606 static void
3607 nxge_ldgv_setup(p_nxge_ldg_t *ldgp, p_nxge_ldv_t *ldvp, uint8_t ldv,
3608 	uint8_t endldg, int *ngrps)
3609 {
3610 	NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup"));
3611 	/* Assign the group number for each device. */
3612 	(*ldvp)->ldg_assigned = (*ldgp)->ldg;
3613 	(*ldvp)->ldgp = *ldgp;
3614 	(*ldvp)->ldv = ldv;
3615 
3616 	NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup: "
3617 		"ldv %d endldg %d ldg %d, ldvp $%p",
3618 		ldv, endldg, (*ldgp)->ldg, (*ldgp)->ldvp));
3619 
3620 	(*ldgp)->nldvs++;
3621 	if ((*ldgp)->ldg == (endldg - 1)) {
3622 		if ((*ldgp)->ldvp == NULL) {
3623 			(*ldgp)->ldvp = *ldvp;
3624 			*ngrps += 1;
3625 			NXGE_DEBUG_MSG((NULL, INT_CTL,
3626 				"==> nxge_ldgv_setup: ngrps %d", *ngrps));
3627 		}
3628 		NXGE_DEBUG_MSG((NULL, INT_CTL,
3629 			"==> nxge_ldgv_setup: ldvp $%p ngrps %d",
3630 			*ldvp, *ngrps));
3631 		++*ldvp;
3632 	} else {
3633 		(*ldgp)->ldvp = *ldvp;
3634 		*ngrps += 1;
3635 		NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup(done): "
3636 			"ldv %d endldg %d ldg %d, ldvp $%p",
3637 			ldv, endldg, (*ldgp)->ldg, (*ldgp)->ldvp));
3638 		(*ldvp) = ++*ldvp;
3639 		(*ldgp) = ++*ldgp;
3640 		NXGE_DEBUG_MSG((NULL, INT_CTL,
3641 			"==> nxge_ldgv_setup: new ngrps %d", *ngrps));
3642 	}
3643 
3644 	NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup: "
3645 		"ldv %d ldvp $%p endldg %d ngrps %d",
3646 		ldv, ldvp, endldg, *ngrps));
3647 
3648 	NXGE_DEBUG_MSG((NULL, INT_CTL, "<== nxge_ldgv_setup"));
3649 }
3650 
3651 /*
3652  * Note: This function assumes the following distribution of mac
3653  * addresses among 4 ports in neptune:
3654  *
3655  *      -------------
3656  *    0|            |0 - local-mac-address for fn 0
3657  *      -------------
3658  *    1|            |1 - local-mac-address for fn 1
3659  *      -------------
3660  *    2|            |2 - local-mac-address for fn 2
3661  *      -------------
3662  *    3|            |3 - local-mac-address for fn 3
3663  *      -------------
3664  *     |            |4 - Start of alt. mac addr. for fn 0
3665  *     |            |
3666  *     |            |
3667  *     |            |10
3668  *     --------------
3669  *     |            |11 - Start of alt. mac addr. for fn 1
3670  *     |            |
3671  *     |            |
3672  *     |            |17
3673  *     --------------
3674  *     |            |18 - Start of alt. mac addr. for fn 2
3675  *     |            |
3676  *     |            |
3677  *     |            |24
3678  *     --------------
3679  *     |            |25 - Start of alt. mac addr. for fn 3
3680  *     |            |
3681  *     |            |
3682  *     |            |31
3683  *     --------------
3684  *
3685  * For N2/NIU the mac addresses is from XAUI card.
3686  *
3687  * When 'compute_addrs' is true, the alternate mac addresses are computed
3688  * using the unique mac address as base. Otherwise the alternate addresses
3689  * are assigned from the list read off the 'mac-addresses' property.
3690  */
3691 
3692 static void
3693 nxge_init_mmac(p_nxge_t nxgep, boolean_t compute_addrs)
3694 {
3695 	int slot;
3696 	uint8_t func_num;
3697 	uint16_t *base_mmac_addr;
3698 	uint32_t alt_mac_ls4b;
3699 	uint16_t *mmac_addr;
3700 	uint32_t base_mac_ls4b; /* least significant 4 bytes */
3701 	nxge_mmac_t *mmac_info;
3702 	npi_mac_addr_t mac_addr;
3703 
3704 	func_num = nxgep->function_num;
3705 	base_mmac_addr = (uint16_t *)&nxgep->factaddr;
3706 	mmac_info = (nxge_mmac_t *)&nxgep->nxge_mmac_info;
3707 
3708 	if (compute_addrs) {
3709 		base_mac_ls4b = ((uint32_t)base_mmac_addr[1]) << 16 |
3710 		    base_mmac_addr[2];
3711 
3712 		if (nxgep->niu_type == N2_NIU) {
3713 			/* ls4b of 1st altmac */
3714 			alt_mac_ls4b = base_mac_ls4b + 1;
3715 		} else {			/* Neptune */
3716 			alt_mac_ls4b = base_mac_ls4b +
3717 			    (nxgep->nports - func_num) +
3718 			    (func_num * (mmac_info->num_factory_mmac));
3719 		}
3720 	}
3721 
3722 	/* Set flags for unique MAC */
3723 	mmac_info->mac_pool[0].flags |= MMAC_SLOT_USED | MMAC_VENDOR_ADDR;
3724 
3725 	/* Clear flags of all alternate MAC slots */
3726 	for (slot = 1; slot <= mmac_info->num_mmac; slot++) {
3727 		if (slot <= mmac_info->num_factory_mmac)
3728 			mmac_info->mac_pool[slot].flags = MMAC_VENDOR_ADDR;
3729 		else
3730 			mmac_info->mac_pool[slot].flags = 0;
3731 	}
3732 
3733 	/* Generate and store factory alternate MACs */
3734 	for (slot = 1; slot <= mmac_info->num_factory_mmac; slot++) {
3735 		mmac_addr = (uint16_t *)&mmac_info->factory_mac_pool[slot];
3736 		if (compute_addrs) {
3737 			mmac_addr[0] = base_mmac_addr[0];
3738 			mac_addr.w2 = mmac_addr[0];
3739 
3740 			mmac_addr[1] = (alt_mac_ls4b >> 16) & 0x0FFFF;
3741 			mac_addr.w1 = mmac_addr[1];
3742 
3743 			mmac_addr[2] = alt_mac_ls4b & 0x0FFFF;
3744 			mac_addr.w0 = mmac_addr[2];
3745 
3746 			alt_mac_ls4b++;
3747 		} else {
3748 			mac_addr.w2 = mmac_addr[0];
3749 			mac_addr.w1 = mmac_addr[1];
3750 			mac_addr.w0 = mmac_addr[2];
3751 		}
3752 
3753 		NXGE_DEBUG_MSG((nxgep, DDI_CTL,
3754 		    "mac_pool_addr[%2x:%2x:%2x:%2x:%2x:%2x] npi_addr[%x%x%x]",
3755 		    mmac_info->factory_mac_pool[slot][0],
3756 		    mmac_info->factory_mac_pool[slot][1],
3757 		    mmac_info->factory_mac_pool[slot][2],
3758 		    mmac_info->factory_mac_pool[slot][3],
3759 		    mmac_info->factory_mac_pool[slot][4],
3760 		    mmac_info->factory_mac_pool[slot][5],
3761 		    mac_addr.w0, mac_addr.w1, mac_addr.w2));
3762 		/*
3763 		 * slot minus 1 because npi_mac_altaddr_entry expects 0
3764 		 * for the first alternate mac address.
3765 		 */
3766 		(void) npi_mac_altaddr_entry(nxgep->npi_handle, OP_SET,
3767 			NXGE_GET_PORT_NUM(func_num), slot - 1, &mac_addr);
3768 	}
3769 	/* Initialize the first two parameters for mmac kstat */
3770 	nxgep->statsp->mmac_stats.mmac_max_cnt = mmac_info->num_mmac;
3771 	nxgep->statsp->mmac_stats.mmac_avail_cnt = mmac_info->num_mmac;
3772 }
3773