144961713Sgirish /*
244961713Sgirish * CDDL HEADER START
344961713Sgirish *
444961713Sgirish * The contents of this file are subject to the terms of the
544961713Sgirish * Common Development and Distribution License (the "License").
644961713Sgirish * You may not use this file except in compliance with the License.
744961713Sgirish *
844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
944961713Sgirish * or http://www.opensolaris.org/os/licensing.
1044961713Sgirish * See the License for the specific language governing permissions
1144961713Sgirish * and limitations under the License.
1244961713Sgirish *
1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each
1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the
1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying
1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner]
1844961713Sgirish *
1944961713Sgirish * CDDL HEADER END
2044961713Sgirish */
2144961713Sgirish /*
229d587972SSantwona Behera * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
2344961713Sgirish */
2444961713Sgirish
25a3c5bd6dSspeer #include <sys/nxge/nxge_impl.h>
26a3c5bd6dSspeer #include <sys/nxge/nxge_mac.h>
27678453a8Sspeer #include <sys/nxge/nxge_hio.h>
2844961713Sgirish
29952a2464SMichael Speer /*
30952a2464SMichael Speer * Local defines for FWARC 2006/556
31952a2464SMichael Speer */
32952a2464SMichael Speer #define NXGE_NIU_TDMA_PROP_LEN 2
33952a2464SMichael Speer #define NXGE_NIU_RDMA_PROP_LEN 2
34952a2464SMichael Speer #define NXGE_NIU_0_INTR_PROP_LEN 19
35952a2464SMichael Speer #define NXGE_NIU_1_INTR_PROP_LEN 17
36952a2464SMichael Speer
37952a2464SMichael Speer /*
38952a2464SMichael Speer * Local functions.
39952a2464SMichael Speer */
4044961713Sgirish static void nxge_get_niu_property(dev_info_t *, niu_type_t *);
4114ea4bb7Ssd static nxge_status_t nxge_get_mac_addr_properties(p_nxge_t);
4244961713Sgirish static nxge_status_t nxge_use_cfg_n2niu_properties(p_nxge_t);
4344961713Sgirish static void nxge_use_cfg_neptune_properties(p_nxge_t);
4444961713Sgirish static void nxge_use_cfg_dma_config(p_nxge_t);
4544961713Sgirish static void nxge_use_cfg_vlan_class_config(p_nxge_t);
4644961713Sgirish static void nxge_use_cfg_mac_class_config(p_nxge_t);
4744961713Sgirish static void nxge_use_cfg_class_config(p_nxge_t);
4844961713Sgirish static void nxge_use_cfg_link_cfg(p_nxge_t);
4944961713Sgirish static void nxge_set_hw_dma_config(p_nxge_t);
5044961713Sgirish static void nxge_set_hw_vlan_class_config(p_nxge_t);
5144961713Sgirish static void nxge_set_hw_mac_class_config(p_nxge_t);
5244961713Sgirish static void nxge_set_hw_class_config(p_nxge_t);
5344961713Sgirish static nxge_status_t nxge_use_default_dma_config_n2(p_nxge_t);
54a3c5bd6dSspeer static void nxge_ldgv_setup(p_nxge_ldg_t *, p_nxge_ldv_t *, uint8_t,
5544961713Sgirish uint8_t, int *);
5659ac0c16Sdavemq static void nxge_init_mmac(p_nxge_t, boolean_t);
57678453a8Sspeer static void nxge_set_rdc_intr_property(p_nxge_t);
5844961713Sgirish
59a3c5bd6dSspeer uint32_t nxge_use_hw_property = 1;
60a3c5bd6dSspeer uint32_t nxge_groups_per_port = 2;
6144961713Sgirish
62a3c5bd6dSspeer extern uint32_t nxge_use_partition;
63a3c5bd6dSspeer extern uint32_t nxge_dma_obp_props_only;
6444961713Sgirish
65*e3d11eeeSToomas Soome extern uint_t nxge_rx_intr(char *, char *);
66*e3d11eeeSToomas Soome extern uint_t nxge_tx_intr(char *, char *);
67*e3d11eeeSToomas Soome extern uint_t nxge_mif_intr(char *, char *);
68*e3d11eeeSToomas Soome extern uint_t nxge_mac_intr(char *, char *);
69*e3d11eeeSToomas Soome extern uint_t nxge_syserr_intr(char *, char *);
7044961713Sgirish extern void *nxge_list;
7144961713Sgirish
7244961713Sgirish #define NXGE_SHARED_REG_SW_SIM
7344961713Sgirish
7444961713Sgirish #ifdef NXGE_SHARED_REG_SW_SIM
7544961713Sgirish uint64_t global_dev_ctrl = 0;
7644961713Sgirish #endif
7744961713Sgirish
7844961713Sgirish #define MAX_SIBLINGS NXGE_MAX_PORTS
7944961713Sgirish
80a3c5bd6dSspeer extern uint32_t nxge_rbr_size;
81a3c5bd6dSspeer extern uint32_t nxge_rcr_size;
82a3c5bd6dSspeer extern uint32_t nxge_tx_ring_size;
83a3c5bd6dSspeer extern uint32_t nxge_rbr_spare_size;
8444961713Sgirish
85a3c5bd6dSspeer extern npi_status_t npi_mac_altaddr_disable(npi_handle_t, uint8_t, uint8_t);
8644961713Sgirish
8744961713Sgirish static uint8_t p2_tx_fair[2] = {12, 12};
8844961713Sgirish static uint8_t p2_tx_equal[2] = {12, 12};
8944961713Sgirish static uint8_t p4_tx_fair[4] = {6, 6, 6, 6};
9044961713Sgirish static uint8_t p4_tx_equal[4] = {6, 6, 6, 6};
9144961713Sgirish static uint8_t p2_rx_fair[2] = {8, 8};
9244961713Sgirish static uint8_t p2_rx_equal[2] = {8, 8};
9344961713Sgirish static uint8_t p4_rx_fair[4] = {4, 4, 4, 4};
9444961713Sgirish static uint8_t p4_rx_equal[4] = {4, 4, 4, 4};
9544961713Sgirish
9644961713Sgirish static uint8_t p2_rdcgrp_fair[2] = {4, 4};
9744961713Sgirish static uint8_t p2_rdcgrp_equal[2] = {4, 4};
9844961713Sgirish static uint8_t p4_rdcgrp_fair[4] = {2, 2, 1, 1};
9944961713Sgirish static uint8_t p4_rdcgrp_equal[4] = {2, 2, 2, 2};
10044961713Sgirish static uint8_t p2_rdcgrp_cls[2] = {1, 1};
10144961713Sgirish static uint8_t p4_rdcgrp_cls[4] = {1, 1, 1, 1};
10244961713Sgirish
10359ac0c16Sdavemq static uint8_t rx_4_1G[4] = {4, 4, 4, 4};
10459ac0c16Sdavemq static uint8_t rx_2_10G[2] = {8, 8};
10559ac0c16Sdavemq static uint8_t rx_2_10G_2_1G[4] = {6, 6, 2, 2};
10659ac0c16Sdavemq static uint8_t rx_1_10G_3_1G[4] = {10, 2, 2, 2};
10759ac0c16Sdavemq static uint8_t rx_1_1G_1_10G_2_1G[4] = {2, 10, 2, 2};
10859ac0c16Sdavemq
10959ac0c16Sdavemq static uint8_t tx_4_1G[4] = {6, 6, 6, 6};
11059ac0c16Sdavemq static uint8_t tx_2_10G[2] = {12, 12};
11159ac0c16Sdavemq static uint8_t tx_2_10G_2_1G[4] = {10, 10, 2, 2};
11259ac0c16Sdavemq static uint8_t tx_1_10G_3_1G[4] = {12, 4, 4, 4};
11359ac0c16Sdavemq static uint8_t tx_1_1G_1_10G_2_1G[4] = {4, 12, 4, 4};
11459ac0c16Sdavemq
11544961713Sgirish typedef enum {
11644961713Sgirish DEFAULT = 0,
11744961713Sgirish EQUAL,
11844961713Sgirish FAIR,
11944961713Sgirish CUSTOM,
12044961713Sgirish CLASSIFY,
12144961713Sgirish L2_CLASSIFY,
12244961713Sgirish L3_DISTRIBUTE,
12344961713Sgirish L3_CLASSIFY,
12444961713Sgirish L3_TCAM,
12544961713Sgirish CONFIG_TOKEN_NONE
12644961713Sgirish } config_token_t;
12744961713Sgirish
12844961713Sgirish static char *token_names[] = {
12944961713Sgirish "default",
13044961713Sgirish "equal",
13144961713Sgirish "fair",
13244961713Sgirish "custom",
13344961713Sgirish "classify",
13444961713Sgirish "l2_classify",
13544961713Sgirish "l3_distribute",
13644961713Sgirish "l3_classify",
13744961713Sgirish "l3_tcam",
13844961713Sgirish "none",
13944961713Sgirish };
14044961713Sgirish
14144961713Sgirish void nxge_virint_regs_dump(p_nxge_t nxgep);
14244961713Sgirish
14344961713Sgirish void
nxge_virint_regs_dump(p_nxge_t nxgep)14444961713Sgirish nxge_virint_regs_dump(p_nxge_t nxgep)
14544961713Sgirish {
146a3c5bd6dSspeer npi_handle_t handle;
14744961713Sgirish
14844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_virint_regs_dump"));
14944961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep);
15044961713Sgirish (void) npi_vir_dump_pio_fzc_regs_one(handle);
15144961713Sgirish (void) npi_vir_dump_ldgnum(handle);
15244961713Sgirish (void) npi_vir_dump_ldsv(handle);
15344961713Sgirish (void) npi_vir_dump_imask0(handle);
15444961713Sgirish (void) npi_vir_dump_sid(handle);
15544961713Sgirish (void) npi_mac_dump_regs(handle, nxgep->function_num);
15644961713Sgirish (void) npi_ipp_dump_regs(handle, nxgep->function_num);
15744961713Sgirish (void) npi_fflp_dump_regs(handle);
15844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_virint_regs_dump"));
15944961713Sgirish }
16044961713Sgirish
16144961713Sgirish /*
16244961713Sgirish * For now: we hard coded the DMA configurations.
16344961713Sgirish * and assume for one partition only.
16444961713Sgirish *
16544961713Sgirish * OBP. Then OBP will pass this partition's
16644961713Sgirish * Neptune configurations to fcode to create
16744961713Sgirish * properties for them.
16844961713Sgirish *
16944961713Sgirish * Since Neptune(PCI-E) and NIU (Niagara-2) has
17044961713Sgirish * different bus interfaces, the driver needs
17144961713Sgirish * to know which bus it is connected to.
17244961713Sgirish * Ravinder suggested: create a device property.
17344961713Sgirish * In partitioning environment, we cannot
17444961713Sgirish * use .conf file (need to check). If conf changes,
17544961713Sgirish * need to reboot the system.
17644961713Sgirish * The following function assumes that we will
17744961713Sgirish * retrieve its properties from a virtualized nexus driver.
17844961713Sgirish */
17944961713Sgirish
18044961713Sgirish nxge_status_t
nxge_cntlops(dev_info_t * dip,nxge_ctl_enum_t ctlop,void * arg,void * result)18144961713Sgirish nxge_cntlops(dev_info_t *dip, nxge_ctl_enum_t ctlop, void *arg, void *result)
18244961713Sgirish {
183a3c5bd6dSspeer nxge_status_t status = NXGE_OK;
18444961713Sgirish int instance;
185a3c5bd6dSspeer p_nxge_t nxgep;
186a3c5bd6dSspeer
18744961713Sgirish #ifndef NXGE_SHARED_REG_SW_SIM
18844961713Sgirish npi_handle_t handle;
18944961713Sgirish uint16_t sr16, cr16;
19044961713Sgirish #endif
19144961713Sgirish instance = ddi_get_instance(dip);
192a3c5bd6dSspeer NXGE_DEBUG_MSG((NULL, VIR_CTL, "Instance %d ", instance));
193a3c5bd6dSspeer
19444961713Sgirish if (nxge_list == NULL) {
19544961713Sgirish NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL,
19652ccf843Smisaki "nxge_cntlops: nxge_list null"));
19744961713Sgirish return (NXGE_ERROR);
19844961713Sgirish }
19944961713Sgirish nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance);
20044961713Sgirish if (nxgep == NULL) {
20144961713Sgirish NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL,
20252ccf843Smisaki "nxge_cntlops: nxgep null"));
20344961713Sgirish return (NXGE_ERROR);
20444961713Sgirish }
20544961713Sgirish #ifndef NXGE_SHARED_REG_SW_SIM
20644961713Sgirish handle = nxgep->npi_reg_handle;
20744961713Sgirish #endif
20844961713Sgirish switch (ctlop) {
20944961713Sgirish case NXGE_CTLOPS_NIUTYPE:
21044961713Sgirish nxge_get_niu_property(dip, (niu_type_t *)result);
21144961713Sgirish return (status);
212a3c5bd6dSspeer
21344961713Sgirish case NXGE_CTLOPS_GET_SHARED_REG:
21444961713Sgirish #ifdef NXGE_SHARED_REG_SW_SIM
21544961713Sgirish *(uint64_t *)result = global_dev_ctrl;
21644961713Sgirish return (0);
21744961713Sgirish #else
21844961713Sgirish status = npi_dev_func_sr_sr_get(handle, &sr16);
21944961713Sgirish *(uint16_t *)result = sr16;
22044961713Sgirish NXGE_DEBUG_MSG((NULL, VIR_CTL,
22152ccf843Smisaki "nxge_cntlops: NXGE_CTLOPS_GET_SHARED_REG"));
22244961713Sgirish return (0);
22344961713Sgirish #endif
22444961713Sgirish
22544961713Sgirish case NXGE_CTLOPS_SET_SHARED_REG_LOCK:
22644961713Sgirish #ifdef NXGE_SHARED_REG_SW_SIM
227a3c5bd6dSspeer global_dev_ctrl = *(uint64_t *)arg;
22844961713Sgirish return (0);
22944961713Sgirish #else
23044961713Sgirish status = NPI_FAILURE;
23144961713Sgirish while (status != NPI_SUCCESS)
23244961713Sgirish status = npi_dev_func_sr_lock_enter(handle);
23344961713Sgirish
23444961713Sgirish sr16 = *(uint16_t *)arg;
23544961713Sgirish status = npi_dev_func_sr_sr_set_only(handle, &sr16);
23644961713Sgirish status = npi_dev_func_sr_lock_free(handle);
23744961713Sgirish NXGE_DEBUG_MSG((NULL, VIR_CTL,
23852ccf843Smisaki "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG"));
23944961713Sgirish return (0);
24044961713Sgirish #endif
24144961713Sgirish
24244961713Sgirish case NXGE_CTLOPS_UPDATE_SHARED_REG:
24344961713Sgirish #ifdef NXGE_SHARED_REG_SW_SIM
24444961713Sgirish global_dev_ctrl |= *(uint64_t *)arg;
24544961713Sgirish return (0);
24644961713Sgirish #else
24744961713Sgirish status = NPI_FAILURE;
24844961713Sgirish while (status != NPI_SUCCESS)
24944961713Sgirish status = npi_dev_func_sr_lock_enter(handle);
25044961713Sgirish status = npi_dev_func_sr_sr_get(handle, &sr16);
25144961713Sgirish sr16 |= *(uint16_t *)arg;
25244961713Sgirish status = npi_dev_func_sr_sr_set_only(handle, &sr16);
25344961713Sgirish status = npi_dev_func_sr_lock_free(handle);
25444961713Sgirish NXGE_DEBUG_MSG((NULL, VIR_CTL,
25552ccf843Smisaki "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG"));
25644961713Sgirish return (0);
25744961713Sgirish #endif
25844961713Sgirish
25944961713Sgirish case NXGE_CTLOPS_CLEAR_BIT_SHARED_REG_UL:
26044961713Sgirish #ifdef NXGE_SHARED_REG_SW_SIM
26144961713Sgirish global_dev_ctrl |= *(uint64_t *)arg;
26244961713Sgirish return (0);
26344961713Sgirish #else
26444961713Sgirish status = npi_dev_func_sr_sr_get(handle, &sr16);
26544961713Sgirish cr16 = *(uint16_t *)arg;
26644961713Sgirish sr16 &= ~cr16;
26744961713Sgirish status = npi_dev_func_sr_sr_set_only(handle, &sr16);
26844961713Sgirish NXGE_DEBUG_MSG((NULL, VIR_CTL,
26952ccf843Smisaki "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG"));
27044961713Sgirish return (0);
27144961713Sgirish #endif
27244961713Sgirish
27344961713Sgirish case NXGE_CTLOPS_CLEAR_BIT_SHARED_REG:
27444961713Sgirish #ifdef NXGE_SHARED_REG_SW_SIM
27544961713Sgirish global_dev_ctrl |= *(uint64_t *)arg;
27644961713Sgirish return (0);
27744961713Sgirish #else
27844961713Sgirish status = NPI_FAILURE;
27944961713Sgirish while (status != NPI_SUCCESS)
28044961713Sgirish status = npi_dev_func_sr_lock_enter(handle);
28144961713Sgirish status = npi_dev_func_sr_sr_get(handle, &sr16);
28244961713Sgirish cr16 = *(uint16_t *)arg;
28344961713Sgirish sr16 &= ~cr16;
28444961713Sgirish status = npi_dev_func_sr_sr_set_only(handle, &sr16);
28544961713Sgirish status = npi_dev_func_sr_lock_free(handle);
28644961713Sgirish NXGE_DEBUG_MSG((NULL, VIR_CTL,
28752ccf843Smisaki "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG"));
28844961713Sgirish return (0);
28944961713Sgirish #endif
29044961713Sgirish
29144961713Sgirish case NXGE_CTLOPS_GET_LOCK_BLOCK:
29244961713Sgirish #ifdef NXGE_SHARED_REG_SW_SIM
29344961713Sgirish global_dev_ctrl |= *(uint64_t *)arg;
29444961713Sgirish return (0);
29544961713Sgirish #else
29644961713Sgirish status = NPI_FAILURE;
29744961713Sgirish while (status != NPI_SUCCESS)
298a3c5bd6dSspeer status = npi_dev_func_sr_lock_enter(handle);
29944961713Sgirish NXGE_DEBUG_MSG((NULL, VIR_CTL,
30052ccf843Smisaki "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_BLOCK"));
30144961713Sgirish return (0);
30244961713Sgirish #endif
30344961713Sgirish case NXGE_CTLOPS_GET_LOCK_TRY:
30444961713Sgirish #ifdef NXGE_SHARED_REG_SW_SIM
30544961713Sgirish global_dev_ctrl |= *(uint64_t *)arg;
30644961713Sgirish return (0);
30744961713Sgirish #else
30844961713Sgirish status = npi_dev_func_sr_lock_enter(handle);
30944961713Sgirish NXGE_DEBUG_MSG((NULL, VIR_CTL,
31052ccf843Smisaki "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_TRY"));
31144961713Sgirish if (status == NPI_SUCCESS)
31244961713Sgirish return (NXGE_OK);
31344961713Sgirish else
31444961713Sgirish return (NXGE_ERROR);
31544961713Sgirish #endif
31644961713Sgirish case NXGE_CTLOPS_FREE_LOCK:
31744961713Sgirish #ifdef NXGE_SHARED_REG_SW_SIM
31844961713Sgirish global_dev_ctrl |= *(uint64_t *)arg;
31944961713Sgirish return (0);
32044961713Sgirish #else
32144961713Sgirish status = npi_dev_func_sr_lock_free(handle);
32244961713Sgirish NXGE_DEBUG_MSG((NULL, VIR_CTL,
32352ccf843Smisaki "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_FREE"));
324a3c5bd6dSspeer if (status == NPI_SUCCESS)
32544961713Sgirish return (NXGE_OK);
32644961713Sgirish else
32744961713Sgirish return (NXGE_ERROR);
32844961713Sgirish #endif
32944961713Sgirish
33044961713Sgirish default:
33144961713Sgirish status = NXGE_ERROR;
33244961713Sgirish }
33344961713Sgirish
33444961713Sgirish return (status);
33544961713Sgirish }
33644961713Sgirish
33744961713Sgirish void
nxge_common_lock_get(p_nxge_t nxgep)33844961713Sgirish nxge_common_lock_get(p_nxge_t nxgep)
33944961713Sgirish {
34044961713Sgirish uint32_t status = NPI_FAILURE;
34144961713Sgirish npi_handle_t handle;
34244961713Sgirish
34344961713Sgirish #if defined(NXGE_SHARE_REG_SW_SIM)
34444961713Sgirish return;
34544961713Sgirish #endif
34644961713Sgirish handle = nxgep->npi_reg_handle;
34744961713Sgirish while (status != NPI_SUCCESS)
34844961713Sgirish status = npi_dev_func_sr_lock_enter(handle);
34944961713Sgirish }
35044961713Sgirish
35144961713Sgirish void
nxge_common_lock_free(p_nxge_t nxgep)35244961713Sgirish nxge_common_lock_free(p_nxge_t nxgep)
35344961713Sgirish {
35444961713Sgirish npi_handle_t handle;
355a3c5bd6dSspeer
35644961713Sgirish #if defined(NXGE_SHARE_REG_SW_SIM)
35744961713Sgirish return;
35844961713Sgirish #endif
35944961713Sgirish handle = nxgep->npi_reg_handle;
36044961713Sgirish (void) npi_dev_func_sr_lock_free(handle);
36144961713Sgirish }
36244961713Sgirish
36356d930aeSspeer
36444961713Sgirish static void
nxge_get_niu_property(dev_info_t * dip,niu_type_t * niu_type)36544961713Sgirish nxge_get_niu_property(dev_info_t *dip, niu_type_t *niu_type)
36644961713Sgirish {
367a3c5bd6dSspeer uchar_t *prop_val;
368a3c5bd6dSspeer uint_t prop_len;
36944961713Sgirish
37059ac0c16Sdavemq *niu_type = NIU_TYPE_NONE;
37144961713Sgirish if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0,
37252ccf843Smisaki "niu-type", (uchar_t **)&prop_val,
37352ccf843Smisaki &prop_len) == DDI_PROP_SUCCESS) {
37444961713Sgirish if (strncmp("niu", (caddr_t)prop_val, (size_t)prop_len) == 0) {
37544961713Sgirish *niu_type = N2_NIU;
37644961713Sgirish }
37744961713Sgirish ddi_prop_free(prop_val);
37844961713Sgirish }
37944961713Sgirish }
38044961713Sgirish
38144961713Sgirish static config_token_t
nxge_get_config_token(char * prop)38244961713Sgirish nxge_get_config_token(char *prop)
38344961713Sgirish {
38444961713Sgirish config_token_t token = DEFAULT;
385a3c5bd6dSspeer
38644961713Sgirish while (token < CONFIG_TOKEN_NONE) {
38744961713Sgirish if (strncmp(prop, token_names[token], 4) == 0)
38844961713Sgirish break;
38944961713Sgirish token++;
39044961713Sgirish }
39144961713Sgirish return (token);
39244961713Sgirish }
39344961713Sgirish
39444961713Sgirish /* per port */
39544961713Sgirish
39644961713Sgirish static nxge_status_t
nxge_update_rxdma_grp_properties(p_nxge_t nxgep,config_token_t token,dev_info_t * s_dip[])39744961713Sgirish nxge_update_rxdma_grp_properties(p_nxge_t nxgep, config_token_t token,
398a3c5bd6dSspeer dev_info_t *s_dip[])
39944961713Sgirish {
40044961713Sgirish nxge_status_t status = NXGE_OK;
40144961713Sgirish int ddi_status;
40244961713Sgirish int num_ports = nxgep->nports;
40344961713Sgirish int port, bits, j;
40444961713Sgirish uint8_t start_grp = 0, num_grps = 0;
40544961713Sgirish p_nxge_param_t param_arr;
40644961713Sgirish uint32_t grp_bitmap[MAX_SIBLINGS];
40744961713Sgirish int custom_start_grp[MAX_SIBLINGS];
40844961713Sgirish int custom_num_grp[MAX_SIBLINGS];
40944961713Sgirish uint8_t bad_config = B_FALSE;
41044961713Sgirish char *start_prop, *num_prop, *cfg_prop;
41144961713Sgirish
41244961713Sgirish start_grp = 0;
41344961713Sgirish param_arr = nxgep->param_arr;
41444961713Sgirish start_prop = param_arr[param_rdc_grps_start].fcode_name;
41544961713Sgirish num_prop = param_arr[param_rx_rdc_grps].fcode_name;
41644961713Sgirish
41744961713Sgirish switch (token) {
418a3c5bd6dSspeer case FAIR:
419a3c5bd6dSspeer cfg_prop = "fair";
420a3c5bd6dSspeer for (port = 0; port < num_ports; port++) {
421a3c5bd6dSspeer custom_num_grp[port] =
42252ccf843Smisaki (num_ports == 4) ?
42352ccf843Smisaki p4_rdcgrp_fair[port] :
42452ccf843Smisaki p2_rdcgrp_fair[port];
425a3c5bd6dSspeer custom_start_grp[port] = start_grp;
426a3c5bd6dSspeer start_grp += custom_num_grp[port];
427a3c5bd6dSspeer }
42844961713Sgirish break;
42944961713Sgirish
430a3c5bd6dSspeer case EQUAL:
431a3c5bd6dSspeer cfg_prop = "equal";
432a3c5bd6dSspeer for (port = 0; port < num_ports; port++) {
433a3c5bd6dSspeer custom_num_grp[port] =
43452ccf843Smisaki (num_ports == 4) ?
43552ccf843Smisaki p4_rdcgrp_equal[port] :
43652ccf843Smisaki p2_rdcgrp_equal[port];
437a3c5bd6dSspeer custom_start_grp[port] = start_grp;
438a3c5bd6dSspeer start_grp += custom_num_grp[port];
439a3c5bd6dSspeer }
440a3c5bd6dSspeer break;
44144961713Sgirish
44244961713Sgirish
443a3c5bd6dSspeer case CLASSIFY:
444a3c5bd6dSspeer cfg_prop = "classify";
445a3c5bd6dSspeer for (port = 0; port < num_ports; port++) {
446a3c5bd6dSspeer custom_num_grp[port] = (num_ports == 4) ?
44752ccf843Smisaki p4_rdcgrp_cls[port] : p2_rdcgrp_cls[port];
448a3c5bd6dSspeer custom_start_grp[port] = start_grp;
449a3c5bd6dSspeer start_grp += custom_num_grp[port];
450a3c5bd6dSspeer }
451a3c5bd6dSspeer break;
45244961713Sgirish
453a3c5bd6dSspeer case CUSTOM:
454a3c5bd6dSspeer cfg_prop = "custom";
455a3c5bd6dSspeer /* See if it is good config */
456a3c5bd6dSspeer num_grps = 0;
457a3c5bd6dSspeer for (port = 0; port < num_ports; port++) {
458a3c5bd6dSspeer custom_start_grp[port] =
45952ccf843Smisaki ddi_prop_get_int(DDI_DEV_T_NONE, s_dip[port],
46052ccf843Smisaki DDI_PROP_DONTPASS, start_prop, -1);
461a3c5bd6dSspeer if ((custom_start_grp[port] == -1) ||
46252ccf843Smisaki (custom_start_grp[port] >=
46352ccf843Smisaki NXGE_MAX_RDC_GRPS)) {
464a3c5bd6dSspeer bad_config = B_TRUE;
465a3c5bd6dSspeer break;
466a3c5bd6dSspeer }
467a3c5bd6dSspeer custom_num_grp[port] = ddi_prop_get_int(
46852ccf843Smisaki DDI_DEV_T_NONE,
46952ccf843Smisaki s_dip[port],
47052ccf843Smisaki DDI_PROP_DONTPASS,
47152ccf843Smisaki num_prop, -1);
472a3c5bd6dSspeer
473a3c5bd6dSspeer if ((custom_num_grp[port] == -1) ||
47452ccf843Smisaki (custom_num_grp[port] >
47552ccf843Smisaki NXGE_MAX_RDC_GRPS) ||
47652ccf843Smisaki ((custom_num_grp[port] +
47752ccf843Smisaki custom_start_grp[port]) >=
47852ccf843Smisaki NXGE_MAX_RDC_GRPS)) {
479a3c5bd6dSspeer bad_config = B_TRUE;
480a3c5bd6dSspeer break;
481a3c5bd6dSspeer }
482a3c5bd6dSspeer num_grps += custom_num_grp[port];
483a3c5bd6dSspeer if (num_grps > NXGE_MAX_RDC_GRPS) {
484a3c5bd6dSspeer bad_config = B_TRUE;
485a3c5bd6dSspeer break;
486a3c5bd6dSspeer }
487a3c5bd6dSspeer grp_bitmap[port] = 0;
488a3c5bd6dSspeer for (bits = 0;
48952ccf843Smisaki bits < custom_num_grp[port];
49052ccf843Smisaki bits++) {
491a3c5bd6dSspeer grp_bitmap[port] |=
49252ccf843Smisaki (1 << (bits + custom_start_grp[port]));
49344961713Sgirish }
49444961713Sgirish
495a3c5bd6dSspeer }
49644961713Sgirish
497a3c5bd6dSspeer if (bad_config == B_FALSE) {
498a3c5bd6dSspeer /* check for overlap */
499a3c5bd6dSspeer for (port = 0; port < num_ports - 1; port++) {
500a3c5bd6dSspeer for (j = port + 1; j < num_ports; j++) {
501a3c5bd6dSspeer if (grp_bitmap[port] &
50252ccf843Smisaki grp_bitmap[j]) {
503a3c5bd6dSspeer bad_config = B_TRUE;
504a3c5bd6dSspeer break;
505a3c5bd6dSspeer }
50644961713Sgirish }
507a3c5bd6dSspeer if (bad_config == B_TRUE)
508a3c5bd6dSspeer break;
50944961713Sgirish }
510a3c5bd6dSspeer }
511a3c5bd6dSspeer if (bad_config == B_TRUE) {
512a3c5bd6dSspeer /* use default config */
51344961713Sgirish for (port = 0; port < num_ports; port++) {
514a3c5bd6dSspeer custom_num_grp[port] =
51552ccf843Smisaki (num_ports == 4) ?
51652ccf843Smisaki p4_rx_fair[port] : p2_rx_fair[port];
51744961713Sgirish custom_start_grp[port] = start_grp;
51844961713Sgirish start_grp += custom_num_grp[port];
51944961713Sgirish }
520a3c5bd6dSspeer }
521a3c5bd6dSspeer break;
522a3c5bd6dSspeer
523a3c5bd6dSspeer default:
524a3c5bd6dSspeer /* use default config */
525a3c5bd6dSspeer cfg_prop = "fair";
526a3c5bd6dSspeer for (port = 0; port < num_ports; port++) {
527a3c5bd6dSspeer custom_num_grp[port] = (num_ports == 4) ?
52852ccf843Smisaki p4_rx_fair[port] : p2_rx_fair[port];
529a3c5bd6dSspeer custom_start_grp[port] = start_grp;
530a3c5bd6dSspeer start_grp += custom_num_grp[port];
531a3c5bd6dSspeer }
532a3c5bd6dSspeer break;
53344961713Sgirish }
53444961713Sgirish
535a3c5bd6dSspeer /* Now Update the rx properties */
53644961713Sgirish for (port = 0; port < num_ports; port++) {
53744961713Sgirish ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port],
53852ccf843Smisaki "rxdma-grp-cfg", cfg_prop);
53944961713Sgirish if (ddi_status != DDI_PROP_SUCCESS) {
54044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
54152ccf843Smisaki " property %s not updating",
54252ccf843Smisaki cfg_prop));
54344961713Sgirish status |= NXGE_DDI_FAILED;
54444961713Sgirish }
54544961713Sgirish ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
54652ccf843Smisaki num_prop, custom_num_grp[port]);
54744961713Sgirish
54844961713Sgirish if (ddi_status != DDI_PROP_SUCCESS) {
54944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
55052ccf843Smisaki " property %s not updating",
55152ccf843Smisaki num_prop));
55244961713Sgirish status |= NXGE_DDI_FAILED;
55344961713Sgirish }
55444961713Sgirish ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
55552ccf843Smisaki start_prop, custom_start_grp[port]);
55644961713Sgirish
55744961713Sgirish if (ddi_status != DDI_PROP_SUCCESS) {
55844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
55952ccf843Smisaki " property %s not updating",
56052ccf843Smisaki start_prop));
56144961713Sgirish status |= NXGE_DDI_FAILED;
56244961713Sgirish }
56344961713Sgirish }
56444961713Sgirish if (status & NXGE_DDI_FAILED)
56544961713Sgirish status |= NXGE_ERROR;
56644961713Sgirish
56744961713Sgirish return (status);
56844961713Sgirish }
56944961713Sgirish
57044961713Sgirish static nxge_status_t
nxge_update_rxdma_properties(p_nxge_t nxgep,config_token_t token,dev_info_t * s_dip[])57144961713Sgirish nxge_update_rxdma_properties(p_nxge_t nxgep, config_token_t token,
572a3c5bd6dSspeer dev_info_t *s_dip[])
57344961713Sgirish {
57444961713Sgirish nxge_status_t status = NXGE_OK;
57544961713Sgirish int ddi_status;
57644961713Sgirish int num_ports = nxgep->nports;
57744961713Sgirish int port, bits, j;
57844961713Sgirish uint8_t start_rdc = 0, num_rdc = 0;
57944961713Sgirish p_nxge_param_t param_arr;
58044961713Sgirish uint32_t rdc_bitmap[MAX_SIBLINGS];
58144961713Sgirish int custom_start_rdc[MAX_SIBLINGS];
58244961713Sgirish int custom_num_rdc[MAX_SIBLINGS];
58344961713Sgirish uint8_t bad_config = B_FALSE;
58444961713Sgirish int *prop_val;
58544961713Sgirish uint_t prop_len;
58644961713Sgirish char *start_rdc_prop, *num_rdc_prop, *cfg_prop;
58744961713Sgirish
58844961713Sgirish start_rdc = 0;
58944961713Sgirish param_arr = nxgep->param_arr;
59044961713Sgirish start_rdc_prop = param_arr[param_rxdma_channels_begin].fcode_name;
59144961713Sgirish num_rdc_prop = param_arr[param_rxdma_channels].fcode_name;
59244961713Sgirish
59344961713Sgirish switch (token) {
594a3c5bd6dSspeer case FAIR:
595a3c5bd6dSspeer cfg_prop = "fair";
596a3c5bd6dSspeer for (port = 0; port < num_ports; port++) {
597a3c5bd6dSspeer custom_num_rdc[port] = (num_ports == 4) ?
59852ccf843Smisaki p4_rx_fair[port] : p2_rx_fair[port];
599a3c5bd6dSspeer custom_start_rdc[port] = start_rdc;
600a3c5bd6dSspeer start_rdc += custom_num_rdc[port];
601a3c5bd6dSspeer }
602a3c5bd6dSspeer break;
60344961713Sgirish
604a3c5bd6dSspeer case EQUAL:
605a3c5bd6dSspeer cfg_prop = "equal";
606a3c5bd6dSspeer for (port = 0; port < num_ports; port++) {
607a3c5bd6dSspeer custom_num_rdc[port] = (num_ports == 4) ?
60852ccf843Smisaki p4_rx_equal[port] :
60952ccf843Smisaki p2_rx_equal[port];
610a3c5bd6dSspeer custom_start_rdc[port] = start_rdc;
611a3c5bd6dSspeer start_rdc += custom_num_rdc[port];
612a3c5bd6dSspeer }
61344961713Sgirish break;
61444961713Sgirish
615a3c5bd6dSspeer case CUSTOM:
616a3c5bd6dSspeer cfg_prop = "custom";
617a3c5bd6dSspeer /* See if it is good config */
618a3c5bd6dSspeer num_rdc = 0;
619a3c5bd6dSspeer for (port = 0; port < num_ports; port++) {
620a3c5bd6dSspeer ddi_status = ddi_prop_lookup_int_array(
62152ccf843Smisaki DDI_DEV_T_ANY,
62252ccf843Smisaki s_dip[port], 0,
62352ccf843Smisaki start_rdc_prop,
62452ccf843Smisaki &prop_val,
62552ccf843Smisaki &prop_len);
626a3c5bd6dSspeer if (ddi_status == DDI_SUCCESS)
627a3c5bd6dSspeer custom_start_rdc[port] = *prop_val;
628a3c5bd6dSspeer else {
629a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, CFG_CTL,
63052ccf843Smisaki " %s custom start port %d"
63152ccf843Smisaki " read failed ",
63252ccf843Smisaki " rxdma-cfg", port));
633a3c5bd6dSspeer bad_config = B_TRUE;
634a3c5bd6dSspeer status |= NXGE_DDI_FAILED;
635a3c5bd6dSspeer }
636a3c5bd6dSspeer if ((custom_start_rdc[port] == -1) ||
63752ccf843Smisaki (custom_start_rdc[port] >=
63852ccf843Smisaki NXGE_MAX_RDCS)) {
639a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, CFG_CTL,
64052ccf843Smisaki " %s custom start %d"
64152ccf843Smisaki " out of range %x ",
64252ccf843Smisaki " rxdma-cfg",
64352ccf843Smisaki port,
64452ccf843Smisaki custom_start_rdc[port]));
645a3c5bd6dSspeer bad_config = B_TRUE;
646a3c5bd6dSspeer break;
647a3c5bd6dSspeer }
648a3c5bd6dSspeer ddi_status = ddi_prop_lookup_int_array(
64952ccf843Smisaki DDI_DEV_T_ANY,
65052ccf843Smisaki s_dip[port],
65152ccf843Smisaki 0,
65252ccf843Smisaki num_rdc_prop,
65352ccf843Smisaki &prop_val,
65452ccf843Smisaki &prop_len);
655a3c5bd6dSspeer
656a3c5bd6dSspeer if (ddi_status == DDI_SUCCESS)
657a3c5bd6dSspeer custom_num_rdc[port] = *prop_val;
658a3c5bd6dSspeer else {
659a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, CFG_CTL,
66052ccf843Smisaki " %s custom num port %d"
66152ccf843Smisaki " read failed ",
66252ccf843Smisaki "rxdma-cfg", port));
663a3c5bd6dSspeer bad_config = B_TRUE;
664a3c5bd6dSspeer status |= NXGE_DDI_FAILED;
66544961713Sgirish }
66644961713Sgirish
667a3c5bd6dSspeer if ((custom_num_rdc[port] == -1) ||
66852ccf843Smisaki (custom_num_rdc[port] >
66952ccf843Smisaki NXGE_MAX_RDCS) ||
67052ccf843Smisaki ((custom_num_rdc[port] +
67152ccf843Smisaki custom_start_rdc[port]) >
67252ccf843Smisaki NXGE_MAX_RDCS)) {
673a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, CFG_CTL,
67452ccf843Smisaki " %s custom num %d"
67552ccf843Smisaki " out of range %x ",
67652ccf843Smisaki " rxdma-cfg",
67752ccf843Smisaki port, custom_num_rdc[port]));
678a3c5bd6dSspeer bad_config = B_TRUE;
679a3c5bd6dSspeer break;
68044961713Sgirish }
681a3c5bd6dSspeer num_rdc += custom_num_rdc[port];
682a3c5bd6dSspeer if (num_rdc > NXGE_MAX_RDCS) {
683a3c5bd6dSspeer bad_config = B_TRUE;
684a3c5bd6dSspeer break;
68544961713Sgirish }
686a3c5bd6dSspeer rdc_bitmap[port] = 0;
687a3c5bd6dSspeer for (bits = 0;
68852ccf843Smisaki bits < custom_num_rdc[port]; bits++) {
689a3c5bd6dSspeer rdc_bitmap[port] |=
69052ccf843Smisaki (1 << (bits + custom_start_rdc[port]));
691a3c5bd6dSspeer }
692a3c5bd6dSspeer }
69344961713Sgirish
694a3c5bd6dSspeer if (bad_config == B_FALSE) {
695a3c5bd6dSspeer /* check for overlap */
696a3c5bd6dSspeer for (port = 0; port < num_ports - 1; port++) {
697a3c5bd6dSspeer for (j = port + 1; j < num_ports; j++) {
698a3c5bd6dSspeer if (rdc_bitmap[port] &
69952ccf843Smisaki rdc_bitmap[j]) {
700a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep,
70152ccf843Smisaki CFG_CTL,
70252ccf843Smisaki " rxdma-cfg"
70352ccf843Smisaki " property custom"
70452ccf843Smisaki " bit overlap"
70552ccf843Smisaki " %d %d ",
70652ccf843Smisaki port, j));
707a3c5bd6dSspeer bad_config = B_TRUE;
708a3c5bd6dSspeer break;
709a3c5bd6dSspeer }
71044961713Sgirish }
711a3c5bd6dSspeer if (bad_config == B_TRUE)
712a3c5bd6dSspeer break;
71344961713Sgirish }
714a3c5bd6dSspeer }
715a3c5bd6dSspeer if (bad_config == B_TRUE) {
716a3c5bd6dSspeer /* use default config */
717a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, CFG_CTL,
71852ccf843Smisaki " rxdma-cfg property:"
71952ccf843Smisaki " bad custom config:"
72052ccf843Smisaki " use default"));
72144961713Sgirish for (port = 0; port < num_ports; port++) {
722a3c5bd6dSspeer custom_num_rdc[port] =
72352ccf843Smisaki (num_ports == 4) ?
72452ccf843Smisaki p4_rx_fair[port] :
72552ccf843Smisaki p2_rx_fair[port];
72644961713Sgirish custom_start_rdc[port] = start_rdc;
72744961713Sgirish start_rdc += custom_num_rdc[port];
72844961713Sgirish }
729a3c5bd6dSspeer }
730a3c5bd6dSspeer break;
731a3c5bd6dSspeer
732a3c5bd6dSspeer default:
733a3c5bd6dSspeer /* use default config */
734a3c5bd6dSspeer cfg_prop = "fair";
735a3c5bd6dSspeer for (port = 0; port < num_ports; port++) {
736a3c5bd6dSspeer custom_num_rdc[port] = (num_ports == 4) ?
73752ccf843Smisaki p4_rx_fair[port] : p2_rx_fair[port];
738a3c5bd6dSspeer custom_start_rdc[port] = start_rdc;
739a3c5bd6dSspeer start_rdc += custom_num_rdc[port];
740a3c5bd6dSspeer }
741a3c5bd6dSspeer break;
74244961713Sgirish }
74344961713Sgirish
744a3c5bd6dSspeer /* Now Update the rx properties */
74544961713Sgirish for (port = 0; port < num_ports; port++) {
74644961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL,
74752ccf843Smisaki " update property rxdma-cfg with %s ", cfg_prop));
74844961713Sgirish ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port],
74952ccf843Smisaki "rxdma-cfg", cfg_prop);
75044961713Sgirish if (ddi_status != DDI_PROP_SUCCESS) {
75144961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL,
75252ccf843Smisaki " property rxdma-cfg is not updating to %s",
75352ccf843Smisaki cfg_prop));
75444961713Sgirish status |= NXGE_DDI_FAILED;
75544961713Sgirish }
75644961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
75752ccf843Smisaki num_rdc_prop, custom_num_rdc[port]));
75844961713Sgirish
75944961713Sgirish ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
76052ccf843Smisaki num_rdc_prop, custom_num_rdc[port]);
76144961713Sgirish
76244961713Sgirish if (ddi_status != DDI_PROP_SUCCESS) {
76344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
76452ccf843Smisaki " property %s not updating with %d",
76552ccf843Smisaki num_rdc_prop, custom_num_rdc[port]));
76644961713Sgirish status |= NXGE_DDI_FAILED;
76744961713Sgirish }
76844961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
76952ccf843Smisaki start_rdc_prop, custom_start_rdc[port]));
77044961713Sgirish ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
77152ccf843Smisaki start_rdc_prop, custom_start_rdc[port]);
77244961713Sgirish
77344961713Sgirish if (ddi_status != DDI_PROP_SUCCESS) {
77444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
77552ccf843Smisaki " property %s not updating with %d ",
77652ccf843Smisaki start_rdc_prop, custom_start_rdc[port]));
77744961713Sgirish status |= NXGE_DDI_FAILED;
77844961713Sgirish }
77944961713Sgirish }
78044961713Sgirish if (status & NXGE_DDI_FAILED)
78144961713Sgirish status |= NXGE_ERROR;
78244961713Sgirish return (status);
78344961713Sgirish }
78444961713Sgirish
78544961713Sgirish static nxge_status_t
nxge_update_txdma_properties(p_nxge_t nxgep,config_token_t token,dev_info_t * s_dip[])78644961713Sgirish nxge_update_txdma_properties(p_nxge_t nxgep, config_token_t token,
787a3c5bd6dSspeer dev_info_t *s_dip[])
78844961713Sgirish {
78944961713Sgirish nxge_status_t status = NXGE_OK;
79044961713Sgirish int ddi_status = DDI_SUCCESS;
79144961713Sgirish int num_ports = nxgep->nports;
79244961713Sgirish int port, bits, j;
793da14cebeSEric Cheng uint8_t start_tdc, num_tdc = 0;
79444961713Sgirish p_nxge_param_t param_arr;
79544961713Sgirish uint32_t tdc_bitmap[MAX_SIBLINGS];
79644961713Sgirish int custom_start_tdc[MAX_SIBLINGS];
79744961713Sgirish int custom_num_tdc[MAX_SIBLINGS];
79844961713Sgirish uint8_t bad_config = B_FALSE;
79944961713Sgirish int *prop_val;
80044961713Sgirish uint_t prop_len;
80144961713Sgirish char *start_tdc_prop, *num_tdc_prop, *cfg_prop;
80244961713Sgirish
80344961713Sgirish start_tdc = 0;
80444961713Sgirish param_arr = nxgep->param_arr;
80544961713Sgirish start_tdc_prop = param_arr[param_txdma_channels_begin].fcode_name;
80644961713Sgirish num_tdc_prop = param_arr[param_txdma_channels].fcode_name;
80744961713Sgirish
80844961713Sgirish switch (token) {
809a3c5bd6dSspeer case FAIR:
810a3c5bd6dSspeer cfg_prop = "fair";
811a3c5bd6dSspeer for (port = 0; port < num_ports; port++) {
812a3c5bd6dSspeer custom_num_tdc[port] = (num_ports == 4) ?
81352ccf843Smisaki p4_tx_fair[port] : p2_tx_fair[port];
814a3c5bd6dSspeer custom_start_tdc[port] = start_tdc;
815a3c5bd6dSspeer start_tdc += custom_num_tdc[port];
816a3c5bd6dSspeer }
817a3c5bd6dSspeer break;
81844961713Sgirish
819a3c5bd6dSspeer case EQUAL:
820a3c5bd6dSspeer cfg_prop = "equal";
821a3c5bd6dSspeer for (port = 0; port < num_ports; port++) {
822a3c5bd6dSspeer custom_num_tdc[port] = (num_ports == 4) ?
82352ccf843Smisaki p4_tx_equal[port] : p2_tx_equal[port];
824a3c5bd6dSspeer custom_start_tdc[port] = start_tdc;
825a3c5bd6dSspeer start_tdc += custom_num_tdc[port];
826a3c5bd6dSspeer }
82744961713Sgirish break;
82844961713Sgirish
829a3c5bd6dSspeer case CUSTOM:
830a3c5bd6dSspeer cfg_prop = "custom";
831a3c5bd6dSspeer /* See if it is good config */
832a3c5bd6dSspeer num_tdc = 0;
833a3c5bd6dSspeer for (port = 0; port < num_ports; port++) {
834a3c5bd6dSspeer ddi_status = ddi_prop_lookup_int_array(
83552ccf843Smisaki DDI_DEV_T_ANY, s_dip[port], 0, start_tdc_prop,
83652ccf843Smisaki &prop_val, &prop_len);
837a3c5bd6dSspeer if (ddi_status == DDI_SUCCESS)
838a3c5bd6dSspeer custom_start_tdc[port] = *prop_val;
839a3c5bd6dSspeer else {
840a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, CFG_CTL,
84152ccf843Smisaki " %s custom start port %d"
84252ccf843Smisaki " read failed ", " txdma-cfg", port));
843a3c5bd6dSspeer bad_config = B_TRUE;
844a3c5bd6dSspeer status |= NXGE_DDI_FAILED;
84544961713Sgirish }
84644961713Sgirish
847a3c5bd6dSspeer if ((custom_start_tdc[port] == -1) ||
84852ccf843Smisaki (custom_start_tdc[port] >=
84952ccf843Smisaki NXGE_MAX_RDCS)) {
850a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, CFG_CTL,
85152ccf843Smisaki " %s custom start %d"
85252ccf843Smisaki " out of range %x ", " txdma-cfg",
85352ccf843Smisaki port, custom_start_tdc[port]));
854a3c5bd6dSspeer bad_config = B_TRUE;
855a3c5bd6dSspeer break;
856a3c5bd6dSspeer }
85744961713Sgirish
858a3c5bd6dSspeer ddi_status = ddi_prop_lookup_int_array(
85952ccf843Smisaki DDI_DEV_T_ANY, s_dip[port], 0, num_tdc_prop,
86052ccf843Smisaki &prop_val, &prop_len);
861a3c5bd6dSspeer if (ddi_status == DDI_SUCCESS)
862a3c5bd6dSspeer custom_num_tdc[port] = *prop_val;
863a3c5bd6dSspeer else {
864a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, CFG_CTL,
86552ccf843Smisaki " %s custom num port %d"
86652ccf843Smisaki " read failed ", " txdma-cfg", port));
867a3c5bd6dSspeer bad_config = B_TRUE;
868a3c5bd6dSspeer status |= NXGE_DDI_FAILED;
869a3c5bd6dSspeer }
87044961713Sgirish
871a3c5bd6dSspeer if ((custom_num_tdc[port] == -1) ||
87252ccf843Smisaki (custom_num_tdc[port] >
87352ccf843Smisaki NXGE_MAX_TDCS) ||
87452ccf843Smisaki ((custom_num_tdc[port] +
87552ccf843Smisaki custom_start_tdc[port]) >
87652ccf843Smisaki NXGE_MAX_TDCS)) {
877a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, CFG_CTL,
87852ccf843Smisaki " %s custom num %d"
87952ccf843Smisaki " out of range %x ", " rxdma-cfg",
88052ccf843Smisaki port, custom_num_tdc[port]));
881a3c5bd6dSspeer bad_config = B_TRUE;
882a3c5bd6dSspeer break;
88344961713Sgirish }
884a3c5bd6dSspeer num_tdc += custom_num_tdc[port];
885a3c5bd6dSspeer if (num_tdc > NXGE_MAX_TDCS) {
886a3c5bd6dSspeer bad_config = B_TRUE;
887a3c5bd6dSspeer break;
888a3c5bd6dSspeer }
889a3c5bd6dSspeer tdc_bitmap[port] = 0;
890a3c5bd6dSspeer for (bits = 0;
89152ccf843Smisaki bits < custom_num_tdc[port]; bits++) {
892a3c5bd6dSspeer tdc_bitmap[port] |=
89352ccf843Smisaki (1 <<
89452ccf843Smisaki (bits + custom_start_tdc[port]));
89544961713Sgirish }
89644961713Sgirish
897a3c5bd6dSspeer }
898a3c5bd6dSspeer
899a3c5bd6dSspeer if (bad_config == B_FALSE) {
900a3c5bd6dSspeer /* check for overlap */
901a3c5bd6dSspeer for (port = 0; port < num_ports - 1; port++) {
902a3c5bd6dSspeer for (j = port + 1; j < num_ports; j++) {
903a3c5bd6dSspeer if (tdc_bitmap[port] &
90452ccf843Smisaki tdc_bitmap[j]) {
905a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, CFG_CTL,
90652ccf843Smisaki " rxdma-cfg"
90752ccf843Smisaki " property custom"
90852ccf843Smisaki " bit overlap"
90952ccf843Smisaki " %d %d ",
91052ccf843Smisaki port, j));
911a3c5bd6dSspeer bad_config = B_TRUE;
912a3c5bd6dSspeer break;
913a3c5bd6dSspeer }
91444961713Sgirish }
915a3c5bd6dSspeer if (bad_config == B_TRUE)
916a3c5bd6dSspeer break;
91744961713Sgirish }
918a3c5bd6dSspeer }
919a3c5bd6dSspeer if (bad_config == B_TRUE) {
920a3c5bd6dSspeer /* use default config */
921a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, CFG_CTL,
92252ccf843Smisaki " txdma-cfg property:"
92352ccf843Smisaki " bad custom config:" " use default"));
92444961713Sgirish
92544961713Sgirish for (port = 0; port < num_ports; port++) {
92644961713Sgirish custom_num_tdc[port] = (num_ports == 4) ?
92752ccf843Smisaki p4_tx_fair[port] : p2_tx_fair[port];
92844961713Sgirish custom_start_tdc[port] = start_tdc;
92944961713Sgirish start_tdc += custom_num_tdc[port];
93044961713Sgirish }
931a3c5bd6dSspeer }
932a3c5bd6dSspeer break;
933a3c5bd6dSspeer
934a3c5bd6dSspeer default:
935a3c5bd6dSspeer /* use default config */
936a3c5bd6dSspeer cfg_prop = "fair";
937a3c5bd6dSspeer for (port = 0; port < num_ports; port++) {
938a3c5bd6dSspeer custom_num_tdc[port] = (num_ports == 4) ?
93952ccf843Smisaki p4_tx_fair[port] : p2_tx_fair[port];
940a3c5bd6dSspeer custom_start_tdc[port] = start_tdc;
941a3c5bd6dSspeer start_tdc += custom_num_tdc[port];
942a3c5bd6dSspeer }
943a3c5bd6dSspeer break;
94444961713Sgirish }
94544961713Sgirish
946a3c5bd6dSspeer /* Now Update the tx properties */
94744961713Sgirish for (port = 0; port < num_ports; port++) {
94844961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL,
94952ccf843Smisaki " update property txdma-cfg with %s ", cfg_prop));
95044961713Sgirish ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port],
95152ccf843Smisaki "txdma-cfg", cfg_prop);
95244961713Sgirish if (ddi_status != DDI_PROP_SUCCESS) {
95344961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL,
95452ccf843Smisaki " property txdma-cfg is not updating to %s",
95552ccf843Smisaki cfg_prop));
95644961713Sgirish status |= NXGE_DDI_FAILED;
95744961713Sgirish }
95844961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
95952ccf843Smisaki num_tdc_prop, custom_num_tdc[port]));
96044961713Sgirish
96144961713Sgirish ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
96252ccf843Smisaki num_tdc_prop, custom_num_tdc[port]);
96344961713Sgirish
96444961713Sgirish if (ddi_status != DDI_PROP_SUCCESS) {
96544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
96652ccf843Smisaki " property %s not updating with %d",
96752ccf843Smisaki num_tdc_prop,
96852ccf843Smisaki custom_num_tdc[port]));
96944961713Sgirish status |= NXGE_DDI_FAILED;
97044961713Sgirish }
97144961713Sgirish
97244961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
97352ccf843Smisaki start_tdc_prop, custom_start_tdc[port]));
97444961713Sgirish
975a3c5bd6dSspeer ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
97652ccf843Smisaki start_tdc_prop, custom_start_tdc[port]);
97744961713Sgirish if (ddi_status != DDI_PROP_SUCCESS) {
97844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
97952ccf843Smisaki " property %s not updating with %d ",
98052ccf843Smisaki start_tdc_prop, custom_start_tdc[port]));
98144961713Sgirish status |= NXGE_DDI_FAILED;
98244961713Sgirish }
98344961713Sgirish }
98444961713Sgirish if (status & NXGE_DDI_FAILED)
98544961713Sgirish status |= NXGE_ERROR;
98644961713Sgirish return (status);
98744961713Sgirish }
98844961713Sgirish
98944961713Sgirish static nxge_status_t
nxge_update_cfg_properties(p_nxge_t nxgep,uint32_t flags,config_token_t token,dev_info_t * s_dip[])99044961713Sgirish nxge_update_cfg_properties(p_nxge_t nxgep, uint32_t flags,
991a3c5bd6dSspeer config_token_t token, dev_info_t *s_dip[])
99244961713Sgirish {
99344961713Sgirish nxge_status_t status = NXGE_OK;
99444961713Sgirish
99544961713Sgirish switch (flags) {
996a3c5bd6dSspeer case COMMON_TXDMA_CFG:
997a3c5bd6dSspeer if (nxge_dma_obp_props_only == 0)
99844961713Sgirish status = nxge_update_txdma_properties(nxgep,
99952ccf843Smisaki token, s_dip);
1000a3c5bd6dSspeer break;
1001a3c5bd6dSspeer case COMMON_RXDMA_CFG:
1002a3c5bd6dSspeer if (nxge_dma_obp_props_only == 0)
100344961713Sgirish status = nxge_update_rxdma_properties(nxgep,
100452ccf843Smisaki token, s_dip);
100544961713Sgirish
1006a3c5bd6dSspeer break;
1007a3c5bd6dSspeer case COMMON_RXDMA_GRP_CFG:
1008a3c5bd6dSspeer status = nxge_update_rxdma_grp_properties(nxgep,
100952ccf843Smisaki token, s_dip);
1010a3c5bd6dSspeer break;
1011a3c5bd6dSspeer default:
1012a3c5bd6dSspeer return (NXGE_ERROR);
101344961713Sgirish }
101444961713Sgirish return (status);
101544961713Sgirish }
101644961713Sgirish
101744961713Sgirish /*
101844961713Sgirish * verify consistence.
101944961713Sgirish * (May require publishing the properties on all the ports.
102044961713Sgirish *
102144961713Sgirish * What if properties are published on function 0 device only?
102244961713Sgirish *
102344961713Sgirish *
102444961713Sgirish * rxdma-cfg, txdma-cfg, rxdma-grp-cfg (required )
102544961713Sgirish * What about class configs?
102644961713Sgirish *
102744961713Sgirish * If consistent, update the property on all the siblings.
102844961713Sgirish * set a flag on hardware shared register
102944961713Sgirish * The rest of the siblings will check the flag
103044961713Sgirish * if the flag is set, they will use the updated property
103144961713Sgirish * without doing any validation.
103244961713Sgirish */
103344961713Sgirish
103444961713Sgirish nxge_status_t
nxge_cfg_verify_set_classify_prop(p_nxge_t nxgep,char * prop,uint64_t known_cfg,uint32_t override,dev_info_t * c_dip[])103544961713Sgirish nxge_cfg_verify_set_classify_prop(p_nxge_t nxgep, char *prop,
1036a3c5bd6dSspeer uint64_t known_cfg, uint32_t override, dev_info_t *c_dip[])
103744961713Sgirish {
103844961713Sgirish nxge_status_t status = NXGE_OK;
103944961713Sgirish int ddi_status = DDI_SUCCESS;
104044961713Sgirish int i = 0, found = 0, update_prop = B_TRUE;
1041a3c5bd6dSspeer int *cfg_val;
1042a3c5bd6dSspeer uint_t new_value, cfg_value[MAX_SIBLINGS];
1043a3c5bd6dSspeer uint_t prop_len;
104444961713Sgirish uint_t known_cfg_value;
104544961713Sgirish
1046*e3d11eeeSToomas Soome new_value = 0;
104744961713Sgirish known_cfg_value = (uint_t)known_cfg;
104844961713Sgirish
104944961713Sgirish if (override == B_TRUE) {
105044961713Sgirish new_value = known_cfg_value;
105144961713Sgirish for (i = 0; i < nxgep->nports; i++) {
105244961713Sgirish ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE,
105352ccf843Smisaki c_dip[i], prop, new_value);
105444961713Sgirish #ifdef NXGE_DEBUG_ERROR
105544961713Sgirish if (ddi_status != DDI_PROP_SUCCESS)
105644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
105752ccf843Smisaki " property %s failed update ", prop));
105844961713Sgirish #endif
105944961713Sgirish }
106044961713Sgirish if (ddi_status != DDI_PROP_SUCCESS)
106144961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED);
106244961713Sgirish }
106344961713Sgirish for (i = 0; i < nxgep->nports; i++) {
106444961713Sgirish cfg_value[i] = known_cfg_value;
106544961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, c_dip[i], 0,
106652ccf843Smisaki prop, &cfg_val,
106752ccf843Smisaki &prop_len) == DDI_PROP_SUCCESS) {
106844961713Sgirish cfg_value[i] = *cfg_val;
106944961713Sgirish ddi_prop_free(cfg_val);
107044961713Sgirish found++;
107144961713Sgirish }
107244961713Sgirish }
107344961713Sgirish
107444961713Sgirish if (found != i) {
107544961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL,
107652ccf843Smisaki " property %s not specified on all ports", prop));
107744961713Sgirish if (found == 0) {
1078a3c5bd6dSspeer /* not specified: Use default */
107944961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL,
108052ccf843Smisaki " property %s not specified on any port:"
108152ccf843Smisaki " Using default", prop));
108244961713Sgirish new_value = known_cfg_value;
108344961713Sgirish } else {
1084a3c5bd6dSspeer /* specified on some */
108544961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL,
108652ccf843Smisaki " property %s not specified"
108752ccf843Smisaki " on some ports: Using default", prop));
108844961713Sgirish /* ? use p0 value instead ? */
108944961713Sgirish new_value = known_cfg_value;
109044961713Sgirish }
109144961713Sgirish } else {
109244961713Sgirish /* check type and consistence */
109344961713Sgirish /* found on all devices */
109444961713Sgirish for (i = 1; i < found; i++) {
1095a3c5bd6dSspeer if (cfg_value[i] != cfg_value[i - 1]) {
109644961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL,
109752ccf843Smisaki " property %s inconsistent:"
109852ccf843Smisaki " Using default", prop));
109944961713Sgirish new_value = known_cfg_value;
110044961713Sgirish break;
1101a3c5bd6dSspeer }
1102a3c5bd6dSspeer /*
1103a3c5bd6dSspeer * Found on all the ports and consistent. Nothing to
1104a3c5bd6dSspeer * do.
1105a3c5bd6dSspeer */
110644961713Sgirish update_prop = B_FALSE;
110744961713Sgirish }
110844961713Sgirish }
110944961713Sgirish
111044961713Sgirish if (update_prop == B_TRUE) {
111144961713Sgirish for (i = 0; i < nxgep->nports; i++) {
111244961713Sgirish ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE,
111352ccf843Smisaki c_dip[i], prop, new_value);
111444961713Sgirish #ifdef NXGE_DEBUG_ERROR
111544961713Sgirish if (ddi_status != DDI_SUCCESS)
111644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
111752ccf843Smisaki " property %s not updating with %d"
111852ccf843Smisaki " Using default",
111952ccf843Smisaki prop, new_value));
112044961713Sgirish #endif
112144961713Sgirish if (ddi_status != DDI_PROP_SUCCESS)
112244961713Sgirish status |= NXGE_DDI_FAILED;
112344961713Sgirish }
112444961713Sgirish }
112544961713Sgirish if (status & NXGE_DDI_FAILED)
112644961713Sgirish status |= NXGE_ERROR;
112744961713Sgirish
112844961713Sgirish return (status);
112944961713Sgirish }
113044961713Sgirish
113144961713Sgirish static uint64_t
nxge_class_get_known_cfg(p_nxge_t nxgep,int class_prop,int rx_quick_cfg)1132a3c5bd6dSspeer nxge_class_get_known_cfg(p_nxge_t nxgep, int class_prop, int rx_quick_cfg)
113344961713Sgirish {
1134a3c5bd6dSspeer int start_prop;
113544961713Sgirish uint64_t cfg_value;
113644961713Sgirish p_nxge_param_t param_arr;
113744961713Sgirish
1138a3c5bd6dSspeer param_arr = nxgep->param_arr;
113944961713Sgirish cfg_value = param_arr[class_prop].value;
114044961713Sgirish start_prop = param_h1_init_value;
114144961713Sgirish
114244961713Sgirish /* update the properties per quick config */
114344961713Sgirish switch (rx_quick_cfg) {
1144a3c5bd6dSspeer case CFG_L3_WEB:
1145a3c5bd6dSspeer case CFG_L3_DISTRIBUTE:
1146a3c5bd6dSspeer cfg_value = nxge_classify_get_cfg_value(nxgep,
114752ccf843Smisaki rx_quick_cfg, class_prop - start_prop);
1148a3c5bd6dSspeer break;
1149a3c5bd6dSspeer default:
1150a3c5bd6dSspeer cfg_value = param_arr[class_prop].value;
1151a3c5bd6dSspeer break;
115244961713Sgirish }
115344961713Sgirish return (cfg_value);
115444961713Sgirish }
115544961713Sgirish
115644961713Sgirish static nxge_status_t
nxge_cfg_verify_set_classify(p_nxge_t nxgep,dev_info_t * c_dip[])115744961713Sgirish nxge_cfg_verify_set_classify(p_nxge_t nxgep, dev_info_t *c_dip[])
115844961713Sgirish {
115944961713Sgirish nxge_status_t status = NXGE_OK;
1160a3c5bd6dSspeer int rx_quick_cfg, class_prop, start_prop, end_prop;
116144961713Sgirish char *prop_name;
116244961713Sgirish int override = B_TRUE;
116344961713Sgirish uint64_t cfg_value;
116444961713Sgirish p_nxge_param_t param_arr;
1165a3c5bd6dSspeer
116644961713Sgirish param_arr = nxgep->param_arr;
116744961713Sgirish rx_quick_cfg = param_arr[param_rx_quick_cfg].value;
116844961713Sgirish start_prop = param_h1_init_value;
116944961713Sgirish end_prop = param_class_opt_ipv6_sctp;
117044961713Sgirish
1171a3c5bd6dSspeer /* update the properties per quick config */
117244961713Sgirish if (rx_quick_cfg == CFG_NOT_SPECIFIED)
117344961713Sgirish override = B_FALSE;
1174a3c5bd6dSspeer
1175a3c5bd6dSspeer /*
1176a3c5bd6dSspeer * these parameter affect the classification outcome.
1177a3c5bd6dSspeer * these parameters are used to configure the Flow key and
1178a3c5bd6dSspeer * the TCAM key for each of the IP classes.
117958324dfcSspeer * Included here are also the H1 and H2 initial values
1180a3c5bd6dSspeer * which affect the distribution as well as final hash value
1181a3c5bd6dSspeer * (hence the offset into RDC table and FCRAM bucket location)
1182a3c5bd6dSspeer *
1183a3c5bd6dSspeer */
1184a3c5bd6dSspeer for (class_prop = start_prop; class_prop <= end_prop; class_prop++) {
118544961713Sgirish prop_name = param_arr[class_prop].fcode_name;
118644961713Sgirish cfg_value = nxge_class_get_known_cfg(nxgep,
118752ccf843Smisaki class_prop, rx_quick_cfg);
1188a3c5bd6dSspeer status = nxge_cfg_verify_set_classify_prop(nxgep, prop_name,
118952ccf843Smisaki cfg_value, override, c_dip);
119044961713Sgirish }
119144961713Sgirish
1192a3c5bd6dSspeer /*
1193a3c5bd6dSspeer * these properties do not affect the actual classification outcome.
1194a3c5bd6dSspeer * used to enable/disable or tune the fflp hardware
1195a3c5bd6dSspeer *
1196a3c5bd6dSspeer * fcram_access_ratio, tcam_access_ratio, tcam_enable, llc_snap_enable
1197a3c5bd6dSspeer *
1198a3c5bd6dSspeer */
119944961713Sgirish override = B_FALSE;
120044961713Sgirish for (class_prop = param_fcram_access_ratio;
120152ccf843Smisaki class_prop <= param_llc_snap_enable; class_prop++) {
120244961713Sgirish prop_name = param_arr[class_prop].fcode_name;
120344961713Sgirish cfg_value = param_arr[class_prop].value;
120444961713Sgirish status = nxge_cfg_verify_set_classify_prop(nxgep, prop_name,
120552ccf843Smisaki cfg_value, override, c_dip);
120644961713Sgirish }
120744961713Sgirish
1208a3c5bd6dSspeer return (status);
120944961713Sgirish }
121044961713Sgirish
121144961713Sgirish nxge_status_t
nxge_cfg_verify_set(p_nxge_t nxgep,uint32_t flag)121244961713Sgirish nxge_cfg_verify_set(p_nxge_t nxgep, uint32_t flag)
121344961713Sgirish {
121444961713Sgirish nxge_status_t status = NXGE_OK;
121544961713Sgirish int i = 0, found = 0;
121644961713Sgirish int num_siblings;
1217a3c5bd6dSspeer dev_info_t *c_dip[MAX_SIBLINGS + 1];
121844961713Sgirish char *prop_val[MAX_SIBLINGS];
121944961713Sgirish config_token_t c_token[MAX_SIBLINGS];
122044961713Sgirish char *prop;
122144961713Sgirish
1222a3c5bd6dSspeer if (nxge_dma_obp_props_only)
122344961713Sgirish return (NXGE_OK);
122444961713Sgirish
122544961713Sgirish num_siblings = 0;
122644961713Sgirish c_dip[num_siblings] = ddi_get_child(nxgep->p_dip);
122744961713Sgirish while (c_dip[num_siblings]) {
122844961713Sgirish c_dip[num_siblings + 1] =
122952ccf843Smisaki ddi_get_next_sibling(c_dip[num_siblings]);
123044961713Sgirish num_siblings++;
123144961713Sgirish }
123244961713Sgirish
123344961713Sgirish switch (flag) {
1234a3c5bd6dSspeer case COMMON_TXDMA_CFG:
1235a3c5bd6dSspeer prop = "txdma-cfg";
1236a3c5bd6dSspeer break;
1237a3c5bd6dSspeer case COMMON_RXDMA_CFG:
1238a3c5bd6dSspeer prop = "rxdma-cfg";
1239a3c5bd6dSspeer break;
1240a3c5bd6dSspeer case COMMON_RXDMA_GRP_CFG:
1241a3c5bd6dSspeer prop = "rxdma-grp-cfg";
1242a3c5bd6dSspeer break;
1243a3c5bd6dSspeer case COMMON_CLASS_CFG:
1244a3c5bd6dSspeer status = nxge_cfg_verify_set_classify(nxgep, c_dip);
1245a3c5bd6dSspeer return (status);
1246a3c5bd6dSspeer default:
1247a3c5bd6dSspeer return (NXGE_ERROR);
124844961713Sgirish }
124944961713Sgirish
125044961713Sgirish i = 0;
125144961713Sgirish while (i < num_siblings) {
1252a3c5bd6dSspeer if (ddi_prop_lookup_string(DDI_DEV_T_ANY, c_dip[i], 0, prop,
125352ccf843Smisaki (char **)&prop_val[i]) == DDI_PROP_SUCCESS) {
125444961713Sgirish c_token[i] = nxge_get_config_token(prop_val[i]);
125544961713Sgirish ddi_prop_free(prop_val[i]);
125644961713Sgirish found++;
125744961713Sgirish } else
125844961713Sgirish c_token[i] = CONFIG_TOKEN_NONE;
125944961713Sgirish i++;
126044961713Sgirish }
126144961713Sgirish
126244961713Sgirish if (found != i) {
126344961713Sgirish if (found == 0) {
1264a3c5bd6dSspeer /* not specified: Use default */
126544961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL,
126652ccf843Smisaki " property %s not specified on any port:"
126752ccf843Smisaki " Using default", prop));
126844961713Sgirish
126944961713Sgirish status = nxge_update_cfg_properties(nxgep,
127052ccf843Smisaki flag, FAIR, c_dip);
127144961713Sgirish return (status);
127244961713Sgirish } else {
127344961713Sgirish /*
1274a3c5bd6dSspeer * if the convention is to use function 0 device then
1275a3c5bd6dSspeer * populate the other devices with this configuration.
127644961713Sgirish *
127744961713Sgirish * The other alternative is to use the default config.
127844961713Sgirish */
1279a3c5bd6dSspeer /* not specified: Use default */
128044961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL,
128152ccf843Smisaki " property %s not specified on some ports:"
128252ccf843Smisaki " Using default", prop));
128344961713Sgirish status = nxge_update_cfg_properties(nxgep,
128452ccf843Smisaki flag, FAIR, c_dip);
128544961713Sgirish return (status);
128644961713Sgirish }
128744961713Sgirish }
128844961713Sgirish
1289a3c5bd6dSspeer /* check type and consistence */
1290a3c5bd6dSspeer /* found on all devices */
1291a3c5bd6dSspeer for (i = 1; i < found; i++) {
1292a3c5bd6dSspeer if (c_token[i] != c_token[i - 1]) {
129344961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL,
129452ccf843Smisaki " property %s inconsistent:"
129552ccf843Smisaki " Using default", prop));
129644961713Sgirish status = nxge_update_cfg_properties(nxgep,
129752ccf843Smisaki flag, FAIR, c_dip);
129844961713Sgirish return (status);
129944961713Sgirish }
130044961713Sgirish }
130144961713Sgirish
1302a3c5bd6dSspeer /*
1303a3c5bd6dSspeer * Found on all the ports check if it is custom configuration. if
1304a3c5bd6dSspeer * custom, then verify consistence
1305a3c5bd6dSspeer *
1306a3c5bd6dSspeer * finally create soft properties
1307a3c5bd6dSspeer */
1308a3c5bd6dSspeer status = nxge_update_cfg_properties(nxgep, flag, c_token[0], c_dip);
130944961713Sgirish return (status);
131044961713Sgirish }
131144961713Sgirish
131244961713Sgirish nxge_status_t
nxge_cfg_verify_set_quick_config(p_nxge_t nxgep)131344961713Sgirish nxge_cfg_verify_set_quick_config(p_nxge_t nxgep)
131444961713Sgirish {
131544961713Sgirish nxge_status_t status = NXGE_OK;
131644961713Sgirish int ddi_status = DDI_SUCCESS;
131744961713Sgirish char *prop_val;
131844961713Sgirish char *rx_prop;
131944961713Sgirish char *prop;
132044961713Sgirish uint32_t cfg_value = CFG_NOT_SPECIFIED;
132144961713Sgirish p_nxge_param_t param_arr;
132244961713Sgirish
1323a3c5bd6dSspeer param_arr = nxgep->param_arr;
132444961713Sgirish rx_prop = param_arr[param_rx_quick_cfg].fcode_name;
132544961713Sgirish
132644961713Sgirish prop = "rx-quick-cfg";
132744961713Sgirish
1328a3c5bd6dSspeer /*
1329a3c5bd6dSspeer * good value are
1330a3c5bd6dSspeer *
1331a3c5bd6dSspeer * "web-server" "generic-server" "l3-classify" "flow-classify"
1332a3c5bd6dSspeer */
133344961713Sgirish if (ddi_prop_lookup_string(DDI_DEV_T_ANY, nxgep->dip, 0,
133452ccf843Smisaki prop, (char **)&prop_val) != DDI_PROP_SUCCESS) {
133544961713Sgirish NXGE_DEBUG_MSG((nxgep, VPD_CTL,
133652ccf843Smisaki " property %s not specified: using default ", prop));
133744961713Sgirish cfg_value = CFG_NOT_SPECIFIED;
133844961713Sgirish } else {
133944961713Sgirish cfg_value = CFG_L3_DISTRIBUTE;
134044961713Sgirish if (strncmp("web-server", (caddr_t)prop_val, 8) == 0) {
134144961713Sgirish cfg_value = CFG_L3_WEB;
134244961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL,
134352ccf843Smisaki " %s: web server ", prop));
134444961713Sgirish }
134544961713Sgirish if (strncmp("generic-server", (caddr_t)prop_val, 8) == 0) {
134644961713Sgirish cfg_value = CFG_L3_DISTRIBUTE;
134744961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL,
134852ccf843Smisaki " %s: distribute ", prop));
134944961713Sgirish }
135044961713Sgirish /* more */
135144961713Sgirish ddi_prop_free(prop_val);
135244961713Sgirish }
135344961713Sgirish
135444961713Sgirish ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
135552ccf843Smisaki rx_prop, cfg_value);
135644961713Sgirish if (ddi_status != DDI_PROP_SUCCESS)
135744961713Sgirish status |= NXGE_DDI_FAILED;
135844961713Sgirish
1359a3c5bd6dSspeer /* now handle specified cases: */
136044961713Sgirish if (status & NXGE_DDI_FAILED)
136144961713Sgirish status |= NXGE_ERROR;
136244961713Sgirish return (status);
136344961713Sgirish }
136444961713Sgirish
136500161856Syc /*
136600161856Syc * Device properties adv-autoneg-cap etc are defined by FWARC
136700161856Syc * http://sac.sfbay/FWARC/2002/345/20020610_asif.haswarey
136800161856Syc */
136944961713Sgirish static void
nxge_use_cfg_link_cfg(p_nxge_t nxgep)137044961713Sgirish nxge_use_cfg_link_cfg(p_nxge_t nxgep)
137144961713Sgirish {
137244961713Sgirish int *prop_val;
137344961713Sgirish uint_t prop_len;
137444961713Sgirish dev_info_t *dip;
137544961713Sgirish int speed;
137644961713Sgirish int duplex;
137744961713Sgirish int adv_autoneg_cap;
137844961713Sgirish int adv_10gfdx_cap;
137944961713Sgirish int adv_10ghdx_cap;
138044961713Sgirish int adv_1000fdx_cap;
138144961713Sgirish int adv_1000hdx_cap;
138244961713Sgirish int adv_100fdx_cap;
138344961713Sgirish int adv_100hdx_cap;
138444961713Sgirish int adv_10fdx_cap;
138544961713Sgirish int adv_10hdx_cap;
138644961713Sgirish int status = DDI_SUCCESS;
138744961713Sgirish
138844961713Sgirish dip = nxgep->dip;
1389a3c5bd6dSspeer
1390a3c5bd6dSspeer /*
1391a3c5bd6dSspeer * first find out the card type and the supported link speeds and
1392a3c5bd6dSspeer * features
1393a3c5bd6dSspeer */
1394a3c5bd6dSspeer /* add code for card type */
139544961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-autoneg-cap",
139652ccf843Smisaki &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
139744961713Sgirish ddi_prop_free(prop_val);
1398a3c5bd6dSspeer return;
139944961713Sgirish }
1400a3c5bd6dSspeer
140144961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10gfdx-cap",
140252ccf843Smisaki &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
140344961713Sgirish ddi_prop_free(prop_val);
1404a3c5bd6dSspeer return;
140544961713Sgirish }
1406a3c5bd6dSspeer
140744961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-1000hdx-cap",
140852ccf843Smisaki &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
140944961713Sgirish ddi_prop_free(prop_val);
1410a3c5bd6dSspeer return;
141144961713Sgirish }
1412a3c5bd6dSspeer
141344961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-1000fdx-cap",
141452ccf843Smisaki &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
141544961713Sgirish ddi_prop_free(prop_val);
1416a3c5bd6dSspeer return;
141744961713Sgirish }
1418a3c5bd6dSspeer
141944961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-100fdx-cap",
142052ccf843Smisaki &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
142144961713Sgirish ddi_prop_free(prop_val);
1422a3c5bd6dSspeer return;
142344961713Sgirish }
1424a3c5bd6dSspeer
142544961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-100hdx-cap",
142652ccf843Smisaki &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
142744961713Sgirish ddi_prop_free(prop_val);
1428a3c5bd6dSspeer return;
142944961713Sgirish }
1430a3c5bd6dSspeer
143144961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10fdx-cap",
143252ccf843Smisaki &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
143344961713Sgirish ddi_prop_free(prop_val);
1434a3c5bd6dSspeer return;
143544961713Sgirish }
1436a3c5bd6dSspeer
143744961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10hdx-cap",
143852ccf843Smisaki &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
143944961713Sgirish ddi_prop_free(prop_val);
1440a3c5bd6dSspeer return;
144144961713Sgirish }
144244961713Sgirish
144344961713Sgirish if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0, "speed",
144452ccf843Smisaki (uchar_t **)&prop_val, &prop_len) == DDI_PROP_SUCCESS) {
144544961713Sgirish if (strncmp("10000", (caddr_t)prop_val,
144652ccf843Smisaki (size_t)prop_len) == 0) {
144744961713Sgirish speed = 10000;
144844961713Sgirish } else if (strncmp("1000", (caddr_t)prop_val,
144952ccf843Smisaki (size_t)prop_len) == 0) {
145044961713Sgirish speed = 1000;
145144961713Sgirish } else if (strncmp("100", (caddr_t)prop_val,
145252ccf843Smisaki (size_t)prop_len) == 0) {
145344961713Sgirish speed = 100;
145444961713Sgirish } else if (strncmp("10", (caddr_t)prop_val,
145552ccf843Smisaki (size_t)prop_len) == 0) {
145644961713Sgirish speed = 10;
145744961713Sgirish } else if (strncmp("auto", (caddr_t)prop_val,
145852ccf843Smisaki (size_t)prop_len) == 0) {
145944961713Sgirish speed = 0;
146044961713Sgirish } else {
146144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_NOTE,
146252ccf843Smisaki "speed property is invalid reverting to auto"));
146344961713Sgirish speed = 0;
146444961713Sgirish }
146544961713Sgirish ddi_prop_free(prop_val);
146644961713Sgirish } else
146744961713Sgirish speed = 0;
146844961713Sgirish
146944961713Sgirish if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0, "duplex",
147052ccf843Smisaki (uchar_t **)&prop_val, &prop_len) == DDI_PROP_SUCCESS) {
147144961713Sgirish if (strncmp("full", (caddr_t)prop_val,
147252ccf843Smisaki (size_t)prop_len) == 0) {
147344961713Sgirish duplex = 2;
147444961713Sgirish } else if (strncmp("half", (caddr_t)prop_val,
147552ccf843Smisaki (size_t)prop_len) == 0) {
147644961713Sgirish duplex = 1;
147744961713Sgirish } else if (strncmp("auto", (caddr_t)prop_val,
147852ccf843Smisaki (size_t)prop_len) == 0) {
147944961713Sgirish duplex = 0;
148044961713Sgirish } else {
148144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_NOTE,
148252ccf843Smisaki "duplex property is invalid"
148352ccf843Smisaki " reverting to auto"));
148444961713Sgirish duplex = 0;
148544961713Sgirish }
148644961713Sgirish ddi_prop_free(prop_val);
148744961713Sgirish } else
148844961713Sgirish duplex = 0;
148944961713Sgirish
149000161856Syc /* speed == 0 or duplex == 0 means auto negotiation. */
149144961713Sgirish adv_autoneg_cap = (speed == 0) || (duplex == 0);
149244961713Sgirish if (adv_autoneg_cap == 0) {
149344961713Sgirish adv_10gfdx_cap = ((speed == 10000) && (duplex == 2));
149444961713Sgirish adv_10ghdx_cap = adv_10gfdx_cap;
149544961713Sgirish adv_10ghdx_cap |= ((speed == 10000) && (duplex == 1));
149644961713Sgirish adv_1000fdx_cap = adv_10ghdx_cap;
149744961713Sgirish adv_1000fdx_cap |= ((speed == 1000) && (duplex == 2));
149844961713Sgirish adv_1000hdx_cap = adv_1000fdx_cap;
149944961713Sgirish adv_1000hdx_cap |= ((speed == 1000) && (duplex == 1));
150044961713Sgirish adv_100fdx_cap = adv_1000hdx_cap;
150144961713Sgirish adv_100fdx_cap |= ((speed == 100) && (duplex == 2));
150244961713Sgirish adv_100hdx_cap = adv_100fdx_cap;
150344961713Sgirish adv_100hdx_cap |= ((speed == 100) && (duplex == 1));
150444961713Sgirish adv_10fdx_cap = adv_100hdx_cap;
150544961713Sgirish adv_10fdx_cap |= ((speed == 10) && (duplex == 2));
150644961713Sgirish adv_10hdx_cap = adv_10fdx_cap;
150744961713Sgirish adv_10hdx_cap |= ((speed == 10) && (duplex == 1));
150844961713Sgirish } else if (speed == 0) {
150944961713Sgirish adv_10gfdx_cap = (duplex == 2);
151044961713Sgirish adv_10ghdx_cap = (duplex == 1);
151144961713Sgirish adv_1000fdx_cap = (duplex == 2);
151244961713Sgirish adv_1000hdx_cap = (duplex == 1);
151344961713Sgirish adv_100fdx_cap = (duplex == 2);
151444961713Sgirish adv_100hdx_cap = (duplex == 1);
151544961713Sgirish adv_10fdx_cap = (duplex == 2);
151644961713Sgirish adv_10hdx_cap = (duplex == 1);
151744961713Sgirish }
151844961713Sgirish if (duplex == 0) {
151944961713Sgirish adv_10gfdx_cap = (speed == 0);
152044961713Sgirish adv_10gfdx_cap |= (speed == 10000);
152144961713Sgirish adv_10ghdx_cap = adv_10gfdx_cap;
152244961713Sgirish adv_10ghdx_cap |= (speed == 10000);
152344961713Sgirish adv_1000fdx_cap = adv_10ghdx_cap;
152444961713Sgirish adv_1000fdx_cap |= (speed == 1000);
152544961713Sgirish adv_1000hdx_cap = adv_1000fdx_cap;
152644961713Sgirish adv_1000hdx_cap |= (speed == 1000);
152744961713Sgirish adv_100fdx_cap = adv_1000hdx_cap;
152844961713Sgirish adv_100fdx_cap |= (speed == 100);
152944961713Sgirish adv_100hdx_cap = adv_100fdx_cap;
153044961713Sgirish adv_100hdx_cap |= (speed == 100);
153144961713Sgirish adv_10fdx_cap = adv_100hdx_cap;
153244961713Sgirish adv_10fdx_cap |= (speed == 10);
153344961713Sgirish adv_10hdx_cap = adv_10fdx_cap;
153444961713Sgirish adv_10hdx_cap |= (speed == 10);
153544961713Sgirish }
153644961713Sgirish status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
153752ccf843Smisaki "adv-autoneg-cap", &adv_autoneg_cap, 1);
153844961713Sgirish if (status)
1539a3c5bd6dSspeer return;
154044961713Sgirish
154144961713Sgirish status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
154252ccf843Smisaki "adv-10gfdx-cap", &adv_10gfdx_cap, 1);
154344961713Sgirish if (status)
154444961713Sgirish goto nxge_map_myargs_to_gmii_fail1;
154544961713Sgirish
154644961713Sgirish status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
154752ccf843Smisaki "adv-10ghdx-cap", &adv_10ghdx_cap, 1);
154844961713Sgirish if (status)
154944961713Sgirish goto nxge_map_myargs_to_gmii_fail2;
155044961713Sgirish
155144961713Sgirish status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
155252ccf843Smisaki "adv-1000fdx-cap", &adv_1000fdx_cap, 1);
155344961713Sgirish if (status)
155444961713Sgirish goto nxge_map_myargs_to_gmii_fail3;
155544961713Sgirish
155644961713Sgirish status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
155752ccf843Smisaki "adv-1000hdx-cap", &adv_1000hdx_cap, 1);
155844961713Sgirish if (status)
155944961713Sgirish goto nxge_map_myargs_to_gmii_fail4;
156044961713Sgirish
156144961713Sgirish status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
156252ccf843Smisaki "adv-100fdx-cap", &adv_100fdx_cap, 1);
156344961713Sgirish if (status)
156444961713Sgirish goto nxge_map_myargs_to_gmii_fail5;
156544961713Sgirish
156644961713Sgirish status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
156752ccf843Smisaki "adv-100hdx-cap", &adv_100hdx_cap, 1);
156844961713Sgirish if (status)
156944961713Sgirish goto nxge_map_myargs_to_gmii_fail6;
157044961713Sgirish
157144961713Sgirish status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
157252ccf843Smisaki "adv-10fdx-cap", &adv_10fdx_cap, 1);
157344961713Sgirish if (status)
157444961713Sgirish goto nxge_map_myargs_to_gmii_fail7;
157544961713Sgirish
157644961713Sgirish status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
157752ccf843Smisaki "adv-10hdx-cap", &adv_10hdx_cap, 1);
157844961713Sgirish if (status)
157944961713Sgirish goto nxge_map_myargs_to_gmii_fail8;
158044961713Sgirish
1581a3c5bd6dSspeer return;
158244961713Sgirish
158344961713Sgirish nxge_map_myargs_to_gmii_fail9:
158444961713Sgirish (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10hdx-cap");
158544961713Sgirish
158644961713Sgirish nxge_map_myargs_to_gmii_fail8:
158744961713Sgirish (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10fdx-cap");
158844961713Sgirish
158944961713Sgirish nxge_map_myargs_to_gmii_fail7:
159044961713Sgirish (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-100hdx-cap");
159144961713Sgirish
159244961713Sgirish nxge_map_myargs_to_gmii_fail6:
159344961713Sgirish (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-100fdx-cap");
159444961713Sgirish
159544961713Sgirish nxge_map_myargs_to_gmii_fail5:
159644961713Sgirish (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-1000hdx-cap");
159744961713Sgirish
159844961713Sgirish nxge_map_myargs_to_gmii_fail4:
159944961713Sgirish (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-1000fdx-cap");
160044961713Sgirish
160144961713Sgirish nxge_map_myargs_to_gmii_fail3:
160244961713Sgirish (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10ghdx-cap");
160344961713Sgirish
160444961713Sgirish nxge_map_myargs_to_gmii_fail2:
160544961713Sgirish (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10gfdx-cap");
160644961713Sgirish
160744961713Sgirish nxge_map_myargs_to_gmii_fail1:
160844961713Sgirish (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-autoneg-cap");
160944961713Sgirish }
161044961713Sgirish
161144961713Sgirish nxge_status_t
nxge_get_config_properties(p_nxge_t nxgep)161244961713Sgirish nxge_get_config_properties(p_nxge_t nxgep)
161344961713Sgirish {
1614a3c5bd6dSspeer nxge_status_t status = NXGE_OK;
1615a3c5bd6dSspeer p_nxge_hw_list_t hw_p;
16164df55fdeSJanie Lu char **prop_val;
16174df55fdeSJanie Lu uint_t prop_len;
16184df55fdeSJanie Lu uint_t i;
161944961713Sgirish
162044961713Sgirish NXGE_DEBUG_MSG((nxgep, VPD_CTL, " ==> nxge_get_config_properties"));
162144961713Sgirish
162244961713Sgirish if ((hw_p = nxgep->nxge_hw_p) == NULL) {
162344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
162452ccf843Smisaki " nxge_get_config_properties:"
162552ccf843Smisaki " common hardware not set", nxgep->niu_type));
162644961713Sgirish return (NXGE_ERROR);
162744961713Sgirish }
162844961713Sgirish
162944961713Sgirish /*
163044961713Sgirish * Get info on how many ports Neptune card has.
163144961713Sgirish */
16322e59129aSraghus nxgep->nports = nxge_get_nports(nxgep);
163359ac0c16Sdavemq if (nxgep->nports <= 0) {
163459ac0c16Sdavemq NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
163559ac0c16Sdavemq "<==nxge_get_config_properties: Invalid Neptune type 0x%x",
163659ac0c16Sdavemq nxgep->niu_type));
163759ac0c16Sdavemq return (NXGE_ERROR);
163859ac0c16Sdavemq }
163959ac0c16Sdavemq nxgep->classifier.tcam_size = TCAM_NIU_TCAM_MAX_ENTRY;
16402e59129aSraghus if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
16412e59129aSraghus nxgep->classifier.tcam_size = TCAM_NXGE_TCAM_MAX_ENTRY;
16422e59129aSraghus }
164359ac0c16Sdavemq if (nxgep->function_num >= nxgep->nports) {
164459ac0c16Sdavemq return (NXGE_ERROR);
164544961713Sgirish }
164644961713Sgirish
164714ea4bb7Ssd status = nxge_get_mac_addr_properties(nxgep);
1648a3c5bd6dSspeer if (status != NXGE_OK)
164914ea4bb7Ssd return (NXGE_ERROR);
165044961713Sgirish
1651a3c5bd6dSspeer /*
1652a3c5bd6dSspeer * read the configuration type. If none is specified, used default.
1653a3c5bd6dSspeer * Config types: equal: (default) DMA channels, RDC groups, TCAM, FCRAM
1654a3c5bd6dSspeer * are shared equally across all the ports.
1655a3c5bd6dSspeer *
165658324dfcSspeer * Fair: DMA channels, RDC groups, TCAM, FCRAM are shared proportional
165758324dfcSspeer * to the port speed.
1658a3c5bd6dSspeer *
1659a3c5bd6dSspeer *
1660a3c5bd6dSspeer * custom: DMA channels, RDC groups, TCAM, FCRAM partition is
1661a3c5bd6dSspeer * specified in nxge.conf. Need to read each parameter and set
1662a3c5bd6dSspeer * up the parameters in nxge structures.
1663a3c5bd6dSspeer *
1664a3c5bd6dSspeer */
1665a3c5bd6dSspeer switch (nxgep->niu_type) {
1666a3c5bd6dSspeer case N2_NIU:
1667a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, VPD_CTL,
166852ccf843Smisaki " ==> nxge_get_config_properties: N2"));
1669a3c5bd6dSspeer MUTEX_ENTER(&hw_p->nxge_cfg_lock);
1670a3c5bd6dSspeer if ((hw_p->flags & COMMON_CFG_VALID) !=
167152ccf843Smisaki COMMON_CFG_VALID) {
1672a3c5bd6dSspeer status = nxge_cfg_verify_set(nxgep,
167352ccf843Smisaki COMMON_RXDMA_GRP_CFG);
1674a3c5bd6dSspeer status = nxge_cfg_verify_set(nxgep,
167552ccf843Smisaki COMMON_CLASS_CFG);
1676a3c5bd6dSspeer hw_p->flags |= COMMON_CFG_VALID;
1677a3c5bd6dSspeer }
1678a3c5bd6dSspeer MUTEX_EXIT(&hw_p->nxge_cfg_lock);
1679a3c5bd6dSspeer status = nxge_use_cfg_n2niu_properties(nxgep);
1680a3c5bd6dSspeer break;
168159ac0c16Sdavemq default:
16822e59129aSraghus if (!NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
168359ac0c16Sdavemq NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
168459ac0c16Sdavemq " nxge_get_config_properties:"
168559ac0c16Sdavemq " unknown NIU type 0x%x", nxgep->niu_type));
168659ac0c16Sdavemq return (NXGE_ERROR);
1687a3c5bd6dSspeer }
168844961713Sgirish
1689a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, VPD_CTL,
169052ccf843Smisaki " ==> nxge_get_config_properties: Neptune"));
1691a3c5bd6dSspeer status = nxge_cfg_verify_set_quick_config(nxgep);
1692a3c5bd6dSspeer MUTEX_ENTER(&hw_p->nxge_cfg_lock);
1693a3c5bd6dSspeer if ((hw_p->flags & COMMON_CFG_VALID) !=
169452ccf843Smisaki COMMON_CFG_VALID) {
1695a3c5bd6dSspeer status = nxge_cfg_verify_set(nxgep,
169652ccf843Smisaki COMMON_TXDMA_CFG);
1697a3c5bd6dSspeer status = nxge_cfg_verify_set(nxgep,
169852ccf843Smisaki COMMON_RXDMA_CFG);
1699a3c5bd6dSspeer status = nxge_cfg_verify_set(nxgep,
170052ccf843Smisaki COMMON_RXDMA_GRP_CFG);
1701a3c5bd6dSspeer status = nxge_cfg_verify_set(nxgep,
170252ccf843Smisaki COMMON_CLASS_CFG);
1703a3c5bd6dSspeer hw_p->flags |= COMMON_CFG_VALID;
1704a3c5bd6dSspeer }
1705a3c5bd6dSspeer MUTEX_EXIT(&hw_p->nxge_cfg_lock);
1706a3c5bd6dSspeer nxge_use_cfg_neptune_properties(nxgep);
1707a3c5bd6dSspeer status = NXGE_OK;
1708a3c5bd6dSspeer break;
170944961713Sgirish }
171044961713Sgirish
17113d16f8e7Sml /*
17123d16f8e7Sml * Get the software LSO enable flag property from the
17133d16f8e7Sml * driver configuration file (nxge.conf).
17143d16f8e7Sml * This flag will be set to disable (0) if this property
17153d16f8e7Sml * does not exist.
17163d16f8e7Sml */
17173d16f8e7Sml nxgep->soft_lso_enable = ddi_prop_get_int(DDI_DEV_T_ANY, nxgep->dip,
17183d16f8e7Sml DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, "soft-lso-enable", 0);
17193d16f8e7Sml NXGE_DEBUG_MSG((nxgep, VPD_CTL,
17203d16f8e7Sml "nxge_get_config_properties: software lso %d\n",
17213d16f8e7Sml nxgep->soft_lso_enable));
17223d16f8e7Sml
17234df55fdeSJanie Lu nxgep->niu_hw_type = NIU_HW_TYPE_DEFAULT;
17244df55fdeSJanie Lu if (nxgep->niu_type == N2_NIU) {
17259d587972SSantwona Behera
17269d587972SSantwona Behera uchar_t *s_prop_val;
17279d587972SSantwona Behera
17284df55fdeSJanie Lu /*
17294df55fdeSJanie Lu * For NIU, the next generation KT has
17304df55fdeSJanie Lu * a few differences in features that the
17314df55fdeSJanie Lu * driver needs to handle them
17324df55fdeSJanie Lu * accordingly.
17334df55fdeSJanie Lu */
17344df55fdeSJanie Lu if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, nxgep->dip, 0,
17354df55fdeSJanie Lu "compatible", &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
17364df55fdeSJanie Lu for (i = 0; i < prop_len; i++) {
17374df55fdeSJanie Lu if ((strcmp((caddr_t)prop_val[i],
17384df55fdeSJanie Lu KT_NIU_COMPATIBLE) == 0)) {
17394df55fdeSJanie Lu nxgep->niu_hw_type = NIU_HW_TYPE_RF;
17404df55fdeSJanie Lu NXGE_DEBUG_MSG((nxgep, VPD_CTL,
17414df55fdeSJanie Lu "NIU type %d", nxgep->niu_hw_type));
17424df55fdeSJanie Lu break;
17434df55fdeSJanie Lu }
17444df55fdeSJanie Lu }
17454df55fdeSJanie Lu }
17464df55fdeSJanie Lu
17474df55fdeSJanie Lu ddi_prop_free(prop_val);
17489d587972SSantwona Behera /*
17499d587972SSantwona Behera * Some Serdes and PHY properties may also be provided as OBP
17509d587972SSantwona Behera * properties
17519d587972SSantwona Behera */
17529d587972SSantwona Behera if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
17539d587972SSantwona Behera "tx-cfg-l", &s_prop_val, &prop_len) == DDI_PROP_SUCCESS) {
17549d587972SSantwona Behera nxgep->srds_prop.tx_cfg_l =
17559d587972SSantwona Behera (uint16_t)(*(uint32_t *)s_prop_val);
17569d587972SSantwona Behera NXGE_DEBUG_MSG((nxgep, VPD_CTL,
17579d587972SSantwona Behera "nxge_get_config_properties: "
17589d587972SSantwona Behera "tx_cfg_l 0x%x, Read from OBP",
17599d587972SSantwona Behera nxgep->srds_prop.tx_cfg_l));
17609d587972SSantwona Behera nxgep->srds_prop.prop_set |= NXGE_SRDS_TXCFGL;
17619d587972SSantwona Behera ddi_prop_free(s_prop_val);
17629d587972SSantwona Behera }
17639d587972SSantwona Behera if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
17649d587972SSantwona Behera "tx-cfg-h", &s_prop_val, &prop_len) == DDI_PROP_SUCCESS) {
17659d587972SSantwona Behera nxgep->srds_prop.tx_cfg_h =
17669d587972SSantwona Behera (uint16_t)(*(uint32_t *)s_prop_val);
17679d587972SSantwona Behera NXGE_DEBUG_MSG((nxgep, VPD_CTL,
17689d587972SSantwona Behera "nxge_get_config_properties: "
17699d587972SSantwona Behera "tx_cfg_h 0x%x, Read from OBP",
17709d587972SSantwona Behera nxgep->srds_prop.tx_cfg_h));
17719d587972SSantwona Behera nxgep->srds_prop.prop_set |= NXGE_SRDS_TXCFGH;
17729d587972SSantwona Behera ddi_prop_free(s_prop_val);
17739d587972SSantwona Behera }
17749d587972SSantwona Behera if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
17759d587972SSantwona Behera "rx-cfg-l", &s_prop_val, &prop_len) == DDI_PROP_SUCCESS) {
17769d587972SSantwona Behera nxgep->srds_prop.rx_cfg_l =
17779d587972SSantwona Behera (uint16_t)(*(uint32_t *)s_prop_val);
17789d587972SSantwona Behera NXGE_DEBUG_MSG((nxgep, VPD_CTL,
17799d587972SSantwona Behera "nxge_get_config_properties: "
17809d587972SSantwona Behera "rx_cfg_l 0x%x, Read from OBP",
17819d587972SSantwona Behera nxgep->srds_prop.rx_cfg_l));
17829d587972SSantwona Behera nxgep->srds_prop.prop_set |= NXGE_SRDS_RXCFGL;
17839d587972SSantwona Behera ddi_prop_free(s_prop_val);
17849d587972SSantwona Behera }
17859d587972SSantwona Behera if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
17869d587972SSantwona Behera "rx-cfg-h", &s_prop_val, &prop_len) == DDI_PROP_SUCCESS) {
17879d587972SSantwona Behera nxgep->srds_prop.rx_cfg_h =
17889d587972SSantwona Behera (uint16_t)(*(uint32_t *)s_prop_val);
17899d587972SSantwona Behera NXGE_DEBUG_MSG((nxgep, VPD_CTL,
17909d587972SSantwona Behera "nxge_get_config_properties: "
17919d587972SSantwona Behera "rx_cfg_h 0x%x, Read from OBP",
17929d587972SSantwona Behera nxgep->srds_prop.rx_cfg_h));
17939d587972SSantwona Behera nxgep->srds_prop.prop_set |= NXGE_SRDS_RXCFGH;
17949d587972SSantwona Behera ddi_prop_free(s_prop_val);
17959d587972SSantwona Behera }
17969d587972SSantwona Behera if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
17979d587972SSantwona Behera "pll-cfg", &s_prop_val, &prop_len) == DDI_PROP_SUCCESS) {
17989d587972SSantwona Behera nxgep->srds_prop.pll_cfg_l =
17999d587972SSantwona Behera (uint16_t)(*(uint32_t *)s_prop_val);
18009d587972SSantwona Behera NXGE_DEBUG_MSG((nxgep, VPD_CTL,
18019d587972SSantwona Behera "nxge_get_config_properties: "
18029d587972SSantwona Behera "pll_cfg_l 0x%x, Read from OBP",
18039d587972SSantwona Behera nxgep->srds_prop.pll_cfg_l));
18049d587972SSantwona Behera nxgep->srds_prop.prop_set |= NXGE_SRDS_PLLCFGL;
18059d587972SSantwona Behera ddi_prop_free(s_prop_val);
18069d587972SSantwona Behera }
18079d587972SSantwona Behera if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
18089d587972SSantwona Behera "phy-reg-values", &s_prop_val, &prop_len) ==
18099d587972SSantwona Behera DDI_PROP_SUCCESS) {
18109d587972SSantwona Behera
18119d587972SSantwona Behera int tun_cnt, i;
18129d587972SSantwona Behera uchar_t *arr = s_prop_val;
18139d587972SSantwona Behera
18149d587972SSantwona Behera tun_cnt = prop_len / 6; /* 3 values, 2 bytes each */
18159d587972SSantwona Behera nxgep->phy_prop.arr =
18169d587972SSantwona Behera KMEM_ZALLOC(sizeof (nxge_phy_mdio_val_t) * tun_cnt,
18179d587972SSantwona Behera KM_SLEEP);
18189d587972SSantwona Behera nxgep->phy_prop.cnt = tun_cnt;
18199d587972SSantwona Behera for (i = 0; i < tun_cnt; i++) {
18209d587972SSantwona Behera nxgep->phy_prop.arr[i].dev = *(uint16_t *)arr;
18219d587972SSantwona Behera arr += 2;
18229d587972SSantwona Behera nxgep->phy_prop.arr[i].reg = *(uint16_t *)arr;
18239d587972SSantwona Behera arr += 2;
18249d587972SSantwona Behera nxgep->phy_prop.arr[i].val = *(uint16_t *)arr;
18259d587972SSantwona Behera arr += 2;
18269d587972SSantwona Behera NXGE_DEBUG_MSG((nxgep, VPD_CTL,
18279d587972SSantwona Behera "nxge_get_config_properties: From OBP, "
18289d587972SSantwona Behera "read PHY <dev.reg.val> = "
18299d587972SSantwona Behera "<0x%x.0x%x.0x%x>",
18309d587972SSantwona Behera nxgep->phy_prop.arr[i].dev,
18319d587972SSantwona Behera nxgep->phy_prop.arr[i].reg,
18329d587972SSantwona Behera nxgep->phy_prop.arr[i].val));
18339d587972SSantwona Behera }
18349d587972SSantwona Behera ddi_prop_free(s_prop_val);
18359d587972SSantwona Behera }
18364df55fdeSJanie Lu }
18374df55fdeSJanie Lu
183844961713Sgirish NXGE_DEBUG_MSG((nxgep, VPD_CTL, " <== nxge_get_config_properties"));
183944961713Sgirish return (status);
184044961713Sgirish }
184144961713Sgirish
184244961713Sgirish static nxge_status_t
nxge_use_cfg_n2niu_properties(p_nxge_t nxgep)184344961713Sgirish nxge_use_cfg_n2niu_properties(p_nxge_t nxgep)
184444961713Sgirish {
184544961713Sgirish nxge_status_t status = NXGE_OK;
184644961713Sgirish
184744961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_n2niu_properties"));
184844961713Sgirish
184944961713Sgirish status = nxge_use_default_dma_config_n2(nxgep);
185044961713Sgirish if (status != NXGE_OK) {
185144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
185252ccf843Smisaki " ==> nxge_use_cfg_n2niu_properties (err 0x%x)",
185352ccf843Smisaki status));
185444961713Sgirish return (status | NXGE_ERROR);
185544961713Sgirish }
185644961713Sgirish
185744961713Sgirish (void) nxge_use_cfg_vlan_class_config(nxgep);
185844961713Sgirish (void) nxge_use_cfg_mac_class_config(nxgep);
185944961713Sgirish (void) nxge_use_cfg_class_config(nxgep);
186044961713Sgirish (void) nxge_use_cfg_link_cfg(nxgep);
186144961713Sgirish
186244961713Sgirish /*
1863a3c5bd6dSspeer * Read in the hardware (fcode) properties. Use the ndd array to read
1864a3c5bd6dSspeer * each property.
186544961713Sgirish */
186644961713Sgirish (void) nxge_get_param_soft_properties(nxgep);
186744961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_n2niu_properties"));
186844961713Sgirish
186944961713Sgirish return (status);
187044961713Sgirish }
187144961713Sgirish
187244961713Sgirish static void
nxge_use_cfg_neptune_properties(p_nxge_t nxgep)187344961713Sgirish nxge_use_cfg_neptune_properties(p_nxge_t nxgep)
187444961713Sgirish {
1875a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_neptune_properties"));
187644961713Sgirish
187744961713Sgirish (void) nxge_use_cfg_dma_config(nxgep);
187844961713Sgirish (void) nxge_use_cfg_vlan_class_config(nxgep);
187944961713Sgirish (void) nxge_use_cfg_mac_class_config(nxgep);
188044961713Sgirish (void) nxge_use_cfg_class_config(nxgep);
188144961713Sgirish (void) nxge_use_cfg_link_cfg(nxgep);
188244961713Sgirish
188344961713Sgirish /*
1884a3c5bd6dSspeer * Read in the hardware (fcode) properties. Use the ndd array to read
1885a3c5bd6dSspeer * each property.
188644961713Sgirish */
188744961713Sgirish (void) nxge_get_param_soft_properties(nxgep);
1888a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_neptune_properties"));
188944961713Sgirish }
189044961713Sgirish
1891a3c5bd6dSspeer /*
1892952a2464SMichael Speer * FWARC 2006/556 for N2 NIU. Get the properties
1893952a2464SMichael Speer * from the prom.
1894a3c5bd6dSspeer */
189544961713Sgirish static nxge_status_t
nxge_use_default_dma_config_n2(p_nxge_t nxgep)189644961713Sgirish nxge_use_default_dma_config_n2(p_nxge_t nxgep)
189744961713Sgirish {
1898952a2464SMichael Speer int ndmas;
1899952a2464SMichael Speer uint8_t func;
1900952a2464SMichael Speer p_nxge_dma_pt_cfg_t p_dma_cfgp;
1901952a2464SMichael Speer p_nxge_hw_pt_cfg_t p_cfgp;
1902952a2464SMichael Speer int *prop_val;
1903952a2464SMichael Speer uint_t prop_len;
1904952a2464SMichael Speer int i;
1905952a2464SMichael Speer nxge_status_t status = NXGE_OK;
190644961713Sgirish
190744961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2"));
190844961713Sgirish
190944961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
191044961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
191144961713Sgirish
191244961713Sgirish func = nxgep->function_num;
191344961713Sgirish p_cfgp->function_number = func;
191444961713Sgirish ndmas = NXGE_TDMA_PER_NIU_PORT;
191544961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
191652ccf843Smisaki "tx-dma-channels", (int **)&prop_val,
191752ccf843Smisaki &prop_len) == DDI_PROP_SUCCESS) {
1918952a2464SMichael Speer if (prop_len != NXGE_NIU_TDMA_PROP_LEN) {
1919952a2464SMichael Speer ddi_prop_free(prop_val);
1920952a2464SMichael Speer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1921952a2464SMichael Speer "==> nxge_use_default_dma_config_n2: "
1922290b5530SMichael Speer "invalid tx-dma-channels property for the NIU, "
1923290b5530SMichael Speer "using defaults"));
1924290b5530SMichael Speer /*
1925290b5530SMichael Speer * Just failover to defaults
1926290b5530SMichael Speer */
1927290b5530SMichael Speer p_cfgp->tdc.start = (func * NXGE_TDMA_PER_NIU_PORT);
1928290b5530SMichael Speer ndmas = NXGE_TDMA_PER_NIU_PORT;
1929952a2464SMichael Speer } else {
1930952a2464SMichael Speer p_cfgp->tdc.start = prop_val[0];
1931952a2464SMichael Speer NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1932952a2464SMichael Speer "==> nxge_use_default_dma_config_n2: tdc starts %d "
1933952a2464SMichael Speer "(#%d)", p_cfgp->tdc.start, prop_len));
1934952a2464SMichael Speer
1935952a2464SMichael Speer ndmas = prop_val[1];
1936952a2464SMichael Speer NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1937952a2464SMichael Speer "==> nxge_use_default_dma_config_n2: #tdc %d (#%d)",
1938952a2464SMichael Speer ndmas, prop_len));
1939952a2464SMichael Speer ddi_prop_free(prop_val);
1940952a2464SMichael Speer }
194144961713Sgirish } else {
194244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
194352ccf843Smisaki "==> nxge_use_default_dma_config_n2: "
194452ccf843Smisaki "get tx-dma-channels failed"));
194544961713Sgirish return (NXGE_DDI_FAILED);
194644961713Sgirish }
194744961713Sgirish
1948da14cebeSEric Cheng p_cfgp->tdc.count = ndmas;
1949678453a8Sspeer p_cfgp->tdc.owned = p_cfgp->tdc.count;
195044961713Sgirish
195144961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: "
1952da14cebeSEric Cheng "p_cfgp 0x%llx max_tdcs %d start %d",
1953da14cebeSEric Cheng p_cfgp, p_cfgp->tdc.count, p_cfgp->tdc.start));
195444961713Sgirish
195544961713Sgirish /* Receive DMA */
195644961713Sgirish ndmas = NXGE_RDMA_PER_NIU_PORT;
195744961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
195852ccf843Smisaki "rx-dma-channels", (int **)&prop_val,
195952ccf843Smisaki &prop_len) == DDI_PROP_SUCCESS) {
1960290b5530SMichael Speer if (prop_len != NXGE_NIU_RDMA_PROP_LEN) {
1961952a2464SMichael Speer ddi_prop_free(prop_val);
1962952a2464SMichael Speer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1963952a2464SMichael Speer "==> nxge_use_default_dma_config_n2: "
1964290b5530SMichael Speer "invalid rx-dma-channels property for the NIU, "
1965290b5530SMichael Speer "using defaults"));
1966290b5530SMichael Speer /*
1967290b5530SMichael Speer * Just failover to defaults
1968290b5530SMichael Speer */
1969290b5530SMichael Speer p_cfgp->start_rdc = (func * NXGE_RDMA_PER_NIU_PORT);
1970290b5530SMichael Speer ndmas = NXGE_RDMA_PER_NIU_PORT;
1971952a2464SMichael Speer } else {
1972952a2464SMichael Speer p_cfgp->start_rdc = prop_val[0];
1973952a2464SMichael Speer NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1974952a2464SMichael Speer "==> nxge_use_default_dma_config_n2(obp):"
1975952a2464SMichael Speer " rdc start %d (#%d)",
1976952a2464SMichael Speer p_cfgp->start_rdc, prop_len));
1977952a2464SMichael Speer ndmas = prop_val[1];
1978952a2464SMichael Speer NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1979952a2464SMichael Speer "==> nxge_use_default_dma_config_n2(obp): "
1980952a2464SMichael Speer "#rdc %d (#%d)", ndmas, prop_len));
1981952a2464SMichael Speer ddi_prop_free(prop_val);
1982952a2464SMichael Speer }
198344961713Sgirish } else {
198444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
198552ccf843Smisaki "==> nxge_use_default_dma_config_n2: "
198652ccf843Smisaki "get rx-dma-channel failed"));
198744961713Sgirish return (NXGE_DDI_FAILED);
198844961713Sgirish }
198944961713Sgirish
1990da14cebeSEric Cheng p_cfgp->max_rdcs = ndmas;
199144961713Sgirish nxgep->rdc_mask = (ndmas - 1);
199244961713Sgirish
199344961713Sgirish /* Hypervisor: rdc # and group # use the same # !! */
1994678453a8Sspeer p_cfgp->max_grpids = p_cfgp->max_rdcs + p_cfgp->tdc.owned;
199544961713Sgirish p_cfgp->mif_ldvid = p_cfgp->mac_ldvid = p_cfgp->ser_ldvid = 0;
199644961713Sgirish
199744961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
199852ccf843Smisaki "interrupts", (int **)&prop_val,
199952ccf843Smisaki &prop_len) == DDI_PROP_SUCCESS) {
2000952a2464SMichael Speer if ((prop_len != NXGE_NIU_0_INTR_PROP_LEN) &&
2001952a2464SMichael Speer (prop_len != NXGE_NIU_1_INTR_PROP_LEN)) {
2002952a2464SMichael Speer ddi_prop_free(prop_val);
2003952a2464SMichael Speer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2004952a2464SMichael Speer "==> nxge_use_default_dma_config_n2: "
2005952a2464SMichael Speer "get interrupts failed"));
2006952a2464SMichael Speer return (NXGE_DDI_FAILED);
2007952a2464SMichael Speer }
2008952a2464SMichael Speer
200944961713Sgirish /*
2010a3c5bd6dSspeer * For each device assigned, the content of each interrupts
2011a3c5bd6dSspeer * property is its logical device group.
201244961713Sgirish *
2013a3c5bd6dSspeer * Assignment of interrupts property is in the the following
2014a3c5bd6dSspeer * order:
201544961713Sgirish *
2016a3c5bd6dSspeer * MAC MIF (if configured) SYSTEM ERROR (if configured) first
2017a3c5bd6dSspeer * receive channel next channel...... last receive channel
2018a3c5bd6dSspeer * first transmit channel next channel...... last transmit
2019a3c5bd6dSspeer * channel
202044961713Sgirish *
2021a3c5bd6dSspeer * prop_len should be at least for one mac and total # of rx and
2022a3c5bd6dSspeer * tx channels. Function 0 owns MIF and ERROR
202344961713Sgirish */
202444961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL,
202552ccf843Smisaki "==> nxge_use_default_dma_config_n2(obp): "
202652ccf843Smisaki "# interrupts %d", prop_len));
202744961713Sgirish
202844961713Sgirish switch (func) {
202944961713Sgirish case 0:
203044961713Sgirish p_cfgp->ldg_chn_start = 3;
203144961713Sgirish p_cfgp->mac_ldvid = NXGE_MAC_LD_PORT0;
203244961713Sgirish p_cfgp->mif_ldvid = NXGE_MIF_LD;
203344961713Sgirish p_cfgp->ser_ldvid = NXGE_SYS_ERROR_LD;
203444961713Sgirish
203544961713Sgirish break;
203644961713Sgirish case 1:
203744961713Sgirish p_cfgp->ldg_chn_start = 1;
203844961713Sgirish p_cfgp->mac_ldvid = NXGE_MAC_LD_PORT1;
203944961713Sgirish
204044961713Sgirish break;
204144961713Sgirish default:
204244961713Sgirish status = NXGE_DDI_FAILED;
204344961713Sgirish break;
204444961713Sgirish }
204544961713Sgirish
2046a3c5bd6dSspeer if (status != NXGE_OK)
204744961713Sgirish return (status);
204844961713Sgirish
204944961713Sgirish for (i = 0; i < prop_len; i++) {
205044961713Sgirish p_cfgp->ldg[i] = prop_val[i];
205144961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL,
205252ccf843Smisaki "==> nxge_use_default_dma_config_n2(obp): "
205352ccf843Smisaki "F%d: interrupt #%d, ldg %d",
205452ccf843Smisaki nxgep->function_num, i, p_cfgp->ldg[i]));
205544961713Sgirish }
205644961713Sgirish
205744961713Sgirish p_cfgp->max_grpids = prop_len;
205844961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL,
205952ccf843Smisaki "==> nxge_use_default_dma_config_n2(obp): %d "
206052ccf843Smisaki "(#%d) maxgrpids %d channel starts %d",
206152ccf843Smisaki p_cfgp->mac_ldvid, i, p_cfgp->max_grpids,
206252ccf843Smisaki p_cfgp->ldg_chn_start));
206344961713Sgirish ddi_prop_free(prop_val);
206444961713Sgirish } else {
206544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
206652ccf843Smisaki "==> nxge_use_default_dma_config_n2: "
206752ccf843Smisaki "get interrupts failed"));
206844961713Sgirish return (NXGE_DDI_FAILED);
206944961713Sgirish }
207044961713Sgirish
207144961713Sgirish p_cfgp->max_ldgs = p_cfgp->max_grpids;
207244961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL,
2073da14cebeSEric Cheng "==> nxge_use_default_dma_config_n2: p_cfgp 0x%llx max_rdcs %d "
2074da14cebeSEric Cheng "max_grpids %d macid %d mifid %d serrid %d",
2075da14cebeSEric Cheng p_cfgp, p_cfgp->max_rdcs, p_cfgp->max_grpids,
207652ccf843Smisaki p_cfgp->mac_ldvid, p_cfgp->mif_ldvid, p_cfgp->ser_ldvid));
207744961713Sgirish
2078da14cebeSEric Cheng
207944961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: "
208052ccf843Smisaki "p_cfgp p%p start_ldg %d nxgep->max_ldgs %d",
208152ccf843Smisaki p_cfgp, p_cfgp->start_ldg, p_cfgp->max_ldgs));
208244961713Sgirish
208344961713Sgirish /*
2084a3c5bd6dSspeer * RDC groups and the beginning RDC group assigned to this function.
208544961713Sgirish */
2086da14cebeSEric Cheng p_cfgp->max_rdc_grpids = NXGE_MAX_RDC_GROUPS / nxgep->nports;
2087da14cebeSEric Cheng p_cfgp->def_mac_rxdma_grpid =
2088da14cebeSEric Cheng nxgep->function_num * NXGE_MAX_RDC_GROUPS / nxgep->nports;
2089da14cebeSEric Cheng p_cfgp->def_mac_txdma_grpid =
2090da14cebeSEric Cheng nxgep->function_num * NXGE_MAX_TDC_GROUPS / nxgep->nports;
2091da14cebeSEric Cheng
2092da14cebeSEric Cheng if ((p_cfgp->def_mac_rxdma_grpid = nxge_fzc_rdc_tbl_bind(nxgep,
2093da14cebeSEric Cheng p_cfgp->def_mac_rxdma_grpid, B_TRUE)) >= NXGE_MAX_RDC_GRPS) {
2094678453a8Sspeer NXGE_ERROR_MSG((nxgep, CFG_CTL,
2095678453a8Sspeer "nxge_use_default_dma_config_n2(): "
2096678453a8Sspeer "nxge_fzc_rdc_tbl_bind failed"));
2097678453a8Sspeer return (NXGE_DDI_FAILED);
2098678453a8Sspeer }
209944961713Sgirish
210044961713Sgirish status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
2101678453a8Sspeer "rx-rdc-grps", p_cfgp->max_rdc_grpids);
210244961713Sgirish if (status) {
210344961713Sgirish return (NXGE_DDI_FAILED);
210444961713Sgirish }
210544961713Sgirish status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
210652ccf843Smisaki "rx-rdc-grps-begin", p_cfgp->def_mac_rxdma_grpid);
210744961713Sgirish if (status) {
210844961713Sgirish (void) ddi_prop_remove(DDI_DEV_T_NONE, nxgep->dip,
210952ccf843Smisaki "rx-rdc-grps");
211044961713Sgirish return (NXGE_DDI_FAILED);
211144961713Sgirish }
211244961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: "
211352ccf843Smisaki "p_cfgp $%p # rdc groups %d start rdc group id %d",
211452ccf843Smisaki p_cfgp, p_cfgp->max_rdc_grpids,
211552ccf843Smisaki p_cfgp->def_mac_rxdma_grpid));
211644961713Sgirish
2117c1f9c6e5SSantwona Behera nxgep->intr_timeout = NXGE_RDC_RCR_TIMEOUT;
2118c1f9c6e5SSantwona Behera if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
2119c1f9c6e5SSantwona Behera "rxdma-intr-time", (int **)&prop_val, &prop_len) ==
2120c1f9c6e5SSantwona Behera DDI_PROP_SUCCESS) {
2121c1f9c6e5SSantwona Behera if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) {
2122c1f9c6e5SSantwona Behera nxgep->intr_timeout = prop_val[0];
2123c1f9c6e5SSantwona Behera (void) ddi_prop_update_int_array(DDI_DEV_T_NONE,
2124c1f9c6e5SSantwona Behera nxgep->dip, "rxdma-intr-time", prop_val, prop_len);
2125c1f9c6e5SSantwona Behera }
2126c1f9c6e5SSantwona Behera ddi_prop_free(prop_val);
2127c1f9c6e5SSantwona Behera }
2128c1f9c6e5SSantwona Behera
2129c1f9c6e5SSantwona Behera nxgep->intr_threshold = NXGE_RDC_RCR_THRESHOLD;
2130c1f9c6e5SSantwona Behera if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
2131c1f9c6e5SSantwona Behera "rxdma-intr-pkts", (int **)&prop_val, &prop_len) ==
2132c1f9c6e5SSantwona Behera DDI_PROP_SUCCESS) {
2133c1f9c6e5SSantwona Behera if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) {
2134c1f9c6e5SSantwona Behera nxgep->intr_threshold = prop_val[0];
2135c1f9c6e5SSantwona Behera (void) ddi_prop_update_int_array(DDI_DEV_T_NONE,
2136c1f9c6e5SSantwona Behera nxgep->dip, "rxdma-intr-pkts", prop_val, prop_len);
2137c1f9c6e5SSantwona Behera }
2138c1f9c6e5SSantwona Behera ddi_prop_free(prop_val);
2139c1f9c6e5SSantwona Behera }
2140c1f9c6e5SSantwona Behera
214144961713Sgirish nxge_set_hw_dma_config(nxgep);
214244961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, "<== nxge_use_default_dma_config_n2"));
214344961713Sgirish return (status);
214444961713Sgirish }
214544961713Sgirish
214644961713Sgirish static void
nxge_use_cfg_dma_config(p_nxge_t nxgep)214744961713Sgirish nxge_use_cfg_dma_config(p_nxge_t nxgep)
214844961713Sgirish {
214959ac0c16Sdavemq int tx_ndmas, rx_ndmas, nrxgp, st_txdma, st_rxdma;
2150a3c5bd6dSspeer p_nxge_dma_pt_cfg_t p_dma_cfgp;
2151a3c5bd6dSspeer p_nxge_hw_pt_cfg_t p_cfgp;
215244961713Sgirish dev_info_t *dip;
215344961713Sgirish p_nxge_param_t param_arr;
215444961713Sgirish char *prop;
2155a3c5bd6dSspeer int *prop_val;
2156a3c5bd6dSspeer uint_t prop_len;
215759ac0c16Sdavemq int i;
215859ac0c16Sdavemq uint8_t *ch_arr_p;
215944961713Sgirish
216044961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_dma_config"));
216144961713Sgirish param_arr = nxgep->param_arr;
216244961713Sgirish
216344961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
216444961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
216544961713Sgirish dip = nxgep->dip;
216644961713Sgirish p_cfgp->function_number = nxgep->function_num;
216744961713Sgirish prop = param_arr[param_txdma_channels_begin].fcode_name;
216844961713Sgirish
216944961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
217052ccf843Smisaki &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
2171678453a8Sspeer p_cfgp->tdc.start = *prop_val;
217244961713Sgirish ddi_prop_free(prop_val);
217344961713Sgirish } else {
217459ac0c16Sdavemq switch (nxgep->niu_type) {
217559ac0c16Sdavemq case NEPTUNE_4_1GC:
217659ac0c16Sdavemq ch_arr_p = &tx_4_1G[0];
217759ac0c16Sdavemq break;
217859ac0c16Sdavemq case NEPTUNE_2_10GF:
217959ac0c16Sdavemq ch_arr_p = &tx_2_10G[0];
218059ac0c16Sdavemq break;
218159ac0c16Sdavemq case NEPTUNE_2_10GF_2_1GC:
218259a835ddSjoycey case NEPTUNE_2_10GF_2_1GRF:
218359ac0c16Sdavemq ch_arr_p = &tx_2_10G_2_1G[0];
218459ac0c16Sdavemq break;
218559ac0c16Sdavemq case NEPTUNE_1_10GF_3_1GC:
218659ac0c16Sdavemq ch_arr_p = &tx_1_10G_3_1G[0];
218759ac0c16Sdavemq break;
218859ac0c16Sdavemq case NEPTUNE_1_1GC_1_10GF_2_1GC:
218959ac0c16Sdavemq ch_arr_p = &tx_1_1G_1_10G_2_1G[0];
219059ac0c16Sdavemq break;
219159ac0c16Sdavemq default:
2192d81011f0Ssbehera switch (nxgep->platform_type) {
2193d81011f0Ssbehera case P_NEPTUNE_ALONSO:
2194d81011f0Ssbehera ch_arr_p = &tx_2_10G_2_1G[0];
2195d81011f0Ssbehera break;
2196d81011f0Ssbehera default:
2197d81011f0Ssbehera ch_arr_p = &p4_tx_equal[0];
2198d81011f0Ssbehera break;
2199d81011f0Ssbehera }
220059ac0c16Sdavemq break;
220144961713Sgirish }
220259ac0c16Sdavemq st_txdma = 0;
220359ac0c16Sdavemq for (i = 0; i < nxgep->function_num; i++, ch_arr_p++)
220459ac0c16Sdavemq st_txdma += *ch_arr_p;
220559ac0c16Sdavemq
2206a3c5bd6dSspeer (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
220759ac0c16Sdavemq prop, st_txdma);
2208678453a8Sspeer p_cfgp->tdc.start = st_txdma;
220944961713Sgirish }
221044961713Sgirish
221144961713Sgirish prop = param_arr[param_txdma_channels].fcode_name;
221244961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
221352ccf843Smisaki &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
221444961713Sgirish tx_ndmas = *prop_val;
221544961713Sgirish ddi_prop_free(prop_val);
221644961713Sgirish } else {
221759ac0c16Sdavemq switch (nxgep->niu_type) {
221859ac0c16Sdavemq case NEPTUNE_4_1GC:
221959ac0c16Sdavemq tx_ndmas = tx_4_1G[nxgep->function_num];
222059ac0c16Sdavemq break;
222159ac0c16Sdavemq case NEPTUNE_2_10GF:
222259ac0c16Sdavemq tx_ndmas = tx_2_10G[nxgep->function_num];
222359ac0c16Sdavemq break;
222459ac0c16Sdavemq case NEPTUNE_2_10GF_2_1GC:
222559a835ddSjoycey case NEPTUNE_2_10GF_2_1GRF:
222659ac0c16Sdavemq tx_ndmas = tx_2_10G_2_1G[nxgep->function_num];
222759ac0c16Sdavemq break;
222859ac0c16Sdavemq case NEPTUNE_1_10GF_3_1GC:
222959ac0c16Sdavemq tx_ndmas = tx_1_10G_3_1G[nxgep->function_num];
223059ac0c16Sdavemq break;
223159ac0c16Sdavemq case NEPTUNE_1_1GC_1_10GF_2_1GC:
223259ac0c16Sdavemq tx_ndmas = tx_1_1G_1_10G_2_1G[nxgep->function_num];
223359ac0c16Sdavemq break;
223459ac0c16Sdavemq default:
2235d81011f0Ssbehera switch (nxgep->platform_type) {
2236d81011f0Ssbehera case P_NEPTUNE_ALONSO:
2237d81011f0Ssbehera tx_ndmas = tx_2_10G_2_1G[nxgep->function_num];
2238d81011f0Ssbehera break;
2239d81011f0Ssbehera default:
2240d81011f0Ssbehera tx_ndmas = p4_tx_equal[nxgep->function_num];
2241d81011f0Ssbehera break;
2242d81011f0Ssbehera }
224359ac0c16Sdavemq break;
224444961713Sgirish }
2245a3c5bd6dSspeer (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
224652ccf843Smisaki prop, tx_ndmas);
224744961713Sgirish }
224844961713Sgirish
2249da14cebeSEric Cheng p_cfgp->tdc.count = tx_ndmas;
2250678453a8Sspeer p_cfgp->tdc.owned = p_cfgp->tdc.count;
225144961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_dma_config: "
2252da14cebeSEric Cheng "p_cfgp 0x%llx max_tdcs %d", p_cfgp, p_cfgp->tdc.count));
225344961713Sgirish
225444961713Sgirish prop = param_arr[param_rxdma_channels_begin].fcode_name;
225544961713Sgirish
225644961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
225752ccf843Smisaki &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
225844961713Sgirish p_cfgp->start_rdc = *prop_val;
225944961713Sgirish ddi_prop_free(prop_val);
226044961713Sgirish } else {
226159ac0c16Sdavemq switch (nxgep->niu_type) {
226259ac0c16Sdavemq case NEPTUNE_4_1GC:
226359ac0c16Sdavemq ch_arr_p = &rx_4_1G[0];
226459ac0c16Sdavemq break;
226559ac0c16Sdavemq case NEPTUNE_2_10GF:
226659ac0c16Sdavemq ch_arr_p = &rx_2_10G[0];
226759ac0c16Sdavemq break;
226859ac0c16Sdavemq case NEPTUNE_2_10GF_2_1GC:
226959a835ddSjoycey case NEPTUNE_2_10GF_2_1GRF:
227059ac0c16Sdavemq ch_arr_p = &rx_2_10G_2_1G[0];
227159ac0c16Sdavemq break;
227259ac0c16Sdavemq case NEPTUNE_1_10GF_3_1GC:
227359ac0c16Sdavemq ch_arr_p = &rx_1_10G_3_1G[0];
227459ac0c16Sdavemq break;
227559ac0c16Sdavemq case NEPTUNE_1_1GC_1_10GF_2_1GC:
227659ac0c16Sdavemq ch_arr_p = &rx_1_1G_1_10G_2_1G[0];
227759ac0c16Sdavemq break;
227859ac0c16Sdavemq default:
2279d81011f0Ssbehera switch (nxgep->platform_type) {
2280d81011f0Ssbehera case P_NEPTUNE_ALONSO:
2281d81011f0Ssbehera ch_arr_p = &rx_2_10G_2_1G[0];
2282d81011f0Ssbehera break;
2283d81011f0Ssbehera default:
2284d81011f0Ssbehera ch_arr_p = &p4_rx_equal[0];
2285d81011f0Ssbehera break;
2286d81011f0Ssbehera }
228759ac0c16Sdavemq break;
228844961713Sgirish }
228959ac0c16Sdavemq st_rxdma = 0;
229059ac0c16Sdavemq for (i = 0; i < nxgep->function_num; i++, ch_arr_p++)
229159ac0c16Sdavemq st_rxdma += *ch_arr_p;
229259ac0c16Sdavemq
2293a3c5bd6dSspeer (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
229459ac0c16Sdavemq prop, st_rxdma);
229559ac0c16Sdavemq p_cfgp->start_rdc = st_rxdma;
229644961713Sgirish }
229744961713Sgirish
229844961713Sgirish prop = param_arr[param_rxdma_channels].fcode_name;
229944961713Sgirish
230044961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
230152ccf843Smisaki &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
230244961713Sgirish rx_ndmas = *prop_val;
230344961713Sgirish ddi_prop_free(prop_val);
230444961713Sgirish } else {
230559ac0c16Sdavemq switch (nxgep->niu_type) {
230659ac0c16Sdavemq case NEPTUNE_4_1GC:
230759ac0c16Sdavemq rx_ndmas = rx_4_1G[nxgep->function_num];
230859ac0c16Sdavemq break;
230959ac0c16Sdavemq case NEPTUNE_2_10GF:
231059ac0c16Sdavemq rx_ndmas = rx_2_10G[nxgep->function_num];
231159ac0c16Sdavemq break;
231259ac0c16Sdavemq case NEPTUNE_2_10GF_2_1GC:
231359a835ddSjoycey case NEPTUNE_2_10GF_2_1GRF:
231459ac0c16Sdavemq rx_ndmas = rx_2_10G_2_1G[nxgep->function_num];
231559ac0c16Sdavemq break;
231659ac0c16Sdavemq case NEPTUNE_1_10GF_3_1GC:
231759ac0c16Sdavemq rx_ndmas = rx_1_10G_3_1G[nxgep->function_num];
231859ac0c16Sdavemq break;
231959ac0c16Sdavemq case NEPTUNE_1_1GC_1_10GF_2_1GC:
232059ac0c16Sdavemq rx_ndmas = rx_1_1G_1_10G_2_1G[nxgep->function_num];
232159ac0c16Sdavemq break;
232259ac0c16Sdavemq default:
2323d81011f0Ssbehera switch (nxgep->platform_type) {
2324d81011f0Ssbehera case P_NEPTUNE_ALONSO:
2325d81011f0Ssbehera rx_ndmas = rx_2_10G_2_1G[nxgep->function_num];
2326d81011f0Ssbehera break;
2327d81011f0Ssbehera default:
2328d81011f0Ssbehera rx_ndmas = p4_rx_equal[nxgep->function_num];
2329d81011f0Ssbehera break;
2330d81011f0Ssbehera }
233159ac0c16Sdavemq break;
233244961713Sgirish }
2333a3c5bd6dSspeer (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
233452ccf843Smisaki prop, rx_ndmas);
233544961713Sgirish }
233644961713Sgirish
2337da14cebeSEric Cheng p_cfgp->max_rdcs = rx_ndmas;
233844961713Sgirish
2339da14cebeSEric Cheng /*
2340da14cebeSEric Cheng * RDC groups and the beginning RDC group assigned to this function.
2341da14cebeSEric Cheng * XXX: this may be wrong if prop value is used.
2342da14cebeSEric Cheng */
2343da14cebeSEric Cheng p_cfgp->def_mac_rxdma_grpid =
2344da14cebeSEric Cheng nxgep->function_num * NXGE_MAX_RDC_GROUPS / nxgep->nports;
2345da14cebeSEric Cheng p_cfgp->def_mac_txdma_grpid =
2346da14cebeSEric Cheng nxgep->function_num * NXGE_MAX_TDC_GROUPS / nxgep->nports;
2347678453a8Sspeer
2348da14cebeSEric Cheng if ((p_cfgp->def_mac_rxdma_grpid = nxge_fzc_rdc_tbl_bind(nxgep,
2349da14cebeSEric Cheng p_cfgp->def_mac_rxdma_grpid, B_TRUE)) >= NXGE_MAX_RDC_GRPS) {
2350da14cebeSEric Cheng NXGE_ERROR_MSG((nxgep, CFG_CTL,
2351da14cebeSEric Cheng "nxge_use_default_dma_config2(): "
2352da14cebeSEric Cheng "nxge_fzc_rdc_tbl_bind failed"));
2353da14cebeSEric Cheng goto nxge_use_cfg_dma_config_exit;
235444961713Sgirish }
235544961713Sgirish
235644961713Sgirish prop = param_arr[param_rx_rdc_grps].fcode_name;
235744961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
235852ccf843Smisaki &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
235944961713Sgirish nrxgp = *prop_val;
236044961713Sgirish ddi_prop_free(prop_val);
236144961713Sgirish } else {
2362da14cebeSEric Cheng nrxgp = NXGE_MAX_RDC_GRPS / nxgep->nports;
2363a3c5bd6dSspeer (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
236452ccf843Smisaki prop, nrxgp);
236544961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL,
236652ccf843Smisaki "==> nxge_use_default_dma_config: "
236752ccf843Smisaki "num_rdc_grpid not found: use def:# of "
236852ccf843Smisaki "rdc groups %d\n", nrxgp));
236944961713Sgirish }
237044961713Sgirish p_cfgp->max_rdc_grpids = nrxgp;
237144961713Sgirish
237244961713Sgirish /*
2373a3c5bd6dSspeer * 2/4 ports have the same hard-wired logical groups assigned.
237444961713Sgirish */
237544961713Sgirish p_cfgp->start_ldg = nxgep->function_num * NXGE_LDGRP_PER_4PORTS;
237644961713Sgirish p_cfgp->max_ldgs = NXGE_LDGRP_PER_4PORTS;
237744961713Sgirish
237844961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_default_dma_config: "
2379da14cebeSEric Cheng "p_cfgp 0x%llx max_rdcs %d max_grpids %d default_grpid %d",
2380da14cebeSEric Cheng p_cfgp, p_cfgp->max_rdcs, p_cfgp->max_grpids,
2381da14cebeSEric Cheng p_cfgp->def_mac_rxdma_grpid));
238244961713Sgirish
238344961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_dma_config: "
238452ccf843Smisaki "p_cfgp 0x%016llx start_ldg %d nxgep->max_ldgs %d "
238552ccf843Smisaki "def_mac_rxdma_grpid %d",
238652ccf843Smisaki p_cfgp, p_cfgp->start_ldg, p_cfgp->max_ldgs,
238752ccf843Smisaki p_cfgp->def_mac_rxdma_grpid));
238844961713Sgirish
2389c1f9c6e5SSantwona Behera nxgep->intr_timeout = NXGE_RDC_RCR_TIMEOUT;
239044961713Sgirish prop = param_arr[param_rxdma_intr_time].fcode_name;
239144961713Sgirish
239244961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
239352ccf843Smisaki &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
239444961713Sgirish if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) {
2395c1f9c6e5SSantwona Behera nxgep->intr_timeout = prop_val[0];
2396a3c5bd6dSspeer (void) ddi_prop_update_int_array(DDI_DEV_T_NONE,
239752ccf843Smisaki nxgep->dip, prop, prop_val, prop_len);
239844961713Sgirish }
239944961713Sgirish ddi_prop_free(prop_val);
240044961713Sgirish }
2401c1f9c6e5SSantwona Behera
2402c1f9c6e5SSantwona Behera nxgep->intr_threshold = NXGE_RDC_RCR_THRESHOLD;
240344961713Sgirish prop = param_arr[param_rxdma_intr_pkts].fcode_name;
240444961713Sgirish
240544961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
240652ccf843Smisaki &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
240744961713Sgirish if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) {
2408c1f9c6e5SSantwona Behera nxgep->intr_threshold = prop_val[0];
2409a3c5bd6dSspeer (void) ddi_prop_update_int_array(DDI_DEV_T_NONE,
241052ccf843Smisaki nxgep->dip, prop, prop_val, prop_len);
241144961713Sgirish }
241244961713Sgirish ddi_prop_free(prop_val);
241344961713Sgirish }
241444961713Sgirish nxge_set_hw_dma_config(nxgep);
2415a3c5bd6dSspeer
241659ac0c16Sdavemq NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_dma_config: "
241759ac0c16Sdavemq "sTDC[%d] nTDC[%d] sRDC[%d] nRDC[%d]",
2418678453a8Sspeer p_cfgp->tdc.start, p_cfgp->tdc.count,
241959ac0c16Sdavemq p_cfgp->start_rdc, p_cfgp->max_rdcs));
242059ac0c16Sdavemq
2421678453a8Sspeer nxge_use_cfg_dma_config_exit:
242244961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_dma_config"));
242344961713Sgirish }
242444961713Sgirish
2425678453a8Sspeer void
nxge_get_logical_props(p_nxge_t nxgep)2426678453a8Sspeer nxge_get_logical_props(p_nxge_t nxgep)
2427678453a8Sspeer {
2428678453a8Sspeer nxge_dma_pt_cfg_t *port = &nxgep->pt_config;
2429678453a8Sspeer nxge_hw_pt_cfg_t *hardware;
2430678453a8Sspeer nxge_rdc_grp_t *group;
2431678453a8Sspeer
2432678453a8Sspeer (void) memset(port, 0, sizeof (*port));
2433678453a8Sspeer
2434da14cebeSEric Cheng port->mac_port = nxgep->function_num; /* := function number */
2435678453a8Sspeer
2436678453a8Sspeer /*
2437678453a8Sspeer * alloc_buf_size:
2438678453a8Sspeer * dead variables.
2439678453a8Sspeer */
2440678453a8Sspeer port->rbr_size = nxge_rbr_size;
2441678453a8Sspeer port->rcr_size = nxge_rcr_size;
2442678453a8Sspeer
2443678453a8Sspeer port->tx_dma_map = 0; /* Transmit DMA channel bit map */
2444678453a8Sspeer
2445678453a8Sspeer nxge_set_rdc_intr_property(nxgep);
2446678453a8Sspeer
2447678453a8Sspeer port->rcr_full_header = NXGE_RCR_FULL_HEADER;
2448678453a8Sspeer port->rx_drr_weight = PT_DRR_WT_DEFAULT_10G;
2449678453a8Sspeer
2450678453a8Sspeer /* ----------------------------------------------------- */
2451678453a8Sspeer hardware = &port->hw_config;
2452678453a8Sspeer
2453678453a8Sspeer (void) memset(hardware, 0, sizeof (*hardware));
2454678453a8Sspeer
2455678453a8Sspeer /*
2456678453a8Sspeer * partition_id, read_write_mode:
2457678453a8Sspeer * dead variables.
2458678453a8Sspeer */
2459678453a8Sspeer
2460678453a8Sspeer /*
2461678453a8Sspeer * drr_wt, rx_full_header, *_ldg?, start_mac_entry,
2462678453a8Sspeer * mac_pref, def_mac_rxdma_grpid, start_vlan, max_vlans,
2463678453a8Sspeer * start_ldgs, max_ldgs, max_ldvs,
2464678453a8Sspeer * vlan_pref, def_vlan_rxdma_grpid are meaningful only
2465678453a8Sspeer * in the service domain.
2466678453a8Sspeer */
2467678453a8Sspeer
2468678453a8Sspeer group = &port->rdc_grps[0];
2469678453a8Sspeer
2470da14cebeSEric Cheng group->flag = B_TRUE; /* configured */
2471678453a8Sspeer group->config_method = RDC_TABLE_ENTRY_METHOD_REP;
2472da14cebeSEric Cheng group->port = NXGE_GET_PORT_NUM(nxgep->function_num);
2473678453a8Sspeer
2474678453a8Sspeer /* HIO futures: this is still an open question. */
2475678453a8Sspeer hardware->max_macs = 1;
2476678453a8Sspeer }
2477678453a8Sspeer
247844961713Sgirish static void
nxge_use_cfg_vlan_class_config(p_nxge_t nxgep)247944961713Sgirish nxge_use_cfg_vlan_class_config(p_nxge_t nxgep)
248044961713Sgirish {
248144961713Sgirish uint_t vlan_cnt;
248244961713Sgirish int *vlan_cfg_val;
248344961713Sgirish int status;
248444961713Sgirish p_nxge_param_t param_arr;
248544961713Sgirish char *prop;
248644961713Sgirish
248744961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_vlan_config"));
248844961713Sgirish param_arr = nxgep->param_arr;
248944961713Sgirish prop = param_arr[param_vlan_2rdc_grp].fcode_name;
249044961713Sgirish
249144961713Sgirish status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
249252ccf843Smisaki &vlan_cfg_val, &vlan_cnt);
249344961713Sgirish if (status == DDI_PROP_SUCCESS) {
249444961713Sgirish status = ddi_prop_update_int_array(DDI_DEV_T_NONE,
249552ccf843Smisaki nxgep->dip, prop, vlan_cfg_val, vlan_cnt);
249644961713Sgirish ddi_prop_free(vlan_cfg_val);
249744961713Sgirish }
249844961713Sgirish nxge_set_hw_vlan_class_config(nxgep);
249944961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_vlan_config"));
250044961713Sgirish }
250144961713Sgirish
250244961713Sgirish static void
nxge_use_cfg_mac_class_config(p_nxge_t nxgep)250344961713Sgirish nxge_use_cfg_mac_class_config(p_nxge_t nxgep)
250444961713Sgirish {
2505a3c5bd6dSspeer p_nxge_dma_pt_cfg_t p_dma_cfgp;
2506a3c5bd6dSspeer p_nxge_hw_pt_cfg_t p_cfgp;
250744961713Sgirish uint_t mac_cnt;
250844961713Sgirish int *mac_cfg_val;
250944961713Sgirish int status;
251044961713Sgirish p_nxge_param_t param_arr;
251144961713Sgirish char *prop;
251244961713Sgirish
251344961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_mac_class_config"));
251444961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
251544961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
251644961713Sgirish p_cfgp->start_mac_entry = 0;
251744961713Sgirish param_arr = nxgep->param_arr;
251844961713Sgirish prop = param_arr[param_mac_2rdc_grp].fcode_name;
251944961713Sgirish
252044961713Sgirish switch (nxgep->function_num) {
252144961713Sgirish case 0:
252244961713Sgirish case 1:
252344961713Sgirish /* 10G ports */
252444961713Sgirish p_cfgp->max_macs = NXGE_MAX_MACS_XMACS;
252544961713Sgirish break;
252644961713Sgirish case 2:
252744961713Sgirish case 3:
252844961713Sgirish /* 1G ports */
252944961713Sgirish default:
253044961713Sgirish p_cfgp->max_macs = NXGE_MAX_MACS_BMACS;
253144961713Sgirish break;
253244961713Sgirish }
253344961713Sgirish
253444961713Sgirish p_cfgp->mac_pref = 1;
253544961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL,
253652ccf843Smisaki "== nxge_use_cfg_mac_class_config: "
253752ccf843Smisaki " mac_pref bit set def_mac_rxdma_grpid %d",
253852ccf843Smisaki p_cfgp->def_mac_rxdma_grpid));
253944961713Sgirish
254044961713Sgirish status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
254152ccf843Smisaki &mac_cfg_val, &mac_cnt);
254244961713Sgirish if (status == DDI_PROP_SUCCESS) {
254344961713Sgirish if (mac_cnt <= p_cfgp->max_macs)
254444961713Sgirish status = ddi_prop_update_int_array(DDI_DEV_T_NONE,
254552ccf843Smisaki nxgep->dip, prop, mac_cfg_val, mac_cnt);
254644961713Sgirish ddi_prop_free(mac_cfg_val);
254744961713Sgirish }
254844961713Sgirish nxge_set_hw_mac_class_config(nxgep);
254944961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_mac_class_config"));
255044961713Sgirish }
255144961713Sgirish
255244961713Sgirish static void
nxge_use_cfg_class_config(p_nxge_t nxgep)255344961713Sgirish nxge_use_cfg_class_config(p_nxge_t nxgep)
255444961713Sgirish {
255544961713Sgirish nxge_set_hw_class_config(nxgep);
255644961713Sgirish }
255744961713Sgirish
255844961713Sgirish static void
nxge_set_rdc_intr_property(p_nxge_t nxgep)255944961713Sgirish nxge_set_rdc_intr_property(p_nxge_t nxgep)
256044961713Sgirish {
2561a3c5bd6dSspeer int i;
2562a3c5bd6dSspeer p_nxge_dma_pt_cfg_t p_dma_cfgp;
2563a3c5bd6dSspeer
256444961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_rdc_intr_property"));
256544961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
256644961713Sgirish
256744961713Sgirish for (i = 0; i < NXGE_MAX_RDCS; i++) {
2568c1f9c6e5SSantwona Behera p_dma_cfgp->rcr_timeout[i] = nxgep->intr_timeout;
2569c1f9c6e5SSantwona Behera p_dma_cfgp->rcr_threshold[i] = nxgep->intr_threshold;
257044961713Sgirish }
257144961713Sgirish
257244961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_rdc_intr_property"));
257344961713Sgirish }
257444961713Sgirish
257544961713Sgirish static void
nxge_set_hw_dma_config(p_nxge_t nxgep)257644961713Sgirish nxge_set_hw_dma_config(p_nxge_t nxgep)
257744961713Sgirish {
2578da14cebeSEric Cheng int i, j, ngrps, bitmap, end, st_rdc;
2579da14cebeSEric Cheng p_nxge_dma_pt_cfg_t p_dma_cfgp;
2580da14cebeSEric Cheng p_nxge_hw_pt_cfg_t p_cfgp;
2581da14cebeSEric Cheng p_nxge_rdc_grp_t rdc_grp_p;
2582da14cebeSEric Cheng p_nxge_tdc_grp_t tdc_grp_p;
2583da14cebeSEric Cheng nxge_grp_t *group;
2584da14cebeSEric Cheng uint8_t nrdcs;
2585da14cebeSEric Cheng dc_map_t map = 0;
2586a3c5bd6dSspeer
258744961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_set_hw_dma_config"));
258844961713Sgirish
258944961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
259044961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
259144961713Sgirish
2592da14cebeSEric Cheng switch (nxgep->niu_type) {
2593da14cebeSEric Cheng case NEPTUNE_4_1GC:
2594da14cebeSEric Cheng case NEPTUNE_2_10GF_2_1GC:
2595da14cebeSEric Cheng case NEPTUNE_1_10GF_3_1GC:
2596da14cebeSEric Cheng case NEPTUNE_1_1GC_1_10GF_2_1GC:
2597da14cebeSEric Cheng case NEPTUNE_2_10GF_2_1GRF:
2598da14cebeSEric Cheng default:
2599da14cebeSEric Cheng ngrps = 2;
2600da14cebeSEric Cheng break;
2601da14cebeSEric Cheng case NEPTUNE_2_10GF:
2602da14cebeSEric Cheng case NEPTUNE_2_1GRF:
2603da14cebeSEric Cheng case N2_NIU:
2604da14cebeSEric Cheng ngrps = 4;
2605da14cebeSEric Cheng break;
2606da14cebeSEric Cheng }
2607da14cebeSEric Cheng
2608da14cebeSEric Cheng /*
2609da14cebeSEric Cheng * Setup TDC groups
2610da14cebeSEric Cheng */
261144961713Sgirish bitmap = 0;
2612678453a8Sspeer end = p_cfgp->tdc.start + p_cfgp->tdc.owned;
2613678453a8Sspeer for (i = p_cfgp->tdc.start; i < end; i++) {
261444961713Sgirish bitmap |= (1 << i);
261544961713Sgirish }
261644961713Sgirish
2617678453a8Sspeer nxgep->tx_set.owned.map |= bitmap; /* Owned, & not shared. */
2618da14cebeSEric Cheng nxgep->tx_set.owned.count = p_cfgp->tdc.owned;
2619da14cebeSEric Cheng p_dma_cfgp->tx_dma_map = bitmap;
2620678453a8Sspeer
2621da14cebeSEric Cheng for (i = 0; i < ngrps; i++) {
2622da14cebeSEric Cheng group = (nxge_grp_t *)nxge_grp_add(nxgep,
2623da14cebeSEric Cheng NXGE_TRANSMIT_GROUP);
2624da14cebeSEric Cheng tdc_grp_p = &p_dma_cfgp->tdc_grps[
2625da14cebeSEric Cheng p_cfgp->def_mac_txdma_grpid + i];
2626da14cebeSEric Cheng if (i == 0)
2627da14cebeSEric Cheng tdc_grp_p->map = bitmap;
2628da14cebeSEric Cheng else
2629da14cebeSEric Cheng tdc_grp_p->map = 0;
2630da14cebeSEric Cheng /* no ring is associated with a group initially */
2631da14cebeSEric Cheng tdc_grp_p->start_tdc = 0;
2632da14cebeSEric Cheng tdc_grp_p->max_tdcs = 0;
2633da14cebeSEric Cheng tdc_grp_p->grp_index = group->index;
2634da14cebeSEric Cheng }
2635678453a8Sspeer
2636da14cebeSEric Cheng /*
2637da14cebeSEric Cheng * Setup RDC groups
2638da14cebeSEric Cheng */
2639da14cebeSEric Cheng st_rdc = p_cfgp->start_rdc;
2640da14cebeSEric Cheng for (i = 0; i < ngrps; i++) {
2641da14cebeSEric Cheng /*
2642da14cebeSEric Cheng * All rings are associated with the default group initially
2643da14cebeSEric Cheng */
2644da14cebeSEric Cheng if (i == 0) {
2645da14cebeSEric Cheng /* default group */
2646da14cebeSEric Cheng switch (nxgep->niu_type) {
2647da14cebeSEric Cheng case NEPTUNE_4_1GC:
2648da14cebeSEric Cheng nrdcs = rx_4_1G[nxgep->function_num];
2649da14cebeSEric Cheng break;
2650da14cebeSEric Cheng case N2_NIU:
2651da14cebeSEric Cheng case NEPTUNE_2_10GF:
2652da14cebeSEric Cheng nrdcs = rx_2_10G[nxgep->function_num];
2653da14cebeSEric Cheng break;
2654da14cebeSEric Cheng case NEPTUNE_2_10GF_2_1GC:
2655da14cebeSEric Cheng nrdcs = rx_2_10G_2_1G[nxgep->function_num];
2656a3c5bd6dSspeer break;
2657da14cebeSEric Cheng case NEPTUNE_1_10GF_3_1GC:
2658da14cebeSEric Cheng nrdcs = rx_1_10G_3_1G[nxgep->function_num];
2659da14cebeSEric Cheng break;
2660da14cebeSEric Cheng case NEPTUNE_1_1GC_1_10GF_2_1GC:
2661da14cebeSEric Cheng nrdcs = rx_1_1G_1_10G_2_1G[nxgep->function_num];
2662a3c5bd6dSspeer break;
2663a3c5bd6dSspeer default:
2664da14cebeSEric Cheng switch (nxgep->platform_type) {
2665da14cebeSEric Cheng case P_NEPTUNE_ALONSO:
2666da14cebeSEric Cheng nrdcs =
2667da14cebeSEric Cheng rx_2_10G_2_1G[nxgep->function_num];
2668da14cebeSEric Cheng break;
2669da14cebeSEric Cheng default:
2670da14cebeSEric Cheng nrdcs = rx_4_1G[nxgep->function_num];
2671da14cebeSEric Cheng break;
2672da14cebeSEric Cheng }
2673a3c5bd6dSspeer break;
267444961713Sgirish }
2675257bdc55SMichael Speer
2676257bdc55SMichael Speer if (p_cfgp->max_rdcs < nrdcs)
2677257bdc55SMichael Speer nrdcs = p_cfgp->max_rdcs;
2678da14cebeSEric Cheng } else {
2679da14cebeSEric Cheng nrdcs = 0;
2680a3c5bd6dSspeer }
2681678453a8Sspeer
2682678453a8Sspeer rdc_grp_p = &p_dma_cfgp->rdc_grps[
268352ccf843Smisaki p_cfgp->def_mac_rxdma_grpid + i];
2684da14cebeSEric Cheng rdc_grp_p->start_rdc = st_rdc;
2685da14cebeSEric Cheng rdc_grp_p->max_rdcs = nrdcs;
2686678453a8Sspeer rdc_grp_p->def_rdc = rdc_grp_p->start_rdc;
268744961713Sgirish
268844961713Sgirish /* default to: 0, 1, 2, 3, ...., 0, 1, 2, 3.... */
2689da14cebeSEric Cheng if (nrdcs != 0) {
2690da14cebeSEric Cheng for (j = 0; j < nrdcs; j++) {
2691da14cebeSEric Cheng map |= (1 << j);
2692da14cebeSEric Cheng }
2693da14cebeSEric Cheng map <<= rdc_grp_p->start_rdc;
2694da14cebeSEric Cheng } else
2695da14cebeSEric Cheng map = 0;
2696678453a8Sspeer rdc_grp_p->map = map;
2697678453a8Sspeer
2698678453a8Sspeer nxgep->rx_set.owned.map |= map; /* Owned, & not shared. */
2699da14cebeSEric Cheng nxgep->rx_set.owned.count = nrdcs;
2700678453a8Sspeer
2701678453a8Sspeer group = (nxge_grp_t *)nxge_grp_add(nxgep, NXGE_RECEIVE_GROUP);
2702678453a8Sspeer
2703678453a8Sspeer rdc_grp_p->config_method = RDC_TABLE_ENTRY_METHOD_SEQ;
2704da14cebeSEric Cheng rdc_grp_p->flag = B_TRUE; /* This group has been configured. */
2705da14cebeSEric Cheng rdc_grp_p->grp_index = group->index;
2706da14cebeSEric Cheng rdc_grp_p->port = NXGE_GET_PORT_NUM(nxgep->function_num);
2707da14cebeSEric Cheng
2708da14cebeSEric Cheng map = 0;
270944961713Sgirish }
271044961713Sgirish
2711678453a8Sspeer
271244961713Sgirish /* default RDC */
2713a3c5bd6dSspeer p_cfgp->def_rdc = p_cfgp->start_rdc;
271444961713Sgirish nxgep->def_rdc = p_cfgp->start_rdc;
271544961713Sgirish
271644961713Sgirish /* full 18 byte header ? */
2717a3c5bd6dSspeer p_dma_cfgp->rcr_full_header = NXGE_RCR_FULL_HEADER;
271844961713Sgirish p_dma_cfgp->rx_drr_weight = PT_DRR_WT_DEFAULT_10G;
271944961713Sgirish if (nxgep->function_num > 1)
272044961713Sgirish p_dma_cfgp->rx_drr_weight = PT_DRR_WT_DEFAULT_1G;
272144961713Sgirish p_dma_cfgp->rbr_size = nxge_rbr_size;
2722a3c5bd6dSspeer p_dma_cfgp->rcr_size = nxge_rcr_size;
272344961713Sgirish
272444961713Sgirish nxge_set_rdc_intr_property(nxgep);
272544961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_hw_dma_config"));
272644961713Sgirish }
272744961713Sgirish
272844961713Sgirish boolean_t
nxge_check_rxdma_port_member(p_nxge_t nxgep,uint8_t rdc)272944961713Sgirish nxge_check_rxdma_port_member(p_nxge_t nxgep, uint8_t rdc)
273044961713Sgirish {
2731a3c5bd6dSspeer p_nxge_dma_pt_cfg_t p_dma_cfgp;
2732a3c5bd6dSspeer p_nxge_hw_pt_cfg_t p_cfgp;
273344961713Sgirish int status = B_TRUE;
2734a3c5bd6dSspeer
273544961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_rxdma_port_member"));
273644961713Sgirish
273744961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
273844961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
273944961713Sgirish
274044961713Sgirish /* Receive DMA Channels */
274144961713Sgirish if (rdc < p_cfgp->max_rdcs)
274244961713Sgirish status = B_TRUE;
274344961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_rxdma_port_member"));
274444961713Sgirish return (status);
274544961713Sgirish }
274644961713Sgirish
274744961713Sgirish boolean_t
nxge_check_txdma_port_member(p_nxge_t nxgep,uint8_t tdc)274844961713Sgirish nxge_check_txdma_port_member(p_nxge_t nxgep, uint8_t tdc)
274944961713Sgirish {
275044961713Sgirish int status = B_FALSE;
2751a3c5bd6dSspeer
2752678453a8Sspeer NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_txdma_port_member"));
275344961713Sgirish
2754678453a8Sspeer if (tdc >= nxgep->pt_config.hw_config.tdc.start &&
2755678453a8Sspeer tdc < nxgep->pt_config.hw_config.tdc.count)
275644961713Sgirish status = B_TRUE;
2757678453a8Sspeer
2758678453a8Sspeer NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_txdma_port_member"));
2759a3c5bd6dSspeer return (status);
276044961713Sgirish }
276144961713Sgirish
276244961713Sgirish boolean_t
nxge_check_rxdma_rdcgrp_member(p_nxge_t nxgep,uint8_t rdc_grp,uint8_t rdc)276344961713Sgirish nxge_check_rxdma_rdcgrp_member(p_nxge_t nxgep, uint8_t rdc_grp, uint8_t rdc)
276444961713Sgirish {
2765a3c5bd6dSspeer p_nxge_dma_pt_cfg_t p_dma_cfgp;
276644961713Sgirish int status = B_TRUE;
2767a3c5bd6dSspeer p_nxge_rdc_grp_t rdc_grp_p;
276844961713Sgirish
276944961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG2_CTL,
277052ccf843Smisaki " ==> nxge_check_rxdma_rdcgrp_member"));
277144961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " nxge_check_rxdma_rdcgrp_member"
277252ccf843Smisaki " rdc %d group %d", rdc, rdc_grp));
277344961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
277444961713Sgirish
277544961713Sgirish rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp];
2776a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " max %d ", rdc_grp_p->max_rdcs));
277744961713Sgirish if (rdc >= rdc_grp_p->max_rdcs) {
277844961713Sgirish status = B_FALSE;
277944961713Sgirish }
278044961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG2_CTL,
278152ccf843Smisaki " <== nxge_check_rxdma_rdcgrp_member"));
278244961713Sgirish return (status);
278344961713Sgirish }
278444961713Sgirish
278544961713Sgirish boolean_t
nxge_check_rdcgrp_port_member(p_nxge_t nxgep,uint8_t rdc_grp)278644961713Sgirish nxge_check_rdcgrp_port_member(p_nxge_t nxgep, uint8_t rdc_grp)
278744961713Sgirish {
2788a3c5bd6dSspeer p_nxge_dma_pt_cfg_t p_dma_cfgp;
2789a3c5bd6dSspeer p_nxge_hw_pt_cfg_t p_cfgp;
279044961713Sgirish int status = B_TRUE;
279144961713Sgirish
279244961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_rdcgrp_port_member"));
279344961713Sgirish
279444961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
279544961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
279644961713Sgirish
279744961713Sgirish if (rdc_grp >= p_cfgp->max_rdc_grpids)
279844961713Sgirish status = B_FALSE;
279944961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_rdcgrp_port_member"));
280044961713Sgirish return (status);
280144961713Sgirish }
280244961713Sgirish
280344961713Sgirish static void
nxge_set_hw_vlan_class_config(p_nxge_t nxgep)280444961713Sgirish nxge_set_hw_vlan_class_config(p_nxge_t nxgep)
280544961713Sgirish {
2806a3c5bd6dSspeer int i;
2807a3c5bd6dSspeer p_nxge_dma_pt_cfg_t p_dma_cfgp;
2808a3c5bd6dSspeer p_nxge_hw_pt_cfg_t p_cfgp;
280944961713Sgirish p_nxge_param_t param_arr;
281044961713Sgirish uint_t vlan_cnt;
281144961713Sgirish int *vlan_cfg_val;
281244961713Sgirish nxge_param_map_t *vmap;
281344961713Sgirish char *prop;
2814a3c5bd6dSspeer p_nxge_class_pt_cfg_t p_class_cfgp;
281544961713Sgirish uint32_t good_cfg[32];
281644961713Sgirish int good_count = 0;
2817a3c5bd6dSspeer nxge_mv_cfg_t *vlan_tbl;
281844961713Sgirish
281944961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_hw_vlan_config"));
282044961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
282144961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
282244961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
282344961713Sgirish
282444961713Sgirish param_arr = nxgep->param_arr;
282544961713Sgirish prop = param_arr[param_vlan_2rdc_grp].fcode_name;
282644961713Sgirish
2827a3c5bd6dSspeer /*
2828a3c5bd6dSspeer * By default, VLAN to RDC group mapping is disabled Need to read HW or
2829a3c5bd6dSspeer * .conf properties to find out if mapping is required
2830a3c5bd6dSspeer *
2831a3c5bd6dSspeer * Format
2832a3c5bd6dSspeer *
2833a3c5bd6dSspeer * uint32_t array, each array entry specifying the VLAN id and the
2834a3c5bd6dSspeer * mapping
2835a3c5bd6dSspeer *
2836a3c5bd6dSspeer * bit[30] = add bit[29] = remove bit[28] = preference bits[23-16] =
2837a3c5bd6dSspeer * rdcgrp bits[15-0] = VLAN ID ( )
2838a3c5bd6dSspeer */
2839a3c5bd6dSspeer
284044961713Sgirish for (i = 0; i < NXGE_MAX_VLANS; i++) {
284144961713Sgirish p_class_cfgp->vlan_tbl[i].flag = 0;
284244961713Sgirish }
284344961713Sgirish
284444961713Sgirish vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0];
284544961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
284652ccf843Smisaki &vlan_cfg_val, &vlan_cnt) == DDI_PROP_SUCCESS) {
284744961713Sgirish for (i = 0; i < vlan_cnt; i++) {
284844961713Sgirish vmap = (nxge_param_map_t *)&vlan_cfg_val[i];
284944961713Sgirish if ((vmap->param_id) &&
285052ccf843Smisaki (vmap->param_id < NXGE_MAX_VLANS) &&
28514df3b64dSToomas Soome (vmap->map_to < p_cfgp->max_rdc_grpids)) {
285244961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG2_CTL,
285352ccf843Smisaki " nxge_vlan_config mapping"
285452ccf843Smisaki " id %d grp %d",
285552ccf843Smisaki vmap->param_id, vmap->map_to));
285644961713Sgirish good_cfg[good_count] = vlan_cfg_val[i];
285744961713Sgirish if (vlan_tbl[vmap->param_id].flag == 0)
285844961713Sgirish good_count++;
285944961713Sgirish vlan_tbl[vmap->param_id].flag = 1;
286044961713Sgirish vlan_tbl[vmap->param_id].rdctbl =
2861678453a8Sspeer vmap->map_to + p_cfgp->def_mac_rxdma_grpid;
286244961713Sgirish vlan_tbl[vmap->param_id].mpr_npr = vmap->pref;
286344961713Sgirish }
286444961713Sgirish }
286544961713Sgirish ddi_prop_free(vlan_cfg_val);
286644961713Sgirish if (good_count != vlan_cnt) {
2867a3c5bd6dSspeer (void) ddi_prop_update_int_array(DDI_DEV_T_NONE,
286852ccf843Smisaki nxgep->dip, prop, (int *)good_cfg, good_count);
286944961713Sgirish }
287044961713Sgirish }
2871a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_set_hw_vlan_config"));
287244961713Sgirish }
287344961713Sgirish
287444961713Sgirish static void
nxge_set_hw_mac_class_config(p_nxge_t nxgep)287544961713Sgirish nxge_set_hw_mac_class_config(p_nxge_t nxgep)
287644961713Sgirish {
2877a3c5bd6dSspeer int i;
2878a3c5bd6dSspeer p_nxge_dma_pt_cfg_t p_dma_cfgp;
2879a3c5bd6dSspeer p_nxge_hw_pt_cfg_t p_cfgp;
288044961713Sgirish p_nxge_param_t param_arr;
288144961713Sgirish uint_t mac_cnt;
288244961713Sgirish int *mac_cfg_val;
288344961713Sgirish nxge_param_map_t *mac_map;
288444961713Sgirish char *prop;
2885a3c5bd6dSspeer p_nxge_class_pt_cfg_t p_class_cfgp;
288644961713Sgirish int good_count = 0;
288744961713Sgirish int good_cfg[NXGE_MAX_MACS];
2888a3c5bd6dSspeer nxge_mv_cfg_t *mac_host_info;
2889a3c5bd6dSspeer
289044961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_set_hw_mac_config"));
289144961713Sgirish
289244961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
289344961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
289444961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
2895a3c5bd6dSspeer mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0];
289644961713Sgirish
289744961713Sgirish param_arr = nxgep->param_arr;
289844961713Sgirish prop = param_arr[param_mac_2rdc_grp].fcode_name;
289944961713Sgirish
290044961713Sgirish for (i = 0; i < NXGE_MAX_MACS; i++) {
290144961713Sgirish p_class_cfgp->mac_host_info[i].flag = 0;
29027b9fa28bSspeer p_class_cfgp->mac_host_info[i].rdctbl =
29037b9fa28bSspeer p_cfgp->def_mac_rxdma_grpid;
290444961713Sgirish }
290544961713Sgirish
290644961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
290752ccf843Smisaki &mac_cfg_val, &mac_cnt) == DDI_PROP_SUCCESS) {
290844961713Sgirish for (i = 0; i < mac_cnt; i++) {
290944961713Sgirish mac_map = (nxge_param_map_t *)&mac_cfg_val[i];
291044961713Sgirish if ((mac_map->param_id < p_cfgp->max_macs) &&
29114df3b64dSToomas Soome (mac_map->map_to < p_cfgp->max_rdc_grpids)) {
291244961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG2_CTL,
291352ccf843Smisaki " nxge_mac_config mapping"
291452ccf843Smisaki " id %d grp %d",
291552ccf843Smisaki mac_map->param_id, mac_map->map_to));
291644961713Sgirish mac_host_info[mac_map->param_id].mpr_npr =
2917da14cebeSEric Cheng p_cfgp->mac_pref;
291844961713Sgirish mac_host_info[mac_map->param_id].rdctbl =
291952ccf843Smisaki mac_map->map_to +
292052ccf843Smisaki p_cfgp->def_mac_rxdma_grpid;
292144961713Sgirish good_cfg[good_count] = mac_cfg_val[i];
292244961713Sgirish if (mac_host_info[mac_map->param_id].flag == 0)
292344961713Sgirish good_count++;
292444961713Sgirish mac_host_info[mac_map->param_id].flag = 1;
292544961713Sgirish }
292644961713Sgirish }
292744961713Sgirish ddi_prop_free(mac_cfg_val);
292844961713Sgirish if (good_count != mac_cnt) {
2929a3c5bd6dSspeer (void) ddi_prop_update_int_array(DDI_DEV_T_NONE,
293052ccf843Smisaki nxgep->dip, prop, good_cfg, good_count);
293144961713Sgirish }
293244961713Sgirish }
2933a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_set_hw_mac_config"));
293444961713Sgirish }
293544961713Sgirish
293644961713Sgirish static void
nxge_set_hw_class_config(p_nxge_t nxgep)293744961713Sgirish nxge_set_hw_class_config(p_nxge_t nxgep)
293844961713Sgirish {
2939a3c5bd6dSspeer int i;
294044961713Sgirish p_nxge_param_t param_arr;
294144961713Sgirish int *int_prop_val;
294244961713Sgirish uint32_t cfg_value;
294344961713Sgirish char *prop;
2944a3c5bd6dSspeer p_nxge_class_pt_cfg_t p_class_cfgp;
294544961713Sgirish int start_prop, end_prop;
294644961713Sgirish uint_t prop_cnt;
2947c1f9c6e5SSantwona Behera int start_class, j = 0;
2948a3c5bd6dSspeer
294944961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_hw_class_config"));
295044961713Sgirish
295144961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
295244961713Sgirish param_arr = nxgep->param_arr;
2953c1f9c6e5SSantwona Behera start_prop = param_class_opt_ipv4_tcp;
295444961713Sgirish end_prop = param_class_opt_ipv6_sctp;
2955c1f9c6e5SSantwona Behera start_class = TCAM_CLASS_TCP_IPV4;
295644961713Sgirish
2957c1f9c6e5SSantwona Behera for (i = start_prop, j = 0; i <= end_prop; i++, j++) {
295844961713Sgirish prop = param_arr[i].fcode_name;
295944961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip,
296052ccf843Smisaki 0, prop, &int_prop_val,
296152ccf843Smisaki &prop_cnt) == DDI_PROP_SUCCESS) {
2962a3c5bd6dSspeer cfg_value = (uint32_t)*int_prop_val;
296344961713Sgirish ddi_prop_free(int_prop_val);
296444961713Sgirish } else {
296544961713Sgirish cfg_value = (uint32_t)param_arr[i].value;
296644961713Sgirish }
2967c1f9c6e5SSantwona Behera p_class_cfgp->class_cfg[start_class + j] = cfg_value;
296844961713Sgirish }
296944961713Sgirish
297044961713Sgirish prop = param_arr[param_h1_init_value].fcode_name;
297144961713Sgirish
297244961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
297352ccf843Smisaki &int_prop_val, &prop_cnt) == DDI_PROP_SUCCESS) {
2974a3c5bd6dSspeer cfg_value = (uint32_t)*int_prop_val;
2975a3c5bd6dSspeer ddi_prop_free(int_prop_val);
297644961713Sgirish } else {
297744961713Sgirish cfg_value = (uint32_t)param_arr[param_h1_init_value].value;
297844961713Sgirish }
297944961713Sgirish
298044961713Sgirish p_class_cfgp->init_h1 = (uint32_t)cfg_value;
298144961713Sgirish prop = param_arr[param_h2_init_value].fcode_name;
298244961713Sgirish
298344961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
298452ccf843Smisaki &int_prop_val, &prop_cnt) == DDI_PROP_SUCCESS) {
2985a3c5bd6dSspeer cfg_value = (uint32_t)*int_prop_val;
2986a3c5bd6dSspeer ddi_prop_free(int_prop_val);
298744961713Sgirish } else {
298844961713Sgirish cfg_value = (uint32_t)param_arr[param_h2_init_value].value;
298944961713Sgirish }
299044961713Sgirish
299144961713Sgirish p_class_cfgp->init_h2 = (uint16_t)cfg_value;
299244961713Sgirish NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_hw_class_config"));
299344961713Sgirish }
299444961713Sgirish
299544961713Sgirish nxge_status_t
nxge_ldgv_init_n2(p_nxge_t nxgep,int * navail_p,int * nrequired_p)299644961713Sgirish nxge_ldgv_init_n2(p_nxge_t nxgep, int *navail_p, int *nrequired_p)
299744961713Sgirish {
2998678453a8Sspeer int i, maxldvs, maxldgs, nldvs;
2999a3c5bd6dSspeer int ldv, endldg;
3000a3c5bd6dSspeer uint8_t func;
3001a3c5bd6dSspeer uint8_t channel;
3002a3c5bd6dSspeer uint8_t chn_start;
3003a3c5bd6dSspeer boolean_t own_sys_err = B_FALSE, own_fzc = B_FALSE;
3004a3c5bd6dSspeer p_nxge_dma_pt_cfg_t p_dma_cfgp;
3005a3c5bd6dSspeer p_nxge_hw_pt_cfg_t p_cfgp;
3006a3c5bd6dSspeer p_nxge_ldgv_t ldgvp;
3007a3c5bd6dSspeer p_nxge_ldg_t ldgp, ptr;
3008d7cf53fcSmisaki Miyashita p_nxge_ldv_t ldvp, sysldvp;
3009a3c5bd6dSspeer nxge_status_t status = NXGE_OK;
3010678453a8Sspeer nxge_grp_set_t *set;
301144961713Sgirish
301244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2"));
301344961713Sgirish if (!*navail_p) {
301444961713Sgirish *nrequired_p = 0;
301544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
301652ccf843Smisaki "<== nxge_ldgv_init:no avail"));
301744961713Sgirish return (NXGE_ERROR);
301844961713Sgirish }
301944961713Sgirish /*
3020a3c5bd6dSspeer * N2/NIU: one logical device owns one logical group. and each
3021a3c5bd6dSspeer * device/group will be assigned one vector by Hypervisor.
302244961713Sgirish */
302344961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
302444961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
302544961713Sgirish maxldgs = p_cfgp->max_ldgs;
302644961713Sgirish if (!maxldgs) {
302744961713Sgirish /* No devices configured. */
302844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_init_n2: "
302952ccf843Smisaki "no logical groups configured."));
303044961713Sgirish return (NXGE_ERROR);
303144961713Sgirish } else {
303244961713Sgirish maxldvs = maxldgs + 1;
303344961713Sgirish }
303444961713Sgirish
303544961713Sgirish /*
3036a3c5bd6dSspeer * If function zero instance, it needs to handle the system and MIF
3037a3c5bd6dSspeer * error interrupts. MIF interrupt may not be needed for N2/NIU.
303844961713Sgirish */
303944961713Sgirish func = nxgep->function_num;
304044961713Sgirish if (func == 0) {
304144961713Sgirish own_sys_err = B_TRUE;
304244961713Sgirish if (!p_cfgp->ser_ldvid) {
304344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
304452ccf843Smisaki "nxge_ldgv_init_n2: func 0, ERR ID not set!"));
304544961713Sgirish }
304644961713Sgirish /* MIF interrupt */
304744961713Sgirish if (!p_cfgp->mif_ldvid) {
304844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
304952ccf843Smisaki "nxge_ldgv_init_n2: func 0, MIF ID not set!"));
305044961713Sgirish }
305144961713Sgirish }
305244961713Sgirish
305344961713Sgirish /*
305444961713Sgirish * Assume single partition, each function owns mac.
305544961713Sgirish */
3056a3c5bd6dSspeer if (!nxge_use_partition)
305744961713Sgirish own_fzc = B_TRUE;
305844961713Sgirish
305944961713Sgirish ldgvp = nxgep->ldgvp;
306044961713Sgirish if (ldgvp == NULL) {
306144961713Sgirish ldgvp = KMEM_ZALLOC(sizeof (nxge_ldgv_t), KM_SLEEP);
306244961713Sgirish nxgep->ldgvp = ldgvp;
306344961713Sgirish ldgvp->maxldgs = (uint8_t)maxldgs;
306444961713Sgirish ldgvp->maxldvs = (uint8_t)maxldvs;
3065678453a8Sspeer ldgp = ldgvp->ldgp = KMEM_ZALLOC(
306652ccf843Smisaki sizeof (nxge_ldg_t) * maxldgs, KM_SLEEP);
3067678453a8Sspeer ldvp = ldgvp->ldvp = KMEM_ZALLOC(
306852ccf843Smisaki sizeof (nxge_ldv_t) * maxldvs, KM_SLEEP);
306944961713Sgirish } else {
307044961713Sgirish ldgp = ldgvp->ldgp;
307144961713Sgirish ldvp = ldgvp->ldvp;
307244961713Sgirish }
307344961713Sgirish
3074678453a8Sspeer ldgvp->ndma_ldvs = p_cfgp->tdc.owned + p_cfgp->max_rdcs;
307544961713Sgirish ldgvp->tmres = NXGE_TIMER_RESO;
307644961713Sgirish
307744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL,
307852ccf843Smisaki "==> nxge_ldgv_init_n2: maxldvs %d maxldgs %d",
307952ccf843Smisaki maxldvs, maxldgs));
3080a3c5bd6dSspeer
308144961713Sgirish /* logical start_ldg is ldv */
308244961713Sgirish ptr = ldgp;
308344961713Sgirish for (i = 0; i < maxldgs; i++) {
308444961713Sgirish ptr->func = func;
308544961713Sgirish ptr->arm = B_TRUE;
308644961713Sgirish ptr->vldg_index = (uint8_t)i;
308744961713Sgirish ptr->ldg_timer = NXGE_TIMER_LDG;
308844961713Sgirish ptr->ldg = p_cfgp->ldg[i];
308944961713Sgirish ptr->sys_intr_handler = nxge_intr;
309044961713Sgirish ptr->nldvs = 0;
309144961713Sgirish ptr->ldvp = NULL;
309244961713Sgirish ptr->nxgep = nxgep;
309344961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL,
309452ccf843Smisaki "==> nxge_ldgv_init_n2: maxldvs %d maxldgs %d "
309552ccf843Smisaki "ldg %d ldgptr $%p",
309652ccf843Smisaki maxldvs, maxldgs, ptr->ldg, ptr));
309744961713Sgirish ptr++;
309844961713Sgirish }
309944961713Sgirish
310044961713Sgirish endldg = NXGE_INT_MAX_LDG;
310144961713Sgirish nldvs = 0;
310244961713Sgirish ldgvp->nldvs = 0;
310344961713Sgirish ldgp->ldvp = NULL;
310444961713Sgirish *nrequired_p = 0;
310544961713Sgirish
310644961713Sgirish /*
3107a3c5bd6dSspeer * logical device group table is organized in the following order (same
3108a3c5bd6dSspeer * as what interrupt property has). function 0: owns MAC, MIF, error,
3109a3c5bd6dSspeer * rx, tx. function 1: owns MAC, rx, tx.
311044961713Sgirish */
311144961713Sgirish
311244961713Sgirish if (own_fzc && p_cfgp->mac_ldvid) {
311344961713Sgirish /* Each function should own MAC interrupt */
311444961713Sgirish ldv = p_cfgp->mac_ldvid;
311544961713Sgirish ldvp->ldv = (uint8_t)ldv;
311644961713Sgirish ldvp->is_mac = B_TRUE;
311744961713Sgirish ldvp->ldv_intr_handler = nxge_mac_intr;
311844961713Sgirish ldvp->ldv_ldf_masks = 0;
311944961713Sgirish ldvp->nxgep = nxgep;
312044961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL,
312152ccf843Smisaki "==> nxge_ldgv_init_n2(mac): maxldvs %d ldv %d "
312252ccf843Smisaki "ldg %d ldgptr $%p ldvptr $%p",
312352ccf843Smisaki maxldvs, ldv, ldgp->ldg, ldgp, ldvp));
312444961713Sgirish nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
312544961713Sgirish nldvs++;
312644961713Sgirish }
312744961713Sgirish
312844961713Sgirish if (own_fzc && p_cfgp->mif_ldvid) {
312944961713Sgirish ldv = p_cfgp->mif_ldvid;
313044961713Sgirish ldvp->ldv = (uint8_t)ldv;
313144961713Sgirish ldvp->is_mif = B_TRUE;
313244961713Sgirish ldvp->ldv_intr_handler = nxge_mif_intr;
313344961713Sgirish ldvp->ldv_ldf_masks = 0;
313444961713Sgirish ldvp->nxgep = nxgep;
313544961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL,
313652ccf843Smisaki "==> nxge_ldgv_init_n2(mif): maxldvs %d ldv %d "
313752ccf843Smisaki "ldg %d ldgptr $%p ldvptr $%p",
313852ccf843Smisaki maxldvs, ldv, ldgp->ldg, ldgp, ldvp));
313944961713Sgirish nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
314044961713Sgirish nldvs++;
314144961713Sgirish }
314244961713Sgirish
3143d7cf53fcSmisaki Miyashita /*
3144da14cebeSEric Cheng * HW based syserr interrupt for port0, and SW based syserr interrupt
3145da14cebeSEric Cheng * for port1
3146d7cf53fcSmisaki Miyashita */
314744961713Sgirish if (own_sys_err && p_cfgp->ser_ldvid) {
314844961713Sgirish ldv = p_cfgp->ser_ldvid;
314944961713Sgirish /*
315044961713Sgirish * Unmask the system interrupt states.
315144961713Sgirish */
315244961713Sgirish (void) nxge_fzc_sys_err_mask_set(nxgep, SYS_ERR_SMX_MASK |
315352ccf843Smisaki SYS_ERR_IPP_MASK | SYS_ERR_TXC_MASK |
315452ccf843Smisaki SYS_ERR_ZCP_MASK);
315544961713Sgirish
3156d7cf53fcSmisaki Miyashita ldvp->use_timer = B_TRUE;
3157d7cf53fcSmisaki Miyashita ldvp->ldv = (uint8_t)ldv;
3158d7cf53fcSmisaki Miyashita ldvp->is_syserr = B_TRUE;
3159d7cf53fcSmisaki Miyashita ldvp->ldv_intr_handler = nxge_syserr_intr;
3160d7cf53fcSmisaki Miyashita ldvp->ldv_ldf_masks = 0;
3161d7cf53fcSmisaki Miyashita ldvp->nxgep = nxgep;
3162d7cf53fcSmisaki Miyashita ldgvp->ldvp_syserr = ldvp;
316344961713Sgirish
3164d7cf53fcSmisaki Miyashita NXGE_DEBUG_MSG((nxgep, INT_CTL,
3165d7cf53fcSmisaki Miyashita "==> nxge_ldgv_init_n2(syserr): maxldvs %d ldv %d "
3166d7cf53fcSmisaki Miyashita "ldg %d ldgptr $%p ldvptr p%p",
3167d7cf53fcSmisaki Miyashita maxldvs, ldv, ldgp->ldg, ldgp, ldvp));
3168d7cf53fcSmisaki Miyashita nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
3169d7cf53fcSmisaki Miyashita nldvs++;
317044961713Sgirish } else {
3171d7cf53fcSmisaki Miyashita /*
3172da14cebeSEric Cheng * SW based: allocate the ldv for the syserr since the vector
3173da14cebeSEric Cheng * should not be consumed for port1
3174d7cf53fcSmisaki Miyashita */
3175d7cf53fcSmisaki Miyashita sysldvp = KMEM_ZALLOC(sizeof (nxge_ldv_t), KM_SLEEP);
3176d7cf53fcSmisaki Miyashita sysldvp->use_timer = B_TRUE;
3177d7cf53fcSmisaki Miyashita sysldvp->ldv = NXGE_SYS_ERROR_LD;
3178d7cf53fcSmisaki Miyashita sysldvp->is_syserr = B_TRUE;
3179d7cf53fcSmisaki Miyashita sysldvp->ldv_intr_handler = nxge_syserr_intr;
3180d7cf53fcSmisaki Miyashita sysldvp->ldv_ldf_masks = 0;
3181d7cf53fcSmisaki Miyashita sysldvp->nxgep = nxgep;
3182d7cf53fcSmisaki Miyashita ldgvp->ldvp_syserr = sysldvp;
3183da14cebeSEric Cheng ldgvp->ldvp_syserr_alloced = B_TRUE;
318444961713Sgirish }
318544961713Sgirish
3186da14cebeSEric Cheng
318744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: "
318852ccf843Smisaki "(before rx) func %d nldvs %d navail %d nrequired %d",
318952ccf843Smisaki func, nldvs, *navail_p, *nrequired_p));
319044961713Sgirish
319144961713Sgirish /*
319244961713Sgirish * Start with RDC to configure logical devices for each group.
319344961713Sgirish */
3194678453a8Sspeer chn_start = p_cfgp->ldg_chn_start;
3195678453a8Sspeer set = &nxgep->rx_set;
3196678453a8Sspeer for (channel = 0; channel < NXGE_MAX_RDCS; channel++) {
3197678453a8Sspeer if ((1 << channel) & set->owned.map) {
3198678453a8Sspeer ldvp->is_rxdma = B_TRUE;
3199678453a8Sspeer ldvp->ldv = (uint8_t)channel + NXGE_RDMA_LD_START;
3200678453a8Sspeer ldvp->channel = channel;
3201678453a8Sspeer ldvp->vdma_index = (uint8_t)channel;
3202678453a8Sspeer ldvp->ldv_intr_handler = nxge_rx_intr;
3203678453a8Sspeer ldvp->ldv_ldf_masks = 0;
3204678453a8Sspeer ldvp->nxgep = nxgep;
3205678453a8Sspeer ldgp->ldg = p_cfgp->ldg[chn_start];
3206678453a8Sspeer
3207678453a8Sspeer NXGE_DEBUG_MSG((nxgep, INT_CTL,
3208678453a8Sspeer "==> nxge_ldgv_init_n2(rx%d): maxldvs %d ldv %d "
3209678453a8Sspeer "ldg %d ldgptr 0x%016llx ldvptr 0x%016llx",
3210678453a8Sspeer i, maxldvs, ldv, ldgp->ldg, ldgp, ldvp));
3211678453a8Sspeer nxge_ldgv_setup(&ldgp, &ldvp, ldvp->ldv,
3212678453a8Sspeer endldg, nrequired_p);
3213678453a8Sspeer nldvs++;
3214678453a8Sspeer chn_start++;
3215678453a8Sspeer }
321644961713Sgirish }
321744961713Sgirish
321844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: "
321952ccf843Smisaki "func %d nldvs %d navail %d nrequired %d",
322052ccf843Smisaki func, nldvs, *navail_p, *nrequired_p));
322144961713Sgirish
322244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: "
322352ccf843Smisaki "func %d nldvs %d navail %d nrequired %d ldgp 0x%llx "
322452ccf843Smisaki "ldvp 0x%llx",
322552ccf843Smisaki func, nldvs, *navail_p, *nrequired_p, ldgp, ldvp));
322644961713Sgirish /*
322744961713Sgirish * Transmit DMA channels.
322844961713Sgirish */
3229678453a8Sspeer chn_start = p_cfgp->ldg_chn_start + 8;
3230678453a8Sspeer set = &nxgep->tx_set;
3231678453a8Sspeer for (channel = 0; channel < NXGE_MAX_TDCS; channel++) {
3232678453a8Sspeer if ((1 << channel) & set->owned.map) {
3233678453a8Sspeer ldvp->is_txdma = B_TRUE;
3234678453a8Sspeer ldvp->ldv = (uint8_t)channel + NXGE_TDMA_LD_START;
3235678453a8Sspeer ldvp->channel = channel;
3236678453a8Sspeer ldvp->vdma_index = (uint8_t)channel;
3237678453a8Sspeer ldvp->ldv_intr_handler = nxge_tx_intr;
3238678453a8Sspeer ldvp->ldv_ldf_masks = 0;
3239678453a8Sspeer ldgp->ldg = p_cfgp->ldg[chn_start];
3240678453a8Sspeer ldvp->nxgep = nxgep;
3241678453a8Sspeer NXGE_DEBUG_MSG((nxgep, INT_CTL,
3242678453a8Sspeer "==> nxge_ldgv_init_n2(tx%d): maxldvs %d ldv %d "
3243678453a8Sspeer "ldg %d ldgptr %p ldvptr %p",
3244678453a8Sspeer channel, maxldvs, ldv, ldgp->ldg, ldgp, ldvp));
3245678453a8Sspeer nxge_ldgv_setup(&ldgp, &ldvp, ldvp->ldv,
3246678453a8Sspeer endldg, nrequired_p);
3247678453a8Sspeer nldvs++;
3248678453a8Sspeer chn_start++;
3249678453a8Sspeer }
325044961713Sgirish }
325144961713Sgirish
325244961713Sgirish ldgvp->ldg_intrs = *nrequired_p;
325344961713Sgirish ldgvp->nldvs = (uint8_t)nldvs;
325444961713Sgirish
325544961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: "
325652ccf843Smisaki "func %d nldvs %d maxgrps %d navail %d nrequired %d",
325752ccf843Smisaki func, nldvs, maxldgs, *navail_p, *nrequired_p));
325844961713Sgirish
325944961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_init_n2"));
326044961713Sgirish return (status);
326144961713Sgirish }
326244961713Sgirish
326344961713Sgirish /*
326444961713Sgirish * Interrupts related interface functions.
326544961713Sgirish */
3266a3c5bd6dSspeer
326744961713Sgirish nxge_status_t
nxge_ldgv_init(p_nxge_t nxgep,int * navail_p,int * nrequired_p)326844961713Sgirish nxge_ldgv_init(p_nxge_t nxgep, int *navail_p, int *nrequired_p)
326944961713Sgirish {
3270678453a8Sspeer int i, maxldvs, maxldgs, nldvs;
3271a3c5bd6dSspeer int ldv, ldg, endldg, ngrps;
3272a3c5bd6dSspeer uint8_t func;
3273a3c5bd6dSspeer uint8_t channel;
3274a3c5bd6dSspeer boolean_t own_sys_err = B_FALSE, own_fzc = B_FALSE;
3275a3c5bd6dSspeer p_nxge_dma_pt_cfg_t p_dma_cfgp;
3276a3c5bd6dSspeer p_nxge_hw_pt_cfg_t p_cfgp;
3277a3c5bd6dSspeer p_nxge_ldgv_t ldgvp;
3278a3c5bd6dSspeer p_nxge_ldg_t ldgp, ptr;
3279a3c5bd6dSspeer p_nxge_ldv_t ldvp;
3280678453a8Sspeer nxge_grp_set_t *set;
3281678453a8Sspeer
3282a3c5bd6dSspeer nxge_status_t status = NXGE_OK;
328344961713Sgirish
328444961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init"));
328544961713Sgirish if (!*navail_p) {
328644961713Sgirish *nrequired_p = 0;
328744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
328852ccf843Smisaki "<== nxge_ldgv_init:no avail"));
328944961713Sgirish return (NXGE_ERROR);
329044961713Sgirish }
329144961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
329244961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
329344961713Sgirish
3294678453a8Sspeer nldvs = p_cfgp->tdc.owned + p_cfgp->max_rdcs;
329544961713Sgirish
329644961713Sgirish /*
3297a3c5bd6dSspeer * If function zero instance, it needs to handle the system error
3298a3c5bd6dSspeer * interrupts.
329944961713Sgirish */
330044961713Sgirish func = nxgep->function_num;
330144961713Sgirish if (func == 0) {
330244961713Sgirish nldvs++;
330344961713Sgirish own_sys_err = B_TRUE;
330444961713Sgirish } else {
330544961713Sgirish /* use timer */
330644961713Sgirish nldvs++;
330744961713Sgirish }
330844961713Sgirish
330944961713Sgirish /*
331044961713Sgirish * Assume single partition, each function owns mac.
331144961713Sgirish */
331244961713Sgirish if (!nxge_use_partition) {
331344961713Sgirish /* mac */
331444961713Sgirish nldvs++;
331544961713Sgirish /* MIF */
331644961713Sgirish nldvs++;
331744961713Sgirish own_fzc = B_TRUE;
331844961713Sgirish }
331944961713Sgirish maxldvs = nldvs;
332044961713Sgirish maxldgs = p_cfgp->max_ldgs;
332144961713Sgirish if (!maxldvs || !maxldgs) {
332244961713Sgirish /* No devices configured. */
332344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_init: "
332452ccf843Smisaki "no logical devices or groups configured."));
332544961713Sgirish return (NXGE_ERROR);
332644961713Sgirish }
332744961713Sgirish ldgvp = nxgep->ldgvp;
332844961713Sgirish if (ldgvp == NULL) {
332944961713Sgirish ldgvp = KMEM_ZALLOC(sizeof (nxge_ldgv_t), KM_SLEEP);
333044961713Sgirish nxgep->ldgvp = ldgvp;
333144961713Sgirish ldgvp->maxldgs = (uint8_t)maxldgs;
333244961713Sgirish ldgvp->maxldvs = (uint8_t)maxldvs;
333344961713Sgirish ldgp = ldgvp->ldgp = KMEM_ZALLOC(sizeof (nxge_ldg_t) * maxldgs,
333452ccf843Smisaki KM_SLEEP);
333544961713Sgirish ldvp = ldgvp->ldvp = KMEM_ZALLOC(sizeof (nxge_ldv_t) * maxldvs,
333652ccf843Smisaki KM_SLEEP);
333744961713Sgirish }
3338678453a8Sspeer ldgvp->ndma_ldvs = p_cfgp->tdc.owned + p_cfgp->max_rdcs;
333944961713Sgirish ldgvp->tmres = NXGE_TIMER_RESO;
334044961713Sgirish
334144961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL,
334252ccf843Smisaki "==> nxge_ldgv_init: maxldvs %d maxldgs %d nldvs %d",
334352ccf843Smisaki maxldvs, maxldgs, nldvs));
334444961713Sgirish ldg = p_cfgp->start_ldg;
334544961713Sgirish ptr = ldgp;
334644961713Sgirish for (i = 0; i < maxldgs; i++) {
334744961713Sgirish ptr->func = func;
334844961713Sgirish ptr->arm = B_TRUE;
334944961713Sgirish ptr->vldg_index = (uint8_t)i;
335044961713Sgirish ptr->ldg_timer = NXGE_TIMER_LDG;
335144961713Sgirish ptr->ldg = ldg++;
335244961713Sgirish ptr->sys_intr_handler = nxge_intr;
335344961713Sgirish ptr->nldvs = 0;
335444961713Sgirish ptr->nxgep = nxgep;
335544961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL,
335652ccf843Smisaki "==> nxge_ldgv_init: maxldvs %d maxldgs %d ldg %d",
335752ccf843Smisaki maxldvs, maxldgs, ptr->ldg));
335844961713Sgirish ptr++;
335944961713Sgirish }
336044961713Sgirish
336144961713Sgirish ldg = p_cfgp->start_ldg;
336244961713Sgirish if (maxldgs > *navail_p) {
336344961713Sgirish ngrps = *navail_p;
336444961713Sgirish } else {
336544961713Sgirish ngrps = maxldgs;
336644961713Sgirish }
336744961713Sgirish endldg = ldg + ngrps;
336844961713Sgirish
336944961713Sgirish /*
337044961713Sgirish * Receive DMA channels.
337144961713Sgirish */
337244961713Sgirish nldvs = 0;
337344961713Sgirish ldgvp->nldvs = 0;
337444961713Sgirish ldgp->ldvp = NULL;
337544961713Sgirish *nrequired_p = 0;
337644961713Sgirish
337744961713Sgirish /*
337844961713Sgirish * Start with RDC to configure logical devices for each group.
337944961713Sgirish */
3380678453a8Sspeer set = &nxgep->rx_set;
3381678453a8Sspeer for (channel = 0; channel < NXGE_MAX_RDCS; channel++) {
3382678453a8Sspeer if ((1 << channel) & set->owned.map) {
3383678453a8Sspeer /* For now, <channel & <vdma_index> are the same. */
3384678453a8Sspeer ldvp->is_rxdma = B_TRUE;
3385678453a8Sspeer ldvp->ldv = (uint8_t)channel + NXGE_RDMA_LD_START;
3386678453a8Sspeer ldvp->channel = channel;
3387678453a8Sspeer ldvp->vdma_index = (uint8_t)channel;
3388678453a8Sspeer ldvp->ldv_intr_handler = nxge_rx_intr;
3389678453a8Sspeer ldvp->ldv_ldf_masks = 0;
3390678453a8Sspeer ldvp->use_timer = B_FALSE;
3391678453a8Sspeer ldvp->nxgep = nxgep;
3392678453a8Sspeer nxge_ldgv_setup(&ldgp, &ldvp, ldvp->ldv,
3393678453a8Sspeer endldg, nrequired_p);
3394678453a8Sspeer nldvs++;
3395678453a8Sspeer }
339644961713Sgirish }
3397a3c5bd6dSspeer
339844961713Sgirish /*
339944961713Sgirish * Transmit DMA channels.
340044961713Sgirish */
3401678453a8Sspeer set = &nxgep->tx_set;
3402678453a8Sspeer for (channel = 0; channel < NXGE_MAX_TDCS; channel++) {
3403678453a8Sspeer if ((1 << channel) & set->owned.map) {
3404678453a8Sspeer /* For now, <channel & <vdma_index> are the same. */
3405678453a8Sspeer ldvp->is_txdma = B_TRUE;
3406678453a8Sspeer ldvp->ldv = (uint8_t)channel + NXGE_TDMA_LD_START;
3407678453a8Sspeer ldvp->channel = channel;
3408678453a8Sspeer ldvp->vdma_index = (uint8_t)channel;
3409678453a8Sspeer ldvp->ldv_intr_handler = nxge_tx_intr;
3410678453a8Sspeer ldvp->ldv_ldf_masks = 0;
3411678453a8Sspeer ldvp->use_timer = B_FALSE;
3412678453a8Sspeer ldvp->nxgep = nxgep;
3413678453a8Sspeer nxge_ldgv_setup(&ldgp, &ldvp, ldvp->ldv,
3414678453a8Sspeer endldg, nrequired_p);
3415678453a8Sspeer nldvs++;
3416678453a8Sspeer }
341744961713Sgirish }
341844961713Sgirish
341944961713Sgirish if (own_fzc) {
342044961713Sgirish ldv = NXGE_MIF_LD;
342144961713Sgirish ldvp->ldv = (uint8_t)ldv;
342244961713Sgirish ldvp->is_mif = B_TRUE;
342344961713Sgirish ldvp->ldv_intr_handler = nxge_mif_intr;
342444961713Sgirish ldvp->ldv_ldf_masks = 0;
342544961713Sgirish ldvp->use_timer = B_FALSE;
342644961713Sgirish ldvp->nxgep = nxgep;
342744961713Sgirish nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
342844961713Sgirish nldvs++;
342944961713Sgirish }
343044961713Sgirish /*
343144961713Sgirish * MAC port (function zero control)
343244961713Sgirish */
343344961713Sgirish if (own_fzc) {
343444961713Sgirish ldvp->is_mac = B_TRUE;
343544961713Sgirish ldvp->ldv_intr_handler = nxge_mac_intr;
343644961713Sgirish ldvp->ldv_ldf_masks = 0;
343744961713Sgirish ldv = func + NXGE_MAC_LD_START;
343844961713Sgirish ldvp->ldv = (uint8_t)ldv;
343944961713Sgirish ldvp->use_timer = B_FALSE;
344044961713Sgirish ldvp->nxgep = nxgep;
344144961713Sgirish nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
344244961713Sgirish nldvs++;
344344961713Sgirish }
344444961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init: "
344552ccf843Smisaki "func %d nldvs %d navail %d nrequired %d",
344652ccf843Smisaki func, nldvs, *navail_p, *nrequired_p));
344744961713Sgirish /*
344844961713Sgirish * Function 0 owns system error interrupts.
344944961713Sgirish */
345014ea4bb7Ssd ldvp->use_timer = B_TRUE;
345144961713Sgirish if (own_sys_err) {
345244961713Sgirish ldv = NXGE_SYS_ERROR_LD;
345344961713Sgirish ldvp->ldv = (uint8_t)ldv;
345444961713Sgirish ldvp->is_syserr = B_TRUE;
345544961713Sgirish ldvp->ldv_intr_handler = nxge_syserr_intr;
345644961713Sgirish ldvp->ldv_ldf_masks = 0;
345744961713Sgirish ldvp->nxgep = nxgep;
345844961713Sgirish ldgvp->ldvp_syserr = ldvp;
345944961713Sgirish /*
346044961713Sgirish * Unmask the system interrupt states.
346144961713Sgirish */
346244961713Sgirish (void) nxge_fzc_sys_err_mask_set(nxgep, SYS_ERR_SMX_MASK |
346352ccf843Smisaki SYS_ERR_IPP_MASK | SYS_ERR_TXC_MASK |
346452ccf843Smisaki SYS_ERR_ZCP_MASK);
346544961713Sgirish
346644961713Sgirish (void) nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
346744961713Sgirish nldvs++;
346844961713Sgirish } else {
346944961713Sgirish ldv = NXGE_SYS_ERROR_LD;
347044961713Sgirish ldvp->ldv = (uint8_t)ldv;
347144961713Sgirish ldvp->is_syserr = B_TRUE;
347244961713Sgirish ldvp->ldv_intr_handler = nxge_syserr_intr;
347344961713Sgirish ldvp->nxgep = nxgep;
347444961713Sgirish ldvp->ldv_ldf_masks = 0;
347544961713Sgirish ldgvp->ldvp_syserr = ldvp;
347644961713Sgirish }
347744961713Sgirish
347844961713Sgirish ldgvp->ldg_intrs = *nrequired_p;
347944961713Sgirish
348044961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init: "
348152ccf843Smisaki "func %d nldvs %d navail %d nrequired %d",
348252ccf843Smisaki func, nldvs, *navail_p, *nrequired_p));
348344961713Sgirish
348444961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_init"));
348544961713Sgirish return (status);
348644961713Sgirish }
348744961713Sgirish
348844961713Sgirish nxge_status_t
nxge_ldgv_uninit(p_nxge_t nxgep)348944961713Sgirish nxge_ldgv_uninit(p_nxge_t nxgep)
349044961713Sgirish {
3491a3c5bd6dSspeer p_nxge_ldgv_t ldgvp;
349244961713Sgirish
349344961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_uninit"));
349444961713Sgirish ldgvp = nxgep->ldgvp;
349544961713Sgirish if (ldgvp == NULL) {
349644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_uninit: "
349752ccf843Smisaki "no logical group configured."));
349844961713Sgirish return (NXGE_OK);
349944961713Sgirish }
3500da14cebeSEric Cheng if (ldgvp->ldvp_syserr_alloced == B_TRUE) {
3501d7cf53fcSmisaki Miyashita KMEM_FREE(ldgvp->ldvp_syserr, sizeof (nxge_ldv_t));
3502d7cf53fcSmisaki Miyashita }
350344961713Sgirish if (ldgvp->ldgp) {
350444961713Sgirish KMEM_FREE(ldgvp->ldgp, sizeof (nxge_ldg_t) * ldgvp->maxldgs);
350544961713Sgirish }
350644961713Sgirish if (ldgvp->ldvp) {
350744961713Sgirish KMEM_FREE(ldgvp->ldvp, sizeof (nxge_ldv_t) * ldgvp->maxldvs);
350844961713Sgirish }
350944961713Sgirish KMEM_FREE(ldgvp, sizeof (nxge_ldgv_t));
351044961713Sgirish nxgep->ldgvp = NULL;
351144961713Sgirish
351244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_uninit"));
351344961713Sgirish return (NXGE_OK);
351444961713Sgirish }
351544961713Sgirish
351644961713Sgirish nxge_status_t
nxge_intr_ldgv_init(p_nxge_t nxgep)351744961713Sgirish nxge_intr_ldgv_init(p_nxge_t nxgep)
351844961713Sgirish {
3519a3c5bd6dSspeer nxge_status_t status = NXGE_OK;
352044961713Sgirish
352144961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_ldgv_init"));
352244961713Sgirish /*
3523a3c5bd6dSspeer * Configure the logical device group numbers, state vectors and
3524a3c5bd6dSspeer * interrupt masks for each logical device.
352544961713Sgirish */
352644961713Sgirish status = nxge_fzc_intr_init(nxgep);
352744961713Sgirish
352844961713Sgirish /*
352944961713Sgirish * Configure logical device masks and timers.
353044961713Sgirish */
353144961713Sgirish status = nxge_intr_mask_mgmt(nxgep);
353244961713Sgirish
353344961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_ldgv_init"));
353444961713Sgirish return (status);
353544961713Sgirish }
353644961713Sgirish
353744961713Sgirish nxge_status_t
nxge_intr_mask_mgmt(p_nxge_t nxgep)353844961713Sgirish nxge_intr_mask_mgmt(p_nxge_t nxgep)
353944961713Sgirish {
3540a3c5bd6dSspeer p_nxge_ldgv_t ldgvp;
3541a3c5bd6dSspeer p_nxge_ldg_t ldgp;
3542a3c5bd6dSspeer p_nxge_ldv_t ldvp;
3543a3c5bd6dSspeer npi_handle_t handle;
3544a3c5bd6dSspeer int i, j;
3545a3c5bd6dSspeer npi_status_t rs = NPI_SUCCESS;
354644961713Sgirish
354744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_mask_mgmt"));
354844961713Sgirish
354944961713Sgirish if ((ldgvp = nxgep->ldgvp) == NULL) {
355044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
355152ccf843Smisaki "<== nxge_intr_mask_mgmt: Null ldgvp"));
355244961713Sgirish return (NXGE_ERROR);
355344961713Sgirish }
355444961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep);
355544961713Sgirish ldgp = ldgvp->ldgp;
355644961713Sgirish ldvp = ldgvp->ldvp;
355744961713Sgirish if (ldgp == NULL || ldvp == NULL) {
355844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
355952ccf843Smisaki "<== nxge_intr_mask_mgmt: Null ldgp or ldvp"));
356044961713Sgirish return (NXGE_ERROR);
356144961713Sgirish }
356244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL,
356352ccf843Smisaki "==> nxge_intr_mask_mgmt: # of intrs %d ", ldgvp->ldg_intrs));
356444961713Sgirish /* Initialize masks. */
356544961713Sgirish if (nxgep->niu_type != N2_NIU) {
356644961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL,
356752ccf843Smisaki "==> nxge_intr_mask_mgmt(Neptune): # intrs %d ",
356852ccf843Smisaki ldgvp->ldg_intrs));
356944961713Sgirish for (i = 0; i < ldgvp->ldg_intrs; i++, ldgp++) {
357044961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL,
357152ccf843Smisaki "==> nxge_intr_mask_mgmt(Neptune): # ldv %d "
357252ccf843Smisaki "in group %d", ldgp->nldvs, ldgp->ldg));
357344961713Sgirish for (j = 0; j < ldgp->nldvs; j++, ldvp++) {
357444961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL,
357552ccf843Smisaki "==> nxge_intr_mask_mgmt: set ldv # %d "
357652ccf843Smisaki "for ldg %d", ldvp->ldv, ldgp->ldg));
357744961713Sgirish rs = npi_intr_mask_set(handle, ldvp->ldv,
357852ccf843Smisaki ldvp->ldv_ldf_masks);
357944961713Sgirish if (rs != NPI_SUCCESS) {
358044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
358152ccf843Smisaki "<== nxge_intr_mask_mgmt: "
358252ccf843Smisaki "set mask failed "
358352ccf843Smisaki " rs 0x%x ldv %d mask 0x%x",
358452ccf843Smisaki rs, ldvp->ldv,
358552ccf843Smisaki ldvp->ldv_ldf_masks));
358644961713Sgirish return (NXGE_ERROR | rs);
358744961713Sgirish }
358844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL,
358952ccf843Smisaki "==> nxge_intr_mask_mgmt: "
359052ccf843Smisaki "set mask OK "
359152ccf843Smisaki " rs 0x%x ldv %d mask 0x%x",
359252ccf843Smisaki rs, ldvp->ldv,
359352ccf843Smisaki ldvp->ldv_ldf_masks));
359444961713Sgirish }
359544961713Sgirish }
359644961713Sgirish }
359744961713Sgirish ldgp = ldgvp->ldgp;
359844961713Sgirish /* Configure timer and arm bit */
359944961713Sgirish for (i = 0; i < nxgep->ldgvp->ldg_intrs; i++, ldgp++) {
360044961713Sgirish rs = npi_intr_ldg_mgmt_set(handle, ldgp->ldg,
360152ccf843Smisaki ldgp->arm, ldgp->ldg_timer);
360244961713Sgirish if (rs != NPI_SUCCESS) {
360344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
360452ccf843Smisaki "<== nxge_intr_mask_mgmt: "
360552ccf843Smisaki "set timer failed "
360652ccf843Smisaki " rs 0x%x dg %d timer 0x%x",
360752ccf843Smisaki rs, ldgp->ldg, ldgp->ldg_timer));
360844961713Sgirish return (NXGE_ERROR | rs);
360944961713Sgirish }
361044961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL,
361152ccf843Smisaki "==> nxge_intr_mask_mgmt: "
361252ccf843Smisaki "set timer OK "
361352ccf843Smisaki " rs 0x%x ldg %d timer 0x%x",
361452ccf843Smisaki rs, ldgp->ldg, ldgp->ldg_timer));
361544961713Sgirish }
361644961713Sgirish
361744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_fzc_intr_mask_mgmt"));
361844961713Sgirish return (NXGE_OK);
361944961713Sgirish }
362044961713Sgirish
362144961713Sgirish nxge_status_t
nxge_intr_mask_mgmt_set(p_nxge_t nxgep,boolean_t on)362244961713Sgirish nxge_intr_mask_mgmt_set(p_nxge_t nxgep, boolean_t on)
362344961713Sgirish {
3624a3c5bd6dSspeer p_nxge_ldgv_t ldgvp;
3625a3c5bd6dSspeer p_nxge_ldg_t ldgp;
3626a3c5bd6dSspeer p_nxge_ldv_t ldvp;
3627a3c5bd6dSspeer npi_handle_t handle;
3628a3c5bd6dSspeer int i, j;
3629a3c5bd6dSspeer npi_status_t rs = NPI_SUCCESS;
363044961713Sgirish
363144961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL,
363252ccf843Smisaki "==> nxge_intr_mask_mgmt_set (%d)", on));
363344961713Sgirish
363444961713Sgirish if (nxgep->niu_type == N2_NIU) {
363544961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL,
363652ccf843Smisaki "<== nxge_intr_mask_mgmt_set (%d) not set (N2/NIU)",
363752ccf843Smisaki on));
363844961713Sgirish return (NXGE_ERROR);
363944961713Sgirish }
3640a3c5bd6dSspeer
364144961713Sgirish if ((ldgvp = nxgep->ldgvp) == NULL) {
364244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
364352ccf843Smisaki "==> nxge_intr_mask_mgmt_set: Null ldgvp"));
364444961713Sgirish return (NXGE_ERROR);
364544961713Sgirish }
3646a3c5bd6dSspeer
364744961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep);
364844961713Sgirish ldgp = ldgvp->ldgp;
364944961713Sgirish ldvp = ldgvp->ldvp;
365044961713Sgirish if (ldgp == NULL || ldvp == NULL) {
365144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
365252ccf843Smisaki "<== nxge_intr_mask_mgmt_set: Null ldgp or ldvp"));
365344961713Sgirish return (NXGE_ERROR);
365444961713Sgirish }
365544961713Sgirish /* set masks. */
365644961713Sgirish for (i = 0; i < ldgvp->ldg_intrs; i++, ldgp++) {
365744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL,
365852ccf843Smisaki "==> nxge_intr_mask_mgmt_set: flag %d ldg %d"
365952ccf843Smisaki "set mask nldvs %d", on, ldgp->ldg, ldgp->nldvs));
366044961713Sgirish for (j = 0; j < ldgp->nldvs; j++, ldvp++) {
366144961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL,
366252ccf843Smisaki "==> nxge_intr_mask_mgmt_set: "
366352ccf843Smisaki "for %d %d flag %d", i, j, on));
366444961713Sgirish if (on) {
366544961713Sgirish ldvp->ldv_ldf_masks = 0;
366644961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL,
366752ccf843Smisaki "==> nxge_intr_mask_mgmt_set: "
366852ccf843Smisaki "ON mask off"));
366944961713Sgirish } else if (!on) {
367044961713Sgirish ldvp->ldv_ldf_masks = (uint8_t)LD_IM1_MASK;
367144961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL,
367252ccf843Smisaki "==> nxge_intr_mask_mgmt_set:mask on"));
367344961713Sgirish }
367444961713Sgirish rs = npi_intr_mask_set(handle, ldvp->ldv,
367552ccf843Smisaki ldvp->ldv_ldf_masks);
367644961713Sgirish if (rs != NPI_SUCCESS) {
367744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
367852ccf843Smisaki "==> nxge_intr_mask_mgmt_set: "
367952ccf843Smisaki "set mask failed "
368052ccf843Smisaki " rs 0x%x ldv %d mask 0x%x",
368152ccf843Smisaki rs, ldvp->ldv, ldvp->ldv_ldf_masks));
368244961713Sgirish return (NXGE_ERROR | rs);
368344961713Sgirish }
368444961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL,
368552ccf843Smisaki "==> nxge_intr_mask_mgmt_set: flag %d"
368652ccf843Smisaki "set mask OK "
368752ccf843Smisaki " ldv %d mask 0x%x",
368852ccf843Smisaki on, ldvp->ldv, ldvp->ldv_ldf_masks));
368944961713Sgirish }
369044961713Sgirish }
369144961713Sgirish
369244961713Sgirish ldgp = ldgvp->ldgp;
369344961713Sgirish /* set the arm bit */
369444961713Sgirish for (i = 0; i < nxgep->ldgvp->ldg_intrs; i++, ldgp++) {
369544961713Sgirish if (on && !ldgp->arm) {
369644961713Sgirish ldgp->arm = B_TRUE;
369744961713Sgirish } else if (!on && ldgp->arm) {
369844961713Sgirish ldgp->arm = B_FALSE;
369944961713Sgirish }
370044961713Sgirish rs = npi_intr_ldg_mgmt_set(handle, ldgp->ldg,
370152ccf843Smisaki ldgp->arm, ldgp->ldg_timer);
370244961713Sgirish if (rs != NPI_SUCCESS) {
370344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
370452ccf843Smisaki "<== nxge_intr_mask_mgmt_set: "
370552ccf843Smisaki "set timer failed "
370652ccf843Smisaki " rs 0x%x ldg %d timer 0x%x",
370752ccf843Smisaki rs, ldgp->ldg, ldgp->ldg_timer));
370844961713Sgirish return (NXGE_ERROR | rs);
370944961713Sgirish }
371044961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL,
371152ccf843Smisaki "==> nxge_intr_mask_mgmt_set: OK (flag %d) "
371252ccf843Smisaki "set timer "
371352ccf843Smisaki " ldg %d timer 0x%x",
371452ccf843Smisaki on, ldgp->ldg, ldgp->ldg_timer));
371544961713Sgirish }
371644961713Sgirish
371744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_mask_mgmt_set"));
371844961713Sgirish return (NXGE_OK);
371944961713Sgirish }
372044961713Sgirish
372114ea4bb7Ssd static nxge_status_t
nxge_get_mac_addr_properties(p_nxge_t nxgep)372244961713Sgirish nxge_get_mac_addr_properties(p_nxge_t nxgep)
372344961713Sgirish {
372459ac0c16Sdavemq #if defined(_BIG_ENDIAN)
3725a3c5bd6dSspeer uchar_t *prop_val;
3726a3c5bd6dSspeer uint_t prop_len;
372759ac0c16Sdavemq uint_t j;
372859ac0c16Sdavemq #endif
3729a3c5bd6dSspeer uint_t i;
3730a3c5bd6dSspeer uint8_t func_num;
373159ac0c16Sdavemq boolean_t compute_macs = B_TRUE;
373244961713Sgirish
373344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_get_mac_addr_properties "));
373444961713Sgirish
373544961713Sgirish #if defined(_BIG_ENDIAN)
373644961713Sgirish /*
373744961713Sgirish * Get the ethernet address.
373844961713Sgirish */
373944961713Sgirish (void) localetheraddr((struct ether_addr *)NULL, &nxgep->ouraddr);
374044961713Sgirish
374144961713Sgirish /*
3742a3c5bd6dSspeer * Check if it is an adapter with its own local mac address If it is
3743a3c5bd6dSspeer * present, override the system mac address.
374444961713Sgirish */
374544961713Sgirish if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
374652ccf843Smisaki "local-mac-address", &prop_val,
374752ccf843Smisaki &prop_len) == DDI_PROP_SUCCESS) {
374844961713Sgirish if (prop_len == ETHERADDRL) {
374944961713Sgirish nxgep->factaddr = *(p_ether_addr_t)prop_val;
375044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Local mac address = "
375152ccf843Smisaki "%02x:%02x:%02x:%02x:%02x:%02x",
375252ccf843Smisaki prop_val[0], prop_val[1], prop_val[2],
375352ccf843Smisaki prop_val[3], prop_val[4], prop_val[5]));
375444961713Sgirish }
375544961713Sgirish ddi_prop_free(prop_val);
375644961713Sgirish }
375744961713Sgirish if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
375852ccf843Smisaki "local-mac-address?", &prop_val,
375952ccf843Smisaki &prop_len) == DDI_PROP_SUCCESS) {
3760a3c5bd6dSspeer if (strncmp("true", (caddr_t)prop_val, (size_t)prop_len) == 0) {
376144961713Sgirish nxgep->ouraddr = nxgep->factaddr;
376244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL,
376352ccf843Smisaki "Using local MAC address"));
376444961713Sgirish }
376544961713Sgirish ddi_prop_free(prop_val);
376644961713Sgirish } else {
376744961713Sgirish nxgep->ouraddr = nxgep->factaddr;
376844961713Sgirish }
376956d930aeSspeer
37702e59129aSraghus if ((!nxgep->vpd_info.present) ||
377159ac0c16Sdavemq (nxge_is_valid_local_mac(nxgep->factaddr)))
377256d930aeSspeer goto got_mac_addr;
377356d930aeSspeer
377456d930aeSspeer NXGE_DEBUG_MSG((nxgep, DDI_CTL, "nxge_get_mac_addr_properties: "
377556d930aeSspeer "MAC address from properties is not valid...reading from PROM"));
377656d930aeSspeer
377744961713Sgirish #endif
377856d930aeSspeer if (!nxgep->vpd_info.ver_valid) {
377956d930aeSspeer (void) nxge_espc_mac_addrs_get(nxgep);
378056d930aeSspeer if (!nxge_is_valid_local_mac(nxgep->factaddr)) {
37812e59129aSraghus NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Failed to get "
37822e59129aSraghus "MAC address"));
378356d930aeSspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "EEPROM version "
378456d930aeSspeer "[%s] invalid...please update",
378556d930aeSspeer nxgep->vpd_info.ver));
378656d930aeSspeer return (NXGE_ERROR);
378756d930aeSspeer }
378856d930aeSspeer nxgep->ouraddr = nxgep->factaddr;
378956d930aeSspeer goto got_mac_addr;
379056d930aeSspeer }
379156d930aeSspeer /*
379256d930aeSspeer * First get the MAC address from the info in the VPD data read
379356d930aeSspeer * from the EEPROM.
379456d930aeSspeer */
379556d930aeSspeer nxge_espc_get_next_mac_addr(nxgep->vpd_info.mac_addr,
379659ac0c16Sdavemq nxgep->function_num, &nxgep->factaddr);
379756d930aeSspeer
379856d930aeSspeer if (!nxge_is_valid_local_mac(nxgep->factaddr)) {
379956d930aeSspeer NXGE_DEBUG_MSG((nxgep, DDI_CTL,
380056d930aeSspeer "nxge_get_mac_addr_properties: "
380156d930aeSspeer "MAC address in EEPROM VPD data not valid"
380256d930aeSspeer "...reading from NCR registers"));
380356d930aeSspeer (void) nxge_espc_mac_addrs_get(nxgep);
380456d930aeSspeer if (!nxge_is_valid_local_mac(nxgep->factaddr)) {
38052e59129aSraghus NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Failed to get "
38062e59129aSraghus "MAC address"));
380756d930aeSspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "EEPROM version "
380856d930aeSspeer "[%s] invalid...please update",
380956d930aeSspeer nxgep->vpd_info.ver));
381056d930aeSspeer return (NXGE_ERROR);
381156d930aeSspeer }
381256d930aeSspeer }
381344961713Sgirish
381456d930aeSspeer nxgep->ouraddr = nxgep->factaddr;
381556d930aeSspeer
381656d930aeSspeer got_mac_addr:
381744961713Sgirish func_num = nxgep->function_num;
381844961713Sgirish
381958324dfcSspeer /*
382059ac0c16Sdavemq * Note: mac-addresses property is the list of mac addresses for a
382159ac0c16Sdavemq * port. NXGE_MAX_MMAC_ADDRS is the total number of MAC addresses
382259ac0c16Sdavemq * allocated for a board.
382358324dfcSspeer */
382459ac0c16Sdavemq nxgep->nxge_mmac_info.total_factory_macs = NXGE_MAX_MMAC_ADDRS;
382544961713Sgirish
382659ac0c16Sdavemq #if defined(_BIG_ENDIAN)
382759ac0c16Sdavemq if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
382859ac0c16Sdavemq "mac-addresses", &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
382944961713Sgirish /*
383059ac0c16Sdavemq * XAUI may have up to 18 MACs, more than the XMAC can
383159ac0c16Sdavemq * use (1 unique MAC plus 16 alternate MACs)
383244961713Sgirish */
383359ac0c16Sdavemq nxgep->nxge_mmac_info.num_factory_mmac =
383459ac0c16Sdavemq prop_len / ETHERADDRL - 1;
383559ac0c16Sdavemq if (nxgep->nxge_mmac_info.num_factory_mmac >
383659ac0c16Sdavemq XMAC_MAX_ALT_ADDR_ENTRY) {
383756d930aeSspeer nxgep->nxge_mmac_info.num_factory_mmac =
383859ac0c16Sdavemq XMAC_MAX_ALT_ADDR_ENTRY;
383959ac0c16Sdavemq }
384059ac0c16Sdavemq
384159ac0c16Sdavemq for (i = 1; i <= nxgep->nxge_mmac_info.num_factory_mmac; i++) {
384259ac0c16Sdavemq for (j = 0; j < ETHERADDRL; j++) {
384359ac0c16Sdavemq nxgep->nxge_mmac_info.factory_mac_pool[i][j] =
384459ac0c16Sdavemq *(prop_val + (i * ETHERADDRL) + j);
384559ac0c16Sdavemq }
384659ac0c16Sdavemq NXGE_DEBUG_MSG((nxgep, DDI_CTL,
384759ac0c16Sdavemq "nxge_get_mac_addr_properties: Alt mac[%d] from "
384859ac0c16Sdavemq "mac-addresses property[%2x:%2x:%2x:%2x:%2x:%2x]",
384959ac0c16Sdavemq i, nxgep->nxge_mmac_info.factory_mac_pool[i][0],
385059ac0c16Sdavemq nxgep->nxge_mmac_info.factory_mac_pool[i][1],
385159ac0c16Sdavemq nxgep->nxge_mmac_info.factory_mac_pool[i][2],
385259ac0c16Sdavemq nxgep->nxge_mmac_info.factory_mac_pool[i][3],
385359ac0c16Sdavemq nxgep->nxge_mmac_info.factory_mac_pool[i][4],
385459ac0c16Sdavemq nxgep->nxge_mmac_info.factory_mac_pool[i][5]));
385556d930aeSspeer }
385659ac0c16Sdavemq
385759ac0c16Sdavemq compute_macs = B_FALSE;
385859ac0c16Sdavemq ddi_prop_free(prop_val);
385959ac0c16Sdavemq goto got_mmac_info;
386058324dfcSspeer }
386159ac0c16Sdavemq #endif
386259ac0c16Sdavemq /*
386359ac0c16Sdavemq * total_factory_macs = 32
386459ac0c16Sdavemq * num_factory_mmac = (32 >> (nports/2)) - 1
386559ac0c16Sdavemq * So if nports = 4, then num_factory_mmac = 7
386659ac0c16Sdavemq * if nports = 2, then num_factory_mmac = 15
386759ac0c16Sdavemq */
386859ac0c16Sdavemq nxgep->nxge_mmac_info.num_factory_mmac =
386959ac0c16Sdavemq ((nxgep->nxge_mmac_info.total_factory_macs >>
387059ac0c16Sdavemq (nxgep->nports >> 1))) - 1;
387156d930aeSspeer
387259ac0c16Sdavemq got_mmac_info:
387359ac0c16Sdavemq
387459ac0c16Sdavemq if ((nxgep->function_num < 2) &&
387559ac0c16Sdavemq (nxgep->nxge_mmac_info.num_factory_mmac >
387659ac0c16Sdavemq XMAC_MAX_ALT_ADDR_ENTRY)) {
387759ac0c16Sdavemq nxgep->nxge_mmac_info.num_factory_mmac =
387859ac0c16Sdavemq XMAC_MAX_ALT_ADDR_ENTRY;
387959ac0c16Sdavemq } else if ((nxgep->function_num > 1) &&
388059ac0c16Sdavemq (nxgep->nxge_mmac_info.num_factory_mmac >
388159ac0c16Sdavemq BMAC_MAX_ALT_ADDR_ENTRY)) {
388259ac0c16Sdavemq nxgep->nxge_mmac_info.num_factory_mmac =
388359ac0c16Sdavemq BMAC_MAX_ALT_ADDR_ENTRY;
388456d930aeSspeer }
388556d930aeSspeer
388658324dfcSspeer for (i = 0; i <= nxgep->nxge_mmac_info.num_mmac; i++) {
388744961713Sgirish (void) npi_mac_altaddr_disable(nxgep->npi_handle,
388852ccf843Smisaki NXGE_GET_PORT_NUM(func_num), i);
388944961713Sgirish }
389044961713Sgirish
389159ac0c16Sdavemq (void) nxge_init_mmac(nxgep, compute_macs);
389214ea4bb7Ssd return (NXGE_OK);
389344961713Sgirish }
389444961713Sgirish
389544961713Sgirish void
nxge_get_xcvr_properties(p_nxge_t nxgep)389644961713Sgirish nxge_get_xcvr_properties(p_nxge_t nxgep)
389744961713Sgirish {
3898a3c5bd6dSspeer uchar_t *prop_val;
3899a3c5bd6dSspeer uint_t prop_len;
390044961713Sgirish
390144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_get_xcvr_properties"));
390244961713Sgirish
390344961713Sgirish /*
390444961713Sgirish * Read the type of physical layer interface being used.
390544961713Sgirish */
390644961713Sgirish nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR;
390744961713Sgirish if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
390852ccf843Smisaki "phy-type", &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
3909a3c5bd6dSspeer if (strncmp("pcs", (caddr_t)prop_val,
391052ccf843Smisaki (size_t)prop_len) == 0) {
391144961713Sgirish nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR;
391244961713Sgirish } else {
391344961713Sgirish nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR;
391444961713Sgirish }
391544961713Sgirish ddi_prop_free(prop_val);
391644961713Sgirish } else if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
391752ccf843Smisaki "phy-interface", &prop_val,
391852ccf843Smisaki &prop_len) == DDI_PROP_SUCCESS) {
391944961713Sgirish if (strncmp("pcs", (caddr_t)prop_val, (size_t)prop_len) == 0) {
392044961713Sgirish nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR;
392144961713Sgirish } else {
392244961713Sgirish nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR;
392344961713Sgirish }
392444961713Sgirish ddi_prop_free(prop_val);
392544961713Sgirish }
392644961713Sgirish }
392744961713Sgirish
392844961713Sgirish /*
392944961713Sgirish * Static functions start here.
393044961713Sgirish */
3931a3c5bd6dSspeer
393244961713Sgirish static void
nxge_ldgv_setup(p_nxge_ldg_t * ldgp,p_nxge_ldv_t * ldvp,uint8_t ldv,uint8_t endldg,int * ngrps)393344961713Sgirish nxge_ldgv_setup(p_nxge_ldg_t *ldgp, p_nxge_ldv_t *ldvp, uint8_t ldv,
3934a3c5bd6dSspeer uint8_t endldg, int *ngrps)
393544961713Sgirish {
393644961713Sgirish NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup"));
393744961713Sgirish /* Assign the group number for each device. */
393844961713Sgirish (*ldvp)->ldg_assigned = (*ldgp)->ldg;
393944961713Sgirish (*ldvp)->ldgp = *ldgp;
394044961713Sgirish (*ldvp)->ldv = ldv;
394144961713Sgirish
394244961713Sgirish NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup: "
394352ccf843Smisaki "ldv %d endldg %d ldg %d, ldvp $%p",
394452ccf843Smisaki ldv, endldg, (*ldgp)->ldg, (*ldgp)->ldvp));
394544961713Sgirish
394644961713Sgirish (*ldgp)->nldvs++;
394744961713Sgirish if ((*ldgp)->ldg == (endldg - 1)) {
394844961713Sgirish if ((*ldgp)->ldvp == NULL) {
394944961713Sgirish (*ldgp)->ldvp = *ldvp;
395044961713Sgirish *ngrps += 1;
395144961713Sgirish NXGE_DEBUG_MSG((NULL, INT_CTL,
395252ccf843Smisaki "==> nxge_ldgv_setup: ngrps %d", *ngrps));
395344961713Sgirish }
395444961713Sgirish NXGE_DEBUG_MSG((NULL, INT_CTL,
395552ccf843Smisaki "==> nxge_ldgv_setup: ldvp $%p ngrps %d",
395652ccf843Smisaki *ldvp, *ngrps));
395744961713Sgirish ++*ldvp;
395844961713Sgirish } else {
395944961713Sgirish (*ldgp)->ldvp = *ldvp;
396044961713Sgirish *ngrps += 1;
396144961713Sgirish NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup(done): "
396252ccf843Smisaki "ldv %d endldg %d ldg %d, ldvp $%p",
396352ccf843Smisaki ldv, endldg, (*ldgp)->ldg, (*ldgp)->ldvp));
39642bc98732SRichard Lowe ++*ldvp;
39652bc98732SRichard Lowe ++*ldgp;
396644961713Sgirish NXGE_DEBUG_MSG((NULL, INT_CTL,
396752ccf843Smisaki "==> nxge_ldgv_setup: new ngrps %d", *ngrps));
396844961713Sgirish }
396944961713Sgirish
397044961713Sgirish NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup: "
397152ccf843Smisaki "ldv %d ldvp $%p endldg %d ngrps %d",
397252ccf843Smisaki ldv, ldvp, endldg, *ngrps));
397344961713Sgirish
397444961713Sgirish NXGE_DEBUG_MSG((NULL, INT_CTL, "<== nxge_ldgv_setup"));
397544961713Sgirish }
397644961713Sgirish
397744961713Sgirish /*
397858324dfcSspeer * Note: This function assumes the following distribution of mac
397944961713Sgirish * addresses among 4 ports in neptune:
398044961713Sgirish *
398144961713Sgirish * -------------
398244961713Sgirish * 0| |0 - local-mac-address for fn 0
398344961713Sgirish * -------------
398444961713Sgirish * 1| |1 - local-mac-address for fn 1
398544961713Sgirish * -------------
398644961713Sgirish * 2| |2 - local-mac-address for fn 2
398744961713Sgirish * -------------
398844961713Sgirish * 3| |3 - local-mac-address for fn 3
398944961713Sgirish * -------------
399044961713Sgirish * | |4 - Start of alt. mac addr. for fn 0
399144961713Sgirish * | |
399244961713Sgirish * | |
399344961713Sgirish * | |10
399444961713Sgirish * --------------
399544961713Sgirish * | |11 - Start of alt. mac addr. for fn 1
399644961713Sgirish * | |
399744961713Sgirish * | |
399844961713Sgirish * | |17
399944961713Sgirish * --------------
400044961713Sgirish * | |18 - Start of alt. mac addr. for fn 2
400144961713Sgirish * | |
400244961713Sgirish * | |
400344961713Sgirish * | |24
400444961713Sgirish * --------------
400544961713Sgirish * | |25 - Start of alt. mac addr. for fn 3
400644961713Sgirish * | |
400744961713Sgirish * | |
400844961713Sgirish * | |31
400944961713Sgirish * --------------
401044961713Sgirish *
401144961713Sgirish * For N2/NIU the mac addresses is from XAUI card.
401259ac0c16Sdavemq *
401359ac0c16Sdavemq * When 'compute_addrs' is true, the alternate mac addresses are computed
401459ac0c16Sdavemq * using the unique mac address as base. Otherwise the alternate addresses
401559ac0c16Sdavemq * are assigned from the list read off the 'mac-addresses' property.
401644961713Sgirish */
401744961713Sgirish
401844961713Sgirish static void
nxge_init_mmac(p_nxge_t nxgep,boolean_t compute_addrs)401959ac0c16Sdavemq nxge_init_mmac(p_nxge_t nxgep, boolean_t compute_addrs)
402044961713Sgirish {
402158324dfcSspeer int slot;
4022a3c5bd6dSspeer uint8_t func_num;
4023a3c5bd6dSspeer uint16_t *base_mmac_addr;
402458324dfcSspeer uint32_t alt_mac_ls4b;
4025a3c5bd6dSspeer uint16_t *mmac_addr;
402658324dfcSspeer uint32_t base_mac_ls4b; /* least significant 4 bytes */
402758324dfcSspeer nxge_mmac_t *mmac_info;
4028a3c5bd6dSspeer npi_mac_addr_t mac_addr;
402944961713Sgirish
4030*e3d11eeeSToomas Soome alt_mac_ls4b = 0;
403144961713Sgirish func_num = nxgep->function_num;
403244961713Sgirish base_mmac_addr = (uint16_t *)&nxgep->factaddr;
403358324dfcSspeer mmac_info = (nxge_mmac_t *)&nxgep->nxge_mmac_info;
403444961713Sgirish
403559ac0c16Sdavemq if (compute_addrs) {
403659ac0c16Sdavemq base_mac_ls4b = ((uint32_t)base_mmac_addr[1]) << 16 |
403759ac0c16Sdavemq base_mmac_addr[2];
403844961713Sgirish
403959ac0c16Sdavemq if (nxgep->niu_type == N2_NIU) {
404059ac0c16Sdavemq /* ls4b of 1st altmac */
404159ac0c16Sdavemq alt_mac_ls4b = base_mac_ls4b + 1;
404259ac0c16Sdavemq } else { /* Neptune */
404359ac0c16Sdavemq alt_mac_ls4b = base_mac_ls4b +
404459ac0c16Sdavemq (nxgep->nports - func_num) +
404559ac0c16Sdavemq (func_num * (mmac_info->num_factory_mmac));
404659ac0c16Sdavemq }
404758324dfcSspeer }
404844961713Sgirish
404958324dfcSspeer /* Set flags for unique MAC */
405058324dfcSspeer mmac_info->mac_pool[0].flags |= MMAC_SLOT_USED | MMAC_VENDOR_ADDR;
405158324dfcSspeer
405258324dfcSspeer /* Clear flags of all alternate MAC slots */
405358324dfcSspeer for (slot = 1; slot <= mmac_info->num_mmac; slot++) {
405458324dfcSspeer if (slot <= mmac_info->num_factory_mmac)
405558324dfcSspeer mmac_info->mac_pool[slot].flags = MMAC_VENDOR_ADDR;
405658324dfcSspeer else
405758324dfcSspeer mmac_info->mac_pool[slot].flags = 0;
405858324dfcSspeer }
405958324dfcSspeer
406058324dfcSspeer /* Generate and store factory alternate MACs */
406158324dfcSspeer for (slot = 1; slot <= mmac_info->num_factory_mmac; slot++) {
406258324dfcSspeer mmac_addr = (uint16_t *)&mmac_info->factory_mac_pool[slot];
406359ac0c16Sdavemq if (compute_addrs) {
406459ac0c16Sdavemq mmac_addr[0] = base_mmac_addr[0];
406559ac0c16Sdavemq mac_addr.w2 = mmac_addr[0];
406659ac0c16Sdavemq
406759ac0c16Sdavemq mmac_addr[1] = (alt_mac_ls4b >> 16) & 0x0FFFF;
406859ac0c16Sdavemq mac_addr.w1 = mmac_addr[1];
406959ac0c16Sdavemq
407059ac0c16Sdavemq mmac_addr[2] = alt_mac_ls4b & 0x0FFFF;
407159ac0c16Sdavemq mac_addr.w0 = mmac_addr[2];
407244961713Sgirish
407359ac0c16Sdavemq alt_mac_ls4b++;
407459ac0c16Sdavemq } else {
407559ac0c16Sdavemq mac_addr.w2 = mmac_addr[0];
407659ac0c16Sdavemq mac_addr.w1 = mmac_addr[1];
407759ac0c16Sdavemq mac_addr.w0 = mmac_addr[2];
407859ac0c16Sdavemq }
407944961713Sgirish
408059ac0c16Sdavemq NXGE_DEBUG_MSG((nxgep, DDI_CTL,
408159ac0c16Sdavemq "mac_pool_addr[%2x:%2x:%2x:%2x:%2x:%2x] npi_addr[%x%x%x]",
408259ac0c16Sdavemq mmac_info->factory_mac_pool[slot][0],
408359ac0c16Sdavemq mmac_info->factory_mac_pool[slot][1],
408459ac0c16Sdavemq mmac_info->factory_mac_pool[slot][2],
408559ac0c16Sdavemq mmac_info->factory_mac_pool[slot][3],
408659ac0c16Sdavemq mmac_info->factory_mac_pool[slot][4],
408759ac0c16Sdavemq mmac_info->factory_mac_pool[slot][5],
408859ac0c16Sdavemq mac_addr.w0, mac_addr.w1, mac_addr.w2));
408944961713Sgirish /*
409059ac0c16Sdavemq * slot minus 1 because npi_mac_altaddr_entry expects 0
409158324dfcSspeer * for the first alternate mac address.
409244961713Sgirish */
409344961713Sgirish (void) npi_mac_altaddr_entry(nxgep->npi_handle, OP_SET,
409452ccf843Smisaki NXGE_GET_PORT_NUM(func_num), slot - 1, &mac_addr);
409544961713Sgirish }
409658324dfcSspeer /* Initialize the first two parameters for mmac kstat */
409758324dfcSspeer nxgep->statsp->mmac_stats.mmac_max_cnt = mmac_info->num_mmac;
409858324dfcSspeer nxgep->statsp->mmac_stats.mmac_avail_cnt = mmac_info->num_mmac;
409944961713Sgirish }
4100da14cebeSEric Cheng
4101da14cebeSEric Cheng /*
4102da14cebeSEric Cheng * Convert an RDC group index into a port ring index. That is, map
4103da14cebeSEric Cheng * <groupid> to an index into nxgep->rx_ring_handles.
4104da14cebeSEric Cheng * (group ring index -> port ring index)
4105da14cebeSEric Cheng */
4106da14cebeSEric Cheng int
nxge_get_rxring_index(p_nxge_t nxgep,int groupid,int ringidx)4107da14cebeSEric Cheng nxge_get_rxring_index(p_nxge_t nxgep, int groupid, int ringidx)
4108da14cebeSEric Cheng {
4109da14cebeSEric Cheng int i;
4110da14cebeSEric Cheng int index = 0;
4111da14cebeSEric Cheng p_nxge_rdc_grp_t rdc_grp_p;
4112da14cebeSEric Cheng p_nxge_dma_pt_cfg_t p_dma_cfgp;
4113da14cebeSEric Cheng p_nxge_hw_pt_cfg_t p_cfgp;
4114da14cebeSEric Cheng
4115da14cebeSEric Cheng p_dma_cfgp = &nxgep->pt_config;
4116da14cebeSEric Cheng p_cfgp = &p_dma_cfgp->hw_config;
4117da14cebeSEric Cheng
411863f531d1SSriharsha Basavapatna if (isLDOMguest(nxgep))
411963f531d1SSriharsha Basavapatna return (ringidx);
412063f531d1SSriharsha Basavapatna
4121da14cebeSEric Cheng for (i = 0; i < groupid; i++) {
4122da14cebeSEric Cheng rdc_grp_p =
4123da14cebeSEric Cheng &p_dma_cfgp->rdc_grps[p_cfgp->def_mac_rxdma_grpid + i];
4124da14cebeSEric Cheng index += rdc_grp_p->max_rdcs;
4125da14cebeSEric Cheng }
4126da14cebeSEric Cheng
4127da14cebeSEric Cheng return (index + ringidx);
4128da14cebeSEric Cheng }
4129