144961713Sgirish /*
244961713Sgirish  * CDDL HEADER START
344961713Sgirish  *
444961713Sgirish  * The contents of this file are subject to the terms of the
544961713Sgirish  * Common Development and Distribution License (the "License").
644961713Sgirish  * You may not use this file except in compliance with the License.
744961713Sgirish  *
844961713Sgirish  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
944961713Sgirish  * or http://www.opensolaris.org/os/licensing.
1044961713Sgirish  * See the License for the specific language governing permissions
1144961713Sgirish  * and limitations under the License.
1244961713Sgirish  *
1344961713Sgirish  * When distributing Covered Code, include this CDDL HEADER in each
1444961713Sgirish  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1544961713Sgirish  * If applicable, add the following below this CDDL HEADER, with the
1644961713Sgirish  * fields enclosed by brackets "[]" replaced with your own identifying
1744961713Sgirish  * information: Portions Copyright [yyyy] [name of copyright owner]
1844961713Sgirish  *
1944961713Sgirish  * CDDL HEADER END
2044961713Sgirish  */
21ef523517SMichael Speer 
2244961713Sgirish /*
230dc2366fSVenugopal Iyer  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
2444961713Sgirish  * Use is subject to license terms.
2544961713Sgirish  */
2644961713Sgirish 
2744961713Sgirish #include <sys/nxge/nxge_impl.h>
2844961713Sgirish #include <sys/nxge/nxge_rxdma.h>
29678453a8Sspeer #include <sys/nxge/nxge_hio.h>
30678453a8Sspeer 
31678453a8Sspeer #if !defined(_BIG_ENDIAN)
32678453a8Sspeer #include <npi_rx_rd32.h>
33678453a8Sspeer #endif
34678453a8Sspeer #include <npi_rx_rd64.h>
35678453a8Sspeer #include <npi_rx_wr64.h>
3644961713Sgirish 
3744961713Sgirish #define	NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp)	\
38678453a8Sspeer 	(rdcgrp + nxgep->pt_config.hw_config.def_mac_rxdma_grpid)
3944961713Sgirish #define	NXGE_ACTUAL_RDC(nxgep, rdc)	\
4044961713Sgirish 	(rdc + nxgep->pt_config.hw_config.start_rdc)
4144961713Sgirish 
4244961713Sgirish /*
4344961713Sgirish  * Globals: tunable parameters (/etc/system or adb)
4444961713Sgirish  *
4544961713Sgirish  */
4644961713Sgirish extern uint32_t nxge_rbr_size;
4744961713Sgirish extern uint32_t nxge_rcr_size;
4844961713Sgirish extern uint32_t	nxge_rbr_spare_size;
494df55fdeSJanie Lu extern uint16_t	nxge_rdc_buf_offset;
5044961713Sgirish 
5144961713Sgirish extern uint32_t nxge_mblks_pending;
5244961713Sgirish 
5344961713Sgirish /*
5444961713Sgirish  * Tunable to reduce the amount of time spent in the
5544961713Sgirish  * ISR doing Rx Processing.
5644961713Sgirish  */
5744961713Sgirish extern uint32_t nxge_max_rx_pkts;
5844961713Sgirish 
5944961713Sgirish /*
6044961713Sgirish  * Tunables to manage the receive buffer blocks.
6144961713Sgirish  *
6244961713Sgirish  * nxge_rx_threshold_hi: copy all buffers.
6344961713Sgirish  * nxge_rx_bcopy_size_type: receive buffer block size type.
6444961713Sgirish  * nxge_rx_threshold_lo: copy only up to tunable block size type.
6544961713Sgirish  */
6644961713Sgirish extern nxge_rxbuf_threshold_t nxge_rx_threshold_hi;
6744961713Sgirish extern nxge_rxbuf_type_t nxge_rx_buf_size_type;
6844961713Sgirish extern nxge_rxbuf_threshold_t nxge_rx_threshold_lo;
6944961713Sgirish 
70b4d05839Sml extern uint32_t	nxge_cksum_offload;
71678453a8Sspeer 
72678453a8Sspeer static nxge_status_t nxge_map_rxdma(p_nxge_t, int);
73678453a8Sspeer static void nxge_unmap_rxdma(p_nxge_t, int);
7444961713Sgirish 
7544961713Sgirish static nxge_status_t nxge_rxdma_hw_start_common(p_nxge_t);
7644961713Sgirish 
77678453a8Sspeer static nxge_status_t nxge_rxdma_hw_start(p_nxge_t, int);
78678453a8Sspeer static void nxge_rxdma_hw_stop(p_nxge_t, int);
7944961713Sgirish 
8044961713Sgirish static nxge_status_t nxge_map_rxdma_channel(p_nxge_t, uint16_t,
8144961713Sgirish     p_nxge_dma_common_t *,  p_rx_rbr_ring_t *,
8244961713Sgirish     uint32_t,
8344961713Sgirish     p_nxge_dma_common_t *, p_rx_rcr_ring_t *,
8444961713Sgirish     p_rx_mbox_t *);
8544961713Sgirish static void nxge_unmap_rxdma_channel(p_nxge_t, uint16_t,
8644961713Sgirish     p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t);
8744961713Sgirish 
8844961713Sgirish static nxge_status_t nxge_map_rxdma_channel_cfg_ring(p_nxge_t,
8944961713Sgirish     uint16_t,
9044961713Sgirish     p_nxge_dma_common_t *, p_rx_rbr_ring_t *,
9144961713Sgirish     p_rx_rcr_ring_t *, p_rx_mbox_t *);
9244961713Sgirish static void nxge_unmap_rxdma_channel_cfg_ring(p_nxge_t,
9344961713Sgirish     p_rx_rcr_ring_t, p_rx_mbox_t);
9444961713Sgirish 
9544961713Sgirish static nxge_status_t nxge_map_rxdma_channel_buf_ring(p_nxge_t,
9644961713Sgirish     uint16_t,
9744961713Sgirish     p_nxge_dma_common_t *,
9844961713Sgirish     p_rx_rbr_ring_t *, uint32_t);
9944961713Sgirish static void nxge_unmap_rxdma_channel_buf_ring(p_nxge_t,
10044961713Sgirish     p_rx_rbr_ring_t);
10144961713Sgirish 
10244961713Sgirish static nxge_status_t nxge_rxdma_start_channel(p_nxge_t, uint16_t,
10344961713Sgirish     p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t);
10444961713Sgirish static nxge_status_t nxge_rxdma_stop_channel(p_nxge_t, uint16_t);
10544961713Sgirish 
106678453a8Sspeer static mblk_t *
107678453a8Sspeer nxge_rx_pkts(p_nxge_t, p_rx_rcr_ring_t, rx_dma_ctl_stat_t, int);
10844961713Sgirish 
10944961713Sgirish static void nxge_receive_packet(p_nxge_t,
11044961713Sgirish 	p_rx_rcr_ring_t,
11144961713Sgirish 	p_rcr_entry_t,
11244961713Sgirish 	boolean_t *,
11344961713Sgirish 	mblk_t **, mblk_t **);
11444961713Sgirish 
11544961713Sgirish nxge_status_t nxge_disable_rxdma_channel(p_nxge_t, uint16_t);
11644961713Sgirish 
11744961713Sgirish static p_rx_msg_t nxge_allocb(size_t, uint32_t, p_nxge_dma_common_t);
11844961713Sgirish static void nxge_freeb(p_rx_msg_t);
119678453a8Sspeer static nxge_status_t nxge_rx_err_evnts(p_nxge_t, int, rx_dma_ctl_stat_t);
12044961713Sgirish 
12144961713Sgirish static nxge_status_t nxge_rxdma_handle_port_errors(p_nxge_t,
12244961713Sgirish 				uint32_t, uint32_t);
12344961713Sgirish 
12444961713Sgirish static nxge_status_t nxge_rxbuf_index_info_init(p_nxge_t,
12544961713Sgirish     p_rx_rbr_ring_t);
12644961713Sgirish 
12744961713Sgirish 
12844961713Sgirish static nxge_status_t
12944961713Sgirish nxge_rxdma_fatal_err_recover(p_nxge_t, uint16_t);
13044961713Sgirish 
13144961713Sgirish nxge_status_t
13244961713Sgirish nxge_rx_port_fatal_err_recover(p_nxge_t);
13344961713Sgirish 
134678453a8Sspeer static void nxge_rxdma_databuf_free(p_rx_rbr_ring_t);
135678453a8Sspeer 
13644961713Sgirish nxge_status_t
nxge_init_rxdma_channels(p_nxge_t nxgep)13744961713Sgirish nxge_init_rxdma_channels(p_nxge_t nxgep)
13844961713Sgirish {
139e11f0814SMichael Speer 	nxge_grp_set_t	*set = &nxgep->rx_set;
140da14cebeSEric Cheng 	int		i, count, channel;
141e11f0814SMichael Speer 	nxge_grp_t	*group;
142da14cebeSEric Cheng 	dc_map_t	map;
143da14cebeSEric Cheng 	int		dev_gindex;
14444961713Sgirish 
14544961713Sgirish 	NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_init_rxdma_channels"));
14644961713Sgirish 
147678453a8Sspeer 	if (!isLDOMguest(nxgep)) {
148678453a8Sspeer 		if (nxge_rxdma_hw_start_common(nxgep) != NXGE_OK) {
149678453a8Sspeer 			cmn_err(CE_NOTE, "hw_start_common");
150678453a8Sspeer 			return (NXGE_ERROR);
151678453a8Sspeer 		}
152678453a8Sspeer 	}
153678453a8Sspeer 
154678453a8Sspeer 	/*
155678453a8Sspeer 	 * NXGE_LOGICAL_GROUP_MAX > NXGE_MAX_RDC_GROUPS (8)
156678453a8Sspeer 	 * We only have 8 hardware RDC tables, but we may have
157678453a8Sspeer 	 * up to 16 logical (software-defined) groups of RDCS,
158678453a8Sspeer 	 * if we make use of layer 3 & 4 hardware classification.
159678453a8Sspeer 	 */
160678453a8Sspeer 	for (i = 0, count = 0; i < NXGE_LOGICAL_GROUP_MAX; i++) {
161678453a8Sspeer 		if ((1 << i) & set->lg.map) {
162e11f0814SMichael Speer 			group = set->group[i];
163da14cebeSEric Cheng 			dev_gindex =
164da14cebeSEric Cheng 			    nxgep->pt_config.hw_config.def_mac_rxdma_grpid + i;
165da14cebeSEric Cheng 			map = nxgep->pt_config.rdc_grps[dev_gindex].map;
166678453a8Sspeer 			for (channel = 0; channel < NXGE_MAX_RDCS; channel++) {
167da14cebeSEric Cheng 				if ((1 << channel) & map) {
168678453a8Sspeer 					if ((nxge_grp_dc_add(nxgep,
1696920a987SMisaki Miyashita 					    group, VP_BOUND_RX, channel)))
170e11f0814SMichael Speer 						goto init_rxdma_channels_exit;
171678453a8Sspeer 				}
172678453a8Sspeer 			}
173678453a8Sspeer 		}
174678453a8Sspeer 		if (++count == set->lg.count)
175678453a8Sspeer 			break;
17644961713Sgirish 	}
17744961713Sgirish 
178678453a8Sspeer 	NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_init_rxdma_channels"));
179678453a8Sspeer 	return (NXGE_OK);
180e11f0814SMichael Speer 
181e11f0814SMichael Speer init_rxdma_channels_exit:
182e11f0814SMichael Speer 	for (i = 0, count = 0; i < NXGE_LOGICAL_GROUP_MAX; i++) {
183e11f0814SMichael Speer 		if ((1 << i) & set->lg.map) {
184e11f0814SMichael Speer 			group = set->group[i];
185da14cebeSEric Cheng 			dev_gindex =
186da14cebeSEric Cheng 			    nxgep->pt_config.hw_config.def_mac_rxdma_grpid + i;
187da14cebeSEric Cheng 			map = nxgep->pt_config.rdc_grps[dev_gindex].map;
188da14cebeSEric Cheng 			for (channel = 0; channel < NXGE_MAX_RDCS; channel++) {
189da14cebeSEric Cheng 				if ((1 << channel) & map) {
190e11f0814SMichael Speer 					nxge_grp_dc_remove(nxgep,
191da14cebeSEric Cheng 					    VP_BOUND_RX, channel);
192e11f0814SMichael Speer 				}
193e11f0814SMichael Speer 			}
194e11f0814SMichael Speer 		}
195e11f0814SMichael Speer 		if (++count == set->lg.count)
196e11f0814SMichael Speer 			break;
197e11f0814SMichael Speer 	}
198e11f0814SMichael Speer 
199e11f0814SMichael Speer 	NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_init_rxdma_channels"));
200e11f0814SMichael Speer 	return (NXGE_ERROR);
201678453a8Sspeer }
202678453a8Sspeer 
203678453a8Sspeer nxge_status_t
nxge_init_rxdma_channel(p_nxge_t nxge,int channel)204678453a8Sspeer nxge_init_rxdma_channel(p_nxge_t nxge, int channel)
205678453a8Sspeer {
20608ac1c49SNicolas Droux 	nxge_status_t	status;
207678453a8Sspeer 
208678453a8Sspeer 	NXGE_DEBUG_MSG((nxge, MEM2_CTL, "==> nxge_init_rxdma_channel"));
209678453a8Sspeer 
210678453a8Sspeer 	status = nxge_map_rxdma(nxge, channel);
21144961713Sgirish 	if (status != NXGE_OK) {
212678453a8Sspeer 		NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL,
213678453a8Sspeer 		    "<== nxge_init_rxdma: status 0x%x", status));
214678453a8Sspeer 		return (status);
21544961713Sgirish 	}
21644961713Sgirish 
21708ac1c49SNicolas Droux #if defined(sun4v)
21808ac1c49SNicolas Droux 	if (isLDOMguest(nxge)) {
21908ac1c49SNicolas Droux 		/* set rcr_ring */
22008ac1c49SNicolas Droux 		p_rx_rcr_ring_t ring = nxge->rx_rcr_rings->rcr_rings[channel];
22108ac1c49SNicolas Droux 
22208ac1c49SNicolas Droux 		status = nxge_hio_rxdma_bind_intr(nxge, ring, channel);
22308ac1c49SNicolas Droux 		if (status != NXGE_OK) {
22408ac1c49SNicolas Droux 			nxge_unmap_rxdma(nxge, channel);
22508ac1c49SNicolas Droux 			return (status);
22608ac1c49SNicolas Droux 		}
22708ac1c49SNicolas Droux 	}
22808ac1c49SNicolas Droux #endif
22908ac1c49SNicolas Droux 
230678453a8Sspeer 	status = nxge_rxdma_hw_start(nxge, channel);
23144961713Sgirish 	if (status != NXGE_OK) {
232678453a8Sspeer 		nxge_unmap_rxdma(nxge, channel);
23344961713Sgirish 	}
23444961713Sgirish 
235678453a8Sspeer 	if (!nxge->statsp->rdc_ksp[channel])
236678453a8Sspeer 		nxge_setup_rdc_kstats(nxge, channel);
237678453a8Sspeer 
238678453a8Sspeer 	NXGE_DEBUG_MSG((nxge, MEM2_CTL,
239678453a8Sspeer 	    "<== nxge_init_rxdma_channel: status 0x%x", status));
24044961713Sgirish 
24144961713Sgirish 	return (status);
24244961713Sgirish }
24344961713Sgirish 
24444961713Sgirish void
nxge_uninit_rxdma_channels(p_nxge_t nxgep)24544961713Sgirish nxge_uninit_rxdma_channels(p_nxge_t nxgep)
24644961713Sgirish {
247678453a8Sspeer 	nxge_grp_set_t *set = &nxgep->rx_set;
248678453a8Sspeer 	int rdc;
249678453a8Sspeer 
25044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_uninit_rxdma_channels"));
25144961713Sgirish 
252678453a8Sspeer 	if (set->owned.map == 0) {
253678453a8Sspeer 		NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
254678453a8Sspeer 		    "nxge_uninit_rxdma_channels: no channels"));
255678453a8Sspeer 		return;
256678453a8Sspeer 	}
25744961713Sgirish 
258678453a8Sspeer 	for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) {
259678453a8Sspeer 		if ((1 << rdc) & set->owned.map) {
260678453a8Sspeer 			nxge_grp_dc_remove(nxgep, VP_BOUND_RX, rdc);
261678453a8Sspeer 		}
262678453a8Sspeer 	}
263678453a8Sspeer 
264678453a8Sspeer 	NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_uninit_rxdma_channels"));
265678453a8Sspeer }
266678453a8Sspeer 
267678453a8Sspeer void
nxge_uninit_rxdma_channel(p_nxge_t nxgep,int channel)268678453a8Sspeer nxge_uninit_rxdma_channel(p_nxge_t nxgep, int channel)
269678453a8Sspeer {
270678453a8Sspeer 	NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_uninit_rxdma_channel"));
271678453a8Sspeer 
272678453a8Sspeer 	if (nxgep->statsp->rdc_ksp[channel]) {
273678453a8Sspeer 		kstat_delete(nxgep->statsp->rdc_ksp[channel]);
274678453a8Sspeer 		nxgep->statsp->rdc_ksp[channel] = 0;
275678453a8Sspeer 	}
276678453a8Sspeer 
277678453a8Sspeer 	nxge_rxdma_hw_stop(nxgep, channel);
278678453a8Sspeer 	nxge_unmap_rxdma(nxgep, channel);
279678453a8Sspeer 
280678453a8Sspeer 	NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_uinit_rxdma_channel"));
28144961713Sgirish }
28244961713Sgirish 
28344961713Sgirish nxge_status_t
nxge_reset_rxdma_channel(p_nxge_t nxgep,uint16_t channel)28444961713Sgirish nxge_reset_rxdma_channel(p_nxge_t nxgep, uint16_t channel)
28544961713Sgirish {
28644961713Sgirish 	npi_handle_t		handle;
28744961713Sgirish 	npi_status_t		rs = NPI_SUCCESS;
28844961713Sgirish 	nxge_status_t		status = NXGE_OK;
28944961713Sgirish 
290330cd344SMichael Speer 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_reset_rxdma_channel"));
29144961713Sgirish 
29244961713Sgirish 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
29344961713Sgirish 	rs = npi_rxdma_cfg_rdc_reset(handle, channel);
29444961713Sgirish 
29544961713Sgirish 	if (rs != NPI_SUCCESS) {
29644961713Sgirish 		status = NXGE_ERROR | rs;
29744961713Sgirish 	}
29844961713Sgirish 
299330cd344SMichael Speer 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_reset_rxdma_channel"));
300330cd344SMichael Speer 
30144961713Sgirish 	return (status);
30244961713Sgirish }
30344961713Sgirish 
30444961713Sgirish void
nxge_rxdma_regs_dump_channels(p_nxge_t nxgep)30544961713Sgirish nxge_rxdma_regs_dump_channels(p_nxge_t nxgep)
30644961713Sgirish {
307678453a8Sspeer 	nxge_grp_set_t *set = &nxgep->rx_set;
308678453a8Sspeer 	int rdc;
30944961713Sgirish 
31044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_regs_dump_channels"));
31144961713Sgirish 
312678453a8Sspeer 	if (!isLDOMguest(nxgep)) {
313678453a8Sspeer 		npi_handle_t handle = NXGE_DEV_NPI_HANDLE(nxgep);
314678453a8Sspeer 		(void) npi_rxdma_dump_fzc_regs(handle);
31544961713Sgirish 	}
316678453a8Sspeer 
317678453a8Sspeer 	if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) {
318678453a8Sspeer 		NXGE_DEBUG_MSG((nxgep, TX_CTL,
319678453a8Sspeer 		    "nxge_rxdma_regs_dump_channels: "
320678453a8Sspeer 		    "NULL ring pointer(s)"));
32144961713Sgirish 		return;
32244961713Sgirish 	}
32344961713Sgirish 
324678453a8Sspeer 	if (set->owned.map == 0) {
32544961713Sgirish 		NXGE_DEBUG_MSG((nxgep, RX_CTL,
326678453a8Sspeer 		    "nxge_rxdma_regs_dump_channels: no channels"));
32744961713Sgirish 		return;
32844961713Sgirish 	}
32944961713Sgirish 
330678453a8Sspeer 	for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) {
331678453a8Sspeer 		if ((1 << rdc) & set->owned.map) {
332678453a8Sspeer 			rx_rbr_ring_t *ring =
333678453a8Sspeer 			    nxgep->rx_rbr_rings->rbr_rings[rdc];
334678453a8Sspeer 			if (ring) {
335678453a8Sspeer 				(void) nxge_dump_rxdma_channel(nxgep, rdc);
336678453a8Sspeer 			}
33744961713Sgirish 		}
33844961713Sgirish 	}
33944961713Sgirish 
34044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_regs_dump"));
34144961713Sgirish }
34244961713Sgirish 
34344961713Sgirish nxge_status_t
nxge_dump_rxdma_channel(p_nxge_t nxgep,uint8_t channel)34444961713Sgirish nxge_dump_rxdma_channel(p_nxge_t nxgep, uint8_t channel)
34544961713Sgirish {
34644961713Sgirish 	npi_handle_t		handle;
34744961713Sgirish 	npi_status_t		rs = NPI_SUCCESS;
34844961713Sgirish 	nxge_status_t		status = NXGE_OK;
34944961713Sgirish 
35044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_dump_rxdma_channel"));
35144961713Sgirish 
35244961713Sgirish 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
35344961713Sgirish 	rs = npi_rxdma_dump_rdc_regs(handle, channel);
35444961713Sgirish 
35544961713Sgirish 	if (rs != NPI_SUCCESS) {
35644961713Sgirish 		status = NXGE_ERROR | rs;
35744961713Sgirish 	}
35844961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_dump_rxdma_channel"));
35944961713Sgirish 	return (status);
36044961713Sgirish }
36144961713Sgirish 
36244961713Sgirish nxge_status_t
nxge_init_rxdma_channel_event_mask(p_nxge_t nxgep,uint16_t channel,p_rx_dma_ent_msk_t mask_p)36344961713Sgirish nxge_init_rxdma_channel_event_mask(p_nxge_t nxgep, uint16_t channel,
36444961713Sgirish     p_rx_dma_ent_msk_t mask_p)
36544961713Sgirish {
36644961713Sgirish 	npi_handle_t		handle;
36744961713Sgirish 	npi_status_t		rs = NPI_SUCCESS;
36844961713Sgirish 	nxge_status_t		status = NXGE_OK;
36944961713Sgirish 
37044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DMA_CTL,
37152ccf843Smisaki 	    "<== nxge_init_rxdma_channel_event_mask"));
37244961713Sgirish 
37344961713Sgirish 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
37444961713Sgirish 	rs = npi_rxdma_event_mask(handle, OP_SET, channel, mask_p);
37544961713Sgirish 	if (rs != NPI_SUCCESS) {
37644961713Sgirish 		status = NXGE_ERROR | rs;
37744961713Sgirish 	}
37844961713Sgirish 
37944961713Sgirish 	return (status);
38044961713Sgirish }
38144961713Sgirish 
38244961713Sgirish nxge_status_t
nxge_init_rxdma_channel_cntl_stat(p_nxge_t nxgep,uint16_t channel,p_rx_dma_ctl_stat_t cs_p)38344961713Sgirish nxge_init_rxdma_channel_cntl_stat(p_nxge_t nxgep, uint16_t channel,
38444961713Sgirish     p_rx_dma_ctl_stat_t cs_p)
38544961713Sgirish {
38644961713Sgirish 	npi_handle_t		handle;
38744961713Sgirish 	npi_status_t		rs = NPI_SUCCESS;
38844961713Sgirish 	nxge_status_t		status = NXGE_OK;
38944961713Sgirish 
39044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DMA_CTL,
39152ccf843Smisaki 	    "<== nxge_init_rxdma_channel_cntl_stat"));
39244961713Sgirish 
39344961713Sgirish 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
39444961713Sgirish 	rs = npi_rxdma_control_status(handle, OP_SET, channel, cs_p);
39544961713Sgirish 
39644961713Sgirish 	if (rs != NPI_SUCCESS) {
39744961713Sgirish 		status = NXGE_ERROR | rs;
39844961713Sgirish 	}
39944961713Sgirish 
40044961713Sgirish 	return (status);
40144961713Sgirish }
40244961713Sgirish 
403678453a8Sspeer /*
404678453a8Sspeer  * nxge_rxdma_cfg_rdcgrp_default_rdc
405678453a8Sspeer  *
406678453a8Sspeer  *	Set the default RDC for an RDC Group (Table)
407678453a8Sspeer  *
408678453a8Sspeer  * Arguments:
409*86ef0a63SRichard Lowe  *	nxgep
410678453a8Sspeer  *	rdcgrp	The group to modify
411678453a8Sspeer  *	rdc	The new default RDC.
412678453a8Sspeer  *
413678453a8Sspeer  * Notes:
414678453a8Sspeer  *
415678453a8Sspeer  * NPI/NXGE function calls:
416678453a8Sspeer  *	npi_rxdma_cfg_rdc_table_default_rdc()
417678453a8Sspeer  *
418678453a8Sspeer  * Registers accessed:
419678453a8Sspeer  *	RDC_TBL_REG: FZC_ZCP + 0x10000
420678453a8Sspeer  *
421678453a8Sspeer  * Context:
422678453a8Sspeer  *	Service domain
423678453a8Sspeer  */
42444961713Sgirish nxge_status_t
nxge_rxdma_cfg_rdcgrp_default_rdc(p_nxge_t nxgep,uint8_t rdcgrp,uint8_t rdc)425678453a8Sspeer nxge_rxdma_cfg_rdcgrp_default_rdc(
426678453a8Sspeer 	p_nxge_t nxgep,
427678453a8Sspeer 	uint8_t rdcgrp,
428678453a8Sspeer 	uint8_t rdc)
42944961713Sgirish {
43044961713Sgirish 	npi_handle_t		handle;
43144961713Sgirish 	npi_status_t		rs = NPI_SUCCESS;
43244961713Sgirish 	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
43344961713Sgirish 	p_nxge_rdc_grp_t	rdc_grp_p;
43444961713Sgirish 	uint8_t actual_rdcgrp, actual_rdc;
43544961713Sgirish 
43644961713Sgirish 	NXGE_DEBUG_MSG((nxgep, RX2_CTL,
43752ccf843Smisaki 	    " ==> nxge_rxdma_cfg_rdcgrp_default_rdc"));
43844961713Sgirish 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
43944961713Sgirish 
44044961713Sgirish 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
44144961713Sgirish 
442678453a8Sspeer 	/*
443678453a8Sspeer 	 * This has to be rewritten.  Do we even allow this anymore?
444678453a8Sspeer 	 */
44544961713Sgirish 	rdc_grp_p = &p_dma_cfgp->rdc_grps[rdcgrp];
446678453a8Sspeer 	RDC_MAP_IN(rdc_grp_p->map, rdc);
447678453a8Sspeer 	rdc_grp_p->def_rdc = rdc;
44844961713Sgirish 
44944961713Sgirish 	actual_rdcgrp = NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp);
45044961713Sgirish 	actual_rdc = NXGE_ACTUAL_RDC(nxgep, rdc);
45144961713Sgirish 
452678453a8Sspeer 	rs = npi_rxdma_cfg_rdc_table_default_rdc(
45352ccf843Smisaki 	    handle, actual_rdcgrp, actual_rdc);
45444961713Sgirish 
45544961713Sgirish 	if (rs != NPI_SUCCESS) {
45644961713Sgirish 		return (NXGE_ERROR | rs);
45744961713Sgirish 	}
45844961713Sgirish 	NXGE_DEBUG_MSG((nxgep, RX2_CTL,
45952ccf843Smisaki 	    " <== nxge_rxdma_cfg_rdcgrp_default_rdc"));
46044961713Sgirish 	return (NXGE_OK);
46144961713Sgirish }
46244961713Sgirish 
46344961713Sgirish nxge_status_t
nxge_rxdma_cfg_port_default_rdc(p_nxge_t nxgep,uint8_t port,uint8_t rdc)46444961713Sgirish nxge_rxdma_cfg_port_default_rdc(p_nxge_t nxgep, uint8_t port, uint8_t rdc)
46544961713Sgirish {
46644961713Sgirish 	npi_handle_t		handle;
46744961713Sgirish 
46844961713Sgirish 	uint8_t actual_rdc;
46944961713Sgirish 	npi_status_t		rs = NPI_SUCCESS;
47044961713Sgirish 
47144961713Sgirish 	NXGE_DEBUG_MSG((nxgep, RX2_CTL,
47252ccf843Smisaki 	    " ==> nxge_rxdma_cfg_port_default_rdc"));
47344961713Sgirish 
47444961713Sgirish 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
475678453a8Sspeer 	actual_rdc = rdc;	/* XXX Hack! */
47644961713Sgirish 	rs = npi_rxdma_cfg_default_port_rdc(handle, port, actual_rdc);
47744961713Sgirish 
47844961713Sgirish 
47944961713Sgirish 	if (rs != NPI_SUCCESS) {
48044961713Sgirish 		return (NXGE_ERROR | rs);
48144961713Sgirish 	}
48244961713Sgirish 	NXGE_DEBUG_MSG((nxgep, RX2_CTL,
48352ccf843Smisaki 	    " <== nxge_rxdma_cfg_port_default_rdc"));
48444961713Sgirish 
48544961713Sgirish 	return (NXGE_OK);
48644961713Sgirish }
48744961713Sgirish 
48844961713Sgirish nxge_status_t
nxge_rxdma_cfg_rcr_threshold(p_nxge_t nxgep,uint8_t channel,uint16_t pkts)48944961713Sgirish nxge_rxdma_cfg_rcr_threshold(p_nxge_t nxgep, uint8_t channel,
490*86ef0a63SRichard Lowe     uint16_t pkts)
49144961713Sgirish {
49244961713Sgirish 	npi_status_t	rs = NPI_SUCCESS;
49344961713Sgirish 	npi_handle_t	handle;
49444961713Sgirish 	NXGE_DEBUG_MSG((nxgep, RX2_CTL,
49552ccf843Smisaki 	    " ==> nxge_rxdma_cfg_rcr_threshold"));
49644961713Sgirish 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
49744961713Sgirish 
49844961713Sgirish 	rs = npi_rxdma_cfg_rdc_rcr_threshold(handle, channel, pkts);
49944961713Sgirish 
50044961713Sgirish 	if (rs != NPI_SUCCESS) {
50144961713Sgirish 		return (NXGE_ERROR | rs);
50244961713Sgirish 	}
50344961713Sgirish 	NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_threshold"));
50444961713Sgirish 	return (NXGE_OK);
50544961713Sgirish }
50644961713Sgirish 
50744961713Sgirish nxge_status_t
nxge_rxdma_cfg_rcr_timeout(p_nxge_t nxgep,uint8_t channel,uint16_t tout,uint8_t enable)50844961713Sgirish nxge_rxdma_cfg_rcr_timeout(p_nxge_t nxgep, uint8_t channel,
509*86ef0a63SRichard Lowe     uint16_t tout, uint8_t enable)
51044961713Sgirish {
51144961713Sgirish 	npi_status_t	rs = NPI_SUCCESS;
51244961713Sgirish 	npi_handle_t	handle;
51344961713Sgirish 	NXGE_DEBUG_MSG((nxgep, RX2_CTL, " ==> nxge_rxdma_cfg_rcr_timeout"));
51444961713Sgirish 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
51544961713Sgirish 	if (enable == 0) {
51644961713Sgirish 		rs = npi_rxdma_cfg_rdc_rcr_timeout_disable(handle, channel);
51744961713Sgirish 	} else {
51844961713Sgirish 		rs = npi_rxdma_cfg_rdc_rcr_timeout(handle, channel,
51952ccf843Smisaki 		    tout);
52044961713Sgirish 	}
52144961713Sgirish 
52244961713Sgirish 	if (rs != NPI_SUCCESS) {
52344961713Sgirish 		return (NXGE_ERROR | rs);
52444961713Sgirish 	}
52544961713Sgirish 	NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_timeout"));
52644961713Sgirish 	return (NXGE_OK);
52744961713Sgirish }
52844961713Sgirish 
52944961713Sgirish nxge_status_t
nxge_enable_rxdma_channel(p_nxge_t nxgep,uint16_t channel,p_rx_rbr_ring_t rbr_p,p_rx_rcr_ring_t rcr_p,p_rx_mbox_t mbox_p)53044961713Sgirish nxge_enable_rxdma_channel(p_nxge_t nxgep, uint16_t channel,
53144961713Sgirish     p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p)
53244961713Sgirish {
53344961713Sgirish 	npi_handle_t		handle;
534*86ef0a63SRichard Lowe 	rdc_desc_cfg_t		rdc_desc;
53544961713Sgirish 	p_rcrcfig_b_t		cfgb_p;
53644961713Sgirish 	npi_status_t		rs = NPI_SUCCESS;
53744961713Sgirish 
53844961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel"));
53944961713Sgirish 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
54044961713Sgirish 	/*
54144961713Sgirish 	 * Use configuration data composed at init time.
54244961713Sgirish 	 * Write to hardware the receive ring configurations.
54344961713Sgirish 	 */
54444961713Sgirish 	rdc_desc.mbox_enable = 1;
54544961713Sgirish 	rdc_desc.mbox_addr = mbox_p->mbox_addr;
54644961713Sgirish 	NXGE_DEBUG_MSG((nxgep, RX_CTL,
54752ccf843Smisaki 	    "==> nxge_enable_rxdma_channel: mboxp $%p($%p)",
54852ccf843Smisaki 	    mbox_p->mbox_addr, rdc_desc.mbox_addr));
54944961713Sgirish 
55044961713Sgirish 	rdc_desc.rbr_len = rbr_p->rbb_max;
55144961713Sgirish 	rdc_desc.rbr_addr = rbr_p->rbr_addr;
55244961713Sgirish 
55344961713Sgirish 	switch (nxgep->rx_bksize_code) {
55444961713Sgirish 	case RBR_BKSIZE_4K:
55544961713Sgirish 		rdc_desc.page_size = SIZE_4KB;
55644961713Sgirish 		break;
55744961713Sgirish 	case RBR_BKSIZE_8K:
55844961713Sgirish 		rdc_desc.page_size = SIZE_8KB;
55944961713Sgirish 		break;
56044961713Sgirish 	case RBR_BKSIZE_16K:
56144961713Sgirish 		rdc_desc.page_size = SIZE_16KB;
56244961713Sgirish 		break;
56344961713Sgirish 	case RBR_BKSIZE_32K:
56444961713Sgirish 		rdc_desc.page_size = SIZE_32KB;
56544961713Sgirish 		break;
56644961713Sgirish 	}
56744961713Sgirish 
56844961713Sgirish 	rdc_desc.size0 = rbr_p->npi_pkt_buf_size0;
56944961713Sgirish 	rdc_desc.valid0 = 1;
57044961713Sgirish 
57144961713Sgirish 	rdc_desc.size1 = rbr_p->npi_pkt_buf_size1;
57244961713Sgirish 	rdc_desc.valid1 = 1;
57344961713Sgirish 
57444961713Sgirish 	rdc_desc.size2 = rbr_p->npi_pkt_buf_size2;
57544961713Sgirish 	rdc_desc.valid2 = 1;
57644961713Sgirish 
57744961713Sgirish 	rdc_desc.full_hdr = rcr_p->full_hdr_flag;
57844961713Sgirish 	rdc_desc.offset = rcr_p->sw_priv_hdr_len;
57944961713Sgirish 
58044961713Sgirish 	rdc_desc.rcr_len = rcr_p->comp_size;
58144961713Sgirish 	rdc_desc.rcr_addr = rcr_p->rcr_addr;
58244961713Sgirish 
58344961713Sgirish 	cfgb_p = &(rcr_p->rcr_cfgb);
58444961713Sgirish 	rdc_desc.rcr_threshold = cfgb_p->bits.ldw.pthres;
585678453a8Sspeer 	/* For now, disable this timeout in a guest domain. */
586678453a8Sspeer 	if (isLDOMguest(nxgep)) {
587678453a8Sspeer 		rdc_desc.rcr_timeout = 0;
588678453a8Sspeer 		rdc_desc.rcr_timeout_enable = 0;
589678453a8Sspeer 	} else {
590678453a8Sspeer 		rdc_desc.rcr_timeout = cfgb_p->bits.ldw.timeout;
591678453a8Sspeer 		rdc_desc.rcr_timeout_enable = cfgb_p->bits.ldw.entout;
592678453a8Sspeer 	}
59344961713Sgirish 
59444961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: "
59552ccf843Smisaki 	    "rbr_len qlen %d pagesize code %d rcr_len %d",
59652ccf843Smisaki 	    rdc_desc.rbr_len, rdc_desc.page_size, rdc_desc.rcr_len));
59744961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: "
59852ccf843Smisaki 	    "size 0 %d size 1 %d size 2 %d",
59952ccf843Smisaki 	    rbr_p->npi_pkt_buf_size0, rbr_p->npi_pkt_buf_size1,
60052ccf843Smisaki 	    rbr_p->npi_pkt_buf_size2));
60144961713Sgirish 
6024df55fdeSJanie Lu 	if (nxgep->niu_hw_type == NIU_HW_TYPE_RF)
6034df55fdeSJanie Lu 		rs = npi_rxdma_cfg_rdc_ring(handle, rbr_p->rdc,
6044df55fdeSJanie Lu 		    &rdc_desc, B_TRUE);
6054df55fdeSJanie Lu 	else
6064df55fdeSJanie Lu 		rs = npi_rxdma_cfg_rdc_ring(handle, rbr_p->rdc,
6074df55fdeSJanie Lu 		    &rdc_desc, B_FALSE);
60844961713Sgirish 	if (rs != NPI_SUCCESS) {
60944961713Sgirish 		return (NXGE_ERROR | rs);
61044961713Sgirish 	}
61144961713Sgirish 
61244961713Sgirish 	/*
61344961713Sgirish 	 * Enable the timeout and threshold.
61444961713Sgirish 	 */
61544961713Sgirish 	rs = npi_rxdma_cfg_rdc_rcr_threshold(handle, channel,
61652ccf843Smisaki 	    rdc_desc.rcr_threshold);
61744961713Sgirish 	if (rs != NPI_SUCCESS) {
61844961713Sgirish 		return (NXGE_ERROR | rs);
61944961713Sgirish 	}
62044961713Sgirish 
62144961713Sgirish 	rs = npi_rxdma_cfg_rdc_rcr_timeout(handle, channel,
62252ccf843Smisaki 	    rdc_desc.rcr_timeout);
62344961713Sgirish 	if (rs != NPI_SUCCESS) {
62444961713Sgirish 		return (NXGE_ERROR | rs);
62544961713Sgirish 	}
62644961713Sgirish 
627e759c33aSMichael Speer 	if (!isLDOMguest(nxgep)) {
628e759c33aSMichael Speer 		/* Enable the DMA */
629e759c33aSMichael Speer 		rs = npi_rxdma_cfg_rdc_enable(handle, channel);
630e759c33aSMichael Speer 		if (rs != NPI_SUCCESS) {
631e759c33aSMichael Speer 			return (NXGE_ERROR | rs);
632e759c33aSMichael Speer 		}
63344961713Sgirish 	}
63444961713Sgirish 
63544961713Sgirish 	/* Kick the DMA engine. */
63644961713Sgirish 	npi_rxdma_rdc_rbr_kick(handle, channel, rbr_p->rbb_max);
637e759c33aSMichael Speer 
638e759c33aSMichael Speer 	if (!isLDOMguest(nxgep)) {
639e759c33aSMichael Speer 		/* Clear the rbr empty bit */
640e759c33aSMichael Speer 		(void) npi_rxdma_channel_rbr_empty_clear(handle, channel);
641e759c33aSMichael Speer 	}
64244961713Sgirish 
64344961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_enable_rxdma_channel"));
64444961713Sgirish 
64544961713Sgirish 	return (NXGE_OK);
64644961713Sgirish }
64744961713Sgirish 
64844961713Sgirish nxge_status_t
nxge_disable_rxdma_channel(p_nxge_t nxgep,uint16_t channel)64944961713Sgirish nxge_disable_rxdma_channel(p_nxge_t nxgep, uint16_t channel)
65044961713Sgirish {
65144961713Sgirish 	npi_handle_t		handle;
65244961713Sgirish 	npi_status_t		rs = NPI_SUCCESS;
65344961713Sgirish 
65444961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_disable_rxdma_channel"));
65544961713Sgirish 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
65644961713Sgirish 
65744961713Sgirish 	/* disable the DMA */
65844961713Sgirish 	rs = npi_rxdma_cfg_rdc_disable(handle, channel);
65944961713Sgirish 	if (rs != NPI_SUCCESS) {
66044961713Sgirish 		NXGE_DEBUG_MSG((nxgep, RX_CTL,
66152ccf843Smisaki 		    "<== nxge_disable_rxdma_channel:failed (0x%x)",
66252ccf843Smisaki 		    rs));
66344961713Sgirish 		return (NXGE_ERROR | rs);
66444961713Sgirish 	}
66544961713Sgirish 
66644961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_disable_rxdma_channel"));
66744961713Sgirish 	return (NXGE_OK);
66844961713Sgirish }
66944961713Sgirish 
67044961713Sgirish nxge_status_t
nxge_rxdma_channel_rcrflush(p_nxge_t nxgep,uint8_t channel)67144961713Sgirish nxge_rxdma_channel_rcrflush(p_nxge_t nxgep, uint8_t channel)
67244961713Sgirish {
67344961713Sgirish 	npi_handle_t		handle;
67444961713Sgirish 	nxge_status_t		status = NXGE_OK;
67544961713Sgirish 
67644961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DMA_CTL,
67752ccf843Smisaki 	    "<== nxge_init_rxdma_channel_rcrflush"));
67844961713Sgirish 
67944961713Sgirish 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
68044961713Sgirish 	npi_rxdma_rdc_rcr_flush(handle, channel);
68144961713Sgirish 
68244961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DMA_CTL,
68352ccf843Smisaki 	    "<== nxge_init_rxdma_channel_rcrflsh"));
68444961713Sgirish 	return (status);
68544961713Sgirish 
68644961713Sgirish }
68744961713Sgirish 
68844961713Sgirish #define	MID_INDEX(l, r) ((r + l + 1) >> 1)
68944961713Sgirish 
69044961713Sgirish #define	TO_LEFT -1
69144961713Sgirish #define	TO_RIGHT 1
69244961713Sgirish #define	BOTH_RIGHT (TO_RIGHT + TO_RIGHT)
69344961713Sgirish #define	BOTH_LEFT (TO_LEFT + TO_LEFT)
69444961713Sgirish #define	IN_MIDDLE (TO_RIGHT + TO_LEFT)
69544961713Sgirish #define	NO_HINT 0xffffffff
69644961713Sgirish 
69744961713Sgirish /*ARGSUSED*/
69844961713Sgirish nxge_status_t
nxge_rxbuf_pp_to_vp(p_nxge_t nxgep,p_rx_rbr_ring_t rbr_p,uint8_t pktbufsz_type,uint64_t * pkt_buf_addr_pp,uint64_t ** pkt_buf_addr_p,uint32_t * bufoffset,uint32_t * msg_index)69944961713Sgirish nxge_rxbuf_pp_to_vp(p_nxge_t nxgep, p_rx_rbr_ring_t rbr_p,
700*86ef0a63SRichard Lowe     uint8_t pktbufsz_type, uint64_t *pkt_buf_addr_pp,
701*86ef0a63SRichard Lowe     uint64_t **pkt_buf_addr_p, uint32_t *bufoffset, uint32_t *msg_index)
70244961713Sgirish {
70344961713Sgirish 	int			bufsize;
70444961713Sgirish 	uint64_t		pktbuf_pp;
705*86ef0a63SRichard Lowe 	uint64_t		dvma_addr;
706*86ef0a63SRichard Lowe 	rxring_info_t		*ring_info;
707*86ef0a63SRichard Lowe 	int			base_side, end_side;
708*86ef0a63SRichard Lowe 	int			r_index, l_index, anchor_index;
709*86ef0a63SRichard Lowe 	int			found, search_done;
71044961713Sgirish 	uint32_t offset, chunk_size, block_size, page_size_mask;
71144961713Sgirish 	uint32_t chunk_index, block_index, total_index;
712*86ef0a63SRichard Lowe 	int			max_iterations, iteration;
713*86ef0a63SRichard Lowe 	rxbuf_index_info_t	*bufinfo;
71444961713Sgirish 
71544961713Sgirish 	NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> nxge_rxbuf_pp_to_vp"));
71644961713Sgirish 
71744961713Sgirish 	NXGE_DEBUG_MSG((nxgep, RX2_CTL,
71852ccf843Smisaki 	    "==> nxge_rxbuf_pp_to_vp: buf_pp $%p btype %d",
71952ccf843Smisaki 	    pkt_buf_addr_pp,
72052ccf843Smisaki 	    pktbufsz_type));
72144961713Sgirish 	pktbuf_pp = (uint64_t)pkt_buf_addr_pp;
72244961713Sgirish 
72344961713Sgirish 	switch (pktbufsz_type) {
72444961713Sgirish 	case 0:
72544961713Sgirish 		bufsize = rbr_p->pkt_buf_size0;
72644961713Sgirish 		break;
72744961713Sgirish 	case 1:
72844961713Sgirish 		bufsize = rbr_p->pkt_buf_size1;
72944961713Sgirish 		break;
73044961713Sgirish 	case 2:
73144961713Sgirish 		bufsize = rbr_p->pkt_buf_size2;
73244961713Sgirish 		break;
73344961713Sgirish 	case RCR_SINGLE_BLOCK:
73444961713Sgirish 		bufsize = 0;
73544961713Sgirish 		anchor_index = 0;
73644961713Sgirish 		break;
73744961713Sgirish 	default:
73844961713Sgirish 		return (NXGE_ERROR);
73944961713Sgirish 	}
74044961713Sgirish 
74144961713Sgirish 	if (rbr_p->num_blocks == 1) {
74244961713Sgirish 		anchor_index = 0;
74344961713Sgirish 		ring_info = rbr_p->ring_info;
74444961713Sgirish 		bufinfo = (rxbuf_index_info_t *)ring_info->buffer;
74544961713Sgirish 		NXGE_DEBUG_MSG((nxgep, RX2_CTL,
74652ccf843Smisaki 		    "==> nxge_rxbuf_pp_to_vp: (found, 1 block) "
74752ccf843Smisaki 		    "buf_pp $%p btype %d anchor_index %d "
74852ccf843Smisaki 		    "bufinfo $%p",
74952ccf843Smisaki 		    pkt_buf_addr_pp,
75052ccf843Smisaki 		    pktbufsz_type,
75152ccf843Smisaki 		    anchor_index,
75252ccf843Smisaki 		    bufinfo));
75344961713Sgirish 
75444961713Sgirish 		goto found_index;
75544961713Sgirish 	}
75644961713Sgirish 
75744961713Sgirish 	NXGE_DEBUG_MSG((nxgep, RX2_CTL,
75852ccf843Smisaki 	    "==> nxge_rxbuf_pp_to_vp: "
75952ccf843Smisaki 	    "buf_pp $%p btype %d  anchor_index %d",
76052ccf843Smisaki 	    pkt_buf_addr_pp,
76152ccf843Smisaki 	    pktbufsz_type,
76252ccf843Smisaki 	    anchor_index));
76344961713Sgirish 
76444961713Sgirish 	ring_info = rbr_p->ring_info;
76544961713Sgirish 	found = B_FALSE;
76644961713Sgirish 	bufinfo = (rxbuf_index_info_t *)ring_info->buffer;
76744961713Sgirish 	iteration = 0;
76844961713Sgirish 	max_iterations = ring_info->max_iterations;
76944961713Sgirish 		/*
770a3c5bd6dSspeer 		 * First check if this block has been seen
77144961713Sgirish 		 * recently. This is indicated by a hint which
77244961713Sgirish 		 * is initialized when the first buffer of the block
77344961713Sgirish 		 * is seen. The hint is reset when the last buffer of
77444961713Sgirish 		 * the block has been processed.
77544961713Sgirish 		 * As three block sizes are supported, three hints
77644961713Sgirish 		 * are kept. The idea behind the hints is that once
777*86ef0a63SRichard Lowe 		 * the hardware	 uses a block for a buffer  of that
77844961713Sgirish 		 * size, it will use it exclusively for that size
77944961713Sgirish 		 * and will use it until it is exhausted. It is assumed
78044961713Sgirish 		 * that there would a single block being used for the same
78144961713Sgirish 		 * buffer sizes at any given time.
78244961713Sgirish 		 */
78344961713Sgirish 	if (ring_info->hint[pktbufsz_type] != NO_HINT) {
78444961713Sgirish 		anchor_index = ring_info->hint[pktbufsz_type];
78544961713Sgirish 		dvma_addr =  bufinfo[anchor_index].dvma_addr;
78644961713Sgirish 		chunk_size = bufinfo[anchor_index].buf_size;
78744961713Sgirish 		if ((pktbuf_pp >= dvma_addr) &&
78852ccf843Smisaki 		    (pktbuf_pp < (dvma_addr + chunk_size))) {
78944961713Sgirish 			found = B_TRUE;
79044961713Sgirish 				/*
79144961713Sgirish 				 * check if this is the last buffer in the block
79244961713Sgirish 				 * If so, then reset the hint for the size;
79344961713Sgirish 				 */
79444961713Sgirish 
79544961713Sgirish 			if ((pktbuf_pp + bufsize) >= (dvma_addr + chunk_size))
79644961713Sgirish 				ring_info->hint[pktbufsz_type] = NO_HINT;
79744961713Sgirish 		}
79844961713Sgirish 	}
79944961713Sgirish 
80044961713Sgirish 	if (found == B_FALSE) {
80144961713Sgirish 		NXGE_DEBUG_MSG((nxgep, RX2_CTL,
80252ccf843Smisaki 		    "==> nxge_rxbuf_pp_to_vp: (!found)"
80352ccf843Smisaki 		    "buf_pp $%p btype %d anchor_index %d",
80452ccf843Smisaki 		    pkt_buf_addr_pp,
80552ccf843Smisaki 		    pktbufsz_type,
80652ccf843Smisaki 		    anchor_index));
80744961713Sgirish 
80844961713Sgirish 			/*
80944961713Sgirish 			 * This is the first buffer of the block of this
81044961713Sgirish 			 * size. Need to search the whole information
81144961713Sgirish 			 * array.
81244961713Sgirish 			 * the search algorithm uses a binary tree search
81344961713Sgirish 			 * algorithm. It assumes that the information is
81444961713Sgirish 			 * already sorted with increasing order
815*86ef0a63SRichard Lowe 			 * info[0] < info[1] < info[2]	.... < info[n-1]
81644961713Sgirish 			 * where n is the size of the information array
81744961713Sgirish 			 */
81844961713Sgirish 		r_index = rbr_p->num_blocks - 1;
81944961713Sgirish 		l_index = 0;
82044961713Sgirish 		search_done = B_FALSE;
82144961713Sgirish 		anchor_index = MID_INDEX(r_index, l_index);
82244961713Sgirish 		while (search_done == B_FALSE) {
82344961713Sgirish 			if ((r_index == l_index) ||
82452ccf843Smisaki 			    (iteration >= max_iterations))
82544961713Sgirish 				search_done = B_TRUE;
82644961713Sgirish 			end_side = TO_RIGHT; /* to the right */
82744961713Sgirish 			base_side = TO_LEFT; /* to the left */
82844961713Sgirish 			/* read the DVMA address information and sort it */
82944961713Sgirish 			dvma_addr =  bufinfo[anchor_index].dvma_addr;
83044961713Sgirish 			chunk_size = bufinfo[anchor_index].buf_size;
83144961713Sgirish 			NXGE_DEBUG_MSG((nxgep, RX2_CTL,
83252ccf843Smisaki 			    "==> nxge_rxbuf_pp_to_vp: (searching)"
83352ccf843Smisaki 			    "buf_pp $%p btype %d "
83452ccf843Smisaki 			    "anchor_index %d chunk_size %d dvmaaddr $%p",
83552ccf843Smisaki 			    pkt_buf_addr_pp,
83652ccf843Smisaki 			    pktbufsz_type,
83752ccf843Smisaki 			    anchor_index,
83852ccf843Smisaki 			    chunk_size,
83952ccf843Smisaki 			    dvma_addr));
84044961713Sgirish 
84144961713Sgirish 			if (pktbuf_pp >= dvma_addr)
84244961713Sgirish 				base_side = TO_RIGHT; /* to the right */
84344961713Sgirish 			if (pktbuf_pp < (dvma_addr + chunk_size))
84444961713Sgirish 				end_side = TO_LEFT; /* to the left */
84544961713Sgirish 
84644961713Sgirish 			switch (base_side + end_side) {
84752ccf843Smisaki 			case IN_MIDDLE:
84852ccf843Smisaki 				/* found */
84952ccf843Smisaki 				found = B_TRUE;
85052ccf843Smisaki 				search_done = B_TRUE;
85152ccf843Smisaki 				if ((pktbuf_pp + bufsize) <
85252ccf843Smisaki 				    (dvma_addr + chunk_size))
85352ccf843Smisaki 					ring_info->hint[pktbufsz_type] =
85452ccf843Smisaki 					    bufinfo[anchor_index].buf_index;
85552ccf843Smisaki 				break;
85652ccf843Smisaki 			case BOTH_RIGHT:
85752ccf843Smisaki 				/* not found: go to the right */
85852ccf843Smisaki 				l_index = anchor_index + 1;
85952ccf843Smisaki 				anchor_index = MID_INDEX(r_index, l_index);
86052ccf843Smisaki 				break;
86152ccf843Smisaki 
86252ccf843Smisaki 			case BOTH_LEFT:
86352ccf843Smisaki 				/* not found: go to the left */
86452ccf843Smisaki 				r_index = anchor_index - 1;
86552ccf843Smisaki 				anchor_index = MID_INDEX(r_index, l_index);
86652ccf843Smisaki 				break;
86752ccf843Smisaki 			default: /* should not come here */
86852ccf843Smisaki 				return (NXGE_ERROR);
86944961713Sgirish 			}
87044961713Sgirish 			iteration++;
87144961713Sgirish 		}
87244961713Sgirish 
87344961713Sgirish 		NXGE_DEBUG_MSG((nxgep, RX2_CTL,
87452ccf843Smisaki 		    "==> nxge_rxbuf_pp_to_vp: (search done)"
87552ccf843Smisaki 		    "buf_pp $%p btype %d anchor_index %d",
87652ccf843Smisaki 		    pkt_buf_addr_pp,
87752ccf843Smisaki 		    pktbufsz_type,
87852ccf843Smisaki 		    anchor_index));
87944961713Sgirish 	}
88044961713Sgirish 
88144961713Sgirish 	if (found == B_FALSE) {
88244961713Sgirish 		NXGE_DEBUG_MSG((nxgep, RX2_CTL,
88352ccf843Smisaki 		    "==> nxge_rxbuf_pp_to_vp: (search failed)"
88452ccf843Smisaki 		    "buf_pp $%p btype %d anchor_index %d",
88552ccf843Smisaki 		    pkt_buf_addr_pp,
88652ccf843Smisaki 		    pktbufsz_type,
88752ccf843Smisaki 		    anchor_index));
88844961713Sgirish 		return (NXGE_ERROR);
88944961713Sgirish 	}
89044961713Sgirish 
89144961713Sgirish found_index:
89244961713Sgirish 	NXGE_DEBUG_MSG((nxgep, RX2_CTL,
89352ccf843Smisaki 	    "==> nxge_rxbuf_pp_to_vp: (FOUND1)"
89452ccf843Smisaki 	    "buf_pp $%p btype %d bufsize %d anchor_index %d",
89552ccf843Smisaki 	    pkt_buf_addr_pp,
89652ccf843Smisaki 	    pktbufsz_type,
89752ccf843Smisaki 	    bufsize,
89852ccf843Smisaki 	    anchor_index));
89944961713Sgirish 
90044961713Sgirish 	/* index of the first block in this chunk */
90144961713Sgirish 	chunk_index = bufinfo[anchor_index].start_index;
90244961713Sgirish 	dvma_addr =  bufinfo[anchor_index].dvma_addr;
90344961713Sgirish 	page_size_mask = ring_info->block_size_mask;
90444961713Sgirish 
90544961713Sgirish 	NXGE_DEBUG_MSG((nxgep, RX2_CTL,
90652ccf843Smisaki 	    "==> nxge_rxbuf_pp_to_vp: (FOUND3), get chunk)"
90752ccf843Smisaki 	    "buf_pp $%p btype %d bufsize %d "
90852ccf843Smisaki 	    "anchor_index %d chunk_index %d dvma $%p",
90952ccf843Smisaki 	    pkt_buf_addr_pp,
91052ccf843Smisaki 	    pktbufsz_type,
91152ccf843Smisaki 	    bufsize,
91252ccf843Smisaki 	    anchor_index,
91352ccf843Smisaki 	    chunk_index,
91452ccf843Smisaki 	    dvma_addr));
91544961713Sgirish 
91644961713Sgirish 	offset = pktbuf_pp - dvma_addr; /* offset within the chunk */
91744961713Sgirish 	block_size = rbr_p->block_size; /* System  block(page) size */
91844961713Sgirish 
91944961713Sgirish 	NXGE_DEBUG_MSG((nxgep, RX2_CTL,
92052ccf843Smisaki 	    "==> nxge_rxbuf_pp_to_vp: (FOUND4), get chunk)"
92152ccf843Smisaki 	    "buf_pp $%p btype %d bufsize %d "
92252ccf843Smisaki 	    "anchor_index %d chunk_index %d dvma $%p "
92352ccf843Smisaki 	    "offset %d block_size %d",
92452ccf843Smisaki 	    pkt_buf_addr_pp,
92552ccf843Smisaki 	    pktbufsz_type,
92652ccf843Smisaki 	    bufsize,
92752ccf843Smisaki 	    anchor_index,
92852ccf843Smisaki 	    chunk_index,
92952ccf843Smisaki 	    dvma_addr,
93052ccf843Smisaki 	    offset,
93152ccf843Smisaki 	    block_size));
93244961713Sgirish 
93344961713Sgirish 	NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> getting total index"));
93444961713Sgirish 
93544961713Sgirish 	block_index = (offset / block_size); /* index within chunk */
93644961713Sgirish 	total_index = chunk_index + block_index;
93744961713Sgirish 
93844961713Sgirish 
93944961713Sgirish 	NXGE_DEBUG_MSG((nxgep, RX2_CTL,
94052ccf843Smisaki 	    "==> nxge_rxbuf_pp_to_vp: "
94152ccf843Smisaki 	    "total_index %d dvma_addr $%p "
94252ccf843Smisaki 	    "offset %d block_size %d "
94352ccf843Smisaki 	    "block_index %d ",
94452ccf843Smisaki 	    total_index, dvma_addr,
94552ccf843Smisaki 	    offset, block_size,
94652ccf843Smisaki 	    block_index));
947adfcba55Sjoycey 	*pkt_buf_addr_p = (uint64_t *)((uint64_t)bufinfo[anchor_index].kaddr +
94852ccf843Smisaki 	    (uint64_t)offset);
94944961713Sgirish 
95044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, RX2_CTL,
95152ccf843Smisaki 	    "==> nxge_rxbuf_pp_to_vp: "
95252ccf843Smisaki 	    "total_index %d dvma_addr $%p "
95352ccf843Smisaki 	    "offset %d block_size %d "
95452ccf843Smisaki 	    "block_index %d "
95552ccf843Smisaki 	    "*pkt_buf_addr_p $%p",
95652ccf843Smisaki 	    total_index, dvma_addr,
95752ccf843Smisaki 	    offset, block_size,
95852ccf843Smisaki 	    block_index,
95952ccf843Smisaki 	    *pkt_buf_addr_p));
96044961713Sgirish 
96144961713Sgirish 
96244961713Sgirish 	*msg_index = total_index;
96344961713Sgirish 	*bufoffset =  (offset & page_size_mask);
96444961713Sgirish 
96544961713Sgirish 	NXGE_DEBUG_MSG((nxgep, RX2_CTL,
96652ccf843Smisaki 	    "==> nxge_rxbuf_pp_to_vp: get msg index: "
96752ccf843Smisaki 	    "msg_index %d bufoffset_index %d",
96852ccf843Smisaki 	    *msg_index,
96952ccf843Smisaki 	    *bufoffset));
97044961713Sgirish 
97144961713Sgirish 	NXGE_DEBUG_MSG((nxgep, RX2_CTL, "<== nxge_rxbuf_pp_to_vp"));
97244961713Sgirish 
97344961713Sgirish 	return (NXGE_OK);
97444961713Sgirish }
97544961713Sgirish 
97644961713Sgirish /*
97744961713Sgirish  * used by quick sort (qsort) function
97844961713Sgirish  * to perform comparison
97944961713Sgirish  */
98044961713Sgirish static int
nxge_sort_compare(const void * p1,const void * p2)98144961713Sgirish nxge_sort_compare(const void *p1, const void *p2)
98244961713Sgirish {
98344961713Sgirish 
98444961713Sgirish 	rxbuf_index_info_t *a, *b;
98544961713Sgirish 
98644961713Sgirish 	a = (rxbuf_index_info_t *)p1;
98744961713Sgirish 	b = (rxbuf_index_info_t *)p2;
98844961713Sgirish 
98944961713Sgirish 	if (a->dvma_addr > b->dvma_addr)
99044961713Sgirish 		return (1);
99144961713Sgirish 	if (a->dvma_addr < b->dvma_addr)
99244961713Sgirish 		return (-1);
99344961713Sgirish 	return (0);
99444961713Sgirish }
99544961713Sgirish 
99644961713Sgirish 
99744961713Sgirish 
99844961713Sgirish /*
99944961713Sgirish  * grabbed this sort implementation from common/syscall/avl.c
100044961713Sgirish  *
100144961713Sgirish  */
100244961713Sgirish /*
100344961713Sgirish  * Generic shellsort, from K&R (1st ed, p 58.), somewhat modified.
100444961713Sgirish  * v = Ptr to array/vector of objs
100544961713Sgirish  * n = # objs in the array
100644961713Sgirish  * s = size of each obj (must be multiples of a word size)
100744961713Sgirish  * f = ptr to function to compare two objs
100844961713Sgirish  *	returns (-1 = less than, 0 = equal, 1 = greater than
100944961713Sgirish  */
101044961713Sgirish void
nxge_ksort(caddr_t v,int n,int s,int (* f)())101144961713Sgirish nxge_ksort(caddr_t v, int n, int s, int (*f)())
101244961713Sgirish {
101344961713Sgirish 	int g, i, j, ii;
101444961713Sgirish 	unsigned int *p1, *p2;
101544961713Sgirish 	unsigned int tmp;
101644961713Sgirish 
101744961713Sgirish 	/* No work to do */
101844961713Sgirish 	if (v == NULL || n <= 1)
101944961713Sgirish 		return;
102044961713Sgirish 	/* Sanity check on arguments */
102144961713Sgirish 	ASSERT(((uintptr_t)v & 0x3) == 0 && (s & 0x3) == 0);
102244961713Sgirish 	ASSERT(s > 0);
102344961713Sgirish 
102444961713Sgirish 	for (g = n / 2; g > 0; g /= 2) {
102544961713Sgirish 		for (i = g; i < n; i++) {
102644961713Sgirish 			for (j = i - g; j >= 0 &&
102752ccf843Smisaki 			    (*f)(v + j * s, v + (j + g) * s) == 1;
102852ccf843Smisaki 			    j -= g) {
102944961713Sgirish 				p1 = (unsigned *)(v + j * s);
103044961713Sgirish 				p2 = (unsigned *)(v + (j + g) * s);
103144961713Sgirish 				for (ii = 0; ii < s / 4; ii++) {
103244961713Sgirish 					tmp = *p1;
103344961713Sgirish 					*p1++ = *p2;
103444961713Sgirish 					*p2++ = tmp;
103544961713Sgirish 				}
103644961713Sgirish 			}
103744961713Sgirish 		}
103844961713Sgirish 	}
103944961713Sgirish }
104044961713Sgirish 
104144961713Sgirish /*
104244961713Sgirish  * Initialize data structures required for rxdma
104344961713Sgirish  * buffer dvma->vmem address lookup
104444961713Sgirish  */
104544961713Sgirish /*ARGSUSED*/
104644961713Sgirish static nxge_status_t
nxge_rxbuf_index_info_init(p_nxge_t nxgep,p_rx_rbr_ring_t rbrp)104744961713Sgirish nxge_rxbuf_index_info_init(p_nxge_t nxgep, p_rx_rbr_ring_t rbrp)
104844961713Sgirish {
104944961713Sgirish 
105044961713Sgirish 	int index;
105144961713Sgirish 	rxring_info_t *ring_info;
105244961713Sgirish 	int max_iteration = 0, max_index = 0;
105344961713Sgirish 
105444961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_rxbuf_index_info_init"));
105544961713Sgirish 
105644961713Sgirish 	ring_info = rbrp->ring_info;
105744961713Sgirish 	ring_info->hint[0] = NO_HINT;
105844961713Sgirish 	ring_info->hint[1] = NO_HINT;
105944961713Sgirish 	ring_info->hint[2] = NO_HINT;
106044961713Sgirish 	max_index = rbrp->num_blocks;
106144961713Sgirish 
106244961713Sgirish 		/* read the DVMA address information and sort it */
106344961713Sgirish 		/* do init of the information array */
106444961713Sgirish 
106544961713Sgirish 
106644961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DMA2_CTL,
106752ccf843Smisaki 	    " nxge_rxbuf_index_info_init Sort ptrs"));
106844961713Sgirish 
106944961713Sgirish 		/* sort the array */
107044961713Sgirish 	nxge_ksort((void *)ring_info->buffer, max_index,
107152ccf843Smisaki 	    sizeof (rxbuf_index_info_t), nxge_sort_compare);
107244961713Sgirish 
107344961713Sgirish 
107444961713Sgirish 
107544961713Sgirish 	for (index = 0; index < max_index; index++) {
107644961713Sgirish 		NXGE_DEBUG_MSG((nxgep, DMA2_CTL,
107752ccf843Smisaki 		    " nxge_rxbuf_index_info_init: sorted chunk %d "
107852ccf843Smisaki 		    " ioaddr $%p kaddr $%p size %x",
107952ccf843Smisaki 		    index, ring_info->buffer[index].dvma_addr,
108052ccf843Smisaki 		    ring_info->buffer[index].kaddr,
108152ccf843Smisaki 		    ring_info->buffer[index].buf_size));
108244961713Sgirish 	}
108344961713Sgirish 
108444961713Sgirish 	max_iteration = 0;
108544961713Sgirish 	while (max_index >= (1ULL << max_iteration))
108644961713Sgirish 		max_iteration++;
108744961713Sgirish 	ring_info->max_iterations = max_iteration + 1;
108844961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DMA2_CTL,
108952ccf843Smisaki 	    " nxge_rxbuf_index_info_init Find max iter %d",
109052ccf843Smisaki 	    ring_info->max_iterations));
109144961713Sgirish 
109244961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxbuf_index_info_init"));
109344961713Sgirish 	return (NXGE_OK);
109444961713Sgirish }
109544961713Sgirish 
10960a8e077aSspeer /* ARGSUSED */
109744961713Sgirish void
nxge_dump_rcr_entry(p_nxge_t nxgep,p_rcr_entry_t entry_p)109844961713Sgirish nxge_dump_rcr_entry(p_nxge_t nxgep, p_rcr_entry_t entry_p)
109944961713Sgirish {
110044961713Sgirish #ifdef	NXGE_DEBUG
110144961713Sgirish 
110244961713Sgirish 	uint32_t bptr;
110344961713Sgirish 	uint64_t pp;
110444961713Sgirish 
110544961713Sgirish 	bptr = entry_p->bits.hdw.pkt_buf_addr;
110644961713Sgirish 
110744961713Sgirish 	NXGE_DEBUG_MSG((nxgep, RX_CTL,
110852ccf843Smisaki 	    "\trcr entry $%p "
110952ccf843Smisaki 	    "\trcr entry 0x%0llx "
111052ccf843Smisaki 	    "\trcr entry 0x%08x "
111152ccf843Smisaki 	    "\trcr entry 0x%08x "
111252ccf843Smisaki 	    "\tvalue 0x%0llx\n"
111352ccf843Smisaki 	    "\tmulti = %d\n"
111452ccf843Smisaki 	    "\tpkt_type = 0x%x\n"
111552ccf843Smisaki 	    "\tzero_copy = %d\n"
111652ccf843Smisaki 	    "\tnoport = %d\n"
111752ccf843Smisaki 	    "\tpromis = %d\n"
111852ccf843Smisaki 	    "\terror = 0x%04x\n"
111952ccf843Smisaki 	    "\tdcf_err = 0x%01x\n"
112052ccf843Smisaki 	    "\tl2_len = %d\n"
112152ccf843Smisaki 	    "\tpktbufsize = %d\n"
112252ccf843Smisaki 	    "\tpkt_buf_addr = $%p\n"
112352ccf843Smisaki 	    "\tpkt_buf_addr (<< 6) = $%p\n",
112452ccf843Smisaki 	    entry_p,
112552ccf843Smisaki 	    *(int64_t *)entry_p,
112652ccf843Smisaki 	    *(int32_t *)entry_p,
112752ccf843Smisaki 	    *(int32_t *)((char *)entry_p + 32),
112852ccf843Smisaki 	    entry_p->value,
112952ccf843Smisaki 	    entry_p->bits.hdw.multi,
113052ccf843Smisaki 	    entry_p->bits.hdw.pkt_type,
113152ccf843Smisaki 	    entry_p->bits.hdw.zero_copy,
113252ccf843Smisaki 	    entry_p->bits.hdw.noport,
113352ccf843Smisaki 	    entry_p->bits.hdw.promis,
113452ccf843Smisaki 	    entry_p->bits.hdw.error,
113552ccf843Smisaki 	    entry_p->bits.hdw.dcf_err,
113652ccf843Smisaki 	    entry_p->bits.hdw.l2_len,
113752ccf843Smisaki 	    entry_p->bits.hdw.pktbufsz,
113852ccf843Smisaki 	    bptr,
113952ccf843Smisaki 	    entry_p->bits.ldw.pkt_buf_addr));
114044961713Sgirish 
114144961713Sgirish 	pp = (entry_p->value & RCR_PKT_BUF_ADDR_MASK) <<
114252ccf843Smisaki 	    RCR_PKT_BUF_ADDR_SHIFT;
114344961713Sgirish 
114444961713Sgirish 	NXGE_DEBUG_MSG((nxgep, RX_CTL, "rcr pp 0x%llx l2 len %d",
114552ccf843Smisaki 	    pp, (*(int64_t *)entry_p >> 40) & 0x3fff));
114644961713Sgirish #endif
114744961713Sgirish }
114844961713Sgirish 
114944961713Sgirish void
nxge_rxdma_regs_dump(p_nxge_t nxgep,int rdc)115044961713Sgirish nxge_rxdma_regs_dump(p_nxge_t nxgep, int rdc)
115144961713Sgirish {
115244961713Sgirish 	npi_handle_t		handle;
1153*86ef0a63SRichard Lowe 	rbr_stat_t		rbr_stat;
1154*86ef0a63SRichard Lowe 	addr44_t		hd_addr;
1155*86ef0a63SRichard Lowe 	addr44_t		tail_addr;
1156*86ef0a63SRichard Lowe 	uint16_t		qlen;
115744961713Sgirish 
115844961713Sgirish 	NXGE_DEBUG_MSG((nxgep, RX_CTL,
115952ccf843Smisaki 	    "==> nxge_rxdma_regs_dump: rdc channel %d", rdc));
116044961713Sgirish 
116144961713Sgirish 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
116244961713Sgirish 
116344961713Sgirish 	/* RBR head */
116444961713Sgirish 	hd_addr.addr = 0;
116544961713Sgirish 	(void) npi_rxdma_rdc_rbr_head_get(handle, rdc, &hd_addr);
1166