1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/nxge/nxge_impl.h> 29 #include <sys/nxge/nxge_rxdma.h> 30 #include <sys/nxge/nxge_hio.h> 31 32 #if !defined(_BIG_ENDIAN) 33 #include <npi_rx_rd32.h> 34 #endif 35 #include <npi_rx_rd64.h> 36 #include <npi_rx_wr64.h> 37 38 #define NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp) \ 39 (rdcgrp + nxgep->pt_config.hw_config.def_mac_rxdma_grpid) 40 #define NXGE_ACTUAL_RDC(nxgep, rdc) \ 41 (rdc + nxgep->pt_config.hw_config.start_rdc) 42 43 /* 44 * Globals: tunable parameters (/etc/system or adb) 45 * 46 */ 47 extern uint32_t nxge_rbr_size; 48 extern uint32_t nxge_rcr_size; 49 extern uint32_t nxge_rbr_spare_size; 50 51 extern uint32_t nxge_mblks_pending; 52 53 /* 54 * Tunable to reduce the amount of time spent in the 55 * ISR doing Rx Processing. 56 */ 57 extern uint32_t nxge_max_rx_pkts; 58 boolean_t nxge_jumbo_enable; 59 60 /* 61 * Tunables to manage the receive buffer blocks. 62 * 63 * nxge_rx_threshold_hi: copy all buffers. 64 * nxge_rx_bcopy_size_type: receive buffer block size type. 65 * nxge_rx_threshold_lo: copy only up to tunable block size type. 66 */ 67 extern nxge_rxbuf_threshold_t nxge_rx_threshold_hi; 68 extern nxge_rxbuf_type_t nxge_rx_buf_size_type; 69 extern nxge_rxbuf_threshold_t nxge_rx_threshold_lo; 70 71 extern uint32_t nxge_cksum_offload; 72 73 static nxge_status_t nxge_map_rxdma(p_nxge_t, int); 74 static void nxge_unmap_rxdma(p_nxge_t, int); 75 76 static nxge_status_t nxge_rxdma_hw_start_common(p_nxge_t); 77 78 static nxge_status_t nxge_rxdma_hw_start(p_nxge_t, int); 79 static void nxge_rxdma_hw_stop(p_nxge_t, int); 80 81 static nxge_status_t nxge_map_rxdma_channel(p_nxge_t, uint16_t, 82 p_nxge_dma_common_t *, p_rx_rbr_ring_t *, 83 uint32_t, 84 p_nxge_dma_common_t *, p_rx_rcr_ring_t *, 85 p_rx_mbox_t *); 86 static void nxge_unmap_rxdma_channel(p_nxge_t, uint16_t, 87 p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t); 88 89 static nxge_status_t nxge_map_rxdma_channel_cfg_ring(p_nxge_t, 90 uint16_t, 91 p_nxge_dma_common_t *, p_rx_rbr_ring_t *, 92 p_rx_rcr_ring_t *, p_rx_mbox_t *); 93 static void nxge_unmap_rxdma_channel_cfg_ring(p_nxge_t, 94 p_rx_rcr_ring_t, p_rx_mbox_t); 95 96 static nxge_status_t nxge_map_rxdma_channel_buf_ring(p_nxge_t, 97 uint16_t, 98 p_nxge_dma_common_t *, 99 p_rx_rbr_ring_t *, uint32_t); 100 static void nxge_unmap_rxdma_channel_buf_ring(p_nxge_t, 101 p_rx_rbr_ring_t); 102 103 static nxge_status_t nxge_rxdma_start_channel(p_nxge_t, uint16_t, 104 p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t); 105 static nxge_status_t nxge_rxdma_stop_channel(p_nxge_t, uint16_t); 106 107 static mblk_t * 108 nxge_rx_pkts(p_nxge_t, p_rx_rcr_ring_t, rx_dma_ctl_stat_t, int); 109 110 static void nxge_receive_packet(p_nxge_t, 111 p_rx_rcr_ring_t, 112 p_rcr_entry_t, 113 boolean_t *, 114 mblk_t **, mblk_t **); 115 116 nxge_status_t nxge_disable_rxdma_channel(p_nxge_t, uint16_t); 117 118 static p_rx_msg_t nxge_allocb(size_t, uint32_t, p_nxge_dma_common_t); 119 static void nxge_freeb(p_rx_msg_t); 120 static void nxge_rx_pkts_vring(p_nxge_t, uint_t, rx_dma_ctl_stat_t); 121 static nxge_status_t nxge_rx_err_evnts(p_nxge_t, int, rx_dma_ctl_stat_t); 122 123 static nxge_status_t nxge_rxdma_handle_port_errors(p_nxge_t, 124 uint32_t, uint32_t); 125 126 static nxge_status_t nxge_rxbuf_index_info_init(p_nxge_t, 127 p_rx_rbr_ring_t); 128 129 130 static nxge_status_t 131 nxge_rxdma_fatal_err_recover(p_nxge_t, uint16_t); 132 133 nxge_status_t 134 nxge_rx_port_fatal_err_recover(p_nxge_t); 135 136 static void nxge_rxdma_databuf_free(p_rx_rbr_ring_t); 137 138 nxge_status_t 139 nxge_init_rxdma_channels(p_nxge_t nxgep) 140 { 141 nxge_grp_set_t *set = &nxgep->rx_set; 142 int i, count; 143 144 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_init_rxdma_channels")); 145 146 if (!isLDOMguest(nxgep)) { 147 if (nxge_rxdma_hw_start_common(nxgep) != NXGE_OK) { 148 cmn_err(CE_NOTE, "hw_start_common"); 149 return (NXGE_ERROR); 150 } 151 } 152 153 /* 154 * NXGE_LOGICAL_GROUP_MAX > NXGE_MAX_RDC_GROUPS (8) 155 * We only have 8 hardware RDC tables, but we may have 156 * up to 16 logical (software-defined) groups of RDCS, 157 * if we make use of layer 3 & 4 hardware classification. 158 */ 159 for (i = 0, count = 0; i < NXGE_LOGICAL_GROUP_MAX; i++) { 160 if ((1 << i) & set->lg.map) { 161 int channel; 162 nxge_grp_t *group = set->group[i]; 163 for (channel = 0; channel < NXGE_MAX_RDCS; channel++) { 164 if ((1 << channel) & group->map) { 165 if ((nxge_grp_dc_add(nxgep, 166 (vr_handle_t)group, 167 VP_BOUND_RX, channel))) 168 return (NXGE_ERROR); 169 } 170 } 171 } 172 if (++count == set->lg.count) 173 break; 174 } 175 176 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_init_rxdma_channels")); 177 178 return (NXGE_OK); 179 } 180 181 nxge_status_t 182 nxge_init_rxdma_channel(p_nxge_t nxge, int channel) 183 { 184 nxge_status_t status; 185 186 NXGE_DEBUG_MSG((nxge, MEM2_CTL, "==> nxge_init_rxdma_channel")); 187 188 status = nxge_map_rxdma(nxge, channel); 189 if (status != NXGE_OK) { 190 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 191 "<== nxge_init_rxdma: status 0x%x", status)); 192 return (status); 193 } 194 195 status = nxge_rxdma_hw_start(nxge, channel); 196 if (status != NXGE_OK) { 197 nxge_unmap_rxdma(nxge, channel); 198 } 199 200 if (!nxge->statsp->rdc_ksp[channel]) 201 nxge_setup_rdc_kstats(nxge, channel); 202 203 NXGE_DEBUG_MSG((nxge, MEM2_CTL, 204 "<== nxge_init_rxdma_channel: status 0x%x", status)); 205 206 return (status); 207 } 208 209 void 210 nxge_uninit_rxdma_channels(p_nxge_t nxgep) 211 { 212 nxge_grp_set_t *set = &nxgep->rx_set; 213 int rdc; 214 215 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_uninit_rxdma_channels")); 216 217 if (set->owned.map == 0) { 218 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 219 "nxge_uninit_rxdma_channels: no channels")); 220 return; 221 } 222 223 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 224 if ((1 << rdc) & set->owned.map) { 225 nxge_grp_dc_remove(nxgep, VP_BOUND_RX, rdc); 226 } 227 } 228 229 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_uninit_rxdma_channels")); 230 } 231 232 void 233 nxge_uninit_rxdma_channel(p_nxge_t nxgep, int channel) 234 { 235 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_uninit_rxdma_channel")); 236 237 if (nxgep->statsp->rdc_ksp[channel]) { 238 kstat_delete(nxgep->statsp->rdc_ksp[channel]); 239 nxgep->statsp->rdc_ksp[channel] = 0; 240 } 241 242 nxge_rxdma_hw_stop(nxgep, channel); 243 nxge_unmap_rxdma(nxgep, channel); 244 245 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_uinit_rxdma_channel")); 246 } 247 248 nxge_status_t 249 nxge_reset_rxdma_channel(p_nxge_t nxgep, uint16_t channel) 250 { 251 npi_handle_t handle; 252 npi_status_t rs = NPI_SUCCESS; 253 nxge_status_t status = NXGE_OK; 254 255 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_reset_rxdma_channel")); 256 257 handle = NXGE_DEV_NPI_HANDLE(nxgep); 258 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 259 260 if (rs != NPI_SUCCESS) { 261 status = NXGE_ERROR | rs; 262 } 263 264 return (status); 265 } 266 267 void 268 nxge_rxdma_regs_dump_channels(p_nxge_t nxgep) 269 { 270 nxge_grp_set_t *set = &nxgep->rx_set; 271 int rdc; 272 273 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_regs_dump_channels")); 274 275 if (!isLDOMguest(nxgep)) { 276 npi_handle_t handle = NXGE_DEV_NPI_HANDLE(nxgep); 277 (void) npi_rxdma_dump_fzc_regs(handle); 278 } 279 280 if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) { 281 NXGE_DEBUG_MSG((nxgep, TX_CTL, 282 "nxge_rxdma_regs_dump_channels: " 283 "NULL ring pointer(s)")); 284 return; 285 } 286 287 if (set->owned.map == 0) { 288 NXGE_DEBUG_MSG((nxgep, RX_CTL, 289 "nxge_rxdma_regs_dump_channels: no channels")); 290 return; 291 } 292 293 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 294 if ((1 << rdc) & set->owned.map) { 295 rx_rbr_ring_t *ring = 296 nxgep->rx_rbr_rings->rbr_rings[rdc]; 297 if (ring) { 298 (void) nxge_dump_rxdma_channel(nxgep, rdc); 299 } 300 } 301 } 302 303 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_regs_dump")); 304 } 305 306 nxge_status_t 307 nxge_dump_rxdma_channel(p_nxge_t nxgep, uint8_t channel) 308 { 309 npi_handle_t handle; 310 npi_status_t rs = NPI_SUCCESS; 311 nxge_status_t status = NXGE_OK; 312 313 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_dump_rxdma_channel")); 314 315 handle = NXGE_DEV_NPI_HANDLE(nxgep); 316 rs = npi_rxdma_dump_rdc_regs(handle, channel); 317 318 if (rs != NPI_SUCCESS) { 319 status = NXGE_ERROR | rs; 320 } 321 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_dump_rxdma_channel")); 322 return (status); 323 } 324 325 nxge_status_t 326 nxge_init_rxdma_channel_event_mask(p_nxge_t nxgep, uint16_t channel, 327 p_rx_dma_ent_msk_t mask_p) 328 { 329 npi_handle_t handle; 330 npi_status_t rs = NPI_SUCCESS; 331 nxge_status_t status = NXGE_OK; 332 333 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 334 "<== nxge_init_rxdma_channel_event_mask")); 335 336 handle = NXGE_DEV_NPI_HANDLE(nxgep); 337 rs = npi_rxdma_event_mask(handle, OP_SET, channel, mask_p); 338 if (rs != NPI_SUCCESS) { 339 status = NXGE_ERROR | rs; 340 } 341 342 return (status); 343 } 344 345 nxge_status_t 346 nxge_init_rxdma_channel_cntl_stat(p_nxge_t nxgep, uint16_t channel, 347 p_rx_dma_ctl_stat_t cs_p) 348 { 349 npi_handle_t handle; 350 npi_status_t rs = NPI_SUCCESS; 351 nxge_status_t status = NXGE_OK; 352 353 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 354 "<== nxge_init_rxdma_channel_cntl_stat")); 355 356 handle = NXGE_DEV_NPI_HANDLE(nxgep); 357 rs = npi_rxdma_control_status(handle, OP_SET, channel, cs_p); 358 359 if (rs != NPI_SUCCESS) { 360 status = NXGE_ERROR | rs; 361 } 362 363 return (status); 364 } 365 366 /* 367 * nxge_rxdma_cfg_rdcgrp_default_rdc 368 * 369 * Set the default RDC for an RDC Group (Table) 370 * 371 * Arguments: 372 * nxgep 373 * rdcgrp The group to modify 374 * rdc The new default RDC. 375 * 376 * Notes: 377 * 378 * NPI/NXGE function calls: 379 * npi_rxdma_cfg_rdc_table_default_rdc() 380 * 381 * Registers accessed: 382 * RDC_TBL_REG: FZC_ZCP + 0x10000 383 * 384 * Context: 385 * Service domain 386 */ 387 nxge_status_t 388 nxge_rxdma_cfg_rdcgrp_default_rdc( 389 p_nxge_t nxgep, 390 uint8_t rdcgrp, 391 uint8_t rdc) 392 { 393 npi_handle_t handle; 394 npi_status_t rs = NPI_SUCCESS; 395 p_nxge_dma_pt_cfg_t p_dma_cfgp; 396 p_nxge_rdc_grp_t rdc_grp_p; 397 uint8_t actual_rdcgrp, actual_rdc; 398 399 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 400 " ==> nxge_rxdma_cfg_rdcgrp_default_rdc")); 401 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 402 403 handle = NXGE_DEV_NPI_HANDLE(nxgep); 404 405 /* 406 * This has to be rewritten. Do we even allow this anymore? 407 */ 408 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdcgrp]; 409 RDC_MAP_IN(rdc_grp_p->map, rdc); 410 rdc_grp_p->def_rdc = rdc; 411 412 actual_rdcgrp = NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp); 413 actual_rdc = NXGE_ACTUAL_RDC(nxgep, rdc); 414 415 rs = npi_rxdma_cfg_rdc_table_default_rdc( 416 handle, actual_rdcgrp, actual_rdc); 417 418 if (rs != NPI_SUCCESS) { 419 return (NXGE_ERROR | rs); 420 } 421 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 422 " <== nxge_rxdma_cfg_rdcgrp_default_rdc")); 423 return (NXGE_OK); 424 } 425 426 nxge_status_t 427 nxge_rxdma_cfg_port_default_rdc(p_nxge_t nxgep, uint8_t port, uint8_t rdc) 428 { 429 npi_handle_t handle; 430 431 uint8_t actual_rdc; 432 npi_status_t rs = NPI_SUCCESS; 433 434 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 435 " ==> nxge_rxdma_cfg_port_default_rdc")); 436 437 handle = NXGE_DEV_NPI_HANDLE(nxgep); 438 actual_rdc = rdc; /* XXX Hack! */ 439 rs = npi_rxdma_cfg_default_port_rdc(handle, port, actual_rdc); 440 441 442 if (rs != NPI_SUCCESS) { 443 return (NXGE_ERROR | rs); 444 } 445 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 446 " <== nxge_rxdma_cfg_port_default_rdc")); 447 448 return (NXGE_OK); 449 } 450 451 nxge_status_t 452 nxge_rxdma_cfg_rcr_threshold(p_nxge_t nxgep, uint8_t channel, 453 uint16_t pkts) 454 { 455 npi_status_t rs = NPI_SUCCESS; 456 npi_handle_t handle; 457 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 458 " ==> nxge_rxdma_cfg_rcr_threshold")); 459 handle = NXGE_DEV_NPI_HANDLE(nxgep); 460 461 rs = npi_rxdma_cfg_rdc_rcr_threshold(handle, channel, pkts); 462 463 if (rs != NPI_SUCCESS) { 464 return (NXGE_ERROR | rs); 465 } 466 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_threshold")); 467 return (NXGE_OK); 468 } 469 470 nxge_status_t 471 nxge_rxdma_cfg_rcr_timeout(p_nxge_t nxgep, uint8_t channel, 472 uint16_t tout, uint8_t enable) 473 { 474 npi_status_t rs = NPI_SUCCESS; 475 npi_handle_t handle; 476 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " ==> nxge_rxdma_cfg_rcr_timeout")); 477 handle = NXGE_DEV_NPI_HANDLE(nxgep); 478 if (enable == 0) { 479 rs = npi_rxdma_cfg_rdc_rcr_timeout_disable(handle, channel); 480 } else { 481 rs = npi_rxdma_cfg_rdc_rcr_timeout(handle, channel, 482 tout); 483 } 484 485 if (rs != NPI_SUCCESS) { 486 return (NXGE_ERROR | rs); 487 } 488 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_timeout")); 489 return (NXGE_OK); 490 } 491 492 nxge_status_t 493 nxge_enable_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 494 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p) 495 { 496 npi_handle_t handle; 497 rdc_desc_cfg_t rdc_desc; 498 p_rcrcfig_b_t cfgb_p; 499 npi_status_t rs = NPI_SUCCESS; 500 501 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel")); 502 handle = NXGE_DEV_NPI_HANDLE(nxgep); 503 /* 504 * Use configuration data composed at init time. 505 * Write to hardware the receive ring configurations. 506 */ 507 rdc_desc.mbox_enable = 1; 508 rdc_desc.mbox_addr = mbox_p->mbox_addr; 509 NXGE_DEBUG_MSG((nxgep, RX_CTL, 510 "==> nxge_enable_rxdma_channel: mboxp $%p($%p)", 511 mbox_p->mbox_addr, rdc_desc.mbox_addr)); 512 513 rdc_desc.rbr_len = rbr_p->rbb_max; 514 rdc_desc.rbr_addr = rbr_p->rbr_addr; 515 516 switch (nxgep->rx_bksize_code) { 517 case RBR_BKSIZE_4K: 518 rdc_desc.page_size = SIZE_4KB; 519 break; 520 case RBR_BKSIZE_8K: 521 rdc_desc.page_size = SIZE_8KB; 522 break; 523 case RBR_BKSIZE_16K: 524 rdc_desc.page_size = SIZE_16KB; 525 break; 526 case RBR_BKSIZE_32K: 527 rdc_desc.page_size = SIZE_32KB; 528 break; 529 } 530 531 rdc_desc.size0 = rbr_p->npi_pkt_buf_size0; 532 rdc_desc.valid0 = 1; 533 534 rdc_desc.size1 = rbr_p->npi_pkt_buf_size1; 535 rdc_desc.valid1 = 1; 536 537 rdc_desc.size2 = rbr_p->npi_pkt_buf_size2; 538 rdc_desc.valid2 = 1; 539 540 rdc_desc.full_hdr = rcr_p->full_hdr_flag; 541 rdc_desc.offset = rcr_p->sw_priv_hdr_len; 542 543 rdc_desc.rcr_len = rcr_p->comp_size; 544 rdc_desc.rcr_addr = rcr_p->rcr_addr; 545 546 cfgb_p = &(rcr_p->rcr_cfgb); 547 rdc_desc.rcr_threshold = cfgb_p->bits.ldw.pthres; 548 /* For now, disable this timeout in a guest domain. */ 549 if (isLDOMguest(nxgep)) { 550 rdc_desc.rcr_timeout = 0; 551 rdc_desc.rcr_timeout_enable = 0; 552 } else { 553 rdc_desc.rcr_timeout = cfgb_p->bits.ldw.timeout; 554 rdc_desc.rcr_timeout_enable = cfgb_p->bits.ldw.entout; 555 } 556 557 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: " 558 "rbr_len qlen %d pagesize code %d rcr_len %d", 559 rdc_desc.rbr_len, rdc_desc.page_size, rdc_desc.rcr_len)); 560 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: " 561 "size 0 %d size 1 %d size 2 %d", 562 rbr_p->npi_pkt_buf_size0, rbr_p->npi_pkt_buf_size1, 563 rbr_p->npi_pkt_buf_size2)); 564 565 rs = npi_rxdma_cfg_rdc_ring(handle, rbr_p->rdc, &rdc_desc); 566 if (rs != NPI_SUCCESS) { 567 return (NXGE_ERROR | rs); 568 } 569 570 /* 571 * Enable the timeout and threshold. 572 */ 573 rs = npi_rxdma_cfg_rdc_rcr_threshold(handle, channel, 574 rdc_desc.rcr_threshold); 575 if (rs != NPI_SUCCESS) { 576 return (NXGE_ERROR | rs); 577 } 578 579 rs = npi_rxdma_cfg_rdc_rcr_timeout(handle, channel, 580 rdc_desc.rcr_timeout); 581 if (rs != NPI_SUCCESS) { 582 return (NXGE_ERROR | rs); 583 } 584 585 /* Enable the DMA */ 586 rs = npi_rxdma_cfg_rdc_enable(handle, channel); 587 if (rs != NPI_SUCCESS) { 588 return (NXGE_ERROR | rs); 589 } 590 591 /* Kick the DMA engine. */ 592 npi_rxdma_rdc_rbr_kick(handle, channel, rbr_p->rbb_max); 593 /* Clear the rbr empty bit */ 594 (void) npi_rxdma_channel_rbr_empty_clear(handle, channel); 595 596 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_enable_rxdma_channel")); 597 598 return (NXGE_OK); 599 } 600 601 nxge_status_t 602 nxge_disable_rxdma_channel(p_nxge_t nxgep, uint16_t channel) 603 { 604 npi_handle_t handle; 605 npi_status_t rs = NPI_SUCCESS; 606 607 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_disable_rxdma_channel")); 608 handle = NXGE_DEV_NPI_HANDLE(nxgep); 609 610 /* disable the DMA */ 611 rs = npi_rxdma_cfg_rdc_disable(handle, channel); 612 if (rs != NPI_SUCCESS) { 613 NXGE_DEBUG_MSG((nxgep, RX_CTL, 614 "<== nxge_disable_rxdma_channel:failed (0x%x)", 615 rs)); 616 return (NXGE_ERROR | rs); 617 } 618 619 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_disable_rxdma_channel")); 620 return (NXGE_OK); 621 } 622 623 nxge_status_t 624 nxge_rxdma_channel_rcrflush(p_nxge_t nxgep, uint8_t channel) 625 { 626 npi_handle_t handle; 627 nxge_status_t status = NXGE_OK; 628 629 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 630 "<== nxge_init_rxdma_channel_rcrflush")); 631 632 handle = NXGE_DEV_NPI_HANDLE(nxgep); 633 npi_rxdma_rdc_rcr_flush(handle, channel); 634 635 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 636 "<== nxge_init_rxdma_channel_rcrflsh")); 637 return (status); 638 639 } 640 641 #define MID_INDEX(l, r) ((r + l + 1) >> 1) 642 643 #define TO_LEFT -1 644 #define TO_RIGHT 1 645 #define BOTH_RIGHT (TO_RIGHT + TO_RIGHT) 646 #define BOTH_LEFT (TO_LEFT + TO_LEFT) 647 #define IN_MIDDLE (TO_RIGHT + TO_LEFT) 648 #define NO_HINT 0xffffffff 649 650 /*ARGSUSED*/ 651 nxge_status_t 652 nxge_rxbuf_pp_to_vp(p_nxge_t nxgep, p_rx_rbr_ring_t rbr_p, 653 uint8_t pktbufsz_type, uint64_t *pkt_buf_addr_pp, 654 uint64_t **pkt_buf_addr_p, uint32_t *bufoffset, uint32_t *msg_index) 655 { 656 int bufsize; 657 uint64_t pktbuf_pp; 658 uint64_t dvma_addr; 659 rxring_info_t *ring_info; 660 int base_side, end_side; 661 int r_index, l_index, anchor_index; 662 int found, search_done; 663 uint32_t offset, chunk_size, block_size, page_size_mask; 664 uint32_t chunk_index, block_index, total_index; 665 int max_iterations, iteration; 666 rxbuf_index_info_t *bufinfo; 667 668 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> nxge_rxbuf_pp_to_vp")); 669 670 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 671 "==> nxge_rxbuf_pp_to_vp: buf_pp $%p btype %d", 672 pkt_buf_addr_pp, 673 pktbufsz_type)); 674 #if defined(__i386) 675 pktbuf_pp = (uint64_t)(uint32_t)pkt_buf_addr_pp; 676 #else 677 pktbuf_pp = (uint64_t)pkt_buf_addr_pp; 678 #endif 679 680 switch (pktbufsz_type) { 681 case 0: 682 bufsize = rbr_p->pkt_buf_size0; 683 break; 684 case 1: 685 bufsize = rbr_p->pkt_buf_size1; 686 break; 687 case 2: 688 bufsize = rbr_p->pkt_buf_size2; 689 break; 690 case RCR_SINGLE_BLOCK: 691 bufsize = 0; 692 anchor_index = 0; 693 break; 694 default: 695 return (NXGE_ERROR); 696 } 697 698 if (rbr_p->num_blocks == 1) { 699 anchor_index = 0; 700 ring_info = rbr_p->ring_info; 701 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 702 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 703 "==> nxge_rxbuf_pp_to_vp: (found, 1 block) " 704 "buf_pp $%p btype %d anchor_index %d " 705 "bufinfo $%p", 706 pkt_buf_addr_pp, 707 pktbufsz_type, 708 anchor_index, 709 bufinfo)); 710 711 goto found_index; 712 } 713 714 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 715 "==> nxge_rxbuf_pp_to_vp: " 716 "buf_pp $%p btype %d anchor_index %d", 717 pkt_buf_addr_pp, 718 pktbufsz_type, 719 anchor_index)); 720 721 ring_info = rbr_p->ring_info; 722 found = B_FALSE; 723 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 724 iteration = 0; 725 max_iterations = ring_info->max_iterations; 726 /* 727 * First check if this block has been seen 728 * recently. This is indicated by a hint which 729 * is initialized when the first buffer of the block 730 * is seen. The hint is reset when the last buffer of 731 * the block has been processed. 732 * As three block sizes are supported, three hints 733 * are kept. The idea behind the hints is that once 734 * the hardware uses a block for a buffer of that 735 * size, it will use it exclusively for that size 736 * and will use it until it is exhausted. It is assumed 737 * that there would a single block being used for the same 738 * buffer sizes at any given time. 739 */ 740 if (ring_info->hint[pktbufsz_type] != NO_HINT) { 741 anchor_index = ring_info->hint[pktbufsz_type]; 742 dvma_addr = bufinfo[anchor_index].dvma_addr; 743 chunk_size = bufinfo[anchor_index].buf_size; 744 if ((pktbuf_pp >= dvma_addr) && 745 (pktbuf_pp < (dvma_addr + chunk_size))) { 746 found = B_TRUE; 747 /* 748 * check if this is the last buffer in the block 749 * If so, then reset the hint for the size; 750 */ 751 752 if ((pktbuf_pp + bufsize) >= (dvma_addr + chunk_size)) 753 ring_info->hint[pktbufsz_type] = NO_HINT; 754 } 755 } 756 757 if (found == B_FALSE) { 758 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 759 "==> nxge_rxbuf_pp_to_vp: (!found)" 760 "buf_pp $%p btype %d anchor_index %d", 761 pkt_buf_addr_pp, 762 pktbufsz_type, 763 anchor_index)); 764 765 /* 766 * This is the first buffer of the block of this 767 * size. Need to search the whole information 768 * array. 769 * the search algorithm uses a binary tree search 770 * algorithm. It assumes that the information is 771 * already sorted with increasing order 772 * info[0] < info[1] < info[2] .... < info[n-1] 773 * where n is the size of the information array 774 */ 775 r_index = rbr_p->num_blocks - 1; 776 l_index = 0; 777 search_done = B_FALSE; 778 anchor_index = MID_INDEX(r_index, l_index); 779 while (search_done == B_FALSE) { 780 if ((r_index == l_index) || 781 (iteration >= max_iterations)) 782 search_done = B_TRUE; 783 end_side = TO_RIGHT; /* to the right */ 784 base_side = TO_LEFT; /* to the left */ 785 /* read the DVMA address information and sort it */ 786 dvma_addr = bufinfo[anchor_index].dvma_addr; 787 chunk_size = bufinfo[anchor_index].buf_size; 788 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 789 "==> nxge_rxbuf_pp_to_vp: (searching)" 790 "buf_pp $%p btype %d " 791 "anchor_index %d chunk_size %d dvmaaddr $%p", 792 pkt_buf_addr_pp, 793 pktbufsz_type, 794 anchor_index, 795 chunk_size, 796 dvma_addr)); 797 798 if (pktbuf_pp >= dvma_addr) 799 base_side = TO_RIGHT; /* to the right */ 800 if (pktbuf_pp < (dvma_addr + chunk_size)) 801 end_side = TO_LEFT; /* to the left */ 802 803 switch (base_side + end_side) { 804 case IN_MIDDLE: 805 /* found */ 806 found = B_TRUE; 807 search_done = B_TRUE; 808 if ((pktbuf_pp + bufsize) < 809 (dvma_addr + chunk_size)) 810 ring_info->hint[pktbufsz_type] = 811 bufinfo[anchor_index].buf_index; 812 break; 813 case BOTH_RIGHT: 814 /* not found: go to the right */ 815 l_index = anchor_index + 1; 816 anchor_index = MID_INDEX(r_index, l_index); 817 break; 818 819 case BOTH_LEFT: 820 /* not found: go to the left */ 821 r_index = anchor_index - 1; 822 anchor_index = MID_INDEX(r_index, l_index); 823 break; 824 default: /* should not come here */ 825 return (NXGE_ERROR); 826 } 827 iteration++; 828 } 829 830 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 831 "==> nxge_rxbuf_pp_to_vp: (search done)" 832 "buf_pp $%p btype %d anchor_index %d", 833 pkt_buf_addr_pp, 834 pktbufsz_type, 835 anchor_index)); 836 } 837 838 if (found == B_FALSE) { 839 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 840 "==> nxge_rxbuf_pp_to_vp: (search failed)" 841 "buf_pp $%p btype %d anchor_index %d", 842 pkt_buf_addr_pp, 843 pktbufsz_type, 844 anchor_index)); 845 return (NXGE_ERROR); 846 } 847 848 found_index: 849 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 850 "==> nxge_rxbuf_pp_to_vp: (FOUND1)" 851 "buf_pp $%p btype %d bufsize %d anchor_index %d", 852 pkt_buf_addr_pp, 853 pktbufsz_type, 854 bufsize, 855 anchor_index)); 856 857 /* index of the first block in this chunk */ 858 chunk_index = bufinfo[anchor_index].start_index; 859 dvma_addr = bufinfo[anchor_index].dvma_addr; 860 page_size_mask = ring_info->block_size_mask; 861 862 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 863 "==> nxge_rxbuf_pp_to_vp: (FOUND3), get chunk)" 864 "buf_pp $%p btype %d bufsize %d " 865 "anchor_index %d chunk_index %d dvma $%p", 866 pkt_buf_addr_pp, 867 pktbufsz_type, 868 bufsize, 869 anchor_index, 870 chunk_index, 871 dvma_addr)); 872 873 offset = pktbuf_pp - dvma_addr; /* offset within the chunk */ 874 block_size = rbr_p->block_size; /* System block(page) size */ 875 876 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 877 "==> nxge_rxbuf_pp_to_vp: (FOUND4), get chunk)" 878 "buf_pp $%p btype %d bufsize %d " 879 "anchor_index %d chunk_index %d dvma $%p " 880 "offset %d block_size %d", 881 pkt_buf_addr_pp, 882 pktbufsz_type, 883 bufsize, 884 anchor_index, 885 chunk_index, 886 dvma_addr, 887 offset, 888 block_size)); 889 890 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> getting total index")); 891 892 block_index = (offset / block_size); /* index within chunk */ 893 total_index = chunk_index + block_index; 894 895 896 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 897 "==> nxge_rxbuf_pp_to_vp: " 898 "total_index %d dvma_addr $%p " 899 "offset %d block_size %d " 900 "block_index %d ", 901 total_index, dvma_addr, 902 offset, block_size, 903 block_index)); 904 #if defined(__i386) 905 *pkt_buf_addr_p = (uint64_t *)((uint32_t)bufinfo[anchor_index].kaddr + 906 (uint32_t)offset); 907 #else 908 *pkt_buf_addr_p = (uint64_t *)((uint64_t)bufinfo[anchor_index].kaddr + 909 (uint64_t)offset); 910 #endif 911 912 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 913 "==> nxge_rxbuf_pp_to_vp: " 914 "total_index %d dvma_addr $%p " 915 "offset %d block_size %d " 916 "block_index %d " 917 "*pkt_buf_addr_p $%p", 918 total_index, dvma_addr, 919 offset, block_size, 920 block_index, 921 *pkt_buf_addr_p)); 922 923 924 *msg_index = total_index; 925 *bufoffset = (offset & page_size_mask); 926 927 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 928 "==> nxge_rxbuf_pp_to_vp: get msg index: " 929 "msg_index %d bufoffset_index %d", 930 *msg_index, 931 *bufoffset)); 932 933 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "<== nxge_rxbuf_pp_to_vp")); 934 935 return (NXGE_OK); 936 } 937 938 /* 939 * used by quick sort (qsort) function 940 * to perform comparison 941 */ 942 static int 943 nxge_sort_compare(const void *p1, const void *p2) 944 { 945 946 rxbuf_index_info_t *a, *b; 947 948 a = (rxbuf_index_info_t *)p1; 949 b = (rxbuf_index_info_t *)p2; 950 951 if (a->dvma_addr > b->dvma_addr) 952 return (1); 953 if (a->dvma_addr < b->dvma_addr) 954 return (-1); 955 return (0); 956 } 957 958 959 960 /* 961 * grabbed this sort implementation from common/syscall/avl.c 962 * 963 */ 964 /* 965 * Generic shellsort, from K&R (1st ed, p 58.), somewhat modified. 966 * v = Ptr to array/vector of objs 967 * n = # objs in the array 968 * s = size of each obj (must be multiples of a word size) 969 * f = ptr to function to compare two objs 970 * returns (-1 = less than, 0 = equal, 1 = greater than 971 */ 972 void 973 nxge_ksort(caddr_t v, int n, int s, int (*f)()) 974 { 975 int g, i, j, ii; 976 unsigned int *p1, *p2; 977 unsigned int tmp; 978 979 /* No work to do */ 980 if (v == NULL || n <= 1) 981 return; 982 /* Sanity check on arguments */ 983 ASSERT(((uintptr_t)v & 0x3) == 0 && (s & 0x3) == 0); 984 ASSERT(s > 0); 985 986 for (g = n / 2; g > 0; g /= 2) { 987 for (i = g; i < n; i++) { 988 for (j = i - g; j >= 0 && 989 (*f)(v + j * s, v + (j + g) * s) == 1; 990 j -= g) { 991 p1 = (unsigned *)(v + j * s); 992 p2 = (unsigned *)(v + (j + g) * s); 993 for (ii = 0; ii < s / 4; ii++) { 994 tmp = *p1; 995 *p1++ = *p2; 996 *p2++ = tmp; 997 } 998 } 999 } 1000 } 1001 } 1002 1003 /* 1004 * Initialize data structures required for rxdma 1005 * buffer dvma->vmem address lookup 1006 */ 1007 /*ARGSUSED*/ 1008 static nxge_status_t 1009 nxge_rxbuf_index_info_init(p_nxge_t nxgep, p_rx_rbr_ring_t rbrp) 1010 { 1011 1012 int index; 1013 rxring_info_t *ring_info; 1014 int max_iteration = 0, max_index = 0; 1015 1016 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_rxbuf_index_info_init")); 1017 1018 ring_info = rbrp->ring_info; 1019 ring_info->hint[0] = NO_HINT; 1020 ring_info->hint[1] = NO_HINT; 1021 ring_info->hint[2] = NO_HINT; 1022 max_index = rbrp->num_blocks; 1023 1024 /* read the DVMA address information and sort it */ 1025 /* do init of the information array */ 1026 1027 1028 NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 1029 " nxge_rxbuf_index_info_init Sort ptrs")); 1030 1031 /* sort the array */ 1032 nxge_ksort((void *)ring_info->buffer, max_index, 1033 sizeof (rxbuf_index_info_t), nxge_sort_compare); 1034 1035 1036 1037 for (index = 0; index < max_index; index++) { 1038 NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 1039 " nxge_rxbuf_index_info_init: sorted chunk %d " 1040 " ioaddr $%p kaddr $%p size %x", 1041 index, ring_info->buffer[index].dvma_addr, 1042 ring_info->buffer[index].kaddr, 1043 ring_info->buffer[index].buf_size)); 1044 } 1045 1046 max_iteration = 0; 1047 while (max_index >= (1ULL << max_iteration)) 1048 max_iteration++; 1049 ring_info->max_iterations = max_iteration + 1; 1050 NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 1051 " nxge_rxbuf_index_info_init Find max iter %d", 1052 ring_info->max_iterations)); 1053 1054 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxbuf_index_info_init")); 1055 return (NXGE_OK); 1056 } 1057 1058 /* ARGSUSED */ 1059 void 1060 nxge_dump_rcr_entry(p_nxge_t nxgep, p_rcr_entry_t entry_p) 1061 { 1062 #ifdef NXGE_DEBUG 1063 1064 uint32_t bptr; 1065 uint64_t pp; 1066 1067 bptr = entry_p->bits.hdw.pkt_buf_addr; 1068 1069 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1070 "\trcr entry $%p " 1071 "\trcr entry 0x%0llx " 1072 "\trcr entry 0x%08x " 1073 "\trcr entry 0x%08x " 1074 "\tvalue 0x%0llx\n" 1075 "\tmulti = %d\n" 1076 "\tpkt_type = 0x%x\n" 1077 "\tzero_copy = %d\n" 1078 "\tnoport = %d\n" 1079 "\tpromis = %d\n" 1080 "\terror = 0x%04x\n" 1081 "\tdcf_err = 0x%01x\n" 1082 "\tl2_len = %d\n" 1083 "\tpktbufsize = %d\n" 1084 "\tpkt_buf_addr = $%p\n" 1085 "\tpkt_buf_addr (<< 6) = $%p\n", 1086 entry_p, 1087 *(int64_t *)entry_p, 1088 *(int32_t *)entry_p, 1089 *(int32_t *)((char *)entry_p + 32), 1090 entry_p->value, 1091 entry_p->bits.hdw.multi, 1092 entry_p->bits.hdw.pkt_type, 1093 entry_p->bits.hdw.zero_copy, 1094 entry_p->bits.hdw.noport, 1095 entry_p->bits.hdw.promis, 1096 entry_p->bits.hdw.error, 1097 entry_p->bits.hdw.dcf_err, 1098 entry_p->bits.hdw.l2_len, 1099 entry_p->bits.hdw.pktbufsz, 1100 bptr, 1101 entry_p->bits.ldw.pkt_buf_addr)); 1102 1103 pp = (entry_p->value & RCR_PKT_BUF_ADDR_MASK) << 1104 RCR_PKT_BUF_ADDR_SHIFT; 1105 1106 NXGE_DEBUG_MSG((nxgep, RX_CTL, "rcr pp 0x%llx l2 len %d", 1107 pp, (*(int64_t *)entry_p >> 40) & 0x3fff)); 1108 #endif 1109 } 1110 1111 void 1112 nxge_rxdma_regs_dump(p_nxge_t nxgep, int rdc) 1113 { 1114 npi_handle_t handle; 1115 rbr_stat_t rbr_stat; 1116 addr44_t hd_addr; 1117 addr44_t tail_addr; 1118 uint16_t qlen; 1119 1120 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1121 "==> nxge_rxdma_regs_dump: rdc channel %d", rdc)); 1122 1123 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1124 1125 /* RBR head */ 1126 hd_addr.addr = 0; 1127 (void) npi_rxdma_rdc_rbr_head_get(handle, rdc, &hd_addr); 1128 #if defined(__i386) 1129 printf("nxge_rxdma_regs_dump: got hdptr $%p \n", 1130 (void *)(uint32_t)hd_addr.addr); 1131 #else 1132 printf("nxge_rxdma_regs_dump: got hdptr $%p \n", 1133 (void *)hd_addr.addr); 1134 #endif 1135 1136 /* RBR stats */ 1137 (void) npi_rxdma_rdc_rbr_stat_get(handle, rdc, &rbr_stat); 1138 printf("nxge_rxdma_regs_dump: rbr len %d \n", rbr_stat.bits.ldw.qlen); 1139 1140 /* RCR tail */ 1141 tail_addr.addr = 0; 1142 (void) npi_rxdma_rdc_rcr_tail_get(handle, rdc, &tail_addr); 1143 #if defined(__i386) 1144 printf("nxge_rxdma_regs_dump: got tail ptr $%p \n", 1145 (void *)(uint32_t)tail_addr.addr); 1146 #else 1147 printf("nxge_rxdma_regs_dump: got tail ptr $%p \n", 1148 (void *)tail_addr.addr); 1149 #endif 1150 1151 /* RCR qlen */ 1152 (void) npi_rxdma_rdc_rcr_qlen_get(handle, rdc, &qlen); 1153 printf("nxge_rxdma_regs_dump: rcr len %x \n", qlen); 1154 1155 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1156 "<== nxge_rxdma_regs_dump: rdc rdc %d", rdc)); 1157 } 1158 1159 void 1160 nxge_rxdma_stop(p_nxge_t nxgep) 1161 { 1162 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop")); 1163 1164 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 1165 (void) nxge_rx_mac_disable(nxgep); 1166 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 1167 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_stop")); 1168 } 1169 1170 void 1171 nxge_rxdma_stop_reinit(p_nxge_t nxgep) 1172 { 1173 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_reinit")); 1174 1175 (void) nxge_rxdma_stop(nxgep); 1176 (void) nxge_uninit_rxdma_channels(nxgep); 1177 (void) nxge_init_rxdma_channels(nxgep); 1178 1179 #ifndef AXIS_DEBUG_LB 1180 (void) nxge_xcvr_init(nxgep); 1181 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 1182 #endif 1183 (void) nxge_rx_mac_enable(nxgep); 1184 1185 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_stop_reinit")); 1186 } 1187 1188 nxge_status_t 1189 nxge_rxdma_hw_mode(p_nxge_t nxgep, boolean_t enable) 1190 { 1191 nxge_grp_set_t *set = &nxgep->rx_set; 1192 nxge_status_t status; 1193 npi_status_t rs; 1194 int rdc; 1195 1196 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1197 "==> nxge_rxdma_hw_mode: mode %d", enable)); 1198 1199 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 1200 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1201 "<== nxge_rxdma_mode: not initialized")); 1202 return (NXGE_ERROR); 1203 } 1204 1205 if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) { 1206 NXGE_DEBUG_MSG((nxgep, TX_CTL, 1207 "<== nxge_tx_port_fatal_err_recover: " 1208 "NULL ring pointer(s)")); 1209 return (NXGE_ERROR); 1210 } 1211 1212 if (set->owned.map == 0) { 1213 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1214 "nxge_rxdma_regs_dump_channels: no channels")); 1215 return (NULL); 1216 } 1217 1218 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1219 if ((1 << rdc) & set->owned.map) { 1220 rx_rbr_ring_t *ring = 1221 nxgep->rx_rbr_rings->rbr_rings[rdc]; 1222 npi_handle_t handle = NXGE_DEV_NPI_HANDLE(nxgep); 1223 if (ring) { 1224 if (enable) { 1225 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1226 "==> nxge_rxdma_hw_mode: " 1227 "channel %d (enable)", rdc)); 1228 rs = npi_rxdma_cfg_rdc_enable 1229 (handle, rdc); 1230 } else { 1231 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1232 "==> nxge_rxdma_hw_mode: " 1233 "channel %d disable)", rdc)); 1234 rs = npi_rxdma_cfg_rdc_disable 1235 (handle, rdc); 1236 } 1237 } 1238 } 1239 } 1240 1241 status = ((rs == NPI_SUCCESS) ? NXGE_OK : NXGE_ERROR | rs); 1242 1243 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1244 "<== nxge_rxdma_hw_mode: status 0x%x", status)); 1245 1246 return (status); 1247 } 1248 1249 void 1250 nxge_rxdma_enable_channel(p_nxge_t nxgep, uint16_t channel) 1251 { 1252 npi_handle_t handle; 1253 1254 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 1255 "==> nxge_rxdma_enable_channel: channel %d", channel)); 1256 1257 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1258 (void) npi_rxdma_cfg_rdc_enable(handle, channel); 1259 1260 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxdma_enable_channel")); 1261 } 1262 1263 void 1264 nxge_rxdma_disable_channel(p_nxge_t nxgep, uint16_t channel) 1265 { 1266 npi_handle_t handle; 1267 1268 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 1269 "==> nxge_rxdma_disable_channel: channel %d", channel)); 1270 1271 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1272 (void) npi_rxdma_cfg_rdc_disable(handle, channel); 1273 1274 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxdma_disable_channel")); 1275 } 1276 1277 void 1278 nxge_hw_start_rx(p_nxge_t nxgep) 1279 { 1280 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_start_rx")); 1281 1282 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_START); 1283 (void) nxge_rx_mac_enable(nxgep); 1284 1285 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_start_rx")); 1286 } 1287 1288 /*ARGSUSED*/ 1289 void 1290 nxge_fixup_rxdma_rings(p_nxge_t nxgep) 1291 { 1292 nxge_grp_set_t *set = &nxgep->rx_set; 1293 int rdc; 1294 1295 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_fixup_rxdma_rings")); 1296 1297 if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) { 1298 NXGE_DEBUG_MSG((nxgep, TX_CTL, 1299 "<== nxge_tx_port_fatal_err_recover: " 1300 "NULL ring pointer(s)")); 1301 return; 1302 } 1303 1304 if (set->owned.map == 0) { 1305 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1306 "nxge_rxdma_regs_dump_channels: no channels")); 1307 return; 1308 } 1309 1310 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1311 if ((1 << rdc) & set->owned.map) { 1312 rx_rbr_ring_t *ring = 1313 nxgep->rx_rbr_rings->rbr_rings[rdc]; 1314 if (ring) { 1315 nxge_rxdma_hw_stop(nxgep, rdc); 1316 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1317 "==> nxge_fixup_rxdma_rings: " 1318 "channel %d ring $%px", 1319 rdc, ring)); 1320 (void) nxge_rxdma_fixup_channel 1321 (nxgep, rdc, rdc); 1322 } 1323 } 1324 } 1325 1326 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_fixup_rxdma_rings")); 1327 } 1328 1329 void 1330 nxge_rxdma_fix_channel(p_nxge_t nxgep, uint16_t channel) 1331 { 1332 int i; 1333 1334 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fix_channel")); 1335 i = nxge_rxdma_get_ring_index(nxgep, channel); 1336 if (i < 0) { 1337 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1338 "<== nxge_rxdma_fix_channel: no entry found")); 1339 return; 1340 } 1341 1342 nxge_rxdma_fixup_channel(nxgep, channel, i); 1343 1344 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_fix_channel")); 1345 } 1346 1347 void 1348 nxge_rxdma_fixup_channel(p_nxge_t nxgep, uint16_t channel, int entry) 1349 { 1350 int ndmas; 1351 p_rx_rbr_rings_t rx_rbr_rings; 1352 p_rx_rbr_ring_t *rbr_rings; 1353 p_rx_rcr_rings_t rx_rcr_rings; 1354 p_rx_rcr_ring_t *rcr_rings; 1355 p_rx_mbox_areas_t rx_mbox_areas_p; 1356 p_rx_mbox_t *rx_mbox_p; 1357 p_nxge_dma_pool_t dma_buf_poolp; 1358 p_nxge_dma_pool_t dma_cntl_poolp; 1359 p_rx_rbr_ring_t rbrp; 1360 p_rx_rcr_ring_t rcrp; 1361 p_rx_mbox_t mboxp; 1362 p_nxge_dma_common_t dmap; 1363 nxge_status_t status = NXGE_OK; 1364 1365 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fixup_channel")); 1366 1367 (void) nxge_rxdma_stop_channel(nxgep, channel); 1368 1369 dma_buf_poolp = nxgep->rx_buf_pool_p; 1370 dma_cntl_poolp = nxgep->rx_cntl_pool_p; 1371 1372 if (!dma_buf_poolp->buf_allocated || !dma_cntl_poolp->buf_allocated) { 1373 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1374 "<== nxge_rxdma_fixup_channel: buf not allocated")); 1375 return; 1376 } 1377 1378 ndmas = dma_buf_poolp->ndmas; 1379 if (!ndmas) { 1380 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1381 "<== nxge_rxdma_fixup_channel: no dma allocated")); 1382 return; 1383 } 1384 1385 rx_rbr_rings = nxgep->rx_rbr_rings; 1386 rx_rcr_rings = nxgep->rx_rcr_rings; 1387 rbr_rings = rx_rbr_rings->rbr_rings; 1388 rcr_rings = rx_rcr_rings->rcr_rings; 1389 rx_mbox_areas_p = nxgep->rx_mbox_areas_p; 1390 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 1391 1392 /* Reinitialize the receive block and completion rings */ 1393 rbrp = (p_rx_rbr_ring_t)rbr_rings[entry], 1394 rcrp = (p_rx_rcr_ring_t)rcr_rings[entry], 1395 mboxp = (p_rx_mbox_t)rx_mbox_p[entry]; 1396 1397 1398 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 1399 rbrp->rbr_rd_index = 0; 1400 rcrp->comp_rd_index = 0; 1401 rcrp->comp_wt_index = 0; 1402 1403 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 1404 bzero((caddr_t)dmap->kaddrp, dmap->alength); 1405 1406 status = nxge_rxdma_start_channel(nxgep, channel, 1407 rbrp, rcrp, mboxp); 1408 if (status != NXGE_OK) { 1409 goto nxge_rxdma_fixup_channel_fail; 1410 } 1411 if (status != NXGE_OK) { 1412 goto nxge_rxdma_fixup_channel_fail; 1413 } 1414 1415 nxge_rxdma_fixup_channel_fail: 1416 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1417 "==> nxge_rxdma_fixup_channel: failed (0x%08x)", status)); 1418 1419 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_fixup_channel")); 1420 } 1421 1422 /* ARGSUSED */ 1423 int 1424 nxge_rxdma_get_ring_index(p_nxge_t nxgep, uint16_t channel) 1425 { 1426 return (channel); 1427 } 1428 1429 p_rx_rbr_ring_t 1430 nxge_rxdma_get_rbr_ring(p_nxge_t nxgep, uint16_t channel) 1431 { 1432 nxge_grp_set_t *set = &nxgep->rx_set; 1433 nxge_channel_t rdc; 1434 1435 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1436 "==> nxge_rxdma_get_rbr_ring: channel %d", channel)); 1437 1438 if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) { 1439 NXGE_DEBUG_MSG((nxgep, TX_CTL, 1440 "<== nxge_rxdma_get_rbr_ring: " 1441 "NULL ring pointer(s)")); 1442 return (NULL); 1443 } 1444 1445 if (set->owned.map == 0) { 1446 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1447 "<== nxge_rxdma_get_rbr_ring: no channels")); 1448 return (NULL); 1449 } 1450 1451 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1452 if ((1 << rdc) & set->owned.map) { 1453 rx_rbr_ring_t *ring = 1454 nxgep->rx_rbr_rings->rbr_rings[rdc]; 1455 if (ring) { 1456 if (channel == ring->rdc) { 1457 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1458 "==> nxge_rxdma_get_rbr_ring: " 1459 "channel %d ring $%p", rdc, ring)); 1460 return (ring); 1461 } 1462 } 1463 } 1464 } 1465 1466 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1467 "<== nxge_rxdma_get_rbr_ring: not found")); 1468 1469 return (NULL); 1470 } 1471 1472 p_rx_rcr_ring_t 1473 nxge_rxdma_get_rcr_ring(p_nxge_t nxgep, uint16_t channel) 1474 { 1475 nxge_grp_set_t *set = &nxgep->rx_set; 1476 nxge_channel_t rdc; 1477 1478 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1479 "==> nxge_rxdma_get_rcr_ring: channel %d", channel)); 1480 1481 if (nxgep->rx_rcr_rings == 0 || nxgep->rx_rcr_rings->rcr_rings == 0) { 1482 NXGE_DEBUG_MSG((nxgep, TX_CTL, 1483 "<== nxge_rxdma_get_rcr_ring: " 1484 "NULL ring pointer(s)")); 1485 return (NULL); 1486 } 1487 1488 if (set->owned.map == 0) { 1489 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1490 "<== nxge_rxdma_get_rbr_ring: no channels")); 1491 return (NULL); 1492 } 1493 1494 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1495 if ((1 << rdc) & set->owned.map) { 1496 rx_rcr_ring_t *ring = 1497 nxgep->rx_rcr_rings->rcr_rings[rdc]; 1498 if (ring) { 1499 if (channel == ring->rdc) { 1500 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1501 "==> nxge_rxdma_get_rcr_ring: " 1502 "channel %d ring $%p", rdc, ring)); 1503 return (ring); 1504 } 1505 } 1506 } 1507 } 1508 1509 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1510 "<== nxge_rxdma_get_rcr_ring: not found")); 1511 1512 return (NULL); 1513 } 1514 1515 /* 1516 * Static functions start here. 1517 */ 1518 static p_rx_msg_t 1519 nxge_allocb(size_t size, uint32_t pri, p_nxge_dma_common_t dmabuf_p) 1520 { 1521 p_rx_msg_t nxge_mp = NULL; 1522 p_nxge_dma_common_t dmamsg_p; 1523 uchar_t *buffer; 1524 1525 nxge_mp = KMEM_ZALLOC(sizeof (rx_msg_t), KM_NOSLEEP); 1526 if (nxge_mp == NULL) { 1527 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 1528 "Allocation of a rx msg failed.")); 1529 goto nxge_allocb_exit; 1530 } 1531 1532 nxge_mp->use_buf_pool = B_FALSE; 1533 if (dmabuf_p) { 1534 nxge_mp->use_buf_pool = B_TRUE; 1535 dmamsg_p = (p_nxge_dma_common_t)&nxge_mp->buf_dma; 1536 *dmamsg_p = *dmabuf_p; 1537 dmamsg_p->nblocks = 1; 1538 dmamsg_p->block_size = size; 1539 dmamsg_p->alength = size; 1540 buffer = (uchar_t *)dmabuf_p->kaddrp; 1541 1542 dmabuf_p->kaddrp = (void *) 1543 ((char *)dmabuf_p->kaddrp + size); 1544 dmabuf_p->ioaddr_pp = (void *) 1545 ((char *)dmabuf_p->ioaddr_pp + size); 1546 dmabuf_p->alength -= size; 1547 dmabuf_p->offset += size; 1548 dmabuf_p->dma_cookie.dmac_laddress += size; 1549 dmabuf_p->dma_cookie.dmac_size -= size; 1550 1551 } else { 1552 buffer = KMEM_ALLOC(size, KM_NOSLEEP); 1553 if (buffer == NULL) { 1554 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 1555 "Allocation of a receive page failed.")); 1556 goto nxge_allocb_fail1; 1557 } 1558 } 1559 1560 nxge_mp->rx_mblk_p = desballoc(buffer, size, pri, &nxge_mp->freeb); 1561 if (nxge_mp->rx_mblk_p == NULL) { 1562 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, "desballoc failed.")); 1563 goto nxge_allocb_fail2; 1564 } 1565 1566 nxge_mp->buffer = buffer; 1567 nxge_mp->block_size = size; 1568 nxge_mp->freeb.free_func = (void (*)())nxge_freeb; 1569 nxge_mp->freeb.free_arg = (caddr_t)nxge_mp; 1570 nxge_mp->ref_cnt = 1; 1571 nxge_mp->free = B_TRUE; 1572 nxge_mp->rx_use_bcopy = B_FALSE; 1573 1574 atomic_inc_32(&nxge_mblks_pending); 1575 1576 goto nxge_allocb_exit; 1577 1578 nxge_allocb_fail2: 1579 if (!nxge_mp->use_buf_pool) { 1580 KMEM_FREE(buffer, size); 1581 } 1582 1583 nxge_allocb_fail1: 1584 KMEM_FREE(nxge_mp, sizeof (rx_msg_t)); 1585 nxge_mp = NULL; 1586 1587 nxge_allocb_exit: 1588 return (nxge_mp); 1589 } 1590 1591 p_mblk_t 1592 nxge_dupb(p_rx_msg_t nxge_mp, uint_t offset, size_t size) 1593 { 1594 p_mblk_t mp; 1595 1596 NXGE_DEBUG_MSG((NULL, MEM_CTL, "==> nxge_dupb")); 1597 NXGE_DEBUG_MSG((NULL, MEM_CTL, "nxge_mp = $%p " 1598 "offset = 0x%08X " 1599 "size = 0x%08X", 1600 nxge_mp, offset, size)); 1601 1602 mp = desballoc(&nxge_mp->buffer[offset], size, 1603 0, &nxge_mp->freeb); 1604 if (mp == NULL) { 1605 NXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 1606 goto nxge_dupb_exit; 1607 } 1608 atomic_inc_32(&nxge_mp->ref_cnt); 1609 1610 1611 nxge_dupb_exit: 1612 NXGE_DEBUG_MSG((NULL, MEM_CTL, "<== nxge_dupb mp = $%p", 1613 nxge_mp)); 1614 return (mp); 1615 } 1616 1617 p_mblk_t 1618 nxge_dupb_bcopy(p_rx_msg_t nxge_mp, uint_t offset, size_t size) 1619 { 1620 p_mblk_t mp; 1621 uchar_t *dp; 1622 1623 mp = allocb(size + NXGE_RXBUF_EXTRA, 0); 1624 if (mp == NULL) { 1625 NXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 1626 goto nxge_dupb_bcopy_exit; 1627 } 1628 dp = mp->b_rptr = mp->b_rptr + NXGE_RXBUF_EXTRA; 1629 bcopy((void *)&nxge_mp->buffer[offset], dp, size); 1630 mp->b_wptr = dp + size; 1631 1632 nxge_dupb_bcopy_exit: 1633 NXGE_DEBUG_MSG((NULL, MEM_CTL, "<== nxge_dupb mp = $%p", 1634 nxge_mp)); 1635 return (mp); 1636 } 1637 1638 void nxge_post_page(p_nxge_t nxgep, p_rx_rbr_ring_t rx_rbr_p, 1639 p_rx_msg_t rx_msg_p); 1640 1641 void 1642 nxge_post_page(p_nxge_t nxgep, p_rx_rbr_ring_t rx_rbr_p, p_rx_msg_t rx_msg_p) 1643 { 1644 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_post_page")); 1645 1646 /* Reuse this buffer */ 1647 rx_msg_p->free = B_FALSE; 1648 rx_msg_p->cur_usage_cnt = 0; 1649 rx_msg_p->max_usage_cnt = 0; 1650 rx_msg_p->pkt_buf_size = 0; 1651 1652 if (rx_rbr_p->rbr_use_bcopy) { 1653 rx_msg_p->rx_use_bcopy = B_FALSE; 1654 atomic_dec_32(&rx_rbr_p->rbr_consumed); 1655 } 1656 1657 /* 1658 * Get the rbr header pointer and its offset index. 1659 */ 1660 MUTEX_ENTER(&rx_rbr_p->post_lock); 1661 rx_rbr_p->rbr_wr_index = ((rx_rbr_p->rbr_wr_index + 1) & 1662 rx_rbr_p->rbr_wrap_mask); 1663 rx_rbr_p->rbr_desc_vp[rx_rbr_p->rbr_wr_index] = rx_msg_p->shifted_addr; 1664 MUTEX_EXIT(&rx_rbr_p->post_lock); 1665 npi_rxdma_rdc_rbr_kick(NXGE_DEV_NPI_HANDLE(nxgep), 1666 rx_rbr_p->rdc, 1); 1667 1668 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1669 "<== nxge_post_page (channel %d post_next_index %d)", 1670 rx_rbr_p->rdc, rx_rbr_p->rbr_wr_index)); 1671 1672 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_post_page")); 1673 } 1674 1675 void 1676 nxge_freeb(p_rx_msg_t rx_msg_p) 1677 { 1678 size_t size; 1679 uchar_t *buffer = NULL; 1680 int ref_cnt; 1681 boolean_t free_state = B_FALSE; 1682 1683 rx_rbr_ring_t *ring = rx_msg_p->rx_rbr_p; 1684 1685 NXGE_DEBUG_MSG((NULL, MEM2_CTL, "==> nxge_freeb")); 1686 NXGE_DEBUG_MSG((NULL, MEM2_CTL, 1687 "nxge_freeb:rx_msg_p = $%p (block pending %d)", 1688 rx_msg_p, nxge_mblks_pending)); 1689 1690 /* 1691 * First we need to get the free state, then 1692 * atomic decrement the reference count to prevent 1693 * the race condition with the interrupt thread that 1694 * is processing a loaned up buffer block. 1695 */ 1696 free_state = rx_msg_p->free; 1697 ref_cnt = atomic_add_32_nv(&rx_msg_p->ref_cnt, -1); 1698 if (!ref_cnt) { 1699 atomic_dec_32(&nxge_mblks_pending); 1700 buffer = rx_msg_p->buffer; 1701 size = rx_msg_p->block_size; 1702 NXGE_DEBUG_MSG((NULL, MEM2_CTL, "nxge_freeb: " 1703 "will free: rx_msg_p = $%p (block pending %d)", 1704 rx_msg_p, nxge_mblks_pending)); 1705 1706 if (!rx_msg_p->use_buf_pool) { 1707 KMEM_FREE(buffer, size); 1708 } 1709 1710 KMEM_FREE(rx_msg_p, sizeof (rx_msg_t)); 1711 1712 if (ring) { 1713 /* 1714 * Decrement the receive buffer ring's reference 1715 * count, too. 1716 */ 1717 atomic_dec_32(&ring->rbr_ref_cnt); 1718 1719 /* 1720 * Free the receive buffer ring, if 1721 * 1. all the receive buffers have been freed 1722 * 2. and we are in the proper state (that is, 1723 * we are not UNMAPPING). 1724 */ 1725 if (ring->rbr_ref_cnt == 0 && 1726 ring->rbr_state == RBR_UNMAPPED) { 1727 /* 1728 * Free receive data buffers, 1729 * buffer index information 1730 * (rxring_info) and 1731 * the message block ring. 1732 */ 1733 NXGE_DEBUG_MSG((NULL, RX_CTL, 1734 "nxge_freeb:rx_msg_p = $%p " 1735 "(block pending %d) free buffers", 1736 rx_msg_p, nxge_mblks_pending)); 1737 nxge_rxdma_databuf_free(ring); 1738 if (ring->ring_info) { 1739 KMEM_FREE(ring->ring_info, 1740 sizeof (rxring_info_t)); 1741 } 1742 1743 if (ring->rx_msg_ring) { 1744 KMEM_FREE(ring->rx_msg_ring, 1745 ring->tnblocks * 1746 sizeof (p_rx_msg_t)); 1747 } 1748 KMEM_FREE(ring, sizeof (*ring)); 1749 } 1750 } 1751 return; 1752 } 1753 1754 /* 1755 * Repost buffer. 1756 */ 1757 if (free_state && (ref_cnt == 1) && ring) { 1758 NXGE_DEBUG_MSG((NULL, RX_CTL, 1759 "nxge_freeb: post page $%p:", rx_msg_p)); 1760 if (ring->rbr_state == RBR_POSTING) 1761 nxge_post_page(rx_msg_p->nxgep, ring, rx_msg_p); 1762 } 1763 1764 NXGE_DEBUG_MSG((NULL, MEM2_CTL, "<== nxge_freeb")); 1765 } 1766 1767 uint_t 1768 nxge_rx_intr(void *arg1, void *arg2) 1769 { 1770 p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 1771 p_nxge_t nxgep = (p_nxge_t)arg2; 1772 p_nxge_ldg_t ldgp; 1773 uint8_t channel; 1774 npi_handle_t handle; 1775 rx_dma_ctl_stat_t cs; 1776 1777 #ifdef NXGE_DEBUG 1778 rxdma_cfig1_t cfg; 1779 #endif 1780 uint_t serviced = DDI_INTR_UNCLAIMED; 1781 1782 if (ldvp == NULL) { 1783 NXGE_DEBUG_MSG((NULL, INT_CTL, 1784 "<== nxge_rx_intr: arg2 $%p arg1 $%p", 1785 nxgep, ldvp)); 1786 1787 return (DDI_INTR_CLAIMED); 1788 } 1789 1790 if (arg2 == NULL || (void *)ldvp->nxgep != arg2) { 1791 nxgep = ldvp->nxgep; 1792 } 1793 1794 if ((!(nxgep->drv_state & STATE_HW_INITIALIZED)) || 1795 (nxgep->nxge_mac_state != NXGE_MAC_STARTED)) { 1796 NXGE_DEBUG_MSG((nxgep, INT_CTL, 1797 "<== nxge_rx_intr: interface not started or intialized")); 1798 return (DDI_INTR_CLAIMED); 1799 } 1800 1801 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1802 "==> nxge_rx_intr: arg2 $%p arg1 $%p", 1803 nxgep, ldvp)); 1804 1805 /* 1806 * This interrupt handler is for a specific 1807 * receive dma channel. 1808 */ 1809 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1810 /* 1811 * Get the control and status for this channel. 1812 */ 1813 channel = ldvp->channel; 1814 ldgp = ldvp->ldgp; 1815 RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel, &cs.value); 1816 1817 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_intr:channel %d " 1818 "cs 0x%016llx rcrto 0x%x rcrthres %x", 1819 channel, 1820 cs.value, 1821 cs.bits.hdw.rcrto, 1822 cs.bits.hdw.rcrthres)); 1823 1824 nxge_rx_pkts_vring(nxgep, ldvp->vdma_index, cs); 1825 serviced = DDI_INTR_CLAIMED; 1826 1827 /* error events. */ 1828 if (cs.value & RX_DMA_CTL_STAT_ERROR) { 1829 (void) nxge_rx_err_evnts(nxgep, channel, cs); 1830 } 1831 1832 nxge_intr_exit: 1833 /* 1834 * Enable the mailbox update interrupt if we want 1835 * to use mailbox. We probably don't need to use 1836 * mailbox as it only saves us one pio read. 1837 * Also write 1 to rcrthres and rcrto to clear 1838 * these two edge triggered bits. 1839 */ 1840 1841 cs.value &= RX_DMA_CTL_STAT_WR1C; 1842 cs.bits.hdw.mex = 1; 1843 RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel, 1844 cs.value); 1845 1846 /* 1847 * Rearm this logical group if this is a single device 1848 * group. 1849 */ 1850 if (ldgp->nldvs == 1) { 1851 ldgimgm_t mgm; 1852 mgm.value = 0; 1853 mgm.bits.ldw.arm = 1; 1854 mgm.bits.ldw.timer = ldgp->ldg_timer; 1855 if (isLDOMguest(nxgep)) { 1856 nxge_hio_ldgimgn(nxgep, ldgp); 1857 } else { 1858 NXGE_REG_WR64(handle, 1859 LDGIMGN_REG + LDSV_OFFSET(ldgp->ldg), 1860 mgm.value); 1861 } 1862 } 1863 1864 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_intr: serviced %d", 1865 serviced)); 1866 return (serviced); 1867 } 1868 1869 /* 1870 * Process the packets received in the specified logical device 1871 * and pass up a chain of message blocks to the upper layer. 1872 */ 1873 static void 1874 nxge_rx_pkts_vring(p_nxge_t nxgep, uint_t vindex, rx_dma_ctl_stat_t cs) 1875 { 1876 p_mblk_t mp; 1877 p_rx_rcr_ring_t rcrp; 1878 1879 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts_vring")); 1880 rcrp = nxgep->rx_rcr_rings->rcr_rings[vindex]; 1881 if (rcrp->poll_flag) { 1882 /* It is in the poll mode */ 1883 return; 1884 } 1885 1886 if ((mp = nxge_rx_pkts(nxgep, rcrp, cs, -1)) == NULL) { 1887 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1888 "<== nxge_rx_pkts_vring: no mp")); 1889 return; 1890 } 1891 1892 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts_vring: $%p", 1893 mp)); 1894 1895 #ifdef NXGE_DEBUG 1896 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1897 "==> nxge_rx_pkts_vring:calling mac_rx " 1898 "LEN %d mp $%p mp->b_cont $%p mp->b_next $%p rcrp $%p " 1899 "mac_handle $%p", 1900 mp->b_wptr - mp->b_rptr, 1901 mp, mp->b_cont, mp->b_next, 1902 rcrp, rcrp->rcr_mac_handle)); 1903 1904 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1905 "==> nxge_rx_pkts_vring: dump packets " 1906 "(mp $%p b_rptr $%p b_wptr $%p):\n %s", 1907 mp, 1908 mp->b_rptr, 1909 mp->b_wptr, 1910 nxge_dump_packet((char *)mp->b_rptr, 1911 mp->b_wptr - mp->b_rptr))); 1912 if (mp->b_cont) { 1913 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1914 "==> nxge_rx_pkts_vring: dump b_cont packets " 1915 "(mp->b_cont $%p b_rptr $%p b_wptr $%p):\n %s", 1916 mp->b_cont, 1917 mp->b_cont->b_rptr, 1918 mp->b_cont->b_wptr, 1919 nxge_dump_packet((char *)mp->b_cont->b_rptr, 1920 mp->b_cont->b_wptr - mp->b_cont->b_rptr))); 1921 } 1922 if (mp->b_next) { 1923 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1924 "==> nxge_rx_pkts_vring: dump next packets " 1925 "(b_rptr $%p): %s", 1926 mp->b_next->b_rptr, 1927 nxge_dump_packet((char *)mp->b_next->b_rptr, 1928 mp->b_next->b_wptr - mp->b_next->b_rptr))); 1929 } 1930 #endif 1931 1932 if (!isLDOMguest(nxgep)) 1933 mac_rx(nxgep->mach, rcrp->rcr_mac_handle, mp); 1934 #if defined(sun4v) 1935 else { /* isLDOMguest(nxgep) */ 1936 nxge_hio_data_t *nhd = (nxge_hio_data_t *) 1937 nxgep->nxge_hw_p->hio; 1938 nx_vio_fp_t *vio = &nhd->hio.vio; 1939 1940 if (vio->cb.vio_net_rx_cb) { 1941 (*vio->cb.vio_net_rx_cb) 1942 (nxgep->hio_vr->vhp, mp); 1943 } 1944 } 1945 #endif 1946 } 1947 1948 1949 /* 1950 * This routine is the main packet receive processing function. 1951 * It gets the packet type, error code, and buffer related 1952 * information from the receive completion entry. 1953 * How many completion entries to process is based on the number of packets 1954 * queued by the hardware, a hardware maintained tail pointer 1955 * and a configurable receive packet count. 1956 * 1957 * A chain of message blocks will be created as result of processing 1958 * the completion entries. This chain of message blocks will be returned and 1959 * a hardware control status register will be updated with the number of 1960 * packets were removed from the hardware queue. 1961 * 1962 */ 1963 static mblk_t * 1964 nxge_rx_pkts(p_nxge_t nxgep, p_rx_rcr_ring_t rcr_p, rx_dma_ctl_stat_t cs, 1965 int bytes_to_pickup) 1966 { 1967 npi_handle_t handle; 1968 uint8_t channel; 1969 uint32_t comp_rd_index; 1970 p_rcr_entry_t rcr_desc_rd_head_p; 1971 p_rcr_entry_t rcr_desc_rd_head_pp; 1972 p_mblk_t nmp, mp_cont, head_mp, *tail_mp; 1973 uint16_t qlen, nrcr_read, npkt_read; 1974 uint32_t qlen_hw; 1975 boolean_t multi; 1976 rcrcfig_b_t rcr_cfg_b; 1977 int totallen = 0; 1978 #if defined(_BIG_ENDIAN) 1979 npi_status_t rs = NPI_SUCCESS; 1980 #endif 1981 1982 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts: " 1983 "channel %d", rcr_p->rdc)); 1984 1985 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 1986 return (NULL); 1987 } 1988 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1989 channel = rcr_p->rdc; 1990 1991 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1992 "==> nxge_rx_pkts: START: rcr channel %d " 1993 "head_p $%p head_pp $%p index %d ", 1994 channel, rcr_p->rcr_desc_rd_head_p, 1995 rcr_p->rcr_desc_rd_head_pp, 1996 rcr_p->comp_rd_index)); 1997 1998 1999 #if !defined(_BIG_ENDIAN) 2000 qlen = RXDMA_REG_READ32(handle, RCRSTAT_A_REG, channel) & 0xffff; 2001 #else 2002 rs = npi_rxdma_rdc_rcr_qlen_get(handle, channel, &qlen); 2003 if (rs != NPI_SUCCESS) { 2004 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts: " 2005 "channel %d, get qlen failed 0x%08x", 2006 channel, rs)); 2007 return (NULL); 2008 } 2009 #endif 2010 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts:rcr channel %d " 2011 "qlen %d", channel, qlen)); 2012 2013 2014 2015 if (!qlen) { 2016 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2017 "==> nxge_rx_pkts:rcr channel %d " 2018 "qlen %d (no pkts)", channel, qlen)); 2019 2020 return (NULL); 2021 } 2022 2023 comp_rd_index = rcr_p->comp_rd_index; 2024 2025 rcr_desc_rd_head_p = rcr_p->rcr_desc_rd_head_p; 2026 rcr_desc_rd_head_pp = rcr_p->rcr_desc_rd_head_pp; 2027 nrcr_read = npkt_read = 0; 2028 2029 /* 2030 * Number of packets queued 2031 * (The jumbo or multi packet will be counted as only one 2032 * packets and it may take up more than one completion entry). 2033 */ 2034 qlen_hw = (qlen < nxge_max_rx_pkts) ? 2035 qlen : nxge_max_rx_pkts; 2036 head_mp = NULL; 2037 tail_mp = &head_mp; 2038 nmp = mp_cont = NULL; 2039 multi = B_FALSE; 2040 2041 while (qlen_hw) { 2042 2043 #ifdef NXGE_DEBUG 2044 nxge_dump_rcr_entry(nxgep, rcr_desc_rd_head_p); 2045 #endif 2046 /* 2047 * Process one completion ring entry. 2048 */ 2049 nxge_receive_packet(nxgep, 2050 rcr_p, rcr_desc_rd_head_p, &multi, &nmp, &mp_cont); 2051 2052 /* 2053 * message chaining modes 2054 */ 2055 if (nmp) { 2056 nmp->b_next = NULL; 2057 if (!multi && !mp_cont) { /* frame fits a partition */ 2058 *tail_mp = nmp; 2059 tail_mp = &nmp->b_next; 2060 totallen += MBLKL(nmp); 2061 nmp = NULL; 2062 } else if (multi && !mp_cont) { /* first segment */ 2063 *tail_mp = nmp; 2064 tail_mp = &nmp->b_cont; 2065 totallen += MBLKL(nmp); 2066 } else if (multi && mp_cont) { /* mid of multi segs */ 2067 *tail_mp = mp_cont; 2068 tail_mp = &mp_cont->b_cont; 2069 totallen += MBLKL(mp_cont); 2070 } else if (!multi && mp_cont) { /* last segment */ 2071 *tail_mp = mp_cont; 2072 tail_mp = &nmp->b_next; 2073 totallen += MBLKL(mp_cont); 2074 nmp = NULL; 2075 } 2076 } 2077 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2078 "==> nxge_rx_pkts: loop: rcr channel %d " 2079 "before updating: multi %d " 2080 "nrcr_read %d " 2081 "npk read %d " 2082 "head_pp $%p index %d ", 2083 channel, 2084 multi, 2085 nrcr_read, npkt_read, rcr_desc_rd_head_pp, 2086 comp_rd_index)); 2087 2088 if (!multi) { 2089 qlen_hw--; 2090 npkt_read++; 2091 } 2092 2093 /* 2094 * Update the next read entry. 2095 */ 2096 comp_rd_index = NEXT_ENTRY(comp_rd_index, 2097 rcr_p->comp_wrap_mask); 2098 2099 rcr_desc_rd_head_p = NEXT_ENTRY_PTR(rcr_desc_rd_head_p, 2100 rcr_p->rcr_desc_first_p, 2101 rcr_p->rcr_desc_last_p); 2102 2103 nrcr_read++; 2104 2105 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2106 "<== nxge_rx_pkts: (SAM, process one packet) " 2107 "nrcr_read %d", 2108 nrcr_read)); 2109 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2110 "==> nxge_rx_pkts: loop: rcr channel %d " 2111 "multi %d " 2112 "nrcr_read %d " 2113 "npk read %d " 2114 "head_pp $%p index %d ", 2115 channel, 2116 multi, 2117 nrcr_read, npkt_read, rcr_desc_rd_head_pp, 2118 comp_rd_index)); 2119 2120 if ((bytes_to_pickup != -1) && 2121 (totallen >= bytes_to_pickup)) { 2122 break; 2123 } 2124 } 2125 2126 rcr_p->rcr_desc_rd_head_pp = rcr_desc_rd_head_pp; 2127 rcr_p->comp_rd_index = comp_rd_index; 2128 rcr_p->rcr_desc_rd_head_p = rcr_desc_rd_head_p; 2129 2130 if ((nxgep->intr_timeout != rcr_p->intr_timeout) || 2131 (nxgep->intr_threshold != rcr_p->intr_threshold)) { 2132 rcr_p->intr_timeout = nxgep->intr_timeout; 2133 rcr_p->intr_threshold = nxgep->intr_threshold; 2134 rcr_cfg_b.value = 0x0ULL; 2135 if (rcr_p->intr_timeout) 2136 rcr_cfg_b.bits.ldw.entout = 1; 2137 rcr_cfg_b.bits.ldw.timeout = rcr_p->intr_timeout; 2138 rcr_cfg_b.bits.ldw.pthres = rcr_p->intr_threshold; 2139 RXDMA_REG_WRITE64(handle, RCRCFIG_B_REG, 2140 channel, rcr_cfg_b.value); 2141 } 2142 2143 cs.bits.ldw.pktread = npkt_read; 2144 cs.bits.ldw.ptrread = nrcr_read; 2145 RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, 2146 channel, cs.value); 2147 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2148 "==> nxge_rx_pkts: EXIT: rcr channel %d " 2149 "head_pp $%p index %016llx ", 2150 channel, 2151 rcr_p->rcr_desc_rd_head_pp, 2152 rcr_p->comp_rd_index)); 2153 /* 2154 * Update RCR buffer pointer read and number of packets 2155 * read. 2156 */ 2157 2158 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_pkts")); 2159 return (head_mp); 2160 } 2161 2162 void 2163 nxge_receive_packet(p_nxge_t nxgep, 2164 p_rx_rcr_ring_t rcr_p, p_rcr_entry_t rcr_desc_rd_head_p, 2165 boolean_t *multi_p, mblk_t **mp, mblk_t **mp_cont) 2166 { 2167 p_mblk_t nmp = NULL; 2168 uint64_t multi; 2169 uint64_t dcf_err; 2170 uint8_t channel; 2171 2172 boolean_t first_entry = B_TRUE; 2173 boolean_t is_tcp_udp = B_FALSE; 2174 boolean_t buffer_free = B_FALSE; 2175 boolean_t error_send_up = B_FALSE; 2176 uint8_t error_type; 2177 uint16_t l2_len; 2178 uint16_t skip_len; 2179 uint8_t pktbufsz_type; 2180 uint64_t rcr_entry; 2181 uint64_t *pkt_buf_addr_pp; 2182 uint64_t *pkt_buf_addr_p; 2183 uint32_t buf_offset; 2184 uint32_t bsize; 2185 uint32_t error_disp_cnt; 2186 uint32_t msg_index; 2187 p_rx_rbr_ring_t rx_rbr_p; 2188 p_rx_msg_t *rx_msg_ring_p; 2189 p_rx_msg_t rx_msg_p; 2190 uint16_t sw_offset_bytes = 0, hdr_size = 0; 2191 nxge_status_t status = NXGE_OK; 2192 boolean_t is_valid = B_FALSE; 2193 p_nxge_rx_ring_stats_t rdc_stats; 2194 uint32_t bytes_read; 2195 uint64_t pkt_type; 2196 uint64_t frag; 2197 boolean_t pkt_too_long_err = B_FALSE; 2198 #ifdef NXGE_DEBUG 2199 int dump_len; 2200 #endif 2201 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> nxge_receive_packet")); 2202 first_entry = (*mp == NULL) ? B_TRUE : B_FALSE; 2203 2204 rcr_entry = *((uint64_t *)rcr_desc_rd_head_p); 2205 2206 multi = (rcr_entry & RCR_MULTI_MASK); 2207 dcf_err = (rcr_entry & RCR_DCF_ERROR_MASK); 2208 pkt_type = (rcr_entry & RCR_PKT_TYPE_MASK); 2209 2210 error_type = ((rcr_entry & RCR_ERROR_MASK) >> RCR_ERROR_SHIFT); 2211 frag = (rcr_entry & RCR_FRAG_MASK); 2212 2213 l2_len = ((rcr_entry & RCR_L2_LEN_MASK) >> RCR_L2_LEN_SHIFT); 2214 2215 pktbufsz_type = ((rcr_entry & RCR_PKTBUFSZ_MASK) >> 2216 RCR_PKTBUFSZ_SHIFT); 2217 #if defined(__i386) 2218 pkt_buf_addr_pp = (uint64_t *)(uint32_t)((rcr_entry & 2219 RCR_PKT_BUF_ADDR_MASK) << RCR_PKT_BUF_ADDR_SHIFT); 2220 #else 2221 pkt_buf_addr_pp = (uint64_t *)((rcr_entry & RCR_PKT_BUF_ADDR_MASK) << 2222 RCR_PKT_BUF_ADDR_SHIFT); 2223 #endif 2224 2225 channel = rcr_p->rdc; 2226 2227 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2228 "==> nxge_receive_packet: entryp $%p entry 0x%0llx " 2229 "pkt_buf_addr_pp $%p l2_len %d multi 0x%llx " 2230 "error_type 0x%x pkt_type 0x%x " 2231 "pktbufsz_type %d ", 2232 rcr_desc_rd_head_p, 2233 rcr_entry, pkt_buf_addr_pp, l2_len, 2234 multi, 2235 error_type, 2236 pkt_type, 2237 pktbufsz_type)); 2238 2239 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2240 "==> nxge_receive_packet: entryp $%p entry 0x%0llx " 2241 "pkt_buf_addr_pp $%p l2_len %d multi 0x%llx " 2242 "error_type 0x%x pkt_type 0x%x ", rcr_desc_rd_head_p, 2243 rcr_entry, pkt_buf_addr_pp, l2_len, 2244 multi, 2245 error_type, 2246 pkt_type)); 2247 2248 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2249 "==> (rbr) nxge_receive_packet: entry 0x%0llx " 2250 "full pkt_buf_addr_pp $%p l2_len %d", 2251 rcr_entry, pkt_buf_addr_pp, l2_len)); 2252 2253 /* get the stats ptr */ 2254 rdc_stats = rcr_p->rdc_stats; 2255 2256 if (!l2_len) { 2257 2258 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2259 "<== nxge_receive_packet: failed: l2 length is 0.")); 2260 return; 2261 } 2262 2263 /* 2264 * Sofware workaround for BMAC hardware limitation that allows 2265 * maxframe size of 1526, instead of 1522 for non-jumbo and 0x2406 2266 * instead of 0x2400 for jumbo. 2267 */ 2268 if (l2_len > nxgep->mac.maxframesize) { 2269 pkt_too_long_err = B_TRUE; 2270 } 2271 2272 /* Hardware sends us 4 bytes of CRC as no stripping is done. */ 2273 l2_len -= ETHERFCSL; 2274 2275 /* shift 6 bits to get the full io address */ 2276 #if defined(__i386) 2277 pkt_buf_addr_pp = (uint64_t *)((uint32_t)pkt_buf_addr_pp << 2278 RCR_PKT_BUF_ADDR_SHIFT_FULL); 2279 #else 2280 pkt_buf_addr_pp = (uint64_t *)((uint64_t)pkt_buf_addr_pp << 2281 RCR_PKT_BUF_ADDR_SHIFT_FULL); 2282 #endif 2283 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2284 "==> (rbr) nxge_receive_packet: entry 0x%0llx " 2285 "full pkt_buf_addr_pp $%p l2_len %d", 2286 rcr_entry, pkt_buf_addr_pp, l2_len)); 2287 2288 rx_rbr_p = rcr_p->rx_rbr_p; 2289 rx_msg_ring_p = rx_rbr_p->rx_msg_ring; 2290 2291 if (first_entry) { 2292 hdr_size = (rcr_p->full_hdr_flag ? RXDMA_HDR_SIZE_FULL : 2293 RXDMA_HDR_SIZE_DEFAULT); 2294 2295 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2296 "==> nxge_receive_packet: first entry 0x%016llx " 2297 "pkt_buf_addr_pp $%p l2_len %d hdr %d", 2298 rcr_entry, pkt_buf_addr_pp, l2_len, 2299 hdr_size)); 2300 } 2301 2302 MUTEX_ENTER(&rcr_p->lock); 2303 MUTEX_ENTER(&rx_rbr_p->lock); 2304 2305 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2306 "==> (rbr 1) nxge_receive_packet: entry 0x%0llx " 2307 "full pkt_buf_addr_pp $%p l2_len %d", 2308 rcr_entry, pkt_buf_addr_pp, l2_len)); 2309 2310 /* 2311 * Packet buffer address in the completion entry points 2312 * to the starting buffer address (offset 0). 2313 * Use the starting buffer address to locate the corresponding 2314 * kernel address. 2315 */ 2316 status = nxge_rxbuf_pp_to_vp(nxgep, rx_rbr_p, 2317 pktbufsz_type, pkt_buf_addr_pp, &pkt_buf_addr_p, 2318 &buf_offset, 2319 &msg_index); 2320 2321 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2322 "==> (rbr 2) nxge_receive_packet: entry 0x%0llx " 2323 "full pkt_buf_addr_pp $%p l2_len %d", 2324 rcr_entry, pkt_buf_addr_pp, l2_len)); 2325 2326 if (status != NXGE_OK) { 2327 MUTEX_EXIT(&rx_rbr_p->lock); 2328 MUTEX_EXIT(&rcr_p->lock); 2329 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2330 "<== nxge_receive_packet: found vaddr failed %d", 2331 status)); 2332 return; 2333 } 2334 2335 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2336 "==> (rbr 3) nxge_receive_packet: entry 0x%0llx " 2337 "full pkt_buf_addr_pp $%p l2_len %d", 2338 rcr_entry, pkt_buf_addr_pp, l2_len)); 2339 2340 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2341 "==> (rbr 4 msgindex %d) nxge_receive_packet: entry 0x%0llx " 2342 "full pkt_buf_addr_pp $%p l2_len %d", 2343 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 2344 2345 rx_msg_p = rx_msg_ring_p[msg_index]; 2346 2347 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2348 "==> (rbr 4 msgindex %d) nxge_receive_packet: entry 0x%0llx " 2349 "full pkt_buf_addr_pp $%p l2_len %d", 2350 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 2351 2352 switch (pktbufsz_type) { 2353 case RCR_PKTBUFSZ_0: 2354 bsize = rx_rbr_p->pkt_buf_size0_bytes; 2355 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2356 "==> nxge_receive_packet: 0 buf %d", bsize)); 2357 break; 2358 case RCR_PKTBUFSZ_1: 2359 bsize = rx_rbr_p->pkt_buf_size1_bytes; 2360 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2361 "==> nxge_receive_packet: 1 buf %d", bsize)); 2362 break; 2363 case RCR_PKTBUFSZ_2: 2364 bsize = rx_rbr_p->pkt_buf_size2_bytes; 2365 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2366 "==> nxge_receive_packet: 2 buf %d", bsize)); 2367 break; 2368 case RCR_SINGLE_BLOCK: 2369 bsize = rx_msg_p->block_size; 2370 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2371 "==> nxge_receive_packet: single %d", bsize)); 2372 2373 break; 2374 default: 2375 MUTEX_EXIT(&rx_rbr_p->lock); 2376 MUTEX_EXIT(&rcr_p->lock); 2377 return; 2378 } 2379 2380 DMA_COMMON_SYNC_OFFSET(rx_msg_p->buf_dma, 2381 (buf_offset + sw_offset_bytes), 2382 (hdr_size + l2_len), 2383 DDI_DMA_SYNC_FORCPU); 2384 2385 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2386 "==> nxge_receive_packet: after first dump:usage count")); 2387 2388 if (rx_msg_p->cur_usage_cnt == 0) { 2389 if (rx_rbr_p->rbr_use_bcopy) { 2390 atomic_inc_32(&rx_rbr_p->rbr_consumed); 2391 if (rx_rbr_p->rbr_consumed < 2392 rx_rbr_p->rbr_threshold_hi) { 2393 if (rx_rbr_p->rbr_threshold_lo == 0 || 2394 ((rx_rbr_p->rbr_consumed >= 2395 rx_rbr_p->rbr_threshold_lo) && 2396 (rx_rbr_p->rbr_bufsize_type >= 2397 pktbufsz_type))) { 2398 rx_msg_p->rx_use_bcopy = B_TRUE; 2399 } 2400 } else { 2401 rx_msg_p->rx_use_bcopy = B_TRUE; 2402 } 2403 } 2404 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2405 "==> nxge_receive_packet: buf %d (new block) ", 2406 bsize)); 2407 2408 rx_msg_p->pkt_buf_size_code = pktbufsz_type; 2409 rx_msg_p->pkt_buf_size = bsize; 2410 rx_msg_p->cur_usage_cnt = 1; 2411 if (pktbufsz_type == RCR_SINGLE_BLOCK) { 2412 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2413 "==> nxge_receive_packet: buf %d " 2414 "(single block) ", 2415 bsize)); 2416 /* 2417 * Buffer can be reused once the free function 2418 * is called. 2419 */ 2420 rx_msg_p->max_usage_cnt = 1; 2421 buffer_free = B_TRUE; 2422 } else { 2423 rx_msg_p->max_usage_cnt = rx_msg_p->block_size/bsize; 2424 if (rx_msg_p->max_usage_cnt == 1) { 2425 buffer_free = B_TRUE; 2426 } 2427 } 2428 } else { 2429 rx_msg_p->cur_usage_cnt++; 2430 if (rx_msg_p->cur_usage_cnt == rx_msg_p->max_usage_cnt) { 2431 buffer_free = B_TRUE; 2432 } 2433 } 2434 2435 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2436 "msgbuf index = %d l2len %d bytes usage %d max_usage %d ", 2437 msg_index, l2_len, 2438 rx_msg_p->cur_usage_cnt, rx_msg_p->max_usage_cnt)); 2439 2440 if ((error_type) || (dcf_err) || (pkt_too_long_err)) { 2441 rdc_stats->ierrors++; 2442 if (dcf_err) { 2443 rdc_stats->dcf_err++; 2444 #ifdef NXGE_DEBUG 2445 if (!rdc_stats->dcf_err) { 2446 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2447 "nxge_receive_packet: channel %d dcf_err rcr" 2448 " 0x%llx", channel, rcr_entry)); 2449 } 2450 #endif 2451 NXGE_FM_REPORT_ERROR(nxgep, nxgep->mac.portnum, NULL, 2452 NXGE_FM_EREPORT_RDMC_DCF_ERR); 2453 } else if (pkt_too_long_err) { 2454 rdc_stats->pkt_too_long_err++; 2455 NXGE_DEBUG_MSG((nxgep, RX_CTL, " nxge_receive_packet:" 2456 " channel %d packet length [%d] > " 2457 "maxframesize [%d]", channel, l2_len + ETHERFCSL, 2458 nxgep->mac.maxframesize)); 2459 } else { 2460 /* Update error stats */ 2461 error_disp_cnt = NXGE_ERROR_SHOW_MAX; 2462 rdc_stats->errlog.compl_err_type = error_type; 2463 2464 switch (error_type) { 2465 /* 2466 * Do not send FMA ereport for RCR_L2_ERROR and 2467 * RCR_L4_CSUM_ERROR because most likely they indicate 2468 * back pressure rather than HW failures. 2469 */ 2470 case RCR_L2_ERROR: 2471 rdc_stats->l2_err++; 2472 if (rdc_stats->l2_err < 2473 error_disp_cnt) { 2474 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2475 " nxge_receive_packet:" 2476 " channel %d RCR L2_ERROR", 2477 channel)); 2478 } 2479 break; 2480 case RCR_L4_CSUM_ERROR: 2481 error_send_up = B_TRUE; 2482 rdc_stats->l4_cksum_err++; 2483 if (rdc_stats->l4_cksum_err < 2484 error_disp_cnt) { 2485 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2486 " nxge_receive_packet:" 2487 " channel %d" 2488 " RCR L4_CSUM_ERROR", channel)); 2489 } 2490 break; 2491 /* 2492 * Do not send FMA ereport for RCR_FFLP_SOFT_ERROR and 2493 * RCR_ZCP_SOFT_ERROR because they reflect the same 2494 * FFLP and ZCP errors that have been reported by 2495 * nxge_fflp.c and nxge_zcp.c. 2496 */ 2497 case RCR_FFLP_SOFT_ERROR: 2498 error_send_up = B_TRUE; 2499 rdc_stats->fflp_soft_err++; 2500 if (rdc_stats->fflp_soft_err < 2501 error_disp_cnt) { 2502 NXGE_ERROR_MSG((nxgep, 2503 NXGE_ERR_CTL, 2504 " nxge_receive_packet:" 2505 " channel %d" 2506 " RCR FFLP_SOFT_ERROR", channel)); 2507 } 2508 break; 2509 case RCR_ZCP_SOFT_ERROR: 2510 error_send_up = B_TRUE; 2511 rdc_stats->fflp_soft_err++; 2512 if (rdc_stats->zcp_soft_err < 2513 error_disp_cnt) 2514 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2515 " nxge_receive_packet: Channel %d" 2516 " RCR ZCP_SOFT_ERROR", channel)); 2517 break; 2518 default: 2519 rdc_stats->rcr_unknown_err++; 2520 if (rdc_stats->rcr_unknown_err 2521 < error_disp_cnt) { 2522 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2523 " nxge_receive_packet: Channel %d" 2524 " RCR entry 0x%llx error 0x%x", 2525 rcr_entry, channel, error_type)); 2526 } 2527 break; 2528 } 2529 } 2530 2531 /* 2532 * Update and repost buffer block if max usage 2533 * count is reached. 2534 */ 2535 if (error_send_up == B_FALSE) { 2536 atomic_inc_32(&rx_msg_p->ref_cnt); 2537 if (buffer_free == B_TRUE) { 2538 rx_msg_p->free = B_TRUE; 2539 } 2540 2541 MUTEX_EXIT(&rx_rbr_p->lock); 2542 MUTEX_EXIT(&rcr_p->lock); 2543 nxge_freeb(rx_msg_p); 2544 return; 2545 } 2546 } 2547 2548 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2549 "==> nxge_receive_packet: DMA sync second ")); 2550 2551 bytes_read = rcr_p->rcvd_pkt_bytes; 2552 skip_len = sw_offset_bytes + hdr_size; 2553 if (!rx_msg_p->rx_use_bcopy) { 2554 /* 2555 * For loaned up buffers, the driver reference count 2556 * will be incremented first and then the free state. 2557 */ 2558 if ((nmp = nxge_dupb(rx_msg_p, buf_offset, bsize)) != NULL) { 2559 if (first_entry) { 2560 nmp->b_rptr = &nmp->b_rptr[skip_len]; 2561 if (l2_len < bsize - skip_len) { 2562 nmp->b_wptr = &nmp->b_rptr[l2_len]; 2563 } else { 2564 nmp->b_wptr = &nmp->b_rptr[bsize 2565 - skip_len]; 2566 } 2567 } else { 2568 if (l2_len - bytes_read < bsize) { 2569 nmp->b_wptr = 2570 &nmp->b_rptr[l2_len - bytes_read]; 2571 } else { 2572 nmp->b_wptr = &nmp->b_rptr[bsize]; 2573 } 2574 } 2575 } 2576 } else { 2577 if (first_entry) { 2578 nmp = nxge_dupb_bcopy(rx_msg_p, buf_offset + skip_len, 2579 l2_len < bsize - skip_len ? 2580 l2_len : bsize - skip_len); 2581 } else { 2582 nmp = nxge_dupb_bcopy(rx_msg_p, buf_offset, 2583 l2_len - bytes_read < bsize ? 2584 l2_len - bytes_read : bsize); 2585 } 2586 } 2587 if (nmp != NULL) { 2588 if (first_entry) 2589 bytes_read = nmp->b_wptr - nmp->b_rptr; 2590 else 2591 bytes_read += nmp->b_wptr - nmp->b_rptr; 2592 2593 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2594 "==> nxge_receive_packet after dupb: " 2595 "rbr consumed %d " 2596 "pktbufsz_type %d " 2597 "nmp $%p rptr $%p wptr $%p " 2598 "buf_offset %d bzise %d l2_len %d skip_len %d", 2599 rx_rbr_p->rbr_consumed, 2600 pktbufsz_type, 2601 nmp, nmp->b_rptr, nmp->b_wptr, 2602 buf_offset, bsize, l2_len, skip_len)); 2603 } else { 2604 cmn_err(CE_WARN, "!nxge_receive_packet: " 2605 "update stats (error)"); 2606 atomic_inc_32(&rx_msg_p->ref_cnt); 2607 if (buffer_free == B_TRUE) { 2608 rx_msg_p->free = B_TRUE; 2609 } 2610 MUTEX_EXIT(&rx_rbr_p->lock); 2611 MUTEX_EXIT(&rcr_p->lock); 2612 nxge_freeb(rx_msg_p); 2613 return; 2614 } 2615 2616 if (buffer_free == B_TRUE) { 2617 rx_msg_p->free = B_TRUE; 2618 } 2619 /* 2620 * ERROR, FRAG and PKT_TYPE are only reported 2621 * in the first entry. 2622 * If a packet is not fragmented and no error bit is set, then 2623 * L4 checksum is OK. 2624 */ 2625 is_valid = (nmp != NULL); 2626 if (first_entry) { 2627 rdc_stats->ipackets++; /* count only 1st seg for jumbo */ 2628 rdc_stats->ibytes += skip_len + l2_len < bsize ? 2629 l2_len : bsize; 2630 } else { 2631 rdc_stats->ibytes += l2_len - bytes_read < bsize ? 2632 l2_len - bytes_read : bsize; 2633 } 2634 2635 rcr_p->rcvd_pkt_bytes = bytes_read; 2636 2637 MUTEX_EXIT(&rx_rbr_p->lock); 2638 MUTEX_EXIT(&rcr_p->lock); 2639 2640 if (rx_msg_p->free && rx_msg_p->rx_use_bcopy) { 2641 atomic_inc_32(&rx_msg_p->ref_cnt); 2642 nxge_freeb(rx_msg_p); 2643 } 2644 2645 if (is_valid) { 2646 nmp->b_cont = NULL; 2647 if (first_entry) { 2648 *mp = nmp; 2649 *mp_cont = NULL; 2650 } else { 2651 *mp_cont = nmp; 2652 } 2653 } 2654 2655 /* 2656 * Update stats and hardware checksuming. 2657 */ 2658 if (is_valid && !multi) { 2659 /* 2660 * If the checksum flag nxge_chksum_offload 2661 * is 1, TCP and UDP packets can be sent 2662 * up with good checksum. If the checksum flag 2663 * is set to 0, checksum reporting will apply to 2664 * TCP packets only (workaround for a hardware bug). 2665 * If the checksum flag nxge_cksum_offload is 2666 * greater than 1, both TCP and UDP packets 2667 * will not be reported its hardware checksum results. 2668 */ 2669 if (nxge_cksum_offload == 1) { 2670 is_tcp_udp = ((pkt_type == RCR_PKT_IS_TCP || 2671 pkt_type == RCR_PKT_IS_UDP) ? 2672 B_TRUE: B_FALSE); 2673 } else if (!nxge_cksum_offload) { 2674 /* TCP checksum only. */ 2675 is_tcp_udp = ((pkt_type == RCR_PKT_IS_TCP) ? 2676 B_TRUE: B_FALSE); 2677 } 2678 2679 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_receive_packet: " 2680 "is_valid 0x%x multi 0x%llx pkt %d frag %d error %d", 2681 is_valid, multi, is_tcp_udp, frag, error_type)); 2682 2683 if (is_tcp_udp && !frag && !error_type) { 2684 (void) hcksum_assoc(nmp, NULL, NULL, 0, 0, 0, 0, 2685 HCK_FULLCKSUM_OK | HCK_FULLCKSUM, 0); 2686 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2687 "==> nxge_receive_packet: Full tcp/udp cksum " 2688 "is_valid 0x%x multi 0x%llx pkt %d frag %d " 2689 "error %d", 2690 is_valid, multi, is_tcp_udp, frag, error_type)); 2691 } 2692 } 2693 2694 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2695 "==> nxge_receive_packet: *mp 0x%016llx", *mp)); 2696 2697 *multi_p = (multi == RCR_MULTI_MASK); 2698 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_receive_packet: " 2699 "multi %d nmp 0x%016llx *mp 0x%016llx *mp_cont 0x%016llx", 2700 *multi_p, nmp, *mp, *mp_cont)); 2701 } 2702 2703 /*ARGSUSED*/ 2704 static nxge_status_t 2705 nxge_rx_err_evnts(p_nxge_t nxgep, int channel, rx_dma_ctl_stat_t cs) 2706 { 2707 p_nxge_rx_ring_stats_t rdc_stats; 2708 npi_handle_t handle; 2709 npi_status_t rs; 2710 boolean_t rxchan_fatal = B_FALSE; 2711 boolean_t rxport_fatal = B_FALSE; 2712 uint8_t portn; 2713 nxge_status_t status = NXGE_OK; 2714 uint32_t error_disp_cnt = NXGE_ERROR_SHOW_MAX; 2715 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_rx_err_evnts")); 2716 2717 handle = NXGE_DEV_NPI_HANDLE(nxgep); 2718 portn = nxgep->mac.portnum; 2719 rdc_stats = &nxgep->statsp->rdc_stats[channel]; 2720 2721 if (cs.bits.hdw.rbr_tmout) { 2722 rdc_stats->rx_rbr_tmout++; 2723 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2724 NXGE_FM_EREPORT_RDMC_RBR_TMOUT); 2725 rxchan_fatal = B_TRUE; 2726 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2727 "==> nxge_rx_err_evnts: rx_rbr_timeout")); 2728 } 2729 if (cs.bits.hdw.rsp_cnt_err) { 2730 rdc_stats->rsp_cnt_err++; 2731 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2732 NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR); 2733 rxchan_fatal = B_TRUE; 2734 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2735 "==> nxge_rx_err_evnts(channel %d): " 2736 "rsp_cnt_err", channel)); 2737 } 2738 if (cs.bits.hdw.byte_en_bus) { 2739 rdc_stats->byte_en_bus++; 2740 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2741 NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS); 2742 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2743 "==> nxge_rx_err_evnts(channel %d): " 2744 "fatal error: byte_en_bus", channel)); 2745 rxchan_fatal = B_TRUE; 2746 } 2747 if (cs.bits.hdw.rsp_dat_err) { 2748 rdc_stats->rsp_dat_err++; 2749 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2750 NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR); 2751 rxchan_fatal = B_TRUE; 2752 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2753 "==> nxge_rx_err_evnts(channel %d): " 2754 "fatal error: rsp_dat_err", channel)); 2755 } 2756 if (cs.bits.hdw.rcr_ack_err) { 2757 rdc_stats->rcr_ack_err++; 2758 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2759 NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR); 2760 rxchan_fatal = B_TRUE; 2761 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2762 "==> nxge_rx_err_evnts(channel %d): " 2763 "fatal error: rcr_ack_err", channel)); 2764 } 2765 if (cs.bits.hdw.dc_fifo_err) { 2766 rdc_stats->dc_fifo_err++; 2767 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2768 NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR); 2769 /* This is not a fatal error! */ 2770 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2771 "==> nxge_rx_err_evnts(channel %d): " 2772 "dc_fifo_err", channel)); 2773 rxport_fatal = B_TRUE; 2774 } 2775 if ((cs.bits.hdw.rcr_sha_par) || (cs.bits.hdw.rbr_pre_par)) { 2776 if ((rs = npi_rxdma_ring_perr_stat_get(handle, 2777 &rdc_stats->errlog.pre_par, 2778 &rdc_stats->errlog.sha_par)) 2779 != NPI_SUCCESS) { 2780 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2781 "==> nxge_rx_err_evnts(channel %d): " 2782 "rcr_sha_par: get perr", channel)); 2783 return (NXGE_ERROR | rs); 2784 } 2785 if (cs.bits.hdw.rcr_sha_par) { 2786 rdc_stats->rcr_sha_par++; 2787 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2788 NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR); 2789 rxchan_fatal = B_TRUE; 2790 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2791 "==> nxge_rx_err_evnts(channel %d): " 2792 "fatal error: rcr_sha_par", channel)); 2793 } 2794 if (cs.bits.hdw.rbr_pre_par) { 2795 rdc_stats->rbr_pre_par++; 2796 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2797 NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR); 2798 rxchan_fatal = B_TRUE; 2799 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2800 "==> nxge_rx_err_evnts(channel %d): " 2801 "fatal error: rbr_pre_par", channel)); 2802 } 2803 } 2804 /* 2805 * The Following 4 status bits are for information, the system 2806 * is running fine. There is no need to send FMA ereports or 2807 * log messages. 2808 */ 2809 if (cs.bits.hdw.port_drop_pkt) { 2810 rdc_stats->port_drop_pkt++; 2811 } 2812 if (cs.bits.hdw.wred_drop) { 2813 rdc_stats->wred_drop++; 2814 } 2815 if (cs.bits.hdw.rbr_pre_empty) { 2816 rdc_stats->rbr_pre_empty++; 2817 } 2818 if (cs.bits.hdw.rcr_shadow_full) { 2819 rdc_stats->rcr_shadow_full++; 2820 } 2821 if (cs.bits.hdw.config_err) { 2822 rdc_stats->config_err++; 2823 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2824 NXGE_FM_EREPORT_RDMC_CONFIG_ERR); 2825 rxchan_fatal = B_TRUE; 2826 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2827 "==> nxge_rx_err_evnts(channel %d): " 2828 "config error", channel)); 2829 } 2830 if (cs.bits.hdw.rcrincon) { 2831 rdc_stats->rcrincon++; 2832 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2833 NXGE_FM_EREPORT_RDMC_RCRINCON); 2834 rxchan_fatal = B_TRUE; 2835 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2836 "==> nxge_rx_err_evnts(channel %d): " 2837 "fatal error: rcrincon error", channel)); 2838 } 2839 if (cs.bits.hdw.rcrfull) { 2840 rdc_stats->rcrfull++; 2841 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2842 NXGE_FM_EREPORT_RDMC_RCRFULL); 2843 rxchan_fatal = B_TRUE; 2844 if (rdc_stats->rcrfull < error_disp_cnt) 2845 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2846 "==> nxge_rx_err_evnts(channel %d): " 2847 "fatal error: rcrfull error", channel)); 2848 } 2849 if (cs.bits.hdw.rbr_empty) { 2850 /* 2851 * This bit is for information, there is no need 2852 * send FMA ereport or log a message. 2853 */ 2854 rdc_stats->rbr_empty++; 2855 } 2856 if (cs.bits.hdw.rbrfull) { 2857 rdc_stats->rbrfull++; 2858 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2859 NXGE_FM_EREPORT_RDMC_RBRFULL); 2860 rxchan_fatal = B_TRUE; 2861 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2862 "==> nxge_rx_err_evnts(channel %d): " 2863 "fatal error: rbr_full error", channel)); 2864 } 2865 if (cs.bits.hdw.rbrlogpage) { 2866 rdc_stats->rbrlogpage++; 2867 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2868 NXGE_FM_EREPORT_RDMC_RBRLOGPAGE); 2869 rxchan_fatal = B_TRUE; 2870 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2871 "==> nxge_rx_err_evnts(channel %d): " 2872 "fatal error: rbr logical page error", channel)); 2873 } 2874 if (cs.bits.hdw.cfiglogpage) { 2875 rdc_stats->cfiglogpage++; 2876 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2877 NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE); 2878 rxchan_fatal = B_TRUE; 2879 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2880 "==> nxge_rx_err_evnts(channel %d): " 2881 "fatal error: cfig logical page error", channel)); 2882 } 2883 2884 if (rxport_fatal) { 2885 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2886 " nxge_rx_err_evnts: fatal error on Port #%d\n", 2887 portn)); 2888 if (isLDOMguest(nxgep)) { 2889 status = NXGE_ERROR; 2890 } else { 2891 status = nxge_ipp_fatal_err_recover(nxgep); 2892 if (status == NXGE_OK) { 2893 FM_SERVICE_RESTORED(nxgep); 2894 } 2895 } 2896 } 2897 2898 if (rxchan_fatal) { 2899 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2900 " nxge_rx_err_evnts: fatal error on Channel #%d\n", 2901 channel)); 2902 if (isLDOMguest(nxgep)) { 2903 status = NXGE_ERROR; 2904 } else { 2905 status = nxge_rxdma_fatal_err_recover(nxgep, channel); 2906 if (status == NXGE_OK) { 2907 FM_SERVICE_RESTORED(nxgep); 2908 } 2909 } 2910 } 2911 2912 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "<== nxge_rx_err_evnts")); 2913 2914 return (status); 2915 } 2916 2917 /* 2918 * nxge_rdc_hvio_setup 2919 * 2920 * This code appears to setup some Hypervisor variables. 2921 * 2922 * Arguments: 2923 * nxgep 2924 * channel 2925 * 2926 * Notes: 2927 * What does NIU_LP_WORKAROUND mean? 2928 * 2929 * NPI/NXGE function calls: 2930 * na 2931 * 2932 * Context: 2933 * Any domain 2934 */ 2935 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2936 static void 2937 nxge_rdc_hvio_setup( 2938 nxge_t *nxgep, int channel) 2939 { 2940 nxge_dma_common_t *dma_common; 2941 nxge_dma_common_t *dma_control; 2942 rx_rbr_ring_t *ring; 2943 2944 ring = nxgep->rx_rbr_rings->rbr_rings[channel]; 2945 dma_common = nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 2946 2947 ring->hv_set = B_FALSE; 2948 2949 ring->hv_rx_buf_base_ioaddr_pp = (uint64_t) 2950 dma_common->orig_ioaddr_pp; 2951 ring->hv_rx_buf_ioaddr_size = (uint64_t) 2952 dma_common->orig_alength; 2953 2954 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_map_rxdma_channel: " 2955 "channel %d data buf base io $%lx ($%p) size 0x%lx (%ld 0x%lx)", 2956 channel, ring->hv_rx_buf_base_ioaddr_pp, 2957 dma_common->ioaddr_pp, ring->hv_rx_buf_ioaddr_size, 2958 dma_common->orig_alength, dma_common->orig_alength)); 2959 2960 dma_control = nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 2961 2962 ring->hv_rx_cntl_base_ioaddr_pp = 2963 (uint64_t)dma_control->orig_ioaddr_pp; 2964 ring->hv_rx_cntl_ioaddr_size = 2965 (uint64_t)dma_control->orig_alength; 2966 2967 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_map_rxdma_channel: " 2968 "channel %d cntl base io $%p ($%p) size 0x%llx (%d 0x%x)", 2969 channel, ring->hv_rx_cntl_base_ioaddr_pp, 2970 dma_control->ioaddr_pp, ring->hv_rx_cntl_ioaddr_size, 2971 dma_control->orig_alength, dma_control->orig_alength)); 2972 } 2973 #endif 2974 2975 /* 2976 * nxge_map_rxdma 2977 * 2978 * Map an RDC into our kernel space. 2979 * 2980 * Arguments: 2981 * nxgep 2982 * channel The channel to map. 2983 * 2984 * Notes: 2985 * 1. Allocate & initialise a memory pool, if necessary. 2986 * 2. Allocate however many receive buffers are required. 2987 * 3. Setup buffers, descriptors, and mailbox. 2988 * 2989 * NPI/NXGE function calls: 2990 * nxge_alloc_rx_mem_pool() 2991 * nxge_alloc_rbb() 2992 * nxge_map_rxdma_channel() 2993 * 2994 * Registers accessed: 2995 * 2996 * Context: 2997 * Any domain 2998 */ 2999 static nxge_status_t 3000 nxge_map_rxdma(p_nxge_t nxgep, int channel) 3001 { 3002 nxge_dma_common_t **data; 3003 nxge_dma_common_t **control; 3004 rx_rbr_ring_t **rbr_ring; 3005 rx_rcr_ring_t **rcr_ring; 3006 rx_mbox_t **mailbox; 3007 uint32_t chunks; 3008 3009 nxge_status_t status; 3010 3011 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_map_rxdma")); 3012 3013 if (!nxgep->rx_buf_pool_p) { 3014 if (nxge_alloc_rx_mem_pool(nxgep) != NXGE_OK) { 3015 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3016 "<== nxge_map_rxdma: buf not allocated")); 3017 return (NXGE_ERROR); 3018 } 3019 } 3020 3021 if (nxge_alloc_rxb(nxgep, channel) != NXGE_OK) 3022 return (NXGE_ERROR); 3023 3024 /* 3025 * Timeout should be set based on the system clock divider. 3026 * The following timeout value of 1 assumes that the 3027 * granularity (1000) is 3 microseconds running at 300MHz. 3028 */ 3029 3030 nxgep->intr_threshold = RXDMA_RCR_PTHRES_DEFAULT; 3031 nxgep->intr_timeout = RXDMA_RCR_TO_DEFAULT; 3032 3033 /* 3034 * Map descriptors from the buffer polls for each dma channel. 3035 */ 3036 3037 /* 3038 * Set up and prepare buffer blocks, descriptors 3039 * and mailbox. 3040 */ 3041 data = &nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 3042 rbr_ring = &nxgep->rx_rbr_rings->rbr_rings[channel]; 3043 chunks = nxgep->rx_buf_pool_p->num_chunks[channel]; 3044 3045 control = &nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 3046 rcr_ring = &nxgep->rx_rcr_rings->rcr_rings[channel]; 3047 3048 mailbox = &nxgep->rx_mbox_areas_p->rxmbox_areas[channel]; 3049 3050 status = nxge_map_rxdma_channel(nxgep, channel, data, rbr_ring, 3051 chunks, control, rcr_ring, mailbox); 3052 if (status != NXGE_OK) { 3053 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3054 "==> nxge_map_rxdma: nxge_map_rxdma_channel(%d) " 3055 "returned 0x%x", 3056 channel, status)); 3057 return (status); 3058 } 3059 nxgep->rx_rbr_rings->rbr_rings[channel]->index = (uint16_t)channel; 3060 nxgep->rx_rcr_rings->rcr_rings[channel]->index = (uint16_t)channel; 3061 nxgep->rx_rcr_rings->rcr_rings[channel]->rdc_stats = 3062 &nxgep->statsp->rdc_stats[channel]; 3063 3064 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3065 if (!isLDOMguest(nxgep)) 3066 nxge_rdc_hvio_setup(nxgep, channel); 3067 #endif 3068 3069 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3070 "<== nxge_map_rxdma: (status 0x%x channel %d)", status, channel)); 3071 3072 return (status); 3073 } 3074 3075 static void 3076 nxge_unmap_rxdma(p_nxge_t nxgep, int channel) 3077 { 3078 rx_rbr_ring_t *rbr_ring; 3079 rx_rcr_ring_t *rcr_ring; 3080 rx_mbox_t *mailbox; 3081 3082 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_unmap_rxdma(%d)", channel)); 3083 3084 if (!nxgep->rx_rbr_rings || !nxgep->rx_rcr_rings || 3085 !nxgep->rx_mbox_areas_p) 3086 return; 3087 3088 rbr_ring = nxgep->rx_rbr_rings->rbr_rings[channel]; 3089 rcr_ring = nxgep->rx_rcr_rings->rcr_rings[channel]; 3090 mailbox = nxgep->rx_mbox_areas_p->rxmbox_areas[channel]; 3091 3092 if (!rbr_ring || !rcr_ring || !mailbox) 3093 return; 3094 3095 (void) nxge_unmap_rxdma_channel( 3096 nxgep, channel, rbr_ring, rcr_ring, mailbox); 3097 3098 nxge_free_rxb(nxgep, channel); 3099 3100 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_unmap_rxdma")); 3101 } 3102 3103 nxge_status_t 3104 nxge_map_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 3105 p_nxge_dma_common_t *dma_buf_p, p_rx_rbr_ring_t *rbr_p, 3106 uint32_t num_chunks, 3107 p_nxge_dma_common_t *dma_cntl_p, p_rx_rcr_ring_t *rcr_p, 3108 p_rx_mbox_t *rx_mbox_p) 3109 { 3110 int status = NXGE_OK; 3111 3112 /* 3113 * Set up and prepare buffer blocks, descriptors 3114 * and mailbox. 3115 */ 3116 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3117 "==> nxge_map_rxdma_channel (channel %d)", channel)); 3118 /* 3119 * Receive buffer blocks 3120 */ 3121 status = nxge_map_rxdma_channel_buf_ring(nxgep, channel, 3122 dma_buf_p, rbr_p, num_chunks); 3123 if (status != NXGE_OK) { 3124 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3125 "==> nxge_map_rxdma_channel (channel %d): " 3126 "map buffer failed 0x%x", channel, status)); 3127 goto nxge_map_rxdma_channel_exit; 3128 } 3129 3130 /* 3131 * Receive block ring, completion ring and mailbox. 3132 */ 3133 status = nxge_map_rxdma_channel_cfg_ring(nxgep, channel, 3134 dma_cntl_p, rbr_p, rcr_p, rx_mbox_p); 3135 if (status != NXGE_OK) { 3136 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3137 "==> nxge_map_rxdma_channel (channel %d): " 3138 "map config failed 0x%x", channel, status)); 3139 goto nxge_map_rxdma_channel_fail2; 3140 } 3141 3142 goto nxge_map_rxdma_channel_exit; 3143 3144 nxge_map_rxdma_channel_fail3: 3145 /* Free rbr, rcr */ 3146 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3147 "==> nxge_map_rxdma_channel: free rbr/rcr " 3148 "(status 0x%x channel %d)", 3149 status, channel)); 3150 nxge_unmap_rxdma_channel_cfg_ring(nxgep, 3151 *rcr_p, *rx_mbox_p); 3152 3153 nxge_map_rxdma_channel_fail2: 3154 /* Free buffer blocks */ 3155 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3156 "==> nxge_map_rxdma_channel: free rx buffers" 3157 "(nxgep 0x%x status 0x%x channel %d)", 3158 nxgep, status, channel)); 3159 nxge_unmap_rxdma_channel_buf_ring(nxgep, *rbr_p); 3160 3161 status = NXGE_ERROR; 3162 3163 nxge_map_rxdma_channel_exit: 3164 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3165 "<== nxge_map_rxdma_channel: " 3166 "(nxgep 0x%x status 0x%x channel %d)", 3167 nxgep, status, channel)); 3168 3169 return (status); 3170 } 3171 3172 /*ARGSUSED*/ 3173 static void 3174 nxge_unmap_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 3175 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 3176 { 3177 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3178 "==> nxge_unmap_rxdma_channel (channel %d)", channel)); 3179 3180 /* 3181 * unmap receive block ring, completion ring and mailbox. 3182 */ 3183 (void) nxge_unmap_rxdma_channel_cfg_ring(nxgep, 3184 rcr_p, rx_mbox_p); 3185 3186 /* unmap buffer blocks */ 3187 (void) nxge_unmap_rxdma_channel_buf_ring(nxgep, rbr_p); 3188 3189 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_unmap_rxdma_channel")); 3190 } 3191 3192 /*ARGSUSED*/ 3193 static nxge_status_t 3194 nxge_map_rxdma_channel_cfg_ring(p_nxge_t nxgep, uint16_t dma_channel, 3195 p_nxge_dma_common_t *dma_cntl_p, p_rx_rbr_ring_t *rbr_p, 3196 p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p) 3197 { 3198 p_rx_rbr_ring_t rbrp; 3199 p_rx_rcr_ring_t rcrp; 3200 p_rx_mbox_t mboxp; 3201 p_nxge_dma_common_t cntl_dmap; 3202 p_nxge_dma_common_t dmap; 3203 p_rx_msg_t *rx_msg_ring; 3204 p_rx_msg_t rx_msg_p; 3205 p_rbr_cfig_a_t rcfga_p; 3206 p_rbr_cfig_b_t rcfgb_p; 3207 p_rcrcfig_a_t cfga_p; 3208 p_rcrcfig_b_t cfgb_p; 3209 p_rxdma_cfig1_t cfig1_p; 3210 p_rxdma_cfig2_t cfig2_p; 3211 p_rbr_kick_t kick_p; 3212 uint32_t dmaaddrp; 3213 uint32_t *rbr_vaddrp; 3214 uint32_t bkaddr; 3215 nxge_status_t status = NXGE_OK; 3216 int i; 3217 uint32_t nxge_port_rcr_size; 3218 3219 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3220 "==> nxge_map_rxdma_channel_cfg_ring")); 3221 3222 cntl_dmap = *dma_cntl_p; 3223 3224 /* Map in the receive block ring */ 3225 rbrp = *rbr_p; 3226 dmap = (p_nxge_dma_common_t)&rbrp->rbr_desc; 3227 nxge_setup_dma_common(dmap, cntl_dmap, rbrp->rbb_max, 4); 3228 /* 3229 * Zero out buffer block ring descriptors. 3230 */ 3231 bzero((caddr_t)dmap->kaddrp, dmap->alength); 3232 3233 rcfga_p = &(rbrp->rbr_cfga); 3234 rcfgb_p = &(rbrp->rbr_cfgb); 3235 kick_p = &(rbrp->rbr_kick); 3236 rcfga_p->value = 0; 3237 rcfgb_p->value = 0; 3238 kick_p->value = 0; 3239 rbrp->rbr_addr = dmap->dma_cookie.dmac_laddress; 3240 rcfga_p->value = (rbrp->rbr_addr & 3241 (RBR_CFIG_A_STDADDR_MASK | 3242 RBR_CFIG_A_STDADDR_BASE_MASK)); 3243 rcfga_p->value |= ((uint64_t)rbrp->rbb_max << RBR_CFIG_A_LEN_SHIFT); 3244 3245 rcfgb_p->bits.ldw.bufsz0 = rbrp->pkt_buf_size0; 3246 rcfgb_p->bits.ldw.vld0 = 1; 3247 rcfgb_p->bits.ldw.bufsz1 = rbrp->pkt_buf_size1; 3248 rcfgb_p->bits.ldw.vld1 = 1; 3249 rcfgb_p->bits.ldw.bufsz2 = rbrp->pkt_buf_size2; 3250 rcfgb_p->bits.ldw.vld2 = 1; 3251 rcfgb_p->bits.ldw.bksize = nxgep->rx_bksize_code; 3252 3253 /* 3254 * For each buffer block, enter receive block address to the ring. 3255 */ 3256 rbr_vaddrp = (uint32_t *)dmap->kaddrp; 3257 rbrp->rbr_desc_vp = (uint32_t *)dmap->kaddrp; 3258 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3259 "==> nxge_map_rxdma_channel_cfg_ring: channel %d " 3260 "rbr_vaddrp $%p", dma_channel, rbr_vaddrp)); 3261 3262 rx_msg_ring = rbrp->rx_msg_ring; 3263 for (i = 0; i < rbrp->tnblocks; i++) { 3264 rx_msg_p = rx_msg_ring[i]; 3265 rx_msg_p->nxgep = nxgep; 3266 rx_msg_p->rx_rbr_p = rbrp; 3267 bkaddr = (uint32_t) 3268 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress 3269 >> RBR_BKADDR_SHIFT)); 3270 rx_msg_p->free = B_FALSE; 3271 rx_msg_p->max_usage_cnt = 0xbaddcafe; 3272 3273 *rbr_vaddrp++ = bkaddr; 3274 } 3275 3276 kick_p->bits.ldw.bkadd = rbrp->rbb_max; 3277 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 3278 3279 rbrp->rbr_rd_index = 0; 3280 3281 rbrp->rbr_consumed = 0; 3282 rbrp->rbr_use_bcopy = B_TRUE; 3283 rbrp->rbr_bufsize_type = RCR_PKTBUFSZ_0; 3284 /* 3285 * Do bcopy on packets greater than bcopy size once 3286 * the lo threshold is reached. 3287 * This lo threshold should be less than the hi threshold. 3288 * 3289 * Do bcopy on every packet once the hi threshold is reached. 3290 */ 3291 if (nxge_rx_threshold_lo >= nxge_rx_threshold_hi) { 3292 /* default it to use hi */ 3293 nxge_rx_threshold_lo = nxge_rx_threshold_hi; 3294 } 3295 3296 if (nxge_rx_buf_size_type > NXGE_RBR_TYPE2) { 3297 nxge_rx_buf_size_type = NXGE_RBR_TYPE2; 3298 } 3299 rbrp->rbr_bufsize_type = nxge_rx_buf_size_type; 3300 3301 switch (nxge_rx_threshold_hi) { 3302 default: 3303 case NXGE_RX_COPY_NONE: 3304 /* Do not do bcopy at all */ 3305 rbrp->rbr_use_bcopy = B_FALSE; 3306 rbrp->rbr_threshold_hi = rbrp->rbb_max; 3307 break; 3308 3309 case NXGE_RX_COPY_1: 3310 case NXGE_RX_COPY_2: 3311 case NXGE_RX_COPY_3: 3312 case NXGE_RX_COPY_4: 3313 case NXGE_RX_COPY_5: 3314 case NXGE_RX_COPY_6: 3315 case NXGE_RX_COPY_7: 3316 rbrp->rbr_threshold_hi = 3317 rbrp->rbb_max * 3318 (nxge_rx_threshold_hi)/NXGE_RX_BCOPY_SCALE; 3319 break; 3320 3321 case NXGE_RX_COPY_ALL: 3322 rbrp->rbr_threshold_hi = 0; 3323 break; 3324 } 3325 3326 switch (nxge_rx_threshold_lo) { 3327 default: 3328 case NXGE_RX_COPY_NONE: 3329 /* Do not do bcopy at all */ 3330 if (rbrp->rbr_use_bcopy) { 3331 rbrp->rbr_use_bcopy = B_FALSE; 3332 } 3333 rbrp->rbr_threshold_lo = rbrp->rbb_max; 3334 break; 3335 3336 case NXGE_RX_COPY_1: 3337 case NXGE_RX_COPY_2: 3338 case NXGE_RX_COPY_3: 3339 case NXGE_RX_COPY_4: 3340 case NXGE_RX_COPY_5: 3341 case NXGE_RX_COPY_6: 3342 case NXGE_RX_COPY_7: 3343 rbrp->rbr_threshold_lo = 3344 rbrp->rbb_max * 3345 (nxge_rx_threshold_lo)/NXGE_RX_BCOPY_SCALE; 3346 break; 3347 3348 case NXGE_RX_COPY_ALL: 3349 rbrp->rbr_threshold_lo = 0; 3350 break; 3351 } 3352 3353 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3354 "nxge_map_rxdma_channel_cfg_ring: channel %d " 3355 "rbb_max %d " 3356 "rbrp->rbr_bufsize_type %d " 3357 "rbb_threshold_hi %d " 3358 "rbb_threshold_lo %d", 3359 dma_channel, 3360 rbrp->rbb_max, 3361 rbrp->rbr_bufsize_type, 3362 rbrp->rbr_threshold_hi, 3363 rbrp->rbr_threshold_lo)); 3364 3365 rbrp->page_valid.value = 0; 3366 rbrp->page_mask_1.value = rbrp->page_mask_2.value = 0; 3367 rbrp->page_value_1.value = rbrp->page_value_2.value = 0; 3368 rbrp->page_reloc_1.value = rbrp->page_reloc_2.value = 0; 3369 rbrp->page_hdl.value = 0; 3370 3371 rbrp->page_valid.bits.ldw.page0 = 1; 3372 rbrp->page_valid.bits.ldw.page1 = 1; 3373 3374 /* Map in the receive completion ring */ 3375 rcrp = (p_rx_rcr_ring_t) 3376 KMEM_ZALLOC(sizeof (rx_rcr_ring_t), KM_SLEEP); 3377 rcrp->rdc = dma_channel; 3378 3379 nxge_port_rcr_size = nxgep->nxge_port_rcr_size; 3380 rcrp->comp_size = nxge_port_rcr_size; 3381 rcrp->comp_wrap_mask = nxge_port_rcr_size - 1; 3382 3383 rcrp->max_receive_pkts = nxge_max_rx_pkts; 3384 3385 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 3386 nxge_setup_dma_common(dmap, cntl_dmap, rcrp->comp_size, 3387 sizeof (rcr_entry_t)); 3388 rcrp->comp_rd_index = 0; 3389 rcrp->comp_wt_index = 0; 3390 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 3391 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 3392 #if defined(__i386) 3393 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 3394 (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3395 #else 3396 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 3397 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3398 #endif 3399 3400 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 3401 (nxge_port_rcr_size - 1); 3402 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 3403 (nxge_port_rcr_size - 1); 3404 3405 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3406 "==> nxge_map_rxdma_channel_cfg_ring: " 3407 "channel %d " 3408 "rbr_vaddrp $%p " 3409 "rcr_desc_rd_head_p $%p " 3410 "rcr_desc_rd_head_pp $%p " 3411 "rcr_desc_rd_last_p $%p " 3412 "rcr_desc_rd_last_pp $%p ", 3413 dma_channel, 3414 rbr_vaddrp, 3415 rcrp->rcr_desc_rd_head_p, 3416 rcrp->rcr_desc_rd_head_pp, 3417 rcrp->rcr_desc_last_p, 3418 rcrp->rcr_desc_last_pp)); 3419 3420 /* 3421 * Zero out buffer block ring descriptors. 3422 */ 3423 bzero((caddr_t)dmap->kaddrp, dmap->alength); 3424 rcrp->intr_timeout = nxgep->intr_timeout; 3425 rcrp->intr_threshold = nxgep->intr_threshold; 3426 rcrp->full_hdr_flag = B_FALSE; 3427 rcrp->sw_priv_hdr_len = 0; 3428 3429 cfga_p = &(rcrp->rcr_cfga); 3430 cfgb_p = &(rcrp->rcr_cfgb); 3431 cfga_p->value = 0; 3432 cfgb_p->value = 0; 3433 rcrp->rcr_addr = dmap->dma_cookie.dmac_laddress; 3434 cfga_p->value = (rcrp->rcr_addr & 3435 (RCRCFIG_A_STADDR_MASK | 3436 RCRCFIG_A_STADDR_BASE_MASK)); 3437 3438 rcfga_p->value |= ((uint64_t)rcrp->comp_size << 3439 RCRCFIG_A_LEN_SHIF); 3440 3441 /* 3442 * Timeout should be set based on the system clock divider. 3443 * The following timeout value of 1 assumes that the 3444 * granularity (1000) is 3 microseconds running at 300MHz. 3445 */ 3446 cfgb_p->bits.ldw.pthres = rcrp->intr_threshold; 3447 cfgb_p->bits.ldw.timeout = rcrp->intr_timeout; 3448 cfgb_p->bits.ldw.entout = 1; 3449 3450 /* Map in the mailbox */ 3451 mboxp = (p_rx_mbox_t) 3452 KMEM_ZALLOC(sizeof (rx_mbox_t), KM_SLEEP); 3453 dmap = (p_nxge_dma_common_t)&mboxp->rx_mbox; 3454 nxge_setup_dma_common(dmap, cntl_dmap, 1, sizeof (rxdma_mailbox_t)); 3455 cfig1_p = (p_rxdma_cfig1_t)&mboxp->rx_cfg1; 3456 cfig2_p = (p_rxdma_cfig2_t)&mboxp->rx_cfg2; 3457 cfig1_p->value = cfig2_p->value = 0; 3458 3459 mboxp->mbox_addr = dmap->dma_cookie.dmac_laddress; 3460 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3461 "==> nxge_map_rxdma_channel_cfg_ring: " 3462 "channel %d cfg1 0x%016llx cfig2 0x%016llx cookie 0x%016llx", 3463 dma_channel, cfig1_p->value, cfig2_p->value, 3464 mboxp->mbox_addr)); 3465 3466 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress >> 32 3467 & 0xfff); 3468 cfig1_p->bits.ldw.mbaddr_h = dmaaddrp; 3469 3470 3471 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 0xffffffff); 3472 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 3473 RXDMA_CFIG2_MBADDR_L_MASK); 3474 3475 cfig2_p->bits.ldw.mbaddr = (dmaaddrp >> RXDMA_CFIG2_MBADDR_L_SHIFT); 3476 3477 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3478 "==> nxge_map_rxdma_channel_cfg_ring: " 3479 "channel %d damaddrp $%p " 3480 "cfg1 0x%016llx cfig2 0x%016llx", 3481 dma_channel, dmaaddrp, 3482 cfig1_p->value, cfig2_p->value)); 3483 3484 cfig2_p->bits.ldw.full_hdr = rcrp->full_hdr_flag; 3485 cfig2_p->bits.ldw.offset = rcrp->sw_priv_hdr_len; 3486 3487 rbrp->rx_rcr_p = rcrp; 3488 rcrp->rx_rbr_p = rbrp; 3489 *rcr_p = rcrp; 3490 *rx_mbox_p = mboxp; 3491 3492 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3493 "<== nxge_map_rxdma_channel_cfg_ring status 0x%08x", status)); 3494 3495 return (status); 3496 } 3497 3498 /*ARGSUSED*/ 3499 static void 3500 nxge_unmap_rxdma_channel_cfg_ring(p_nxge_t nxgep, 3501 p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 3502 { 3503 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3504 "==> nxge_unmap_rxdma_channel_cfg_ring: channel %d", 3505 rcr_p->rdc)); 3506 3507 KMEM_FREE(rcr_p, sizeof (rx_rcr_ring_t)); 3508 KMEM_FREE(rx_mbox_p, sizeof (rx_mbox_t)); 3509 3510 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3511 "<== nxge_unmap_rxdma_channel_cfg_ring")); 3512 } 3513 3514 static nxge_status_t 3515 nxge_map_rxdma_channel_buf_ring(p_nxge_t nxgep, uint16_t channel, 3516 p_nxge_dma_common_t *dma_buf_p, 3517 p_rx_rbr_ring_t *rbr_p, uint32_t num_chunks) 3518 { 3519 p_rx_rbr_ring_t rbrp; 3520 p_nxge_dma_common_t dma_bufp, tmp_bufp; 3521 p_rx_msg_t *rx_msg_ring; 3522 p_rx_msg_t rx_msg_p; 3523 p_mblk_t mblk_p; 3524 3525 rxring_info_t *ring_info; 3526 nxge_status_t status = NXGE_OK; 3527 int i, j, index; 3528 uint32_t size, bsize, nblocks, nmsgs; 3529 3530 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3531 "==> nxge_map_rxdma_channel_buf_ring: channel %d", 3532 channel)); 3533 3534 dma_bufp = tmp_bufp = *dma_buf_p; 3535 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3536 " nxge_map_rxdma_channel_buf_ring: channel %d to map %d " 3537 "chunks bufp 0x%016llx", 3538 channel, num_chunks, dma_bufp)); 3539 3540 nmsgs = 0; 3541 for (i = 0; i < num_chunks; i++, tmp_bufp++) { 3542 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3543 "==> nxge_map_rxdma_channel_buf_ring: channel %d " 3544 "bufp 0x%016llx nblocks %d nmsgs %d", 3545 channel, tmp_bufp, tmp_bufp->nblocks, nmsgs)); 3546 nmsgs += tmp_bufp->nblocks; 3547 } 3548 if (!nmsgs) { 3549 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3550 "<== nxge_map_rxdma_channel_buf_ring: channel %d " 3551 "no msg blocks", 3552 channel)); 3553 status = NXGE_ERROR; 3554 goto nxge_map_rxdma_channel_buf_ring_exit; 3555 } 3556 3557 rbrp = (p_rx_rbr_ring_t)KMEM_ZALLOC(sizeof (*rbrp), KM_SLEEP); 3558 3559 size = nmsgs * sizeof (p_rx_msg_t); 3560 rx_msg_ring = KMEM_ZALLOC(size, KM_SLEEP); 3561 ring_info = (rxring_info_t *)KMEM_ZALLOC(sizeof (rxring_info_t), 3562 KM_SLEEP); 3563 3564 MUTEX_INIT(&rbrp->lock, NULL, MUTEX_DRIVER, 3565 (void *)nxgep->interrupt_cookie); 3566 MUTEX_INIT(&rbrp->post_lock, NULL, MUTEX_DRIVER, 3567 (void *)nxgep->interrupt_cookie); 3568 rbrp->rdc = channel; 3569 rbrp->num_blocks = num_chunks; 3570 rbrp->tnblocks = nmsgs; 3571 rbrp->rbb_max = nmsgs; 3572 rbrp->rbr_max_size = nmsgs; 3573 rbrp->rbr_wrap_mask = (rbrp->rbb_max - 1); 3574 3575 /* 3576 * Buffer sizes suggested by NIU architect. 3577 * 256, 512 and 2K. 3578 */ 3579 3580 rbrp->pkt_buf_size0 = RBR_BUFSZ0_256B; 3581 rbrp->pkt_buf_size0_bytes = RBR_BUFSZ0_256_BYTES; 3582 rbrp->npi_pkt_buf_size0 = SIZE_256B; 3583 3584 rbrp->pkt_buf_size1 = RBR_BUFSZ1_1K; 3585 rbrp->pkt_buf_size1_bytes = RBR_BUFSZ1_1K_BYTES; 3586 rbrp->npi_pkt_buf_size1 = SIZE_1KB; 3587 3588 rbrp->block_size = nxgep->rx_default_block_size; 3589 3590 if (!nxge_jumbo_enable && !nxgep->param_arr[param_accept_jumbo].value) { 3591 rbrp->pkt_buf_size2 = RBR_BUFSZ2_2K; 3592 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_2K_BYTES; 3593 rbrp->npi_pkt_buf_size2 = SIZE_2KB; 3594 } else { 3595 if (rbrp->block_size >= 0x2000) { 3596 rbrp->pkt_buf_size2 = RBR_BUFSZ2_8K; 3597 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_8K_BYTES; 3598 rbrp->npi_pkt_buf_size2 = SIZE_8KB; 3599 } else { 3600 rbrp->pkt_buf_size2 = RBR_BUFSZ2_4K; 3601 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_4K_BYTES; 3602 rbrp->npi_pkt_buf_size2 = SIZE_4KB; 3603 } 3604 } 3605 3606 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3607 "==> nxge_map_rxdma_channel_buf_ring: channel %d " 3608 "actual rbr max %d rbb_max %d nmsgs %d " 3609 "rbrp->block_size %d default_block_size %d " 3610 "(config nxge_rbr_size %d nxge_rbr_spare_size %d)", 3611 channel, rbrp->rbr_max_size, rbrp->rbb_max, nmsgs, 3612 rbrp->block_size, nxgep->rx_default_block_size, 3613 nxge_rbr_size, nxge_rbr_spare_size)); 3614 3615 /* Map in buffers from the buffer pool. */ 3616 index = 0; 3617 for (i = 0; i < rbrp->num_blocks; i++, dma_bufp++) { 3618 bsize = dma_bufp->block_size; 3619 nblocks = dma_bufp->nblocks; 3620 #if defined(__i386) 3621 ring_info->buffer[i].dvma_addr = (uint32_t)dma_bufp->ioaddr_pp; 3622 #else 3623 ring_info->buffer[i].dvma_addr = (uint64_t)dma_bufp->ioaddr_pp; 3624 #endif 3625 ring_info->buffer[i].buf_index = i; 3626 ring_info->buffer[i].buf_size = dma_bufp->alength; 3627 ring_info->buffer[i].start_index = index; 3628 #if defined(__i386) 3629 ring_info->buffer[i].kaddr = (uint32_t)dma_bufp->kaddrp; 3630 #else 3631 ring_info->buffer[i].kaddr = (uint64_t)dma_bufp->kaddrp; 3632 #endif 3633 3634 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3635 " nxge_map_rxdma_channel_buf_ring: map channel %d " 3636 "chunk %d" 3637 " nblocks %d chunk_size %x block_size 0x%x " 3638 "dma_bufp $%p", channel, i, 3639 dma_bufp->nblocks, ring_info->buffer[i].buf_size, bsize, 3640 dma_bufp)); 3641 3642 for (j = 0; j < nblocks; j++) { 3643 if ((rx_msg_p = nxge_allocb(bsize, BPRI_LO, 3644 dma_bufp)) == NULL) { 3645 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3646 "allocb failed (index %d i %d j %d)", 3647 index, i, j)); 3648 goto nxge_map_rxdma_channel_buf_ring_fail1; 3649 } 3650 rx_msg_ring[index] = rx_msg_p; 3651 rx_msg_p->block_index = index; 3652 rx_msg_p->shifted_addr = (uint32_t) 3653 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress >> 3654 RBR_BKADDR_SHIFT)); 3655 3656 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3657 "index %d j %d rx_msg_p $%p mblk %p", 3658 index, j, rx_msg_p, rx_msg_p->rx_mblk_p)); 3659 3660 mblk_p = rx_msg_p->rx_mblk_p; 3661 mblk_p->b_wptr = mblk_p->b_rptr + bsize; 3662 3663 rbrp->rbr_ref_cnt++; 3664 index++; 3665 rx_msg_p->buf_dma.dma_channel = channel; 3666 } 3667 3668 rbrp->rbr_alloc_type = DDI_MEM_ALLOC; 3669 if (dma_bufp->contig_alloc_type) { 3670 rbrp->rbr_alloc_type = CONTIG_MEM_ALLOC; 3671 } 3672 3673 if (dma_bufp->kmem_alloc_type) { 3674 rbrp->rbr_alloc_type = KMEM_ALLOC; 3675 } 3676 3677 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3678 " nxge_map_rxdma_channel_buf_ring: map channel %d " 3679 "chunk %d" 3680 " nblocks %d chunk_size %x block_size 0x%x " 3681 "dma_bufp $%p", 3682 channel, i, 3683 dma_bufp->nblocks, ring_info->buffer[i].buf_size, bsize, 3684 dma_bufp)); 3685 } 3686 if (i < rbrp->num_blocks) { 3687 goto nxge_map_rxdma_channel_buf_ring_fail1; 3688 } 3689 3690 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3691 "nxge_map_rxdma_channel_buf_ring: done buf init " 3692 "channel %d msg block entries %d", 3693 channel, index)); 3694 ring_info->block_size_mask = bsize - 1; 3695 rbrp->rx_msg_ring = rx_msg_ring; 3696 rbrp->dma_bufp = dma_buf_p; 3697 rbrp->ring_info = ring_info; 3698 3699 status = nxge_rxbuf_index_info_init(nxgep, rbrp); 3700 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3701 " nxge_map_rxdma_channel_buf_ring: " 3702 "channel %d done buf info init", channel)); 3703 3704 /* 3705 * Finally, permit nxge_freeb() to call nxge_post_page(). 3706 */ 3707 rbrp->rbr_state = RBR_POSTING; 3708 3709 *rbr_p = rbrp; 3710 goto nxge_map_rxdma_channel_buf_ring_exit; 3711 3712 nxge_map_rxdma_channel_buf_ring_fail1: 3713 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3714 " nxge_map_rxdma_channel_buf_ring: failed channel (0x%x)", 3715 channel, status)); 3716 3717 index--; 3718 for (; index >= 0; index--) { 3719 rx_msg_p = rx_msg_ring[index]; 3720 if (rx_msg_p != NULL) { 3721 freeb(rx_msg_p->rx_mblk_p); 3722 rx_msg_ring[index] = NULL; 3723 } 3724 } 3725 nxge_map_rxdma_channel_buf_ring_fail: 3726 MUTEX_DESTROY(&rbrp->post_lock); 3727 MUTEX_DESTROY(&rbrp->lock); 3728 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 3729 KMEM_FREE(rx_msg_ring, size); 3730 KMEM_FREE(rbrp, sizeof (rx_rbr_ring_t)); 3731 3732 status = NXGE_ERROR; 3733 3734 nxge_map_rxdma_channel_buf_ring_exit: 3735 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3736 "<== nxge_map_rxdma_channel_buf_ring status 0x%08x", status)); 3737 3738 return (status); 3739 } 3740 3741 /*ARGSUSED*/ 3742 static void 3743 nxge_unmap_rxdma_channel_buf_ring(p_nxge_t nxgep, 3744 p_rx_rbr_ring_t rbr_p) 3745 { 3746 p_rx_msg_t *rx_msg_ring; 3747 p_rx_msg_t rx_msg_p; 3748 rxring_info_t *ring_info; 3749 int i; 3750 uint32_t size; 3751 #ifdef NXGE_DEBUG 3752 int num_chunks; 3753 #endif 3754 3755 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3756 "==> nxge_unmap_rxdma_channel_buf_ring")); 3757 if (rbr_p == NULL) { 3758 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3759 "<== nxge_unmap_rxdma_channel_buf_ring: NULL rbrp")); 3760 return; 3761 } 3762 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3763 "==> nxge_unmap_rxdma_channel_buf_ring: channel %d", 3764 rbr_p->rdc)); 3765 3766 rx_msg_ring = rbr_p->rx_msg_ring; 3767 ring_info = rbr_p->ring_info; 3768 3769 if (rx_msg_ring == NULL || ring_info == NULL) { 3770 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3771 "<== nxge_unmap_rxdma_channel_buf_ring: " 3772 "rx_msg_ring $%p ring_info $%p", 3773 rx_msg_p, ring_info)); 3774 return; 3775 } 3776 3777 #ifdef NXGE_DEBUG 3778 num_chunks = rbr_p->num_blocks; 3779 #endif 3780 size = rbr_p->tnblocks * sizeof (p_rx_msg_t); 3781 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3782 " nxge_unmap_rxdma_channel_buf_ring: channel %d chunks %d " 3783 "tnblocks %d (max %d) size ptrs %d ", 3784 rbr_p->rdc, num_chunks, 3785 rbr_p->tnblocks, rbr_p->rbr_max_size, size)); 3786 3787 for (i = 0; i < rbr_p->tnblocks; i++) { 3788 rx_msg_p = rx_msg_ring[i]; 3789 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3790 " nxge_unmap_rxdma_channel_buf_ring: " 3791 "rx_msg_p $%p", 3792 rx_msg_p)); 3793 if (rx_msg_p != NULL) { 3794 freeb(rx_msg_p->rx_mblk_p); 3795 rx_msg_ring[i] = NULL; 3796 } 3797 } 3798 3799 /* 3800 * We no longer may use the mutex <post_lock>. By setting 3801 * <rbr_state> to anything but POSTING, we prevent 3802 * nxge_post_page() from accessing a dead mutex. 3803 */ 3804 rbr_p->rbr_state = RBR_UNMAPPING; 3805 MUTEX_DESTROY(&rbr_p->post_lock); 3806 3807 MUTEX_DESTROY(&rbr_p->lock); 3808 3809 if (rbr_p->rbr_ref_cnt == 0) { 3810 /* 3811 * This is the normal state of affairs. 3812 * Need to free the following buffers: 3813 * - data buffers 3814 * - rx_msg ring 3815 * - ring_info 3816 * - rbr ring 3817 */ 3818 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3819 "unmap_rxdma_buf_ring: No outstanding - freeing ")); 3820 nxge_rxdma_databuf_free(rbr_p); 3821 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 3822 KMEM_FREE(rx_msg_ring, size); 3823 KMEM_FREE(rbr_p, sizeof (*rbr_p)); 3824 } else { 3825 /* 3826 * Some of our buffers are still being used. 3827 * Therefore, tell nxge_freeb() this ring is 3828 * unmapped, so it may free <rbr_p> for us. 3829 */ 3830 rbr_p->rbr_state = RBR_UNMAPPED; 3831 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3832 "unmap_rxdma_buf_ring: %d %s outstanding.", 3833 rbr_p->rbr_ref_cnt, 3834 rbr_p->rbr_ref_cnt == 1 ? "msg" : "msgs")); 3835 } 3836 3837 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3838 "<== nxge_unmap_rxdma_channel_buf_ring")); 3839 } 3840 3841 /* 3842 * nxge_rxdma_hw_start_common 3843 * 3844 * Arguments: 3845 * nxgep 3846 * 3847 * Notes: 3848 * 3849 * NPI/NXGE function calls: 3850 * nxge_init_fzc_rx_common(); 3851 * nxge_init_fzc_rxdma_port(); 3852 * 3853 * Registers accessed: 3854 * 3855 * Context: 3856 * Service domain 3857 */ 3858 static nxge_status_t 3859 nxge_rxdma_hw_start_common(p_nxge_t nxgep) 3860 { 3861 nxge_status_t status = NXGE_OK; 3862 3863 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start_common")); 3864 3865 /* 3866 * Load the sharable parameters by writing to the 3867 * function zero control registers. These FZC registers 3868 * should be initialized only once for the entire chip. 3869 */ 3870 (void) nxge_init_fzc_rx_common(nxgep); 3871 3872 /* 3873 * Initialize the RXDMA port specific FZC control configurations. 3874 * These FZC registers are pertaining to each port. 3875 */ 3876 (void) nxge_init_fzc_rxdma_port(nxgep); 3877 3878 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start_common")); 3879 3880 return (status); 3881 } 3882 3883 static nxge_status_t 3884 nxge_rxdma_hw_start(p_nxge_t nxgep, int channel) 3885 { 3886 int i, ndmas; 3887 p_rx_rbr_rings_t rx_rbr_rings; 3888 p_rx_rbr_ring_t *rbr_rings; 3889 p_rx_rcr_rings_t rx_rcr_rings; 3890 p_rx_rcr_ring_t *rcr_rings; 3891 p_rx_mbox_areas_t rx_mbox_areas_p; 3892 p_rx_mbox_t *rx_mbox_p; 3893 nxge_status_t status = NXGE_OK; 3894 3895 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start")); 3896 3897 rx_rbr_rings = nxgep->rx_rbr_rings; 3898 rx_rcr_rings = nxgep->rx_rcr_rings; 3899 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 3900 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3901 "<== nxge_rxdma_hw_start: NULL ring pointers")); 3902 return (NXGE_ERROR); 3903 } 3904 ndmas = rx_rbr_rings->ndmas; 3905 if (ndmas == 0) { 3906 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3907 "<== nxge_rxdma_hw_start: no dma channel allocated")); 3908 return (NXGE_ERROR); 3909 } 3910 3911 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3912 "==> nxge_rxdma_hw_start (ndmas %d)", ndmas)); 3913 3914 rbr_rings = rx_rbr_rings->rbr_rings; 3915 rcr_rings = rx_rcr_rings->rcr_rings; 3916 rx_mbox_areas_p = nxgep->rx_mbox_areas_p; 3917 if (rx_mbox_areas_p) { 3918 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 3919 } 3920 3921 i = channel; 3922 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3923 "==> nxge_rxdma_hw_start (ndmas %d) channel %d", 3924 ndmas, channel)); 3925 status = nxge_rxdma_start_channel(nxgep, channel, 3926 (p_rx_rbr_ring_t)rbr_rings[i], 3927 (p_rx_rcr_ring_t)rcr_rings[i], 3928 (p_rx_mbox_t)rx_mbox_p[i]); 3929 if (status != NXGE_OK) { 3930 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3931 "==> nxge_rxdma_hw_start: disable " 3932 "(status 0x%x channel %d)", status, channel)); 3933 return (status); 3934 } 3935 3936 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start: " 3937 "rx_rbr_rings 0x%016llx rings 0x%016llx", 3938 rx_rbr_rings, rx_rcr_rings)); 3939 3940 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3941 "==> nxge_rxdma_hw_start: (status 0x%x)", status)); 3942 3943 return (status); 3944 } 3945 3946 static void 3947 nxge_rxdma_hw_stop(p_nxge_t nxgep, int channel) 3948 { 3949 p_rx_rbr_rings_t rx_rbr_rings; 3950 p_rx_rcr_rings_t rx_rcr_rings; 3951 3952 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop")); 3953 3954 rx_rbr_rings = nxgep->rx_rbr_rings; 3955 rx_rcr_rings = nxgep->rx_rcr_rings; 3956 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 3957 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3958 "<== nxge_rxdma_hw_stop: NULL ring pointers")); 3959 return; 3960 } 3961 3962 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3963 "==> nxge_rxdma_hw_stop(channel %d)", 3964 channel)); 3965 (void) nxge_rxdma_stop_channel(nxgep, channel); 3966 3967 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop: " 3968 "rx_rbr_rings 0x%016llx rings 0x%016llx", 3969 rx_rbr_rings, rx_rcr_rings)); 3970 3971 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_rxdma_hw_stop")); 3972 } 3973 3974 3975 static nxge_status_t 3976 nxge_rxdma_start_channel(p_nxge_t nxgep, uint16_t channel, 3977 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p) 3978 3979 { 3980 npi_handle_t handle; 3981 npi_status_t rs = NPI_SUCCESS; 3982 rx_dma_ctl_stat_t cs; 3983 rx_dma_ent_msk_t ent_mask; 3984 nxge_status_t status = NXGE_OK; 3985 3986 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel")); 3987 3988 handle = NXGE_DEV_NPI_HANDLE(nxgep); 3989 3990 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "nxge_rxdma_start_channel: " 3991 "npi handle addr $%p acc $%p", 3992 nxgep->npi_handle.regp, nxgep->npi_handle.regh)); 3993 3994 /* Reset RXDMA channel, but not if you're a guest. */ 3995 if (!isLDOMguest(nxgep)) { 3996 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 3997 if (rs != NPI_SUCCESS) { 3998 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3999 "==> nxge_init_fzc_rdc: " 4000 "npi_rxdma_cfg_rdc_reset(%d) returned 0x%08x", 4001 channel, rs)); 4002 return (NXGE_ERROR | rs); 4003 } 4004 4005 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4006 "==> nxge_rxdma_start_channel: reset done: channel %d", 4007 channel)); 4008 } 4009 4010 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 4011 if (isLDOMguest(nxgep)) 4012 (void) nxge_rdc_lp_conf(nxgep, channel); 4013 #endif 4014 4015 /* 4016 * Initialize the RXDMA channel specific FZC control 4017 * configurations. These FZC registers are pertaining 4018 * to each RX channel (logical pages). 4019 */ 4020 if (!isLDOMguest(nxgep)) { 4021 status = nxge_init_fzc_rxdma_channel(nxgep, channel); 4022 if (status != NXGE_OK) { 4023 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4024 "==> nxge_rxdma_start_channel: " 4025 "init fzc rxdma failed (0x%08x channel %d)", 4026 status, channel)); 4027 return (status); 4028 } 4029 4030 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4031 "==> nxge_rxdma_start_channel: fzc done")); 4032 } 4033 4034 /* Set up the interrupt event masks. */ 4035 ent_mask.value = 0; 4036 ent_mask.value |= RX_DMA_ENT_MSK_RBREMPTY_MASK; 4037 rs = npi_rxdma_event_mask(handle, OP_SET, channel, 4038 &ent_mask); 4039 if (rs != NPI_SUCCESS) { 4040 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4041 "==> nxge_rxdma_start_channel: " 4042 "init rxdma event masks failed " 4043 "(0x%08x channel %d)", 4044 status, channel)); 4045 return (NXGE_ERROR | rs); 4046 } 4047 4048 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4049 "==> nxge_rxdma_start_channel: " 4050 "event done: channel %d (mask 0x%016llx)", 4051 channel, ent_mask.value)); 4052 4053 /* Initialize the receive DMA control and status register */ 4054 cs.value = 0; 4055 cs.bits.hdw.mex = 1; 4056 cs.bits.hdw.rcrthres = 1; 4057 cs.bits.hdw.rcrto = 1; 4058 cs.bits.hdw.rbr_empty = 1; 4059 status = nxge_init_rxdma_channel_cntl_stat(nxgep, channel, &cs); 4060 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 4061 "channel %d rx_dma_cntl_stat 0x%0016llx", channel, cs.value)); 4062 if (status != NXGE_OK) { 4063 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4064 "==> nxge_rxdma_start_channel: " 4065 "init rxdma control register failed (0x%08x channel %d", 4066 status, channel)); 4067 return (status); 4068 } 4069 4070 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 4071 "control done - channel %d cs 0x%016llx", channel, cs.value)); 4072 4073 /* 4074 * Load RXDMA descriptors, buffers, mailbox, 4075 * initialise the receive DMA channels and 4076 * enable each DMA channel. 4077 */ 4078 status = nxge_enable_rxdma_channel(nxgep, 4079 channel, rbr_p, rcr_p, mbox_p); 4080 4081 if (status != NXGE_OK) { 4082 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4083 " nxge_rxdma_start_channel: " 4084 " enable rxdma failed (0x%08x channel %d)", 4085 status, channel)); 4086 return (status); 4087 } 4088 4089 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4090 "==> nxge_rxdma_start_channel: enabled channel %d")); 4091 4092 if (isLDOMguest(nxgep)) { 4093 /* Add interrupt handler for this channel. */ 4094 if (nxge_hio_intr_add(nxgep, VP_BOUND_RX, channel) 4095 != NXGE_OK) { 4096 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4097 " nxge_rxdma_start_channel: " 4098 " nxge_hio_intr_add failed (0x%08x channel %d)", 4099 status, channel)); 4100 } 4101 } 4102 4103 ent_mask.value = 0; 4104 ent_mask.value |= (RX_DMA_ENT_MSK_WRED_DROP_MASK | 4105 RX_DMA_ENT_MSK_PTDROP_PKT_MASK); 4106 rs = npi_rxdma_event_mask(handle, OP_SET, channel, 4107 &ent_mask); 4108 if (rs != NPI_SUCCESS) { 4109 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4110 "==> nxge_rxdma_start_channel: " 4111 "init rxdma event masks failed (0x%08x channel %d)", 4112 status, channel)); 4113 return (NXGE_ERROR | rs); 4114 } 4115 4116 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 4117 "control done - channel %d cs 0x%016llx", channel, cs.value)); 4118 4119 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_rxdma_start_channel")); 4120 4121 return (NXGE_OK); 4122 } 4123 4124 static nxge_status_t 4125 nxge_rxdma_stop_channel(p_nxge_t nxgep, uint16_t channel) 4126 { 4127 npi_handle_t handle; 4128 npi_status_t rs = NPI_SUCCESS; 4129 rx_dma_ctl_stat_t cs; 4130 rx_dma_ent_msk_t ent_mask; 4131 nxge_status_t status = NXGE_OK; 4132 4133 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_channel")); 4134 4135 handle = NXGE_DEV_NPI_HANDLE(nxgep); 4136 4137 NXGE_DEBUG_MSG((nxgep, RX_CTL, "nxge_rxdma_stop_channel: " 4138 "npi handle addr $%p acc $%p", 4139 nxgep->npi_handle.regp, nxgep->npi_handle.regh)); 4140 4141 /* Reset RXDMA channel */ 4142 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 4143 if (rs != NPI_SUCCESS) { 4144 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4145 " nxge_rxdma_stop_channel: " 4146 " reset rxdma failed (0x%08x channel %d)", 4147 rs, channel)); 4148 return (NXGE_ERROR | rs); 4149 } 4150 4151 NXGE_DEBUG_MSG((nxgep, RX_CTL, 4152 "==> nxge_rxdma_stop_channel: reset done")); 4153 4154 /* Set up the interrupt event masks. */ 4155 ent_mask.value = RX_DMA_ENT_MSK_ALL; 4156 rs = npi_rxdma_event_mask(handle, OP_SET, channel, 4157 &ent_mask); 4158 if (rs != NPI_SUCCESS) { 4159 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4160 "==> nxge_rxdma_stop_channel: " 4161 "set rxdma event masks failed (0x%08x channel %d)", 4162 rs, channel)); 4163 return (NXGE_ERROR | rs); 4164 } 4165 4166 NXGE_DEBUG_MSG((nxgep, RX_CTL, 4167 "==> nxge_rxdma_stop_channel: event done")); 4168 4169 /* Initialize the receive DMA control and status register */ 4170 cs.value = 0; 4171 status = nxge_init_rxdma_channel_cntl_stat(nxgep, channel, 4172 &cs); 4173 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_channel: control " 4174 " to default (all 0s) 0x%08x", cs.value)); 4175 if (status != NXGE_OK) { 4176 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4177 " nxge_rxdma_stop_channel: init rxdma" 4178 " control register failed (0x%08x channel %d", 4179 status, channel)); 4180 return (status); 4181 } 4182 4183 NXGE_DEBUG_MSG((nxgep, RX_CTL, 4184 "==> nxge_rxdma_stop_channel: control done")); 4185 4186 /* disable dma channel */ 4187 status = nxge_disable_rxdma_channel(nxgep, channel); 4188 4189 if (status != NXGE_OK) { 4190 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4191 " nxge_rxdma_stop_channel: " 4192 " init enable rxdma failed (0x%08x channel %d)", 4193 status, channel)); 4194 return (status); 4195 } 4196 4197 NXGE_DEBUG_MSG((nxgep, 4198 RX_CTL, "==> nxge_rxdma_stop_channel: disable done")); 4199 4200 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_stop_channel")); 4201 4202 return (NXGE_OK); 4203 } 4204 4205 nxge_status_t 4206 nxge_rxdma_handle_sys_errors(p_nxge_t nxgep) 4207 { 4208 npi_handle_t handle; 4209 p_nxge_rdc_sys_stats_t statsp; 4210 rx_ctl_dat_fifo_stat_t stat; 4211 uint32_t zcp_err_status; 4212 uint32_t ipp_err_status; 4213 nxge_status_t status = NXGE_OK; 4214 npi_status_t rs = NPI_SUCCESS; 4215 boolean_t my_err = B_FALSE; 4216 4217 handle = nxgep->npi_handle; 4218 statsp = (p_nxge_rdc_sys_stats_t)&nxgep->statsp->rdc_sys_stats; 4219 4220 rs = npi_rxdma_rxctl_fifo_error_intr_get(handle, &stat); 4221 4222 if (rs != NPI_SUCCESS) 4223 return (NXGE_ERROR | rs); 4224 4225 if (stat.bits.ldw.id_mismatch) { 4226 statsp->id_mismatch++; 4227 NXGE_FM_REPORT_ERROR(nxgep, nxgep->mac.portnum, NULL, 4228 NXGE_FM_EREPORT_RDMC_ID_MISMATCH); 4229 /* Global fatal error encountered */ 4230 } 4231 4232 if ((stat.bits.ldw.zcp_eop_err) || (stat.bits.ldw.ipp_eop_err)) { 4233 switch (nxgep->mac.portnum) { 4234 case 0: 4235 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT0) || 4236 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT0)) { 4237 my_err = B_TRUE; 4238 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4239 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4240 } 4241 break; 4242 case 1: 4243 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT1) || 4244 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT1)) { 4245 my_err = B_TRUE; 4246 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4247 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4248 } 4249 break; 4250 case 2: 4251 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT2) || 4252 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT2)) { 4253 my_err = B_TRUE; 4254 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4255 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4256 } 4257 break; 4258 case 3: 4259 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT3) || 4260 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT3)) { 4261 my_err = B_TRUE; 4262 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4263 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4264 } 4265 break; 4266 default: 4267 return (NXGE_ERROR); 4268 } 4269 } 4270 4271 if (my_err) { 4272 status = nxge_rxdma_handle_port_errors(nxgep, ipp_err_status, 4273 zcp_err_status); 4274 if (status != NXGE_OK) 4275 return (status); 4276 } 4277 4278 return (NXGE_OK); 4279 } 4280 4281 static nxge_status_t 4282 nxge_rxdma_handle_port_errors(p_nxge_t nxgep, uint32_t ipp_status, 4283 uint32_t zcp_status) 4284 { 4285 boolean_t rxport_fatal = B_FALSE; 4286 p_nxge_rdc_sys_stats_t statsp; 4287 nxge_status_t status = NXGE_OK; 4288 uint8_t portn; 4289 4290 portn = nxgep->mac.portnum; 4291 statsp = (p_nxge_rdc_sys_stats_t)&nxgep->statsp->rdc_sys_stats; 4292 4293 if (ipp_status & (0x1 << portn)) { 4294 statsp->ipp_eop_err++; 4295 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 4296 NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR); 4297 rxport_fatal = B_TRUE; 4298 } 4299 4300 if (zcp_status & (0x1 << portn)) { 4301 statsp->zcp_eop_err++; 4302 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 4303 NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR); 4304 rxport_fatal = B_TRUE; 4305 } 4306 4307 if (rxport_fatal) { 4308 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4309 " nxge_rxdma_handle_port_error: " 4310 " fatal error on Port #%d\n", 4311 portn)); 4312 status = nxge_rx_port_fatal_err_recover(nxgep); 4313 if (status == NXGE_OK) { 4314 FM_SERVICE_RESTORED(nxgep); 4315 } 4316 } 4317 4318 return (status); 4319 } 4320 4321 static nxge_status_t 4322 nxge_rxdma_fatal_err_recover(p_nxge_t nxgep, uint16_t channel) 4323 { 4324 npi_handle_t handle; 4325 npi_status_t rs = NPI_SUCCESS; 4326 nxge_status_t status = NXGE_OK; 4327 p_rx_rbr_ring_t rbrp; 4328 p_rx_rcr_ring_t rcrp; 4329 p_rx_mbox_t mboxp; 4330 rx_dma_ent_msk_t ent_mask; 4331 p_nxge_dma_common_t dmap; 4332 int ring_idx; 4333 uint32_t ref_cnt; 4334 p_rx_msg_t rx_msg_p; 4335 int i; 4336 uint32_t nxge_port_rcr_size; 4337 4338 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_fatal_err_recover")); 4339 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4340 "Recovering from RxDMAChannel#%d error...", channel)); 4341 4342 /* 4343 * Stop the dma channel waits for the stop done. 4344 * If the stop done bit is not set, then create 4345 * an error. 4346 */ 4347 4348 handle = NXGE_DEV_NPI_HANDLE(nxgep); 4349 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Rx DMA stop...")); 4350 4351 ring_idx = nxge_rxdma_get_ring_index(nxgep, channel); 4352 rbrp = (p_rx_rbr_ring_t)nxgep->rx_rbr_rings->rbr_rings[ring_idx]; 4353 rcrp = (p_rx_rcr_ring_t)nxgep->rx_rcr_rings->rcr_rings[ring_idx]; 4354 4355 MUTEX_ENTER(&rcrp->lock); 4356 MUTEX_ENTER(&rbrp->lock); 4357 MUTEX_ENTER(&rbrp->post_lock); 4358 4359 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxDMA channel...")); 4360 4361 rs = npi_rxdma_cfg_rdc_disable(handle, channel); 4362 if (rs != NPI_SUCCESS) { 4363 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4364 "nxge_disable_rxdma_channel:failed")); 4365 goto fail; 4366 } 4367 4368 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxDMA interrupt...")); 4369 4370 /* Disable interrupt */ 4371 ent_mask.value = RX_DMA_ENT_MSK_ALL; 4372 rs = npi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 4373 if (rs != NPI_SUCCESS) { 4374 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4375 "nxge_rxdma_stop_channel: " 4376 "set rxdma event masks failed (channel %d)", 4377 channel)); 4378 } 4379 4380 NXGE_DEBUG_MSG((nxgep, RX_CTL, "RxDMA channel reset...")); 4381 4382 /* Reset RXDMA channel */ 4383 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 4384 if (rs != NPI_SUCCESS) { 4385 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4386 "nxge_rxdma_fatal_err_recover: " 4387 " reset rxdma failed (channel %d)", channel)); 4388 goto fail; 4389 } 4390 4391 nxge_port_rcr_size = nxgep->nxge_port_rcr_size; 4392 4393 mboxp = 4394 (p_rx_mbox_t)nxgep->rx_mbox_areas_p->rxmbox_areas[ring_idx]; 4395 4396 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 4397 rbrp->rbr_rd_index = 0; 4398 4399 rcrp->comp_rd_index = 0; 4400 rcrp->comp_wt_index = 0; 4401 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 4402 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 4403 #if defined(__i386) 4404 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 4405 (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 4406 #else 4407 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 4408 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 4409 #endif 4410 4411 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 4412 (nxge_port_rcr_size - 1); 4413 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 4414 (nxge_port_rcr_size - 1); 4415 4416 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 4417 bzero((caddr_t)dmap->kaddrp, dmap->alength); 4418 4419 cmn_err(CE_NOTE, "!rbr entries = %d\n", rbrp->rbr_max_size); 4420 4421 for (i = 0; i < rbrp->rbr_max_size; i++) { 4422 rx_msg_p = rbrp->rx_msg_ring[i]; 4423 ref_cnt = rx_msg_p->ref_cnt; 4424 if (ref_cnt != 1) { 4425 if (rx_msg_p->cur_usage_cnt != 4426 rx_msg_p->max_usage_cnt) { 4427 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4428 "buf[%d]: cur_usage_cnt = %d " 4429 "max_usage_cnt = %d\n", i, 4430 rx_msg_p->cur_usage_cnt, 4431 rx_msg_p->max_usage_cnt)); 4432 } else { 4433 /* Buffer can be re-posted */ 4434 rx_msg_p->free = B_TRUE; 4435 rx_msg_p->cur_usage_cnt = 0; 4436 rx_msg_p->max_usage_cnt = 0xbaddcafe; 4437 rx_msg_p->pkt_buf_size = 0; 4438 } 4439 } 4440 } 4441 4442 NXGE_DEBUG_MSG((nxgep, RX_CTL, "RxDMA channel re-start...")); 4443 4444 status = nxge_rxdma_start_channel(nxgep, channel, rbrp, rcrp, mboxp); 4445 if (status != NXGE_OK) { 4446 goto fail; 4447 } 4448 4449 MUTEX_EXIT(&rbrp->post_lock); 4450 MUTEX_EXIT(&rbrp->lock); 4451 MUTEX_EXIT(&rcrp->lock); 4452 4453 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4454 "Recovery Successful, RxDMAChannel#%d Restored", 4455 channel)); 4456 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fatal_err_recover")); 4457 4458 return (NXGE_OK); 4459 fail: 4460 MUTEX_EXIT(&rbrp->post_lock); 4461 MUTEX_EXIT(&rbrp->lock); 4462 MUTEX_EXIT(&rcrp->lock); 4463 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Recovery failed")); 4464 4465 return (NXGE_ERROR | rs); 4466 } 4467 4468 nxge_status_t 4469 nxge_rx_port_fatal_err_recover(p_nxge_t nxgep) 4470 { 4471 nxge_grp_set_t *set = &nxgep->rx_set; 4472 nxge_status_t status = NXGE_OK; 4473 int rdc; 4474 4475 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_port_fatal_err_recover")); 4476 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4477 "Recovering from RxPort error...")); 4478 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disabling RxMAC...\n")); 4479 4480 if (nxge_rx_mac_disable(nxgep) != NXGE_OK) 4481 goto fail; 4482 4483 NXGE_DELAY(1000); 4484 4485 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Stopping all RxDMA channels...")); 4486 4487 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 4488 if ((1 << rdc) & set->owned.map) { 4489 if (nxge_rxdma_fatal_err_recover(nxgep, rdc) 4490 != NXGE_OK) { 4491 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4492 "Could not recover channel %d", rdc)); 4493 } 4494 } 4495 } 4496 4497 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Resetting IPP...")); 4498 4499 /* Reset IPP */ 4500 if (nxge_ipp_reset(nxgep) != NXGE_OK) { 4501 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4502 "nxge_rx_port_fatal_err_recover: " 4503 "Failed to reset IPP")); 4504 goto fail; 4505 } 4506 4507 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Reset RxMAC...")); 4508 4509 /* Reset RxMAC */ 4510 if (nxge_rx_mac_reset(nxgep) != NXGE_OK) { 4511 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4512 "nxge_rx_port_fatal_err_recover: " 4513 "Failed to reset RxMAC")); 4514 goto fail; 4515 } 4516 4517 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-initialize IPP...")); 4518 4519 /* Re-Initialize IPP */ 4520 if (nxge_ipp_init(nxgep) != NXGE_OK) { 4521 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4522 "nxge_rx_port_fatal_err_recover: " 4523 "Failed to init IPP")); 4524 goto fail; 4525 } 4526 4527 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-initialize RxMAC...")); 4528 4529 /* Re-Initialize RxMAC */ 4530 if ((status = nxge_rx_mac_init(nxgep)) != NXGE_OK) { 4531 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4532 "nxge_rx_port_fatal_err_recover: " 4533 "Failed to reset RxMAC")); 4534 goto fail; 4535 } 4536 4537 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-enable RxMAC...")); 4538 4539 /* Re-enable RxMAC */ 4540 if ((status = nxge_rx_mac_enable(nxgep)) != NXGE_OK) { 4541 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4542 "nxge_rx_port_fatal_err_recover: " 4543 "Failed to enable RxMAC")); 4544 goto fail; 4545 } 4546 4547 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4548 "Recovery Successful, RxPort Restored")); 4549 4550 return (NXGE_OK); 4551 fail: 4552 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Recovery failed")); 4553 return (status); 4554 } 4555 4556 void 4557 nxge_rxdma_inject_err(p_nxge_t nxgep, uint32_t err_id, uint8_t chan) 4558 { 4559 rx_dma_ctl_stat_t cs; 4560 rx_ctl_dat_fifo_stat_t cdfs; 4561 4562 switch (err_id) { 4563 case NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR: 4564 case NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR: 4565 case NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR: 4566 case NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR: 4567 case NXGE_FM_EREPORT_RDMC_RBR_TMOUT: 4568 case NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR: 4569 case NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS: 4570 case NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR: 4571 case NXGE_FM_EREPORT_RDMC_RCRINCON: 4572 case NXGE_FM_EREPORT_RDMC_RCRFULL: 4573 case NXGE_FM_EREPORT_RDMC_RBRFULL: 4574 case NXGE_FM_EREPORT_RDMC_RBRLOGPAGE: 4575 case NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE: 4576 case NXGE_FM_EREPORT_RDMC_CONFIG_ERR: 4577 RXDMA_REG_READ64(nxgep->npi_handle, RX_DMA_CTL_STAT_DBG_REG, 4578 chan, &cs.value); 4579 if (err_id == NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR) 4580 cs.bits.hdw.rcr_ack_err = 1; 4581 else if (err_id == NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR) 4582 cs.bits.hdw.dc_fifo_err = 1; 4583 else if (err_id == NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR) 4584 cs.bits.hdw.rcr_sha_par = 1; 4585 else if (err_id == NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR) 4586 cs.bits.hdw.rbr_pre_par = 1; 4587 else if (err_id == NXGE_FM_EREPORT_RDMC_RBR_TMOUT) 4588 cs.bits.hdw.rbr_tmout = 1; 4589 else if (err_id == NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR) 4590 cs.bits.hdw.rsp_cnt_err = 1; 4591 else if (err_id == NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS) 4592 cs.bits.hdw.byte_en_bus = 1; 4593 else if (err_id == NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR) 4594 cs.bits.hdw.rsp_dat_err = 1; 4595 else if (err_id == NXGE_FM_EREPORT_RDMC_CONFIG_ERR) 4596 cs.bits.hdw.config_err = 1; 4597 else if (err_id == NXGE_FM_EREPORT_RDMC_RCRINCON) 4598 cs.bits.hdw.rcrincon = 1; 4599 else if (err_id == NXGE_FM_EREPORT_RDMC_RCRFULL) 4600 cs.bits.hdw.rcrfull = 1; 4601 else if (err_id == NXGE_FM_EREPORT_RDMC_RBRFULL) 4602 cs.bits.hdw.rbrfull = 1; 4603 else if (err_id == NXGE_FM_EREPORT_RDMC_RBRLOGPAGE) 4604 cs.bits.hdw.rbrlogpage = 1; 4605 else if (err_id == NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE) 4606 cs.bits.hdw.cfiglogpage = 1; 4607 #if defined(__i386) 4608 cmn_err(CE_NOTE, "!Write 0x%llx to RX_DMA_CTL_STAT_DBG_REG\n", 4609 cs.value); 4610 #else 4611 cmn_err(CE_NOTE, "!Write 0x%lx to RX_DMA_CTL_STAT_DBG_REG\n", 4612 cs.value); 4613 #endif 4614 RXDMA_REG_WRITE64(nxgep->npi_handle, RX_DMA_CTL_STAT_DBG_REG, 4615 chan, cs.value); 4616 break; 4617 case NXGE_FM_EREPORT_RDMC_ID_MISMATCH: 4618 case NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR: 4619 case NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR: 4620 cdfs.value = 0; 4621 if (err_id == NXGE_FM_EREPORT_RDMC_ID_MISMATCH) 4622 cdfs.bits.ldw.id_mismatch = (1 << nxgep->mac.portnum); 4623 else if (err_id == NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR) 4624 cdfs.bits.ldw.zcp_eop_err = (1 << nxgep->mac.portnum); 4625 else if (err_id == NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR) 4626 cdfs.bits.ldw.ipp_eop_err = (1 << nxgep->mac.portnum); 4627 #if defined(__i386) 4628 cmn_err(CE_NOTE, 4629 "!Write 0x%llx to RX_CTL_DAT_FIFO_STAT_DBG_REG\n", 4630 cdfs.value); 4631 #else 4632 cmn_err(CE_NOTE, 4633 "!Write 0x%lx to RX_CTL_DAT_FIFO_STAT_DBG_REG\n", 4634 cdfs.value); 4635 #endif 4636 NXGE_REG_WR64(nxgep->npi_handle, 4637 RX_CTL_DAT_FIFO_STAT_DBG_REG, cdfs.value); 4638 break; 4639 case NXGE_FM_EREPORT_RDMC_DCF_ERR: 4640 break; 4641 case NXGE_FM_EREPORT_RDMC_RCR_ERR: 4642 break; 4643 } 4644 } 4645 4646 static void 4647 nxge_rxdma_databuf_free(p_rx_rbr_ring_t rbr_p) 4648 { 4649 rxring_info_t *ring_info; 4650 int index; 4651 uint32_t chunk_size; 4652 uint64_t kaddr; 4653 uint_t num_blocks; 4654 4655 NXGE_DEBUG_MSG((NULL, DMA_CTL, "==> nxge_rxdma_databuf_free")); 4656 4657 if (rbr_p == NULL) { 4658 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 4659 "==> nxge_rxdma_databuf_free: NULL rbr pointer")); 4660 return; 4661 } 4662 4663 if (rbr_p->rbr_alloc_type == DDI_MEM_ALLOC) { 4664 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 4665 "==> nxge_rxdma_databuf_free: DDI")); 4666 return; 4667 } 4668 4669 ring_info = rbr_p->ring_info; 4670 if (ring_info == NULL) { 4671 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 4672 "==> nxge_rxdma_databuf_free: NULL ring info")); 4673 return; 4674 } 4675 num_blocks = rbr_p->num_blocks; 4676 for (index = 0; index < num_blocks; index++) { 4677 kaddr = ring_info->buffer[index].kaddr; 4678 chunk_size = ring_info->buffer[index].buf_size; 4679 NXGE_DEBUG_MSG((NULL, DMA_CTL, 4680 "==> nxge_rxdma_databuf_free: free chunk %d " 4681 "kaddrp $%p chunk size %d", 4682 index, kaddr, chunk_size)); 4683 if (kaddr == NULL) continue; 4684 nxge_free_buf(rbr_p->rbr_alloc_type, kaddr, chunk_size); 4685 ring_info->buffer[index].kaddr = NULL; 4686 } 4687 4688 NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_databuf_free")); 4689 } 4690 4691 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 4692 extern void contig_mem_free(void *, size_t); 4693 #endif 4694 4695 void 4696 nxge_free_buf(buf_alloc_type_t alloc_type, uint64_t kaddr, uint32_t buf_size) 4697 { 4698 NXGE_DEBUG_MSG((NULL, DMA_CTL, "==> nxge_free_buf")); 4699 4700 if (kaddr == NULL || !buf_size) { 4701 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 4702 "==> nxge_free_buf: invalid kaddr $%p size to free %d", 4703 kaddr, buf_size)); 4704 return; 4705 } 4706 4707 switch (alloc_type) { 4708 case KMEM_ALLOC: 4709 NXGE_DEBUG_MSG((NULL, DMA_CTL, 4710 "==> nxge_free_buf: freeing kmem $%p size %d", 4711 kaddr, buf_size)); 4712 #if defined(__i386) 4713 KMEM_FREE((void *)(uint32_t)kaddr, buf_size); 4714 #else 4715 KMEM_FREE((void *)kaddr, buf_size); 4716 #endif 4717 break; 4718 4719 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 4720 case CONTIG_MEM_ALLOC: 4721 NXGE_DEBUG_MSG((NULL, DMA_CTL, 4722 "==> nxge_free_buf: freeing contig_mem kaddr $%p size %d", 4723 kaddr, buf_size)); 4724 contig_mem_free((void *)kaddr, buf_size); 4725 break; 4726 #endif 4727 4728 default: 4729 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 4730 "<== nxge_free_buf: unsupported alloc type %d", 4731 alloc_type)); 4732 return; 4733 } 4734 4735 NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_free_buf")); 4736 } 4737