144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 21ef523517SMichael Speer 2244961713Sgirish /* 237b26d9ffSSantwona Behera * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 2444961713Sgirish * Use is subject to license terms. 2544961713Sgirish */ 2644961713Sgirish 2744961713Sgirish #include <sys/nxge/nxge_impl.h> 2844961713Sgirish #include <sys/nxge/nxge_rxdma.h> 29678453a8Sspeer #include <sys/nxge/nxge_hio.h> 30678453a8Sspeer 31678453a8Sspeer #if !defined(_BIG_ENDIAN) 32678453a8Sspeer #include <npi_rx_rd32.h> 33678453a8Sspeer #endif 34678453a8Sspeer #include <npi_rx_rd64.h> 35678453a8Sspeer #include <npi_rx_wr64.h> 3644961713Sgirish 3744961713Sgirish #define NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp) \ 38678453a8Sspeer (rdcgrp + nxgep->pt_config.hw_config.def_mac_rxdma_grpid) 3944961713Sgirish #define NXGE_ACTUAL_RDC(nxgep, rdc) \ 4044961713Sgirish (rdc + nxgep->pt_config.hw_config.start_rdc) 4144961713Sgirish 4244961713Sgirish /* 4344961713Sgirish * Globals: tunable parameters (/etc/system or adb) 4444961713Sgirish * 4544961713Sgirish */ 4644961713Sgirish extern uint32_t nxge_rbr_size; 4744961713Sgirish extern uint32_t nxge_rcr_size; 4844961713Sgirish extern uint32_t nxge_rbr_spare_size; 49*4df55fdeSJanie Lu extern uint16_t nxge_rdc_buf_offset; 5044961713Sgirish 5144961713Sgirish extern uint32_t nxge_mblks_pending; 5244961713Sgirish 5344961713Sgirish /* 5444961713Sgirish * Tunable to reduce the amount of time spent in the 5544961713Sgirish * ISR doing Rx Processing. 5644961713Sgirish */ 5744961713Sgirish extern uint32_t nxge_max_rx_pkts; 5844961713Sgirish 5944961713Sgirish /* 6044961713Sgirish * Tunables to manage the receive buffer blocks. 6144961713Sgirish * 6244961713Sgirish * nxge_rx_threshold_hi: copy all buffers. 6344961713Sgirish * nxge_rx_bcopy_size_type: receive buffer block size type. 6444961713Sgirish * nxge_rx_threshold_lo: copy only up to tunable block size type. 6544961713Sgirish */ 6644961713Sgirish extern nxge_rxbuf_threshold_t nxge_rx_threshold_hi; 6744961713Sgirish extern nxge_rxbuf_type_t nxge_rx_buf_size_type; 6844961713Sgirish extern nxge_rxbuf_threshold_t nxge_rx_threshold_lo; 6944961713Sgirish 70b4d05839Sml extern uint32_t nxge_cksum_offload; 71678453a8Sspeer 72678453a8Sspeer static nxge_status_t nxge_map_rxdma(p_nxge_t, int); 73678453a8Sspeer static void nxge_unmap_rxdma(p_nxge_t, int); 7444961713Sgirish 7544961713Sgirish static nxge_status_t nxge_rxdma_hw_start_common(p_nxge_t); 7644961713Sgirish 77678453a8Sspeer static nxge_status_t nxge_rxdma_hw_start(p_nxge_t, int); 78678453a8Sspeer static void nxge_rxdma_hw_stop(p_nxge_t, int); 7944961713Sgirish 8044961713Sgirish static nxge_status_t nxge_map_rxdma_channel(p_nxge_t, uint16_t, 8144961713Sgirish p_nxge_dma_common_t *, p_rx_rbr_ring_t *, 8244961713Sgirish uint32_t, 8344961713Sgirish p_nxge_dma_common_t *, p_rx_rcr_ring_t *, 8444961713Sgirish p_rx_mbox_t *); 8544961713Sgirish static void nxge_unmap_rxdma_channel(p_nxge_t, uint16_t, 8644961713Sgirish p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t); 8744961713Sgirish 8844961713Sgirish static nxge_status_t nxge_map_rxdma_channel_cfg_ring(p_nxge_t, 8944961713Sgirish uint16_t, 9044961713Sgirish p_nxge_dma_common_t *, p_rx_rbr_ring_t *, 9144961713Sgirish p_rx_rcr_ring_t *, p_rx_mbox_t *); 9244961713Sgirish static void nxge_unmap_rxdma_channel_cfg_ring(p_nxge_t, 9344961713Sgirish p_rx_rcr_ring_t, p_rx_mbox_t); 9444961713Sgirish 9544961713Sgirish static nxge_status_t nxge_map_rxdma_channel_buf_ring(p_nxge_t, 9644961713Sgirish uint16_t, 9744961713Sgirish p_nxge_dma_common_t *, 9844961713Sgirish p_rx_rbr_ring_t *, uint32_t); 9944961713Sgirish static void nxge_unmap_rxdma_channel_buf_ring(p_nxge_t, 10044961713Sgirish p_rx_rbr_ring_t); 10144961713Sgirish 10244961713Sgirish static nxge_status_t nxge_rxdma_start_channel(p_nxge_t, uint16_t, 10344961713Sgirish p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t); 10444961713Sgirish static nxge_status_t nxge_rxdma_stop_channel(p_nxge_t, uint16_t); 10544961713Sgirish 106678453a8Sspeer static mblk_t * 107678453a8Sspeer nxge_rx_pkts(p_nxge_t, p_rx_rcr_ring_t, rx_dma_ctl_stat_t, int); 10844961713Sgirish 10944961713Sgirish static void nxge_receive_packet(p_nxge_t, 11044961713Sgirish p_rx_rcr_ring_t, 11144961713Sgirish p_rcr_entry_t, 11244961713Sgirish boolean_t *, 11344961713Sgirish mblk_t **, mblk_t **); 11444961713Sgirish 11544961713Sgirish nxge_status_t nxge_disable_rxdma_channel(p_nxge_t, uint16_t); 11644961713Sgirish 11744961713Sgirish static p_rx_msg_t nxge_allocb(size_t, uint32_t, p_nxge_dma_common_t); 11844961713Sgirish static void nxge_freeb(p_rx_msg_t); 119678453a8Sspeer static nxge_status_t nxge_rx_err_evnts(p_nxge_t, int, rx_dma_ctl_stat_t); 12044961713Sgirish 12144961713Sgirish static nxge_status_t nxge_rxdma_handle_port_errors(p_nxge_t, 12244961713Sgirish uint32_t, uint32_t); 12344961713Sgirish 12444961713Sgirish static nxge_status_t nxge_rxbuf_index_info_init(p_nxge_t, 12544961713Sgirish p_rx_rbr_ring_t); 12644961713Sgirish 12744961713Sgirish 12844961713Sgirish static nxge_status_t 12944961713Sgirish nxge_rxdma_fatal_err_recover(p_nxge_t, uint16_t); 13044961713Sgirish 13144961713Sgirish nxge_status_t 13244961713Sgirish nxge_rx_port_fatal_err_recover(p_nxge_t); 13344961713Sgirish 134678453a8Sspeer static void nxge_rxdma_databuf_free(p_rx_rbr_ring_t); 135678453a8Sspeer 13644961713Sgirish nxge_status_t 13744961713Sgirish nxge_init_rxdma_channels(p_nxge_t nxgep) 13844961713Sgirish { 139e11f0814SMichael Speer nxge_grp_set_t *set = &nxgep->rx_set; 140da14cebeSEric Cheng int i, count, channel; 141e11f0814SMichael Speer nxge_grp_t *group; 142da14cebeSEric Cheng dc_map_t map; 143da14cebeSEric Cheng int dev_gindex; 14444961713Sgirish 14544961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_init_rxdma_channels")); 14644961713Sgirish 147678453a8Sspeer if (!isLDOMguest(nxgep)) { 148678453a8Sspeer if (nxge_rxdma_hw_start_common(nxgep) != NXGE_OK) { 149678453a8Sspeer cmn_err(CE_NOTE, "hw_start_common"); 150678453a8Sspeer return (NXGE_ERROR); 151678453a8Sspeer } 152678453a8Sspeer } 153678453a8Sspeer 154678453a8Sspeer /* 155678453a8Sspeer * NXGE_LOGICAL_GROUP_MAX > NXGE_MAX_RDC_GROUPS (8) 156678453a8Sspeer * We only have 8 hardware RDC tables, but we may have 157678453a8Sspeer * up to 16 logical (software-defined) groups of RDCS, 158678453a8Sspeer * if we make use of layer 3 & 4 hardware classification. 159678453a8Sspeer */ 160678453a8Sspeer for (i = 0, count = 0; i < NXGE_LOGICAL_GROUP_MAX; i++) { 161678453a8Sspeer if ((1 << i) & set->lg.map) { 162e11f0814SMichael Speer group = set->group[i]; 163da14cebeSEric Cheng dev_gindex = 164da14cebeSEric Cheng nxgep->pt_config.hw_config.def_mac_rxdma_grpid + i; 165da14cebeSEric Cheng map = nxgep->pt_config.rdc_grps[dev_gindex].map; 166678453a8Sspeer for (channel = 0; channel < NXGE_MAX_RDCS; channel++) { 167da14cebeSEric Cheng if ((1 << channel) & map) { 168678453a8Sspeer if ((nxge_grp_dc_add(nxgep, 1696920a987SMisaki Miyashita group, VP_BOUND_RX, channel))) 170e11f0814SMichael Speer goto init_rxdma_channels_exit; 171678453a8Sspeer } 172678453a8Sspeer } 173678453a8Sspeer } 174678453a8Sspeer if (++count == set->lg.count) 175678453a8Sspeer break; 17644961713Sgirish } 17744961713Sgirish 178678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_init_rxdma_channels")); 179678453a8Sspeer return (NXGE_OK); 180e11f0814SMichael Speer 181e11f0814SMichael Speer init_rxdma_channels_exit: 182e11f0814SMichael Speer for (i = 0, count = 0; i < NXGE_LOGICAL_GROUP_MAX; i++) { 183e11f0814SMichael Speer if ((1 << i) & set->lg.map) { 184e11f0814SMichael Speer group = set->group[i]; 185da14cebeSEric Cheng dev_gindex = 186da14cebeSEric Cheng nxgep->pt_config.hw_config.def_mac_rxdma_grpid + i; 187da14cebeSEric Cheng map = nxgep->pt_config.rdc_grps[dev_gindex].map; 188da14cebeSEric Cheng for (channel = 0; channel < NXGE_MAX_RDCS; channel++) { 189da14cebeSEric Cheng if ((1 << channel) & map) { 190e11f0814SMichael Speer nxge_grp_dc_remove(nxgep, 191da14cebeSEric Cheng VP_BOUND_RX, channel); 192e11f0814SMichael Speer } 193e11f0814SMichael Speer } 194e11f0814SMichael Speer } 195e11f0814SMichael Speer if (++count == set->lg.count) 196e11f0814SMichael Speer break; 197e11f0814SMichael Speer } 198e11f0814SMichael Speer 199e11f0814SMichael Speer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_init_rxdma_channels")); 200e11f0814SMichael Speer return (NXGE_ERROR); 201678453a8Sspeer } 202678453a8Sspeer 203678453a8Sspeer nxge_status_t 204678453a8Sspeer nxge_init_rxdma_channel(p_nxge_t nxge, int channel) 205678453a8Sspeer { 20608ac1c49SNicolas Droux nxge_status_t status; 207678453a8Sspeer 208678453a8Sspeer NXGE_DEBUG_MSG((nxge, MEM2_CTL, "==> nxge_init_rxdma_channel")); 209678453a8Sspeer 210678453a8Sspeer status = nxge_map_rxdma(nxge, channel); 21144961713Sgirish if (status != NXGE_OK) { 212678453a8Sspeer NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 213678453a8Sspeer "<== nxge_init_rxdma: status 0x%x", status)); 214678453a8Sspeer return (status); 21544961713Sgirish } 21644961713Sgirish 21708ac1c49SNicolas Droux #if defined(sun4v) 21808ac1c49SNicolas Droux if (isLDOMguest(nxge)) { 21908ac1c49SNicolas Droux /* set rcr_ring */ 22008ac1c49SNicolas Droux p_rx_rcr_ring_t ring = nxge->rx_rcr_rings->rcr_rings[channel]; 22108ac1c49SNicolas Droux 22208ac1c49SNicolas Droux status = nxge_hio_rxdma_bind_intr(nxge, ring, channel); 22308ac1c49SNicolas Droux if (status != NXGE_OK) { 22408ac1c49SNicolas Droux nxge_unmap_rxdma(nxge, channel); 22508ac1c49SNicolas Droux return (status); 22608ac1c49SNicolas Droux } 22708ac1c49SNicolas Droux } 22808ac1c49SNicolas Droux #endif 22908ac1c49SNicolas Droux 230678453a8Sspeer status = nxge_rxdma_hw_start(nxge, channel); 23144961713Sgirish if (status != NXGE_OK) { 232678453a8Sspeer nxge_unmap_rxdma(nxge, channel); 23344961713Sgirish } 23444961713Sgirish 235678453a8Sspeer if (!nxge->statsp->rdc_ksp[channel]) 236678453a8Sspeer nxge_setup_rdc_kstats(nxge, channel); 237678453a8Sspeer 238678453a8Sspeer NXGE_DEBUG_MSG((nxge, MEM2_CTL, 239678453a8Sspeer "<== nxge_init_rxdma_channel: status 0x%x", status)); 24044961713Sgirish 24144961713Sgirish return (status); 24244961713Sgirish } 24344961713Sgirish 24444961713Sgirish void 24544961713Sgirish nxge_uninit_rxdma_channels(p_nxge_t nxgep) 24644961713Sgirish { 247678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set; 248678453a8Sspeer int rdc; 249678453a8Sspeer 25044961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_uninit_rxdma_channels")); 25144961713Sgirish 252678453a8Sspeer if (set->owned.map == 0) { 253678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 254678453a8Sspeer "nxge_uninit_rxdma_channels: no channels")); 255678453a8Sspeer return; 256678453a8Sspeer } 25744961713Sgirish 258678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 259678453a8Sspeer if ((1 << rdc) & set->owned.map) { 260678453a8Sspeer nxge_grp_dc_remove(nxgep, VP_BOUND_RX, rdc); 261678453a8Sspeer } 262678453a8Sspeer } 263678453a8Sspeer 264678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_uninit_rxdma_channels")); 265678453a8Sspeer } 266678453a8Sspeer 267678453a8Sspeer void 268678453a8Sspeer nxge_uninit_rxdma_channel(p_nxge_t nxgep, int channel) 269678453a8Sspeer { 270678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_uninit_rxdma_channel")); 271678453a8Sspeer 272678453a8Sspeer if (nxgep->statsp->rdc_ksp[channel]) { 273678453a8Sspeer kstat_delete(nxgep->statsp->rdc_ksp[channel]); 274678453a8Sspeer nxgep->statsp->rdc_ksp[channel] = 0; 275678453a8Sspeer } 276678453a8Sspeer 277678453a8Sspeer nxge_rxdma_hw_stop(nxgep, channel); 278678453a8Sspeer nxge_unmap_rxdma(nxgep, channel); 279678453a8Sspeer 280678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_uinit_rxdma_channel")); 28144961713Sgirish } 28244961713Sgirish 28344961713Sgirish nxge_status_t 28444961713Sgirish nxge_reset_rxdma_channel(p_nxge_t nxgep, uint16_t channel) 28544961713Sgirish { 28644961713Sgirish npi_handle_t handle; 28744961713Sgirish npi_status_t rs = NPI_SUCCESS; 28844961713Sgirish nxge_status_t status = NXGE_OK; 28944961713Sgirish 290330cd344SMichael Speer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_reset_rxdma_channel")); 29144961713Sgirish 29244961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 29344961713Sgirish rs = npi_rxdma_cfg_rdc_reset(handle, channel); 29444961713Sgirish 29544961713Sgirish if (rs != NPI_SUCCESS) { 29644961713Sgirish status = NXGE_ERROR | rs; 29744961713Sgirish } 29844961713Sgirish 299330cd344SMichael Speer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_reset_rxdma_channel")); 300330cd344SMichael Speer 30144961713Sgirish return (status); 30244961713Sgirish } 30344961713Sgirish 30444961713Sgirish void 30544961713Sgirish nxge_rxdma_regs_dump_channels(p_nxge_t nxgep) 30644961713Sgirish { 307678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set; 308678453a8Sspeer int rdc; 30944961713Sgirish 31044961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_regs_dump_channels")); 31144961713Sgirish 312678453a8Sspeer if (!isLDOMguest(nxgep)) { 313678453a8Sspeer npi_handle_t handle = NXGE_DEV_NPI_HANDLE(nxgep); 314678453a8Sspeer (void) npi_rxdma_dump_fzc_regs(handle); 31544961713Sgirish } 316678453a8Sspeer 317678453a8Sspeer if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) { 318678453a8Sspeer NXGE_DEBUG_MSG((nxgep, TX_CTL, 319678453a8Sspeer "nxge_rxdma_regs_dump_channels: " 320678453a8Sspeer "NULL ring pointer(s)")); 32144961713Sgirish return; 32244961713Sgirish } 32344961713Sgirish 324678453a8Sspeer if (set->owned.map == 0) { 32544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 326678453a8Sspeer "nxge_rxdma_regs_dump_channels: no channels")); 32744961713Sgirish return; 32844961713Sgirish } 32944961713Sgirish 330678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 331678453a8Sspeer if ((1 << rdc) & set->owned.map) { 332678453a8Sspeer rx_rbr_ring_t *ring = 333678453a8Sspeer nxgep->rx_rbr_rings->rbr_rings[rdc]; 334678453a8Sspeer if (ring) { 335678453a8Sspeer (void) nxge_dump_rxdma_channel(nxgep, rdc); 336678453a8Sspeer } 33744961713Sgirish } 33844961713Sgirish } 33944961713Sgirish 34044961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_regs_dump")); 34144961713Sgirish } 34244961713Sgirish 34344961713Sgirish nxge_status_t 34444961713Sgirish nxge_dump_rxdma_channel(p_nxge_t nxgep, uint8_t channel) 34544961713Sgirish { 34644961713Sgirish npi_handle_t handle; 34744961713Sgirish npi_status_t rs = NPI_SUCCESS; 34844961713Sgirish nxge_status_t status = NXGE_OK; 34944961713Sgirish 35044961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_dump_rxdma_channel")); 35144961713Sgirish 35244961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 35344961713Sgirish rs = npi_rxdma_dump_rdc_regs(handle, channel); 35444961713Sgirish 35544961713Sgirish if (rs != NPI_SUCCESS) { 35644961713Sgirish status = NXGE_ERROR | rs; 35744961713Sgirish } 35844961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_dump_rxdma_channel")); 35944961713Sgirish return (status); 36044961713Sgirish } 36144961713Sgirish 36244961713Sgirish nxge_status_t 36344961713Sgirish nxge_init_rxdma_channel_event_mask(p_nxge_t nxgep, uint16_t channel, 36444961713Sgirish p_rx_dma_ent_msk_t mask_p) 36544961713Sgirish { 36644961713Sgirish npi_handle_t handle; 36744961713Sgirish npi_status_t rs = NPI_SUCCESS; 36844961713Sgirish nxge_status_t status = NXGE_OK; 36944961713Sgirish 37044961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 37152ccf843Smisaki "<== nxge_init_rxdma_channel_event_mask")); 37244961713Sgirish 37344961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 37444961713Sgirish rs = npi_rxdma_event_mask(handle, OP_SET, channel, mask_p); 37544961713Sgirish if (rs != NPI_SUCCESS) { 37644961713Sgirish status = NXGE_ERROR | rs; 37744961713Sgirish } 37844961713Sgirish 37944961713Sgirish return (status); 38044961713Sgirish } 38144961713Sgirish 38244961713Sgirish nxge_status_t 38344961713Sgirish nxge_init_rxdma_channel_cntl_stat(p_nxge_t nxgep, uint16_t channel, 38444961713Sgirish p_rx_dma_ctl_stat_t cs_p) 38544961713Sgirish { 38644961713Sgirish npi_handle_t handle; 38744961713Sgirish npi_status_t rs = NPI_SUCCESS; 38844961713Sgirish nxge_status_t status = NXGE_OK; 38944961713Sgirish 39044961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 39152ccf843Smisaki "<== nxge_init_rxdma_channel_cntl_stat")); 39244961713Sgirish 39344961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 39444961713Sgirish rs = npi_rxdma_control_status(handle, OP_SET, channel, cs_p); 39544961713Sgirish 39644961713Sgirish if (rs != NPI_SUCCESS) { 39744961713Sgirish status = NXGE_ERROR | rs; 39844961713Sgirish } 39944961713Sgirish 40044961713Sgirish return (status); 40144961713Sgirish } 40244961713Sgirish 403678453a8Sspeer /* 404678453a8Sspeer * nxge_rxdma_cfg_rdcgrp_default_rdc 405678453a8Sspeer * 406678453a8Sspeer * Set the default RDC for an RDC Group (Table) 407678453a8Sspeer * 408678453a8Sspeer * Arguments: 409678453a8Sspeer * nxgep 410678453a8Sspeer * rdcgrp The group to modify 411678453a8Sspeer * rdc The new default RDC. 412678453a8Sspeer * 413678453a8Sspeer * Notes: 414678453a8Sspeer * 415678453a8Sspeer * NPI/NXGE function calls: 416678453a8Sspeer * npi_rxdma_cfg_rdc_table_default_rdc() 417678453a8Sspeer * 418678453a8Sspeer * Registers accessed: 419678453a8Sspeer * RDC_TBL_REG: FZC_ZCP + 0x10000 420678453a8Sspeer * 421678453a8Sspeer * Context: 422678453a8Sspeer * Service domain 423678453a8Sspeer */ 42444961713Sgirish nxge_status_t 425678453a8Sspeer nxge_rxdma_cfg_rdcgrp_default_rdc( 426678453a8Sspeer p_nxge_t nxgep, 427678453a8Sspeer uint8_t rdcgrp, 428678453a8Sspeer uint8_t rdc) 42944961713Sgirish { 43044961713Sgirish npi_handle_t handle; 43144961713Sgirish npi_status_t rs = NPI_SUCCESS; 43244961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 43344961713Sgirish p_nxge_rdc_grp_t rdc_grp_p; 43444961713Sgirish uint8_t actual_rdcgrp, actual_rdc; 43544961713Sgirish 43644961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 43752ccf843Smisaki " ==> nxge_rxdma_cfg_rdcgrp_default_rdc")); 43844961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 43944961713Sgirish 44044961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 44144961713Sgirish 442678453a8Sspeer /* 443678453a8Sspeer * This has to be rewritten. Do we even allow this anymore? 444678453a8Sspeer */ 44544961713Sgirish rdc_grp_p = &p_dma_cfgp->rdc_grps[rdcgrp]; 446678453a8Sspeer RDC_MAP_IN(rdc_grp_p->map, rdc); 447678453a8Sspeer rdc_grp_p->def_rdc = rdc; 44844961713Sgirish 44944961713Sgirish actual_rdcgrp = NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp); 45044961713Sgirish actual_rdc = NXGE_ACTUAL_RDC(nxgep, rdc); 45144961713Sgirish 452678453a8Sspeer rs = npi_rxdma_cfg_rdc_table_default_rdc( 45352ccf843Smisaki handle, actual_rdcgrp, actual_rdc); 45444961713Sgirish 45544961713Sgirish if (rs != NPI_SUCCESS) { 45644961713Sgirish return (NXGE_ERROR | rs); 45744961713Sgirish } 45844961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 45952ccf843Smisaki " <== nxge_rxdma_cfg_rdcgrp_default_rdc")); 46044961713Sgirish return (NXGE_OK); 46144961713Sgirish } 46244961713Sgirish 46344961713Sgirish nxge_status_t 46444961713Sgirish nxge_rxdma_cfg_port_default_rdc(p_nxge_t nxgep, uint8_t port, uint8_t rdc) 46544961713Sgirish { 46644961713Sgirish npi_handle_t handle; 46744961713Sgirish 46844961713Sgirish uint8_t actual_rdc; 46944961713Sgirish npi_status_t rs = NPI_SUCCESS; 47044961713Sgirish 47144961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 47252ccf843Smisaki " ==> nxge_rxdma_cfg_port_default_rdc")); 47344961713Sgirish 47444961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 475678453a8Sspeer actual_rdc = rdc; /* XXX Hack! */ 47644961713Sgirish rs = npi_rxdma_cfg_default_port_rdc(handle, port, actual_rdc); 47744961713Sgirish 47844961713Sgirish 47944961713Sgirish if (rs != NPI_SUCCESS) { 48044961713Sgirish return (NXGE_ERROR | rs); 48144961713Sgirish } 48244961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 48352ccf843Smisaki " <== nxge_rxdma_cfg_port_default_rdc")); 48444961713Sgirish 48544961713Sgirish return (NXGE_OK); 48644961713Sgirish } 48744961713Sgirish 48844961713Sgirish nxge_status_t 48944961713Sgirish nxge_rxdma_cfg_rcr_threshold(p_nxge_t nxgep, uint8_t channel, 49044961713Sgirish uint16_t pkts) 49144961713Sgirish { 49244961713Sgirish npi_status_t rs = NPI_SUCCESS; 49344961713Sgirish npi_handle_t handle; 49444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 49552ccf843Smisaki " ==> nxge_rxdma_cfg_rcr_threshold")); 49644961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 49744961713Sgirish 49844961713Sgirish rs = npi_rxdma_cfg_rdc_rcr_threshold(handle, channel, pkts); 49944961713Sgirish 50044961713Sgirish if (rs != NPI_SUCCESS) { 50144961713Sgirish return (NXGE_ERROR | rs); 50244961713Sgirish } 50344961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_threshold")); 50444961713Sgirish return (NXGE_OK); 50544961713Sgirish } 50644961713Sgirish 50744961713Sgirish nxge_status_t 50844961713Sgirish nxge_rxdma_cfg_rcr_timeout(p_nxge_t nxgep, uint8_t channel, 50944961713Sgirish uint16_t tout, uint8_t enable) 51044961713Sgirish { 51144961713Sgirish npi_status_t rs = NPI_SUCCESS; 51244961713Sgirish npi_handle_t handle; 51344961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, " ==> nxge_rxdma_cfg_rcr_timeout")); 51444961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 51544961713Sgirish if (enable == 0) { 51644961713Sgirish rs = npi_rxdma_cfg_rdc_rcr_timeout_disable(handle, channel); 51744961713Sgirish } else { 51844961713Sgirish rs = npi_rxdma_cfg_rdc_rcr_timeout(handle, channel, 51952ccf843Smisaki tout); 52044961713Sgirish } 52144961713Sgirish 52244961713Sgirish if (rs != NPI_SUCCESS) { 52344961713Sgirish return (NXGE_ERROR | rs); 52444961713Sgirish } 52544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_timeout")); 52644961713Sgirish return (NXGE_OK); 52744961713Sgirish } 52844961713Sgirish 52944961713Sgirish nxge_status_t 53044961713Sgirish nxge_enable_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 53144961713Sgirish p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p) 53244961713Sgirish { 53344961713Sgirish npi_handle_t handle; 53444961713Sgirish rdc_desc_cfg_t rdc_desc; 53544961713Sgirish p_rcrcfig_b_t cfgb_p; 53644961713Sgirish npi_status_t rs = NPI_SUCCESS; 53744961713Sgirish 53844961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel")); 53944961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 54044961713Sgirish /* 54144961713Sgirish * Use configuration data composed at init time. 54244961713Sgirish * Write to hardware the receive ring configurations. 54344961713Sgirish */ 54444961713Sgirish rdc_desc.mbox_enable = 1; 54544961713Sgirish rdc_desc.mbox_addr = mbox_p->mbox_addr; 54644961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 54752ccf843Smisaki "==> nxge_enable_rxdma_channel: mboxp $%p($%p)", 54852ccf843Smisaki mbox_p->mbox_addr, rdc_desc.mbox_addr)); 54944961713Sgirish 55044961713Sgirish rdc_desc.rbr_len = rbr_p->rbb_max; 55144961713Sgirish rdc_desc.rbr_addr = rbr_p->rbr_addr; 55244961713Sgirish 55344961713Sgirish switch (nxgep->rx_bksize_code) { 55444961713Sgirish case RBR_BKSIZE_4K: 55544961713Sgirish rdc_desc.page_size = SIZE_4KB; 55644961713Sgirish break; 55744961713Sgirish case RBR_BKSIZE_8K: 55844961713Sgirish rdc_desc.page_size = SIZE_8KB; 55944961713Sgirish break; 56044961713Sgirish case RBR_BKSIZE_16K: 56144961713Sgirish rdc_desc.page_size = SIZE_16KB; 56244961713Sgirish break; 56344961713Sgirish case RBR_BKSIZE_32K: 56444961713Sgirish rdc_desc.page_size = SIZE_32KB; 56544961713Sgirish break; 56644961713Sgirish } 56744961713Sgirish 56844961713Sgirish rdc_desc.size0 = rbr_p->npi_pkt_buf_size0; 56944961713Sgirish rdc_desc.valid0 = 1; 57044961713Sgirish 57144961713Sgirish rdc_desc.size1 = rbr_p->npi_pkt_buf_size1; 57244961713Sgirish rdc_desc.valid1 = 1; 57344961713Sgirish 57444961713Sgirish rdc_desc.size2 = rbr_p->npi_pkt_buf_size2; 57544961713Sgirish rdc_desc.valid2 = 1; 57644961713Sgirish 57744961713Sgirish rdc_desc.full_hdr = rcr_p->full_hdr_flag; 57844961713Sgirish rdc_desc.offset = rcr_p->sw_priv_hdr_len; 57944961713Sgirish 58044961713Sgirish rdc_desc.rcr_len = rcr_p->comp_size; 58144961713Sgirish rdc_desc.rcr_addr = rcr_p->rcr_addr; 58244961713Sgirish 58344961713Sgirish cfgb_p = &(rcr_p->rcr_cfgb); 58444961713Sgirish rdc_desc.rcr_threshold = cfgb_p->bits.ldw.pthres; 585678453a8Sspeer /* For now, disable this timeout in a guest domain. */ 586678453a8Sspeer if (isLDOMguest(nxgep)) { 587678453a8Sspeer rdc_desc.rcr_timeout = 0; 588678453a8Sspeer rdc_desc.rcr_timeout_enable = 0; 589678453a8Sspeer } else { 590678453a8Sspeer rdc_desc.rcr_timeout = cfgb_p->bits.ldw.timeout; 591678453a8Sspeer rdc_desc.rcr_timeout_enable = cfgb_p->bits.ldw.entout; 592678453a8Sspeer } 59344961713Sgirish 59444961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: " 59552ccf843Smisaki "rbr_len qlen %d pagesize code %d rcr_len %d", 59652ccf843Smisaki rdc_desc.rbr_len, rdc_desc.page_size, rdc_desc.rcr_len)); 59744961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: " 59852ccf843Smisaki "size 0 %d size 1 %d size 2 %d", 59952ccf843Smisaki rbr_p->npi_pkt_buf_size0, rbr_p->npi_pkt_buf_size1, 60052ccf843Smisaki rbr_p->npi_pkt_buf_size2)); 60144961713Sgirish 602*4df55fdeSJanie Lu if (nxgep->niu_hw_type == NIU_HW_TYPE_RF) 603*4df55fdeSJanie Lu rs = npi_rxdma_cfg_rdc_ring(handle, rbr_p->rdc, 604*4df55fdeSJanie Lu &rdc_desc, B_TRUE); 605*4df55fdeSJanie Lu else 606*4df55fdeSJanie Lu rs = npi_rxdma_cfg_rdc_ring(handle, rbr_p->rdc, 607*4df55fdeSJanie Lu &rdc_desc, B_FALSE); 60844961713Sgirish if (rs != NPI_SUCCESS) { 60944961713Sgirish return (NXGE_ERROR | rs); 61044961713Sgirish } 61144961713Sgirish 61244961713Sgirish /* 61344961713Sgirish * Enable the timeout and threshold. 61444961713Sgirish */ 61544961713Sgirish rs = npi_rxdma_cfg_rdc_rcr_threshold(handle, channel, 61652ccf843Smisaki rdc_desc.rcr_threshold); 61744961713Sgirish if (rs != NPI_SUCCESS) { 61844961713Sgirish return (NXGE_ERROR | rs); 61944961713Sgirish } 62044961713Sgirish 62144961713Sgirish rs = npi_rxdma_cfg_rdc_rcr_timeout(handle, channel, 62252ccf843Smisaki rdc_desc.rcr_timeout); 62344961713Sgirish if (rs != NPI_SUCCESS) { 62444961713Sgirish return (NXGE_ERROR | rs); 62544961713Sgirish } 62644961713Sgirish 627e759c33aSMichael Speer if (!isLDOMguest(nxgep)) { 628e759c33aSMichael Speer /* Enable the DMA */ 629e759c33aSMichael Speer rs = npi_rxdma_cfg_rdc_enable(handle, channel); 630e759c33aSMichael Speer if (rs != NPI_SUCCESS) { 631e759c33aSMichael Speer return (NXGE_ERROR | rs); 632e759c33aSMichael Speer } 63344961713Sgirish } 63444961713Sgirish 63544961713Sgirish /* Kick the DMA engine. */ 63644961713Sgirish npi_rxdma_rdc_rbr_kick(handle, channel, rbr_p->rbb_max); 637e759c33aSMichael Speer 638e759c33aSMichael Speer if (!isLDOMguest(nxgep)) { 639e759c33aSMichael Speer /* Clear the rbr empty bit */ 640e759c33aSMichael Speer (void) npi_rxdma_channel_rbr_empty_clear(handle, channel); 641e759c33aSMichael Speer } 64244961713Sgirish 64344961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_enable_rxdma_channel")); 64444961713Sgirish 64544961713Sgirish return (NXGE_OK); 64644961713Sgirish } 64744961713Sgirish 64844961713Sgirish nxge_status_t 64944961713Sgirish nxge_disable_rxdma_channel(p_nxge_t nxgep, uint16_t channel) 65044961713Sgirish { 65144961713Sgirish npi_handle_t handle; 65244961713Sgirish npi_status_t rs = NPI_SUCCESS; 65344961713Sgirish 65444961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_disable_rxdma_channel")); 65544961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 65644961713Sgirish 65744961713Sgirish /* disable the DMA */ 65844961713Sgirish rs = npi_rxdma_cfg_rdc_disable(handle, channel); 65944961713Sgirish if (rs != NPI_SUCCESS) { 66044961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 66152ccf843Smisaki "<== nxge_disable_rxdma_channel:failed (0x%x)", 66252ccf843Smisaki rs)); 66344961713Sgirish return (NXGE_ERROR | rs); 66444961713Sgirish } 66544961713Sgirish 66644961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_disable_rxdma_channel")); 66744961713Sgirish return (NXGE_OK); 66844961713Sgirish } 66944961713Sgirish 67044961713Sgirish nxge_status_t 67144961713Sgirish nxge_rxdma_channel_rcrflush(p_nxge_t nxgep, uint8_t channel) 67244961713Sgirish { 67344961713Sgirish npi_handle_t handle; 67444961713Sgirish nxge_status_t status = NXGE_OK; 67544961713Sgirish 67644961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 67752ccf843Smisaki "<== nxge_init_rxdma_channel_rcrflush")); 67844961713Sgirish 67944961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 68044961713Sgirish npi_rxdma_rdc_rcr_flush(handle, channel); 68144961713Sgirish 68244961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 68352ccf843Smisaki "<== nxge_init_rxdma_channel_rcrflsh")); 68444961713Sgirish return (status); 68544961713Sgirish 68644961713Sgirish } 68744961713Sgirish 68844961713Sgirish #define MID_INDEX(l, r) ((r + l + 1) >> 1) 68944961713Sgirish 69044961713Sgirish #define TO_LEFT -1 69144961713Sgirish #define TO_RIGHT 1 69244961713Sgirish #define BOTH_RIGHT (TO_RIGHT + TO_RIGHT) 69344961713Sgirish #define BOTH_LEFT (TO_LEFT + TO_LEFT) 69444961713Sgirish #define IN_MIDDLE (TO_RIGHT + TO_LEFT) 69544961713Sgirish #define NO_HINT 0xffffffff 69644961713Sgirish 69744961713Sgirish /*ARGSUSED*/ 69844961713Sgirish nxge_status_t 69944961713Sgirish nxge_rxbuf_pp_to_vp(p_nxge_t nxgep, p_rx_rbr_ring_t rbr_p, 700a3c5bd6dSspeer uint8_t pktbufsz_type, uint64_t *pkt_buf_addr_pp, 701a3c5bd6dSspeer uint64_t **pkt_buf_addr_p, uint32_t *bufoffset, uint32_t *msg_index) 70244961713Sgirish { 70344961713Sgirish int bufsize; 70444961713Sgirish uint64_t pktbuf_pp; 70544961713Sgirish uint64_t dvma_addr; 70644961713Sgirish rxring_info_t *ring_info; 70744961713Sgirish int base_side, end_side; 70844961713Sgirish int r_index, l_index, anchor_index; 70944961713Sgirish int found, search_done; 71044961713Sgirish uint32_t offset, chunk_size, block_size, page_size_mask; 71144961713Sgirish uint32_t chunk_index, block_index, total_index; 71244961713Sgirish int max_iterations, iteration; 71344961713Sgirish rxbuf_index_info_t *bufinfo; 71444961713Sgirish 71544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> nxge_rxbuf_pp_to_vp")); 71644961713Sgirish 71744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 71852ccf843Smisaki "==> nxge_rxbuf_pp_to_vp: buf_pp $%p btype %d", 71952ccf843Smisaki pkt_buf_addr_pp, 72052ccf843Smisaki pktbufsz_type)); 721adfcba55Sjoycey #if defined(__i386) 722adfcba55Sjoycey pktbuf_pp = (uint64_t)(uint32_t)pkt_buf_addr_pp; 723adfcba55Sjoycey #else 72444961713Sgirish pktbuf_pp = (uint64_t)pkt_buf_addr_pp; 725adfcba55Sjoycey #endif 72644961713Sgirish 72744961713Sgirish switch (pktbufsz_type) { 72844961713Sgirish case 0: 72944961713Sgirish bufsize = rbr_p->pkt_buf_size0; 73044961713Sgirish break; 73144961713Sgirish case 1: 73244961713Sgirish bufsize = rbr_p->pkt_buf_size1; 73344961713Sgirish break; 73444961713Sgirish case 2: 73544961713Sgirish bufsize = rbr_p->pkt_buf_size2; 73644961713Sgirish break; 73744961713Sgirish case RCR_SINGLE_BLOCK: 73844961713Sgirish bufsize = 0; 73944961713Sgirish anchor_index = 0; 74044961713Sgirish break; 74144961713Sgirish default: 74244961713Sgirish return (NXGE_ERROR); 74344961713Sgirish } 74444961713Sgirish 74544961713Sgirish if (rbr_p->num_blocks == 1) { 74644961713Sgirish anchor_index = 0; 74744961713Sgirish ring_info = rbr_p->ring_info; 74844961713Sgirish bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 74944961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 75052ccf843Smisaki "==> nxge_rxbuf_pp_to_vp: (found, 1 block) " 75152ccf843Smisaki "buf_pp $%p btype %d anchor_index %d " 75252ccf843Smisaki "bufinfo $%p", 75352ccf843Smisaki pkt_buf_addr_pp, 75452ccf843Smisaki pktbufsz_type, 75552ccf843Smisaki anchor_index, 75652ccf843Smisaki bufinfo)); 75744961713Sgirish 75844961713Sgirish goto found_index; 75944961713Sgirish } 76044961713Sgirish 76144961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 76252ccf843Smisaki "==> nxge_rxbuf_pp_to_vp: " 76352ccf843Smisaki "buf_pp $%p btype %d anchor_index %d", 76452ccf843Smisaki pkt_buf_addr_pp, 76552ccf843Smisaki pktbufsz_type, 76652ccf843Smisaki anchor_index)); 76744961713Sgirish 76844961713Sgirish ring_info = rbr_p->ring_info; 76944961713Sgirish found = B_FALSE; 77044961713Sgirish bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 77144961713Sgirish iteration = 0; 77244961713Sgirish max_iterations = ring_info->max_iterations; 77344961713Sgirish /* 774a3c5bd6dSspeer * First check if this block has been seen 77544961713Sgirish * recently. This is indicated by a hint which 77644961713Sgirish * is initialized when the first buffer of the block 77744961713Sgirish * is seen. The hint is reset when the last buffer of 77844961713Sgirish * the block has been processed. 77944961713Sgirish * As three block sizes are supported, three hints 78044961713Sgirish * are kept. The idea behind the hints is that once 78144961713Sgirish * the hardware uses a block for a buffer of that 78244961713Sgirish * size, it will use it exclusively for that size 78344961713Sgirish * and will use it until it is exhausted. It is assumed 78444961713Sgirish * that there would a single block being used for the same 78544961713Sgirish * buffer sizes at any given time. 78644961713Sgirish */ 78744961713Sgirish if (ring_info->hint[pktbufsz_type] != NO_HINT) { 78844961713Sgirish anchor_index = ring_info->hint[pktbufsz_type]; 78944961713Sgirish dvma_addr = bufinfo[anchor_index].dvma_addr; 79044961713Sgirish chunk_size = bufinfo[anchor_index].buf_size; 79144961713Sgirish if ((pktbuf_pp >= dvma_addr) && 79252ccf843Smisaki (pktbuf_pp < (dvma_addr + chunk_size))) { 79344961713Sgirish found = B_TRUE; 79444961713Sgirish /* 79544961713Sgirish * check if this is the last buffer in the block 79644961713Sgirish * If so, then reset the hint for the size; 79744961713Sgirish */ 79844961713Sgirish 79944961713Sgirish if ((pktbuf_pp + bufsize) >= (dvma_addr + chunk_size)) 80044961713Sgirish ring_info->hint[pktbufsz_type] = NO_HINT; 80144961713Sgirish } 80244961713Sgirish } 80344961713Sgirish 80444961713Sgirish if (found == B_FALSE) { 80544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 80652ccf843Smisaki "==> nxge_rxbuf_pp_to_vp: (!found)" 80752ccf843Smisaki "buf_pp $%p btype %d anchor_index %d", 80852ccf843Smisaki pkt_buf_addr_pp, 80952ccf843Smisaki pktbufsz_type, 81052ccf843Smisaki anchor_index)); 81144961713Sgirish 81244961713Sgirish /* 81344961713Sgirish * This is the first buffer of the block of this 81444961713Sgirish * size. Need to search the whole information 81544961713Sgirish * array. 81644961713Sgirish * the search algorithm uses a binary tree search 81744961713Sgirish * algorithm. It assumes that the information is 81844961713Sgirish * already sorted with increasing order 81944961713Sgirish * info[0] < info[1] < info[2] .... < info[n-1] 82044961713Sgirish * where n is the size of the information array 82144961713Sgirish */ 82244961713Sgirish r_index = rbr_p->num_blocks - 1; 82344961713Sgirish l_index = 0; 82444961713Sgirish search_done = B_FALSE; 82544961713Sgirish anchor_index = MID_INDEX(r_index, l_index); 82644961713Sgirish while (search_done == B_FALSE) { 82744961713Sgirish if ((r_index == l_index) || 82852ccf843Smisaki (iteration >= max_iterations)) 82944961713Sgirish search_done = B_TRUE; 83044961713Sgirish end_side = TO_RIGHT; /* to the right */ 83144961713Sgirish base_side = TO_LEFT; /* to the left */ 83244961713Sgirish /* read the DVMA address information and sort it */ 83344961713Sgirish dvma_addr = bufinfo[anchor_index].dvma_addr; 83444961713Sgirish chunk_size = bufinfo[anchor_index].buf_size; 83544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 83652ccf843Smisaki "==> nxge_rxbuf_pp_to_vp: (searching)" 83752ccf843Smisaki "buf_pp $%p btype %d " 83852ccf843Smisaki "anchor_index %d chunk_size %d dvmaaddr $%p", 83952ccf843Smisaki pkt_buf_addr_pp, 84052ccf843Smisaki pktbufsz_type, 84152ccf843Smisaki anchor_index, 84252ccf843Smisaki chunk_size, 84352ccf843Smisaki dvma_addr)); 84444961713Sgirish 84544961713Sgirish if (pktbuf_pp >= dvma_addr) 84644961713Sgirish base_side = TO_RIGHT; /* to the right */ 84744961713Sgirish if (pktbuf_pp < (dvma_addr + chunk_size)) 84844961713Sgirish end_side = TO_LEFT; /* to the left */ 84944961713Sgirish 85044961713Sgirish switch (base_side + end_side) { 85152ccf843Smisaki case IN_MIDDLE: 85252ccf843Smisaki /* found */ 85352ccf843Smisaki found = B_TRUE; 85452ccf843Smisaki search_done = B_TRUE; 85552ccf843Smisaki if ((pktbuf_pp + bufsize) < 85652ccf843Smisaki (dvma_addr + chunk_size)) 85752ccf843Smisaki ring_info->hint[pktbufsz_type] = 85852ccf843Smisaki bufinfo[anchor_index].buf_index; 85952ccf843Smisaki break; 86052ccf843Smisaki case BOTH_RIGHT: 86152ccf843Smisaki /* not found: go to the right */ 86252ccf843Smisaki l_index = anchor_index + 1; 86352ccf843Smisaki anchor_index = MID_INDEX(r_index, l_index); 86452ccf843Smisaki break; 86552ccf843Smisaki 86652ccf843Smisaki case BOTH_LEFT: 86752ccf843Smisaki /* not found: go to the left */ 86852ccf843Smisaki r_index = anchor_index - 1; 86952ccf843Smisaki anchor_index = MID_INDEX(r_index, l_index); 87052ccf843Smisaki break; 87152ccf843Smisaki default: /* should not come here */ 87252ccf843Smisaki return (NXGE_ERROR); 87344961713Sgirish } 87444961713Sgirish iteration++; 87544961713Sgirish } 87644961713Sgirish 87744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 87852ccf843Smisaki "==> nxge_rxbuf_pp_to_vp: (search done)" 87952ccf843Smisaki "buf_pp $%p btype %d anchor_index %d", 88052ccf843Smisaki pkt_buf_addr_pp, 88152ccf843Smisaki pktbufsz_type, 88252ccf843Smisaki anchor_index)); 88344961713Sgirish } 88444961713Sgirish 88544961713Sgirish if (found == B_FALSE) { 88644961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 88752ccf843Smisaki "==> nxge_rxbuf_pp_to_vp: (search failed)" 88852ccf843Smisaki "buf_pp $%p btype %d anchor_index %d", 88952ccf843Smisaki pkt_buf_addr_pp, 89052ccf843Smisaki pktbufsz_type, 89152ccf843Smisaki anchor_index)); 89244961713Sgirish return (NXGE_ERROR); 89344961713Sgirish } 89444961713Sgirish 89544961713Sgirish found_index: 89644961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 89752ccf843Smisaki "==> nxge_rxbuf_pp_to_vp: (FOUND1)" 89852ccf843Smisaki "buf_pp $%p btype %d bufsize %d anchor_index %d", 89952ccf843Smisaki pkt_buf_addr_pp, 90052ccf843Smisaki pktbufsz_type, 90152ccf843Smisaki bufsize, 90252ccf843Smisaki anchor_index)); 90344961713Sgirish 90444961713Sgirish /* index of the first block in this chunk */ 90544961713Sgirish chunk_index = bufinfo[anchor_index].start_index; 90644961713Sgirish dvma_addr = bufinfo[anchor_index].dvma_addr; 90744961713Sgirish page_size_mask = ring_info->block_size_mask; 90844961713Sgirish 90944961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 91052ccf843Smisaki "==> nxge_rxbuf_pp_to_vp: (FOUND3), get chunk)" 91152ccf843Smisaki "buf_pp $%p btype %d bufsize %d " 91252ccf843Smisaki "anchor_index %d chunk_index %d dvma $%p", 91352ccf843Smisaki pkt_buf_addr_pp, 91452ccf843Smisaki pktbufsz_type, 91552ccf843Smisaki bufsize, 91652ccf843Smisaki anchor_index, 91752ccf843Smisaki chunk_index, 91852ccf843Smisaki dvma_addr)); 91944961713Sgirish 92044961713Sgirish offset = pktbuf_pp - dvma_addr; /* offset within the chunk */ 92144961713Sgirish block_size = rbr_p->block_size; /* System block(page) size */ 92244961713Sgirish 92344961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 92452ccf843Smisaki "==> nxge_rxbuf_pp_to_vp: (FOUND4), get chunk)" 92552ccf843Smisaki "buf_pp $%p btype %d bufsize %d " 92652ccf843Smisaki "anchor_index %d chunk_index %d dvma $%p " 92752ccf843Smisaki "offset %d block_size %d", 92852ccf843Smisaki pkt_buf_addr_pp, 92952ccf843Smisaki pktbufsz_type, 93052ccf843Smisaki bufsize, 93152ccf843Smisaki anchor_index, 93252ccf843Smisaki chunk_index, 93352ccf843Smisaki dvma_addr, 93452ccf843Smisaki offset, 93552ccf843Smisaki block_size)); 93644961713Sgirish 93744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> getting total index")); 93844961713Sgirish 93944961713Sgirish block_index = (offset / block_size); /* index within chunk */ 94044961713Sgirish total_index = chunk_index + block_index; 94144961713Sgirish 94244961713Sgirish 94344961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 94452ccf843Smisaki "==> nxge_rxbuf_pp_to_vp: " 94552ccf843Smisaki "total_index %d dvma_addr $%p " 94652ccf843Smisaki "offset %d block_size %d " 94752ccf843Smisaki "block_index %d ", 94852ccf843Smisaki total_index, dvma_addr, 94952ccf843Smisaki offset, block_size, 95052ccf843Smisaki block_index)); 951adfcba55Sjoycey #if defined(__i386) 952adfcba55Sjoycey *pkt_buf_addr_p = (uint64_t *)((uint32_t)bufinfo[anchor_index].kaddr + 95352ccf843Smisaki (uint32_t)offset); 954adfcba55Sjoycey #else 955adfcba55Sjoycey *pkt_buf_addr_p = (uint64_t *)((uint64_t)bufinfo[anchor_index].kaddr + 95652ccf843Smisaki (uint64_t)offset); 957adfcba55Sjoycey #endif 95844961713Sgirish 95944961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 96052ccf843Smisaki "==> nxge_rxbuf_pp_to_vp: " 96152ccf843Smisaki "total_index %d dvma_addr $%p " 96252ccf843Smisaki "offset %d block_size %d " 96352ccf843Smisaki "block_index %d " 96452ccf843Smisaki "*pkt_buf_addr_p $%p", 96552ccf843Smisaki total_index, dvma_addr, 96652ccf843Smisaki offset, block_size, 96752ccf843Smisaki block_index, 96852ccf843Smisaki *pkt_buf_addr_p)); 96944961713Sgirish 97044961713Sgirish 97144961713Sgirish *msg_index = total_index; 97244961713Sgirish *bufoffset = (offset & page_size_mask); 97344961713Sgirish 97444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 97552ccf843Smisaki "==> nxge_rxbuf_pp_to_vp: get msg index: " 97652ccf843Smisaki "msg_index %d bufoffset_index %d", 97752ccf843Smisaki *msg_index, 97852ccf843Smisaki *bufoffset)); 97944961713Sgirish 98044961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, "<== nxge_rxbuf_pp_to_vp")); 98144961713Sgirish 98244961713Sgirish return (NXGE_OK); 98344961713Sgirish } 98444961713Sgirish 98544961713Sgirish /* 98644961713Sgirish * used by quick sort (qsort) function 98744961713Sgirish * to perform comparison 98844961713Sgirish */ 98944961713Sgirish static int 99044961713Sgirish nxge_sort_compare(const void *p1, const void *p2) 99144961713Sgirish { 99244961713Sgirish 99344961713Sgirish rxbuf_index_info_t *a, *b; 99444961713Sgirish 99544961713Sgirish a = (rxbuf_index_info_t *)p1; 99644961713Sgirish b = (rxbuf_index_info_t *)p2; 99744961713Sgirish 99844961713Sgirish if (a->dvma_addr > b->dvma_addr) 99944961713Sgirish return (1); 100044961713Sgirish if (a->dvma_addr < b->dvma_addr) 100144961713Sgirish return (-1); 100244961713Sgirish return (0); 100344961713Sgirish } 100444961713Sgirish 100544961713Sgirish 100644961713Sgirish 100744961713Sgirish /* 100844961713Sgirish * grabbed this sort implementation from common/syscall/avl.c 100944961713Sgirish * 101044961713Sgirish */ 101144961713Sgirish /* 101244961713Sgirish * Generic shellsort, from K&R (1st ed, p 58.), somewhat modified. 101344961713Sgirish * v = Ptr to array/vector of objs 101444961713Sgirish * n = # objs in the array 101544961713Sgirish * s = size of each obj (must be multiples of a word size) 101644961713Sgirish * f = ptr to function to compare two objs 101744961713Sgirish * returns (-1 = less than, 0 = equal, 1 = greater than 101844961713Sgirish */ 101944961713Sgirish void 102044961713Sgirish nxge_ksort(caddr_t v, int n, int s, int (*f)()) 102144961713Sgirish { 102244961713Sgirish int g, i, j, ii; 102344961713Sgirish unsigned int *p1, *p2; 102444961713Sgirish unsigned int tmp; 102544961713Sgirish 102644961713Sgirish /* No work to do */ 102744961713Sgirish if (v == NULL || n <= 1) 102844961713Sgirish return; 102944961713Sgirish /* Sanity check on arguments */ 103044961713Sgirish ASSERT(((uintptr_t)v & 0x3) == 0 && (s & 0x3) == 0); 103144961713Sgirish ASSERT(s > 0); 103244961713Sgirish 103344961713Sgirish for (g = n / 2; g > 0; g /= 2) { 103444961713Sgirish for (i = g; i < n; i++) { 103544961713Sgirish for (j = i - g; j >= 0 && 103652ccf843Smisaki (*f)(v + j * s, v + (j + g) * s) == 1; 103752ccf843Smisaki j -= g) { 103844961713Sgirish p1 = (unsigned *)(v + j * s); 103944961713Sgirish p2 = (unsigned *)(v + (j + g) * s); 104044961713Sgirish for (ii = 0; ii < s / 4; ii++) { 104144961713Sgirish tmp = *p1; 104244961713Sgirish *p1++ = *p2; 104344961713Sgirish *p2++ = tmp; 104444961713Sgirish } 104544961713Sgirish } 104644961713Sgirish } 104744961713Sgirish } 104844961713Sgirish } 104944961713Sgirish 105044961713Sgirish /* 105144961713Sgirish * Initialize data structures required for rxdma 105244961713Sgirish * buffer dvma->vmem address lookup 105344961713Sgirish */ 105444961713Sgirish /*ARGSUSED*/ 105544961713Sgirish static nxge_status_t 105644961713Sgirish nxge_rxbuf_index_info_init(p_nxge_t nxgep, p_rx_rbr_ring_t rbrp) 105744961713Sgirish { 105844961713Sgirish 105944961713Sgirish int index; 106044961713Sgirish rxring_info_t *ring_info; 106144961713Sgirish int max_iteration = 0, max_index = 0; 106244961713Sgirish 106344961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_rxbuf_index_info_init")); 106444961713Sgirish 106544961713Sgirish ring_info = rbrp->ring_info; 106644961713Sgirish ring_info->hint[0] = NO_HINT; 106744961713Sgirish ring_info->hint[1] = NO_HINT; 106844961713Sgirish ring_info->hint[2] = NO_HINT; 106944961713Sgirish max_index = rbrp->num_blocks; 107044961713Sgirish 107144961713Sgirish /* read the DVMA address information and sort it */ 107244961713Sgirish /* do init of the information array */ 107344961713Sgirish 107444961713Sgirish 107544961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 107652ccf843Smisaki " nxge_rxbuf_index_info_init Sort ptrs")); 107744961713Sgirish 107844961713Sgirish /* sort the array */ 107944961713Sgirish nxge_ksort((void *)ring_info->buffer, max_index, 108052ccf843Smisaki sizeof (rxbuf_index_info_t), nxge_sort_compare); 108144961713Sgirish 108244961713Sgirish 108344961713Sgirish 108444961713Sgirish for (index = 0; index < max_index; index++) { 108544961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 108652ccf843Smisaki " nxge_rxbuf_index_info_init: sorted chunk %d " 108752ccf843Smisaki " ioaddr $%p kaddr $%p size %x", 108852ccf843Smisaki index, ring_info->buffer[index].dvma_addr, 108952ccf843Smisaki ring_info->buffer[index].kaddr, 109052ccf843Smisaki ring_info->buffer[index].buf_size)); 109144961713Sgirish } 109244961713Sgirish 109344961713Sgirish max_iteration = 0; 109444961713Sgirish while (max_index >= (1ULL << max_iteration)) 109544961713Sgirish max_iteration++; 109644961713Sgirish ring_info->max_iterations = max_iteration + 1; 109744961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 109852ccf843Smisaki " nxge_rxbuf_index_info_init Find max iter %d", 109952ccf843Smisaki ring_info->max_iterations)); 110044961713Sgirish 110144961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxbuf_index_info_init")); 110244961713Sgirish return (NXGE_OK); 110344961713Sgirish } 110444961713Sgirish 11050a8e077aSspeer /* ARGSUSED */ 110644961713Sgirish void 110744961713Sgirish nxge_dump_rcr_entry(p_nxge_t nxgep, p_rcr_entry_t entry_p) 110844961713Sgirish { 110944961713Sgirish #ifdef NXGE_DEBUG 111044961713Sgirish 111144961713Sgirish uint32_t bptr; 111244961713Sgirish uint64_t pp; 111344961713Sgirish 111444961713Sgirish bptr = entry_p->bits.hdw.pkt_buf_addr; 111544961713Sgirish 111644961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 111752ccf843Smisaki "\trcr entry $%p " 111852ccf843Smisaki "\trcr entry 0x%0llx " 111952ccf843Smisaki "\trcr entry 0x%08x " 112052ccf843Smisaki "\trcr entry 0x%08x " 112152ccf843Smisaki "\tvalue 0x%0llx\n" 112252ccf843Smisaki "\tmulti = %d\n" 112352ccf843Smisaki "\tpkt_type = 0x%x\n" 112452ccf843Smisaki "\tzero_copy = %d\n" 112552ccf843Smisaki "\tnoport = %d\n" 112652ccf843Smisaki "\tpromis = %d\n" 112752ccf843Smisaki "\terror = 0x%04x\n" 112852ccf843Smisaki "\tdcf_err = 0x%01x\n" 112952ccf843Smisaki "\tl2_len = %d\n" 113052ccf843Smisaki "\tpktbufsize = %d\n" 113152ccf843Smisaki "\tpkt_buf_addr = $%p\n" 113252ccf843Smisaki "\tpkt_buf_addr (<< 6) = $%p\n", 113352ccf843Smisaki entry_p, 113452ccf843Smisaki *(int64_t *)entry_p, 113552ccf843Smisaki *(int32_t *)entry_p, 113652ccf843Smisaki *(int32_t *)((char *)entry_p + 32), 113752ccf843Smisaki entry_p->value, 113852ccf843Smisaki entry_p->bits.hdw.multi, 113952ccf843Smisaki entry_p->bits.hdw.pkt_type, 114052ccf843Smisaki entry_p->bits.hdw.zero_copy, 114152ccf843Smisaki entry_p->bits.hdw.noport, 114252ccf843Smisaki entry_p->bits.hdw.promis, 114352ccf843Smisaki entry_p->bits.hdw.error, 114452ccf843Smisaki entry_p->bits.hdw.dcf_err, 114552ccf843Smisaki entry_p->bits.hdw.l2_len, 114652ccf843Smisaki entry_p->bits.hdw.pktbufsz, 114752ccf843Smisaki bptr, 114852ccf843Smisaki entry_p->bits.ldw.pkt_buf_addr)); 114944961713Sgirish 115044961713Sgirish pp = (entry_p->value & RCR_PKT_BUF_ADDR_MASK) << 115152ccf843Smisaki RCR_PKT_BUF_ADDR_SHIFT; 115244961713Sgirish 115344961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "rcr pp 0x%llx l2 len %d", 115452ccf843Smisaki pp, (*(int64_t *)entry_p >> 40) & 0x3fff)); 115544961713Sgirish #endif 115644961713Sgirish } 115744961713Sgirish 115844961713Sgirish void 115944961713Sgirish nxge_rxdma_regs_dump(p_nxge_t nxgep, int rdc) 116044961713Sgirish { 116144961713Sgirish npi_handle_t handle; 116244961713Sgirish rbr_stat_t rbr_stat; 116344961713Sgirish addr44_t hd_addr; 116444961713Sgirish addr44_t tail_addr; 116544961713Sgirish uint16_t qlen; 116644961713Sgirish 116744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 116852ccf843Smisaki "==> nxge_rxdma_regs_dump: rdc channel %d", rdc)); 116944961713Sgirish 117044961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 117144961713Sgirish 117244961713Sgirish /* RBR head */ 117344961713Sgirish hd_addr.addr = 0; 117444961713Sgirish (void) npi_rxdma_rdc_rbr_head_get(handle, rdc, &hd_addr); 1175adfcba55Sjoycey #if defined(__i386) 117653f3d8ecSyc printf("nxge_rxdma_regs_dump: got hdptr $%p \n", 117752ccf843Smisaki (void *)(uint32_t)hd_addr.addr); 1178adfcba55Sjoycey #else 117953f3d8ecSyc printf("nxge_rxdma_regs_dump: got hdptr $%p \n", 118052ccf843Smisaki (void *)hd_addr.addr); 1181adfcba55Sjoycey #endif 118244961713Sgirish 118344961713Sgirish /* RBR stats */ 118444961713Sgirish (void) npi_rxdma_rdc_rbr_stat_get(handle, rdc, &rbr_stat); 118544961713Sgirish printf("nxge_rxdma_regs_dump: rbr len %d \n", rbr_stat.bits.ldw.qlen); 118644961713Sgirish 118744961713Sgirish /* RCR tail */ 118844961713Sgirish tail_addr.addr = 0; 118944961713Sgirish (void) npi_rxdma_rdc_rcr_tail_get(handle, rdc, &tail_addr); 1190adfcba55Sjoycey #if defined(__i386) 119153f3d8ecSyc printf("nxge_rxdma_regs_dump: got tail ptr $%p \n", 119252ccf843Smisaki (void *)(uint32_t)tail_addr.addr); 1193adfcba55Sjoycey #else 119453f3d8ecSyc printf("nxge_rxdma_regs_dump: got tail ptr $%p \n", 119552ccf843Smisaki (void *)tail_addr.addr); 1196adfcba55Sjoycey #endif 119744961713Sgirish 119844961713Sgirish /* RCR qlen */ 119944961713Sgirish (void) npi_rxdma_rdc_rcr_qlen_get(handle, rdc, &qlen); 120044961713Sgirish printf("nxge_rxdma_regs_dump: rcr len %x \n", qlen); 120144961713Sgirish 120244961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 120352ccf843Smisaki "<== nxge_rxdma_regs_dump: rdc rdc %d", rdc)); 120444961713Sgirish } 120544961713Sgirish 120644961713Sgirish nxge_status_t 120744961713Sgirish nxge_rxdma_hw_mode(p_nxge_t nxgep, boolean_t enable) 120844961713Sgirish { 1209678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set; 1210678453a8Sspeer nxge_status_t status; 1211678453a8Sspeer npi_status_t rs; 1212678453a8Sspeer int rdc; 121344961713Sgirish 121444961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 121552ccf843Smisaki "==> nxge_rxdma_hw_mode: mode %d", enable)); 121644961713Sgirish 121744961713Sgirish if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 121844961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 1219678453a8Sspeer "<== nxge_rxdma_mode: not initialized")); 122044961713Sgirish return (NXGE_ERROR); 122144961713Sgirish } 122244961713Sgirish 1223678453a8Sspeer if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) { 1224678453a8Sspeer NXGE_DEBUG_MSG((nxgep, TX_CTL, 1225678453a8Sspeer "<== nxge_tx_port_fatal_err_recover: " 1226678453a8Sspeer "NULL ring pointer(s)")); 122744961713Sgirish return (NXGE_ERROR); 122844961713Sgirish } 122944961713Sgirish 1230678453a8Sspeer if (set->owned.map == 0) { 123144961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 1232678453a8Sspeer "nxge_rxdma_regs_dump_channels: no channels")); 1233678453a8Sspeer return (NULL); 123444961713Sgirish } 123544961713Sgirish 1236678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1237678453a8Sspeer if ((1 << rdc) & set->owned.map) { 1238678453a8Sspeer rx_rbr_ring_t *ring = 1239678453a8Sspeer nxgep->rx_rbr_rings->rbr_rings[rdc]; 1240678453a8Sspeer npi_handle_t handle = NXGE_DEV_NPI_HANDLE(nxgep); 1241678453a8Sspeer if (ring) { 1242678453a8Sspeer if (enable) { 1243678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1244678453a8Sspeer "==> nxge_rxdma_hw_mode: " 1245678453a8Sspeer "channel %d (enable)", rdc)); 1246678453a8Sspeer rs = npi_rxdma_cfg_rdc_enable 1247678453a8Sspeer (handle, rdc); 1248678453a8Sspeer } else { 1249678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1250678453a8Sspeer "==> nxge_rxdma_hw_mode: " 1251678453a8Sspeer "channel %d disable)", rdc)); 1252678453a8Sspeer rs = npi_rxdma_cfg_rdc_disable 1253678453a8Sspeer (handle, rdc); 1254678453a8Sspeer } 1255678453a8Sspeer } 125644961713Sgirish } 125744961713Sgirish } 125844961713Sgirish 125944961713Sgirish status = ((rs == NPI_SUCCESS) ? NXGE_OK : NXGE_ERROR | rs); 126044961713Sgirish 126144961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 126252ccf843Smisaki "<== nxge_rxdma_hw_mode: status 0x%x", status)); 126344961713Sgirish 126444961713Sgirish return (status); 126544961713Sgirish } 126644961713Sgirish 126744961713Sgirish void 126844961713Sgirish nxge_rxdma_enable_channel(p_nxge_t nxgep, uint16_t channel) 126944961713Sgirish { 127044961713Sgirish npi_handle_t handle; 127144961713Sgirish 127244961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 127352ccf843Smisaki "==> nxge_rxdma_enable_channel: channel %d", channel)); 127444961713Sgirish 127544961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 127644961713Sgirish (void) npi_rxdma_cfg_rdc_enable(handle, channel); 127744961713Sgirish 127844961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxdma_enable_channel")); 127944961713Sgirish } 128044961713Sgirish 128144961713Sgirish void 128244961713Sgirish nxge_rxdma_disable_channel(p_nxge_t nxgep, uint16_t channel) 128344961713Sgirish { 128444961713Sgirish npi_handle_t handle; 128544961713Sgirish 128644961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 128752ccf843Smisaki "==> nxge_rxdma_disable_channel: channel %d", channel)); 128844961713Sgirish 128944961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 129044961713Sgirish (void) npi_rxdma_cfg_rdc_disable(handle, channel); 129144961713Sgirish 129244961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxdma_disable_channel")); 129344961713Sgirish } 129444961713Sgirish 129544961713Sgirish void 129644961713Sgirish nxge_hw_start_rx(p_nxge_t nxgep) 129744961713Sgirish { 129844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_start_rx")); 129944961713Sgirish 130044961713Sgirish (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_START); 130144961713Sgirish (void) nxge_rx_mac_enable(nxgep); 130244961713Sgirish 130344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_start_rx")); 130444961713Sgirish } 130544961713Sgirish 130644961713Sgirish /*ARGSUSED*/ 130744961713Sgirish void 130844961713Sgirish nxge_fixup_rxdma_rings(p_nxge_t nxgep) 130944961713Sgirish { 1310678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set; 1311678453a8Sspeer int rdc; 131244961713Sgirish 131344961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_fixup_rxdma_rings")); 131444961713Sgirish 1315678453a8Sspeer if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) { 1316678453a8Sspeer NXGE_DEBUG_MSG((nxgep, TX_CTL, 1317678453a8Sspeer "<== nxge_tx_port_fatal_err_recover: " 1318678453a8Sspeer "NULL ring pointer(s)")); 131944961713Sgirish return; 132044961713Sgirish } 132144961713Sgirish 1322678453a8Sspeer if (set->owned.map == 0) { 132344961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 1324678453a8Sspeer "nxge_rxdma_regs_dump_channels: no channels")); 132544961713Sgirish return; 132644961713Sgirish } 132744961713Sgirish 1328678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1329678453a8Sspeer if ((1 << rdc) & set->owned.map) { 1330678453a8Sspeer rx_rbr_ring_t *ring = 1331678453a8Sspeer nxgep->rx_rbr_rings->rbr_rings[rdc]; 1332678453a8Sspeer if (ring) { 1333678453a8Sspeer nxge_rxdma_hw_stop(nxgep, rdc); 1334678453a8Sspeer NXGE_DEBUG_MSG((nxgep, RX_CTL, 133552ccf843Smisaki "==> nxge_fixup_rxdma_rings: " 133652ccf843Smisaki "channel %d ring $%px", 133752ccf843Smisaki rdc, ring)); 13383587e8e2SMichael Speer (void) nxge_rxdma_fix_channel(nxgep, rdc); 1339678453a8Sspeer } 1340678453a8Sspeer } 134144961713Sgirish } 134244961713Sgirish 134344961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_fixup_rxdma_rings")); 134444961713Sgirish } 134544961713Sgirish 134644961713Sgirish void 134744961713Sgirish nxge_rxdma_fix_channel(p_nxge_t nxgep, uint16_t channel) 134844961713Sgirish { 134944961713Sgirish int ndmas; 135044961713Sgirish p_rx_rbr_rings_t rx_rbr_rings; 135144961713Sgirish p_rx_rbr_ring_t *rbr_rings; 135244961713Sgirish p_rx_rcr_rings_t rx_rcr_rings; 135344961713Sgirish p_rx_rcr_ring_t *rcr_rings; 135444961713Sgirish p_rx_mbox_areas_t rx_mbox_areas_p; 135544961713Sgirish p_rx_mbox_t *rx_mbox_p; 135644961713Sgirish p_nxge_dma_pool_t dma_buf_poolp; 135744961713Sgirish p_nxge_dma_pool_t dma_cntl_poolp; 135844961713Sgirish p_rx_rbr_ring_t rbrp; 135944961713Sgirish p_rx_rcr_ring_t rcrp; 136044961713Sgirish p_rx_mbox_t mboxp; 136144961713Sgirish p_nxge_dma_common_t dmap; 136244961713Sgirish nxge_status_t status = NXGE_OK; 136344961713Sgirish 13643587e8e2SMichael Speer NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fix_channel")); 136544961713Sgirish 136644961713Sgirish (void) nxge_rxdma_stop_channel(nxgep, channel); 136744961713Sgirish 136844961713Sgirish dma_buf_poolp = nxgep->rx_buf_pool_p; 136944961713Sgirish dma_cntl_poolp = nxgep->rx_cntl_pool_p; 137044961713Sgirish 137144961713Sgirish if (!dma_buf_poolp->buf_allocated || !dma_cntl_poolp->buf_allocated) { 137244961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 13733587e8e2SMichael Speer "<== nxge_rxdma_fix_channel: buf not allocated")); 137444961713Sgirish return; 137544961713Sgirish } 137644961713Sgirish 137744961713Sgirish ndmas = dma_buf_poolp->ndmas; 137844961713Sgirish if (!ndmas) { 137944961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 13803587e8e2SMichael Speer "<== nxge_rxdma_fix_channel: no dma allocated")); 138144961713Sgirish return; 138244961713Sgirish } 138344961713Sgirish 1384a3c5bd6dSspeer rx_rbr_rings = nxgep->rx_rbr_rings; 138544961713Sgirish rx_rcr_rings = nxgep->rx_rcr_rings; 138644961713Sgirish rbr_rings = rx_rbr_rings->rbr_rings; 138744961713Sgirish rcr_rings = rx_rcr_rings->rcr_rings; 138844961713Sgirish rx_mbox_areas_p = nxgep->rx_mbox_areas_p; 138944961713Sgirish rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 139044961713Sgirish 139144961713Sgirish /* Reinitialize the receive block and completion rings */ 13923587e8e2SMichael Speer rbrp = (p_rx_rbr_ring_t)rbr_rings[channel], 13933587e8e2SMichael Speer rcrp = (p_rx_rcr_ring_t)rcr_rings[channel], 13943587e8e2SMichael Speer mboxp = (p_rx_mbox_t)rx_mbox_p[channel]; 139544961713Sgirish 139644961713Sgirish rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 139744961713Sgirish rbrp->rbr_rd_index = 0; 139844961713Sgirish rcrp->comp_rd_index = 0; 139944961713Sgirish rcrp->comp_wt_index = 0; 140044961713Sgirish 140144961713Sgirish dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 140244961713Sgirish bzero((caddr_t)dmap->kaddrp, dmap->alength); 140344961713Sgirish 140444961713Sgirish status = nxge_rxdma_start_channel(nxgep, channel, 140552ccf843Smisaki rbrp, rcrp, mboxp); 140644961713Sgirish if (status != NXGE_OK) { 14073587e8e2SMichael Speer goto nxge_rxdma_fix_channel_fail; 1408da14cebeSEric Cheng } 1409da14cebeSEric Cheng 1410da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, RX_CTL, 14113587e8e2SMichael Speer "<== nxge_rxdma_fix_channel: success (0x%08x)", status)); 14123587e8e2SMichael Speer return; 1413da14cebeSEric Cheng 14143587e8e2SMichael Speer nxge_rxdma_fix_channel_fail: 1415da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, RX_CTL, 14163587e8e2SMichael Speer "<== nxge_rxdma_fix_channel: failed (0x%08x)", status)); 141744961713Sgirish } 141844961713Sgirish 141944961713Sgirish p_rx_rbr_ring_t 142044961713Sgirish nxge_rxdma_get_rbr_ring(p_nxge_t nxgep, uint16_t channel) 142144961713Sgirish { 1422678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set; 1423678453a8Sspeer nxge_channel_t rdc; 142444961713Sgirish 142544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 142652ccf843Smisaki "==> nxge_rxdma_get_rbr_ring: channel %d", channel)); 142744961713Sgirish 1428678453a8Sspeer if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) { 1429678453a8Sspeer NXGE_DEBUG_MSG((nxgep, TX_CTL, 1430678453a8Sspeer "<== nxge_rxdma_get_rbr_ring: " 1431678453a8Sspeer "NULL ring pointer(s)")); 143244961713Sgirish return (NULL); 143344961713Sgirish } 1434678453a8Sspeer 1435678453a8Sspeer if (set->owned.map == 0) { 143644961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 1437678453a8Sspeer "<== nxge_rxdma_get_rbr_ring: no channels")); 143844961713Sgirish return (NULL); 143944961713Sgirish } 144044961713Sgirish 1441678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1442678453a8Sspeer if ((1 << rdc) & set->owned.map) { 1443678453a8Sspeer rx_rbr_ring_t *ring = 1444678453a8Sspeer nxgep->rx_rbr_rings->rbr_rings[rdc]; 1445678453a8Sspeer if (ring) { 1446678453a8Sspeer if (channel == ring->rdc) { 1447678453a8Sspeer NXGE_DEBUG_MSG((nxgep, RX_CTL, 1448678453a8Sspeer "==> nxge_rxdma_get_rbr_ring: " 1449678453a8Sspeer "channel %d ring $%p", rdc, ring)); 1450678453a8Sspeer return (ring); 1451678453a8Sspeer } 1452678453a8Sspeer } 145344961713Sgirish } 145444961713Sgirish } 145544961713Sgirish 145644961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 145752ccf843Smisaki "<== nxge_rxdma_get_rbr_ring: not found")); 145844961713Sgirish 145944961713Sgirish return (NULL); 146044961713Sgirish } 146144961713Sgirish 146244961713Sgirish p_rx_rcr_ring_t 146344961713Sgirish nxge_rxdma_get_rcr_ring(p_nxge_t nxgep, uint16_t channel) 146444961713Sgirish { 1465678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set; 1466678453a8Sspeer nxge_channel_t rdc; 146744961713Sgirish 146844961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 146952ccf843Smisaki "==> nxge_rxdma_get_rcr_ring: channel %d", channel)); 147044961713Sgirish 1471678453a8Sspeer if (nxgep->rx_rcr_rings == 0 || nxgep->rx_rcr_rings->rcr_rings == 0) { 1472678453a8Sspeer NXGE_DEBUG_MSG((nxgep, TX_CTL, 1473678453a8Sspeer "<== nxge_rxdma_get_rcr_ring: " 1474678453a8Sspeer "NULL ring pointer(s)")); 147544961713Sgirish return (NULL); 147644961713Sgirish } 1477678453a8Sspeer 1478678453a8Sspeer if (set->owned.map == 0) { 147944961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 1480678453a8Sspeer "<== nxge_rxdma_get_rbr_ring: no channels")); 148144961713Sgirish return (NULL); 148244961713Sgirish } 148344961713Sgirish 1484678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1485678453a8Sspeer if ((1 << rdc) & set->owned.map) { 1486678453a8Sspeer rx_rcr_ring_t *ring = 1487678453a8Sspeer nxgep->rx_rcr_rings->rcr_rings[rdc]; 1488678453a8Sspeer if (ring) { 1489678453a8Sspeer if (channel == ring->rdc) { 1490678453a8Sspeer NXGE_DEBUG_MSG((nxgep, RX_CTL, 1491678453a8Sspeer "==> nxge_rxdma_get_rcr_ring: " 1492678453a8Sspeer "channel %d ring $%p", rdc, ring)); 1493678453a8Sspeer return (ring); 1494678453a8Sspeer } 1495678453a8Sspeer } 149644961713Sgirish } 149744961713Sgirish } 149844961713Sgirish 149944961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 150052ccf843Smisaki "<== nxge_rxdma_get_rcr_ring: not found")); 150144961713Sgirish 150244961713Sgirish return (NULL); 150344961713Sgirish } 150444961713Sgirish 150544961713Sgirish /* 150644961713Sgirish * Static functions start here. 150744961713Sgirish */ 150844961713Sgirish static p_rx_msg_t 150944961713Sgirish nxge_allocb(size_t size, uint32_t pri, p_nxge_dma_common_t dmabuf_p) 151044961713Sgirish { 151144961713Sgirish p_rx_msg_t nxge_mp = NULL; 151244961713Sgirish p_nxge_dma_common_t dmamsg_p; 151344961713Sgirish uchar_t *buffer; 151444961713Sgirish 151544961713Sgirish nxge_mp = KMEM_ZALLOC(sizeof (rx_msg_t), KM_NOSLEEP); 151644961713Sgirish if (nxge_mp == NULL) { 151756d930aeSspeer NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 151852ccf843Smisaki "Allocation of a rx msg failed.")); 151944961713Sgirish goto nxge_allocb_exit; 152044961713Sgirish } 152144961713Sgirish 152244961713Sgirish nxge_mp->use_buf_pool = B_FALSE; 152344961713Sgirish if (dmabuf_p) { 152444961713Sgirish nxge_mp->use_buf_pool = B_TRUE; 152544961713Sgirish dmamsg_p = (p_nxge_dma_common_t)&nxge_mp->buf_dma; 152644961713Sgirish *dmamsg_p = *dmabuf_p; 152744961713Sgirish dmamsg_p->nblocks = 1; 152844961713Sgirish dmamsg_p->block_size = size; 152944961713Sgirish dmamsg_p->alength = size; 153044961713Sgirish buffer = (uchar_t *)dmabuf_p->kaddrp; 153144961713Sgirish 153244961713Sgirish dmabuf_p->kaddrp = (void *) 153352ccf843Smisaki ((char *)dmabuf_p->kaddrp + size); 153444961713Sgirish dmabuf_p->ioaddr_pp = (void *) 153552ccf843Smisaki ((char *)dmabuf_p->ioaddr_pp + size); 153644961713Sgirish dmabuf_p->alength -= size; 153744961713Sgirish dmabuf_p->offset += size; 153844961713Sgirish dmabuf_p->dma_cookie.dmac_laddress += size; 153944961713Sgirish dmabuf_p->dma_cookie.dmac_size -= size; 154044961713Sgirish 154144961713Sgirish } else { 154244961713Sgirish buffer = KMEM_ALLOC(size, KM_NOSLEEP); 154344961713Sgirish if (buffer == NULL) { 154456d930aeSspeer NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 154552ccf843Smisaki "Allocation of a receive page failed.")); 154644961713Sgirish goto nxge_allocb_fail1; 154744961713Sgirish } 154844961713Sgirish } 154944961713Sgirish 155044961713Sgirish nxge_mp->rx_mblk_p = desballoc(buffer, size, pri, &nxge_mp->freeb); 155144961713Sgirish if (nxge_mp->rx_mblk_p == NULL) { 155256d930aeSspeer NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, "desballoc failed.")); 155344961713Sgirish goto nxge_allocb_fail2; 155444961713Sgirish } 155544961713Sgirish 155644961713Sgirish nxge_mp->buffer = buffer; 155744961713Sgirish nxge_mp->block_size = size; 155844961713Sgirish nxge_mp->freeb.free_func = (void (*)())nxge_freeb; 155944961713Sgirish nxge_mp->freeb.free_arg = (caddr_t)nxge_mp; 156044961713Sgirish nxge_mp->ref_cnt = 1; 156144961713Sgirish nxge_mp->free = B_TRUE; 156244961713Sgirish nxge_mp->rx_use_bcopy = B_FALSE; 156344961713Sgirish 156414ea4bb7Ssd atomic_inc_32(&nxge_mblks_pending); 156544961713Sgirish 156644961713Sgirish goto nxge_allocb_exit; 156744961713Sgirish 156844961713Sgirish nxge_allocb_fail2: 156944961713Sgirish if (!nxge_mp->use_buf_pool) { 157044961713Sgirish KMEM_FREE(buffer, size); 157144961713Sgirish } 157244961713Sgirish 157344961713Sgirish nxge_allocb_fail1: 157444961713Sgirish KMEM_FREE(nxge_mp, sizeof (rx_msg_t)); 157544961713Sgirish nxge_mp = NULL; 157644961713Sgirish 157744961713Sgirish nxge_allocb_exit: 157844961713Sgirish return (nxge_mp); 157944961713Sgirish } 158044961713Sgirish 158144961713Sgirish p_mblk_t 158244961713Sgirish nxge_dupb(p_rx_msg_t nxge_mp, uint_t offset, size_t size) 158344961713Sgirish { 158444961713Sgirish p_mblk_t mp; 158544961713Sgirish 158644961713Sgirish NXGE_DEBUG_MSG((NULL, MEM_CTL, "==> nxge_dupb")); 158744961713Sgirish NXGE_DEBUG_MSG((NULL, MEM_CTL, "nxge_mp = $%p " 158852ccf843Smisaki "offset = 0x%08X " 158952ccf843Smisaki "size = 0x%08X", 159052ccf843Smisaki nxge_mp, offset, size)); 159144961713Sgirish 159244961713Sgirish mp = desballoc(&nxge_mp->buffer[offset], size, 159352ccf843Smisaki 0, &nxge_mp->freeb); 159444961713Sgirish if (mp == NULL) { 159544961713Sgirish NXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 159644961713Sgirish goto nxge_dupb_exit; 159744961713Sgirish } 159844961713Sgirish atomic_inc_32(&nxge_mp->ref_cnt); 159944961713Sgirish 160044961713Sgirish 160144961713Sgirish nxge_dupb_exit: 160244961713Sgirish NXGE_DEBUG_MSG((NULL, MEM_CTL, "<== nxge_dupb mp = $%p", 160352ccf843Smisaki nxge_mp)); 160444961713Sgirish return (mp); 160544961713Sgirish } 160644961713Sgirish 160744961713Sgirish p_mblk_t 160844961713Sgirish nxge_dupb_bcopy(p_rx_msg_t nxge_mp, uint_t offset, size_t size) 160944961713Sgirish { 161044961713Sgirish p_mblk_t mp; 161144961713Sgirish uchar_t *dp; 161244961713Sgirish 161344961713Sgirish mp = allocb(size + NXGE_RXBUF_EXTRA, 0); 161444961713Sgirish if (mp == NULL) { 161544961713Sgirish NXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 161644961713Sgirish goto nxge_dupb_bcopy_exit; 161744961713Sgirish } 161844961713Sgirish dp = mp->b_rptr = mp->b_rptr + NXGE_RXBUF_EXTRA; 161944961713Sgirish bcopy((void *)&nxge_mp->buffer[offset], dp, size); 162044961713Sgirish mp->b_wptr = dp + size; 162144961713Sgirish 162244961713Sgirish nxge_dupb_bcopy_exit: 162344961713Sgirish NXGE_DEBUG_MSG((NULL, MEM_CTL, "<== nxge_dupb mp = $%p", 162452ccf843Smisaki nxge_mp)); 162544961713Sgirish return (mp); 162644961713Sgirish } 162744961713Sgirish 162844961713Sgirish void nxge_post_page(p_nxge_t nxgep, p_rx_rbr_ring_t rx_rbr_p, 162944961713Sgirish p_rx_msg_t rx_msg_p); 163044961713Sgirish 163144961713Sgirish void 163244961713Sgirish nxge_post_page(p_nxge_t nxgep, p_rx_rbr_ring_t rx_rbr_p, p_rx_msg_t rx_msg_p) 163344961713Sgirish { 163444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_post_page")); 163544961713Sgirish 163644961713Sgirish /* Reuse this buffer */ 163744961713Sgirish rx_msg_p->free = B_FALSE; 163844961713Sgirish rx_msg_p->cur_usage_cnt = 0; 163944961713Sgirish rx_msg_p->max_usage_cnt = 0; 164044961713Sgirish rx_msg_p->pkt_buf_size = 0; 164144961713Sgirish 164244961713Sgirish if (rx_rbr_p->rbr_use_bcopy) { 164344961713Sgirish rx_msg_p->rx_use_bcopy = B_FALSE; 164444961713Sgirish atomic_dec_32(&rx_rbr_p->rbr_consumed); 164544961713Sgirish } 164644961713Sgirish 164744961713Sgirish /* 164844961713Sgirish * Get the rbr header pointer and its offset index. 164944961713Sgirish */ 165044961713Sgirish MUTEX_ENTER(&rx_rbr_p->post_lock); 165144961713Sgirish rx_rbr_p->rbr_wr_index = ((rx_rbr_p->rbr_wr_index + 1) & 165252ccf843Smisaki rx_rbr_p->rbr_wrap_mask); 165344961713Sgirish rx_rbr_p->rbr_desc_vp[rx_rbr_p->rbr_wr_index] = rx_msg_p->shifted_addr; 165444961713Sgirish MUTEX_EXIT(&rx_rbr_p->post_lock); 165530ac2e7bSml npi_rxdma_rdc_rbr_kick(NXGE_DEV_NPI_HANDLE(nxgep), 165630ac2e7bSml rx_rbr_p->rdc, 1); 165744961713Sgirish 165844961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 165952ccf843Smisaki "<== nxge_post_page (channel %d post_next_index %d)", 166052ccf843Smisaki rx_rbr_p->rdc, rx_rbr_p->rbr_wr_index)); 166144961713Sgirish 166244961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_post_page")); 166344961713Sgirish } 166444961713Sgirish 166544961713Sgirish void 166644961713Sgirish nxge_freeb(p_rx_msg_t rx_msg_p) 166744961713Sgirish { 166844961713Sgirish size_t size; 166944961713Sgirish uchar_t *buffer = NULL; 167044961713Sgirish int ref_cnt; 1671958cea9eSml boolean_t free_state = B_FALSE; 167244961713Sgirish 1673007969e0Stm rx_rbr_ring_t *ring = rx_msg_p->rx_rbr_p; 1674007969e0Stm 167544961713Sgirish NXGE_DEBUG_MSG((NULL, MEM2_CTL, "==> nxge_freeb")); 167644961713Sgirish NXGE_DEBUG_MSG((NULL, MEM2_CTL, 167752ccf843Smisaki "nxge_freeb:rx_msg_p = $%p (block pending %d)", 167852ccf843Smisaki rx_msg_p, nxge_mblks_pending)); 167944961713Sgirish 1680958cea9eSml /* 1681958cea9eSml * First we need to get the free state, then 1682958cea9eSml * atomic decrement the reference count to prevent 1683958cea9eSml * the race condition with the interrupt thread that 1684958cea9eSml * is processing a loaned up buffer block. 1685958cea9eSml */ 1686958cea9eSml free_state = rx_msg_p->free; 1687958cea9eSml ref_cnt = atomic_add_32_nv(&rx_msg_p->ref_cnt, -1); 168844961713Sgirish if (!ref_cnt) { 168930ac2e7bSml atomic_dec_32(&nxge_mblks_pending); 169044961713Sgirish buffer = rx_msg_p->buffer; 169144961713Sgirish size = rx_msg_p->block_size; 169244961713Sgirish NXGE_DEBUG_MSG((NULL, MEM2_CTL, "nxge_freeb: " 169352ccf843Smisaki "will free: rx_msg_p = $%p (block pending %d)", 169452ccf843Smisaki rx_msg_p, nxge_mblks_pending)); 169544961713Sgirish 169644961713Sgirish if (!rx_msg_p->use_buf_pool) { 169744961713Sgirish KMEM_FREE(buffer, size); 169844961713Sgirish } 169914ea4bb7Ssd 170014ea4bb7Ssd KMEM_FREE(rx_msg_p, sizeof (rx_msg_t)); 1701007969e0Stm 17023e82a89eSmisaki if (ring) { 17033e82a89eSmisaki /* 17043e82a89eSmisaki * Decrement the receive buffer ring's reference 17053e82a89eSmisaki * count, too. 17063e82a89eSmisaki */ 17073e82a89eSmisaki atomic_dec_32(&ring->rbr_ref_cnt); 1708007969e0Stm 17093e82a89eSmisaki /* 1710678453a8Sspeer * Free the receive buffer ring, if 17113e82a89eSmisaki * 1. all the receive buffers have been freed 17123e82a89eSmisaki * 2. and we are in the proper state (that is, 17133e82a89eSmisaki * we are not UNMAPPING). 17143e82a89eSmisaki */ 17153e82a89eSmisaki if (ring->rbr_ref_cnt == 0 && 17163e82a89eSmisaki ring->rbr_state == RBR_UNMAPPED) { 1717678453a8Sspeer /* 1718678453a8Sspeer * Free receive data buffers, 1719678453a8Sspeer * buffer index information 1720678453a8Sspeer * (rxring_info) and 1721678453a8Sspeer * the message block ring. 1722678453a8Sspeer */ 1723678453a8Sspeer NXGE_DEBUG_MSG((NULL, RX_CTL, 1724678453a8Sspeer "nxge_freeb:rx_msg_p = $%p " 1725678453a8Sspeer "(block pending %d) free buffers", 1726678453a8Sspeer rx_msg_p, nxge_mblks_pending)); 1727678453a8Sspeer nxge_rxdma_databuf_free(ring); 1728678453a8Sspeer if (ring->ring_info) { 1729678453a8Sspeer KMEM_FREE(ring->ring_info, 1730678453a8Sspeer sizeof (rxring_info_t)); 1731678453a8Sspeer } 1732678453a8Sspeer 1733678453a8Sspeer if (ring->rx_msg_ring) { 1734678453a8Sspeer KMEM_FREE(ring->rx_msg_ring, 1735678453a8Sspeer ring->tnblocks * 1736678453a8Sspeer sizeof (p_rx_msg_t)); 1737678453a8Sspeer } 17383e82a89eSmisaki KMEM_FREE(ring, sizeof (*ring)); 17393e82a89eSmisaki } 1740007969e0Stm } 174114ea4bb7Ssd return; 174244961713Sgirish } 174344961713Sgirish 174444961713Sgirish /* 174544961713Sgirish * Repost buffer. 174644961713Sgirish */ 17473e82a89eSmisaki if (free_state && (ref_cnt == 1) && ring) { 174844961713Sgirish NXGE_DEBUG_MSG((NULL, RX_CTL, 174944961713Sgirish "nxge_freeb: post page $%p:", rx_msg_p)); 1750007969e0Stm if (ring->rbr_state == RBR_POSTING) 1751007969e0Stm nxge_post_page(rx_msg_p->nxgep, ring, rx_msg_p); 175244961713Sgirish } 175344961713Sgirish 175444961713Sgirish NXGE_DEBUG_MSG((NULL, MEM2_CTL, "<== nxge_freeb")); 175544961713Sgirish } 175644961713Sgirish 175744961713Sgirish uint_t 175844961713Sgirish nxge_rx_intr(void *arg1, void *arg2) 175944961713Sgirish { 176044961713Sgirish p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 176144961713Sgirish p_nxge_t nxgep = (p_nxge_t)arg2; 176244961713Sgirish p_nxge_ldg_t ldgp; 176344961713Sgirish uint8_t channel; 176444961713Sgirish npi_handle_t handle; 176544961713Sgirish rx_dma_ctl_stat_t cs; 176663f531d1SSriharsha Basavapatna p_rx_rcr_ring_t rcrp; 176748056c53SMichael Speer mblk_t *mp = NULL; 176844961713Sgirish 176944961713Sgirish if (ldvp == NULL) { 177044961713Sgirish NXGE_DEBUG_MSG((NULL, INT_CTL, 177152ccf843Smisaki "<== nxge_rx_intr: arg2 $%p arg1 $%p", 177252ccf843Smisaki nxgep, ldvp)); 177344961713Sgirish return (DDI_INTR_CLAIMED); 177444961713Sgirish } 177544961713Sgirish 177644961713Sgirish if (arg2 == NULL || (void *)ldvp->nxgep != arg2) { 177744961713Sgirish nxgep = ldvp->nxgep; 177844961713Sgirish } 17791d36aa9eSspeer 17801d36aa9eSspeer if ((!(nxgep->drv_state & STATE_HW_INITIALIZED)) || 17811d36aa9eSspeer (nxgep->nxge_mac_state != NXGE_MAC_STARTED)) { 17821d36aa9eSspeer NXGE_DEBUG_MSG((nxgep, INT_CTL, 17831d36aa9eSspeer "<== nxge_rx_intr: interface not started or intialized")); 17841d36aa9eSspeer return (DDI_INTR_CLAIMED); 17851d36aa9eSspeer } 17861d36aa9eSspeer 178744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 178852ccf843Smisaki "==> nxge_rx_intr: arg2 $%p arg1 $%p", 178952ccf843Smisaki nxgep, ldvp)); 179044961713Sgirish 179144961713Sgirish /* 1792e759c33aSMichael Speer * Get the PIO handle. 179344961713Sgirish */ 179444961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 1795da14cebeSEric Cheng 1796e759c33aSMichael Speer /* 1797e759c33aSMichael Speer * Get the ring to enable us to process packets. 1798e759c33aSMichael Speer */ 179963f531d1SSriharsha Basavapatna rcrp = nxgep->rx_rcr_rings->rcr_rings[ldvp->vdma_index]; 1800da14cebeSEric Cheng 1801da14cebeSEric Cheng /* 1802da14cebeSEric Cheng * The RCR ring lock must be held when packets 1803da14cebeSEric Cheng * are being processed and the hardware registers are 1804da14cebeSEric Cheng * being read or written to prevent race condition 1805da14cebeSEric Cheng * among the interrupt thread, the polling thread 1806da14cebeSEric Cheng * (will cause fatal errors such as rcrincon bit set) 1807da14cebeSEric Cheng * and the setting of the poll_flag. 1808da14cebeSEric Cheng */ 180963f531d1SSriharsha Basavapatna MUTEX_ENTER(&rcrp->lock); 1810da14cebeSEric Cheng 181144961713Sgirish /* 181244961713Sgirish * Get the control and status for this channel. 181344961713Sgirish */ 181444961713Sgirish channel = ldvp->channel; 181544961713Sgirish ldgp = ldvp->ldgp; 1816da14cebeSEric Cheng 1817e759c33aSMichael Speer if (!isLDOMguest(nxgep) && (!nxgep->rx_channel_started[channel])) { 1818e759c33aSMichael Speer NXGE_DEBUG_MSG((nxgep, INT_CTL, 1819e759c33aSMichael Speer "<== nxge_rx_intr: channel is not started")); 1820e759c33aSMichael Speer 1821e759c33aSMichael Speer /* 1822e759c33aSMichael Speer * We received an interrupt before the ring is started. 1823e759c33aSMichael Speer */ 1824e759c33aSMichael Speer RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel, 1825e759c33aSMichael Speer &cs.value); 1826e759c33aSMichael Speer cs.value &= RX_DMA_CTL_STAT_WR1C; 1827e759c33aSMichael Speer cs.bits.hdw.mex = 1; 1828e759c33aSMichael Speer RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel, 1829e759c33aSMichael Speer cs.value); 1830e759c33aSMichael Speer 1831e759c33aSMichael Speer /* 1832e759c33aSMichael Speer * Rearm this logical group if this is a single device 1833e759c33aSMichael Speer * group. 1834e759c33aSMichael Speer */ 1835e759c33aSMichael Speer if (ldgp->nldvs == 1) { 1836e759c33aSMichael Speer if (isLDOMguest(nxgep)) { 1837e759c33aSMichael Speer nxge_hio_ldgimgn(nxgep, ldgp); 1838e759c33aSMichael Speer } else { 1839e759c33aSMichael Speer ldgimgm_t mgm; 1840e759c33aSMichael Speer 1841e759c33aSMichael Speer mgm.value = 0; 1842e759c33aSMichael Speer mgm.bits.ldw.arm = 1; 1843e759c33aSMichael Speer mgm.bits.ldw.timer = ldgp->ldg_timer; 1844e759c33aSMichael Speer 1845e759c33aSMichael Speer NXGE_REG_WR64(handle, 1846e759c33aSMichael Speer LDGIMGN_REG + LDSV_OFFSET(ldgp->ldg), 1847e759c33aSMichael Speer mgm.value); 1848e759c33aSMichael Speer } 1849da14cebeSEric Cheng } 185063f531d1SSriharsha Basavapatna MUTEX_EXIT(&rcrp->lock); 1851e759c33aSMichael Speer return (DDI_INTR_CLAIMED); 1852da14cebeSEric Cheng } 1853da14cebeSEric Cheng 185463f531d1SSriharsha Basavapatna ASSERT(rcrp->ldgp == ldgp); 185563f531d1SSriharsha Basavapatna ASSERT(rcrp->ldvp == ldvp); 1856da14cebeSEric Cheng 185744961713Sgirish RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel, &cs.value); 185844961713Sgirish 185944961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_intr:channel %d " 186052ccf843Smisaki "cs 0x%016llx rcrto 0x%x rcrthres %x", 186152ccf843Smisaki channel, 186252ccf843Smisaki cs.value, 186352ccf843Smisaki cs.bits.hdw.rcrto, 186452ccf843Smisaki cs.bits.hdw.rcrthres)); 186544961713Sgirish 186663f531d1SSriharsha Basavapatna if (!rcrp->poll_flag) { 186763f531d1SSriharsha Basavapatna mp = nxge_rx_pkts(nxgep, rcrp, cs, -1); 186848056c53SMichael Speer } 186944961713Sgirish 187044961713Sgirish /* error events. */ 187144961713Sgirish if (cs.value & RX_DMA_CTL_STAT_ERROR) { 1872678453a8Sspeer (void) nxge_rx_err_evnts(nxgep, channel, cs); 187344961713Sgirish } 187444961713Sgirish 187544961713Sgirish /* 187644961713Sgirish * Enable the mailbox update interrupt if we want 187744961713Sgirish * to use mailbox. We probably don't need to use 187844961713Sgirish * mailbox as it only saves us one pio read. 187944961713Sgirish * Also write 1 to rcrthres and rcrto to clear 188044961713Sgirish * these two edge triggered bits. 188144961713Sgirish */ 188244961713Sgirish cs.value &= RX_DMA_CTL_STAT_WR1C; 188363f531d1SSriharsha Basavapatna cs.bits.hdw.mex = rcrp->poll_flag ? 0 : 1; 188444961713Sgirish RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel, 188552ccf843Smisaki cs.value); 188644961713Sgirish 188744961713Sgirish /* 1888da14cebeSEric Cheng * If the polling mode is enabled, disable the interrupt. 188944961713Sgirish */ 189063f531d1SSriharsha Basavapatna if (rcrp->poll_flag) { 1891da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 1892da14cebeSEric Cheng "==> nxge_rx_intr: rdc %d ldgp $%p ldvp $%p " 1893da14cebeSEric Cheng "(disabling interrupts)", channel, ldgp, ldvp)); 189463f531d1SSriharsha Basavapatna 1895da14cebeSEric Cheng /* 1896da14cebeSEric Cheng * Disarm this logical group if this is a single device 1897da14cebeSEric Cheng * group. 1898da14cebeSEric Cheng */ 1899da14cebeSEric Cheng if (ldgp->nldvs == 1) { 190063f531d1SSriharsha Basavapatna if (isLDOMguest(nxgep)) { 190163f531d1SSriharsha Basavapatna ldgp->arm = B_FALSE; 190263f531d1SSriharsha Basavapatna nxge_hio_ldgimgn(nxgep, ldgp); 190363f531d1SSriharsha Basavapatna } else { 190463f531d1SSriharsha Basavapatna ldgimgm_t mgm; 190563f531d1SSriharsha Basavapatna mgm.value = 0; 190663f531d1SSriharsha Basavapatna mgm.bits.ldw.arm = 0; 190763f531d1SSriharsha Basavapatna NXGE_REG_WR64(handle, 190863f531d1SSriharsha Basavapatna LDGIMGN_REG + LDSV_OFFSET(ldgp->ldg), 190963f531d1SSriharsha Basavapatna mgm.value); 191063f531d1SSriharsha Basavapatna } 1911da14cebeSEric Cheng } 1912da14cebeSEric Cheng } else { 1913da14cebeSEric Cheng /* 191408ac1c49SNicolas Droux * Rearm this logical group if this is a single device 191508ac1c49SNicolas Droux * group. 1916da14cebeSEric Cheng */ 1917da14cebeSEric Cheng if (ldgp->nldvs == 1) { 1918da14cebeSEric Cheng if (isLDOMguest(nxgep)) { 1919da14cebeSEric Cheng nxge_hio_ldgimgn(nxgep, ldgp); 1920da14cebeSEric Cheng } else { 1921da14cebeSEric Cheng ldgimgm_t mgm; 1922da14cebeSEric Cheng 1923da14cebeSEric Cheng mgm.value = 0; 1924da14cebeSEric Cheng mgm.bits.ldw.arm = 1; 1925da14cebeSEric Cheng mgm.bits.ldw.timer = ldgp->ldg_timer; 1926da14cebeSEric Cheng 1927da14cebeSEric Cheng NXGE_REG_WR64(handle, 1928da14cebeSEric Cheng LDGIMGN_REG + LDSV_OFFSET(ldgp->ldg), 1929da14cebeSEric Cheng mgm.value); 1930da14cebeSEric Cheng } 1931678453a8Sspeer } 1932da14cebeSEric Cheng 1933da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 1934da14cebeSEric Cheng "==> nxge_rx_intr: rdc %d ldgp $%p " 1935da14cebeSEric Cheng "exiting ISR (and call mac_rx_ring)", channel, ldgp)); 193644961713Sgirish } 193763f531d1SSriharsha Basavapatna MUTEX_EXIT(&rcrp->lock); 193844961713Sgirish 193948056c53SMichael Speer if (mp != NULL) { 194063f531d1SSriharsha Basavapatna mac_rx_ring(nxgep->mach, rcrp->rcr_mac_handle, mp, 194163f531d1SSriharsha Basavapatna rcrp->rcr_gen_num); 1942da14cebeSEric Cheng } 1943da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_intr: DDI_INTR_CLAIMED")); 1944da14cebeSEric Cheng return (DDI_INTR_CLAIMED); 194544961713Sgirish } 194644961713Sgirish 194744961713Sgirish /* 194844961713Sgirish * This routine is the main packet receive processing function. 194944961713Sgirish * It gets the packet type, error code, and buffer related 195044961713Sgirish * information from the receive completion entry. 195144961713Sgirish * How many completion entries to process is based on the number of packets 195244961713Sgirish * queued by the hardware, a hardware maintained tail pointer 195344961713Sgirish * and a configurable receive packet count. 195444961713Sgirish * 195544961713Sgirish * A chain of message blocks will be created as result of processing 195644961713Sgirish * the completion entries. This chain of message blocks will be returned and 195744961713Sgirish * a hardware control status register will be updated with the number of 195844961713Sgirish * packets were removed from the hardware queue. 195944961713Sgirish * 1960da14cebeSEric Cheng * The RCR ring lock is held when entering this function. 196144961713Sgirish */ 1962678453a8Sspeer static mblk_t * 1963678453a8Sspeer nxge_rx_pkts(p_nxge_t nxgep, p_rx_rcr_ring_t rcr_p, rx_dma_ctl_stat_t cs, 1964678453a8Sspeer int bytes_to_pickup) 196544961713Sgirish { 196644961713Sgirish npi_handle_t handle; 196744961713Sgirish uint8_t channel; 196844961713Sgirish uint32_t comp_rd_index; 196944961713Sgirish p_rcr_entry_t rcr_desc_rd_head_p; 197044961713Sgirish p_rcr_entry_t rcr_desc_rd_head_pp; 197144961713Sgirish p_mblk_t nmp, mp_cont, head_mp, *tail_mp; 197244961713Sgirish uint16_t qlen, nrcr_read, npkt_read; 1973678453a8Sspeer uint32_t qlen_hw; 197444961713Sgirish boolean_t multi; 1975678453a8Sspeer rcrcfig_b_t rcr_cfg_b; 1976678453a8Sspeer int totallen = 0; 1977a3c5bd6dSspeer #if defined(_BIG_ENDIAN) 197844961713Sgirish npi_status_t rs = NPI_SUCCESS; 197944961713Sgirish #endif 198044961713Sgirish 1981da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_rx_pkts: " 198252ccf843Smisaki "channel %d", rcr_p->rdc)); 198344961713Sgirish 198444961713Sgirish if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 198544961713Sgirish return (NULL); 198644961713Sgirish } 198744961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 198844961713Sgirish channel = rcr_p->rdc; 198944961713Sgirish 199044961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 199152ccf843Smisaki "==> nxge_rx_pkts: START: rcr channel %d " 199252ccf843Smisaki "head_p $%p head_pp $%p index %d ", 199352ccf843Smisaki channel, rcr_p->rcr_desc_rd_head_p, 199452ccf843Smisaki rcr_p->rcr_desc_rd_head_pp, 199552ccf843Smisaki rcr_p->comp_rd_index)); 199644961713Sgirish 199744961713Sgirish 1998a3c5bd6dSspeer #if !defined(_BIG_ENDIAN) 199944961713Sgirish qlen = RXDMA_REG_READ32(handle, RCRSTAT_A_REG, channel) & 0xffff; 200044961713Sgirish #else 200144961713Sgirish rs = npi_rxdma_rdc_rcr_qlen_get(handle, channel, &qlen); 200244961713Sgirish if (rs != NPI_SUCCESS) { 2003678453a8Sspeer NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts: " 200444961713Sgirish "channel %d, get qlen failed 0x%08x", 200552ccf843Smisaki channel, rs)); 200644961713Sgirish return (NULL); 200744961713Sgirish } 200844961713Sgirish #endif 200944961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts:rcr channel %d " 201052ccf843Smisaki "qlen %d", channel, qlen)); 201144961713Sgirish 201244961713Sgirish 201344961713Sgirish 201444961713Sgirish if (!qlen) { 2015da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 201652ccf843Smisaki "==> nxge_rx_pkts:rcr channel %d " 201752ccf843Smisaki "qlen %d (no pkts)", channel, qlen)); 201844961713Sgirish 201944961713Sgirish return (NULL); 202044961713Sgirish } 202144961713Sgirish 202244961713Sgirish comp_rd_index = rcr_p->comp_rd_index; 202344961713Sgirish 202444961713Sgirish rcr_desc_rd_head_p = rcr_p->rcr_desc_rd_head_p; 202544961713Sgirish rcr_desc_rd_head_pp = rcr_p->rcr_desc_rd_head_pp; 202644961713Sgirish nrcr_read = npkt_read = 0; 202744961713Sgirish 202844961713Sgirish /* 202944961713Sgirish * Number of packets queued 203044961713Sgirish * (The jumbo or multi packet will be counted as only one 203144961713Sgirish * packets and it may take up more than one completion entry). 203244961713Sgirish */ 203344961713Sgirish qlen_hw = (qlen < nxge_max_rx_pkts) ? 203452ccf843Smisaki qlen : nxge_max_rx_pkts; 203544961713Sgirish head_mp = NULL; 203644961713Sgirish tail_mp = &head_mp; 203744961713Sgirish nmp = mp_cont = NULL; 203844961713Sgirish multi = B_FALSE; 203944961713Sgirish 2040a3c5bd6dSspeer while (qlen_hw) { 204144961713Sgirish 204244961713Sgirish #ifdef NXGE_DEBUG 204344961713Sgirish nxge_dump_rcr_entry(nxgep, rcr_desc_rd_head_p); 204444961713Sgirish #endif 204544961713Sgirish /* 204644961713Sgirish * Process one completion ring entry. 204744961713Sgirish */ 204844961713Sgirish nxge_receive_packet(nxgep, 204952ccf843Smisaki rcr_p, rcr_desc_rd_head_p, &multi, &nmp, &mp_cont); 205044961713Sgirish 205144961713Sgirish /* 205244961713Sgirish * message chaining modes 205344961713Sgirish */ 205414ea4bb7Ssd if (nmp) { 205544961713Sgirish nmp->b_next = NULL; 205614ea4bb7Ssd if (!multi && !mp_cont) { /* frame fits a partition */ 205714ea4bb7Ssd *tail_mp = nmp; 205814ea4bb7Ssd tail_mp = &nmp->b_next; 2059678453a8Sspeer totallen += MBLKL(nmp); 206014ea4bb7Ssd nmp = NULL; 206114ea4bb7Ssd } else if (multi && !mp_cont) { /* first segment */ 206214ea4bb7Ssd *tail_mp = nmp; 206314ea4bb7Ssd tail_mp = &nmp->b_cont; 2064678453a8Sspeer totallen += MBLKL(nmp); 206514ea4bb7Ssd } else if (multi && mp_cont) { /* mid of multi segs */ 206614ea4bb7Ssd *tail_mp = mp_cont; 206714ea4bb7Ssd tail_mp = &mp_cont->b_cont; 2068678453a8Sspeer totallen += MBLKL(mp_cont); 206914ea4bb7Ssd } else if (!multi && mp_cont) { /* last segment */ 2070a3c5bd6dSspeer *tail_mp = mp_cont; 207114ea4bb7Ssd tail_mp = &nmp->b_next; 2072678453a8Sspeer totallen += MBLKL(mp_cont); 207314ea4bb7Ssd nmp = NULL; 207414ea4bb7Ssd } 207544961713Sgirish } 207644961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 207752ccf843Smisaki "==> nxge_rx_pkts: loop: rcr channel %d " 207852ccf843Smisaki "before updating: multi %d " 207952ccf843Smisaki "nrcr_read %d " 208052ccf843Smisaki "npk read %d " 208152ccf843Smisaki "head_pp $%p index %d ", 208252ccf843Smisaki channel, 208352ccf843Smisaki multi, 208452ccf843Smisaki nrcr_read, npkt_read, rcr_desc_rd_head_pp, 208552ccf843Smisaki comp_rd_index)); 208644961713Sgirish 208744961713Sgirish if (!multi) { 208844961713Sgirish qlen_hw--; 208944961713Sgirish npkt_read++; 209044961713Sgirish } 209144961713Sgirish 209244961713Sgirish /* 209344961713Sgirish * Update the next read entry. 209444961713Sgirish */ 209544961713Sgirish comp_rd_index = NEXT_ENTRY(comp_rd_index, 209652ccf843Smisaki rcr_p->comp_wrap_mask); 209744961713Sgirish 209844961713Sgirish rcr_desc_rd_head_p = NEXT_ENTRY_PTR(rcr_desc_rd_head_p, 209952ccf843Smisaki rcr_p->rcr_desc_first_p, 210052ccf843Smisaki rcr_p->rcr_desc_last_p); 210144961713Sgirish 210244961713Sgirish nrcr_read++; 210344961713Sgirish 210444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 210552ccf843Smisaki "<== nxge_rx_pkts: (SAM, process one packet) " 210652ccf843Smisaki "nrcr_read %d", 210752ccf843Smisaki nrcr_read)); 210844961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 210952ccf843Smisaki "==> nxge_rx_pkts: loop: rcr channel %d " 211052ccf843Smisaki "multi %d " 211152ccf843Smisaki "nrcr_read %d " 211252ccf843Smisaki "npk read %d " 211352ccf843Smisaki "head_pp $%p index %d ", 211452ccf843Smisaki channel, 211552ccf843Smisaki multi, 211652ccf843Smisaki nrcr_read, npkt_read, rcr_desc_rd_head_pp, 211752ccf843Smisaki comp_rd_index)); 211844961713Sgirish 2119678453a8Sspeer if ((bytes_to_pickup != -1) && 2120678453a8Sspeer (totallen >= bytes_to_pickup)) { 2121678453a8Sspeer break; 2122678453a8Sspeer } 212344961713Sgirish } 212444961713Sgirish 212544961713Sgirish rcr_p->rcr_desc_rd_head_pp = rcr_desc_rd_head_pp; 212644961713Sgirish rcr_p->comp_rd_index = comp_rd_index; 212744961713Sgirish rcr_p->rcr_desc_rd_head_p = rcr_desc_rd_head_p; 212814ea4bb7Ssd if ((nxgep->intr_timeout != rcr_p->intr_timeout) || 212952ccf843Smisaki (nxgep->intr_threshold != rcr_p->intr_threshold)) { 21307b26d9ffSSantwona Behera 21317b26d9ffSSantwona Behera rcr_p->intr_timeout = (nxgep->intr_timeout < 21327b26d9ffSSantwona Behera NXGE_RDC_RCR_TIMEOUT_MIN) ? NXGE_RDC_RCR_TIMEOUT_MIN : 21337b26d9ffSSantwona Behera nxgep->intr_timeout; 21347b26d9ffSSantwona Behera 21357b26d9ffSSantwona Behera rcr_p->intr_threshold = (nxgep->intr_threshold < 21367b26d9ffSSantwona Behera NXGE_RDC_RCR_THRESHOLD_MIN) ? NXGE_RDC_RCR_THRESHOLD_MIN : 21377b26d9ffSSantwona Behera nxgep->intr_threshold; 21387b26d9ffSSantwona Behera 213914ea4bb7Ssd rcr_cfg_b.value = 0x0ULL; 21407b26d9ffSSantwona Behera rcr_cfg_b.bits.ldw.entout = 1; 214114ea4bb7Ssd rcr_cfg_b.bits.ldw.timeout = rcr_p->intr_timeout; 214214ea4bb7Ssd rcr_cfg_b.bits.ldw.pthres = rcr_p->intr_threshold; 21437b26d9ffSSantwona Behera 214414ea4bb7Ssd RXDMA_REG_WRITE64(handle, RCRCFIG_B_REG, 214552ccf843Smisaki channel, rcr_cfg_b.value); 214614ea4bb7Ssd } 214744961713Sgirish 214844961713Sgirish cs.bits.ldw.pktread = npkt_read; 214944961713Sgirish cs.bits.ldw.ptrread = nrcr_read; 215044961713Sgirish RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, 215152ccf843Smisaki channel, cs.value); 215244961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 215352ccf843Smisaki "==> nxge_rx_pkts: EXIT: rcr channel %d " 215452ccf843Smisaki "head_pp $%p index %016llx ", 215552ccf843Smisaki channel, 215652ccf843Smisaki rcr_p->rcr_desc_rd_head_pp, 215752ccf843Smisaki rcr_p->comp_rd_index)); 215844961713Sgirish /* 215944961713Sgirish * Update RCR buffer pointer read and number of packets 216044961713Sgirish * read. 216144961713Sgirish */ 216244961713Sgirish 2163da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_rx_pkts: return" 2164da14cebeSEric Cheng "channel %d", rcr_p->rdc)); 2165da14cebeSEric Cheng 216644961713Sgirish return (head_mp); 216744961713Sgirish } 216844961713Sgirish 216944961713Sgirish void 217044961713Sgirish nxge_receive_packet(p_nxge_t nxgep, 217144961713Sgirish p_rx_rcr_ring_t rcr_p, p_rcr_entry_t rcr_desc_rd_head_p, 217244961713Sgirish boolean_t *multi_p, mblk_t **mp, mblk_t **mp_cont) 217344961713Sgirish { 217444961713Sgirish p_mblk_t nmp = NULL; 217544961713Sgirish uint64_t multi; 217644961713Sgirish uint64_t dcf_err; 217744961713Sgirish uint8_t channel; 217844961713Sgirish 217944961713Sgirish boolean_t first_entry = B_TRUE; 218044961713Sgirish boolean_t is_tcp_udp = B_FALSE; 218144961713Sgirish boolean_t buffer_free = B_FALSE; 218244961713Sgirish boolean_t error_send_up = B_FALSE; 218344961713Sgirish uint8_t error_type; 218444961713Sgirish uint16_t l2_len; 218544961713Sgirish uint16_t skip_len; 218644961713Sgirish uint8_t pktbufsz_type; 218744961713Sgirish uint64_t rcr_entry; 218844961713Sgirish uint64_t *pkt_buf_addr_pp; 218944961713Sgirish uint64_t *pkt_buf_addr_p; 219044961713Sgirish uint32_t buf_offset; 219144961713Sgirish uint32_t bsize; 219244961713Sgirish uint32_t error_disp_cnt; 219344961713Sgirish uint32_t msg_index; 219444961713Sgirish p_rx_rbr_ring_t rx_rbr_p; 219544961713Sgirish p_rx_msg_t *rx_msg_ring_p; 219644961713Sgirish p_rx_msg_t rx_msg_p; 219744961713Sgirish uint16_t sw_offset_bytes = 0, hdr_size = 0; 219844961713Sgirish nxge_status_t status = NXGE_OK; 219944961713Sgirish boolean_t is_valid = B_FALSE; 220044961713Sgirish p_nxge_rx_ring_stats_t rdc_stats; 2201a3c5bd6dSspeer uint32_t bytes_read; 2202a3c5bd6dSspeer uint64_t pkt_type; 2203a3c5bd6dSspeer uint64_t frag; 22044202ea4bSsbehera boolean_t pkt_too_long_err = B_FALSE; 220544961713Sgirish #ifdef NXGE_DEBUG 220644961713Sgirish int dump_len; 220744961713Sgirish #endif 220844961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> nxge_receive_packet")); 220944961713Sgirish first_entry = (*mp == NULL) ? B_TRUE : B_FALSE; 221044961713Sgirish 221144961713Sgirish rcr_entry = *((uint64_t *)rcr_desc_rd_head_p); 221244961713Sgirish 221344961713Sgirish multi = (rcr_entry & RCR_MULTI_MASK); 221444961713Sgirish dcf_err = (rcr_entry & RCR_DCF_ERROR_MASK); 221544961713Sgirish pkt_type = (rcr_entry & RCR_PKT_TYPE_MASK); 221644961713Sgirish 221744961713Sgirish error_type = ((rcr_entry & RCR_ERROR_MASK) >> RCR_ERROR_SHIFT); 221844961713Sgirish frag = (rcr_entry & RCR_FRAG_MASK); 221944961713Sgirish 222044961713Sgirish l2_len = ((rcr_entry & RCR_L2_LEN_MASK) >> RCR_L2_LEN_SHIFT); 222144961713Sgirish 222244961713Sgirish pktbufsz_type = ((rcr_entry & RCR_PKTBUFSZ_MASK) >> 222352ccf843Smisaki RCR_PKTBUFSZ_SHIFT); 2224adfcba55Sjoycey #if defined(__i386) 2225adfcba55Sjoycey pkt_buf_addr_pp = (uint64_t *)(uint32_t)((rcr_entry & 222652ccf843Smisaki RCR_PKT_BUF_ADDR_MASK) << RCR_PKT_BUF_ADDR_SHIFT); 2227adfcba55Sjoycey #else 222844961713Sgirish pkt_buf_addr_pp = (uint64_t *)((rcr_entry & RCR_PKT_BUF_ADDR_MASK) << 222952ccf843Smisaki RCR_PKT_BUF_ADDR_SHIFT); 2230adfcba55Sjoycey #endif 223144961713Sgirish 223244961713Sgirish channel = rcr_p->rdc; 223344961713Sgirish 223444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 223552ccf843Smisaki "==> nxge_receive_packet: entryp $%p entry 0x%0llx " 223652ccf843Smisaki "pkt_buf_addr_pp $%p l2_len %d multi 0x%llx " 223752ccf843Smisaki "error_type 0x%x pkt_type 0x%x " 223852ccf843Smisaki "pktbufsz_type %d ", 223952ccf843Smisaki rcr_desc_rd_head_p, 224052ccf843Smisaki rcr_entry, pkt_buf_addr_pp, l2_len, 224152ccf843Smisaki multi, 224252ccf843Smisaki error_type, 224352ccf843Smisaki pkt_type, 224452ccf843Smisaki pktbufsz_type)); 224544961713Sgirish 224644961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 224752ccf843Smisaki "==> nxge_receive_packet: entryp $%p entry 0x%0llx " 224852ccf843Smisaki "pkt_buf_addr_pp $%p l2_len %d multi 0x%llx " 224952ccf843Smisaki "error_type 0x%x pkt_type 0x%x ", rcr_desc_rd_head_p, 225052ccf843Smisaki rcr_entry, pkt_buf_addr_pp, l2_len, 225152ccf843Smisaki multi, 225252ccf843Smisaki error_type, 225352ccf843Smisaki pkt_type)); 225444961713Sgirish 225544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 225652ccf843Smisaki "==> (rbr) nxge_receive_packet: entry 0x%0llx " 225752ccf843Smisaki "full pkt_buf_addr_pp $%p l2_len %d", 225852ccf843Smisaki rcr_entry, pkt_buf_addr_pp, l2_len)); 225944961713Sgirish 226044961713Sgirish /* get the stats ptr */ 226144961713Sgirish rdc_stats = rcr_p->rdc_stats; 226244961713Sgirish 226344961713Sgirish if (!l2_len) { 226444961713Sgirish 226544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 226652ccf843Smisaki "<== nxge_receive_packet: failed: l2 length is 0.")); 226744961713Sgirish return; 226844961713Sgirish } 226944961713Sgirish 22704202ea4bSsbehera /* 2271da14cebeSEric Cheng * Software workaround for BMAC hardware limitation that allows 22724202ea4bSsbehera * maxframe size of 1526, instead of 1522 for non-jumbo and 0x2406 22734202ea4bSsbehera * instead of 0x2400 for jumbo. 22744202ea4bSsbehera */ 22754202ea4bSsbehera if (l2_len > nxgep->mac.maxframesize) { 22764202ea4bSsbehera pkt_too_long_err = B_TRUE; 22774202ea4bSsbehera } 22784202ea4bSsbehera 227956d930aeSspeer /* Hardware sends us 4 bytes of CRC as no stripping is done. */ 228056d930aeSspeer l2_len -= ETHERFCSL; 228156d930aeSspeer 228244961713Sgirish /* shift 6 bits to get the full io address */ 2283adfcba55Sjoycey #if defined(__i386) 2284adfcba55Sjoycey pkt_buf_addr_pp = (uint64_t *)((uint32_t)pkt_buf_addr_pp << 228552ccf843Smisaki RCR_PKT_BUF_ADDR_SHIFT_FULL); 2286adfcba55Sjoycey #else 228744961713Sgirish pkt_buf_addr_pp = (uint64_t *)((uint64_t)pkt_buf_addr_pp << 228852ccf843Smisaki RCR_PKT_BUF_ADDR_SHIFT_FULL); 2289adfcba55Sjoycey #endif 229044961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 229152ccf843Smisaki "==> (rbr) nxge_receive_packet: entry 0x%0llx " 229252ccf843Smisaki "full pkt_buf_addr_pp $%p l2_len %d", 229352ccf843Smisaki rcr_entry, pkt_buf_addr_pp, l2_len)); 229444961713Sgirish 229544961713Sgirish rx_rbr_p = rcr_p->rx_rbr_p; 229644961713Sgirish rx_msg_ring_p = rx_rbr_p->rx_msg_ring; 229744961713Sgirish 229844961713Sgirish if (first_entry) { 229944961713Sgirish hdr_size = (rcr_p->full_hdr_flag ? RXDMA_HDR_SIZE_FULL : 230052ccf843Smisaki RXDMA_HDR_SIZE_DEFAULT); 230144961713Sgirish 230244961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 230352ccf843Smisaki "==> nxge_receive_packet: first entry 0x%016llx " 230452ccf843Smisaki "pkt_buf_addr_pp $%p l2_len %d hdr %d", 230552ccf843Smisaki rcr_entry, pkt_buf_addr_pp, l2_len, 230652ccf843Smisaki hdr_size)); 230744961713Sgirish } 230844961713Sgirish 230944961713Sgirish MUTEX_ENTER(&rx_rbr_p->lock); 231044961713Sgirish 231144961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 231252ccf843Smisaki "==> (rbr 1) nxge_receive_packet: entry 0x%0llx " 231352ccf843Smisaki "full pkt_buf_addr_pp $%p l2_len %d", 231452ccf843Smisaki rcr_entry, pkt_buf_addr_pp, l2_len)); 231544961713Sgirish 231644961713Sgirish /* 231744961713Sgirish * Packet buffer address in the completion entry points 231844961713Sgirish * to the starting buffer address (offset 0). 231944961713Sgirish * Use the starting buffer address to locate the corresponding 232044961713Sgirish * kernel address. 232144961713Sgirish */ 232244961713Sgirish status = nxge_rxbuf_pp_to_vp(nxgep, rx_rbr_p, 232352ccf843Smisaki pktbufsz_type, pkt_buf_addr_pp, &pkt_buf_addr_p, 232452ccf843Smisaki &buf_offset, 232552ccf843Smisaki &msg_index); 232644961713Sgirish 232744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 232852ccf843Smisaki "==> (rbr 2) nxge_receive_packet: entry 0x%0llx " 232952ccf843Smisaki "full pkt_buf_addr_pp $%p l2_len %d", 233052ccf843Smisaki rcr_entry, pkt_buf_addr_pp, l2_len)); 233144961713Sgirish 233244961713Sgirish if (status != NXGE_OK) { 233344961713Sgirish MUTEX_EXIT(&rx_rbr_p->lock); 233444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 233552ccf843Smisaki "<== nxge_receive_packet: found vaddr failed %d", 233652ccf843Smisaki status)); 233744961713Sgirish return; 233844961713Sgirish } 233944961713Sgirish 234044961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 234152ccf843Smisaki "==> (rbr 3) nxge_receive_packet: entry 0x%0llx " 234252ccf843Smisaki "full pkt_buf_addr_pp $%p l2_len %d", 234352ccf843Smisaki rcr_entry, pkt_buf_addr_pp, l2_len)); 234444961713Sgirish 234544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 234652ccf843Smisaki "==> (rbr 4 msgindex %d) nxge_receive_packet: entry 0x%0llx " 234752ccf843Smisaki "full pkt_buf_addr_pp $%p l2_len %d", 234852ccf843Smisaki msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 234944961713Sgirish 235044961713Sgirish rx_msg_p = rx_msg_ring_p[msg_index]; 235144961713Sgirish 235244961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 235352ccf843Smisaki "==> (rbr 4 msgindex %d) nxge_receive_packet: entry 0x%0llx " 235452ccf843Smisaki "full pkt_buf_addr_pp $%p l2_len %d", 235552ccf843Smisaki msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 235644961713Sgirish 235744961713Sgirish switch (pktbufsz_type) { 235844961713Sgirish case RCR_PKTBUFSZ_0: 235944961713Sgirish bsize = rx_rbr_p->pkt_buf_size0_bytes; 236044961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 236152ccf843Smisaki "==> nxge_receive_packet: 0 buf %d", bsize)); 236244961713Sgirish break; 236344961713Sgirish case RCR_PKTBUFSZ_1: 236444961713Sgirish bsize = rx_rbr_p->pkt_buf_size1_bytes; 236544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 236652ccf843Smisaki "==> nxge_receive_packet: 1 buf %d", bsize)); 236744961713Sgirish break; 236844961713Sgirish case RCR_PKTBUFSZ_2: 236944961713Sgirish bsize = rx_rbr_p->pkt_buf_size2_bytes; 237044961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 237152ccf843Smisaki "==> nxge_receive_packet: 2 buf %d", bsize)); 237244961713Sgirish break; 237344961713Sgirish case RCR_SINGLE_BLOCK: 237444961713Sgirish bsize = rx_msg_p->block_size; 237544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 237652ccf843Smisaki "==> nxge_receive_packet: single %d", bsize)); 237744961713Sgirish 237844961713Sgirish break; 237944961713Sgirish default: 238044961713Sgirish MUTEX_EXIT(&rx_rbr_p->lock); 238144961713Sgirish return; 238244961713Sgirish } 238344961713Sgirish 2384*4df55fdeSJanie Lu switch (nxge_rdc_buf_offset) { 2385*4df55fdeSJanie Lu case SW_OFFSET_NO_OFFSET: 2386*4df55fdeSJanie Lu sw_offset_bytes = 0; 2387*4df55fdeSJanie Lu break; 2388*4df55fdeSJanie Lu case SW_OFFSET_64: 2389*4df55fdeSJanie Lu sw_offset_bytes = 64; 2390*4df55fdeSJanie Lu break; 2391*4df55fdeSJanie Lu case SW_OFFSET_128: 2392*4df55fdeSJanie Lu sw_offset_bytes = 128; 2393*4df55fdeSJanie Lu break; 2394*4df55fdeSJanie Lu case SW_OFFSET_192: 2395*4df55fdeSJanie Lu sw_offset_bytes = 192; 2396*4df55fdeSJanie Lu break; 2397*4df55fdeSJanie Lu case SW_OFFSET_256: 2398*4df55fdeSJanie Lu sw_offset_bytes = 256; 2399*4df55fdeSJanie Lu break; 2400*4df55fdeSJanie Lu case SW_OFFSET_320: 2401*4df55fdeSJanie Lu sw_offset_bytes = 320; 2402*4df55fdeSJanie Lu break; 2403*4df55fdeSJanie Lu case SW_OFFSET_384: 2404*4df55fdeSJanie Lu sw_offset_bytes = 384; 2405*4df55fdeSJanie Lu break; 2406*4df55fdeSJanie Lu case SW_OFFSET_448: 2407*4df55fdeSJanie Lu sw_offset_bytes = 448; 2408*4df55fdeSJanie Lu break; 2409*4df55fdeSJanie Lu default: 2410*4df55fdeSJanie Lu sw_offset_bytes = 0; 2411*4df55fdeSJanie Lu break; 2412*4df55fdeSJanie Lu } 2413*4df55fdeSJanie Lu 241444961713Sgirish DMA_COMMON_SYNC_OFFSET(rx_msg_p->buf_dma, 241552ccf843Smisaki (buf_offset + sw_offset_bytes), 241652ccf843Smisaki (hdr_size + l2_len), 241752ccf843Smisaki DDI_DMA_SYNC_FORCPU); 241844961713Sgirish 241944961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 242052ccf843Smisaki "==> nxge_receive_packet: after first dump:usage count")); 242144961713Sgirish 242244961713Sgirish if (rx_msg_p->cur_usage_cnt == 0) { 242344961713Sgirish if (rx_rbr_p->rbr_use_bcopy) { 242444961713Sgirish atomic_inc_32(&rx_rbr_p->rbr_consumed); 242544961713Sgirish if (rx_rbr_p->rbr_consumed < 242652ccf843Smisaki rx_rbr_p->rbr_threshold_hi) { 242744961713Sgirish if (rx_rbr_p->rbr_threshold_lo == 0 || 242852ccf843Smisaki ((rx_rbr_p->rbr_consumed >= 242952ccf843Smisaki rx_rbr_p->rbr_threshold_lo) && 243052ccf843Smisaki (rx_rbr_p->rbr_bufsize_type >= 243152ccf843Smisaki pktbufsz_type))) { 243244961713Sgirish rx_msg_p->rx_use_bcopy = B_TRUE; 243344961713Sgirish } 243444961713Sgirish } else { 243544961713Sgirish rx_msg_p->rx_use_bcopy = B_TRUE; 243644961713Sgirish } 243744961713Sgirish } 243844961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 243952ccf843Smisaki "==> nxge_receive_packet: buf %d (new block) ", 244052ccf843Smisaki bsize)); 244144961713Sgirish 244244961713Sgirish rx_msg_p->pkt_buf_size_code = pktbufsz_type; 244344961713Sgirish rx_msg_p->pkt_buf_size = bsize; 244444961713Sgirish rx_msg_p->cur_usage_cnt = 1; 244544961713Sgirish if (pktbufsz_type == RCR_SINGLE_BLOCK) { 244644961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 244752ccf843Smisaki "==> nxge_receive_packet: buf %d " 244852ccf843Smisaki "(single block) ", 244952ccf843Smisaki bsize)); 245044961713Sgirish /* 245144961713Sgirish * Buffer can be reused once the free function 245244961713Sgirish * is called. 245344961713Sgirish */ 245444961713Sgirish rx_msg_p->max_usage_cnt = 1; 245544961713Sgirish buffer_free = B_TRUE; 245644961713Sgirish } else { 245744961713Sgirish rx_msg_p->max_usage_cnt = rx_msg_p->block_size/bsize; 245844961713Sgirish if (rx_msg_p->max_usage_cnt == 1) { 245944961713Sgirish buffer_free = B_TRUE; 246044961713Sgirish } 246144961713Sgirish } 246244961713Sgirish } else { 246344961713Sgirish rx_msg_p->cur_usage_cnt++; 246444961713Sgirish if (rx_msg_p->cur_usage_cnt == rx_msg_p->max_usage_cnt) { 246544961713Sgirish buffer_free = B_TRUE; 246644961713Sgirish } 246744961713Sgirish } 246844961713Sgirish 246944961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 247044961713Sgirish "msgbuf index = %d l2len %d bytes usage %d max_usage %d ", 247152ccf843Smisaki msg_index, l2_len, 247252ccf843Smisaki rx_msg_p->cur_usage_cnt, rx_msg_p->max_usage_cnt)); 247344961713Sgirish 24744202ea4bSsbehera if ((error_type) || (dcf_err) || (pkt_too_long_err)) { 247544961713Sgirish rdc_stats->ierrors++; 247644961713Sgirish if (dcf_err) { 247744961713Sgirish rdc_stats->dcf_err++; 247844961713Sgirish #ifdef NXGE_DEBUG 247944961713Sgirish if (!rdc_stats->dcf_err) { 248044961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 248144961713Sgirish "nxge_receive_packet: channel %d dcf_err rcr" 248244961713Sgirish " 0x%llx", channel, rcr_entry)); 248344961713Sgirish } 248444961713Sgirish #endif 248544961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, nxgep->mac.portnum, NULL, 248652ccf843Smisaki NXGE_FM_EREPORT_RDMC_DCF_ERR); 24874202ea4bSsbehera } else if (pkt_too_long_err) { 24884202ea4bSsbehera rdc_stats->pkt_too_long_err++; 24894202ea4bSsbehera NXGE_DEBUG_MSG((nxgep, RX_CTL, " nxge_receive_packet:" 24904202ea4bSsbehera " channel %d packet length [%d] > " 24914202ea4bSsbehera "maxframesize [%d]", channel, l2_len + ETHERFCSL, 24924202ea4bSsbehera nxgep->mac.maxframesize)); 249344961713Sgirish } else { 249444961713Sgirish /* Update error stats */ 249544961713Sgirish error_disp_cnt = NXGE_ERROR_SHOW_MAX; 249644961713Sgirish rdc_stats->errlog.compl_err_type = error_type; 249744961713Sgirish 249844961713Sgirish switch (error_type) { 2499f6485eecSyc /* 2500f6485eecSyc * Do not send FMA ereport for RCR_L2_ERROR and 2501f6485eecSyc * RCR_L4_CSUM_ERROR because most likely they indicate 2502f6485eecSyc * back pressure rather than HW failures. 2503f6485eecSyc */ 250453f3d8ecSyc case RCR_L2_ERROR: 250553f3d8ecSyc rdc_stats->l2_err++; 250653f3d8ecSyc if (rdc_stats->l2_err < 250753f3d8ecSyc error_disp_cnt) { 250844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 250953f3d8ecSyc " nxge_receive_packet:" 251053f3d8ecSyc " channel %d RCR L2_ERROR", 251153f3d8ecSyc channel)); 251253f3d8ecSyc } 251353f3d8ecSyc break; 251453f3d8ecSyc case RCR_L4_CSUM_ERROR: 251553f3d8ecSyc error_send_up = B_TRUE; 251653f3d8ecSyc rdc_stats->l4_cksum_err++; 251753f3d8ecSyc if (rdc_stats->l4_cksum_err < 251853f3d8ecSyc error_disp_cnt) { 251953f3d8ecSyc NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 252053f3d8ecSyc " nxge_receive_packet:" 252153f3d8ecSyc " channel %d" 252253f3d8ecSyc " RCR L4_CSUM_ERROR", channel)); 252353f3d8ecSyc } 252453f3d8ecSyc break; 2525f6485eecSyc /* 2526f6485eecSyc * Do not send FMA ereport for RCR_FFLP_SOFT_ERROR and 2527f6485eecSyc * RCR_ZCP_SOFT_ERROR because they reflect the same 2528f6485eecSyc * FFLP and ZCP errors that have been reported by 2529f6485eecSyc * nxge_fflp.c and nxge_zcp.c. 2530f6485eecSyc */ 253153f3d8ecSyc case RCR_FFLP_SOFT_ERROR: 253253f3d8ecSyc error_send_up = B_TRUE; 253353f3d8ecSyc rdc_stats->fflp_soft_err++; 253453f3d8ecSyc if (rdc_stats->fflp_soft_err < 253553f3d8ecSyc error_disp_cnt) { 253653f3d8ecSyc NXGE_ERROR_MSG((nxgep, 253753f3d8ecSyc NXGE_ERR_CTL, 253853f3d8ecSyc " nxge_receive_packet:" 253953f3d8ecSyc " channel %d" 254053f3d8ecSyc " RCR FFLP_SOFT_ERROR", channel)); 254153f3d8ecSyc } 254253f3d8ecSyc break; 254353f3d8ecSyc case RCR_ZCP_SOFT_ERROR: 254453f3d8ecSyc error_send_up = B_TRUE; 254553f3d8ecSyc rdc_stats->fflp_soft_err++; 254653f3d8ecSyc if (rdc_stats->zcp_soft_err < 254753f3d8ecSyc error_disp_cnt) 254853f3d8ecSyc NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 254953f3d8ecSyc " nxge_receive_packet: Channel %d" 255053f3d8ecSyc " RCR ZCP_SOFT_ERROR", channel)); 255153f3d8ecSyc break; 255253f3d8ecSyc default: 255353f3d8ecSyc rdc_stats->rcr_unknown_err++; 255453f3d8ecSyc if (rdc_stats->rcr_unknown_err 255553f3d8ecSyc < error_disp_cnt) { 255653f3d8ecSyc NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 255753f3d8ecSyc " nxge_receive_packet: Channel %d" 255853f3d8ecSyc " RCR entry 0x%llx error 0x%x", 255953f3d8ecSyc rcr_entry, channel, error_type)); 256053f3d8ecSyc } 256153f3d8ecSyc break; 256244961713Sgirish } 256344961713Sgirish } 256444961713Sgirish 256544961713Sgirish /* 256644961713Sgirish * Update and repost buffer block if max usage 256744961713Sgirish * count is reached. 256844961713Sgirish */ 256944961713Sgirish if (error_send_up == B_FALSE) { 2570958cea9eSml atomic_inc_32(&rx_msg_p->ref_cnt); 257144961713Sgirish if (buffer_free == B_TRUE) { 257244961713Sgirish rx_msg_p->free = B_TRUE; 257344961713Sgirish } 257444961713Sgirish 257544961713Sgirish MUTEX_EXIT(&rx_rbr_p->lock); 257644961713Sgirish nxge_freeb(rx_msg_p); 257744961713Sgirish return; 257844961713Sgirish } 257944961713Sgirish } 258044961713Sgirish 258144961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 258252ccf843Smisaki "==> nxge_receive_packet: DMA sync second ")); 258344961713Sgirish 258453f3d8ecSyc bytes_read = rcr_p->rcvd_pkt_bytes; 258544961713Sgirish skip_len = sw_offset_bytes + hdr_size; 258644961713Sgirish if (!rx_msg_p->rx_use_bcopy) { 2587958cea9eSml /* 2588958cea9eSml * For loaned up buffers, the driver reference count 2589958cea9eSml * will be incremented first and then the free state. 2590958cea9eSml */ 259153f3d8ecSyc if ((nmp = nxge_dupb(rx_msg_p, buf_offset, bsize)) != NULL) { 259214ea4bb7Ssd if (first_entry) { 259314ea4bb7Ssd nmp->b_rptr = &nmp->b_rptr[skip_len]; 259453f3d8ecSyc if (l2_len < bsize - skip_len) { 259514ea4bb7Ssd nmp->b_wptr = &nmp->b_rptr[l2_len]; 259653f3d8ecSyc } else { 259753f3d8ecSyc nmp->b_wptr = &nmp->b_rptr[bsize 259853f3d8ecSyc - skip_len]; 259953f3d8ecSyc } 260014ea4bb7Ssd } else { 260153f3d8ecSyc if (l2_len - bytes_read < bsize) { 260214ea4bb7Ssd nmp->b_wptr = 260314ea4bb7Ssd &nmp->b_rptr[l2_len - bytes_read]; 260453f3d8ecSyc } else { 260553f3d8ecSyc nmp->b_wptr = &nmp->b_rptr[bsize]; 260653f3d8ecSyc } 260714ea4bb7Ssd } 260844961713Sgirish } 260953f3d8ecSyc } else { 261053f3d8ecSyc if (first_entry) { 261153f3d8ecSyc nmp = nxge_dupb_bcopy(rx_msg_p, buf_offset + skip_len, 261253f3d8ecSyc l2_len < bsize - skip_len ? 261353f3d8ecSyc l2_len : bsize - skip_len); 261453f3d8ecSyc } else { 261553f3d8ecSyc nmp = nxge_dupb_bcopy(rx_msg_p, buf_offset, 261653f3d8ecSyc l2_len - bytes_read < bsize ? 261753f3d8ecSyc l2_len - bytes_read : bsize); 261853f3d8ecSyc } 261953f3d8ecSyc } 262053f3d8ecSyc if (nmp != NULL) { 2621f720bc57Syc if (first_entry) { 2622f720bc57Syc /* 2623f720bc57Syc * Jumbo packets may be received with more than one 2624f720bc57Syc * buffer, increment ipackets for the first entry only. 2625f720bc57Syc */ 2626f720bc57Syc rdc_stats->ipackets++; 2627f720bc57Syc 2628f720bc57Syc /* Update ibytes for kstat. */ 2629f720bc57Syc rdc_stats->ibytes += skip_len 2630f720bc57Syc + l2_len < bsize ? l2_len : bsize; 2631f720bc57Syc /* 2632f720bc57Syc * Update the number of bytes read so far for the 2633f720bc57Syc * current frame. 2634f720bc57Syc */ 263553f3d8ecSyc bytes_read = nmp->b_wptr - nmp->b_rptr; 2636f720bc57Syc } else { 2637f720bc57Syc rdc_stats->ibytes += l2_len - bytes_read < bsize ? 2638f720bc57Syc l2_len - bytes_read : bsize; 263953f3d8ecSyc bytes_read += nmp->b_wptr - nmp->b_rptr; 2640f720bc57Syc } 264153f3d8ecSyc 264253f3d8ecSyc NXGE_DEBUG_MSG((nxgep, RX_CTL, 264353f3d8ecSyc "==> nxge_receive_packet after dupb: " 264453f3d8ecSyc "rbr consumed %d " 264553f3d8ecSyc "pktbufsz_type %d " 264653f3d8ecSyc "nmp $%p rptr $%p wptr $%p " 264753f3d8ecSyc "buf_offset %d bzise %d l2_len %d skip_len %d", 264853f3d8ecSyc rx_rbr_p->rbr_consumed, 264953f3d8ecSyc pktbufsz_type, 265053f3d8ecSyc nmp, nmp->b_rptr, nmp->b_wptr, 265153f3d8ecSyc buf_offset, bsize, l2_len, skip_len)); 265244961713Sgirish } else { 265344961713Sgirish cmn_err(CE_WARN, "!nxge_receive_packet: " 265452ccf843Smisaki "update stats (error)"); 26552e59129aSraghus atomic_inc_32(&rx_msg_p->ref_cnt); 26562e59129aSraghus if (buffer_free == B_TRUE) { 26572e59129aSraghus rx_msg_p->free = B_TRUE; 26582e59129aSraghus } 26592e59129aSraghus MUTEX_EXIT(&rx_rbr_p->lock); 26602e59129aSraghus nxge_freeb(rx_msg_p); 26612e59129aSraghus return; 266244961713Sgirish } 2663ee5416c9Syc 266444961713Sgirish if (buffer_free == B_TRUE) { 266544961713Sgirish rx_msg_p->free = B_TRUE; 266644961713Sgirish } 2667f720bc57Syc 266844961713Sgirish is_valid = (nmp != NULL); 266953f3d8ecSyc 267053f3d8ecSyc rcr_p->rcvd_pkt_bytes = bytes_read; 267153f3d8ecSyc 267244961713Sgirish MUTEX_EXIT(&rx_rbr_p->lock); 267344961713Sgirish 267444961713Sgirish if (rx_msg_p->free && rx_msg_p->rx_use_bcopy) { 267544961713Sgirish atomic_inc_32(&rx_msg_p->ref_cnt); 267644961713Sgirish nxge_freeb(rx_msg_p); 267744961713Sgirish } 267844961713Sgirish 267944961713Sgirish if (is_valid) { 2680a3c5bd6dSspeer nmp->b_cont = NULL; 268144961713Sgirish if (first_entry) { 268244961713Sgirish *mp = nmp; 268344961713Sgirish *mp_cont = NULL; 268453f3d8ecSyc } else { 268544961713Sgirish *mp_cont = nmp; 268653f3d8ecSyc } 268744961713Sgirish } 268844961713Sgirish 268944961713Sgirish /* 2690f720bc57Syc * ERROR, FRAG and PKT_TYPE are only reported in the first entry. 2691f720bc57Syc * If a packet is not fragmented and no error bit is set, then 2692f720bc57Syc * L4 checksum is OK. 269344961713Sgirish */ 2694f720bc57Syc 269544961713Sgirish if (is_valid && !multi) { 2696678453a8Sspeer /* 2697b4d05839Sml * If the checksum flag nxge_chksum_offload 2698b4d05839Sml * is 1, TCP and UDP packets can be sent 2699678453a8Sspeer * up with good checksum. If the checksum flag 2700b4d05839Sml * is set to 0, checksum reporting will apply to 2701678453a8Sspeer * TCP packets only (workaround for a hardware bug). 2702b4d05839Sml * If the checksum flag nxge_cksum_offload is 2703b4d05839Sml * greater than 1, both TCP and UDP packets 2704b4d05839Sml * will not be reported its hardware checksum results. 2705678453a8Sspeer */ 2706b4d05839Sml if (nxge_cksum_offload == 1) { 2707678453a8Sspeer is_tcp_udp = ((pkt_type == RCR_PKT_IS_TCP || 270852ccf843Smisaki pkt_type == RCR_PKT_IS_UDP) ? 270952ccf843Smisaki B_TRUE: B_FALSE); 2710b4d05839Sml } else if (!nxge_cksum_offload) { 2711678453a8Sspeer /* TCP checksum only. */ 2712678453a8Sspeer is_tcp_udp = ((pkt_type == RCR_PKT_IS_TCP) ? 271352ccf843Smisaki B_TRUE: B_FALSE); 2714678453a8Sspeer } 271544961713Sgirish 271644961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_receive_packet: " 271752ccf843Smisaki "is_valid 0x%x multi 0x%llx pkt %d frag %d error %d", 271852ccf843Smisaki is_valid, multi, is_tcp_udp, frag, error_type)); 271944961713Sgirish 272044961713Sgirish if (is_tcp_udp && !frag && !error_type) { 272144961713Sgirish (void) hcksum_assoc(nmp, NULL, NULL, 0, 0, 0, 0, 272252ccf843Smisaki HCK_FULLCKSUM_OK | HCK_FULLCKSUM, 0); 272344961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 272452ccf843Smisaki "==> nxge_receive_packet: Full tcp/udp cksum " 272552ccf843Smisaki "is_valid 0x%x multi 0x%llx pkt %d frag %d " 272652ccf843Smisaki "error %d", 272752ccf843Smisaki is_valid, multi, is_tcp_udp, frag, error_type)); 272844961713Sgirish } 272944961713Sgirish } 273044961713Sgirish 273144961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 273252ccf843Smisaki "==> nxge_receive_packet: *mp 0x%016llx", *mp)); 273344961713Sgirish 273444961713Sgirish *multi_p = (multi == RCR_MULTI_MASK); 273544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_receive_packet: " 273652ccf843Smisaki "multi %d nmp 0x%016llx *mp 0x%016llx *mp_cont 0x%016llx", 273752ccf843Smisaki *multi_p, nmp, *mp, *mp_cont)); 273844961713Sgirish } 273944961713Sgirish 2740da14cebeSEric Cheng /* 2741da14cebeSEric Cheng * Enable polling for a ring. Interrupt for the ring is disabled when 2742da14cebeSEric Cheng * the nxge interrupt comes (see nxge_rx_intr). 2743da14cebeSEric Cheng */ 2744da14cebeSEric Cheng int 2745da14cebeSEric Cheng nxge_enable_poll(void *arg) 2746da14cebeSEric Cheng { 2747da14cebeSEric Cheng p_nxge_ring_handle_t ring_handle = (p_nxge_ring_handle_t)arg; 2748da14cebeSEric Cheng p_rx_rcr_ring_t ringp; 2749da14cebeSEric Cheng p_nxge_t nxgep; 2750da14cebeSEric Cheng p_nxge_ldg_t ldgp; 2751da14cebeSEric Cheng uint32_t channel; 2752da14cebeSEric Cheng 2753da14cebeSEric Cheng if (ring_handle == NULL) { 275463f531d1SSriharsha Basavapatna ASSERT(ring_handle != NULL); 2755da14cebeSEric Cheng return (0); 2756da14cebeSEric Cheng } 2757da14cebeSEric Cheng 2758da14cebeSEric Cheng nxgep = ring_handle->nxgep; 2759da14cebeSEric Cheng channel = nxgep->pt_config.hw_config.start_rdc + ring_handle->index; 2760da14cebeSEric Cheng ringp = nxgep->rx_rcr_rings->rcr_rings[channel]; 2761da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2762da14cebeSEric Cheng "==> nxge_enable_poll: rdc %d ", ringp->rdc)); 2763da14cebeSEric Cheng ldgp = ringp->ldgp; 2764da14cebeSEric Cheng if (ldgp == NULL) { 2765da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2766da14cebeSEric Cheng "==> nxge_enable_poll: rdc %d NULL ldgp: no change", 2767da14cebeSEric Cheng ringp->rdc)); 2768da14cebeSEric Cheng return (0); 2769da14cebeSEric Cheng } 2770da14cebeSEric Cheng 2771da14cebeSEric Cheng MUTEX_ENTER(&ringp->lock); 2772da14cebeSEric Cheng /* enable polling */ 2773da14cebeSEric Cheng if (ringp->poll_flag == 0) { 2774da14cebeSEric Cheng ringp->poll_flag = 1; 2775da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2776da14cebeSEric Cheng "==> nxge_enable_poll: rdc %d set poll flag to 1", 2777da14cebeSEric Cheng ringp->rdc)); 2778da14cebeSEric Cheng } 2779da14cebeSEric Cheng 2780da14cebeSEric Cheng MUTEX_EXIT(&ringp->lock); 2781da14cebeSEric Cheng return (0); 2782da14cebeSEric Cheng } 2783da14cebeSEric Cheng /* 2784da14cebeSEric Cheng * Disable polling for a ring and enable its interrupt. 2785da14cebeSEric Cheng */ 2786da14cebeSEric Cheng int 2787da14cebeSEric Cheng nxge_disable_poll(void *arg) 2788da14cebeSEric Cheng { 2789da14cebeSEric Cheng p_nxge_ring_handle_t ring_handle = (p_nxge_ring_handle_t)arg; 2790da14cebeSEric Cheng p_rx_rcr_ring_t ringp; 2791da14cebeSEric Cheng p_nxge_t nxgep; 2792da14cebeSEric Cheng uint32_t channel; 2793da14cebeSEric Cheng 2794da14cebeSEric Cheng if (ring_handle == NULL) { 279563f531d1SSriharsha Basavapatna ASSERT(ring_handle != NULL); 2796da14cebeSEric Cheng return (0); 2797da14cebeSEric Cheng } 2798da14cebeSEric Cheng 2799da14cebeSEric Cheng nxgep = ring_handle->nxgep; 2800da14cebeSEric Cheng channel = nxgep->pt_config.hw_config.start_rdc + ring_handle->index; 2801da14cebeSEric Cheng ringp = nxgep->rx_rcr_rings->rcr_rings[channel]; 2802da14cebeSEric Cheng 2803da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2804da14cebeSEric Cheng "==> nxge_disable_poll: rdc %d poll_flag %d", ringp->rdc)); 2805da14cebeSEric Cheng 2806da14cebeSEric Cheng MUTEX_ENTER(&ringp->lock); 2807da14cebeSEric Cheng 2808da14cebeSEric Cheng /* disable polling: enable interrupt */ 2809da14cebeSEric Cheng if (ringp->poll_flag) { 2810da14cebeSEric Cheng npi_handle_t handle; 2811da14cebeSEric Cheng rx_dma_ctl_stat_t cs; 2812da14cebeSEric Cheng uint8_t channel; 2813da14cebeSEric Cheng p_nxge_ldg_t ldgp; 2814da14cebeSEric Cheng 2815da14cebeSEric Cheng /* 2816da14cebeSEric Cheng * Get the control and status for this channel. 2817da14cebeSEric Cheng */ 2818da14cebeSEric Cheng handle = NXGE_DEV_NPI_HANDLE(nxgep); 2819da14cebeSEric Cheng channel = ringp->rdc; 2820da14cebeSEric Cheng RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, 2821da14cebeSEric Cheng channel, &cs.value); 2822da14cebeSEric Cheng 2823da14cebeSEric Cheng /* 2824da14cebeSEric Cheng * Enable mailbox update 2825da14cebeSEric Cheng * Since packets were not read and the hardware uses 2826da14cebeSEric Cheng * bits pktread and ptrread to update the queue 2827da14cebeSEric Cheng * length, we need to set both bits to 0. 2828da14cebeSEric Cheng */ 2829da14cebeSEric Cheng cs.bits.ldw.pktread = 0; 2830da14cebeSEric Cheng cs.bits.ldw.ptrread = 0; 2831da14cebeSEric Cheng cs.bits.hdw.mex = 1; 2832da14cebeSEric Cheng RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel, 2833da14cebeSEric Cheng cs.value); 2834da14cebeSEric Cheng 2835da14cebeSEric Cheng /* 2836da14cebeSEric Cheng * Rearm this logical group if this is a single device 2837da14cebeSEric Cheng * group. 2838da14cebeSEric Cheng */ 2839da14cebeSEric Cheng ldgp = ringp->ldgp; 2840da14cebeSEric Cheng if (ldgp == NULL) { 2841da14cebeSEric Cheng ringp->poll_flag = 0; 2842da14cebeSEric Cheng MUTEX_EXIT(&ringp->lock); 2843da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2844da14cebeSEric Cheng "==> nxge_disable_poll: no ldgp rdc %d " 2845da14cebeSEric Cheng "(still set poll to 0", ringp->rdc)); 2846da14cebeSEric Cheng return (0); 2847da14cebeSEric Cheng } 2848da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2849da14cebeSEric Cheng "==> nxge_disable_poll: rdc %d ldgp $%p (enable intr)", 2850da14cebeSEric Cheng ringp->rdc, ldgp)); 2851da14cebeSEric Cheng if (ldgp->nldvs == 1) { 285263f531d1SSriharsha Basavapatna if (isLDOMguest(nxgep)) { 285363f531d1SSriharsha Basavapatna ldgp->arm = B_TRUE; 285463f531d1SSriharsha Basavapatna nxge_hio_ldgimgn(nxgep, ldgp); 285563f531d1SSriharsha Basavapatna } else { 285663f531d1SSriharsha Basavapatna ldgimgm_t mgm; 285763f531d1SSriharsha Basavapatna mgm.value = 0; 285863f531d1SSriharsha Basavapatna mgm.bits.ldw.arm = 1; 285963f531d1SSriharsha Basavapatna mgm.bits.ldw.timer = ldgp->ldg_timer; 286063f531d1SSriharsha Basavapatna NXGE_REG_WR64(handle, 286163f531d1SSriharsha Basavapatna LDGIMGN_REG + LDSV_OFFSET(ldgp->ldg), 286263f531d1SSriharsha Basavapatna mgm.value); 286363f531d1SSriharsha Basavapatna } 2864da14cebeSEric Cheng } 2865da14cebeSEric Cheng ringp->poll_flag = 0; 2866da14cebeSEric Cheng } 2867da14cebeSEric Cheng 2868da14cebeSEric Cheng MUTEX_EXIT(&ringp->lock); 2869da14cebeSEric Cheng return (0); 2870da14cebeSEric Cheng } 2871da14cebeSEric Cheng 2872da14cebeSEric Cheng /* 2873da14cebeSEric Cheng * Poll 'bytes_to_pickup' bytes of message from the rx ring. 2874da14cebeSEric Cheng */ 2875da14cebeSEric Cheng mblk_t * 2876da14cebeSEric Cheng nxge_rx_poll(void *arg, int bytes_to_pickup) 2877da14cebeSEric Cheng { 2878da14cebeSEric Cheng p_nxge_ring_handle_t ring_handle = (p_nxge_ring_handle_t)arg; 2879da14cebeSEric Cheng p_rx_rcr_ring_t rcr_p; 2880da14cebeSEric Cheng p_nxge_t nxgep; 2881da14cebeSEric Cheng npi_handle_t handle; 2882da14cebeSEric Cheng rx_dma_ctl_stat_t cs; 2883da14cebeSEric Cheng mblk_t *mblk; 2884da14cebeSEric Cheng p_nxge_ldv_t ldvp; 2885da14cebeSEric Cheng uint32_t channel; 2886da14cebeSEric Cheng 2887da14cebeSEric Cheng nxgep = ring_handle->nxgep; 2888da14cebeSEric Cheng 2889da14cebeSEric Cheng /* 2890da14cebeSEric Cheng * Get the control and status for this channel. 2891da14cebeSEric Cheng */ 2892da14cebeSEric Cheng handle = NXGE_DEV_NPI_HANDLE(nxgep); 2893da14cebeSEric Cheng channel = nxgep->pt_config.hw_config.start_rdc + ring_handle->index; 2894da14cebeSEric Cheng rcr_p = nxgep->rx_rcr_rings->rcr_rings[channel]; 2895da14cebeSEric Cheng MUTEX_ENTER(&rcr_p->lock); 2896da14cebeSEric Cheng ASSERT(rcr_p->poll_flag == 1); 2897da14cebeSEric Cheng 2898da14cebeSEric Cheng RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, rcr_p->rdc, &cs.value); 2899da14cebeSEric Cheng 2900da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2901da14cebeSEric Cheng "==> nxge_rx_poll: calling nxge_rx_pkts: rdc %d poll_flag %d", 2902da14cebeSEric Cheng rcr_p->rdc, rcr_p->poll_flag)); 2903da14cebeSEric Cheng mblk = nxge_rx_pkts(nxgep, rcr_p, cs, bytes_to_pickup); 2904da14cebeSEric Cheng 2905da14cebeSEric Cheng ldvp = rcr_p->ldvp; 2906da14cebeSEric Cheng /* error events. */ 2907da14cebeSEric Cheng if (ldvp && (cs.value & RX_DMA_CTL_STAT_ERROR)) { 2908da14cebeSEric Cheng (void) nxge_rx_err_evnts(nxgep, ldvp->vdma_index, cs); 2909da14cebeSEric Cheng } 2910da14cebeSEric Cheng 2911da14cebeSEric Cheng MUTEX_EXIT(&rcr_p->lock); 2912da14cebeSEric Cheng 2913da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2914da14cebeSEric Cheng "<== nxge_rx_poll: rdc %d mblk $%p", rcr_p->rdc, mblk)); 2915da14cebeSEric Cheng return (mblk); 2916da14cebeSEric Cheng } 2917da14cebeSEric Cheng 2918da14cebeSEric Cheng 291944961713Sgirish /*ARGSUSED*/ 292044961713Sgirish static nxge_status_t 2921678453a8Sspeer nxge_rx_err_evnts(p_nxge_t nxgep, int channel, rx_dma_ctl_stat_t cs) 292244961713Sgirish { 292344961713Sgirish p_nxge_rx_ring_stats_t rdc_stats; 292444961713Sgirish npi_handle_t handle; 292544961713Sgirish npi_status_t rs; 292644961713Sgirish boolean_t rxchan_fatal = B_FALSE; 292744961713Sgirish boolean_t rxport_fatal = B_FALSE; 292844961713Sgirish uint8_t portn; 292944961713Sgirish nxge_status_t status = NXGE_OK; 293044961713Sgirish uint32_t error_disp_cnt = NXGE_ERROR_SHOW_MAX; 293144961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_rx_err_evnts")); 293244961713Sgirish 293344961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 293444961713Sgirish portn = nxgep->mac.portnum; 2935678453a8Sspeer rdc_stats = &nxgep->statsp->rdc_stats[channel]; 293644961713Sgirish 293744961713Sgirish if (cs.bits.hdw.rbr_tmout) { 293844961713Sgirish rdc_stats->rx_rbr_tmout++; 293944961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 294052ccf843Smisaki NXGE_FM_EREPORT_RDMC_RBR_TMOUT); 294144961713Sgirish rxchan_fatal = B_TRUE; 294244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 294352ccf843Smisaki "==> nxge_rx_err_evnts: rx_rbr_timeout")); 294444961713Sgirish } 294544961713Sgirish if (cs.bits.hdw.rsp_cnt_err) { 294644961713Sgirish rdc_stats->rsp_cnt_err++; 294744961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 294852ccf843Smisaki NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR); 294944961713Sgirish rxchan_fatal = B_TRUE; 295044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 295152ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 295252ccf843Smisaki "rsp_cnt_err", channel)); 295344961713Sgirish } 295444961713Sgirish if (cs.bits.hdw.byte_en_bus) { 295544961713Sgirish rdc_stats->byte_en_bus++; 295644961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 295752ccf843Smisaki NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS); 295844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 295952ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 296052ccf843Smisaki "fatal error: byte_en_bus", channel)); 296144961713Sgirish rxchan_fatal = B_TRUE; 296244961713Sgirish } 296344961713Sgirish if (cs.bits.hdw.rsp_dat_err) { 296444961713Sgirish rdc_stats->rsp_dat_err++; 296544961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 296652ccf843Smisaki NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR); 296744961713Sgirish rxchan_fatal = B_TRUE; 296844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 296952ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 297052ccf843Smisaki "fatal error: rsp_dat_err", channel)); 297144961713Sgirish } 297244961713Sgirish if (cs.bits.hdw.rcr_ack_err) { 297344961713Sgirish rdc_stats->rcr_ack_err++; 297444961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 297552ccf843Smisaki NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR); 297644961713Sgirish rxchan_fatal = B_TRUE; 297744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 297852ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 297952ccf843Smisaki "fatal error: rcr_ack_err", channel)); 298044961713Sgirish } 298144961713Sgirish if (cs.bits.hdw.dc_fifo_err) { 298244961713Sgirish rdc_stats->dc_fifo_err++; 298344961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 298452ccf843Smisaki NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR); 298544961713Sgirish /* This is not a fatal error! */ 298644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 298752ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 298852ccf843Smisaki "dc_fifo_err", channel)); 298944961713Sgirish rxport_fatal = B_TRUE; 299044961713Sgirish } 299144961713Sgirish if ((cs.bits.hdw.rcr_sha_par) || (cs.bits.hdw.rbr_pre_par)) { 299244961713Sgirish if ((rs = npi_rxdma_ring_perr_stat_get(handle, 299352ccf843Smisaki &rdc_stats->errlog.pre_par, 299452ccf843Smisaki &rdc_stats->errlog.sha_par)) 299552ccf843Smisaki != NPI_SUCCESS) { 299644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 299752ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 299852ccf843Smisaki "rcr_sha_par: get perr", channel)); 299944961713Sgirish return (NXGE_ERROR | rs); 300044961713Sgirish } 300144961713Sgirish if (cs.bits.hdw.rcr_sha_par) { 300244961713Sgirish rdc_stats->rcr_sha_par++; 300344961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 300452ccf843Smisaki NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR); 300544961713Sgirish rxchan_fatal = B_TRUE; 300644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 300752ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 300852ccf843Smisaki "fatal error: rcr_sha_par", channel)); 300944961713Sgirish } 301044961713Sgirish if (cs.bits.hdw.rbr_pre_par) { 301144961713Sgirish rdc_stats->rbr_pre_par++; 301244961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 301352ccf843Smisaki NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR); 301444961713Sgirish rxchan_fatal = B_TRUE; 301544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 301652ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 301752ccf843Smisaki "fatal error: rbr_pre_par", channel)); 301844961713Sgirish } 301944961713Sgirish } 302063e23a19Syc /* 302163e23a19Syc * The Following 4 status bits are for information, the system 302263e23a19Syc * is running fine. There is no need to send FMA ereports or 302363e23a19Syc * log messages. 302463e23a19Syc */ 302544961713Sgirish if (cs.bits.hdw.port_drop_pkt) { 302644961713Sgirish rdc_stats->port_drop_pkt++; 302744961713Sgirish } 302844961713Sgirish if (cs.bits.hdw.wred_drop) { 302944961713Sgirish rdc_stats->wred_drop++; 303044961713Sgirish } 303144961713Sgirish if (cs.bits.hdw.rbr_pre_empty) { 303244961713Sgirish rdc_stats->rbr_pre_empty++; 303344961713Sgirish } 303444961713Sgirish if (cs.bits.hdw.rcr_shadow_full) { 303544961713Sgirish rdc_stats->rcr_shadow_full++; 303644961713Sgirish } 303744961713Sgirish if (cs.bits.hdw.config_err) { 303844961713Sgirish rdc_stats->config_err++; 303944961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 304052ccf843Smisaki NXGE_FM_EREPORT_RDMC_CONFIG_ERR); 304144961713Sgirish rxchan_fatal = B_TRUE; 304244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 304352ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 304452ccf843Smisaki "config error", channel)); 304544961713Sgirish } 304644961713Sgirish if (cs.bits.hdw.rcrincon) { 304744961713Sgirish rdc_stats->rcrincon++; 304844961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 304952ccf843Smisaki NXGE_FM_EREPORT_RDMC_RCRINCON); 305044961713Sgirish rxchan_fatal = B_TRUE; 305144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 305252ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 305352ccf843Smisaki "fatal error: rcrincon error", channel)); 305444961713Sgirish } 305544961713Sgirish if (cs.bits.hdw.rcrfull) { 305644961713Sgirish rdc_stats->rcrfull++; 305744961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 305852ccf843Smisaki NXGE_FM_EREPORT_RDMC_RCRFULL); 305944961713Sgirish rxchan_fatal = B_TRUE; 306044961713Sgirish if (rdc_stats->rcrfull < error_disp_cnt) 306144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 306252ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 306352ccf843Smisaki "fatal error: rcrfull error", channel)); 306444961713Sgirish } 306544961713Sgirish if (cs.bits.hdw.rbr_empty) { 306663e23a19Syc /* 306763e23a19Syc * This bit is for information, there is no need 306863e23a19Syc * send FMA ereport or log a message. 306963e23a19Syc */ 307044961713Sgirish rdc_stats->rbr_empty++; 307144961713Sgirish } 307244961713Sgirish if (cs.bits.hdw.rbrfull) { 307344961713Sgirish rdc_stats->rbrfull++; 307444961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 307552ccf843Smisaki NXGE_FM_EREPORT_RDMC_RBRFULL); 307644961713Sgirish rxchan_fatal = B_TRUE; 307744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 307852ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 307952ccf843Smisaki "fatal error: rbr_full error", channel)); 308044961713Sgirish } 308144961713Sgirish if (cs.bits.hdw.rbrlogpage) { 308244961713Sgirish rdc_stats->rbrlogpage++; 308344961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 308452ccf843Smisaki NXGE_FM_EREPORT_RDMC_RBRLOGPAGE); 308544961713Sgirish rxchan_fatal = B_TRUE; 308644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 308752ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 308852ccf843Smisaki "fatal error: rbr logical page error", channel)); 308944961713Sgirish } 309044961713Sgirish if (cs.bits.hdw.cfiglogpage) { 309144961713Sgirish rdc_stats->cfiglogpage++; 309244961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 309352ccf843Smisaki NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE); 309444961713Sgirish rxchan_fatal = B_TRUE; 309544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 309652ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 309752ccf843Smisaki "fatal error: cfig logical page error", channel)); 309844961713Sgirish } 309944961713Sgirish 310044961713Sgirish if (rxport_fatal) { 310144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3102678453a8Sspeer " nxge_rx_err_evnts: fatal error on Port #%d\n", 3103678453a8Sspeer portn)); 3104678453a8Sspeer if (isLDOMguest(nxgep)) { 3105678453a8Sspeer status = NXGE_ERROR; 3106678453a8Sspeer } else { 3107678453a8Sspeer status = nxge_ipp_fatal_err_recover(nxgep); 3108678453a8Sspeer if (status == NXGE_OK) { 3109678453a8Sspeer FM_SERVICE_RESTORED(nxgep); 3110678453a8Sspeer } 311144961713Sgirish } 311244961713Sgirish } 311344961713Sgirish 311444961713Sgirish if (rxchan_fatal) { 311544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3116678453a8Sspeer " nxge_rx_err_evnts: fatal error on Channel #%d\n", 3117678453a8Sspeer channel)); 3118678453a8Sspeer if (isLDOMguest(nxgep)) { 3119678453a8Sspeer status = NXGE_ERROR; 3120678453a8Sspeer } else { 3121678453a8Sspeer status = nxge_rxdma_fatal_err_recover(nxgep, channel); 3122678453a8Sspeer if (status == NXGE_OK) { 3123678453a8Sspeer FM_SERVICE_RESTORED(nxgep); 3124678453a8Sspeer } 312544961713Sgirish } 312644961713Sgirish } 312744961713Sgirish 312844961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, "<== nxge_rx_err_evnts")); 312944961713Sgirish 313044961713Sgirish return (status); 313144961713Sgirish } 313244961713Sgirish 3133678453a8Sspeer /* 3134678453a8Sspeer * nxge_rdc_hvio_setup 3135678453a8Sspeer * 3136678453a8Sspeer * This code appears to setup some Hypervisor variables. 3137678453a8Sspeer * 3138678453a8Sspeer * Arguments: 3139678453a8Sspeer * nxgep 3140678453a8Sspeer * channel 3141678453a8Sspeer * 3142678453a8Sspeer * Notes: 3143678453a8Sspeer * What does NIU_LP_WORKAROUND mean? 3144678453a8Sspeer * 3145678453a8Sspeer * NPI/NXGE function calls: 3146678453a8Sspeer * na 3147678453a8Sspeer * 3148678453a8Sspeer * Context: 3149678453a8Sspeer * Any domain 3150678453a8Sspeer */ 3151678453a8Sspeer #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3152678453a8Sspeer static void 3153678453a8Sspeer nxge_rdc_hvio_setup( 3154678453a8Sspeer nxge_t *nxgep, int channel) 315544961713Sgirish { 3156678453a8Sspeer nxge_dma_common_t *dma_common; 3157678453a8Sspeer nxge_dma_common_t *dma_control; 3158678453a8Sspeer rx_rbr_ring_t *ring; 3159678453a8Sspeer 3160678453a8Sspeer ring = nxgep->rx_rbr_rings->rbr_rings[channel]; 3161678453a8Sspeer dma_common = nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 3162678453a8Sspeer 3163678453a8Sspeer ring->hv_set = B_FALSE; 3164678453a8Sspeer 3165678453a8Sspeer ring->hv_rx_buf_base_ioaddr_pp = (uint64_t) 3166678453a8Sspeer dma_common->orig_ioaddr_pp; 3167678453a8Sspeer ring->hv_rx_buf_ioaddr_size = (uint64_t) 3168678453a8Sspeer dma_common->orig_alength; 3169678453a8Sspeer 3170678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_map_rxdma_channel: " 3171678453a8Sspeer "channel %d data buf base io $%lx ($%p) size 0x%lx (%ld 0x%lx)", 3172678453a8Sspeer channel, ring->hv_rx_buf_base_ioaddr_pp, 3173678453a8Sspeer dma_common->ioaddr_pp, ring->hv_rx_buf_ioaddr_size, 3174678453a8Sspeer dma_common->orig_alength, dma_common->orig_alength)); 3175678453a8Sspeer 3176678453a8Sspeer dma_control = nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 3177678453a8Sspeer 3178678453a8Sspeer ring->hv_rx_cntl_base_ioaddr_pp = 3179678453a8Sspeer (uint64_t)dma_control->orig_ioaddr_pp; 3180678453a8Sspeer ring->hv_rx_cntl_ioaddr_size = 3181678453a8Sspeer (uint64_t)dma_control->orig_alength; 3182678453a8Sspeer 3183678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_map_rxdma_channel: " 3184678453a8Sspeer "channel %d cntl base io $%p ($%p) size 0x%llx (%d 0x%x)", 3185678453a8Sspeer channel, ring->hv_rx_cntl_base_ioaddr_pp, 3186678453a8Sspeer dma_control->ioaddr_pp, ring->hv_rx_cntl_ioaddr_size, 3187678453a8Sspeer dma_control->orig_alength, dma_control->orig_alength)); 3188678453a8Sspeer } 318944961713Sgirish #endif 319044961713Sgirish 3191678453a8Sspeer /* 3192678453a8Sspeer * nxge_map_rxdma 3193678453a8Sspeer * 3194678453a8Sspeer * Map an RDC into our kernel space. 3195678453a8Sspeer * 3196678453a8Sspeer * Arguments: 3197678453a8Sspeer * nxgep 3198678453a8Sspeer * channel The channel to map. 3199678453a8Sspeer * 3200678453a8Sspeer * Notes: 3201678453a8Sspeer * 1. Allocate & initialise a memory pool, if necessary. 3202678453a8Sspeer * 2. Allocate however many receive buffers are required. 3203678453a8Sspeer * 3. Setup buffers, descriptors, and mailbox. 3204678453a8Sspeer * 3205678453a8Sspeer * NPI/NXGE function calls: 3206678453a8Sspeer * nxge_alloc_rx_mem_pool() 3207678453a8Sspeer * nxge_alloc_rbb() 3208678453a8Sspeer * nxge_map_rxdma_channel() 3209678453a8Sspeer * 3210678453a8Sspeer * Registers accessed: 3211678453a8Sspeer * 3212678453a8Sspeer * Context: 3213678453a8Sspeer * Any domain 3214678453a8Sspeer */ 3215678453a8Sspeer static nxge_status_t 3216678453a8Sspeer nxge_map_rxdma(p_nxge_t nxgep, int channel) 3217678453a8Sspeer { 3218678453a8Sspeer nxge_dma_common_t **data; 3219678453a8Sspeer nxge_dma_common_t **control; 3220678453a8Sspeer rx_rbr_ring_t **rbr_ring; 3221678453a8Sspeer rx_rcr_ring_t **rcr_ring; 3222678453a8Sspeer rx_mbox_t **mailbox; 3223678453a8Sspeer uint32_t chunks; 322444961713Sgirish 3225678453a8Sspeer nxge_status_t status; 322644961713Sgirish 3227678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_map_rxdma")); 322844961713Sgirish 3229678453a8Sspeer if (!nxgep->rx_buf_pool_p) { 3230678453a8Sspeer if (nxge_alloc_rx_mem_pool(nxgep) != NXGE_OK) { 3231678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3232678453a8Sspeer "<== nxge_map_rxdma: buf not allocated")); 3233678453a8Sspeer return (NXGE_ERROR); 3234678453a8Sspeer } 323544961713Sgirish } 323644961713Sgirish 3237678453a8Sspeer if (nxge_alloc_rxb(nxgep, channel) != NXGE_OK) 3238678453a8Sspeer return (NXGE_ERROR); 323914ea4bb7Ssd 324044961713Sgirish /* 3241678453a8Sspeer * Map descriptors from the buffer polls for each dma channel. 324244961713Sgirish */ 324344961713Sgirish 3244678453a8Sspeer /* 3245678453a8Sspeer * Set up and prepare buffer blocks, descriptors 3246678453a8Sspeer * and mailbox. 3247678453a8Sspeer */ 3248678453a8Sspeer data = &nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 3249678453a8Sspeer rbr_ring = &nxgep->rx_rbr_rings->rbr_rings[channel]; 3250678453a8Sspeer chunks = nxgep->rx_buf_pool_p->num_chunks[channel]; 325144961713Sgirish 3252678453a8Sspeer control = &nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 3253678453a8Sspeer rcr_ring = &nxgep->rx_rcr_rings->rcr_rings[channel]; 325444961713Sgirish 3255678453a8Sspeer mailbox = &nxgep->rx_mbox_areas_p->rxmbox_areas[channel]; 325644961713Sgirish 3257678453a8Sspeer status = nxge_map_rxdma_channel(nxgep, channel, data, rbr_ring, 3258678453a8Sspeer chunks, control, rcr_ring, mailbox); 3259678453a8Sspeer if (status != NXGE_OK) { 3260678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 326152ccf843Smisaki "==> nxge_map_rxdma: nxge_map_rxdma_channel(%d) " 326252ccf843Smisaki "returned 0x%x", 326352ccf843Smisaki channel, status)); 3264678453a8Sspeer return (status); 3265678453a8Sspeer } 3266678453a8Sspeer nxgep->rx_rbr_rings->rbr_rings[channel]->index = (uint16_t)channel; 3267678453a8Sspeer nxgep->rx_rcr_rings->rcr_rings[channel]->index = (uint16_t)channel; 3268678453a8Sspeer nxgep->rx_rcr_rings->rcr_rings[channel]->rdc_stats = 3269678453a8Sspeer &nxgep->statsp->rdc_stats[channel]; 327044961713Sgirish 3271678453a8Sspeer #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3272678453a8Sspeer if (!isLDOMguest(nxgep)) 3273678453a8Sspeer nxge_rdc_hvio_setup(nxgep, channel); 3274678453a8Sspeer #endif 327544961713Sgirish 327644961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3277678453a8Sspeer "<== nxge_map_rxdma: (status 0x%x channel %d)", status, channel)); 327844961713Sgirish 327944961713Sgirish return (status); 328044961713Sgirish } 328144961713Sgirish 328244961713Sgirish static void 3283678453a8Sspeer nxge_unmap_rxdma(p_nxge_t nxgep, int channel) 328444961713Sgirish { 3285678453a8Sspeer rx_rbr_ring_t *rbr_ring; 3286678453a8Sspeer rx_rcr_ring_t *rcr_ring; 3287678453a8Sspeer rx_mbox_t *mailbox; 328844961713Sgirish 3289678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_unmap_rxdma(%d)", channel)); 329044961713Sgirish 3291678453a8Sspeer if (!nxgep->rx_rbr_rings || !nxgep->rx_rcr_rings || 3292678453a8Sspeer !nxgep->rx_mbox_areas_p) 329344961713Sgirish return; 329444961713Sgirish 3295678453a8Sspeer rbr_ring = nxgep->rx_rbr_rings->rbr_rings[channel]; 3296678453a8Sspeer rcr_ring = nxgep->rx_rcr_rings->rcr_rings[channel]; 3297678453a8Sspeer mailbox = nxgep->rx_mbox_areas_p->rxmbox_areas[channel]; 329844961713Sgirish 3299678453a8Sspeer if (!rbr_ring || !rcr_ring || !mailbox) 3300678453a8Sspeer return; 330144961713Sgirish 3302678453a8Sspeer (void) nxge_unmap_rxdma_channel( 330352ccf843Smisaki nxgep, channel, rbr_ring, rcr_ring, mailbox); 330444961713Sgirish 3305678453a8Sspeer nxge_free_rxb(nxgep, channel); 330644961713Sgirish 3307678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_unmap_rxdma")); 330844961713Sgirish } 330944961713Sgirish 331044961713Sgirish nxge_status_t 331144961713Sgirish nxge_map_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 331244961713Sgirish p_nxge_dma_common_t *dma_buf_p, p_rx_rbr_ring_t *rbr_p, 331344961713Sgirish uint32_t num_chunks, 331444961713Sgirish p_nxge_dma_common_t *dma_cntl_p, p_rx_rcr_ring_t *rcr_p, 331544961713Sgirish p_rx_mbox_t *rx_mbox_p) 331644961713Sgirish { 331744961713Sgirish int status = NXGE_OK; 331844961713Sgirish 331944961713Sgirish /* 332044961713Sgirish * Set up and prepare buffer blocks, descriptors 332144961713Sgirish * and mailbox. 332244961713Sgirish */ 332344961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 332452ccf843Smisaki "==> nxge_map_rxdma_channel (channel %d)", channel)); 332544961713Sgirish /* 332644961713Sgirish * Receive buffer blocks 332744961713Sgirish */ 332844961713Sgirish status = nxge_map_rxdma_channel_buf_ring(nxgep, channel, 332952ccf843Smisaki dma_buf_p, rbr_p, num_chunks); 333044961713Sgirish if (status != NXGE_OK) { 333144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 333252ccf843Smisaki "==> nxge_map_rxdma_channel (channel %d): " 333352ccf843Smisaki "map buffer failed 0x%x", channel, status)); 333444961713Sgirish goto nxge_map_rxdma_channel_exit; 333544961713Sgirish } 333644961713Sgirish 333744961713Sgirish /* 333844961713Sgirish * Receive block ring, completion ring and mailbox. 333944961713Sgirish */ 334044961713Sgirish status = nxge_map_rxdma_channel_cfg_ring(nxgep, channel, 334152ccf843Smisaki dma_cntl_p, rbr_p, rcr_p, rx_mbox_p); 334244961713Sgirish if (status != NXGE_OK) { 334344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 334452ccf843Smisaki "==> nxge_map_rxdma_channel (channel %d): " 334552ccf843Smisaki "map config failed 0x%x", channel, status)); 334644961713Sgirish goto nxge_map_rxdma_channel_fail2; 334744961713Sgirish } 334844961713Sgirish 334944961713Sgirish goto nxge_map_rxdma_channel_exit; 335044961713Sgirish 335144961713Sgirish nxge_map_rxdma_channel_fail3: 335244961713Sgirish /* Free rbr, rcr */ 335344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 335452ccf843Smisaki "==> nxge_map_rxdma_channel: free rbr/rcr " 335552ccf843Smisaki "(status 0x%x channel %d)", 335652ccf843Smisaki status, channel)); 335744961713Sgirish nxge_unmap_rxdma_channel_cfg_ring(nxgep, 335852ccf843Smisaki *rcr_p, *rx_mbox_p); 335944961713Sgirish 336044961713Sgirish nxge_map_rxdma_channel_fail2: 336144961713Sgirish /* Free buffer blocks */ 336244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 336352ccf843Smisaki "==> nxge_map_rxdma_channel: free rx buffers" 336452ccf843Smisaki "(nxgep 0x%x status 0x%x channel %d)", 336552ccf843Smisaki nxgep, status, channel)); 336644961713Sgirish nxge_unmap_rxdma_channel_buf_ring(nxgep, *rbr_p); 336744961713Sgirish 336856d930aeSspeer status = NXGE_ERROR; 336956d930aeSspeer 337044961713Sgirish nxge_map_rxdma_channel_exit: 337144961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 337252ccf843Smisaki "<== nxge_map_rxdma_channel: " 337352ccf843Smisaki "(nxgep 0x%x status 0x%x channel %d)", 337452ccf843Smisaki nxgep, status, channel)); 337544961713Sgirish 337644961713Sgirish return (status); 337744961713Sgirish } 337844961713Sgirish 337944961713Sgirish /*ARGSUSED*/ 338044961713Sgirish static void 338144961713Sgirish nxge_unmap_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 338244961713Sgirish p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 338344961713Sgirish { 338444961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 338552ccf843Smisaki "==> nxge_unmap_rxdma_channel (channel %d)", channel)); 338644961713Sgirish 338744961713Sgirish /* 338844961713Sgirish * unmap receive block ring, completion ring and mailbox. 338944961713Sgirish */ 339044961713Sgirish (void) nxge_unmap_rxdma_channel_cfg_ring(nxgep, 339152ccf843Smisaki rcr_p, rx_mbox_p); 339244961713Sgirish 339344961713Sgirish /* unmap buffer blocks */ 339444961713Sgirish (void) nxge_unmap_rxdma_channel_buf_ring(nxgep, rbr_p); 339544961713Sgirish 339644961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_unmap_rxdma_channel")); 339744961713Sgirish } 339844961713Sgirish 339944961713Sgirish /*ARGSUSED*/ 340044961713Sgirish static nxge_status_t 340144961713Sgirish nxge_map_rxdma_channel_cfg_ring(p_nxge_t nxgep, uint16_t dma_channel, 340244961713Sgirish p_nxge_dma_common_t *dma_cntl_p, p_rx_rbr_ring_t *rbr_p, 340344961713Sgirish p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p) 340444961713Sgirish { 340544961713Sgirish p_rx_rbr_ring_t rbrp; 340644961713Sgirish p_rx_rcr_ring_t rcrp; 340744961713Sgirish p_rx_mbox_t mboxp; 340844961713Sgirish p_nxge_dma_common_t cntl_dmap; 340944961713Sgirish p_nxge_dma_common_t dmap; 341044961713Sgirish p_rx_msg_t *rx_msg_ring; 341144961713Sgirish p_rx_msg_t rx_msg_p; 341244961713Sgirish p_rbr_cfig_a_t rcfga_p; 341344961713Sgirish p_rbr_cfig_b_t rcfgb_p; 341444961713Sgirish p_rcrcfig_a_t cfga_p; 341544961713Sgirish p_rcrcfig_b_t cfgb_p; 341644961713Sgirish p_rxdma_cfig1_t cfig1_p; 341744961713Sgirish p_rxdma_cfig2_t cfig2_p; 341844961713Sgirish p_rbr_kick_t kick_p; 341944961713Sgirish uint32_t dmaaddrp; 342044961713Sgirish uint32_t *rbr_vaddrp; 342144961713Sgirish uint32_t bkaddr; 342244961713Sgirish nxge_status_t status = NXGE_OK; 342344961713Sgirish int i; 342444961713Sgirish uint32_t nxge_port_rcr_size; 342544961713Sgirish 342644961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 342752ccf843Smisaki "==> nxge_map_rxdma_channel_cfg_ring")); 342844961713Sgirish 342944961713Sgirish cntl_dmap = *dma_cntl_p; 343044961713Sgirish 343144961713Sgirish /* Map in the receive block ring */ 343244961713Sgirish rbrp = *rbr_p; 343344961713Sgirish dmap = (p_nxge_dma_common_t)&rbrp->rbr_desc; 343444961713Sgirish nxge_setup_dma_common(dmap, cntl_dmap, rbrp->rbb_max, 4); 343544961713Sgirish /* 343644961713Sgirish * Zero out buffer block ring descriptors. 343744961713Sgirish */ 343844961713Sgirish bzero((caddr_t)dmap->kaddrp, dmap->alength); 343944961713Sgirish 344044961713Sgirish rcfga_p = &(rbrp->rbr_cfga); 344144961713Sgirish rcfgb_p = &(rbrp->rbr_cfgb); 344244961713Sgirish kick_p = &(rbrp->rbr_kick); 344344961713Sgirish rcfga_p->value = 0; 344444961713Sgirish rcfgb_p->value = 0; 344544961713Sgirish kick_p->value = 0; 344644961713Sgirish rbrp->rbr_addr = dmap->dma_cookie.dmac_laddress; 344744961713Sgirish rcfga_p->value = (rbrp->rbr_addr & 344852ccf843Smisaki (RBR_CFIG_A_STDADDR_MASK | 344952ccf843Smisaki RBR_CFIG_A_STDADDR_BASE_MASK)); 345044961713Sgirish rcfga_p->value |= ((uint64_t)rbrp->rbb_max << RBR_CFIG_A_LEN_SHIFT); 345144961713Sgirish 345244961713Sgirish rcfgb_p->bits.ldw.bufsz0 = rbrp->pkt_buf_size0; 345344961713Sgirish rcfgb_p->bits.ldw.vld0 = 1; 345444961713Sgirish rcfgb_p->bits.ldw.bufsz1 = rbrp->pkt_buf_size1; 345544961713Sgirish rcfgb_p->bits.ldw.vld1 = 1; 345644961713Sgirish rcfgb_p->bits.ldw.bufsz2 = rbrp->pkt_buf_size2; 345744961713Sgirish rcfgb_p->bits.ldw.vld2 = 1; 345844961713Sgirish rcfgb_p->bits.ldw.bksize = nxgep->rx_bksize_code; 345944961713Sgirish 346044961713Sgirish /* 346144961713Sgirish * For each buffer block, enter receive block address to the ring. 346244961713Sgirish */ 346344961713Sgirish rbr_vaddrp = (uint32_t *)dmap->kaddrp; 346444961713Sgirish rbrp->rbr_desc_vp = (uint32_t *)dmap->kaddrp; 346544961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 346652ccf843Smisaki "==> nxge_map_rxdma_channel_cfg_ring: channel %d " 346752ccf843Smisaki "rbr_vaddrp $%p", dma_channel, rbr_vaddrp)); 346844961713Sgirish 346944961713Sgirish rx_msg_ring = rbrp->rx_msg_ring; 347044961713Sgirish for (i = 0; i < rbrp->tnblocks; i++) { 347144961713Sgirish rx_msg_p = rx_msg_ring[i]; 347244961713Sgirish rx_msg_p->nxgep = nxgep; 347344961713Sgirish rx_msg_p->rx_rbr_p = rbrp; 347444961713Sgirish bkaddr = (uint32_t) 347552ccf843Smisaki ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress 347652ccf843Smisaki >> RBR_BKADDR_SHIFT)); 347744961713Sgirish rx_msg_p->free = B_FALSE; 347844961713Sgirish rx_msg_p->max_usage_cnt = 0xbaddcafe; 347944961713Sgirish 348044961713Sgirish *rbr_vaddrp++ = bkaddr; 348144961713Sgirish } 348244961713Sgirish 348344961713Sgirish kick_p->bits.ldw.bkadd = rbrp->rbb_max; 348444961713Sgirish rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 348544961713Sgirish 348644961713Sgirish rbrp->rbr_rd_index = 0; 348744961713Sgirish 348844961713Sgirish rbrp->rbr_consumed = 0; 348944961713Sgirish rbrp->rbr_use_bcopy = B_TRUE; 349044961713Sgirish rbrp->rbr_bufsize_type = RCR_PKTBUFSZ_0; 349144961713Sgirish /* 349244961713Sgirish * Do bcopy on packets greater than bcopy size once 349344961713Sgirish * the lo threshold is reached. 349444961713Sgirish * This lo threshold should be less than the hi threshold. 349544961713Sgirish * 349644961713Sgirish * Do bcopy on every packet once the hi threshold is reached. 349744961713Sgirish */ 349844961713Sgirish if (nxge_rx_threshold_lo >= nxge_rx_threshold_hi) { 349944961713Sgirish /* default it to use hi */ 350044961713Sgirish nxge_rx_threshold_lo = nxge_rx_threshold_hi; 350144961713Sgirish } 350244961713Sgirish 350344961713Sgirish if (nxge_rx_buf_size_type > NXGE_RBR_TYPE2) { 350444961713Sgirish nxge_rx_buf_size_type = NXGE_RBR_TYPE2; 350544961713Sgirish } 350644961713Sgirish rbrp->rbr_bufsize_type = nxge_rx_buf_size_type; 350744961713Sgirish 350844961713Sgirish switch (nxge_rx_threshold_hi) { 350944961713Sgirish default: 351044961713Sgirish case NXGE_RX_COPY_NONE: 351144961713Sgirish /* Do not do bcopy at all */ 351244961713Sgirish rbrp->rbr_use_bcopy = B_FALSE; 351344961713Sgirish rbrp->rbr_threshold_hi = rbrp->rbb_max; 351444961713Sgirish break; 351544961713Sgirish 351644961713Sgirish case NXGE_RX_COPY_1: 351744961713Sgirish case NXGE_RX_COPY_2: 351844961713Sgirish case NXGE_RX_COPY_3: 351944961713Sgirish case NXGE_RX_COPY_4: 352044961713Sgirish case NXGE_RX_COPY_5: 352144961713Sgirish case NXGE_RX_COPY_6: 352244961713Sgirish case NXGE_RX_COPY_7: 352344961713Sgirish rbrp->rbr_threshold_hi = 352452ccf843Smisaki rbrp->rbb_max * 352552ccf843Smisaki (nxge_rx_threshold_hi)/NXGE_RX_BCOPY_SCALE; 352644961713Sgirish break; 352744961713Sgirish 352844961713Sgirish case NXGE_RX_COPY_ALL: 352944961713Sgirish rbrp->rbr_threshold_hi = 0; 353044961713Sgirish break; 353144961713Sgirish } 353244961713Sgirish 353344961713Sgirish switch (nxge_rx_threshold_lo) { 353444961713Sgirish default: 353544961713Sgirish case NXGE_RX_COPY_NONE: 353644961713Sgirish /* Do not do bcopy at all */ 353744961713Sgirish if (rbrp->rbr_use_bcopy) { 353844961713Sgirish rbrp->rbr_use_bcopy = B_FALSE; 353944961713Sgirish } 354044961713Sgirish rbrp->rbr_threshold_lo = rbrp->rbb_max; 354144961713Sgirish break; 354244961713Sgirish 354344961713Sgirish case NXGE_RX_COPY_1: 354444961713Sgirish case NXGE_RX_COPY_2: 354544961713Sgirish case NXGE_RX_COPY_3: 354644961713Sgirish case NXGE_RX_COPY_4: 354744961713Sgirish case NXGE_RX_COPY_5: 354844961713Sgirish case NXGE_RX_COPY_6: 354944961713Sgirish case NXGE_RX_COPY_7: 355044961713Sgirish rbrp->rbr_threshold_lo = 355152ccf843Smisaki rbrp->rbb_max * 355252ccf843Smisaki (nxge_rx_threshold_lo)/NXGE_RX_BCOPY_SCALE; 355344961713Sgirish break; 355444961713Sgirish 355544961713Sgirish case NXGE_RX_COPY_ALL: 355644961713Sgirish rbrp->rbr_threshold_lo = 0; 355744961713Sgirish break; 355844961713Sgirish } 355944961713Sgirish 356044961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 356152ccf843Smisaki "nxge_map_rxdma_channel_cfg_ring: channel %d " 356252ccf843Smisaki "rbb_max %d " 356352ccf843Smisaki "rbrp->rbr_bufsize_type %d " 356452ccf843Smisaki "rbb_threshold_hi %d " 356552ccf843Smisaki "rbb_threshold_lo %d", 356652ccf843Smisaki dma_channel, 356752ccf843Smisaki rbrp->rbb_max, 356852ccf843Smisaki rbrp->rbr_bufsize_type, 356952ccf843Smisaki rbrp->rbr_threshold_hi, 357052ccf843Smisaki rbrp->rbr_threshold_lo)); 357144961713Sgirish 357244961713Sgirish rbrp->page_valid.value = 0; 357344961713Sgirish rbrp->page_mask_1.value = rbrp->page_mask_2.value = 0; 357444961713Sgirish rbrp->page_value_1.value = rbrp->page_value_2.value = 0; 357544961713Sgirish rbrp->page_reloc_1.value = rbrp->page_reloc_2.value = 0; 357644961713Sgirish rbrp->page_hdl.value = 0; 357744961713Sgirish 357844961713Sgirish rbrp->page_valid.bits.ldw.page0 = 1; 357944961713Sgirish rbrp->page_valid.bits.ldw.page1 = 1; 358044961713Sgirish 358144961713Sgirish /* Map in the receive completion ring */ 358244961713Sgirish rcrp = (p_rx_rcr_ring_t) 358352ccf843Smisaki KMEM_ZALLOC(sizeof (rx_rcr_ring_t), KM_SLEEP); 358444961713Sgirish rcrp->rdc = dma_channel; 358544961713Sgirish 358644961713Sgirish nxge_port_rcr_size = nxgep->nxge_port_rcr_size; 358744961713Sgirish rcrp->comp_size = nxge_port_rcr_size; 358844961713Sgirish rcrp->comp_wrap_mask = nxge_port_rcr_size - 1; 358944961713Sgirish 359044961713Sgirish rcrp->max_receive_pkts = nxge_max_rx_pkts; 359144961713Sgirish 359244961713Sgirish dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 359344961713Sgirish nxge_setup_dma_common(dmap, cntl_dmap, rcrp->comp_size, 359452ccf843Smisaki sizeof (rcr_entry_t)); 359544961713Sgirish rcrp->comp_rd_index = 0; 359644961713Sgirish rcrp->comp_wt_index = 0; 359744961713Sgirish rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 359852ccf843Smisaki (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 3599adfcba55Sjoycey #if defined(__i386) 360052ccf843Smisaki rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 360152ccf843Smisaki (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3602adfcba55Sjoycey #else 360352ccf843Smisaki rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 360452ccf843Smisaki (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3605adfcba55Sjoycey #endif 360644961713Sgirish 360744961713Sgirish rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 360852ccf843Smisaki (nxge_port_rcr_size - 1); 360944961713Sgirish rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 361052ccf843Smisaki (nxge_port_rcr_size - 1); 361144961713Sgirish 361244961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 361352ccf843Smisaki "==> nxge_map_rxdma_channel_cfg_ring: " 361452ccf843Smisaki "channel %d " 361552ccf843Smisaki "rbr_vaddrp $%p " 361652ccf843Smisaki "rcr_desc_rd_head_p $%p " 361752ccf843Smisaki "rcr_desc_rd_head_pp $%p " 361852ccf843Smisaki "rcr_desc_rd_last_p $%p " 361952ccf843Smisaki "rcr_desc_rd_last_pp $%p ", 362052ccf843Smisaki dma_channel, 362152ccf843Smisaki rbr_vaddrp, 362252ccf843Smisaki rcrp->rcr_desc_rd_head_p, 362352ccf843Smisaki rcrp->rcr_desc_rd_head_pp, 362452ccf843Smisaki rcrp->rcr_desc_last_p, 362552ccf843Smisaki rcrp->rcr_desc_last_pp)); 362644961713Sgirish 362744961713Sgirish /* 362844961713Sgirish * Zero out buffer block ring descriptors. 362944961713Sgirish */ 363044961713Sgirish bzero((caddr_t)dmap->kaddrp, dmap->alength); 36317b26d9ffSSantwona Behera 36327b26d9ffSSantwona Behera rcrp->intr_timeout = (nxgep->intr_timeout < 36337b26d9ffSSantwona Behera NXGE_RDC_RCR_TIMEOUT_MIN) ? NXGE_RDC_RCR_TIMEOUT_MIN : 36347b26d9ffSSantwona Behera nxgep->intr_timeout; 36357b26d9ffSSantwona Behera 36367b26d9ffSSantwona Behera rcrp->intr_threshold = (nxgep->intr_threshold < 36377b26d9ffSSantwona Behera NXGE_RDC_RCR_THRESHOLD_MIN) ? NXGE_RDC_RCR_THRESHOLD_MIN : 36387b26d9ffSSantwona Behera nxgep->intr_threshold; 36397b26d9ffSSantwona Behera 364044961713Sgirish rcrp->full_hdr_flag = B_FALSE; 3641*4df55fdeSJanie Lu 3642*4df55fdeSJanie Lu rcrp->sw_priv_hdr_len = nxge_rdc_buf_offset; 3643*4df55fdeSJanie Lu 364444961713Sgirish 364544961713Sgirish cfga_p = &(rcrp->rcr_cfga); 364644961713Sgirish cfgb_p = &(rcrp->rcr_cfgb); 364744961713Sgirish cfga_p->value = 0; 364844961713Sgirish cfgb_p->value = 0; 364944961713Sgirish rcrp->rcr_addr = dmap->dma_cookie.dmac_laddress; 365044961713Sgirish cfga_p->value = (rcrp->rcr_addr & 365152ccf843Smisaki (RCRCFIG_A_STADDR_MASK | 365252ccf843Smisaki RCRCFIG_A_STADDR_BASE_MASK)); 365344961713Sgirish 365444961713Sgirish rcfga_p->value |= ((uint64_t)rcrp->comp_size << 365552ccf843Smisaki RCRCFIG_A_LEN_SHIF); 365644961713Sgirish 365744961713Sgirish /* 365844961713Sgirish * Timeout should be set based on the system clock divider. 36597b26d9ffSSantwona Behera * A timeout value of 1 assumes that the 366044961713Sgirish * granularity (1000) is 3 microseconds running at 300MHz. 366144961713Sgirish */ 366214ea4bb7Ssd cfgb_p->bits.ldw.pthres = rcrp->intr_threshold; 366314ea4bb7Ssd cfgb_p->bits.ldw.timeout = rcrp->intr_timeout; 366444961713Sgirish cfgb_p->bits.ldw.entout = 1; 366544961713Sgirish 366644961713Sgirish /* Map in the mailbox */ 366744961713Sgirish mboxp = (p_rx_mbox_t) 366852ccf843Smisaki KMEM_ZALLOC(sizeof (rx_mbox_t), KM_SLEEP); 366944961713Sgirish dmap = (p_nxge_dma_common_t)&mboxp->rx_mbox; 367044961713Sgirish nxge_setup_dma_common(dmap, cntl_dmap, 1, sizeof (rxdma_mailbox_t)); 367144961713Sgirish cfig1_p = (p_rxdma_cfig1_t)&mboxp->rx_cfg1; 367244961713Sgirish cfig2_p = (p_rxdma_cfig2_t)&mboxp->rx_cfg2; 367344961713Sgirish cfig1_p->value = cfig2_p->value = 0; 367444961713Sgirish 367544961713Sgirish mboxp->mbox_addr = dmap->dma_cookie.dmac_laddress; 367644961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 367752ccf843Smisaki "==> nxge_map_rxdma_channel_cfg_ring: " 367852ccf843Smisaki "channel %d cfg1 0x%016llx cfig2 0x%016llx cookie 0x%016llx", 367952ccf843Smisaki dma_channel, cfig1_p->value, cfig2_p->value, 368052ccf843Smisaki mboxp->mbox_addr)); 368144961713Sgirish 368244961713Sgirish dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress >> 32 368352ccf843Smisaki & 0xfff); 368444961713Sgirish cfig1_p->bits.ldw.mbaddr_h = dmaaddrp; 368544961713Sgirish 368644961713Sgirish 368744961713Sgirish dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 0xffffffff); 368844961713Sgirish dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 368952ccf843Smisaki RXDMA_CFIG2_MBADDR_L_MASK); 369044961713Sgirish 369144961713Sgirish cfig2_p->bits.ldw.mbaddr = (dmaaddrp >> RXDMA_CFIG2_MBADDR_L_SHIFT); 369244961713Sgirish 369344961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 369452ccf843Smisaki "==> nxge_map_rxdma_channel_cfg_ring: " 369552ccf843Smisaki "channel %d damaddrp $%p " 369652ccf843Smisaki "cfg1 0x%016llx cfig2 0x%016llx", 369752ccf843Smisaki dma_channel, dmaaddrp, 369852ccf843Smisaki cfig1_p->value, cfig2_p->value)); 369944961713Sgirish 370044961713Sgirish cfig2_p->bits.ldw.full_hdr = rcrp->full_hdr_flag; 3701*4df55fdeSJanie Lu if (nxgep->niu_hw_type == NIU_HW_TYPE_RF) { 3702*4df55fdeSJanie Lu switch (rcrp->sw_priv_hdr_len) { 3703*4df55fdeSJanie Lu case SW_OFFSET_NO_OFFSET: 3704*4df55fdeSJanie Lu case SW_OFFSET_64: 3705*4df55fdeSJanie Lu case SW_OFFSET_128: 3706*4df55fdeSJanie Lu case SW_OFFSET_192: 3707*4df55fdeSJanie Lu cfig2_p->bits.ldw.offset = 3708*4df55fdeSJanie Lu rcrp->sw_priv_hdr_len; 3709*4df55fdeSJanie Lu cfig2_p->bits.ldw.offset256 = 0; 3710*4df55fdeSJanie Lu break; 3711*4df55fdeSJanie Lu case SW_OFFSET_256: 3712*4df55fdeSJanie Lu case SW_OFFSET_320: 3713*4df55fdeSJanie Lu case SW_OFFSET_384: 3714*4df55fdeSJanie Lu case SW_OFFSET_448: 3715*4df55fdeSJanie Lu cfig2_p->bits.ldw.offset = 3716*4df55fdeSJanie Lu rcrp->sw_priv_hdr_len & 0x3; 3717*4df55fdeSJanie Lu cfig2_p->bits.ldw.offset256 = 1; 3718*4df55fdeSJanie Lu break; 3719*4df55fdeSJanie Lu default: 3720*4df55fdeSJanie Lu cfig2_p->bits.ldw.offset = SW_OFFSET_NO_OFFSET; 3721*4df55fdeSJanie Lu cfig2_p->bits.ldw.offset256 = 0; 3722*4df55fdeSJanie Lu } 3723*4df55fdeSJanie Lu } else { 3724*4df55fdeSJanie Lu cfig2_p->bits.ldw.offset = rcrp->sw_priv_hdr_len; 3725*4df55fdeSJanie Lu } 372644961713Sgirish 372744961713Sgirish rbrp->rx_rcr_p = rcrp; 372844961713Sgirish rcrp->rx_rbr_p = rbrp; 372944961713Sgirish *rcr_p = rcrp; 373044961713Sgirish *rx_mbox_p = mboxp; 373144961713Sgirish 373244961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 373352ccf843Smisaki "<== nxge_map_rxdma_channel_cfg_ring status 0x%08x", status)); 373444961713Sgirish 373544961713Sgirish return (status); 373644961713Sgirish } 373744961713Sgirish 373844961713Sgirish /*ARGSUSED*/ 373944961713Sgirish static void 374044961713Sgirish nxge_unmap_rxdma_channel_cfg_ring(p_nxge_t nxgep, 374144961713Sgirish p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 374244961713Sgirish { 374344961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 374452ccf843Smisaki "==> nxge_unmap_rxdma_channel_cfg_ring: channel %d", 374552ccf843Smisaki rcr_p->rdc)); 374644961713Sgirish 374744961713Sgirish KMEM_FREE(rcr_p, sizeof (rx_rcr_ring_t)); 374844961713Sgirish KMEM_FREE(rx_mbox_p, sizeof (rx_mbox_t)); 374944961713Sgirish 375044961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 375152ccf843Smisaki "<== nxge_unmap_rxdma_channel_cfg_ring")); 375244961713Sgirish } 375344961713Sgirish 375444961713Sgirish static nxge_status_t 375544961713Sgirish nxge_map_rxdma_channel_buf_ring(p_nxge_t nxgep, uint16_t channel, 375644961713Sgirish p_nxge_dma_common_t *dma_buf_p, 375744961713Sgirish p_rx_rbr_ring_t *rbr_p, uint32_t num_chunks) 375844961713Sgirish { 375944961713Sgirish p_rx_rbr_ring_t rbrp; 376044961713Sgirish p_nxge_dma_common_t dma_bufp, tmp_bufp; 376144961713Sgirish p_rx_msg_t *rx_msg_ring; 376244961713Sgirish p_rx_msg_t rx_msg_p; 376344961713Sgirish p_mblk_t mblk_p; 376444961713Sgirish 376544961713Sgirish rxring_info_t *ring_info; 376644961713Sgirish nxge_status_t status = NXGE_OK; 376744961713Sgirish int i, j, index; 376844961713Sgirish uint32_t size, bsize, nblocks, nmsgs; 376944961713Sgirish 377044961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 377152ccf843Smisaki "==> nxge_map_rxdma_channel_buf_ring: channel %d", 377252ccf843Smisaki channel)); 377344961713Sgirish 377444961713Sgirish dma_bufp = tmp_bufp = *dma_buf_p; 377544961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 377652ccf843Smisaki " nxge_map_rxdma_channel_buf_ring: channel %d to map %d " 377752ccf843Smisaki "chunks bufp 0x%016llx", 377852ccf843Smisaki channel, num_chunks, dma_bufp)); 377944961713Sgirish 378044961713Sgirish nmsgs = 0; 378144961713Sgirish for (i = 0; i < num_chunks; i++, tmp_bufp++) { 378244961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 378352ccf843Smisaki "==> nxge_map_rxdma_channel_buf_ring: channel %d " 378452ccf843Smisaki "bufp 0x%016llx nblocks %d nmsgs %d", 378552ccf843Smisaki channel, tmp_bufp, tmp_bufp->nblocks, nmsgs)); 378644961713Sgirish nmsgs += tmp_bufp->nblocks; 378744961713Sgirish } 378844961713Sgirish if (!nmsgs) { 378956d930aeSspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 379052ccf843Smisaki "<== nxge_map_rxdma_channel_buf_ring: channel %d " 379152ccf843Smisaki "no msg blocks", 379252ccf843Smisaki channel)); 379344961713Sgirish status = NXGE_ERROR; 379444961713Sgirish goto nxge_map_rxdma_channel_buf_ring_exit; 379544961713Sgirish } 379644961713Sgirish 3797007969e0Stm rbrp = (p_rx_rbr_ring_t)KMEM_ZALLOC(sizeof (*rbrp), KM_SLEEP); 379844961713Sgirish 379944961713Sgirish size = nmsgs * sizeof (p_rx_msg_t); 380044961713Sgirish rx_msg_ring = KMEM_ZALLOC(size, KM_SLEEP); 380144961713Sgirish ring_info = (rxring_info_t *)KMEM_ZALLOC(sizeof (rxring_info_t), 380252ccf843Smisaki KM_SLEEP); 380344961713Sgirish 380444961713Sgirish MUTEX_INIT(&rbrp->lock, NULL, MUTEX_DRIVER, 380552ccf843Smisaki (void *)nxgep->interrupt_cookie); 380644961713Sgirish MUTEX_INIT(&rbrp->post_lock, NULL, MUTEX_DRIVER, 380752ccf843Smisaki (void *)nxgep->interrupt_cookie); 380844961713Sgirish rbrp->rdc = channel; 380944961713Sgirish rbrp->num_blocks = num_chunks; 381044961713Sgirish rbrp->tnblocks = nmsgs; 381144961713Sgirish rbrp->rbb_max = nmsgs; 381244961713Sgirish rbrp->rbr_max_size = nmsgs; 381344961713Sgirish rbrp->rbr_wrap_mask = (rbrp->rbb_max - 1); 381444961713Sgirish 381544961713Sgirish /* 381644961713Sgirish * Buffer sizes suggested by NIU architect. 381744961713Sgirish * 256, 512 and 2K. 381844961713Sgirish */ 381944961713Sgirish 382044961713Sgirish rbrp->pkt_buf_size0 = RBR_BUFSZ0_256B; 382144961713Sgirish rbrp->pkt_buf_size0_bytes = RBR_BUFSZ0_256_BYTES; 382244961713Sgirish rbrp->npi_pkt_buf_size0 = SIZE_256B; 382344961713Sgirish 382444961713Sgirish rbrp->pkt_buf_size1 = RBR_BUFSZ1_1K; 382544961713Sgirish rbrp->pkt_buf_size1_bytes = RBR_BUFSZ1_1K_BYTES; 382644961713Sgirish rbrp->npi_pkt_buf_size1 = SIZE_1KB; 382744961713Sgirish 382844961713Sgirish rbrp->block_size = nxgep->rx_default_block_size; 382944961713Sgirish 383048056c53SMichael Speer if (!nxgep->mac.is_jumbo) { 383144961713Sgirish rbrp->pkt_buf_size2 = RBR_BUFSZ2_2K; 383244961713Sgirish rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_2K_BYTES; 383344961713Sgirish rbrp->npi_pkt_buf_size2 = SIZE_2KB; 383444961713Sgirish } else { 383544961713Sgirish if (rbrp->block_size >= 0x2000) { 383644961713Sgirish rbrp->pkt_buf_size2 = RBR_BUFSZ2_8K; 383744961713Sgirish rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_8K_BYTES; 383844961713Sgirish rbrp->npi_pkt_buf_size2 = SIZE_8KB; 383944961713Sgirish } else { 384044961713Sgirish rbrp->pkt_buf_size2 = RBR_BUFSZ2_4K; 384144961713Sgirish rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_4K_BYTES; 384244961713Sgirish rbrp->npi_pkt_buf_size2 = SIZE_4KB; 384344961713Sgirish } 384444961713Sgirish } 384544961713Sgirish 384644961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 384752ccf843Smisaki "==> nxge_map_rxdma_channel_buf_ring: channel %d " 384852ccf843Smisaki "actual rbr max %d rbb_max %d nmsgs %d " 384952ccf843Smisaki "rbrp->block_size %d default_block_size %d " 385052ccf843Smisaki "(config nxge_rbr_size %d nxge_rbr_spare_size %d)", 385152ccf843Smisaki channel, rbrp->rbr_max_size, rbrp->rbb_max, nmsgs, 385252ccf843Smisaki rbrp->block_size, nxgep->rx_default_block_size, 385352ccf843Smisaki nxge_rbr_size, nxge_rbr_spare_size)); 385444961713Sgirish 385544961713Sgirish /* Map in buffers from the buffer pool. */ 385644961713Sgirish index = 0; 385744961713Sgirish for (i = 0; i < rbrp->num_blocks; i++, dma_bufp++) { 385844961713Sgirish bsize = dma_bufp->block_size; 385944961713Sgirish nblocks = dma_bufp->nblocks; 3860adfcba55Sjoycey #if defined(__i386) 3861adfcba55Sjoycey ring_info->buffer[i].dvma_addr = (uint32_t)dma_bufp->ioaddr_pp; 3862adfcba55Sjoycey #else 386344961713Sgirish ring_info->buffer[i].dvma_addr = (uint64_t)dma_bufp->ioaddr_pp; 3864adfcba55Sjoycey #endif 386544961713Sgirish ring_info->buffer[i].buf_index = i; 386644961713Sgirish ring_info->buffer[i].buf_size = dma_bufp->alength; 386744961713Sgirish ring_info->buffer[i].start_index = index; 3868adfcba55Sjoycey #if defined(__i386) 3869adfcba55Sjoycey ring_info->buffer[i].kaddr = (uint32_t)dma_bufp->kaddrp; 3870adfcba55Sjoycey #else 387144961713Sgirish ring_info->buffer[i].kaddr = (uint64_t)dma_bufp->kaddrp; 3872adfcba55Sjoycey #endif 387344961713Sgirish 387444961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 387552ccf843Smisaki " nxge_map_rxdma_channel_buf_ring: map channel %d " 387652ccf843Smisaki "chunk %d" 387752ccf843Smisaki " nblocks %d chunk_size %x block_size 0x%x " 387852ccf843Smisaki "dma_bufp $%p", channel, i, 387952ccf843Smisaki dma_bufp->nblocks, ring_info->buffer[i].buf_size, bsize, 388052ccf843Smisaki dma_bufp)); 388144961713Sgirish 388244961713Sgirish for (j = 0; j < nblocks; j++) { 388344961713Sgirish if ((rx_msg_p = nxge_allocb(bsize, BPRI_LO, 388452ccf843Smisaki dma_bufp)) == NULL) { 388556d930aeSspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 388652ccf843Smisaki "allocb failed (index %d i %d j %d)", 388752ccf843Smisaki index, i, j)); 388856d930aeSspeer goto nxge_map_rxdma_channel_buf_ring_fail1; 388944961713Sgirish } 389044961713Sgirish rx_msg_ring[index] = rx_msg_p; 389144961713Sgirish rx_msg_p->block_index = index; 389244961713Sgirish rx_msg_p->shifted_addr = (uint32_t) 389352ccf843Smisaki ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress >> 389452ccf843Smisaki RBR_BKADDR_SHIFT)); 389544961713Sgirish 389644961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 389752ccf843Smisaki "index %d j %d rx_msg_p $%p mblk %p", 389852ccf843Smisaki index, j, rx_msg_p, rx_msg_p->rx_mblk_p)); 389944961713Sgirish 390044961713Sgirish mblk_p = rx_msg_p->rx_mblk_p; 390144961713Sgirish mblk_p->b_wptr = mblk_p->b_rptr + bsize; 3902007969e0Stm 3903007969e0Stm rbrp->rbr_ref_cnt++; 390444961713Sgirish index++; 390544961713Sgirish rx_msg_p->buf_dma.dma_channel = channel; 390644961713Sgirish } 3907678453a8Sspeer 3908678453a8Sspeer rbrp->rbr_alloc_type = DDI_MEM_ALLOC; 3909678453a8Sspeer if (dma_bufp->contig_alloc_type) { 3910678453a8Sspeer rbrp->rbr_alloc_type = CONTIG_MEM_ALLOC; 3911678453a8Sspeer } 3912678453a8Sspeer 3913678453a8Sspeer if (dma_bufp->kmem_alloc_type) { 3914678453a8Sspeer rbrp->rbr_alloc_type = KMEM_ALLOC; 3915678453a8Sspeer } 3916678453a8Sspeer 3917678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3918678453a8Sspeer " nxge_map_rxdma_channel_buf_ring: map channel %d " 3919678453a8Sspeer "chunk %d" 3920678453a8Sspeer " nblocks %d chunk_size %x block_size 0x%x " 3921678453a8Sspeer "dma_bufp $%p", 3922678453a8Sspeer channel, i, 3923678453a8Sspeer dma_bufp->nblocks, ring_info->buffer[i].buf_size, bsize, 3924678453a8Sspeer dma_bufp)); 392544961713Sgirish } 392644961713Sgirish if (i < rbrp->num_blocks) { 392744961713Sgirish goto nxge_map_rxdma_channel_buf_ring_fail1; 392844961713Sgirish } 392944961713Sgirish 393044961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 393152ccf843Smisaki "nxge_map_rxdma_channel_buf_ring: done buf init " 393252ccf843Smisaki "channel %d msg block entries %d", 393352ccf843Smisaki channel, index)); 393444961713Sgirish ring_info->block_size_mask = bsize - 1; 393544961713Sgirish rbrp->rx_msg_ring = rx_msg_ring; 393644961713Sgirish rbrp->dma_bufp = dma_buf_p; 393744961713Sgirish rbrp->ring_info = ring_info; 393844961713Sgirish 393944961713Sgirish status = nxge_rxbuf_index_info_init(nxgep, rbrp); 394044961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 394152ccf843Smisaki " nxge_map_rxdma_channel_buf_ring: " 394252ccf843Smisaki "channel %d done buf info init", channel)); 394344961713Sgirish 3944007969e0Stm /* 3945007969e0Stm * Finally, permit nxge_freeb() to call nxge_post_page(). 3946007969e0Stm */ 3947007969e0Stm rbrp->rbr_state = RBR_POSTING; 3948007969e0Stm 394944961713Sgirish *rbr_p = rbrp; 395044961713Sgirish goto nxge_map_rxdma_channel_buf_ring_exit; 395144961713Sgirish 395244961713Sgirish nxge_map_rxdma_channel_buf_ring_fail1: 395344961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 395452ccf843Smisaki " nxge_map_rxdma_channel_buf_ring: failed channel (0x%x)", 395552ccf843Smisaki channel, status)); 395644961713Sgirish 395744961713Sgirish index--; 395844961713Sgirish for (; index >= 0; index--) { 395944961713Sgirish rx_msg_p = rx_msg_ring[index]; 396044961713Sgirish if (rx_msg_p != NULL) { 396114ea4bb7Ssd freeb(rx_msg_p->rx_mblk_p); 396244961713Sgirish rx_msg_ring[index] = NULL; 396344961713Sgirish } 396444961713Sgirish } 396544961713Sgirish nxge_map_rxdma_channel_buf_ring_fail: 396644961713Sgirish MUTEX_DESTROY(&rbrp->post_lock); 396744961713Sgirish MUTEX_DESTROY(&rbrp->lock); 396844961713Sgirish KMEM_FREE(ring_info, sizeof (rxring_info_t)); 396944961713Sgirish KMEM_FREE(rx_msg_ring, size); 397044961713Sgirish KMEM_FREE(rbrp, sizeof (rx_rbr_ring_t)); 397144961713Sgirish 397256d930aeSspeer status = NXGE_ERROR; 397356d930aeSspeer 397444961713Sgirish nxge_map_rxdma_channel_buf_ring_exit: 397544961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 397652ccf843Smisaki "<== nxge_map_rxdma_channel_buf_ring status 0x%08x", status)); 397744961713Sgirish 397844961713Sgirish return (status); 397944961713Sgirish } 398044961713Sgirish 398144961713Sgirish /*ARGSUSED*/ 398244961713Sgirish static void 398344961713Sgirish nxge_unmap_rxdma_channel_buf_ring(p_nxge_t nxgep, 398444961713Sgirish p_rx_rbr_ring_t rbr_p) 398544961713Sgirish { 398644961713Sgirish p_rx_msg_t *rx_msg_ring; 398744961713Sgirish p_rx_msg_t rx_msg_p; 398844961713Sgirish rxring_info_t *ring_info; 398944961713Sgirish int i; 399044961713Sgirish uint32_t size; 399144961713Sgirish #ifdef NXGE_DEBUG 399244961713Sgirish int num_chunks; 399344961713Sgirish #endif 399444961713Sgirish 399544961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 399652ccf843Smisaki "==> nxge_unmap_rxdma_channel_buf_ring")); 399744961713Sgirish if (rbr_p == NULL) { 399844961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 399952ccf843Smisaki "<== nxge_unmap_rxdma_channel_buf_ring: NULL rbrp")); 400044961713Sgirish return; 400144961713Sgirish } 400244961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 400352ccf843Smisaki "==> nxge_unmap_rxdma_channel_buf_ring: channel %d", 400452ccf843Smisaki rbr_p->rdc)); 400544961713Sgirish 400644961713Sgirish rx_msg_ring = rbr_p->rx_msg_ring; 400744961713Sgirish ring_info = rbr_p->ring_info; 400844961713Sgirish 400944961713Sgirish if (rx_msg_ring == NULL || ring_info == NULL) { 401052ccf843Smisaki NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 401152ccf843Smisaki "<== nxge_unmap_rxdma_channel_buf_ring: " 401252ccf843Smisaki "rx_msg_ring $%p ring_info $%p", 401352ccf843Smisaki rx_msg_p, ring_info)); 401444961713Sgirish return; 401544961713Sgirish } 401644961713Sgirish 401744961713Sgirish #ifdef NXGE_DEBUG 401844961713Sgirish num_chunks = rbr_p->num_blocks; 401944961713Sgirish #endif 402044961713Sgirish size = rbr_p->tnblocks * sizeof (p_rx_msg_t); 402144961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 402252ccf843Smisaki " nxge_unmap_rxdma_channel_buf_ring: channel %d chunks %d " 402352ccf843Smisaki "tnblocks %d (max %d) size ptrs %d ", 402452ccf843Smisaki rbr_p->rdc, num_chunks, 402552ccf843Smisaki rbr_p->tnblocks, rbr_p->rbr_max_size, size)); 402644961713Sgirish 402744961713Sgirish for (i = 0; i < rbr_p->tnblocks; i++) { 402844961713Sgirish rx_msg_p = rx_msg_ring[i]; 402944961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 403052ccf843Smisaki " nxge_unmap_rxdma_channel_buf_ring: " 403152ccf843Smisaki "rx_msg_p $%p", 403252ccf843Smisaki rx_msg_p)); 403344961713Sgirish if (rx_msg_p != NULL) { 403414ea4bb7Ssd freeb(rx_msg_p->rx_mblk_p); 403544961713Sgirish rx_msg_ring[i] = NULL; 403644961713Sgirish } 403744961713Sgirish } 403844961713Sgirish 4039007969e0Stm /* 4040007969e0Stm * We no longer may use the mutex <post_lock>. By setting 4041007969e0Stm * <rbr_state> to anything but POSTING, we prevent 4042007969e0Stm * nxge_post_page() from accessing a dead mutex. 4043007969e0Stm */ 4044007969e0Stm rbr_p->rbr_state = RBR_UNMAPPING; 404544961713Sgirish MUTEX_DESTROY(&rbr_p->post_lock); 4046007969e0Stm 404744961713Sgirish MUTEX_DESTROY(&rbr_p->lock); 4048007969e0Stm 4049007969e0Stm if (rbr_p->rbr_ref_cnt == 0) { 4050678453a8Sspeer /* 4051678453a8Sspeer * This is the normal state of affairs. 4052678453a8Sspeer * Need to free the following buffers: 4053678453a8Sspeer * - data buffers 4054678453a8Sspeer * - rx_msg ring 4055678453a8Sspeer * - ring_info 4056678453a8Sspeer * - rbr ring 4057678453a8Sspeer */ 4058678453a8Sspeer NXGE_DEBUG_MSG((nxgep, RX_CTL, 4059678453a8Sspeer "unmap_rxdma_buf_ring: No outstanding - freeing ")); 4060678453a8Sspeer nxge_rxdma_databuf_free(rbr_p); 4061678453a8Sspeer KMEM_FREE(ring_info, sizeof (rxring_info_t)); 4062678453a8Sspeer KMEM_FREE(rx_msg_ring, size); 4063007969e0Stm KMEM_FREE(rbr_p, sizeof (*rbr_p)); 4064007969e0Stm } else { 4065007969e0Stm /* 4066007969e0Stm * Some of our buffers are still being used. 4067007969e0Stm * Therefore, tell nxge_freeb() this ring is 4068007969e0Stm * unmapped, so it may free <rbr_p> for us. 4069007969e0Stm */ 4070007969e0Stm rbr_p->rbr_state = RBR_UNMAPPED; 4071007969e0Stm NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4072007969e0Stm "unmap_rxdma_buf_ring: %d %s outstanding.", 4073007969e0Stm rbr_p->rbr_ref_cnt, 4074007969e0Stm rbr_p->rbr_ref_cnt == 1 ? "msg" : "msgs")); 4075007969e0Stm } 407644961713Sgirish 407744961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 407852ccf843Smisaki "<== nxge_unmap_rxdma_channel_buf_ring")); 407944961713Sgirish } 408044961713Sgirish 4081678453a8Sspeer /* 4082678453a8Sspeer * nxge_rxdma_hw_start_common 4083678453a8Sspeer * 4084678453a8Sspeer * Arguments: 4085678453a8Sspeer * nxgep 4086678453a8Sspeer * 4087678453a8Sspeer * Notes: 4088678453a8Sspeer * 4089678453a8Sspeer * NPI/NXGE function calls: 4090678453a8Sspeer * nxge_init_fzc_rx_common(); 4091678453a8Sspeer * nxge_init_fzc_rxdma_port(); 4092678453a8Sspeer * 4093678453a8Sspeer * Registers accessed: 4094678453a8Sspeer * 4095678453a8Sspeer * Context: 4096678453a8Sspeer * Service domain 4097678453a8Sspeer */ 409844961713Sgirish static nxge_status_t 409944961713Sgirish nxge_rxdma_hw_start_common(p_nxge_t nxgep) 410044961713Sgirish { 410144961713Sgirish nxge_status_t status = NXGE_OK; 410244961713Sgirish 410344961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start_common")); 410444961713Sgirish 410544961713Sgirish /* 410644961713Sgirish * Load the sharable parameters by writing to the 410744961713Sgirish * function zero control registers. These FZC registers 410844961713Sgirish * should be initialized only once for the entire chip. 410944961713Sgirish */ 411044961713Sgirish (void) nxge_init_fzc_rx_common(nxgep); 411144961713Sgirish 411244961713Sgirish /* 411344961713Sgirish * Initialize the RXDMA port specific FZC control configurations. 411444961713Sgirish * These FZC registers are pertaining to each port. 411544961713Sgirish */ 411644961713Sgirish (void) nxge_init_fzc_rxdma_port(nxgep); 411744961713Sgirish 411844961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start_common")); 411944961713Sgirish 412044961713Sgirish return (status); 412144961713Sgirish } 412244961713Sgirish 412344961713Sgirish static nxge_status_t 4124678453a8Sspeer nxge_rxdma_hw_start(p_nxge_t nxgep, int channel) 412544961713Sgirish { 412644961713Sgirish int i, ndmas; 412744961713Sgirish p_rx_rbr_rings_t rx_rbr_rings; 412844961713Sgirish p_rx_rbr_ring_t *rbr_rings; 412944961713Sgirish p_rx_rcr_rings_t rx_rcr_rings; 413044961713Sgirish p_rx_rcr_ring_t *rcr_rings; 413144961713Sgirish p_rx_mbox_areas_t rx_mbox_areas_p; 413244961713Sgirish p_rx_mbox_t *rx_mbox_p; 413344961713Sgirish nxge_status_t status = NXGE_OK; 413444961713Sgirish 413544961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start")); 413644961713Sgirish 413744961713Sgirish rx_rbr_rings = nxgep->rx_rbr_rings; 413844961713Sgirish rx_rcr_rings = nxgep->rx_rcr_rings; 413944961713Sgirish if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 414044961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 414152ccf843Smisaki "<== nxge_rxdma_hw_start: NULL ring pointers")); 414244961713Sgirish return (NXGE_ERROR); 414344961713Sgirish } 414444961713Sgirish ndmas = rx_rbr_rings->ndmas; 414544961713Sgirish if (ndmas == 0) { 414644961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 414752ccf843Smisaki "<== nxge_rxdma_hw_start: no dma channel allocated")); 414844961713Sgirish return (NXGE_ERROR); 414944961713Sgirish } 415044961713Sgirish 415144961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 415252ccf843Smisaki "==> nxge_rxdma_hw_start (ndmas %d)", ndmas)); 415344961713Sgirish 415444961713Sgirish rbr_rings = rx_rbr_rings->rbr_rings; 415544961713Sgirish rcr_rings = rx_rcr_rings->rcr_rings; 415644961713Sgirish rx_mbox_areas_p = nxgep->rx_mbox_areas_p; 415744961713Sgirish if (rx_mbox_areas_p) { 415844961713Sgirish rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 415944961713Sgirish } 416044961713Sgirish 4161678453a8Sspeer i = channel; 4162678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 416352ccf843Smisaki "==> nxge_rxdma_hw_start (ndmas %d) channel %d", 416452ccf843Smisaki ndmas, channel)); 4165678453a8Sspeer status = nxge_rxdma_start_channel(nxgep, channel, 4166678453a8Sspeer (p_rx_rbr_ring_t)rbr_rings[i], 4167678453a8Sspeer (p_rx_rcr_ring_t)rcr_rings[i], 4168678453a8Sspeer (p_rx_mbox_t)rx_mbox_p[i]); 4169678453a8Sspeer if (status != NXGE_OK) { 4170678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4171678453a8Sspeer "==> nxge_rxdma_hw_start: disable " 4172678453a8Sspeer "(status 0x%x channel %d)", status, channel)); 4173678453a8Sspeer return (status); 417444961713Sgirish } 417544961713Sgirish 417644961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start: " 417752ccf843Smisaki "rx_rbr_rings 0x%016llx rings 0x%016llx", 417852ccf843Smisaki rx_rbr_rings, rx_rcr_rings)); 417944961713Sgirish 418044961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 418152ccf843Smisaki "==> nxge_rxdma_hw_start: (status 0x%x)", status)); 418244961713Sgirish 418344961713Sgirish return (status); 418444961713Sgirish } 418544961713Sgirish 418644961713Sgirish static void 4187678453a8Sspeer nxge_rxdma_hw_stop(p_nxge_t nxgep, int channel) 418844961713Sgirish { 418944961713Sgirish p_rx_rbr_rings_t rx_rbr_rings; 419044961713Sgirish p_rx_rcr_rings_t rx_rcr_rings; 419144961713Sgirish 419244961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop")); 419344961713Sgirish 419444961713Sgirish rx_rbr_rings = nxgep->rx_rbr_rings; 419544961713Sgirish rx_rcr_rings = nxgep->rx_rcr_rings; 419644961713Sgirish if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 419744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 419852ccf843Smisaki "<== nxge_rxdma_hw_stop: NULL ring pointers")); 419944961713Sgirish return; 420044961713Sgirish } 420144961713Sgirish 420244961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 420352ccf843Smisaki "==> nxge_rxdma_hw_stop(channel %d)", 420452ccf843Smisaki channel)); 4205678453a8Sspeer (void) nxge_rxdma_stop_channel(nxgep, channel); 420644961713Sgirish 420744961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop: " 420852ccf843Smisaki "rx_rbr_rings 0x%016llx rings 0x%016llx", 420952ccf843Smisaki rx_rbr_rings, rx_rcr_rings)); 421044961713Sgirish 421144961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_rxdma_hw_stop")); 421244961713Sgirish } 421344961713Sgirish 421444961713Sgirish 421544961713Sgirish static nxge_status_t 421644961713Sgirish nxge_rxdma_start_channel(p_nxge_t nxgep, uint16_t channel, 421744961713Sgirish p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p) 421844961713Sgirish 421944961713Sgirish { 422044961713Sgirish npi_handle_t handle; 422144961713Sgirish npi_status_t rs = NPI_SUCCESS; 422244961713Sgirish rx_dma_ctl_stat_t cs; 422344961713Sgirish rx_dma_ent_msk_t ent_mask; 422444961713Sgirish nxge_status_t status = NXGE_OK; 422544961713Sgirish 422644961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel")); 422744961713Sgirish 422844961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 422944961713Sgirish 423044961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "nxge_rxdma_start_channel: " 423144961713Sgirish "npi handle addr $%p acc $%p", 423244961713Sgirish nxgep->npi_handle.regp, nxgep->npi_handle.regh)); 423344961713Sgirish 4234678453a8Sspeer /* Reset RXDMA channel, but not if you're a guest. */ 4235678453a8Sspeer if (!isLDOMguest(nxgep)) { 4236678453a8Sspeer rs = npi_rxdma_cfg_rdc_reset(handle, channel); 4237678453a8Sspeer if (rs != NPI_SUCCESS) { 4238678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4239678453a8Sspeer "==> nxge_init_fzc_rdc: " 4240678453a8Sspeer "npi_rxdma_cfg_rdc_reset(%d) returned 0x%08x", 4241678453a8Sspeer channel, rs)); 4242678453a8Sspeer return (NXGE_ERROR | rs); 4243678453a8Sspeer } 4244678453a8Sspeer 4245678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4246678453a8Sspeer "==> nxge_rxdma_start_channel: reset done: channel %d", 4247678453a8Sspeer channel)); 424844961713Sgirish } 424944961713Sgirish 4250678453a8Sspeer #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 4251678453a8Sspeer if (isLDOMguest(nxgep)) 4252678453a8Sspeer (void) nxge_rdc_lp_conf(nxgep, channel); 4253678453a8Sspeer #endif 425444961713Sgirish 425544961713Sgirish /* 425644961713Sgirish * Initialize the RXDMA channel specific FZC control 425744961713Sgirish * configurations. These FZC registers are pertaining 425844961713Sgirish * to each RX channel (logical pages). 425944961713Sgirish */ 4260678453a8Sspeer if (!isLDOMguest(nxgep)) { 4261678453a8Sspeer status = nxge_init_fzc_rxdma_channel(nxgep, channel); 4262678453a8Sspeer if (status != NXGE_OK) { 4263678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4264678453a8Sspeer "==> nxge_rxdma_start_channel: " 4265678453a8Sspeer "init fzc rxdma failed (0x%08x channel %d)", 4266678453a8Sspeer status, channel)); 4267678453a8Sspeer return (status); 4268678453a8Sspeer } 426944961713Sgirish 4270678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4271678453a8Sspeer "==> nxge_rxdma_start_channel: fzc done")); 4272678453a8Sspeer } 427344961713Sgirish 427444961713Sgirish /* Set up the interrupt event masks. */ 427544961713Sgirish ent_mask.value = 0; 427644961713Sgirish ent_mask.value |= RX_DMA_ENT_MSK_RBREMPTY_MASK; 427744961713Sgirish rs = npi_rxdma_event_mask(handle, OP_SET, channel, 4278678453a8Sspeer &ent_mask); 427944961713Sgirish if (rs != NPI_SUCCESS) { 428044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 428144961713Sgirish "==> nxge_rxdma_start_channel: " 4282678453a8Sspeer "init rxdma event masks failed " 4283678453a8Sspeer "(0x%08x channel %d)", 428444961713Sgirish status, channel)); 428544961713Sgirish return (NXGE_ERROR | rs); 428644961713Sgirish } 428744961713Sgirish 4288678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4289678453a8Sspeer "==> nxge_rxdma_start_channel: " 429044961713Sgirish "event done: channel %d (mask 0x%016llx)", 429144961713Sgirish channel, ent_mask.value)); 429244961713Sgirish 429344961713Sgirish /* Initialize the receive DMA control and status register */ 429444961713Sgirish cs.value = 0; 429544961713Sgirish cs.bits.hdw.mex = 1; 429644961713Sgirish cs.bits.hdw.rcrthres = 1; 429744961713Sgirish cs.bits.hdw.rcrto = 1; 429844961713Sgirish cs.bits.hdw.rbr_empty = 1; 429944961713Sgirish status = nxge_init_rxdma_channel_cntl_stat(nxgep, channel, &cs); 430044961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 430144961713Sgirish "channel %d rx_dma_cntl_stat 0x%0016llx", channel, cs.value)); 430244961713Sgirish if (status != NXGE_OK) { 430344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 430444961713Sgirish "==> nxge_rxdma_start_channel: " 430544961713Sgirish "init rxdma control register failed (0x%08x channel %d", 430644961713Sgirish status, channel)); 430744961713Sgirish return (status); 430844961713Sgirish } 430944961713Sgirish 431044961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 431144961713Sgirish "control done - channel %d cs 0x%016llx", channel, cs.value)); 431244961713Sgirish 431344961713Sgirish /* 431444961713Sgirish * Load RXDMA descriptors, buffers, mailbox, 431544961713Sgirish * initialise the receive DMA channels and 431644961713Sgirish * enable each DMA channel. 431744961713Sgirish */ 431844961713Sgirish status = nxge_enable_rxdma_channel(nxgep, 4319678453a8Sspeer channel, rbr_p, rcr_p, mbox_p); 432044961713Sgirish 432144961713Sgirish if (status != NXGE_OK) { 432244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4323678453a8Sspeer " nxge_rxdma_start_channel: " 4324678453a8Sspeer " enable rxdma failed (0x%08x channel %d)", 4325678453a8Sspeer status, channel)); 432644961713Sgirish return (status); 432744961713Sgirish } 432844961713Sgirish 4329678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4330678453a8Sspeer "==> nxge_rxdma_start_channel: enabled channel %d")); 4331678453a8Sspeer 4332678453a8Sspeer if (isLDOMguest(nxgep)) { 4333678453a8Sspeer /* Add interrupt handler for this channel. */ 4334ef523517SMichael Speer status = nxge_hio_intr_add(nxgep, VP_BOUND_RX, channel); 4335ef523517SMichael Speer if (status != NXGE_OK) { 4336678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4337678453a8Sspeer " nxge_rxdma_start_channel: " 4338678453a8Sspeer " nxge_hio_intr_add failed (0x%08x channel %d)", 4339ef523517SMichael Speer status, channel)); 4340ef523517SMichael Speer return (status); 4341678453a8Sspeer } 4342678453a8Sspeer } 4343678453a8Sspeer 434444961713Sgirish ent_mask.value = 0; 434544961713Sgirish ent_mask.value |= (RX_DMA_ENT_MSK_WRED_DROP_MASK | 434644961713Sgirish RX_DMA_ENT_MSK_PTDROP_PKT_MASK); 434744961713Sgirish rs = npi_rxdma_event_mask(handle, OP_SET, channel, 434844961713Sgirish &ent_mask); 434944961713Sgirish if (rs != NPI_SUCCESS) { 435044961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 435144961713Sgirish "==> nxge_rxdma_start_channel: " 435244961713Sgirish "init rxdma event masks failed (0x%08x channel %d)", 435344961713Sgirish status, channel)); 435444961713Sgirish return (NXGE_ERROR | rs); 435544961713Sgirish } 435644961713Sgirish 435744961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 435844961713Sgirish "control done - channel %d cs 0x%016llx", channel, cs.value)); 435944961713Sgirish 436044961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_rxdma_start_channel")); 436144961713Sgirish 436244961713Sgirish return (NXGE_OK); 436344961713Sgirish } 436444961713Sgirish 436544961713Sgirish static nxge_status_t 436644961713Sgirish nxge_rxdma_stop_channel(p_nxge_t nxgep, uint16_t channel) 436744961713Sgirish { 436844961713Sgirish npi_handle_t handle; 436944961713Sgirish npi_status_t rs = NPI_SUCCESS; 437044961713Sgirish rx_dma_ctl_stat_t cs; 437144961713Sgirish rx_dma_ent_msk_t ent_mask; 437244961713Sgirish nxge_status_t status = NXGE_OK; 437344961713Sgirish 437444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_channel")); 437544961713Sgirish 437644961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 437744961713Sgirish 437844961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "nxge_rxdma_stop_channel: " 437952ccf843Smisaki "npi handle addr $%p acc $%p", 438052ccf843Smisaki nxgep->npi_handle.regp, nxgep->npi_handle.regh)); 438144961713Sgirish 4382330cd344SMichael Speer if (!isLDOMguest(nxgep)) { 4383330cd344SMichael Speer /* 4384330cd344SMichael Speer * Stop RxMAC = A.9.2.6 4385330cd344SMichael Speer */ 4386330cd344SMichael Speer if (nxge_rx_mac_disable(nxgep) != NXGE_OK) { 4387330cd344SMichael Speer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4388330cd344SMichael Speer "nxge_rxdma_stop_channel: " 4389330cd344SMichael Speer "Failed to disable RxMAC")); 4390330cd344SMichael Speer } 4391330cd344SMichael Speer 4392330cd344SMichael Speer /* 4393330cd344SMichael Speer * Drain IPP Port = A.9.3.6 4394330cd344SMichael Speer */ 4395330cd344SMichael Speer (void) nxge_ipp_drain(nxgep); 4396330cd344SMichael Speer } 4397330cd344SMichael Speer 439844961713Sgirish /* Reset RXDMA channel */ 439944961713Sgirish rs = npi_rxdma_cfg_rdc_reset(handle, channel); 440044961713Sgirish if (rs != NPI_SUCCESS) { 440144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 440252ccf843Smisaki " nxge_rxdma_stop_channel: " 440352ccf843Smisaki " reset rxdma failed (0x%08x channel %d)", 440452ccf843Smisaki rs, channel)); 440544961713Sgirish return (NXGE_ERROR | rs); 440644961713Sgirish } 440744961713Sgirish 440844961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 440952ccf843Smisaki "==> nxge_rxdma_stop_channel: reset done")); 441044961713Sgirish 441144961713Sgirish /* Set up the interrupt event masks. */ 441244961713Sgirish ent_mask.value = RX_DMA_ENT_MSK_ALL; 441344961713Sgirish rs = npi_rxdma_event_mask(handle, OP_SET, channel, 441452ccf843Smisaki &ent_mask); 441544961713Sgirish if (rs != NPI_SUCCESS) { 441644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 441752ccf843Smisaki "==> nxge_rxdma_stop_channel: " 441852ccf843Smisaki "set rxdma event masks failed (0x%08x channel %d)", 441952ccf843Smisaki rs, channel)); 442044961713Sgirish return (NXGE_ERROR | rs); 442144961713Sgirish } 442244961713Sgirish 442344961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 442452ccf843Smisaki "==> nxge_rxdma_stop_channel: event done")); 442544961713Sgirish 4426330cd344SMichael Speer /* 4427330cd344SMichael Speer * Initialize the receive DMA control and status register 4428330cd344SMichael Speer */ 442944961713Sgirish cs.value = 0; 4430330cd344SMichael Speer status = nxge_init_rxdma_channel_cntl_stat(nxgep, channel, &cs); 443144961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_channel: control " 443252ccf843Smisaki " to default (all 0s) 0x%08x", cs.value)); 443344961713Sgirish if (status != NXGE_OK) { 443444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 443552ccf843Smisaki " nxge_rxdma_stop_channel: init rxdma" 443652ccf843Smisaki " control register failed (0x%08x channel %d", 443752ccf843Smisaki status, channel)); 443844961713Sgirish return (status); 443944961713Sgirish } 444044961713Sgirish 444144961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 444252ccf843Smisaki "==> nxge_rxdma_stop_channel: control done")); 444344961713Sgirish 4444330cd344SMichael Speer /* 4445330cd344SMichael Speer * Make sure channel is disabled. 4446330cd344SMichael Speer */ 444744961713Sgirish status = nxge_disable_rxdma_channel(nxgep, channel); 4448da14cebeSEric Cheng 444944961713Sgirish if (status != NXGE_OK) { 445044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 445152ccf843Smisaki " nxge_rxdma_stop_channel: " 445252ccf843Smisaki " init enable rxdma failed (0x%08x channel %d)", 445352ccf843Smisaki status, channel)); 445444961713Sgirish return (status); 445544961713Sgirish } 445644961713Sgirish 4457330cd344SMichael Speer if (!isLDOMguest(nxgep)) { 4458330cd344SMichael Speer /* 4459330cd344SMichael Speer * Enable RxMAC = A.9.2.10 4460330cd344SMichael Speer */ 4461330cd344SMichael Speer if (nxge_rx_mac_enable(nxgep) != NXGE_OK) { 4462330cd344SMichael Speer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4463330cd344SMichael Speer "nxge_rxdma_stop_channel: Rx MAC still disabled")); 4464330cd344SMichael Speer } 4465330cd344SMichael Speer } 4466330cd344SMichael Speer 446744961713Sgirish NXGE_DEBUG_MSG((nxgep, 446852ccf843Smisaki RX_CTL, "==> nxge_rxdma_stop_channel: disable done")); 446944961713Sgirish 447044961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_stop_channel")); 447144961713Sgirish 447244961713Sgirish return (NXGE_OK); 447344961713Sgirish } 447444961713Sgirish 447544961713Sgirish nxge_status_t 447644961713Sgirish nxge_rxdma_handle_sys_errors(p_nxge_t nxgep) 447744961713Sgirish { 447844961713Sgirish npi_handle_t handle; 447944961713Sgirish p_nxge_rdc_sys_stats_t statsp; 448044961713Sgirish rx_ctl_dat_fifo_stat_t stat; 448144961713Sgirish uint32_t zcp_err_status; 448244961713Sgirish uint32_t ipp_err_status; 448344961713Sgirish nxge_status_t status = NXGE_OK; 448444961713Sgirish npi_status_t rs = NPI_SUCCESS; 448544961713Sgirish boolean_t my_err = B_FALSE; 448644961713Sgirish 448744961713Sgirish handle = nxgep->npi_handle; 448844961713Sgirish statsp = (p_nxge_rdc_sys_stats_t)&nxgep->statsp->rdc_sys_stats; 448944961713Sgirish 449044961713Sgirish rs = npi_rxdma_rxctl_fifo_error_intr_get(handle, &stat); 449144961713Sgirish 449244961713Sgirish if (rs != NPI_SUCCESS) 449344961713Sgirish return (NXGE_ERROR | rs); 449444961713Sgirish 449544961713Sgirish if (stat.bits.ldw.id_mismatch) { 449644961713Sgirish statsp->id_mismatch++; 449744961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, nxgep->mac.portnum, NULL, 449852ccf843Smisaki NXGE_FM_EREPORT_RDMC_ID_MISMATCH); 449944961713Sgirish /* Global fatal error encountered */ 450044961713Sgirish } 450144961713Sgirish 450244961713Sgirish if ((stat.bits.ldw.zcp_eop_err) || (stat.bits.ldw.ipp_eop_err)) { 450344961713Sgirish switch (nxgep->mac.portnum) { 450444961713Sgirish case 0: 450544961713Sgirish if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT0) || 450652ccf843Smisaki (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT0)) { 450744961713Sgirish my_err = B_TRUE; 450844961713Sgirish zcp_err_status = stat.bits.ldw.zcp_eop_err; 450944961713Sgirish ipp_err_status = stat.bits.ldw.ipp_eop_err; 451044961713Sgirish } 451144961713Sgirish break; 451244961713Sgirish case 1: 451344961713Sgirish if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT1) || 451452ccf843Smisaki (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT1)) { 451544961713Sgirish my_err = B_TRUE; 451644961713Sgirish zcp_err_status = stat.bits.ldw.zcp_eop_err; 451744961713Sgirish ipp_err_status = stat.bits.ldw.ipp_eop_err; 451844961713Sgirish } 451944961713Sgirish break; 452044961713Sgirish case 2: 452144961713Sgirish if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT2) || 452252ccf843Smisaki (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT2)) { 452344961713Sgirish my_err = B_TRUE; 452444961713Sgirish zcp_err_status = stat.bits.ldw.zcp_eop_err; 452544961713Sgirish ipp_err_status = stat.bits.ldw.ipp_eop_err; 452644961713Sgirish } 452744961713Sgirish break; 452844961713Sgirish case 3: 452944961713Sgirish if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT3) || 453052ccf843Smisaki (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT3)) { 453144961713Sgirish my_err = B_TRUE; 453244961713Sgirish zcp_err_status = stat.bits.ldw.zcp_eop_err; 453344961713Sgirish ipp_err_status = stat.bits.ldw.ipp_eop_err; 453444961713Sgirish } 453544961713Sgirish break; 453644961713Sgirish default: 453744961713Sgirish return (NXGE_ERROR); 453844961713Sgirish } 453944961713Sgirish } 454044961713Sgirish 454144961713Sgirish if (my_err) { 454244961713Sgirish status = nxge_rxdma_handle_port_errors(nxgep, ipp_err_status, 454352ccf843Smisaki zcp_err_status); 454444961713Sgirish if (status != NXGE_OK) 454544961713Sgirish return (status); 454644961713Sgirish } 454744961713Sgirish 454844961713Sgirish return (NXGE_OK); 454944961713Sgirish } 455044961713Sgirish 455144961713Sgirish static nxge_status_t 455244961713Sgirish nxge_rxdma_handle_port_errors(p_nxge_t nxgep, uint32_t ipp_status, 455344961713Sgirish uint32_t zcp_status) 455444961713Sgirish { 455544961713Sgirish boolean_t rxport_fatal = B_FALSE; 455644961713Sgirish p_nxge_rdc_sys_stats_t statsp; 455744961713Sgirish nxge_status_t status = NXGE_OK; 455844961713Sgirish uint8_t portn; 455944961713Sgirish 456044961713Sgirish portn = nxgep->mac.portnum; 456144961713Sgirish statsp = (p_nxge_rdc_sys_stats_t)&nxgep->statsp->rdc_sys_stats; 456244961713Sgirish 456344961713Sgirish if (ipp_status & (0x1 << portn)) { 456444961713Sgirish statsp->ipp_eop_err++; 456544961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 456652ccf843Smisaki NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR); 456744961713Sgirish rxport_fatal = B_TRUE; 456844961713Sgirish } 456944961713Sgirish 457044961713Sgirish if (zcp_status & (0x1 << portn)) { 457144961713Sgirish statsp->zcp_eop_err++; 457244961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 457352ccf843Smisaki NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR); 457444961713Sgirish rxport_fatal = B_TRUE; 457544961713Sgirish } 457644961713Sgirish 457744961713Sgirish if (rxport_fatal) { 457844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 457952ccf843Smisaki " nxge_rxdma_handle_port_error: " 458052ccf843Smisaki " fatal error on Port #%d\n", 458152ccf843Smisaki portn)); 458244961713Sgirish status = nxge_rx_port_fatal_err_recover(nxgep); 458344961713Sgirish if (status == NXGE_OK) { 458444961713Sgirish FM_SERVICE_RESTORED(nxgep); 458544961713Sgirish } 458644961713Sgirish } 458744961713Sgirish 458844961713Sgirish return (status); 458944961713Sgirish } 459044961713Sgirish 459144961713Sgirish static nxge_status_t 459244961713Sgirish nxge_rxdma_fatal_err_recover(p_nxge_t nxgep, uint16_t channel) 459344961713Sgirish { 459444961713Sgirish npi_handle_t handle; 459544961713Sgirish npi_status_t rs = NPI_SUCCESS; 459644961713Sgirish nxge_status_t status = NXGE_OK; 459744961713Sgirish p_rx_rbr_ring_t rbrp; 459844961713Sgirish p_rx_rcr_ring_t rcrp; 459944961713Sgirish p_rx_mbox_t mboxp; 460044961713Sgirish rx_dma_ent_msk_t ent_mask; 460144961713Sgirish p_nxge_dma_common_t dmap; 460244961713Sgirish uint32_t ref_cnt; 460344961713Sgirish p_rx_msg_t rx_msg_p; 460444961713Sgirish int i; 460544961713Sgirish uint32_t nxge_port_rcr_size; 460644961713Sgirish 460744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_fatal_err_recover")); 460844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 460952ccf843Smisaki "Recovering from RxDMAChannel#%d error...", channel)); 461044961713Sgirish 461144961713Sgirish /* 461244961713Sgirish * Stop the dma channel waits for the stop done. 461344961713Sgirish * If the stop done bit is not set, then create 461444961713Sgirish * an error. 461544961713Sgirish */ 461644961713Sgirish 461744961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 461844961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "Rx DMA stop...")); 461944961713Sgirish 46203587e8e2SMichael Speer rbrp = (p_rx_rbr_ring_t)nxgep->rx_rbr_rings->rbr_rings[channel]; 46213587e8e2SMichael Speer rcrp = (p_rx_rcr_ring_t)nxgep->rx_rcr_rings->rcr_rings[channel]; 462244961713Sgirish 462344961713Sgirish MUTEX_ENTER(&rbrp->lock); 462444961713Sgirish MUTEX_ENTER(&rbrp->post_lock); 462544961713Sgirish 462644961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxDMA channel...")); 462744961713Sgirish 462844961713Sgirish rs = npi_rxdma_cfg_rdc_disable(handle, channel); 462944961713Sgirish if (rs != NPI_SUCCESS) { 463044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 463152ccf843Smisaki "nxge_disable_rxdma_channel:failed")); 463244961713Sgirish goto fail; 463344961713Sgirish } 463444961713Sgirish 463544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxDMA interrupt...")); 463644961713Sgirish 463744961713Sgirish /* Disable interrupt */ 463844961713Sgirish ent_mask.value = RX_DMA_ENT_MSK_ALL; 463944961713Sgirish rs = npi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 464044961713Sgirish if (rs != NPI_SUCCESS) { 464144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 464252ccf843Smisaki "nxge_rxdma_stop_channel: " 464352ccf843Smisaki "set rxdma event masks failed (channel %d)", 464452ccf843Smisaki channel)); 464544961713Sgirish } 464644961713Sgirish 464744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "RxDMA channel reset...")); 464844961713Sgirish 464944961713Sgirish /* Reset RXDMA channel */ 465044961713Sgirish rs = npi_rxdma_cfg_rdc_reset(handle, channel); 465144961713Sgirish if (rs != NPI_SUCCESS) { 465244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 465352ccf843Smisaki "nxge_rxdma_fatal_err_recover: " 465452ccf843Smisaki " reset rxdma failed (channel %d)", channel)); 465544961713Sgirish goto fail; 465644961713Sgirish } 465744961713Sgirish 465844961713Sgirish nxge_port_rcr_size = nxgep->nxge_port_rcr_size; 465944961713Sgirish 46603587e8e2SMichael Speer mboxp = (p_rx_mbox_t)nxgep->rx_mbox_areas_p->rxmbox_areas[channel]; 466144961713Sgirish 466244961713Sgirish rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 466344961713Sgirish rbrp->rbr_rd_index = 0; 466444961713Sgirish 466544961713Sgirish rcrp->comp_rd_index = 0; 466644961713Sgirish rcrp->comp_wt_index = 0; 466744961713Sgirish rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 466852ccf843Smisaki (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 4669adfcba55Sjoycey #if defined(__i386) 467052ccf843Smisaki rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 467152ccf843Smisaki (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 4672adfcba55Sjoycey #else 467352ccf843Smisaki rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 467452ccf843Smisaki (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 4675adfcba55Sjoycey #endif 467644961713Sgirish 467744961713Sgirish rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 467852ccf843Smisaki (nxge_port_rcr_size - 1); 467944961713Sgirish rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 468052ccf843Smisaki (nxge_port_rcr_size - 1); 468144961713Sgirish 468244961713Sgirish dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 468344961713Sgirish bzero((caddr_t)dmap->kaddrp, dmap->alength); 468444961713Sgirish 468544961713Sgirish cmn_err(CE_NOTE, "!rbr entries = %d\n", rbrp->rbr_max_size); 468644961713Sgirish 468744961713Sgirish for (i = 0; i < rbrp->rbr_max_size; i++) { 468844961713Sgirish rx_msg_p = rbrp->rx_msg_ring[i]; 468944961713Sgirish ref_cnt = rx_msg_p->ref_cnt; 469044961713Sgirish if (ref_cnt != 1) { 4691a3c5bd6dSspeer if (rx_msg_p->cur_usage_cnt != 469252ccf843Smisaki rx_msg_p->max_usage_cnt) { 469344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 469452ccf843Smisaki "buf[%d]: cur_usage_cnt = %d " 469552ccf843Smisaki "max_usage_cnt = %d\n", i, 469652ccf843Smisaki rx_msg_p->cur_usage_cnt, 469752ccf843Smisaki rx_msg_p->max_usage_cnt)); 4698a3c5bd6dSspeer } else { 4699a3c5bd6dSspeer /* Buffer can be re-posted */ 4700a3c5bd6dSspeer rx_msg_p->free = B_TRUE; 4701a3c5bd6dSspeer rx_msg_p->cur_usage_cnt = 0; 4702a3c5bd6dSspeer rx_msg_p->max_usage_cnt = 0xbaddcafe; 4703a3c5bd6dSspeer rx_msg_p->pkt_buf_size = 0; 4704a3c5bd6dSspeer } 470544961713Sgirish } 470644961713Sgirish } 470744961713Sgirish 470844961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "RxDMA channel re-start...")); 470944961713Sgirish 471044961713Sgirish status = nxge_rxdma_start_channel(nxgep, channel, rbrp, rcrp, mboxp); 471144961713Sgirish if (status != NXGE_OK) { 471244961713Sgirish goto fail; 471344961713Sgirish } 471444961713Sgirish 471544961713Sgirish MUTEX_EXIT(&rbrp->post_lock); 471644961713Sgirish MUTEX_EXIT(&rbrp->lock); 471744961713Sgirish 471844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 471952ccf843Smisaki "Recovery Successful, RxDMAChannel#%d Restored", 472052ccf843Smisaki channel)); 472144961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fatal_err_recover")); 472244961713Sgirish return (NXGE_OK); 4723ef523517SMichael Speer 472444961713Sgirish fail: 472544961713Sgirish MUTEX_EXIT(&rbrp->post_lock); 472644961713Sgirish MUTEX_EXIT(&rbrp->lock); 472744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Recovery failed")); 472844961713Sgirish return (NXGE_ERROR | rs); 472944961713Sgirish } 473044961713Sgirish 473144961713Sgirish nxge_status_t 473244961713Sgirish nxge_rx_port_fatal_err_recover(p_nxge_t nxgep) 473344961713Sgirish { 4734678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set; 4735678453a8Sspeer nxge_status_t status = NXGE_OK; 4736ef523517SMichael Speer p_rx_rcr_ring_t rcrp; 4737678453a8Sspeer int rdc; 473844961713Sgirish 473944961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_port_fatal_err_recover")); 474044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 474152ccf843Smisaki "Recovering from RxPort error...")); 4742678453a8Sspeer NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disabling RxMAC...\n")); 474344961713Sgirish 474444961713Sgirish if (nxge_rx_mac_disable(nxgep) != NXGE_OK) 474544961713Sgirish goto fail; 474644961713Sgirish 474744961713Sgirish NXGE_DELAY(1000); 474844961713Sgirish 4749678453a8Sspeer NXGE_DEBUG_MSG((nxgep, RX_CTL, "Stopping all RxDMA channels...")); 475044961713Sgirish 4751678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 4752678453a8Sspeer if ((1 << rdc) & set->owned.map) { 4753ef523517SMichael Speer rcrp = nxgep->rx_rcr_rings->rcr_rings[rdc]; 4754ef523517SMichael Speer if (rcrp != NULL) { 4755ef523517SMichael Speer MUTEX_ENTER(&rcrp->lock); 4756ef523517SMichael Speer if (nxge_rxdma_fatal_err_recover(nxgep, 4757ef523517SMichael Speer rdc) != NXGE_OK) { 4758ef523517SMichael Speer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4759ef523517SMichael Speer "Could not recover " 4760ef523517SMichael Speer "channel %d", rdc)); 4761ef523517SMichael Speer } 4762ef523517SMichael Speer MUTEX_EXIT(&rcrp->lock); 4763678453a8Sspeer } 476444961713Sgirish } 476544961713Sgirish } 476644961713Sgirish 4767678453a8Sspeer NXGE_DEBUG_MSG((nxgep, RX_CTL, "Resetting IPP...")); 476844961713Sgirish 476944961713Sgirish /* Reset IPP */ 477044961713Sgirish if (nxge_ipp_reset(nxgep) != NXGE_OK) { 477144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 477252ccf843Smisaki "nxge_rx_port_fatal_err_recover: " 477352ccf843Smisaki "Failed to reset IPP")); 477444961713Sgirish goto fail; 477544961713Sgirish } 477644961713Sgirish 477744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "Reset RxMAC...")); 477844961713Sgirish 477944961713Sgirish /* Reset RxMAC */ 478044961713Sgirish if (nxge_rx_mac_reset(nxgep) != NXGE_OK) { 478144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 478252ccf843Smisaki "nxge_rx_port_fatal_err_recover: " 478352ccf843Smisaki "Failed to reset RxMAC")); 478444961713Sgirish goto fail; 478544961713Sgirish } 478644961713Sgirish 478744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-initialize IPP...")); 478844961713Sgirish 478944961713Sgirish /* Re-Initialize IPP */ 479044961713Sgirish if (nxge_ipp_init(nxgep) != NXGE_OK) { 479144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 479252ccf843Smisaki "nxge_rx_port_fatal_err_recover: " 479352ccf843Smisaki "Failed to init IPP")); 479444961713Sgirish goto fail; 479544961713Sgirish } 479644961713Sgirish 479744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-initialize RxMAC...")); 479844961713Sgirish 479944961713Sgirish /* Re-Initialize RxMAC */ 480044961713Sgirish if ((status = nxge_rx_mac_init(nxgep)) != NXGE_OK) { 480144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 480252ccf843Smisaki "nxge_rx_port_fatal_err_recover: " 480352ccf843Smisaki "Failed to reset RxMAC")); 480444961713Sgirish goto fail; 480544961713Sgirish } 480644961713Sgirish 480744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-enable RxMAC...")); 480844961713Sgirish 480944961713Sgirish /* Re-enable RxMAC */ 481044961713Sgirish if ((status = nxge_rx_mac_enable(nxgep)) != NXGE_OK) { 481144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 481252ccf843Smisaki "nxge_rx_port_fatal_err_recover: " 481352ccf843Smisaki "Failed to enable RxMAC")); 481444961713Sgirish goto fail; 481544961713Sgirish } 481644961713Sgirish 481744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 481852ccf843Smisaki "Recovery Successful, RxPort Restored")); 481944961713Sgirish 482044961713Sgirish return (NXGE_OK); 482144961713Sgirish fail: 482244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Recovery failed")); 482344961713Sgirish return (status); 482444961713Sgirish } 482544961713Sgirish 482644961713Sgirish void 482744961713Sgirish nxge_rxdma_inject_err(p_nxge_t nxgep, uint32_t err_id, uint8_t chan) 482844961713Sgirish { 482944961713Sgirish rx_dma_ctl_stat_t cs; 483044961713Sgirish rx_ctl_dat_fifo_stat_t cdfs; 483144961713Sgirish 483244961713Sgirish switch (err_id) { 483344961713Sgirish case NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR: 483444961713Sgirish case NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR: 483544961713Sgirish case NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR: 483644961713Sgirish case NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR: 483744961713Sgirish case NXGE_FM_EREPORT_RDMC_RBR_TMOUT: 483844961713Sgirish case NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR: 483944961713Sgirish case NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS: 484044961713Sgirish case NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR: 484144961713Sgirish case NXGE_FM_EREPORT_RDMC_RCRINCON: 484244961713Sgirish case NXGE_FM_EREPORT_RDMC_RCRFULL: 484344961713Sgirish case NXGE_FM_EREPORT_RDMC_RBRFULL: 484444961713Sgirish case NXGE_FM_EREPORT_RDMC_RBRLOGPAGE: 484544961713Sgirish case NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE: 484644961713Sgirish case NXGE_FM_EREPORT_RDMC_CONFIG_ERR: 484744961713Sgirish RXDMA_REG_READ64(nxgep->npi_handle, RX_DMA_CTL_STAT_DBG_REG, 484852ccf843Smisaki chan, &cs.value); 484944961713Sgirish if (err_id == NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR) 485044961713Sgirish cs.bits.hdw.rcr_ack_err = 1; 485144961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR) 485244961713Sgirish cs.bits.hdw.dc_fifo_err = 1; 485344961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR) 485444961713Sgirish cs.bits.hdw.rcr_sha_par = 1; 485544961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR) 485644961713Sgirish cs.bits.hdw.rbr_pre_par = 1; 485744961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_RBR_TMOUT) 485844961713Sgirish cs.bits.hdw.rbr_tmout = 1; 485944961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR) 486044961713Sgirish cs.bits.hdw.rsp_cnt_err = 1; 486144961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS) 486244961713Sgirish cs.bits.hdw.byte_en_bus = 1; 486344961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR) 486444961713Sgirish cs.bits.hdw.rsp_dat_err = 1; 486544961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_CONFIG_ERR) 486644961713Sgirish cs.bits.hdw.config_err = 1; 486744961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_RCRINCON) 486844961713Sgirish cs.bits.hdw.rcrincon = 1; 486944961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_RCRFULL) 487044961713Sgirish cs.bits.hdw.rcrfull = 1; 487144961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_RBRFULL) 487244961713Sgirish cs.bits.hdw.rbrfull = 1; 487344961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_RBRLOGPAGE) 487444961713Sgirish cs.bits.hdw.rbrlogpage = 1; 487544961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE) 487644961713Sgirish cs.bits.hdw.cfiglogpage = 1; 4877adfcba55Sjoycey #if defined(__i386) 4878adfcba55Sjoycey cmn_err(CE_NOTE, "!Write 0x%llx to RX_DMA_CTL_STAT_DBG_REG\n", 487952ccf843Smisaki cs.value); 4880adfcba55Sjoycey #else 488144961713Sgirish cmn_err(CE_NOTE, "!Write 0x%lx to RX_DMA_CTL_STAT_DBG_REG\n", 488252ccf843Smisaki cs.value); 4883adfcba55Sjoycey #endif 488444961713Sgirish RXDMA_REG_WRITE64(nxgep->npi_handle, RX_DMA_CTL_STAT_DBG_REG, 488552ccf843Smisaki chan, cs.value); 488644961713Sgirish break; 488744961713Sgirish case NXGE_FM_EREPORT_RDMC_ID_MISMATCH: 488844961713Sgirish case NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR: 488944961713Sgirish case NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR: 489044961713Sgirish cdfs.value = 0; 489144961713Sgirish if (err_id == NXGE_FM_EREPORT_RDMC_ID_MISMATCH) 489244961713Sgirish cdfs.bits.ldw.id_mismatch = (1 << nxgep->mac.portnum); 489344961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR) 489444961713Sgirish cdfs.bits.ldw.zcp_eop_err = (1 << nxgep->mac.portnum); 489544961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR) 489644961713Sgirish cdfs.bits.ldw.ipp_eop_err = (1 << nxgep->mac.portnum); 4897adfcba55Sjoycey #if defined(__i386) 4898adfcba55Sjoycey cmn_err(CE_NOTE, 489952ccf843Smisaki "!Write 0x%llx to RX_CTL_DAT_FIFO_STAT_DBG_REG\n", 490052ccf843Smisaki cdfs.value); 4901adfcba55Sjoycey #else 490244961713Sgirish cmn_err(CE_NOTE, 490352ccf843Smisaki "!Write 0x%lx to RX_CTL_DAT_FIFO_STAT_DBG_REG\n", 490452ccf843Smisaki cdfs.value); 4905adfcba55Sjoycey #endif 4906678453a8Sspeer NXGE_REG_WR64(nxgep->npi_handle, 4907678453a8Sspeer RX_CTL_DAT_FIFO_STAT_DBG_REG, cdfs.value); 490844961713Sgirish break; 490944961713Sgirish case NXGE_FM_EREPORT_RDMC_DCF_ERR: 491044961713Sgirish break; 491153f3d8ecSyc case NXGE_FM_EREPORT_RDMC_RCR_ERR: 491244961713Sgirish break; 491344961713Sgirish } 491444961713Sgirish } 4915678453a8Sspeer 4916678453a8Sspeer static void 4917678453a8Sspeer nxge_rxdma_databuf_free(p_rx_rbr_ring_t rbr_p) 4918678453a8Sspeer { 4919678453a8Sspeer rxring_info_t *ring_info; 4920678453a8Sspeer int index; 4921678453a8Sspeer uint32_t chunk_size; 4922678453a8Sspeer uint64_t kaddr; 4923678453a8Sspeer uint_t num_blocks; 4924678453a8Sspeer 4925678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, "==> nxge_rxdma_databuf_free")); 4926678453a8Sspeer 4927678453a8Sspeer if (rbr_p == NULL) { 4928678453a8Sspeer NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 4929678453a8Sspeer "==> nxge_rxdma_databuf_free: NULL rbr pointer")); 4930678453a8Sspeer return; 4931678453a8Sspeer } 4932678453a8Sspeer 4933678453a8Sspeer if (rbr_p->rbr_alloc_type == DDI_MEM_ALLOC) { 4934e759c33aSMichael Speer NXGE_DEBUG_MSG((NULL, DMA_CTL, 4935e759c33aSMichael Speer "<== nxge_rxdma_databuf_free: DDI")); 4936678453a8Sspeer return; 4937678453a8Sspeer } 4938678453a8Sspeer 4939678453a8Sspeer ring_info = rbr_p->ring_info; 4940678453a8Sspeer if (ring_info == NULL) { 4941678453a8Sspeer NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 4942678453a8Sspeer "==> nxge_rxdma_databuf_free: NULL ring info")); 4943678453a8Sspeer return; 4944678453a8Sspeer } 4945678453a8Sspeer num_blocks = rbr_p->num_blocks; 4946678453a8Sspeer for (index = 0; index < num_blocks; index++) { 4947678453a8Sspeer kaddr = ring_info->buffer[index].kaddr; 4948678453a8Sspeer chunk_size = ring_info->buffer[index].buf_size; 4949678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, 4950678453a8Sspeer "==> nxge_rxdma_databuf_free: free chunk %d " 4951678453a8Sspeer "kaddrp $%p chunk size %d", 4952678453a8Sspeer index, kaddr, chunk_size)); 4953678453a8Sspeer if (kaddr == NULL) continue; 4954678453a8Sspeer nxge_free_buf(rbr_p->rbr_alloc_type, kaddr, chunk_size); 4955678453a8Sspeer ring_info->buffer[index].kaddr = NULL; 4956678453a8Sspeer } 4957678453a8Sspeer 4958678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_databuf_free")); 4959678453a8Sspeer } 4960678453a8Sspeer 4961678453a8Sspeer #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 4962678453a8Sspeer extern void contig_mem_free(void *, size_t); 4963678453a8Sspeer #endif 4964678453a8Sspeer 4965678453a8Sspeer void 4966678453a8Sspeer nxge_free_buf(buf_alloc_type_t alloc_type, uint64_t kaddr, uint32_t buf_size) 4967678453a8Sspeer { 4968678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, "==> nxge_free_buf")); 4969678453a8Sspeer 4970678453a8Sspeer if (kaddr == NULL || !buf_size) { 4971678453a8Sspeer NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 4972678453a8Sspeer "==> nxge_free_buf: invalid kaddr $%p size to free %d", 4973678453a8Sspeer kaddr, buf_size)); 4974678453a8Sspeer return; 4975678453a8Sspeer } 4976678453a8Sspeer 4977678453a8Sspeer switch (alloc_type) { 4978678453a8Sspeer case KMEM_ALLOC: 4979678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, 4980678453a8Sspeer "==> nxge_free_buf: freeing kmem $%p size %d", 4981678453a8Sspeer kaddr, buf_size)); 4982678453a8Sspeer #if defined(__i386) 4983678453a8Sspeer KMEM_FREE((void *)(uint32_t)kaddr, buf_size); 4984678453a8Sspeer #else 4985678453a8Sspeer KMEM_FREE((void *)kaddr, buf_size); 4986678453a8Sspeer #endif 4987678453a8Sspeer break; 4988678453a8Sspeer 4989678453a8Sspeer #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 4990678453a8Sspeer case CONTIG_MEM_ALLOC: 4991678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, 4992678453a8Sspeer "==> nxge_free_buf: freeing contig_mem kaddr $%p size %d", 4993678453a8Sspeer kaddr, buf_size)); 4994678453a8Sspeer contig_mem_free((void *)kaddr, buf_size); 4995678453a8Sspeer break; 4996678453a8Sspeer #endif 4997678453a8Sspeer 4998678453a8Sspeer default: 4999678453a8Sspeer NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 5000678453a8Sspeer "<== nxge_free_buf: unsupported alloc type %d", 5001678453a8Sspeer alloc_type)); 5002678453a8Sspeer return; 5003678453a8Sspeer } 5004678453a8Sspeer 5005678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_free_buf")); 5006678453a8Sspeer } 5007