144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 223e82a89eSmisaki * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 2344961713Sgirish * Use is subject to license terms. 2444961713Sgirish */ 2544961713Sgirish 2644961713Sgirish #include <sys/nxge/nxge_impl.h> 2744961713Sgirish #include <sys/nxge/nxge_rxdma.h> 28678453a8Sspeer #include <sys/nxge/nxge_hio.h> 29678453a8Sspeer 30678453a8Sspeer #if !defined(_BIG_ENDIAN) 31678453a8Sspeer #include <npi_rx_rd32.h> 32678453a8Sspeer #endif 33678453a8Sspeer #include <npi_rx_rd64.h> 34678453a8Sspeer #include <npi_rx_wr64.h> 3544961713Sgirish 3644961713Sgirish #define NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp) \ 37678453a8Sspeer (rdcgrp + nxgep->pt_config.hw_config.def_mac_rxdma_grpid) 3844961713Sgirish #define NXGE_ACTUAL_RDC(nxgep, rdc) \ 3944961713Sgirish (rdc + nxgep->pt_config.hw_config.start_rdc) 4044961713Sgirish 4144961713Sgirish /* 4244961713Sgirish * Globals: tunable parameters (/etc/system or adb) 4344961713Sgirish * 4444961713Sgirish */ 4544961713Sgirish extern uint32_t nxge_rbr_size; 4644961713Sgirish extern uint32_t nxge_rcr_size; 4744961713Sgirish extern uint32_t nxge_rbr_spare_size; 4844961713Sgirish 4944961713Sgirish extern uint32_t nxge_mblks_pending; 5044961713Sgirish 5144961713Sgirish /* 5244961713Sgirish * Tunable to reduce the amount of time spent in the 5344961713Sgirish * ISR doing Rx Processing. 5444961713Sgirish */ 5544961713Sgirish extern uint32_t nxge_max_rx_pkts; 5644961713Sgirish boolean_t nxge_jumbo_enable; 5744961713Sgirish 5844961713Sgirish /* 5944961713Sgirish * Tunables to manage the receive buffer blocks. 6044961713Sgirish * 6144961713Sgirish * nxge_rx_threshold_hi: copy all buffers. 6244961713Sgirish * nxge_rx_bcopy_size_type: receive buffer block size type. 6344961713Sgirish * nxge_rx_threshold_lo: copy only up to tunable block size type. 6444961713Sgirish */ 6544961713Sgirish extern nxge_rxbuf_threshold_t nxge_rx_threshold_hi; 6644961713Sgirish extern nxge_rxbuf_type_t nxge_rx_buf_size_type; 6744961713Sgirish extern nxge_rxbuf_threshold_t nxge_rx_threshold_lo; 6844961713Sgirish 69b4d05839Sml extern uint32_t nxge_cksum_offload; 70678453a8Sspeer 71678453a8Sspeer static nxge_status_t nxge_map_rxdma(p_nxge_t, int); 72678453a8Sspeer static void nxge_unmap_rxdma(p_nxge_t, int); 7344961713Sgirish 7444961713Sgirish static nxge_status_t nxge_rxdma_hw_start_common(p_nxge_t); 7544961713Sgirish 76678453a8Sspeer static nxge_status_t nxge_rxdma_hw_start(p_nxge_t, int); 77678453a8Sspeer static void nxge_rxdma_hw_stop(p_nxge_t, int); 7844961713Sgirish 7944961713Sgirish static nxge_status_t nxge_map_rxdma_channel(p_nxge_t, uint16_t, 8044961713Sgirish p_nxge_dma_common_t *, p_rx_rbr_ring_t *, 8144961713Sgirish uint32_t, 8244961713Sgirish p_nxge_dma_common_t *, p_rx_rcr_ring_t *, 8344961713Sgirish p_rx_mbox_t *); 8444961713Sgirish static void nxge_unmap_rxdma_channel(p_nxge_t, uint16_t, 8544961713Sgirish p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t); 8644961713Sgirish 8744961713Sgirish static nxge_status_t nxge_map_rxdma_channel_cfg_ring(p_nxge_t, 8844961713Sgirish uint16_t, 8944961713Sgirish p_nxge_dma_common_t *, p_rx_rbr_ring_t *, 9044961713Sgirish p_rx_rcr_ring_t *, p_rx_mbox_t *); 9144961713Sgirish static void nxge_unmap_rxdma_channel_cfg_ring(p_nxge_t, 9244961713Sgirish p_rx_rcr_ring_t, p_rx_mbox_t); 9344961713Sgirish 9444961713Sgirish static nxge_status_t nxge_map_rxdma_channel_buf_ring(p_nxge_t, 9544961713Sgirish uint16_t, 9644961713Sgirish p_nxge_dma_common_t *, 9744961713Sgirish p_rx_rbr_ring_t *, uint32_t); 9844961713Sgirish static void nxge_unmap_rxdma_channel_buf_ring(p_nxge_t, 9944961713Sgirish p_rx_rbr_ring_t); 10044961713Sgirish 10144961713Sgirish static nxge_status_t nxge_rxdma_start_channel(p_nxge_t, uint16_t, 10244961713Sgirish p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t); 10344961713Sgirish static nxge_status_t nxge_rxdma_stop_channel(p_nxge_t, uint16_t); 10444961713Sgirish 105678453a8Sspeer static mblk_t * 106678453a8Sspeer nxge_rx_pkts(p_nxge_t, p_rx_rcr_ring_t, rx_dma_ctl_stat_t, int); 10744961713Sgirish 10844961713Sgirish static void nxge_receive_packet(p_nxge_t, 10944961713Sgirish p_rx_rcr_ring_t, 11044961713Sgirish p_rcr_entry_t, 11144961713Sgirish boolean_t *, 11244961713Sgirish mblk_t **, mblk_t **); 11344961713Sgirish 11444961713Sgirish nxge_status_t nxge_disable_rxdma_channel(p_nxge_t, uint16_t); 11544961713Sgirish 11644961713Sgirish static p_rx_msg_t nxge_allocb(size_t, uint32_t, p_nxge_dma_common_t); 11744961713Sgirish static void nxge_freeb(p_rx_msg_t); 118678453a8Sspeer static void nxge_rx_pkts_vring(p_nxge_t, uint_t, rx_dma_ctl_stat_t); 119678453a8Sspeer static nxge_status_t nxge_rx_err_evnts(p_nxge_t, int, rx_dma_ctl_stat_t); 12044961713Sgirish 12144961713Sgirish static nxge_status_t nxge_rxdma_handle_port_errors(p_nxge_t, 12244961713Sgirish uint32_t, uint32_t); 12344961713Sgirish 12444961713Sgirish static nxge_status_t nxge_rxbuf_index_info_init(p_nxge_t, 12544961713Sgirish p_rx_rbr_ring_t); 12644961713Sgirish 12744961713Sgirish 12844961713Sgirish static nxge_status_t 12944961713Sgirish nxge_rxdma_fatal_err_recover(p_nxge_t, uint16_t); 13044961713Sgirish 13144961713Sgirish nxge_status_t 13244961713Sgirish nxge_rx_port_fatal_err_recover(p_nxge_t); 13344961713Sgirish 134678453a8Sspeer static void nxge_rxdma_databuf_free(p_rx_rbr_ring_t); 135678453a8Sspeer 13644961713Sgirish nxge_status_t 13744961713Sgirish nxge_init_rxdma_channels(p_nxge_t nxgep) 13844961713Sgirish { 139678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set; 140678453a8Sspeer int i, count; 14144961713Sgirish 14244961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_init_rxdma_channels")); 14344961713Sgirish 144678453a8Sspeer if (!isLDOMguest(nxgep)) { 145678453a8Sspeer if (nxge_rxdma_hw_start_common(nxgep) != NXGE_OK) { 146678453a8Sspeer cmn_err(CE_NOTE, "hw_start_common"); 147678453a8Sspeer return (NXGE_ERROR); 148678453a8Sspeer } 149678453a8Sspeer } 150678453a8Sspeer 151678453a8Sspeer /* 152678453a8Sspeer * NXGE_LOGICAL_GROUP_MAX > NXGE_MAX_RDC_GROUPS (8) 153678453a8Sspeer * We only have 8 hardware RDC tables, but we may have 154678453a8Sspeer * up to 16 logical (software-defined) groups of RDCS, 155678453a8Sspeer * if we make use of layer 3 & 4 hardware classification. 156678453a8Sspeer */ 157678453a8Sspeer for (i = 0, count = 0; i < NXGE_LOGICAL_GROUP_MAX; i++) { 158678453a8Sspeer if ((1 << i) & set->lg.map) { 159678453a8Sspeer int channel; 160678453a8Sspeer nxge_grp_t *group = set->group[i]; 161678453a8Sspeer for (channel = 0; channel < NXGE_MAX_RDCS; channel++) { 162678453a8Sspeer if ((1 << channel) & group->map) { 163678453a8Sspeer if ((nxge_grp_dc_add(nxgep, 1646920a987SMisaki Miyashita group, VP_BOUND_RX, channel))) 165678453a8Sspeer return (NXGE_ERROR); 166678453a8Sspeer } 167678453a8Sspeer } 168678453a8Sspeer } 169678453a8Sspeer if (++count == set->lg.count) 170678453a8Sspeer break; 17144961713Sgirish } 17244961713Sgirish 173678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_init_rxdma_channels")); 174678453a8Sspeer 175678453a8Sspeer return (NXGE_OK); 176678453a8Sspeer } 177678453a8Sspeer 178678453a8Sspeer nxge_status_t 179678453a8Sspeer nxge_init_rxdma_channel(p_nxge_t nxge, int channel) 180678453a8Sspeer { 181678453a8Sspeer nxge_status_t status; 182678453a8Sspeer 183678453a8Sspeer NXGE_DEBUG_MSG((nxge, MEM2_CTL, "==> nxge_init_rxdma_channel")); 184678453a8Sspeer 185678453a8Sspeer status = nxge_map_rxdma(nxge, channel); 18644961713Sgirish if (status != NXGE_OK) { 187678453a8Sspeer NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 188678453a8Sspeer "<== nxge_init_rxdma: status 0x%x", status)); 189678453a8Sspeer return (status); 19044961713Sgirish } 19144961713Sgirish 192678453a8Sspeer status = nxge_rxdma_hw_start(nxge, channel); 19344961713Sgirish if (status != NXGE_OK) { 194678453a8Sspeer nxge_unmap_rxdma(nxge, channel); 19544961713Sgirish } 19644961713Sgirish 197678453a8Sspeer if (!nxge->statsp->rdc_ksp[channel]) 198678453a8Sspeer nxge_setup_rdc_kstats(nxge, channel); 199678453a8Sspeer 200678453a8Sspeer NXGE_DEBUG_MSG((nxge, MEM2_CTL, 201678453a8Sspeer "<== nxge_init_rxdma_channel: status 0x%x", status)); 20244961713Sgirish 20344961713Sgirish return (status); 20444961713Sgirish } 20544961713Sgirish 20644961713Sgirish void 20744961713Sgirish nxge_uninit_rxdma_channels(p_nxge_t nxgep) 20844961713Sgirish { 209678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set; 210678453a8Sspeer int rdc; 211678453a8Sspeer 21244961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_uninit_rxdma_channels")); 21344961713Sgirish 214678453a8Sspeer if (set->owned.map == 0) { 215678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 216678453a8Sspeer "nxge_uninit_rxdma_channels: no channels")); 217678453a8Sspeer return; 218678453a8Sspeer } 21944961713Sgirish 220678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 221678453a8Sspeer if ((1 << rdc) & set->owned.map) { 222678453a8Sspeer nxge_grp_dc_remove(nxgep, VP_BOUND_RX, rdc); 223678453a8Sspeer } 224678453a8Sspeer } 225678453a8Sspeer 226678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_uninit_rxdma_channels")); 227678453a8Sspeer } 228678453a8Sspeer 229678453a8Sspeer void 230678453a8Sspeer nxge_uninit_rxdma_channel(p_nxge_t nxgep, int channel) 231678453a8Sspeer { 232678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_uninit_rxdma_channel")); 233678453a8Sspeer 234678453a8Sspeer if (nxgep->statsp->rdc_ksp[channel]) { 235678453a8Sspeer kstat_delete(nxgep->statsp->rdc_ksp[channel]); 236678453a8Sspeer nxgep->statsp->rdc_ksp[channel] = 0; 237678453a8Sspeer } 238678453a8Sspeer 239678453a8Sspeer nxge_rxdma_hw_stop(nxgep, channel); 240678453a8Sspeer nxge_unmap_rxdma(nxgep, channel); 241678453a8Sspeer 242678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_uinit_rxdma_channel")); 24344961713Sgirish } 24444961713Sgirish 24544961713Sgirish nxge_status_t 24644961713Sgirish nxge_reset_rxdma_channel(p_nxge_t nxgep, uint16_t channel) 24744961713Sgirish { 24844961713Sgirish npi_handle_t handle; 24944961713Sgirish npi_status_t rs = NPI_SUCCESS; 25044961713Sgirish nxge_status_t status = NXGE_OK; 25144961713Sgirish 252*330cd344SMichael Speer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_reset_rxdma_channel")); 25344961713Sgirish 25444961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 25544961713Sgirish rs = npi_rxdma_cfg_rdc_reset(handle, channel); 25644961713Sgirish 25744961713Sgirish if (rs != NPI_SUCCESS) { 25844961713Sgirish status = NXGE_ERROR | rs; 25944961713Sgirish } 26044961713Sgirish 261*330cd344SMichael Speer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_reset_rxdma_channel")); 262*330cd344SMichael Speer 26344961713Sgirish return (status); 26444961713Sgirish } 26544961713Sgirish 26644961713Sgirish void 26744961713Sgirish nxge_rxdma_regs_dump_channels(p_nxge_t nxgep) 26844961713Sgirish { 269678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set; 270678453a8Sspeer int rdc; 27144961713Sgirish 27244961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_regs_dump_channels")); 27344961713Sgirish 274678453a8Sspeer if (!isLDOMguest(nxgep)) { 275678453a8Sspeer npi_handle_t handle = NXGE_DEV_NPI_HANDLE(nxgep); 276678453a8Sspeer (void) npi_rxdma_dump_fzc_regs(handle); 27744961713Sgirish } 278678453a8Sspeer 279678453a8Sspeer if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) { 280678453a8Sspeer NXGE_DEBUG_MSG((nxgep, TX_CTL, 281678453a8Sspeer "nxge_rxdma_regs_dump_channels: " 282678453a8Sspeer "NULL ring pointer(s)")); 28344961713Sgirish return; 28444961713Sgirish } 28544961713Sgirish 286678453a8Sspeer if (set->owned.map == 0) { 28744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 288678453a8Sspeer "nxge_rxdma_regs_dump_channels: no channels")); 28944961713Sgirish return; 29044961713Sgirish } 29144961713Sgirish 292678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 293678453a8Sspeer if ((1 << rdc) & set->owned.map) { 294678453a8Sspeer rx_rbr_ring_t *ring = 295678453a8Sspeer nxgep->rx_rbr_rings->rbr_rings[rdc]; 296678453a8Sspeer if (ring) { 297678453a8Sspeer (void) nxge_dump_rxdma_channel(nxgep, rdc); 298678453a8Sspeer } 29944961713Sgirish } 30044961713Sgirish } 30144961713Sgirish 30244961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_regs_dump")); 30344961713Sgirish } 30444961713Sgirish 30544961713Sgirish nxge_status_t 30644961713Sgirish nxge_dump_rxdma_channel(p_nxge_t nxgep, uint8_t channel) 30744961713Sgirish { 30844961713Sgirish npi_handle_t handle; 30944961713Sgirish npi_status_t rs = NPI_SUCCESS; 31044961713Sgirish nxge_status_t status = NXGE_OK; 31144961713Sgirish 31244961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_dump_rxdma_channel")); 31344961713Sgirish 31444961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 31544961713Sgirish rs = npi_rxdma_dump_rdc_regs(handle, channel); 31644961713Sgirish 31744961713Sgirish if (rs != NPI_SUCCESS) { 31844961713Sgirish status = NXGE_ERROR | rs; 31944961713Sgirish } 32044961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_dump_rxdma_channel")); 32144961713Sgirish return (status); 32244961713Sgirish } 32344961713Sgirish 32444961713Sgirish nxge_status_t 32544961713Sgirish nxge_init_rxdma_channel_event_mask(p_nxge_t nxgep, uint16_t channel, 32644961713Sgirish p_rx_dma_ent_msk_t mask_p) 32744961713Sgirish { 32844961713Sgirish npi_handle_t handle; 32944961713Sgirish npi_status_t rs = NPI_SUCCESS; 33044961713Sgirish nxge_status_t status = NXGE_OK; 33144961713Sgirish 33244961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 33352ccf843Smisaki "<== nxge_init_rxdma_channel_event_mask")); 33444961713Sgirish 33544961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 33644961713Sgirish rs = npi_rxdma_event_mask(handle, OP_SET, channel, mask_p); 33744961713Sgirish if (rs != NPI_SUCCESS) { 33844961713Sgirish status = NXGE_ERROR | rs; 33944961713Sgirish } 34044961713Sgirish 34144961713Sgirish return (status); 34244961713Sgirish } 34344961713Sgirish 34444961713Sgirish nxge_status_t 34544961713Sgirish nxge_init_rxdma_channel_cntl_stat(p_nxge_t nxgep, uint16_t channel, 34644961713Sgirish p_rx_dma_ctl_stat_t cs_p) 34744961713Sgirish { 34844961713Sgirish npi_handle_t handle; 34944961713Sgirish npi_status_t rs = NPI_SUCCESS; 35044961713Sgirish nxge_status_t status = NXGE_OK; 35144961713Sgirish 35244961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 35352ccf843Smisaki "<== nxge_init_rxdma_channel_cntl_stat")); 35444961713Sgirish 35544961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 35644961713Sgirish rs = npi_rxdma_control_status(handle, OP_SET, channel, cs_p); 35744961713Sgirish 35844961713Sgirish if (rs != NPI_SUCCESS) { 35944961713Sgirish status = NXGE_ERROR | rs; 36044961713Sgirish } 36144961713Sgirish 36244961713Sgirish return (status); 36344961713Sgirish } 36444961713Sgirish 365678453a8Sspeer /* 366678453a8Sspeer * nxge_rxdma_cfg_rdcgrp_default_rdc 367678453a8Sspeer * 368678453a8Sspeer * Set the default RDC for an RDC Group (Table) 369678453a8Sspeer * 370678453a8Sspeer * Arguments: 371678453a8Sspeer * nxgep 372678453a8Sspeer * rdcgrp The group to modify 373678453a8Sspeer * rdc The new default RDC. 374678453a8Sspeer * 375678453a8Sspeer * Notes: 376678453a8Sspeer * 377678453a8Sspeer * NPI/NXGE function calls: 378678453a8Sspeer * npi_rxdma_cfg_rdc_table_default_rdc() 379678453a8Sspeer * 380678453a8Sspeer * Registers accessed: 381678453a8Sspeer * RDC_TBL_REG: FZC_ZCP + 0x10000 382678453a8Sspeer * 383678453a8Sspeer * Context: 384678453a8Sspeer * Service domain 385678453a8Sspeer */ 38644961713Sgirish nxge_status_t 387678453a8Sspeer nxge_rxdma_cfg_rdcgrp_default_rdc( 388678453a8Sspeer p_nxge_t nxgep, 389678453a8Sspeer uint8_t rdcgrp, 390678453a8Sspeer uint8_t rdc) 39144961713Sgirish { 39244961713Sgirish npi_handle_t handle; 39344961713Sgirish npi_status_t rs = NPI_SUCCESS; 39444961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 39544961713Sgirish p_nxge_rdc_grp_t rdc_grp_p; 39644961713Sgirish uint8_t actual_rdcgrp, actual_rdc; 39744961713Sgirish 39844961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 39952ccf843Smisaki " ==> nxge_rxdma_cfg_rdcgrp_default_rdc")); 40044961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 40144961713Sgirish 40244961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 40344961713Sgirish 404678453a8Sspeer /* 405678453a8Sspeer * This has to be rewritten. Do we even allow this anymore? 406678453a8Sspeer */ 40744961713Sgirish rdc_grp_p = &p_dma_cfgp->rdc_grps[rdcgrp]; 408678453a8Sspeer RDC_MAP_IN(rdc_grp_p->map, rdc); 409678453a8Sspeer rdc_grp_p->def_rdc = rdc; 41044961713Sgirish 41144961713Sgirish actual_rdcgrp = NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp); 41244961713Sgirish actual_rdc = NXGE_ACTUAL_RDC(nxgep, rdc); 41344961713Sgirish 414678453a8Sspeer rs = npi_rxdma_cfg_rdc_table_default_rdc( 41552ccf843Smisaki handle, actual_rdcgrp, actual_rdc); 41644961713Sgirish 41744961713Sgirish if (rs != NPI_SUCCESS) { 41844961713Sgirish return (NXGE_ERROR | rs); 41944961713Sgirish } 42044961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 42152ccf843Smisaki " <== nxge_rxdma_cfg_rdcgrp_default_rdc")); 42244961713Sgirish return (NXGE_OK); 42344961713Sgirish } 42444961713Sgirish 42544961713Sgirish nxge_status_t 42644961713Sgirish nxge_rxdma_cfg_port_default_rdc(p_nxge_t nxgep, uint8_t port, uint8_t rdc) 42744961713Sgirish { 42844961713Sgirish npi_handle_t handle; 42944961713Sgirish 43044961713Sgirish uint8_t actual_rdc; 43144961713Sgirish npi_status_t rs = NPI_SUCCESS; 43244961713Sgirish 43344961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 43452ccf843Smisaki " ==> nxge_rxdma_cfg_port_default_rdc")); 43544961713Sgirish 43644961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 437678453a8Sspeer actual_rdc = rdc; /* XXX Hack! */ 43844961713Sgirish rs = npi_rxdma_cfg_default_port_rdc(handle, port, actual_rdc); 43944961713Sgirish 44044961713Sgirish 44144961713Sgirish if (rs != NPI_SUCCESS) { 44244961713Sgirish return (NXGE_ERROR | rs); 44344961713Sgirish } 44444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 44552ccf843Smisaki " <== nxge_rxdma_cfg_port_default_rdc")); 44644961713Sgirish 44744961713Sgirish return (NXGE_OK); 44844961713Sgirish } 44944961713Sgirish 45044961713Sgirish nxge_status_t 45144961713Sgirish nxge_rxdma_cfg_rcr_threshold(p_nxge_t nxgep, uint8_t channel, 45244961713Sgirish uint16_t pkts) 45344961713Sgirish { 45444961713Sgirish npi_status_t rs = NPI_SUCCESS; 45544961713Sgirish npi_handle_t handle; 45644961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 45752ccf843Smisaki " ==> nxge_rxdma_cfg_rcr_threshold")); 45844961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 45944961713Sgirish 46044961713Sgirish rs = npi_rxdma_cfg_rdc_rcr_threshold(handle, channel, pkts); 46144961713Sgirish 46244961713Sgirish if (rs != NPI_SUCCESS) { 46344961713Sgirish return (NXGE_ERROR | rs); 46444961713Sgirish } 46544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_threshold")); 46644961713Sgirish return (NXGE_OK); 46744961713Sgirish } 46844961713Sgirish 46944961713Sgirish nxge_status_t 47044961713Sgirish nxge_rxdma_cfg_rcr_timeout(p_nxge_t nxgep, uint8_t channel, 47144961713Sgirish uint16_t tout, uint8_t enable) 47244961713Sgirish { 47344961713Sgirish npi_status_t rs = NPI_SUCCESS; 47444961713Sgirish npi_handle_t handle; 47544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, " ==> nxge_rxdma_cfg_rcr_timeout")); 47644961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 47744961713Sgirish if (enable == 0) { 47844961713Sgirish rs = npi_rxdma_cfg_rdc_rcr_timeout_disable(handle, channel); 47944961713Sgirish } else { 48044961713Sgirish rs = npi_rxdma_cfg_rdc_rcr_timeout(handle, channel, 48152ccf843Smisaki tout); 48244961713Sgirish } 48344961713Sgirish 48444961713Sgirish if (rs != NPI_SUCCESS) { 48544961713Sgirish return (NXGE_ERROR | rs); 48644961713Sgirish } 48744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_timeout")); 48844961713Sgirish return (NXGE_OK); 48944961713Sgirish } 49044961713Sgirish 49144961713Sgirish nxge_status_t 49244961713Sgirish nxge_enable_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 49344961713Sgirish p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p) 49444961713Sgirish { 49544961713Sgirish npi_handle_t handle; 49644961713Sgirish rdc_desc_cfg_t rdc_desc; 49744961713Sgirish p_rcrcfig_b_t cfgb_p; 49844961713Sgirish npi_status_t rs = NPI_SUCCESS; 49944961713Sgirish 50044961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel")); 50144961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 50244961713Sgirish /* 50344961713Sgirish * Use configuration data composed at init time. 50444961713Sgirish * Write to hardware the receive ring configurations. 50544961713Sgirish */ 50644961713Sgirish rdc_desc.mbox_enable = 1; 50744961713Sgirish rdc_desc.mbox_addr = mbox_p->mbox_addr; 50844961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 50952ccf843Smisaki "==> nxge_enable_rxdma_channel: mboxp $%p($%p)", 51052ccf843Smisaki mbox_p->mbox_addr, rdc_desc.mbox_addr)); 51144961713Sgirish 51244961713Sgirish rdc_desc.rbr_len = rbr_p->rbb_max; 51344961713Sgirish rdc_desc.rbr_addr = rbr_p->rbr_addr; 51444961713Sgirish 51544961713Sgirish switch (nxgep->rx_bksize_code) { 51644961713Sgirish case RBR_BKSIZE_4K: 51744961713Sgirish rdc_desc.page_size = SIZE_4KB; 51844961713Sgirish break; 51944961713Sgirish case RBR_BKSIZE_8K: 52044961713Sgirish rdc_desc.page_size = SIZE_8KB; 52144961713Sgirish break; 52244961713Sgirish case RBR_BKSIZE_16K: 52344961713Sgirish rdc_desc.page_size = SIZE_16KB; 52444961713Sgirish break; 52544961713Sgirish case RBR_BKSIZE_32K: 52644961713Sgirish rdc_desc.page_size = SIZE_32KB; 52744961713Sgirish break; 52844961713Sgirish } 52944961713Sgirish 53044961713Sgirish rdc_desc.size0 = rbr_p->npi_pkt_buf_size0; 53144961713Sgirish rdc_desc.valid0 = 1; 53244961713Sgirish 53344961713Sgirish rdc_desc.size1 = rbr_p->npi_pkt_buf_size1; 53444961713Sgirish rdc_desc.valid1 = 1; 53544961713Sgirish 53644961713Sgirish rdc_desc.size2 = rbr_p->npi_pkt_buf_size2; 53744961713Sgirish rdc_desc.valid2 = 1; 53844961713Sgirish 53944961713Sgirish rdc_desc.full_hdr = rcr_p->full_hdr_flag; 54044961713Sgirish rdc_desc.offset = rcr_p->sw_priv_hdr_len; 54144961713Sgirish 54244961713Sgirish rdc_desc.rcr_len = rcr_p->comp_size; 54344961713Sgirish rdc_desc.rcr_addr = rcr_p->rcr_addr; 54444961713Sgirish 54544961713Sgirish cfgb_p = &(rcr_p->rcr_cfgb); 54644961713Sgirish rdc_desc.rcr_threshold = cfgb_p->bits.ldw.pthres; 547678453a8Sspeer /* For now, disable this timeout in a guest domain. */ 548678453a8Sspeer if (isLDOMguest(nxgep)) { 549678453a8Sspeer rdc_desc.rcr_timeout = 0; 550678453a8Sspeer rdc_desc.rcr_timeout_enable = 0; 551678453a8Sspeer } else { 552678453a8Sspeer rdc_desc.rcr_timeout = cfgb_p->bits.ldw.timeout; 553678453a8Sspeer rdc_desc.rcr_timeout_enable = cfgb_p->bits.ldw.entout; 554678453a8Sspeer } 55544961713Sgirish 55644961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: " 55752ccf843Smisaki "rbr_len qlen %d pagesize code %d rcr_len %d", 55852ccf843Smisaki rdc_desc.rbr_len, rdc_desc.page_size, rdc_desc.rcr_len)); 55944961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: " 56052ccf843Smisaki "size 0 %d size 1 %d size 2 %d", 56152ccf843Smisaki rbr_p->npi_pkt_buf_size0, rbr_p->npi_pkt_buf_size1, 56252ccf843Smisaki rbr_p->npi_pkt_buf_size2)); 56344961713Sgirish 56444961713Sgirish rs = npi_rxdma_cfg_rdc_ring(handle, rbr_p->rdc, &rdc_desc); 56544961713Sgirish if (rs != NPI_SUCCESS) { 56644961713Sgirish return (NXGE_ERROR | rs); 56744961713Sgirish } 56844961713Sgirish 56944961713Sgirish /* 57044961713Sgirish * Enable the timeout and threshold. 57144961713Sgirish */ 57244961713Sgirish rs = npi_rxdma_cfg_rdc_rcr_threshold(handle, channel, 57352ccf843Smisaki rdc_desc.rcr_threshold); 57444961713Sgirish if (rs != NPI_SUCCESS) { 57544961713Sgirish return (NXGE_ERROR | rs); 57644961713Sgirish } 57744961713Sgirish 57844961713Sgirish rs = npi_rxdma_cfg_rdc_rcr_timeout(handle, channel, 57952ccf843Smisaki rdc_desc.rcr_timeout); 58044961713Sgirish if (rs != NPI_SUCCESS) { 58144961713Sgirish return (NXGE_ERROR | rs); 58244961713Sgirish } 58344961713Sgirish 58444961713Sgirish /* Enable the DMA */ 58544961713Sgirish rs = npi_rxdma_cfg_rdc_enable(handle, channel); 58644961713Sgirish if (rs != NPI_SUCCESS) { 58744961713Sgirish return (NXGE_ERROR | rs); 58844961713Sgirish } 58944961713Sgirish 59044961713Sgirish /* Kick the DMA engine. */ 59144961713Sgirish npi_rxdma_rdc_rbr_kick(handle, channel, rbr_p->rbb_max); 59244961713Sgirish /* Clear the rbr empty bit */ 59344961713Sgirish (void) npi_rxdma_channel_rbr_empty_clear(handle, channel); 59444961713Sgirish 59544961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_enable_rxdma_channel")); 59644961713Sgirish 59744961713Sgirish return (NXGE_OK); 59844961713Sgirish } 59944961713Sgirish 60044961713Sgirish nxge_status_t 60144961713Sgirish nxge_disable_rxdma_channel(p_nxge_t nxgep, uint16_t channel) 60244961713Sgirish { 60344961713Sgirish npi_handle_t handle; 60444961713Sgirish npi_status_t rs = NPI_SUCCESS; 60544961713Sgirish 60644961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_disable_rxdma_channel")); 60744961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 60844961713Sgirish 60944961713Sgirish /* disable the DMA */ 61044961713Sgirish rs = npi_rxdma_cfg_rdc_disable(handle, channel); 61144961713Sgirish if (rs != NPI_SUCCESS) { 61244961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 61352ccf843Smisaki "<== nxge_disable_rxdma_channel:failed (0x%x)", 61452ccf843Smisaki rs)); 61544961713Sgirish return (NXGE_ERROR | rs); 61644961713Sgirish } 61744961713Sgirish 61844961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_disable_rxdma_channel")); 61944961713Sgirish return (NXGE_OK); 62044961713Sgirish } 62144961713Sgirish 62244961713Sgirish nxge_status_t 62344961713Sgirish nxge_rxdma_channel_rcrflush(p_nxge_t nxgep, uint8_t channel) 62444961713Sgirish { 62544961713Sgirish npi_handle_t handle; 62644961713Sgirish nxge_status_t status = NXGE_OK; 62744961713Sgirish 62844961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 62952ccf843Smisaki "<== nxge_init_rxdma_channel_rcrflush")); 63044961713Sgirish 63144961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 63244961713Sgirish npi_rxdma_rdc_rcr_flush(handle, channel); 63344961713Sgirish 63444961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 63552ccf843Smisaki "<== nxge_init_rxdma_channel_rcrflsh")); 63644961713Sgirish return (status); 63744961713Sgirish 63844961713Sgirish } 63944961713Sgirish 64044961713Sgirish #define MID_INDEX(l, r) ((r + l + 1) >> 1) 64144961713Sgirish 64244961713Sgirish #define TO_LEFT -1 64344961713Sgirish #define TO_RIGHT 1 64444961713Sgirish #define BOTH_RIGHT (TO_RIGHT + TO_RIGHT) 64544961713Sgirish #define BOTH_LEFT (TO_LEFT + TO_LEFT) 64644961713Sgirish #define IN_MIDDLE (TO_RIGHT + TO_LEFT) 64744961713Sgirish #define NO_HINT 0xffffffff 64844961713Sgirish 64944961713Sgirish /*ARGSUSED*/ 65044961713Sgirish nxge_status_t 65144961713Sgirish nxge_rxbuf_pp_to_vp(p_nxge_t nxgep, p_rx_rbr_ring_t rbr_p, 652a3c5bd6dSspeer uint8_t pktbufsz_type, uint64_t *pkt_buf_addr_pp, 653a3c5bd6dSspeer uint64_t **pkt_buf_addr_p, uint32_t *bufoffset, uint32_t *msg_index) 65444961713Sgirish { 65544961713Sgirish int bufsize; 65644961713Sgirish uint64_t pktbuf_pp; 65744961713Sgirish uint64_t dvma_addr; 65844961713Sgirish rxring_info_t *ring_info; 65944961713Sgirish int base_side, end_side; 66044961713Sgirish int r_index, l_index, anchor_index; 66144961713Sgirish int found, search_done; 66244961713Sgirish uint32_t offset, chunk_size, block_size, page_size_mask; 66344961713Sgirish uint32_t chunk_index, block_index, total_index; 66444961713Sgirish int max_iterations, iteration; 66544961713Sgirish rxbuf_index_info_t *bufinfo; 66644961713Sgirish 66744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> nxge_rxbuf_pp_to_vp")); 66844961713Sgirish 66944961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 67052ccf843Smisaki "==> nxge_rxbuf_pp_to_vp: buf_pp $%p btype %d", 67152ccf843Smisaki pkt_buf_addr_pp, 67252ccf843Smisaki pktbufsz_type)); 673adfcba55Sjoycey #if defined(__i386) 674adfcba55Sjoycey pktbuf_pp = (uint64_t)(uint32_t)pkt_buf_addr_pp; 675adfcba55Sjoycey #else 67644961713Sgirish pktbuf_pp = (uint64_t)pkt_buf_addr_pp; 677adfcba55Sjoycey #endif 67844961713Sgirish 67944961713Sgirish switch (pktbufsz_type) { 68044961713Sgirish case 0: 68144961713Sgirish bufsize = rbr_p->pkt_buf_size0; 68244961713Sgirish break; 68344961713Sgirish case 1: 68444961713Sgirish bufsize = rbr_p->pkt_buf_size1; 68544961713Sgirish break; 68644961713Sgirish case 2: 68744961713Sgirish bufsize = rbr_p->pkt_buf_size2; 68844961713Sgirish break; 68944961713Sgirish case RCR_SINGLE_BLOCK: 69044961713Sgirish bufsize = 0; 69144961713Sgirish anchor_index = 0; 69244961713Sgirish break; 69344961713Sgirish default: 69444961713Sgirish return (NXGE_ERROR); 69544961713Sgirish } 69644961713Sgirish 69744961713Sgirish if (rbr_p->num_blocks == 1) { 69844961713Sgirish anchor_index = 0; 69944961713Sgirish ring_info = rbr_p->ring_info; 70044961713Sgirish bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 70144961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 70252ccf843Smisaki "==> nxge_rxbuf_pp_to_vp: (found, 1 block) " 70352ccf843Smisaki "buf_pp $%p btype %d anchor_index %d " 70452ccf843Smisaki "bufinfo $%p", 70552ccf843Smisaki pkt_buf_addr_pp, 70652ccf843Smisaki pktbufsz_type, 70752ccf843Smisaki anchor_index, 70852ccf843Smisaki bufinfo)); 70944961713Sgirish 71044961713Sgirish goto found_index; 71144961713Sgirish } 71244961713Sgirish 71344961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 71452ccf843Smisaki "==> nxge_rxbuf_pp_to_vp: " 71552ccf843Smisaki "buf_pp $%p btype %d anchor_index %d", 71652ccf843Smisaki pkt_buf_addr_pp, 71752ccf843Smisaki pktbufsz_type, 71852ccf843Smisaki anchor_index)); 71944961713Sgirish 72044961713Sgirish ring_info = rbr_p->ring_info; 72144961713Sgirish found = B_FALSE; 72244961713Sgirish bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 72344961713Sgirish iteration = 0; 72444961713Sgirish max_iterations = ring_info->max_iterations; 72544961713Sgirish /* 726a3c5bd6dSspeer * First check if this block has been seen 72744961713Sgirish * recently. This is indicated by a hint which 72844961713Sgirish * is initialized when the first buffer of the block 72944961713Sgirish * is seen. The hint is reset when the last buffer of 73044961713Sgirish * the block has been processed. 73144961713Sgirish * As three block sizes are supported, three hints 73244961713Sgirish * are kept. The idea behind the hints is that once 73344961713Sgirish * the hardware uses a block for a buffer of that 73444961713Sgirish * size, it will use it exclusively for that size 73544961713Sgirish * and will use it until it is exhausted. It is assumed 73644961713Sgirish * that there would a single block being used for the same 73744961713Sgirish * buffer sizes at any given time. 73844961713Sgirish */ 73944961713Sgirish if (ring_info->hint[pktbufsz_type] != NO_HINT) { 74044961713Sgirish anchor_index = ring_info->hint[pktbufsz_type]; 74144961713Sgirish dvma_addr = bufinfo[anchor_index].dvma_addr; 74244961713Sgirish chunk_size = bufinfo[anchor_index].buf_size; 74344961713Sgirish if ((pktbuf_pp >= dvma_addr) && 74452ccf843Smisaki (pktbuf_pp < (dvma_addr + chunk_size))) { 74544961713Sgirish found = B_TRUE; 74644961713Sgirish /* 74744961713Sgirish * check if this is the last buffer in the block 74844961713Sgirish * If so, then reset the hint for the size; 74944961713Sgirish */ 75044961713Sgirish 75144961713Sgirish if ((pktbuf_pp + bufsize) >= (dvma_addr + chunk_size)) 75244961713Sgirish ring_info->hint[pktbufsz_type] = NO_HINT; 75344961713Sgirish } 75444961713Sgirish } 75544961713Sgirish 75644961713Sgirish if (found == B_FALSE) { 75744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 75852ccf843Smisaki "==> nxge_rxbuf_pp_to_vp: (!found)" 75952ccf843Smisaki "buf_pp $%p btype %d anchor_index %d", 76052ccf843Smisaki pkt_buf_addr_pp, 76152ccf843Smisaki pktbufsz_type, 76252ccf843Smisaki anchor_index)); 76344961713Sgirish 76444961713Sgirish /* 76544961713Sgirish * This is the first buffer of the block of this 76644961713Sgirish * size. Need to search the whole information 76744961713Sgirish * array. 76844961713Sgirish * the search algorithm uses a binary tree search 76944961713Sgirish * algorithm. It assumes that the information is 77044961713Sgirish * already sorted with increasing order 77144961713Sgirish * info[0] < info[1] < info[2] .... < info[n-1] 77244961713Sgirish * where n is the size of the information array 77344961713Sgirish */ 77444961713Sgirish r_index = rbr_p->num_blocks - 1; 77544961713Sgirish l_index = 0; 77644961713Sgirish search_done = B_FALSE; 77744961713Sgirish anchor_index = MID_INDEX(r_index, l_index); 77844961713Sgirish while (search_done == B_FALSE) { 77944961713Sgirish if ((r_index == l_index) || 78052ccf843Smisaki (iteration >= max_iterations)) 78144961713Sgirish search_done = B_TRUE; 78244961713Sgirish end_side = TO_RIGHT; /* to the right */ 78344961713Sgirish base_side = TO_LEFT; /* to the left */ 78444961713Sgirish /* read the DVMA address information and sort it */ 78544961713Sgirish dvma_addr = bufinfo[anchor_index].dvma_addr; 78644961713Sgirish chunk_size = bufinfo[anchor_index].buf_size; 78744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 78852ccf843Smisaki "==> nxge_rxbuf_pp_to_vp: (searching)" 78952ccf843Smisaki "buf_pp $%p btype %d " 79052ccf843Smisaki "anchor_index %d chunk_size %d dvmaaddr $%p", 79152ccf843Smisaki pkt_buf_addr_pp, 79252ccf843Smisaki pktbufsz_type, 79352ccf843Smisaki anchor_index, 79452ccf843Smisaki chunk_size, 79552ccf843Smisaki dvma_addr)); 79644961713Sgirish 79744961713Sgirish if (pktbuf_pp >= dvma_addr) 79844961713Sgirish base_side = TO_RIGHT; /* to the right */ 79944961713Sgirish if (pktbuf_pp < (dvma_addr + chunk_size)) 80044961713Sgirish end_side = TO_LEFT; /* to the left */ 80144961713Sgirish 80244961713Sgirish switch (base_side + end_side) { 80352ccf843Smisaki case IN_MIDDLE: 80452ccf843Smisaki /* found */ 80552ccf843Smisaki found = B_TRUE; 80652ccf843Smisaki search_done = B_TRUE; 80752ccf843Smisaki if ((pktbuf_pp + bufsize) < 80852ccf843Smisaki (dvma_addr + chunk_size)) 80952ccf843Smisaki ring_info->hint[pktbufsz_type] = 81052ccf843Smisaki bufinfo[anchor_index].buf_index; 81152ccf843Smisaki break; 81252ccf843Smisaki case BOTH_RIGHT: 81352ccf843Smisaki /* not found: go to the right */ 81452ccf843Smisaki l_index = anchor_index + 1; 81552ccf843Smisaki anchor_index = MID_INDEX(r_index, l_index); 81652ccf843Smisaki break; 81752ccf843Smisaki 81852ccf843Smisaki case BOTH_LEFT: 81952ccf843Smisaki /* not found: go to the left */ 82052ccf843Smisaki r_index = anchor_index - 1; 82152ccf843Smisaki anchor_index = MID_INDEX(r_index, l_index); 82252ccf843Smisaki break; 82352ccf843Smisaki default: /* should not come here */ 82452ccf843Smisaki return (NXGE_ERROR); 82544961713Sgirish } 82644961713Sgirish iteration++; 82744961713Sgirish } 82844961713Sgirish 82944961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 83052ccf843Smisaki "==> nxge_rxbuf_pp_to_vp: (search done)" 83152ccf843Smisaki "buf_pp $%p btype %d anchor_index %d", 83252ccf843Smisaki pkt_buf_addr_pp, 83352ccf843Smisaki pktbufsz_type, 83452ccf843Smisaki anchor_index)); 83544961713Sgirish } 83644961713Sgirish 83744961713Sgirish if (found == B_FALSE) { 83844961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 83952ccf843Smisaki "==> nxge_rxbuf_pp_to_vp: (search failed)" 84052ccf843Smisaki "buf_pp $%p btype %d anchor_index %d", 84152ccf843Smisaki pkt_buf_addr_pp, 84252ccf843Smisaki pktbufsz_type, 84352ccf843Smisaki anchor_index)); 84444961713Sgirish return (NXGE_ERROR); 84544961713Sgirish } 84644961713Sgirish 84744961713Sgirish found_index: 84844961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 84952ccf843Smisaki "==> nxge_rxbuf_pp_to_vp: (FOUND1)" 85052ccf843Smisaki "buf_pp $%p btype %d bufsize %d anchor_index %d", 85152ccf843Smisaki pkt_buf_addr_pp, 85252ccf843Smisaki pktbufsz_type, 85352ccf843Smisaki bufsize, 85452ccf843Smisaki anchor_index)); 85544961713Sgirish 85644961713Sgirish /* index of the first block in this chunk */ 85744961713Sgirish chunk_index = bufinfo[anchor_index].start_index; 85844961713Sgirish dvma_addr = bufinfo[anchor_index].dvma_addr; 85944961713Sgirish page_size_mask = ring_info->block_size_mask; 86044961713Sgirish 86144961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 86252ccf843Smisaki "==> nxge_rxbuf_pp_to_vp: (FOUND3), get chunk)" 86352ccf843Smisaki "buf_pp $%p btype %d bufsize %d " 86452ccf843Smisaki "anchor_index %d chunk_index %d dvma $%p", 86552ccf843Smisaki pkt_buf_addr_pp, 86652ccf843Smisaki pktbufsz_type, 86752ccf843Smisaki bufsize, 86852ccf843Smisaki anchor_index, 86952ccf843Smisaki chunk_index, 87052ccf843Smisaki dvma_addr)); 87144961713Sgirish 87244961713Sgirish offset = pktbuf_pp - dvma_addr; /* offset within the chunk */ 87344961713Sgirish block_size = rbr_p->block_size; /* System block(page) size */ 87444961713Sgirish 87544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 87652ccf843Smisaki "==> nxge_rxbuf_pp_to_vp: (FOUND4), get chunk)" 87752ccf843Smisaki "buf_pp $%p btype %d bufsize %d " 87852ccf843Smisaki "anchor_index %d chunk_index %d dvma $%p " 87952ccf843Smisaki "offset %d block_size %d", 88052ccf843Smisaki pkt_buf_addr_pp, 88152ccf843Smisaki pktbufsz_type, 88252ccf843Smisaki bufsize, 88352ccf843Smisaki anchor_index, 88452ccf843Smisaki chunk_index, 88552ccf843Smisaki dvma_addr, 88652ccf843Smisaki offset, 88752ccf843Smisaki block_size)); 88844961713Sgirish 88944961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> getting total index")); 89044961713Sgirish 89144961713Sgirish block_index = (offset / block_size); /* index within chunk */ 89244961713Sgirish total_index = chunk_index + block_index; 89344961713Sgirish 89444961713Sgirish 89544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 89652ccf843Smisaki "==> nxge_rxbuf_pp_to_vp: " 89752ccf843Smisaki "total_index %d dvma_addr $%p " 89852ccf843Smisaki "offset %d block_size %d " 89952ccf843Smisaki "block_index %d ", 90052ccf843Smisaki total_index, dvma_addr, 90152ccf843Smisaki offset, block_size, 90252ccf843Smisaki block_index)); 903adfcba55Sjoycey #if defined(__i386) 904adfcba55Sjoycey *pkt_buf_addr_p = (uint64_t *)((uint32_t)bufinfo[anchor_index].kaddr + 90552ccf843Smisaki (uint32_t)offset); 906adfcba55Sjoycey #else 907adfcba55Sjoycey *pkt_buf_addr_p = (uint64_t *)((uint64_t)bufinfo[anchor_index].kaddr + 90852ccf843Smisaki (uint64_t)offset); 909adfcba55Sjoycey #endif 91044961713Sgirish 91144961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 91252ccf843Smisaki "==> nxge_rxbuf_pp_to_vp: " 91352ccf843Smisaki "total_index %d dvma_addr $%p " 91452ccf843Smisaki "offset %d block_size %d " 91552ccf843Smisaki "block_index %d " 91652ccf843Smisaki "*pkt_buf_addr_p $%p", 91752ccf843Smisaki total_index, dvma_addr, 91852ccf843Smisaki offset, block_size, 91952ccf843Smisaki block_index, 92052ccf843Smisaki *pkt_buf_addr_p)); 92144961713Sgirish 92244961713Sgirish 92344961713Sgirish *msg_index = total_index; 92444961713Sgirish *bufoffset = (offset & page_size_mask); 92544961713Sgirish 92644961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 92752ccf843Smisaki "==> nxge_rxbuf_pp_to_vp: get msg index: " 92852ccf843Smisaki "msg_index %d bufoffset_index %d", 92952ccf843Smisaki *msg_index, 93052ccf843Smisaki *bufoffset)); 93144961713Sgirish 93244961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, "<== nxge_rxbuf_pp_to_vp")); 93344961713Sgirish 93444961713Sgirish return (NXGE_OK); 93544961713Sgirish } 93644961713Sgirish 93744961713Sgirish /* 93844961713Sgirish * used by quick sort (qsort) function 93944961713Sgirish * to perform comparison 94044961713Sgirish */ 94144961713Sgirish static int 94244961713Sgirish nxge_sort_compare(const void *p1, const void *p2) 94344961713Sgirish { 94444961713Sgirish 94544961713Sgirish rxbuf_index_info_t *a, *b; 94644961713Sgirish 94744961713Sgirish a = (rxbuf_index_info_t *)p1; 94844961713Sgirish b = (rxbuf_index_info_t *)p2; 94944961713Sgirish 95044961713Sgirish if (a->dvma_addr > b->dvma_addr) 95144961713Sgirish return (1); 95244961713Sgirish if (a->dvma_addr < b->dvma_addr) 95344961713Sgirish return (-1); 95444961713Sgirish return (0); 95544961713Sgirish } 95644961713Sgirish 95744961713Sgirish 95844961713Sgirish 95944961713Sgirish /* 96044961713Sgirish * grabbed this sort implementation from common/syscall/avl.c 96144961713Sgirish * 96244961713Sgirish */ 96344961713Sgirish /* 96444961713Sgirish * Generic shellsort, from K&R (1st ed, p 58.), somewhat modified. 96544961713Sgirish * v = Ptr to array/vector of objs 96644961713Sgirish * n = # objs in the array 96744961713Sgirish * s = size of each obj (must be multiples of a word size) 96844961713Sgirish * f = ptr to function to compare two objs 96944961713Sgirish * returns (-1 = less than, 0 = equal, 1 = greater than 97044961713Sgirish */ 97144961713Sgirish void 97244961713Sgirish nxge_ksort(caddr_t v, int n, int s, int (*f)()) 97344961713Sgirish { 97444961713Sgirish int g, i, j, ii; 97544961713Sgirish unsigned int *p1, *p2; 97644961713Sgirish unsigned int tmp; 97744961713Sgirish 97844961713Sgirish /* No work to do */ 97944961713Sgirish if (v == NULL || n <= 1) 98044961713Sgirish return; 98144961713Sgirish /* Sanity check on arguments */ 98244961713Sgirish ASSERT(((uintptr_t)v & 0x3) == 0 && (s & 0x3) == 0); 98344961713Sgirish ASSERT(s > 0); 98444961713Sgirish 98544961713Sgirish for (g = n / 2; g > 0; g /= 2) { 98644961713Sgirish for (i = g; i < n; i++) { 98744961713Sgirish for (j = i - g; j >= 0 && 98852ccf843Smisaki (*f)(v + j * s, v + (j + g) * s) == 1; 98952ccf843Smisaki j -= g) { 99044961713Sgirish p1 = (unsigned *)(v + j * s); 99144961713Sgirish p2 = (unsigned *)(v + (j + g) * s); 99244961713Sgirish for (ii = 0; ii < s / 4; ii++) { 99344961713Sgirish tmp = *p1; 99444961713Sgirish *p1++ = *p2; 99544961713Sgirish *p2++ = tmp; 99644961713Sgirish } 99744961713Sgirish } 99844961713Sgirish } 99944961713Sgirish } 100044961713Sgirish } 100144961713Sgirish 100244961713Sgirish /* 100344961713Sgirish * Initialize data structures required for rxdma 100444961713Sgirish * buffer dvma->vmem address lookup 100544961713Sgirish */ 100644961713Sgirish /*ARGSUSED*/ 100744961713Sgirish static nxge_status_t 100844961713Sgirish nxge_rxbuf_index_info_init(p_nxge_t nxgep, p_rx_rbr_ring_t rbrp) 100944961713Sgirish { 101044961713Sgirish 101144961713Sgirish int index; 101244961713Sgirish rxring_info_t *ring_info; 101344961713Sgirish int max_iteration = 0, max_index = 0; 101444961713Sgirish 101544961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_rxbuf_index_info_init")); 101644961713Sgirish 101744961713Sgirish ring_info = rbrp->ring_info; 101844961713Sgirish ring_info->hint[0] = NO_HINT; 101944961713Sgirish ring_info->hint[1] = NO_HINT; 102044961713Sgirish ring_info->hint[2] = NO_HINT; 102144961713Sgirish max_index = rbrp->num_blocks; 102244961713Sgirish 102344961713Sgirish /* read the DVMA address information and sort it */ 102444961713Sgirish /* do init of the information array */ 102544961713Sgirish 102644961713Sgirish 102744961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 102852ccf843Smisaki " nxge_rxbuf_index_info_init Sort ptrs")); 102944961713Sgirish 103044961713Sgirish /* sort the array */ 103144961713Sgirish nxge_ksort((void *)ring_info->buffer, max_index, 103252ccf843Smisaki sizeof (rxbuf_index_info_t), nxge_sort_compare); 103344961713Sgirish 103444961713Sgirish 103544961713Sgirish 103644961713Sgirish for (index = 0; index < max_index; index++) { 103744961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 103852ccf843Smisaki " nxge_rxbuf_index_info_init: sorted chunk %d " 103952ccf843Smisaki " ioaddr $%p kaddr $%p size %x", 104052ccf843Smisaki index, ring_info->buffer[index].dvma_addr, 104152ccf843Smisaki ring_info->buffer[index].kaddr, 104252ccf843Smisaki ring_info->buffer[index].buf_size)); 104344961713Sgirish } 104444961713Sgirish 104544961713Sgirish max_iteration = 0; 104644961713Sgirish while (max_index >= (1ULL << max_iteration)) 104744961713Sgirish max_iteration++; 104844961713Sgirish ring_info->max_iterations = max_iteration + 1; 104944961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 105052ccf843Smisaki " nxge_rxbuf_index_info_init Find max iter %d", 105152ccf843Smisaki ring_info->max_iterations)); 105244961713Sgirish 105344961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxbuf_index_info_init")); 105444961713Sgirish return (NXGE_OK); 105544961713Sgirish } 105644961713Sgirish 10570a8e077aSspeer /* ARGSUSED */ 105844961713Sgirish void 105944961713Sgirish nxge_dump_rcr_entry(p_nxge_t nxgep, p_rcr_entry_t entry_p) 106044961713Sgirish { 106144961713Sgirish #ifdef NXGE_DEBUG 106244961713Sgirish 106344961713Sgirish uint32_t bptr; 106444961713Sgirish uint64_t pp; 106544961713Sgirish 106644961713Sgirish bptr = entry_p->bits.hdw.pkt_buf_addr; 106744961713Sgirish 106844961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 106952ccf843Smisaki "\trcr entry $%p " 107052ccf843Smisaki "\trcr entry 0x%0llx " 107152ccf843Smisaki "\trcr entry 0x%08x " 107252ccf843Smisaki "\trcr entry 0x%08x " 107352ccf843Smisaki "\tvalue 0x%0llx\n" 107452ccf843Smisaki "\tmulti = %d\n" 107552ccf843Smisaki "\tpkt_type = 0x%x\n" 107652ccf843Smisaki "\tzero_copy = %d\n" 107752ccf843Smisaki "\tnoport = %d\n" 107852ccf843Smisaki "\tpromis = %d\n" 107952ccf843Smisaki "\terror = 0x%04x\n" 108052ccf843Smisaki "\tdcf_err = 0x%01x\n" 108152ccf843Smisaki "\tl2_len = %d\n" 108252ccf843Smisaki "\tpktbufsize = %d\n" 108352ccf843Smisaki "\tpkt_buf_addr = $%p\n" 108452ccf843Smisaki "\tpkt_buf_addr (<< 6) = $%p\n", 108552ccf843Smisaki entry_p, 108652ccf843Smisaki *(int64_t *)entry_p, 108752ccf843Smisaki *(int32_t *)entry_p, 108852ccf843Smisaki *(int32_t *)((char *)entry_p + 32), 108952ccf843Smisaki entry_p->value, 109052ccf843Smisaki entry_p->bits.hdw.multi, 109152ccf843Smisaki entry_p->bits.hdw.pkt_type, 109252ccf843Smisaki entry_p->bits.hdw.zero_copy, 109352ccf843Smisaki entry_p->bits.hdw.noport, 109452ccf843Smisaki entry_p->bits.hdw.promis, 109552ccf843Smisaki entry_p->bits.hdw.error, 109652ccf843Smisaki entry_p->bits.hdw.dcf_err, 109752ccf843Smisaki entry_p->bits.hdw.l2_len, 109852ccf843Smisaki entry_p->bits.hdw.pktbufsz, 109952ccf843Smisaki bptr, 110052ccf843Smisaki entry_p->bits.ldw.pkt_buf_addr)); 110144961713Sgirish 110244961713Sgirish pp = (entry_p->value & RCR_PKT_BUF_ADDR_MASK) << 110352ccf843Smisaki RCR_PKT_BUF_ADDR_SHIFT; 110444961713Sgirish 110544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "rcr pp 0x%llx l2 len %d", 110652ccf843Smisaki pp, (*(int64_t *)entry_p >> 40) & 0x3fff)); 110744961713Sgirish #endif 110844961713Sgirish } 110944961713Sgirish 111044961713Sgirish void 111144961713Sgirish nxge_rxdma_regs_dump(p_nxge_t nxgep, int rdc) 111244961713Sgirish { 111344961713Sgirish npi_handle_t handle; 111444961713Sgirish rbr_stat_t rbr_stat; 111544961713Sgirish addr44_t hd_addr; 111644961713Sgirish addr44_t tail_addr; 111744961713Sgirish uint16_t qlen; 111844961713Sgirish 111944961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 112052ccf843Smisaki "==> nxge_rxdma_regs_dump: rdc channel %d", rdc)); 112144961713Sgirish 112244961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 112344961713Sgirish 112444961713Sgirish /* RBR head */ 112544961713Sgirish hd_addr.addr = 0; 112644961713Sgirish (void) npi_rxdma_rdc_rbr_head_get(handle, rdc, &hd_addr); 1127adfcba55Sjoycey #if defined(__i386) 112853f3d8ecSyc printf("nxge_rxdma_regs_dump: got hdptr $%p \n", 112952ccf843Smisaki (void *)(uint32_t)hd_addr.addr); 1130adfcba55Sjoycey #else 113153f3d8ecSyc printf("nxge_rxdma_regs_dump: got hdptr $%p \n", 113252ccf843Smisaki (void *)hd_addr.addr); 1133adfcba55Sjoycey #endif 113444961713Sgirish 113544961713Sgirish /* RBR stats */ 113644961713Sgirish (void) npi_rxdma_rdc_rbr_stat_get(handle, rdc, &rbr_stat); 113744961713Sgirish printf("nxge_rxdma_regs_dump: rbr len %d \n", rbr_stat.bits.ldw.qlen); 113844961713Sgirish 113944961713Sgirish /* RCR tail */ 114044961713Sgirish tail_addr.addr = 0; 114144961713Sgirish (void) npi_rxdma_rdc_rcr_tail_get(handle, rdc, &tail_addr); 1142adfcba55Sjoycey #if defined(__i386) 114353f3d8ecSyc printf("nxge_rxdma_regs_dump: got tail ptr $%p \n", 114452ccf843Smisaki (void *)(uint32_t)tail_addr.addr); 1145adfcba55Sjoycey #else 114653f3d8ecSyc printf("nxge_rxdma_regs_dump: got tail ptr $%p \n", 114752ccf843Smisaki (void *)tail_addr.addr); 1148adfcba55Sjoycey #endif 114944961713Sgirish 115044961713Sgirish /* RCR qlen */ 115144961713Sgirish (void) npi_rxdma_rdc_rcr_qlen_get(handle, rdc, &qlen); 115244961713Sgirish printf("nxge_rxdma_regs_dump: rcr len %x \n", qlen); 115344961713Sgirish 115444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 115552ccf843Smisaki "<== nxge_rxdma_regs_dump: rdc rdc %d", rdc)); 115644961713Sgirish } 115744961713Sgirish 115844961713Sgirish void 115944961713Sgirish nxge_rxdma_stop(p_nxge_t nxgep) 116044961713Sgirish { 116144961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop")); 116244961713Sgirish 116344961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 116444961713Sgirish (void) nxge_rx_mac_disable(nxgep); 116544961713Sgirish (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 116644961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_stop")); 116744961713Sgirish } 116844961713Sgirish 116944961713Sgirish void 117044961713Sgirish nxge_rxdma_stop_reinit(p_nxge_t nxgep) 117144961713Sgirish { 117244961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_reinit")); 117344961713Sgirish 117444961713Sgirish (void) nxge_rxdma_stop(nxgep); 117544961713Sgirish (void) nxge_uninit_rxdma_channels(nxgep); 117644961713Sgirish (void) nxge_init_rxdma_channels(nxgep); 117744961713Sgirish 117844961713Sgirish #ifndef AXIS_DEBUG_LB 117944961713Sgirish (void) nxge_xcvr_init(nxgep); 118044961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 118144961713Sgirish #endif 118244961713Sgirish (void) nxge_rx_mac_enable(nxgep); 118344961713Sgirish 118444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_stop_reinit")); 118544961713Sgirish } 118644961713Sgirish 118744961713Sgirish nxge_status_t 118844961713Sgirish nxge_rxdma_hw_mode(p_nxge_t nxgep, boolean_t enable) 118944961713Sgirish { 1190678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set; 1191678453a8Sspeer nxge_status_t status; 1192678453a8Sspeer npi_status_t rs; 1193678453a8Sspeer int rdc; 119444961713Sgirish 119544961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 119652ccf843Smisaki "==> nxge_rxdma_hw_mode: mode %d", enable)); 119744961713Sgirish 119844961713Sgirish if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 119944961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 1200678453a8Sspeer "<== nxge_rxdma_mode: not initialized")); 120144961713Sgirish return (NXGE_ERROR); 120244961713Sgirish } 120344961713Sgirish 1204678453a8Sspeer if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) { 1205678453a8Sspeer NXGE_DEBUG_MSG((nxgep, TX_CTL, 1206678453a8Sspeer "<== nxge_tx_port_fatal_err_recover: " 1207678453a8Sspeer "NULL ring pointer(s)")); 120844961713Sgirish return (NXGE_ERROR); 120944961713Sgirish } 121044961713Sgirish 1211678453a8Sspeer if (set->owned.map == 0) { 121244961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 1213678453a8Sspeer "nxge_rxdma_regs_dump_channels: no channels")); 1214678453a8Sspeer return (NULL); 121544961713Sgirish } 121644961713Sgirish 1217678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1218678453a8Sspeer if ((1 << rdc) & set->owned.map) { 1219678453a8Sspeer rx_rbr_ring_t *ring = 1220678453a8Sspeer nxgep->rx_rbr_rings->rbr_rings[rdc]; 1221678453a8Sspeer npi_handle_t handle = NXGE_DEV_NPI_HANDLE(nxgep); 1222678453a8Sspeer if (ring) { 1223678453a8Sspeer if (enable) { 1224678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1225678453a8Sspeer "==> nxge_rxdma_hw_mode: " 1226678453a8Sspeer "channel %d (enable)", rdc)); 1227678453a8Sspeer rs = npi_rxdma_cfg_rdc_enable 1228678453a8Sspeer (handle, rdc); 1229678453a8Sspeer } else { 1230678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1231678453a8Sspeer "==> nxge_rxdma_hw_mode: " 1232678453a8Sspeer "channel %d disable)", rdc)); 1233678453a8Sspeer rs = npi_rxdma_cfg_rdc_disable 1234678453a8Sspeer (handle, rdc); 1235678453a8Sspeer } 1236678453a8Sspeer } 123744961713Sgirish } 123844961713Sgirish } 123944961713Sgirish 124044961713Sgirish status = ((rs == NPI_SUCCESS) ? NXGE_OK : NXGE_ERROR | rs); 124144961713Sgirish 124244961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 124352ccf843Smisaki "<== nxge_rxdma_hw_mode: status 0x%x", status)); 124444961713Sgirish 124544961713Sgirish return (status); 124644961713Sgirish } 124744961713Sgirish 124844961713Sgirish void 124944961713Sgirish nxge_rxdma_enable_channel(p_nxge_t nxgep, uint16_t channel) 125044961713Sgirish { 125144961713Sgirish npi_handle_t handle; 125244961713Sgirish 125344961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 125452ccf843Smisaki "==> nxge_rxdma_enable_channel: channel %d", channel)); 125544961713Sgirish 125644961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 125744961713Sgirish (void) npi_rxdma_cfg_rdc_enable(handle, channel); 125844961713Sgirish 125944961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxdma_enable_channel")); 126044961713Sgirish } 126144961713Sgirish 126244961713Sgirish void 126344961713Sgirish nxge_rxdma_disable_channel(p_nxge_t nxgep, uint16_t channel) 126444961713Sgirish { 126544961713Sgirish npi_handle_t handle; 126644961713Sgirish 126744961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 126852ccf843Smisaki "==> nxge_rxdma_disable_channel: channel %d", channel)); 126944961713Sgirish 127044961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 127144961713Sgirish (void) npi_rxdma_cfg_rdc_disable(handle, channel); 127244961713Sgirish 127344961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxdma_disable_channel")); 127444961713Sgirish } 127544961713Sgirish 127644961713Sgirish void 127744961713Sgirish nxge_hw_start_rx(p_nxge_t nxgep) 127844961713Sgirish { 127944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_start_rx")); 128044961713Sgirish 128144961713Sgirish (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_START); 128244961713Sgirish (void) nxge_rx_mac_enable(nxgep); 128344961713Sgirish 128444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_start_rx")); 128544961713Sgirish } 128644961713Sgirish 128744961713Sgirish /*ARGSUSED*/ 128844961713Sgirish void 128944961713Sgirish nxge_fixup_rxdma_rings(p_nxge_t nxgep) 129044961713Sgirish { 1291678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set; 1292678453a8Sspeer int rdc; 129344961713Sgirish 129444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_fixup_rxdma_rings")); 129544961713Sgirish 1296678453a8Sspeer if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) { 1297678453a8Sspeer NXGE_DEBUG_MSG((nxgep, TX_CTL, 1298678453a8Sspeer "<== nxge_tx_port_fatal_err_recover: " 1299678453a8Sspeer "NULL ring pointer(s)")); 130044961713Sgirish return; 130144961713Sgirish } 130244961713Sgirish 1303678453a8Sspeer if (set->owned.map == 0) { 130444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 1305678453a8Sspeer "nxge_rxdma_regs_dump_channels: no channels")); 130644961713Sgirish return; 130744961713Sgirish } 130844961713Sgirish 1309678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1310678453a8Sspeer if ((1 << rdc) & set->owned.map) { 1311678453a8Sspeer rx_rbr_ring_t *ring = 1312678453a8Sspeer nxgep->rx_rbr_rings->rbr_rings[rdc]; 1313678453a8Sspeer if (ring) { 1314678453a8Sspeer nxge_rxdma_hw_stop(nxgep, rdc); 1315678453a8Sspeer NXGE_DEBUG_MSG((nxgep, RX_CTL, 131652ccf843Smisaki "==> nxge_fixup_rxdma_rings: " 131752ccf843Smisaki "channel %d ring $%px", 131852ccf843Smisaki rdc, ring)); 1319678453a8Sspeer (void) nxge_rxdma_fixup_channel 1320678453a8Sspeer (nxgep, rdc, rdc); 1321678453a8Sspeer } 1322678453a8Sspeer } 132344961713Sgirish } 132444961713Sgirish 132544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_fixup_rxdma_rings")); 132644961713Sgirish } 132744961713Sgirish 132844961713Sgirish void 132944961713Sgirish nxge_rxdma_fix_channel(p_nxge_t nxgep, uint16_t channel) 133044961713Sgirish { 133144961713Sgirish int i; 133244961713Sgirish 133344961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fix_channel")); 133444961713Sgirish i = nxge_rxdma_get_ring_index(nxgep, channel); 133544961713Sgirish if (i < 0) { 133644961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 133752ccf843Smisaki "<== nxge_rxdma_fix_channel: no entry found")); 133844961713Sgirish return; 133944961713Sgirish } 134044961713Sgirish 134144961713Sgirish nxge_rxdma_fixup_channel(nxgep, channel, i); 134244961713Sgirish 1343678453a8Sspeer NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_fix_channel")); 134444961713Sgirish } 134544961713Sgirish 134644961713Sgirish void 134744961713Sgirish nxge_rxdma_fixup_channel(p_nxge_t nxgep, uint16_t channel, int entry) 134844961713Sgirish { 134944961713Sgirish int ndmas; 135044961713Sgirish p_rx_rbr_rings_t rx_rbr_rings; 135144961713Sgirish p_rx_rbr_ring_t *rbr_rings; 135244961713Sgirish p_rx_rcr_rings_t rx_rcr_rings; 135344961713Sgirish p_rx_rcr_ring_t *rcr_rings; 135444961713Sgirish p_rx_mbox_areas_t rx_mbox_areas_p; 135544961713Sgirish p_rx_mbox_t *rx_mbox_p; 135644961713Sgirish p_nxge_dma_pool_t dma_buf_poolp; 135744961713Sgirish p_nxge_dma_pool_t dma_cntl_poolp; 135844961713Sgirish p_rx_rbr_ring_t rbrp; 135944961713Sgirish p_rx_rcr_ring_t rcrp; 136044961713Sgirish p_rx_mbox_t mboxp; 136144961713Sgirish p_nxge_dma_common_t dmap; 136244961713Sgirish nxge_status_t status = NXGE_OK; 136344961713Sgirish 136444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fixup_channel")); 136544961713Sgirish 136644961713Sgirish (void) nxge_rxdma_stop_channel(nxgep, channel); 136744961713Sgirish 136844961713Sgirish dma_buf_poolp = nxgep->rx_buf_pool_p; 136944961713Sgirish dma_cntl_poolp = nxgep->rx_cntl_pool_p; 137044961713Sgirish 137144961713Sgirish if (!dma_buf_poolp->buf_allocated || !dma_cntl_poolp->buf_allocated) { 137244961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 137352ccf843Smisaki "<== nxge_rxdma_fixup_channel: buf not allocated")); 137444961713Sgirish return; 137544961713Sgirish } 137644961713Sgirish 137744961713Sgirish ndmas = dma_buf_poolp->ndmas; 137844961713Sgirish if (!ndmas) { 137944961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 138052ccf843Smisaki "<== nxge_rxdma_fixup_channel: no dma allocated")); 138144961713Sgirish return; 138244961713Sgirish } 138344961713Sgirish 1384a3c5bd6dSspeer rx_rbr_rings = nxgep->rx_rbr_rings; 138544961713Sgirish rx_rcr_rings = nxgep->rx_rcr_rings; 138644961713Sgirish rbr_rings = rx_rbr_rings->rbr_rings; 138744961713Sgirish rcr_rings = rx_rcr_rings->rcr_rings; 138844961713Sgirish rx_mbox_areas_p = nxgep->rx_mbox_areas_p; 138944961713Sgirish rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 139044961713Sgirish 139144961713Sgirish /* Reinitialize the receive block and completion rings */ 139244961713Sgirish rbrp = (p_rx_rbr_ring_t)rbr_rings[entry], 139352ccf843Smisaki rcrp = (p_rx_rcr_ring_t)rcr_rings[entry], 139452ccf843Smisaki mboxp = (p_rx_mbox_t)rx_mbox_p[entry]; 139544961713Sgirish 139644961713Sgirish 139744961713Sgirish rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 139844961713Sgirish rbrp->rbr_rd_index = 0; 139944961713Sgirish rcrp->comp_rd_index = 0; 140044961713Sgirish rcrp->comp_wt_index = 0; 140144961713Sgirish 140244961713Sgirish dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 140344961713Sgirish bzero((caddr_t)dmap->kaddrp, dmap->alength); 140444961713Sgirish 140544961713Sgirish status = nxge_rxdma_start_channel(nxgep, channel, 140652ccf843Smisaki rbrp, rcrp, mboxp); 140744961713Sgirish if (status != NXGE_OK) { 140844961713Sgirish goto nxge_rxdma_fixup_channel_fail; 140944961713Sgirish } 141044961713Sgirish if (status != NXGE_OK) { 141144961713Sgirish goto nxge_rxdma_fixup_channel_fail; 141244961713Sgirish } 141344961713Sgirish 141444961713Sgirish nxge_rxdma_fixup_channel_fail: 141544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 141652ccf843Smisaki "==> nxge_rxdma_fixup_channel: failed (0x%08x)", status)); 141744961713Sgirish 141844961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_fixup_channel")); 141944961713Sgirish } 142044961713Sgirish 1421678453a8Sspeer /* ARGSUSED */ 142244961713Sgirish int 142344961713Sgirish nxge_rxdma_get_ring_index(p_nxge_t nxgep, uint16_t channel) 142444961713Sgirish { 1425678453a8Sspeer return (channel); 142644961713Sgirish } 142744961713Sgirish 142844961713Sgirish p_rx_rbr_ring_t 142944961713Sgirish nxge_rxdma_get_rbr_ring(p_nxge_t nxgep, uint16_t channel) 143044961713Sgirish { 1431678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set; 1432678453a8Sspeer nxge_channel_t rdc; 143344961713Sgirish 143444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 143552ccf843Smisaki "==> nxge_rxdma_get_rbr_ring: channel %d", channel)); 143644961713Sgirish 1437678453a8Sspeer if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) { 1438678453a8Sspeer NXGE_DEBUG_MSG((nxgep, TX_CTL, 1439678453a8Sspeer "<== nxge_rxdma_get_rbr_ring: " 1440678453a8Sspeer "NULL ring pointer(s)")); 144144961713Sgirish return (NULL); 144244961713Sgirish } 1443678453a8Sspeer 1444678453a8Sspeer if (set->owned.map == 0) { 144544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 1446678453a8Sspeer "<== nxge_rxdma_get_rbr_ring: no channels")); 144744961713Sgirish return (NULL); 144844961713Sgirish } 144944961713Sgirish 1450678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1451678453a8Sspeer if ((1 << rdc) & set->owned.map) { 1452678453a8Sspeer rx_rbr_ring_t *ring = 1453678453a8Sspeer nxgep->rx_rbr_rings->rbr_rings[rdc]; 1454678453a8Sspeer if (ring) { 1455678453a8Sspeer if (channel == ring->rdc) { 1456678453a8Sspeer NXGE_DEBUG_MSG((nxgep, RX_CTL, 1457678453a8Sspeer "==> nxge_rxdma_get_rbr_ring: " 1458678453a8Sspeer "channel %d ring $%p", rdc, ring)); 1459678453a8Sspeer return (ring); 1460678453a8Sspeer } 1461678453a8Sspeer } 146244961713Sgirish } 146344961713Sgirish } 146444961713Sgirish 146544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 146652ccf843Smisaki "<== nxge_rxdma_get_rbr_ring: not found")); 146744961713Sgirish 146844961713Sgirish return (NULL); 146944961713Sgirish } 147044961713Sgirish 147144961713Sgirish p_rx_rcr_ring_t 147244961713Sgirish nxge_rxdma_get_rcr_ring(p_nxge_t nxgep, uint16_t channel) 147344961713Sgirish { 1474678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set; 1475678453a8Sspeer nxge_channel_t rdc; 147644961713Sgirish 147744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 147852ccf843Smisaki "==> nxge_rxdma_get_rcr_ring: channel %d", channel)); 147944961713Sgirish 1480678453a8Sspeer if (nxgep->rx_rcr_rings == 0 || nxgep->rx_rcr_rings->rcr_rings == 0) { 1481678453a8Sspeer NXGE_DEBUG_MSG((nxgep, TX_CTL, 1482678453a8Sspeer "<== nxge_rxdma_get_rcr_ring: " 1483678453a8Sspeer "NULL ring pointer(s)")); 148444961713Sgirish return (NULL); 148544961713Sgirish } 1486678453a8Sspeer 1487678453a8Sspeer if (set->owned.map == 0) { 148844961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 1489678453a8Sspeer "<== nxge_rxdma_get_rbr_ring: no channels")); 149044961713Sgirish return (NULL); 149144961713Sgirish } 149244961713Sgirish 1493678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1494678453a8Sspeer if ((1 << rdc) & set->owned.map) { 1495678453a8Sspeer rx_rcr_ring_t *ring = 1496678453a8Sspeer nxgep->rx_rcr_rings->rcr_rings[rdc]; 1497678453a8Sspeer if (ring) { 1498678453a8Sspeer if (channel == ring->rdc) { 1499678453a8Sspeer NXGE_DEBUG_MSG((nxgep, RX_CTL, 1500678453a8Sspeer "==> nxge_rxdma_get_rcr_ring: " 1501678453a8Sspeer "channel %d ring $%p", rdc, ring)); 1502678453a8Sspeer return (ring); 1503678453a8Sspeer } 1504678453a8Sspeer } 150544961713Sgirish } 150644961713Sgirish } 150744961713Sgirish 150844961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 150952ccf843Smisaki "<== nxge_rxdma_get_rcr_ring: not found")); 151044961713Sgirish 151144961713Sgirish return (NULL); 151244961713Sgirish } 151344961713Sgirish 151444961713Sgirish /* 151544961713Sgirish * Static functions start here. 151644961713Sgirish */ 151744961713Sgirish static p_rx_msg_t 151844961713Sgirish nxge_allocb(size_t size, uint32_t pri, p_nxge_dma_common_t dmabuf_p) 151944961713Sgirish { 152044961713Sgirish p_rx_msg_t nxge_mp = NULL; 152144961713Sgirish p_nxge_dma_common_t dmamsg_p; 152244961713Sgirish uchar_t *buffer; 152344961713Sgirish 152444961713Sgirish nxge_mp = KMEM_ZALLOC(sizeof (rx_msg_t), KM_NOSLEEP); 152544961713Sgirish if (nxge_mp == NULL) { 152656d930aeSspeer NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 152752ccf843Smisaki "Allocation of a rx msg failed.")); 152844961713Sgirish goto nxge_allocb_exit; 152944961713Sgirish } 153044961713Sgirish 153144961713Sgirish nxge_mp->use_buf_pool = B_FALSE; 153244961713Sgirish if (dmabuf_p) { 153344961713Sgirish nxge_mp->use_buf_pool = B_TRUE; 153444961713Sgirish dmamsg_p = (p_nxge_dma_common_t)&nxge_mp->buf_dma; 153544961713Sgirish *dmamsg_p = *dmabuf_p; 153644961713Sgirish dmamsg_p->nblocks = 1; 153744961713Sgirish dmamsg_p->block_size = size; 153844961713Sgirish dmamsg_p->alength = size; 153944961713Sgirish buffer = (uchar_t *)dmabuf_p->kaddrp; 154044961713Sgirish 154144961713Sgirish dmabuf_p->kaddrp = (void *) 154252ccf843Smisaki ((char *)dmabuf_p->kaddrp + size); 154344961713Sgirish dmabuf_p->ioaddr_pp = (void *) 154452ccf843Smisaki ((char *)dmabuf_p->ioaddr_pp + size); 154544961713Sgirish dmabuf_p->alength -= size; 154644961713Sgirish dmabuf_p->offset += size; 154744961713Sgirish dmabuf_p->dma_cookie.dmac_laddress += size; 154844961713Sgirish dmabuf_p->dma_cookie.dmac_size -= size; 154944961713Sgirish 155044961713Sgirish } else { 155144961713Sgirish buffer = KMEM_ALLOC(size, KM_NOSLEEP); 155244961713Sgirish if (buffer == NULL) { 155356d930aeSspeer NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 155452ccf843Smisaki "Allocation of a receive page failed.")); 155544961713Sgirish goto nxge_allocb_fail1; 155644961713Sgirish } 155744961713Sgirish } 155844961713Sgirish 155944961713Sgirish nxge_mp->rx_mblk_p = desballoc(buffer, size, pri, &nxge_mp->freeb); 156044961713Sgirish if (nxge_mp->rx_mblk_p == NULL) { 156156d930aeSspeer NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, "desballoc failed.")); 156244961713Sgirish goto nxge_allocb_fail2; 156344961713Sgirish } 156444961713Sgirish 156544961713Sgirish nxge_mp->buffer = buffer; 156644961713Sgirish nxge_mp->block_size = size; 156744961713Sgirish nxge_mp->freeb.free_func = (void (*)())nxge_freeb; 156844961713Sgirish nxge_mp->freeb.free_arg = (caddr_t)nxge_mp; 156944961713Sgirish nxge_mp->ref_cnt = 1; 157044961713Sgirish nxge_mp->free = B_TRUE; 157144961713Sgirish nxge_mp->rx_use_bcopy = B_FALSE; 157244961713Sgirish 157314ea4bb7Ssd atomic_inc_32(&nxge_mblks_pending); 157444961713Sgirish 157544961713Sgirish goto nxge_allocb_exit; 157644961713Sgirish 157744961713Sgirish nxge_allocb_fail2: 157844961713Sgirish if (!nxge_mp->use_buf_pool) { 157944961713Sgirish KMEM_FREE(buffer, size); 158044961713Sgirish } 158144961713Sgirish 158244961713Sgirish nxge_allocb_fail1: 158344961713Sgirish KMEM_FREE(nxge_mp, sizeof (rx_msg_t)); 158444961713Sgirish nxge_mp = NULL; 158544961713Sgirish 158644961713Sgirish nxge_allocb_exit: 158744961713Sgirish return (nxge_mp); 158844961713Sgirish } 158944961713Sgirish 159044961713Sgirish p_mblk_t 159144961713Sgirish nxge_dupb(p_rx_msg_t nxge_mp, uint_t offset, size_t size) 159244961713Sgirish { 159344961713Sgirish p_mblk_t mp; 159444961713Sgirish 159544961713Sgirish NXGE_DEBUG_MSG((NULL, MEM_CTL, "==> nxge_dupb")); 159644961713Sgirish NXGE_DEBUG_MSG((NULL, MEM_CTL, "nxge_mp = $%p " 159752ccf843Smisaki "offset = 0x%08X " 159852ccf843Smisaki "size = 0x%08X", 159952ccf843Smisaki nxge_mp, offset, size)); 160044961713Sgirish 160144961713Sgirish mp = desballoc(&nxge_mp->buffer[offset], size, 160252ccf843Smisaki 0, &nxge_mp->freeb); 160344961713Sgirish if (mp == NULL) { 160444961713Sgirish NXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 160544961713Sgirish goto nxge_dupb_exit; 160644961713Sgirish } 160744961713Sgirish atomic_inc_32(&nxge_mp->ref_cnt); 160844961713Sgirish 160944961713Sgirish 161044961713Sgirish nxge_dupb_exit: 161144961713Sgirish NXGE_DEBUG_MSG((NULL, MEM_CTL, "<== nxge_dupb mp = $%p", 161252ccf843Smisaki nxge_mp)); 161344961713Sgirish return (mp); 161444961713Sgirish } 161544961713Sgirish 161644961713Sgirish p_mblk_t 161744961713Sgirish nxge_dupb_bcopy(p_rx_msg_t nxge_mp, uint_t offset, size_t size) 161844961713Sgirish { 161944961713Sgirish p_mblk_t mp; 162044961713Sgirish uchar_t *dp; 162144961713Sgirish 162244961713Sgirish mp = allocb(size + NXGE_RXBUF_EXTRA, 0); 162344961713Sgirish if (mp == NULL) { 162444961713Sgirish NXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 162544961713Sgirish goto nxge_dupb_bcopy_exit; 162644961713Sgirish } 162744961713Sgirish dp = mp->b_rptr = mp->b_rptr + NXGE_RXBUF_EXTRA; 162844961713Sgirish bcopy((void *)&nxge_mp->buffer[offset], dp, size); 162944961713Sgirish mp->b_wptr = dp + size; 163044961713Sgirish 163144961713Sgirish nxge_dupb_bcopy_exit: 163244961713Sgirish NXGE_DEBUG_MSG((NULL, MEM_CTL, "<== nxge_dupb mp = $%p", 163352ccf843Smisaki nxge_mp)); 163444961713Sgirish return (mp); 163544961713Sgirish } 163644961713Sgirish 163744961713Sgirish void nxge_post_page(p_nxge_t nxgep, p_rx_rbr_ring_t rx_rbr_p, 163844961713Sgirish p_rx_msg_t rx_msg_p); 163944961713Sgirish 164044961713Sgirish void 164144961713Sgirish nxge_post_page(p_nxge_t nxgep, p_rx_rbr_ring_t rx_rbr_p, p_rx_msg_t rx_msg_p) 164244961713Sgirish { 164344961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_post_page")); 164444961713Sgirish 164544961713Sgirish /* Reuse this buffer */ 164644961713Sgirish rx_msg_p->free = B_FALSE; 164744961713Sgirish rx_msg_p->cur_usage_cnt = 0; 164844961713Sgirish rx_msg_p->max_usage_cnt = 0; 164944961713Sgirish rx_msg_p->pkt_buf_size = 0; 165044961713Sgirish 165144961713Sgirish if (rx_rbr_p->rbr_use_bcopy) { 165244961713Sgirish rx_msg_p->rx_use_bcopy = B_FALSE; 165344961713Sgirish atomic_dec_32(&rx_rbr_p->rbr_consumed); 165444961713Sgirish } 165544961713Sgirish 165644961713Sgirish /* 165744961713Sgirish * Get the rbr header pointer and its offset index. 165844961713Sgirish */ 165944961713Sgirish MUTEX_ENTER(&rx_rbr_p->post_lock); 166044961713Sgirish rx_rbr_p->rbr_wr_index = ((rx_rbr_p->rbr_wr_index + 1) & 166152ccf843Smisaki rx_rbr_p->rbr_wrap_mask); 166244961713Sgirish rx_rbr_p->rbr_desc_vp[rx_rbr_p->rbr_wr_index] = rx_msg_p->shifted_addr; 166344961713Sgirish MUTEX_EXIT(&rx_rbr_p->post_lock); 166430ac2e7bSml npi_rxdma_rdc_rbr_kick(NXGE_DEV_NPI_HANDLE(nxgep), 166530ac2e7bSml rx_rbr_p->rdc, 1); 166644961713Sgirish 166744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 166852ccf843Smisaki "<== nxge_post_page (channel %d post_next_index %d)", 166952ccf843Smisaki rx_rbr_p->rdc, rx_rbr_p->rbr_wr_index)); 167044961713Sgirish 167144961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_post_page")); 167244961713Sgirish } 167344961713Sgirish 167444961713Sgirish void 167544961713Sgirish nxge_freeb(p_rx_msg_t rx_msg_p) 167644961713Sgirish { 167744961713Sgirish size_t size; 167844961713Sgirish uchar_t *buffer = NULL; 167944961713Sgirish int ref_cnt; 1680958cea9eSml boolean_t free_state = B_FALSE; 168144961713Sgirish 1682007969e0Stm rx_rbr_ring_t *ring = rx_msg_p->rx_rbr_p; 1683007969e0Stm 168444961713Sgirish NXGE_DEBUG_MSG((NULL, MEM2_CTL, "==> nxge_freeb")); 168544961713Sgirish NXGE_DEBUG_MSG((NULL, MEM2_CTL, 168652ccf843Smisaki "nxge_freeb:rx_msg_p = $%p (block pending %d)", 168752ccf843Smisaki rx_msg_p, nxge_mblks_pending)); 168844961713Sgirish 1689958cea9eSml /* 1690958cea9eSml * First we need to get the free state, then 1691958cea9eSml * atomic decrement the reference count to prevent 1692958cea9eSml * the race condition with the interrupt thread that 1693958cea9eSml * is processing a loaned up buffer block. 1694958cea9eSml */ 1695958cea9eSml free_state = rx_msg_p->free; 1696958cea9eSml ref_cnt = atomic_add_32_nv(&rx_msg_p->ref_cnt, -1); 169744961713Sgirish if (!ref_cnt) { 169830ac2e7bSml atomic_dec_32(&nxge_mblks_pending); 169944961713Sgirish buffer = rx_msg_p->buffer; 170044961713Sgirish size = rx_msg_p->block_size; 170144961713Sgirish NXGE_DEBUG_MSG((NULL, MEM2_CTL, "nxge_freeb: " 170252ccf843Smisaki "will free: rx_msg_p = $%p (block pending %d)", 170352ccf843Smisaki rx_msg_p, nxge_mblks_pending)); 170444961713Sgirish 170544961713Sgirish if (!rx_msg_p->use_buf_pool) { 170644961713Sgirish KMEM_FREE(buffer, size); 170744961713Sgirish } 170814ea4bb7Ssd 170914ea4bb7Ssd KMEM_FREE(rx_msg_p, sizeof (rx_msg_t)); 1710007969e0Stm 17113e82a89eSmisaki if (ring) { 17123e82a89eSmisaki /* 17133e82a89eSmisaki * Decrement the receive buffer ring's reference 17143e82a89eSmisaki * count, too. 17153e82a89eSmisaki */ 17163e82a89eSmisaki atomic_dec_32(&ring->rbr_ref_cnt); 1717007969e0Stm 17183e82a89eSmisaki /* 1719678453a8Sspeer * Free the receive buffer ring, if 17203e82a89eSmisaki * 1. all the receive buffers have been freed 17213e82a89eSmisaki * 2. and we are in the proper state (that is, 17223e82a89eSmisaki * we are not UNMAPPING). 17233e82a89eSmisaki */ 17243e82a89eSmisaki if (ring->rbr_ref_cnt == 0 && 17253e82a89eSmisaki ring->rbr_state == RBR_UNMAPPED) { 1726678453a8Sspeer /* 1727678453a8Sspeer * Free receive data buffers, 1728678453a8Sspeer * buffer index information 1729678453a8Sspeer * (rxring_info) and 1730678453a8Sspeer * the message block ring. 1731678453a8Sspeer */ 1732678453a8Sspeer NXGE_DEBUG_MSG((NULL, RX_CTL, 1733678453a8Sspeer "nxge_freeb:rx_msg_p = $%p " 1734678453a8Sspeer "(block pending %d) free buffers", 1735678453a8Sspeer rx_msg_p, nxge_mblks_pending)); 1736678453a8Sspeer nxge_rxdma_databuf_free(ring); 1737678453a8Sspeer if (ring->ring_info) { 1738678453a8Sspeer KMEM_FREE(ring->ring_info, 1739678453a8Sspeer sizeof (rxring_info_t)); 1740678453a8Sspeer } 1741678453a8Sspeer 1742678453a8Sspeer if (ring->rx_msg_ring) { 1743678453a8Sspeer KMEM_FREE(ring->rx_msg_ring, 1744678453a8Sspeer ring->tnblocks * 1745678453a8Sspeer sizeof (p_rx_msg_t)); 1746678453a8Sspeer } 17473e82a89eSmisaki KMEM_FREE(ring, sizeof (*ring)); 17483e82a89eSmisaki } 1749007969e0Stm } 175014ea4bb7Ssd return; 175144961713Sgirish } 175244961713Sgirish 175344961713Sgirish /* 175444961713Sgirish * Repost buffer. 175544961713Sgirish */ 17563e82a89eSmisaki if (free_state && (ref_cnt == 1) && ring) { 175744961713Sgirish NXGE_DEBUG_MSG((NULL, RX_CTL, 175844961713Sgirish "nxge_freeb: post page $%p:", rx_msg_p)); 1759007969e0Stm if (ring->rbr_state == RBR_POSTING) 1760007969e0Stm nxge_post_page(rx_msg_p->nxgep, ring, rx_msg_p); 176144961713Sgirish } 176244961713Sgirish 176344961713Sgirish NXGE_DEBUG_MSG((NULL, MEM2_CTL, "<== nxge_freeb")); 176444961713Sgirish } 176544961713Sgirish 176644961713Sgirish uint_t 176744961713Sgirish nxge_rx_intr(void *arg1, void *arg2) 176844961713Sgirish { 176944961713Sgirish p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 177044961713Sgirish p_nxge_t nxgep = (p_nxge_t)arg2; 177144961713Sgirish p_nxge_ldg_t ldgp; 177244961713Sgirish uint8_t channel; 177344961713Sgirish npi_handle_t handle; 177444961713Sgirish rx_dma_ctl_stat_t cs; 177544961713Sgirish 177644961713Sgirish #ifdef NXGE_DEBUG 177744961713Sgirish rxdma_cfig1_t cfg; 177844961713Sgirish #endif 177944961713Sgirish uint_t serviced = DDI_INTR_UNCLAIMED; 178044961713Sgirish 178144961713Sgirish if (ldvp == NULL) { 178244961713Sgirish NXGE_DEBUG_MSG((NULL, INT_CTL, 178352ccf843Smisaki "<== nxge_rx_intr: arg2 $%p arg1 $%p", 178452ccf843Smisaki nxgep, ldvp)); 178544961713Sgirish 178644961713Sgirish return (DDI_INTR_CLAIMED); 178744961713Sgirish } 178844961713Sgirish 178944961713Sgirish if (arg2 == NULL || (void *)ldvp->nxgep != arg2) { 179044961713Sgirish nxgep = ldvp->nxgep; 179144961713Sgirish } 17921d36aa9eSspeer 17931d36aa9eSspeer if ((!(nxgep->drv_state & STATE_HW_INITIALIZED)) || 17941d36aa9eSspeer (nxgep->nxge_mac_state != NXGE_MAC_STARTED)) { 17951d36aa9eSspeer NXGE_DEBUG_MSG((nxgep, INT_CTL, 17961d36aa9eSspeer "<== nxge_rx_intr: interface not started or intialized")); 17971d36aa9eSspeer return (DDI_INTR_CLAIMED); 17981d36aa9eSspeer } 17991d36aa9eSspeer 180044961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 180152ccf843Smisaki "==> nxge_rx_intr: arg2 $%p arg1 $%p", 180252ccf843Smisaki nxgep, ldvp)); 180344961713Sgirish 180444961713Sgirish /* 180544961713Sgirish * This interrupt handler is for a specific 180644961713Sgirish * receive dma channel. 180744961713Sgirish */ 180844961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 180944961713Sgirish /* 181044961713Sgirish * Get the control and status for this channel. 181144961713Sgirish */ 181244961713Sgirish channel = ldvp->channel; 181344961713Sgirish ldgp = ldvp->ldgp; 181444961713Sgirish RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel, &cs.value); 181544961713Sgirish 181644961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_intr:channel %d " 181752ccf843Smisaki "cs 0x%016llx rcrto 0x%x rcrthres %x", 181852ccf843Smisaki channel, 181952ccf843Smisaki cs.value, 182052ccf843Smisaki cs.bits.hdw.rcrto, 182152ccf843Smisaki cs.bits.hdw.rcrthres)); 182244961713Sgirish 1823678453a8Sspeer nxge_rx_pkts_vring(nxgep, ldvp->vdma_index, cs); 182444961713Sgirish serviced = DDI_INTR_CLAIMED; 182544961713Sgirish 182644961713Sgirish /* error events. */ 182744961713Sgirish if (cs.value & RX_DMA_CTL_STAT_ERROR) { 1828678453a8Sspeer (void) nxge_rx_err_evnts(nxgep, channel, cs); 182944961713Sgirish } 183044961713Sgirish 183144961713Sgirish nxge_intr_exit: 183244961713Sgirish /* 183344961713Sgirish * Enable the mailbox update interrupt if we want 183444961713Sgirish * to use mailbox. We probably don't need to use 183544961713Sgirish * mailbox as it only saves us one pio read. 183644961713Sgirish * Also write 1 to rcrthres and rcrto to clear 183744961713Sgirish * these two edge triggered bits. 183844961713Sgirish */ 183944961713Sgirish 184044961713Sgirish cs.value &= RX_DMA_CTL_STAT_WR1C; 184144961713Sgirish cs.bits.hdw.mex = 1; 184244961713Sgirish RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel, 184352ccf843Smisaki cs.value); 184444961713Sgirish 184544961713Sgirish /* 184644961713Sgirish * Rearm this logical group if this is a single device 184744961713Sgirish * group. 184844961713Sgirish */ 184944961713Sgirish if (ldgp->nldvs == 1) { 185044961713Sgirish ldgimgm_t mgm; 185144961713Sgirish mgm.value = 0; 185244961713Sgirish mgm.bits.ldw.arm = 1; 185344961713Sgirish mgm.bits.ldw.timer = ldgp->ldg_timer; 1854678453a8Sspeer if (isLDOMguest(nxgep)) { 1855678453a8Sspeer nxge_hio_ldgimgn(nxgep, ldgp); 1856678453a8Sspeer } else { 1857678453a8Sspeer NXGE_REG_WR64(handle, 185844961713Sgirish LDGIMGN_REG + LDSV_OFFSET(ldgp->ldg), 185944961713Sgirish mgm.value); 1860678453a8Sspeer } 186144961713Sgirish } 186244961713Sgirish 186344961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_intr: serviced %d", 186452ccf843Smisaki serviced)); 186544961713Sgirish return (serviced); 186644961713Sgirish } 186744961713Sgirish 186844961713Sgirish /* 186944961713Sgirish * Process the packets received in the specified logical device 187044961713Sgirish * and pass up a chain of message blocks to the upper layer. 187144961713Sgirish */ 187244961713Sgirish static void 1873678453a8Sspeer nxge_rx_pkts_vring(p_nxge_t nxgep, uint_t vindex, rx_dma_ctl_stat_t cs) 187444961713Sgirish { 187544961713Sgirish p_mblk_t mp; 187644961713Sgirish p_rx_rcr_ring_t rcrp; 187744961713Sgirish 187844961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts_vring")); 1879678453a8Sspeer rcrp = nxgep->rx_rcr_rings->rcr_rings[vindex]; 1880678453a8Sspeer if (rcrp->poll_flag) { 1881678453a8Sspeer /* It is in the poll mode */ 1882678453a8Sspeer return; 1883678453a8Sspeer } 1884678453a8Sspeer 1885678453a8Sspeer if ((mp = nxge_rx_pkts(nxgep, rcrp, cs, -1)) == NULL) { 188644961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 188752ccf843Smisaki "<== nxge_rx_pkts_vring: no mp")); 188844961713Sgirish return; 188944961713Sgirish } 189044961713Sgirish 189144961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts_vring: $%p", 189252ccf843Smisaki mp)); 189344961713Sgirish 189444961713Sgirish #ifdef NXGE_DEBUG 189544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 189652ccf843Smisaki "==> nxge_rx_pkts_vring:calling mac_rx " 189752ccf843Smisaki "LEN %d mp $%p mp->b_cont $%p mp->b_next $%p rcrp $%p " 189852ccf843Smisaki "mac_handle $%p", 189952ccf843Smisaki mp->b_wptr - mp->b_rptr, 190052ccf843Smisaki mp, mp->b_cont, mp->b_next, 190152ccf843Smisaki rcrp, rcrp->rcr_mac_handle)); 190244961713Sgirish 190344961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 190452ccf843Smisaki "==> nxge_rx_pkts_vring: dump packets " 190552ccf843Smisaki "(mp $%p b_rptr $%p b_wptr $%p):\n %s", 190652ccf843Smisaki mp, 190752ccf843Smisaki mp->b_rptr, 190852ccf843Smisaki mp->b_wptr, 190952ccf843Smisaki nxge_dump_packet((char *)mp->b_rptr, 191052ccf843Smisaki mp->b_wptr - mp->b_rptr))); 191114ea4bb7Ssd if (mp->b_cont) { 191214ea4bb7Ssd NXGE_DEBUG_MSG((nxgep, RX_CTL, 191352ccf843Smisaki "==> nxge_rx_pkts_vring: dump b_cont packets " 191452ccf843Smisaki "(mp->b_cont $%p b_rptr $%p b_wptr $%p):\n %s", 191552ccf843Smisaki mp->b_cont, 191652ccf843Smisaki mp->b_cont->b_rptr, 191752ccf843Smisaki mp->b_cont->b_wptr, 191852ccf843Smisaki nxge_dump_packet((char *)mp->b_cont->b_rptr, 191952ccf843Smisaki mp->b_cont->b_wptr - mp->b_cont->b_rptr))); 192014ea4bb7Ssd } 192144961713Sgirish if (mp->b_next) { 192244961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 192352ccf843Smisaki "==> nxge_rx_pkts_vring: dump next packets " 192452ccf843Smisaki "(b_rptr $%p): %s", 192552ccf843Smisaki mp->b_next->b_rptr, 192652ccf843Smisaki nxge_dump_packet((char *)mp->b_next->b_rptr, 192752ccf843Smisaki mp->b_next->b_wptr - mp->b_next->b_rptr))); 192844961713Sgirish } 192944961713Sgirish #endif 193044961713Sgirish 1931678453a8Sspeer if (!isLDOMguest(nxgep)) 1932678453a8Sspeer mac_rx(nxgep->mach, rcrp->rcr_mac_handle, mp); 1933678453a8Sspeer #if defined(sun4v) 1934678453a8Sspeer else { /* isLDOMguest(nxgep) */ 1935678453a8Sspeer nxge_hio_data_t *nhd = (nxge_hio_data_t *) 1936678453a8Sspeer nxgep->nxge_hw_p->hio; 1937678453a8Sspeer nx_vio_fp_t *vio = &nhd->hio.vio; 1938678453a8Sspeer 1939678453a8Sspeer if (vio->cb.vio_net_rx_cb) { 1940678453a8Sspeer (*vio->cb.vio_net_rx_cb) 1941678453a8Sspeer (nxgep->hio_vr->vhp, mp); 1942678453a8Sspeer } 1943678453a8Sspeer } 1944678453a8Sspeer #endif 194544961713Sgirish } 194644961713Sgirish 194744961713Sgirish 194844961713Sgirish /* 194944961713Sgirish * This routine is the main packet receive processing function. 195044961713Sgirish * It gets the packet type, error code, and buffer related 195144961713Sgirish * information from the receive completion entry. 195244961713Sgirish * How many completion entries to process is based on the number of packets 195344961713Sgirish * queued by the hardware, a hardware maintained tail pointer 195444961713Sgirish * and a configurable receive packet count. 195544961713Sgirish * 195644961713Sgirish * A chain of message blocks will be created as result of processing 195744961713Sgirish * the completion entries. This chain of message blocks will be returned and 195844961713Sgirish * a hardware control status register will be updated with the number of 195944961713Sgirish * packets were removed from the hardware queue. 196044961713Sgirish * 196144961713Sgirish */ 1962678453a8Sspeer static mblk_t * 1963678453a8Sspeer nxge_rx_pkts(p_nxge_t nxgep, p_rx_rcr_ring_t rcr_p, rx_dma_ctl_stat_t cs, 1964678453a8Sspeer int bytes_to_pickup) 196544961713Sgirish { 196644961713Sgirish npi_handle_t handle; 196744961713Sgirish uint8_t channel; 196844961713Sgirish uint32_t comp_rd_index; 196944961713Sgirish p_rcr_entry_t rcr_desc_rd_head_p; 197044961713Sgirish p_rcr_entry_t rcr_desc_rd_head_pp; 197144961713Sgirish p_mblk_t nmp, mp_cont, head_mp, *tail_mp; 197244961713Sgirish uint16_t qlen, nrcr_read, npkt_read; 1973678453a8Sspeer uint32_t qlen_hw; 197444961713Sgirish boolean_t multi; 1975678453a8Sspeer rcrcfig_b_t rcr_cfg_b; 1976678453a8Sspeer int totallen = 0; 1977a3c5bd6dSspeer #if defined(_BIG_ENDIAN) 197844961713Sgirish npi_status_t rs = NPI_SUCCESS; 197944961713Sgirish #endif 198044961713Sgirish 1981678453a8Sspeer NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts: " 198252ccf843Smisaki "channel %d", rcr_p->rdc)); 198344961713Sgirish 198444961713Sgirish if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 198544961713Sgirish return (NULL); 198644961713Sgirish } 198744961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 198844961713Sgirish channel = rcr_p->rdc; 198944961713Sgirish 199044961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 199152ccf843Smisaki "==> nxge_rx_pkts: START: rcr channel %d " 199252ccf843Smisaki "head_p $%p head_pp $%p index %d ", 199352ccf843Smisaki channel, rcr_p->rcr_desc_rd_head_p, 199452ccf843Smisaki rcr_p->rcr_desc_rd_head_pp, 199552ccf843Smisaki rcr_p->comp_rd_index)); 199644961713Sgirish 199744961713Sgirish 1998a3c5bd6dSspeer #if !defined(_BIG_ENDIAN) 199944961713Sgirish qlen = RXDMA_REG_READ32(handle, RCRSTAT_A_REG, channel) & 0xffff; 200044961713Sgirish #else 200144961713Sgirish rs = npi_rxdma_rdc_rcr_qlen_get(handle, channel, &qlen); 200244961713Sgirish if (rs != NPI_SUCCESS) { 2003678453a8Sspeer NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts: " 200444961713Sgirish "channel %d, get qlen failed 0x%08x", 200552ccf843Smisaki channel, rs)); 200644961713Sgirish return (NULL); 200744961713Sgirish } 200844961713Sgirish #endif 200944961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts:rcr channel %d " 201052ccf843Smisaki "qlen %d", channel, qlen)); 201144961713Sgirish 201244961713Sgirish 201344961713Sgirish 201444961713Sgirish if (!qlen) { 201544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 201652ccf843Smisaki "==> nxge_rx_pkts:rcr channel %d " 201752ccf843Smisaki "qlen %d (no pkts)", channel, qlen)); 201844961713Sgirish 201944961713Sgirish return (NULL); 202044961713Sgirish } 202144961713Sgirish 202244961713Sgirish comp_rd_index = rcr_p->comp_rd_index; 202344961713Sgirish 202444961713Sgirish rcr_desc_rd_head_p = rcr_p->rcr_desc_rd_head_p; 202544961713Sgirish rcr_desc_rd_head_pp = rcr_p->rcr_desc_rd_head_pp; 202644961713Sgirish nrcr_read = npkt_read = 0; 202744961713Sgirish 202844961713Sgirish /* 202944961713Sgirish * Number of packets queued 203044961713Sgirish * (The jumbo or multi packet will be counted as only one 203144961713Sgirish * packets and it may take up more than one completion entry). 203244961713Sgirish */ 203344961713Sgirish qlen_hw = (qlen < nxge_max_rx_pkts) ? 203452ccf843Smisaki qlen : nxge_max_rx_pkts; 203544961713Sgirish head_mp = NULL; 203644961713Sgirish tail_mp = &head_mp; 203744961713Sgirish nmp = mp_cont = NULL; 203844961713Sgirish multi = B_FALSE; 203944961713Sgirish 2040a3c5bd6dSspeer while (qlen_hw) { 204144961713Sgirish 204244961713Sgirish #ifdef NXGE_DEBUG 204344961713Sgirish nxge_dump_rcr_entry(nxgep, rcr_desc_rd_head_p); 204444961713Sgirish #endif 204544961713Sgirish /* 204644961713Sgirish * Process one completion ring entry. 204744961713Sgirish */ 204844961713Sgirish nxge_receive_packet(nxgep, 204952ccf843Smisaki rcr_p, rcr_desc_rd_head_p, &multi, &nmp, &mp_cont); 205044961713Sgirish 205144961713Sgirish /* 205244961713Sgirish * message chaining modes 205344961713Sgirish */ 205414ea4bb7Ssd if (nmp) { 205544961713Sgirish nmp->b_next = NULL; 205614ea4bb7Ssd if (!multi && !mp_cont) { /* frame fits a partition */ 205714ea4bb7Ssd *tail_mp = nmp; 205814ea4bb7Ssd tail_mp = &nmp->b_next; 2059678453a8Sspeer totallen += MBLKL(nmp); 206014ea4bb7Ssd nmp = NULL; 206114ea4bb7Ssd } else if (multi && !mp_cont) { /* first segment */ 206214ea4bb7Ssd *tail_mp = nmp; 206314ea4bb7Ssd tail_mp = &nmp->b_cont; 2064678453a8Sspeer totallen += MBLKL(nmp); 206514ea4bb7Ssd } else if (multi && mp_cont) { /* mid of multi segs */ 206614ea4bb7Ssd *tail_mp = mp_cont; 206714ea4bb7Ssd tail_mp = &mp_cont->b_cont; 2068678453a8Sspeer totallen += MBLKL(mp_cont); 206914ea4bb7Ssd } else if (!multi && mp_cont) { /* last segment */ 2070a3c5bd6dSspeer *tail_mp = mp_cont; 207114ea4bb7Ssd tail_mp = &nmp->b_next; 2072678453a8Sspeer totallen += MBLKL(mp_cont); 207314ea4bb7Ssd nmp = NULL; 207414ea4bb7Ssd } 207544961713Sgirish } 207644961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 207752ccf843Smisaki "==> nxge_rx_pkts: loop: rcr channel %d " 207852ccf843Smisaki "before updating: multi %d " 207952ccf843Smisaki "nrcr_read %d " 208052ccf843Smisaki "npk read %d " 208152ccf843Smisaki "head_pp $%p index %d ", 208252ccf843Smisaki channel, 208352ccf843Smisaki multi, 208452ccf843Smisaki nrcr_read, npkt_read, rcr_desc_rd_head_pp, 208552ccf843Smisaki comp_rd_index)); 208644961713Sgirish 208744961713Sgirish if (!multi) { 208844961713Sgirish qlen_hw--; 208944961713Sgirish npkt_read++; 209044961713Sgirish } 209144961713Sgirish 209244961713Sgirish /* 209344961713Sgirish * Update the next read entry. 209444961713Sgirish */ 209544961713Sgirish comp_rd_index = NEXT_ENTRY(comp_rd_index, 209652ccf843Smisaki rcr_p->comp_wrap_mask); 209744961713Sgirish 209844961713Sgirish rcr_desc_rd_head_p = NEXT_ENTRY_PTR(rcr_desc_rd_head_p, 209952ccf843Smisaki rcr_p->rcr_desc_first_p, 210052ccf843Smisaki rcr_p->rcr_desc_last_p); 210144961713Sgirish 210244961713Sgirish nrcr_read++; 210344961713Sgirish 210444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 210552ccf843Smisaki "<== nxge_rx_pkts: (SAM, process one packet) " 210652ccf843Smisaki "nrcr_read %d", 210752ccf843Smisaki nrcr_read)); 210844961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 210952ccf843Smisaki "==> nxge_rx_pkts: loop: rcr channel %d " 211052ccf843Smisaki "multi %d " 211152ccf843Smisaki "nrcr_read %d " 211252ccf843Smisaki "npk read %d " 211352ccf843Smisaki "head_pp $%p index %d ", 211452ccf843Smisaki channel, 211552ccf843Smisaki multi, 211652ccf843Smisaki nrcr_read, npkt_read, rcr_desc_rd_head_pp, 211752ccf843Smisaki comp_rd_index)); 211844961713Sgirish 2119678453a8Sspeer if ((bytes_to_pickup != -1) && 2120678453a8Sspeer (totallen >= bytes_to_pickup)) { 2121678453a8Sspeer break; 2122678453a8Sspeer } 212344961713Sgirish } 212444961713Sgirish 212544961713Sgirish rcr_p->rcr_desc_rd_head_pp = rcr_desc_rd_head_pp; 212644961713Sgirish rcr_p->comp_rd_index = comp_rd_index; 212744961713Sgirish rcr_p->rcr_desc_rd_head_p = rcr_desc_rd_head_p; 212844961713Sgirish 212914ea4bb7Ssd if ((nxgep->intr_timeout != rcr_p->intr_timeout) || 213052ccf843Smisaki (nxgep->intr_threshold != rcr_p->intr_threshold)) { 213114ea4bb7Ssd rcr_p->intr_timeout = nxgep->intr_timeout; 213214ea4bb7Ssd rcr_p->intr_threshold = nxgep->intr_threshold; 213314ea4bb7Ssd rcr_cfg_b.value = 0x0ULL; 213414ea4bb7Ssd if (rcr_p->intr_timeout) 213514ea4bb7Ssd rcr_cfg_b.bits.ldw.entout = 1; 213614ea4bb7Ssd rcr_cfg_b.bits.ldw.timeout = rcr_p->intr_timeout; 213714ea4bb7Ssd rcr_cfg_b.bits.ldw.pthres = rcr_p->intr_threshold; 213814ea4bb7Ssd RXDMA_REG_WRITE64(handle, RCRCFIG_B_REG, 213952ccf843Smisaki channel, rcr_cfg_b.value); 214014ea4bb7Ssd } 214144961713Sgirish 214244961713Sgirish cs.bits.ldw.pktread = npkt_read; 214344961713Sgirish cs.bits.ldw.ptrread = nrcr_read; 214444961713Sgirish RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, 214552ccf843Smisaki channel, cs.value); 214644961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 214752ccf843Smisaki "==> nxge_rx_pkts: EXIT: rcr channel %d " 214852ccf843Smisaki "head_pp $%p index %016llx ", 214952ccf843Smisaki channel, 215052ccf843Smisaki rcr_p->rcr_desc_rd_head_pp, 215152ccf843Smisaki rcr_p->comp_rd_index)); 215244961713Sgirish /* 215344961713Sgirish * Update RCR buffer pointer read and number of packets 215444961713Sgirish * read. 215544961713Sgirish */ 215644961713Sgirish 215744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_pkts")); 215844961713Sgirish return (head_mp); 215944961713Sgirish } 216044961713Sgirish 216144961713Sgirish void 216244961713Sgirish nxge_receive_packet(p_nxge_t nxgep, 216344961713Sgirish p_rx_rcr_ring_t rcr_p, p_rcr_entry_t rcr_desc_rd_head_p, 216444961713Sgirish boolean_t *multi_p, mblk_t **mp, mblk_t **mp_cont) 216544961713Sgirish { 216644961713Sgirish p_mblk_t nmp = NULL; 216744961713Sgirish uint64_t multi; 216844961713Sgirish uint64_t dcf_err; 216944961713Sgirish uint8_t channel; 217044961713Sgirish 217144961713Sgirish boolean_t first_entry = B_TRUE; 217244961713Sgirish boolean_t is_tcp_udp = B_FALSE; 217344961713Sgirish boolean_t buffer_free = B_FALSE; 217444961713Sgirish boolean_t error_send_up = B_FALSE; 217544961713Sgirish uint8_t error_type; 217644961713Sgirish uint16_t l2_len; 217744961713Sgirish uint16_t skip_len; 217844961713Sgirish uint8_t pktbufsz_type; 217944961713Sgirish uint64_t rcr_entry; 218044961713Sgirish uint64_t *pkt_buf_addr_pp; 218144961713Sgirish uint64_t *pkt_buf_addr_p; 218244961713Sgirish uint32_t buf_offset; 218344961713Sgirish uint32_t bsize; 218444961713Sgirish uint32_t error_disp_cnt; 218544961713Sgirish uint32_t msg_index; 218644961713Sgirish p_rx_rbr_ring_t rx_rbr_p; 218744961713Sgirish p_rx_msg_t *rx_msg_ring_p; 218844961713Sgirish p_rx_msg_t rx_msg_p; 218944961713Sgirish uint16_t sw_offset_bytes = 0, hdr_size = 0; 219044961713Sgirish nxge_status_t status = NXGE_OK; 219144961713Sgirish boolean_t is_valid = B_FALSE; 219244961713Sgirish p_nxge_rx_ring_stats_t rdc_stats; 2193a3c5bd6dSspeer uint32_t bytes_read; 2194a3c5bd6dSspeer uint64_t pkt_type; 2195a3c5bd6dSspeer uint64_t frag; 21964202ea4bSsbehera boolean_t pkt_too_long_err = B_FALSE; 219744961713Sgirish #ifdef NXGE_DEBUG 219844961713Sgirish int dump_len; 219944961713Sgirish #endif 220044961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> nxge_receive_packet")); 220144961713Sgirish first_entry = (*mp == NULL) ? B_TRUE : B_FALSE; 220244961713Sgirish 220344961713Sgirish rcr_entry = *((uint64_t *)rcr_desc_rd_head_p); 220444961713Sgirish 220544961713Sgirish multi = (rcr_entry & RCR_MULTI_MASK); 220644961713Sgirish dcf_err = (rcr_entry & RCR_DCF_ERROR_MASK); 220744961713Sgirish pkt_type = (rcr_entry & RCR_PKT_TYPE_MASK); 220844961713Sgirish 220944961713Sgirish error_type = ((rcr_entry & RCR_ERROR_MASK) >> RCR_ERROR_SHIFT); 221044961713Sgirish frag = (rcr_entry & RCR_FRAG_MASK); 221144961713Sgirish 221244961713Sgirish l2_len = ((rcr_entry & RCR_L2_LEN_MASK) >> RCR_L2_LEN_SHIFT); 221344961713Sgirish 221444961713Sgirish pktbufsz_type = ((rcr_entry & RCR_PKTBUFSZ_MASK) >> 221552ccf843Smisaki RCR_PKTBUFSZ_SHIFT); 2216adfcba55Sjoycey #if defined(__i386) 2217adfcba55Sjoycey pkt_buf_addr_pp = (uint64_t *)(uint32_t)((rcr_entry & 221852ccf843Smisaki RCR_PKT_BUF_ADDR_MASK) << RCR_PKT_BUF_ADDR_SHIFT); 2219adfcba55Sjoycey #else 222044961713Sgirish pkt_buf_addr_pp = (uint64_t *)((rcr_entry & RCR_PKT_BUF_ADDR_MASK) << 222152ccf843Smisaki RCR_PKT_BUF_ADDR_SHIFT); 2222adfcba55Sjoycey #endif 222344961713Sgirish 222444961713Sgirish channel = rcr_p->rdc; 222544961713Sgirish 222644961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 222752ccf843Smisaki "==> nxge_receive_packet: entryp $%p entry 0x%0llx " 222852ccf843Smisaki "pkt_buf_addr_pp $%p l2_len %d multi 0x%llx " 222952ccf843Smisaki "error_type 0x%x pkt_type 0x%x " 223052ccf843Smisaki "pktbufsz_type %d ", 223152ccf843Smisaki rcr_desc_rd_head_p, 223252ccf843Smisaki rcr_entry, pkt_buf_addr_pp, l2_len, 223352ccf843Smisaki multi, 223452ccf843Smisaki error_type, 223552ccf843Smisaki pkt_type, 223652ccf843Smisaki pktbufsz_type)); 223744961713Sgirish 223844961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 223952ccf843Smisaki "==> nxge_receive_packet: entryp $%p entry 0x%0llx " 224052ccf843Smisaki "pkt_buf_addr_pp $%p l2_len %d multi 0x%llx " 224152ccf843Smisaki "error_type 0x%x pkt_type 0x%x ", rcr_desc_rd_head_p, 224252ccf843Smisaki rcr_entry, pkt_buf_addr_pp, l2_len, 224352ccf843Smisaki multi, 224452ccf843Smisaki error_type, 224552ccf843Smisaki pkt_type)); 224644961713Sgirish 224744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 224852ccf843Smisaki "==> (rbr) nxge_receive_packet: entry 0x%0llx " 224952ccf843Smisaki "full pkt_buf_addr_pp $%p l2_len %d", 225052ccf843Smisaki rcr_entry, pkt_buf_addr_pp, l2_len)); 225144961713Sgirish 225244961713Sgirish /* get the stats ptr */ 225344961713Sgirish rdc_stats = rcr_p->rdc_stats; 225444961713Sgirish 225544961713Sgirish if (!l2_len) { 225644961713Sgirish 225744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 225852ccf843Smisaki "<== nxge_receive_packet: failed: l2 length is 0.")); 225944961713Sgirish return; 226044961713Sgirish } 226144961713Sgirish 22624202ea4bSsbehera /* 22634202ea4bSsbehera * Sofware workaround for BMAC hardware limitation that allows 22644202ea4bSsbehera * maxframe size of 1526, instead of 1522 for non-jumbo and 0x2406 22654202ea4bSsbehera * instead of 0x2400 for jumbo. 22664202ea4bSsbehera */ 22674202ea4bSsbehera if (l2_len > nxgep->mac.maxframesize) { 22684202ea4bSsbehera pkt_too_long_err = B_TRUE; 22694202ea4bSsbehera } 22704202ea4bSsbehera 227156d930aeSspeer /* Hardware sends us 4 bytes of CRC as no stripping is done. */ 227256d930aeSspeer l2_len -= ETHERFCSL; 227356d930aeSspeer 227444961713Sgirish /* shift 6 bits to get the full io address */ 2275adfcba55Sjoycey #if defined(__i386) 2276adfcba55Sjoycey pkt_buf_addr_pp = (uint64_t *)((uint32_t)pkt_buf_addr_pp << 227752ccf843Smisaki RCR_PKT_BUF_ADDR_SHIFT_FULL); 2278adfcba55Sjoycey #else 227944961713Sgirish pkt_buf_addr_pp = (uint64_t *)((uint64_t)pkt_buf_addr_pp << 228052ccf843Smisaki RCR_PKT_BUF_ADDR_SHIFT_FULL); 2281adfcba55Sjoycey #endif 228244961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 228352ccf843Smisaki "==> (rbr) nxge_receive_packet: entry 0x%0llx " 228452ccf843Smisaki "full pkt_buf_addr_pp $%p l2_len %d", 228552ccf843Smisaki rcr_entry, pkt_buf_addr_pp, l2_len)); 228644961713Sgirish 228744961713Sgirish rx_rbr_p = rcr_p->rx_rbr_p; 228844961713Sgirish rx_msg_ring_p = rx_rbr_p->rx_msg_ring; 228944961713Sgirish 229044961713Sgirish if (first_entry) { 229144961713Sgirish hdr_size = (rcr_p->full_hdr_flag ? RXDMA_HDR_SIZE_FULL : 229252ccf843Smisaki RXDMA_HDR_SIZE_DEFAULT); 229344961713Sgirish 229444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 229552ccf843Smisaki "==> nxge_receive_packet: first entry 0x%016llx " 229652ccf843Smisaki "pkt_buf_addr_pp $%p l2_len %d hdr %d", 229752ccf843Smisaki rcr_entry, pkt_buf_addr_pp, l2_len, 229852ccf843Smisaki hdr_size)); 229944961713Sgirish } 230044961713Sgirish 230144961713Sgirish MUTEX_ENTER(&rcr_p->lock); 230244961713Sgirish MUTEX_ENTER(&rx_rbr_p->lock); 230344961713Sgirish 230444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 230552ccf843Smisaki "==> (rbr 1) nxge_receive_packet: entry 0x%0llx " 230652ccf843Smisaki "full pkt_buf_addr_pp $%p l2_len %d", 230752ccf843Smisaki rcr_entry, pkt_buf_addr_pp, l2_len)); 230844961713Sgirish 230944961713Sgirish /* 231044961713Sgirish * Packet buffer address in the completion entry points 231144961713Sgirish * to the starting buffer address (offset 0). 231244961713Sgirish * Use the starting buffer address to locate the corresponding 231344961713Sgirish * kernel address. 231444961713Sgirish */ 231544961713Sgirish status = nxge_rxbuf_pp_to_vp(nxgep, rx_rbr_p, 231652ccf843Smisaki pktbufsz_type, pkt_buf_addr_pp, &pkt_buf_addr_p, 231752ccf843Smisaki &buf_offset, 231852ccf843Smisaki &msg_index); 231944961713Sgirish 232044961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 232152ccf843Smisaki "==> (rbr 2) nxge_receive_packet: entry 0x%0llx " 232252ccf843Smisaki "full pkt_buf_addr_pp $%p l2_len %d", 232352ccf843Smisaki rcr_entry, pkt_buf_addr_pp, l2_len)); 232444961713Sgirish 232544961713Sgirish if (status != NXGE_OK) { 232644961713Sgirish MUTEX_EXIT(&rx_rbr_p->lock); 232744961713Sgirish MUTEX_EXIT(&rcr_p->lock); 232844961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 232952ccf843Smisaki "<== nxge_receive_packet: found vaddr failed %d", 233052ccf843Smisaki status)); 233144961713Sgirish return; 233244961713Sgirish } 233344961713Sgirish 233444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 233552ccf843Smisaki "==> (rbr 3) nxge_receive_packet: entry 0x%0llx " 233652ccf843Smisaki "full pkt_buf_addr_pp $%p l2_len %d", 233752ccf843Smisaki rcr_entry, pkt_buf_addr_pp, l2_len)); 233844961713Sgirish 233944961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 234052ccf843Smisaki "==> (rbr 4 msgindex %d) nxge_receive_packet: entry 0x%0llx " 234152ccf843Smisaki "full pkt_buf_addr_pp $%p l2_len %d", 234252ccf843Smisaki msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 234344961713Sgirish 234444961713Sgirish rx_msg_p = rx_msg_ring_p[msg_index]; 234544961713Sgirish 234644961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 234752ccf843Smisaki "==> (rbr 4 msgindex %d) nxge_receive_packet: entry 0x%0llx " 234852ccf843Smisaki "full pkt_buf_addr_pp $%p l2_len %d", 234952ccf843Smisaki msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 235044961713Sgirish 235144961713Sgirish switch (pktbufsz_type) { 235244961713Sgirish case RCR_PKTBUFSZ_0: 235344961713Sgirish bsize = rx_rbr_p->pkt_buf_size0_bytes; 235444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 235552ccf843Smisaki "==> nxge_receive_packet: 0 buf %d", bsize)); 235644961713Sgirish break; 235744961713Sgirish case RCR_PKTBUFSZ_1: 235844961713Sgirish bsize = rx_rbr_p->pkt_buf_size1_bytes; 235944961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 236052ccf843Smisaki "==> nxge_receive_packet: 1 buf %d", bsize)); 236144961713Sgirish break; 236244961713Sgirish case RCR_PKTBUFSZ_2: 236344961713Sgirish bsize = rx_rbr_p->pkt_buf_size2_bytes; 236444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 236552ccf843Smisaki "==> nxge_receive_packet: 2 buf %d", bsize)); 236644961713Sgirish break; 236744961713Sgirish case RCR_SINGLE_BLOCK: 236844961713Sgirish bsize = rx_msg_p->block_size; 236944961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 237052ccf843Smisaki "==> nxge_receive_packet: single %d", bsize)); 237144961713Sgirish 237244961713Sgirish break; 237344961713Sgirish default: 237444961713Sgirish MUTEX_EXIT(&rx_rbr_p->lock); 237544961713Sgirish MUTEX_EXIT(&rcr_p->lock); 237644961713Sgirish return; 237744961713Sgirish } 237844961713Sgirish 237944961713Sgirish DMA_COMMON_SYNC_OFFSET(rx_msg_p->buf_dma, 238052ccf843Smisaki (buf_offset + sw_offset_bytes), 238152ccf843Smisaki (hdr_size + l2_len), 238252ccf843Smisaki DDI_DMA_SYNC_FORCPU); 238344961713Sgirish 238444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 238552ccf843Smisaki "==> nxge_receive_packet: after first dump:usage count")); 238644961713Sgirish 238744961713Sgirish if (rx_msg_p->cur_usage_cnt == 0) { 238844961713Sgirish if (rx_rbr_p->rbr_use_bcopy) { 238944961713Sgirish atomic_inc_32(&rx_rbr_p->rbr_consumed); 239044961713Sgirish if (rx_rbr_p->rbr_consumed < 239152ccf843Smisaki rx_rbr_p->rbr_threshold_hi) { 239244961713Sgirish if (rx_rbr_p->rbr_threshold_lo == 0 || 239352ccf843Smisaki ((rx_rbr_p->rbr_consumed >= 239452ccf843Smisaki rx_rbr_p->rbr_threshold_lo) && 239552ccf843Smisaki (rx_rbr_p->rbr_bufsize_type >= 239652ccf843Smisaki pktbufsz_type))) { 239744961713Sgirish rx_msg_p->rx_use_bcopy = B_TRUE; 239844961713Sgirish } 239944961713Sgirish } else { 240044961713Sgirish rx_msg_p->rx_use_bcopy = B_TRUE; 240144961713Sgirish } 240244961713Sgirish } 240344961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 240452ccf843Smisaki "==> nxge_receive_packet: buf %d (new block) ", 240552ccf843Smisaki bsize)); 240644961713Sgirish 240744961713Sgirish rx_msg_p->pkt_buf_size_code = pktbufsz_type; 240844961713Sgirish rx_msg_p->pkt_buf_size = bsize; 240944961713Sgirish rx_msg_p->cur_usage_cnt = 1; 241044961713Sgirish if (pktbufsz_type == RCR_SINGLE_BLOCK) { 241144961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 241252ccf843Smisaki "==> nxge_receive_packet: buf %d " 241352ccf843Smisaki "(single block) ", 241452ccf843Smisaki bsize)); 241544961713Sgirish /* 241644961713Sgirish * Buffer can be reused once the free function 241744961713Sgirish * is called. 241844961713Sgirish */ 241944961713Sgirish rx_msg_p->max_usage_cnt = 1; 242044961713Sgirish buffer_free = B_TRUE; 242144961713Sgirish } else { 242244961713Sgirish rx_msg_p->max_usage_cnt = rx_msg_p->block_size/bsize; 242344961713Sgirish if (rx_msg_p->max_usage_cnt == 1) { 242444961713Sgirish buffer_free = B_TRUE; 242544961713Sgirish } 242644961713Sgirish } 242744961713Sgirish } else { 242844961713Sgirish rx_msg_p->cur_usage_cnt++; 242944961713Sgirish if (rx_msg_p->cur_usage_cnt == rx_msg_p->max_usage_cnt) { 243044961713Sgirish buffer_free = B_TRUE; 243144961713Sgirish } 243244961713Sgirish } 243344961713Sgirish 243444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 243544961713Sgirish "msgbuf index = %d l2len %d bytes usage %d max_usage %d ", 243652ccf843Smisaki msg_index, l2_len, 243752ccf843Smisaki rx_msg_p->cur_usage_cnt, rx_msg_p->max_usage_cnt)); 243844961713Sgirish 24394202ea4bSsbehera if ((error_type) || (dcf_err) || (pkt_too_long_err)) { 244044961713Sgirish rdc_stats->ierrors++; 244144961713Sgirish if (dcf_err) { 244244961713Sgirish rdc_stats->dcf_err++; 244344961713Sgirish #ifdef NXGE_DEBUG 244444961713Sgirish if (!rdc_stats->dcf_err) { 244544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 244644961713Sgirish "nxge_receive_packet: channel %d dcf_err rcr" 244744961713Sgirish " 0x%llx", channel, rcr_entry)); 244844961713Sgirish } 244944961713Sgirish #endif 245044961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, nxgep->mac.portnum, NULL, 245152ccf843Smisaki NXGE_FM_EREPORT_RDMC_DCF_ERR); 24524202ea4bSsbehera } else if (pkt_too_long_err) { 24534202ea4bSsbehera rdc_stats->pkt_too_long_err++; 24544202ea4bSsbehera NXGE_DEBUG_MSG((nxgep, RX_CTL, " nxge_receive_packet:" 24554202ea4bSsbehera " channel %d packet length [%d] > " 24564202ea4bSsbehera "maxframesize [%d]", channel, l2_len + ETHERFCSL, 24574202ea4bSsbehera nxgep->mac.maxframesize)); 245844961713Sgirish } else { 245944961713Sgirish /* Update error stats */ 246044961713Sgirish error_disp_cnt = NXGE_ERROR_SHOW_MAX; 246144961713Sgirish rdc_stats->errlog.compl_err_type = error_type; 246244961713Sgirish 246344961713Sgirish switch (error_type) { 2464f6485eecSyc /* 2465f6485eecSyc * Do not send FMA ereport for RCR_L2_ERROR and 2466f6485eecSyc * RCR_L4_CSUM_ERROR because most likely they indicate 2467f6485eecSyc * back pressure rather than HW failures. 2468f6485eecSyc */ 246953f3d8ecSyc case RCR_L2_ERROR: 247053f3d8ecSyc rdc_stats->l2_err++; 247153f3d8ecSyc if (rdc_stats->l2_err < 247253f3d8ecSyc error_disp_cnt) { 247344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 247453f3d8ecSyc " nxge_receive_packet:" 247553f3d8ecSyc " channel %d RCR L2_ERROR", 247653f3d8ecSyc channel)); 247753f3d8ecSyc } 247853f3d8ecSyc break; 247953f3d8ecSyc case RCR_L4_CSUM_ERROR: 248053f3d8ecSyc error_send_up = B_TRUE; 248153f3d8ecSyc rdc_stats->l4_cksum_err++; 248253f3d8ecSyc if (rdc_stats->l4_cksum_err < 248353f3d8ecSyc error_disp_cnt) { 248453f3d8ecSyc NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 248553f3d8ecSyc " nxge_receive_packet:" 248653f3d8ecSyc " channel %d" 248753f3d8ecSyc " RCR L4_CSUM_ERROR", channel)); 248853f3d8ecSyc } 248953f3d8ecSyc break; 2490f6485eecSyc /* 2491f6485eecSyc * Do not send FMA ereport for RCR_FFLP_SOFT_ERROR and 2492f6485eecSyc * RCR_ZCP_SOFT_ERROR because they reflect the same 2493f6485eecSyc * FFLP and ZCP errors that have been reported by 2494f6485eecSyc * nxge_fflp.c and nxge_zcp.c. 2495f6485eecSyc */ 249653f3d8ecSyc case RCR_FFLP_SOFT_ERROR: 249753f3d8ecSyc error_send_up = B_TRUE; 249853f3d8ecSyc rdc_stats->fflp_soft_err++; 249953f3d8ecSyc if (rdc_stats->fflp_soft_err < 250053f3d8ecSyc error_disp_cnt) { 250153f3d8ecSyc NXGE_ERROR_MSG((nxgep, 250253f3d8ecSyc NXGE_ERR_CTL, 250353f3d8ecSyc " nxge_receive_packet:" 250453f3d8ecSyc " channel %d" 250553f3d8ecSyc " RCR FFLP_SOFT_ERROR", channel)); 250653f3d8ecSyc } 250753f3d8ecSyc break; 250853f3d8ecSyc case RCR_ZCP_SOFT_ERROR: 250953f3d8ecSyc error_send_up = B_TRUE; 251053f3d8ecSyc rdc_stats->fflp_soft_err++; 251153f3d8ecSyc if (rdc_stats->zcp_soft_err < 251253f3d8ecSyc error_disp_cnt) 251353f3d8ecSyc NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 251453f3d8ecSyc " nxge_receive_packet: Channel %d" 251553f3d8ecSyc " RCR ZCP_SOFT_ERROR", channel)); 251653f3d8ecSyc break; 251753f3d8ecSyc default: 251853f3d8ecSyc rdc_stats->rcr_unknown_err++; 251953f3d8ecSyc if (rdc_stats->rcr_unknown_err 252053f3d8ecSyc < error_disp_cnt) { 252153f3d8ecSyc NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 252253f3d8ecSyc " nxge_receive_packet: Channel %d" 252353f3d8ecSyc " RCR entry 0x%llx error 0x%x", 252453f3d8ecSyc rcr_entry, channel, error_type)); 252553f3d8ecSyc } 252653f3d8ecSyc break; 252744961713Sgirish } 252844961713Sgirish } 252944961713Sgirish 253044961713Sgirish /* 253144961713Sgirish * Update and repost buffer block if max usage 253244961713Sgirish * count is reached. 253344961713Sgirish */ 253444961713Sgirish if (error_send_up == B_FALSE) { 2535958cea9eSml atomic_inc_32(&rx_msg_p->ref_cnt); 253644961713Sgirish if (buffer_free == B_TRUE) { 253744961713Sgirish rx_msg_p->free = B_TRUE; 253844961713Sgirish } 253944961713Sgirish 254044961713Sgirish MUTEX_EXIT(&rx_rbr_p->lock); 254144961713Sgirish MUTEX_EXIT(&rcr_p->lock); 254244961713Sgirish nxge_freeb(rx_msg_p); 254344961713Sgirish return; 254444961713Sgirish } 254544961713Sgirish } 254644961713Sgirish 254744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 254852ccf843Smisaki "==> nxge_receive_packet: DMA sync second ")); 254944961713Sgirish 255053f3d8ecSyc bytes_read = rcr_p->rcvd_pkt_bytes; 255144961713Sgirish skip_len = sw_offset_bytes + hdr_size; 255244961713Sgirish if (!rx_msg_p->rx_use_bcopy) { 2553958cea9eSml /* 2554958cea9eSml * For loaned up buffers, the driver reference count 2555958cea9eSml * will be incremented first and then the free state. 2556958cea9eSml */ 255753f3d8ecSyc if ((nmp = nxge_dupb(rx_msg_p, buf_offset, bsize)) != NULL) { 255814ea4bb7Ssd if (first_entry) { 255914ea4bb7Ssd nmp->b_rptr = &nmp->b_rptr[skip_len]; 256053f3d8ecSyc if (l2_len < bsize - skip_len) { 256114ea4bb7Ssd nmp->b_wptr = &nmp->b_rptr[l2_len]; 256253f3d8ecSyc } else { 256353f3d8ecSyc nmp->b_wptr = &nmp->b_rptr[bsize 256453f3d8ecSyc - skip_len]; 256553f3d8ecSyc } 256614ea4bb7Ssd } else { 256753f3d8ecSyc if (l2_len - bytes_read < bsize) { 256814ea4bb7Ssd nmp->b_wptr = 256914ea4bb7Ssd &nmp->b_rptr[l2_len - bytes_read]; 257053f3d8ecSyc } else { 257153f3d8ecSyc nmp->b_wptr = &nmp->b_rptr[bsize]; 257253f3d8ecSyc } 257314ea4bb7Ssd } 257444961713Sgirish } 257553f3d8ecSyc } else { 257653f3d8ecSyc if (first_entry) { 257753f3d8ecSyc nmp = nxge_dupb_bcopy(rx_msg_p, buf_offset + skip_len, 257853f3d8ecSyc l2_len < bsize - skip_len ? 257953f3d8ecSyc l2_len : bsize - skip_len); 258053f3d8ecSyc } else { 258153f3d8ecSyc nmp = nxge_dupb_bcopy(rx_msg_p, buf_offset, 258253f3d8ecSyc l2_len - bytes_read < bsize ? 258353f3d8ecSyc l2_len - bytes_read : bsize); 258453f3d8ecSyc } 258553f3d8ecSyc } 258653f3d8ecSyc if (nmp != NULL) { 2587f720bc57Syc if (first_entry) { 2588f720bc57Syc /* 2589f720bc57Syc * Jumbo packets may be received with more than one 2590f720bc57Syc * buffer, increment ipackets for the first entry only. 2591f720bc57Syc */ 2592f720bc57Syc rdc_stats->ipackets++; 2593f720bc57Syc 2594f720bc57Syc /* Update ibytes for kstat. */ 2595f720bc57Syc rdc_stats->ibytes += skip_len 2596f720bc57Syc + l2_len < bsize ? l2_len : bsize; 2597f720bc57Syc /* 2598f720bc57Syc * Update the number of bytes read so far for the 2599f720bc57Syc * current frame. 2600f720bc57Syc */ 260153f3d8ecSyc bytes_read = nmp->b_wptr - nmp->b_rptr; 2602f720bc57Syc } else { 2603f720bc57Syc rdc_stats->ibytes += l2_len - bytes_read < bsize ? 2604f720bc57Syc l2_len - bytes_read : bsize; 260553f3d8ecSyc bytes_read += nmp->b_wptr - nmp->b_rptr; 2606f720bc57Syc } 260753f3d8ecSyc 260853f3d8ecSyc NXGE_DEBUG_MSG((nxgep, RX_CTL, 260953f3d8ecSyc "==> nxge_receive_packet after dupb: " 261053f3d8ecSyc "rbr consumed %d " 261153f3d8ecSyc "pktbufsz_type %d " 261253f3d8ecSyc "nmp $%p rptr $%p wptr $%p " 261353f3d8ecSyc "buf_offset %d bzise %d l2_len %d skip_len %d", 261453f3d8ecSyc rx_rbr_p->rbr_consumed, 261553f3d8ecSyc pktbufsz_type, 261653f3d8ecSyc nmp, nmp->b_rptr, nmp->b_wptr, 261753f3d8ecSyc buf_offset, bsize, l2_len, skip_len)); 261844961713Sgirish } else { 261944961713Sgirish cmn_err(CE_WARN, "!nxge_receive_packet: " 262052ccf843Smisaki "update stats (error)"); 26212e59129aSraghus atomic_inc_32(&rx_msg_p->ref_cnt); 26222e59129aSraghus if (buffer_free == B_TRUE) { 26232e59129aSraghus rx_msg_p->free = B_TRUE; 26242e59129aSraghus } 26252e59129aSraghus MUTEX_EXIT(&rx_rbr_p->lock); 26262e59129aSraghus MUTEX_EXIT(&rcr_p->lock); 26272e59129aSraghus nxge_freeb(rx_msg_p); 26282e59129aSraghus return; 262944961713Sgirish } 2630ee5416c9Syc 263144961713Sgirish if (buffer_free == B_TRUE) { 263244961713Sgirish rx_msg_p->free = B_TRUE; 263344961713Sgirish } 2634f720bc57Syc 263544961713Sgirish is_valid = (nmp != NULL); 263653f3d8ecSyc 263753f3d8ecSyc rcr_p->rcvd_pkt_bytes = bytes_read; 263853f3d8ecSyc 263944961713Sgirish MUTEX_EXIT(&rx_rbr_p->lock); 264044961713Sgirish MUTEX_EXIT(&rcr_p->lock); 264144961713Sgirish 264244961713Sgirish if (rx_msg_p->free && rx_msg_p->rx_use_bcopy) { 264344961713Sgirish atomic_inc_32(&rx_msg_p->ref_cnt); 264444961713Sgirish nxge_freeb(rx_msg_p); 264544961713Sgirish } 264644961713Sgirish 264744961713Sgirish if (is_valid) { 2648a3c5bd6dSspeer nmp->b_cont = NULL; 264944961713Sgirish if (first_entry) { 265044961713Sgirish *mp = nmp; 265144961713Sgirish *mp_cont = NULL; 265253f3d8ecSyc } else { 265344961713Sgirish *mp_cont = nmp; 265453f3d8ecSyc } 265544961713Sgirish } 265644961713Sgirish 265744961713Sgirish /* 2658f720bc57Syc * ERROR, FRAG and PKT_TYPE are only reported in the first entry. 2659f720bc57Syc * If a packet is not fragmented and no error bit is set, then 2660f720bc57Syc * L4 checksum is OK. 266144961713Sgirish */ 2662f720bc57Syc 266344961713Sgirish if (is_valid && !multi) { 2664678453a8Sspeer /* 2665f720bc57Syc * Update hardware checksuming. 2666f720bc57Syc * 2667b4d05839Sml * If the checksum flag nxge_chksum_offload 2668b4d05839Sml * is 1, TCP and UDP packets can be sent 2669678453a8Sspeer * up with good checksum. If the checksum flag 2670b4d05839Sml * is set to 0, checksum reporting will apply to 2671678453a8Sspeer * TCP packets only (workaround for a hardware bug). 2672b4d05839Sml * If the checksum flag nxge_cksum_offload is 2673b4d05839Sml * greater than 1, both TCP and UDP packets 2674b4d05839Sml * will not be reported its hardware checksum results. 2675678453a8Sspeer */ 2676b4d05839Sml if (nxge_cksum_offload == 1) { 2677678453a8Sspeer is_tcp_udp = ((pkt_type == RCR_PKT_IS_TCP || 267852ccf843Smisaki pkt_type == RCR_PKT_IS_UDP) ? 267952ccf843Smisaki B_TRUE: B_FALSE); 2680b4d05839Sml } else if (!nxge_cksum_offload) { 2681678453a8Sspeer /* TCP checksum only. */ 2682678453a8Sspeer is_tcp_udp = ((pkt_type == RCR_PKT_IS_TCP) ? 268352ccf843Smisaki B_TRUE: B_FALSE); 2684678453a8Sspeer } 268544961713Sgirish 268644961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_receive_packet: " 268752ccf843Smisaki "is_valid 0x%x multi 0x%llx pkt %d frag %d error %d", 268852ccf843Smisaki is_valid, multi, is_tcp_udp, frag, error_type)); 268944961713Sgirish 269044961713Sgirish if (is_tcp_udp && !frag && !error_type) { 269144961713Sgirish (void) hcksum_assoc(nmp, NULL, NULL, 0, 0, 0, 0, 269252ccf843Smisaki HCK_FULLCKSUM_OK | HCK_FULLCKSUM, 0); 269344961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 269452ccf843Smisaki "==> nxge_receive_packet: Full tcp/udp cksum " 269552ccf843Smisaki "is_valid 0x%x multi 0x%llx pkt %d frag %d " 269652ccf843Smisaki "error %d", 269752ccf843Smisaki is_valid, multi, is_tcp_udp, frag, error_type)); 269844961713Sgirish } 269944961713Sgirish } 270044961713Sgirish 270144961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, 270252ccf843Smisaki "==> nxge_receive_packet: *mp 0x%016llx", *mp)); 270344961713Sgirish 270444961713Sgirish *multi_p = (multi == RCR_MULTI_MASK); 270544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_receive_packet: " 270652ccf843Smisaki "multi %d nmp 0x%016llx *mp 0x%016llx *mp_cont 0x%016llx", 270752ccf843Smisaki *multi_p, nmp, *mp, *mp_cont)); 270844961713Sgirish } 270944961713Sgirish 271044961713Sgirish /*ARGSUSED*/ 271144961713Sgirish static nxge_status_t 2712678453a8Sspeer nxge_rx_err_evnts(p_nxge_t nxgep, int channel, rx_dma_ctl_stat_t cs) 271344961713Sgirish { 271444961713Sgirish p_nxge_rx_ring_stats_t rdc_stats; 271544961713Sgirish npi_handle_t handle; 271644961713Sgirish npi_status_t rs; 271744961713Sgirish boolean_t rxchan_fatal = B_FALSE; 271844961713Sgirish boolean_t rxport_fatal = B_FALSE; 271944961713Sgirish uint8_t portn; 272044961713Sgirish nxge_status_t status = NXGE_OK; 272144961713Sgirish uint32_t error_disp_cnt = NXGE_ERROR_SHOW_MAX; 272244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_rx_err_evnts")); 272344961713Sgirish 272444961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 272544961713Sgirish portn = nxgep->mac.portnum; 2726678453a8Sspeer rdc_stats = &nxgep->statsp->rdc_stats[channel]; 272744961713Sgirish 272844961713Sgirish if (cs.bits.hdw.rbr_tmout) { 272944961713Sgirish rdc_stats->rx_rbr_tmout++; 273044961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 273152ccf843Smisaki NXGE_FM_EREPORT_RDMC_RBR_TMOUT); 273244961713Sgirish rxchan_fatal = B_TRUE; 273344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 273452ccf843Smisaki "==> nxge_rx_err_evnts: rx_rbr_timeout")); 273544961713Sgirish } 273644961713Sgirish if (cs.bits.hdw.rsp_cnt_err) { 273744961713Sgirish rdc_stats->rsp_cnt_err++; 273844961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 273952ccf843Smisaki NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR); 274044961713Sgirish rxchan_fatal = B_TRUE; 274144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 274252ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 274352ccf843Smisaki "rsp_cnt_err", channel)); 274444961713Sgirish } 274544961713Sgirish if (cs.bits.hdw.byte_en_bus) { 274644961713Sgirish rdc_stats->byte_en_bus++; 274744961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 274852ccf843Smisaki NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS); 274944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 275052ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 275152ccf843Smisaki "fatal error: byte_en_bus", channel)); 275244961713Sgirish rxchan_fatal = B_TRUE; 275344961713Sgirish } 275444961713Sgirish if (cs.bits.hdw.rsp_dat_err) { 275544961713Sgirish rdc_stats->rsp_dat_err++; 275644961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 275752ccf843Smisaki NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR); 275844961713Sgirish rxchan_fatal = B_TRUE; 275944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 276052ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 276152ccf843Smisaki "fatal error: rsp_dat_err", channel)); 276244961713Sgirish } 276344961713Sgirish if (cs.bits.hdw.rcr_ack_err) { 276444961713Sgirish rdc_stats->rcr_ack_err++; 276544961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 276652ccf843Smisaki NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR); 276744961713Sgirish rxchan_fatal = B_TRUE; 276844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 276952ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 277052ccf843Smisaki "fatal error: rcr_ack_err", channel)); 277144961713Sgirish } 277244961713Sgirish if (cs.bits.hdw.dc_fifo_err) { 277344961713Sgirish rdc_stats->dc_fifo_err++; 277444961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 277552ccf843Smisaki NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR); 277644961713Sgirish /* This is not a fatal error! */ 277744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 277852ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 277952ccf843Smisaki "dc_fifo_err", channel)); 278044961713Sgirish rxport_fatal = B_TRUE; 278144961713Sgirish } 278244961713Sgirish if ((cs.bits.hdw.rcr_sha_par) || (cs.bits.hdw.rbr_pre_par)) { 278344961713Sgirish if ((rs = npi_rxdma_ring_perr_stat_get(handle, 278452ccf843Smisaki &rdc_stats->errlog.pre_par, 278552ccf843Smisaki &rdc_stats->errlog.sha_par)) 278652ccf843Smisaki != NPI_SUCCESS) { 278744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 278852ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 278952ccf843Smisaki "rcr_sha_par: get perr", channel)); 279044961713Sgirish return (NXGE_ERROR | rs); 279144961713Sgirish } 279244961713Sgirish if (cs.bits.hdw.rcr_sha_par) { 279344961713Sgirish rdc_stats->rcr_sha_par++; 279444961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 279552ccf843Smisaki NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR); 279644961713Sgirish rxchan_fatal = B_TRUE; 279744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 279852ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 279952ccf843Smisaki "fatal error: rcr_sha_par", channel)); 280044961713Sgirish } 280144961713Sgirish if (cs.bits.hdw.rbr_pre_par) { 280244961713Sgirish rdc_stats->rbr_pre_par++; 280344961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 280452ccf843Smisaki NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR); 280544961713Sgirish rxchan_fatal = B_TRUE; 280644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 280752ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 280852ccf843Smisaki "fatal error: rbr_pre_par", channel)); 280944961713Sgirish } 281044961713Sgirish } 281163e23a19Syc /* 281263e23a19Syc * The Following 4 status bits are for information, the system 281363e23a19Syc * is running fine. There is no need to send FMA ereports or 281463e23a19Syc * log messages. 281563e23a19Syc */ 281644961713Sgirish if (cs.bits.hdw.port_drop_pkt) { 281744961713Sgirish rdc_stats->port_drop_pkt++; 281844961713Sgirish } 281944961713Sgirish if (cs.bits.hdw.wred_drop) { 282044961713Sgirish rdc_stats->wred_drop++; 282144961713Sgirish } 282244961713Sgirish if (cs.bits.hdw.rbr_pre_empty) { 282344961713Sgirish rdc_stats->rbr_pre_empty++; 282444961713Sgirish } 282544961713Sgirish if (cs.bits.hdw.rcr_shadow_full) { 282644961713Sgirish rdc_stats->rcr_shadow_full++; 282744961713Sgirish } 282844961713Sgirish if (cs.bits.hdw.config_err) { 282944961713Sgirish rdc_stats->config_err++; 283044961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 283152ccf843Smisaki NXGE_FM_EREPORT_RDMC_CONFIG_ERR); 283244961713Sgirish rxchan_fatal = B_TRUE; 283344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 283452ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 283552ccf843Smisaki "config error", channel)); 283644961713Sgirish } 283744961713Sgirish if (cs.bits.hdw.rcrincon) { 283844961713Sgirish rdc_stats->rcrincon++; 283944961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 284052ccf843Smisaki NXGE_FM_EREPORT_RDMC_RCRINCON); 284144961713Sgirish rxchan_fatal = B_TRUE; 284244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 284352ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 284452ccf843Smisaki "fatal error: rcrincon error", channel)); 284544961713Sgirish } 284644961713Sgirish if (cs.bits.hdw.rcrfull) { 284744961713Sgirish rdc_stats->rcrfull++; 284844961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 284952ccf843Smisaki NXGE_FM_EREPORT_RDMC_RCRFULL); 285044961713Sgirish rxchan_fatal = B_TRUE; 285144961713Sgirish if (rdc_stats->rcrfull < error_disp_cnt) 285244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 285352ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 285452ccf843Smisaki "fatal error: rcrfull error", channel)); 285544961713Sgirish } 285644961713Sgirish if (cs.bits.hdw.rbr_empty) { 285763e23a19Syc /* 285863e23a19Syc * This bit is for information, there is no need 285963e23a19Syc * send FMA ereport or log a message. 286063e23a19Syc */ 286144961713Sgirish rdc_stats->rbr_empty++; 286244961713Sgirish } 286344961713Sgirish if (cs.bits.hdw.rbrfull) { 286444961713Sgirish rdc_stats->rbrfull++; 286544961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 286652ccf843Smisaki NXGE_FM_EREPORT_RDMC_RBRFULL); 286744961713Sgirish rxchan_fatal = B_TRUE; 286844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 286952ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 287052ccf843Smisaki "fatal error: rbr_full error", channel)); 287144961713Sgirish } 287244961713Sgirish if (cs.bits.hdw.rbrlogpage) { 287344961713Sgirish rdc_stats->rbrlogpage++; 287444961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 287552ccf843Smisaki NXGE_FM_EREPORT_RDMC_RBRLOGPAGE); 287644961713Sgirish rxchan_fatal = B_TRUE; 287744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 287852ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 287952ccf843Smisaki "fatal error: rbr logical page error", channel)); 288044961713Sgirish } 288144961713Sgirish if (cs.bits.hdw.cfiglogpage) { 288244961713Sgirish rdc_stats->cfiglogpage++; 288344961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 288452ccf843Smisaki NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE); 288544961713Sgirish rxchan_fatal = B_TRUE; 288644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 288752ccf843Smisaki "==> nxge_rx_err_evnts(channel %d): " 288852ccf843Smisaki "fatal error: cfig logical page error", channel)); 288944961713Sgirish } 289044961713Sgirish 289144961713Sgirish if (rxport_fatal) { 289244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2893678453a8Sspeer " nxge_rx_err_evnts: fatal error on Port #%d\n", 2894678453a8Sspeer portn)); 2895678453a8Sspeer if (isLDOMguest(nxgep)) { 2896678453a8Sspeer status = NXGE_ERROR; 2897678453a8Sspeer } else { 2898678453a8Sspeer status = nxge_ipp_fatal_err_recover(nxgep); 2899678453a8Sspeer if (status == NXGE_OK) { 2900678453a8Sspeer FM_SERVICE_RESTORED(nxgep); 2901678453a8Sspeer } 290244961713Sgirish } 290344961713Sgirish } 290444961713Sgirish 290544961713Sgirish if (rxchan_fatal) { 290644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2907678453a8Sspeer " nxge_rx_err_evnts: fatal error on Channel #%d\n", 2908678453a8Sspeer channel)); 2909678453a8Sspeer if (isLDOMguest(nxgep)) { 2910678453a8Sspeer status = NXGE_ERROR; 2911678453a8Sspeer } else { 2912678453a8Sspeer status = nxge_rxdma_fatal_err_recover(nxgep, channel); 2913678453a8Sspeer if (status == NXGE_OK) { 2914678453a8Sspeer FM_SERVICE_RESTORED(nxgep); 2915678453a8Sspeer } 291644961713Sgirish } 291744961713Sgirish } 291844961713Sgirish 291944961713Sgirish NXGE_DEBUG_MSG((nxgep, RX2_CTL, "<== nxge_rx_err_evnts")); 292044961713Sgirish 292144961713Sgirish return (status); 292244961713Sgirish } 292344961713Sgirish 2924678453a8Sspeer /* 2925678453a8Sspeer * nxge_rdc_hvio_setup 2926678453a8Sspeer * 2927678453a8Sspeer * This code appears to setup some Hypervisor variables. 2928678453a8Sspeer * 2929678453a8Sspeer * Arguments: 2930678453a8Sspeer * nxgep 2931678453a8Sspeer * channel 2932678453a8Sspeer * 2933678453a8Sspeer * Notes: 2934678453a8Sspeer * What does NIU_LP_WORKAROUND mean? 2935678453a8Sspeer * 2936678453a8Sspeer * NPI/NXGE function calls: 2937678453a8Sspeer * na 2938678453a8Sspeer * 2939678453a8Sspeer * Context: 2940678453a8Sspeer * Any domain 2941678453a8Sspeer */ 2942678453a8Sspeer #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2943678453a8Sspeer static void 2944678453a8Sspeer nxge_rdc_hvio_setup( 2945678453a8Sspeer nxge_t *nxgep, int channel) 294644961713Sgirish { 2947678453a8Sspeer nxge_dma_common_t *dma_common; 2948678453a8Sspeer nxge_dma_common_t *dma_control; 2949678453a8Sspeer rx_rbr_ring_t *ring; 2950678453a8Sspeer 2951678453a8Sspeer ring = nxgep->rx_rbr_rings->rbr_rings[channel]; 2952678453a8Sspeer dma_common = nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 2953678453a8Sspeer 2954678453a8Sspeer ring->hv_set = B_FALSE; 2955678453a8Sspeer 2956678453a8Sspeer ring->hv_rx_buf_base_ioaddr_pp = (uint64_t) 2957678453a8Sspeer dma_common->orig_ioaddr_pp; 2958678453a8Sspeer ring->hv_rx_buf_ioaddr_size = (uint64_t) 2959678453a8Sspeer dma_common->orig_alength; 2960678453a8Sspeer 2961678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_map_rxdma_channel: " 2962678453a8Sspeer "channel %d data buf base io $%lx ($%p) size 0x%lx (%ld 0x%lx)", 2963678453a8Sspeer channel, ring->hv_rx_buf_base_ioaddr_pp, 2964678453a8Sspeer dma_common->ioaddr_pp, ring->hv_rx_buf_ioaddr_size, 2965678453a8Sspeer dma_common->orig_alength, dma_common->orig_alength)); 2966678453a8Sspeer 2967678453a8Sspeer dma_control = nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 2968678453a8Sspeer 2969678453a8Sspeer ring->hv_rx_cntl_base_ioaddr_pp = 2970678453a8Sspeer (uint64_t)dma_control->orig_ioaddr_pp; 2971678453a8Sspeer ring->hv_rx_cntl_ioaddr_size = 2972678453a8Sspeer (uint64_t)dma_control->orig_alength; 2973678453a8Sspeer 2974678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_map_rxdma_channel: " 2975678453a8Sspeer "channel %d cntl base io $%p ($%p) size 0x%llx (%d 0x%x)", 2976678453a8Sspeer channel, ring->hv_rx_cntl_base_ioaddr_pp, 2977678453a8Sspeer dma_control->ioaddr_pp, ring->hv_rx_cntl_ioaddr_size, 2978678453a8Sspeer dma_control->orig_alength, dma_control->orig_alength)); 2979678453a8Sspeer } 298044961713Sgirish #endif 298144961713Sgirish 2982678453a8Sspeer /* 2983678453a8Sspeer * nxge_map_rxdma 2984678453a8Sspeer * 2985678453a8Sspeer * Map an RDC into our kernel space. 2986678453a8Sspeer * 2987678453a8Sspeer * Arguments: 2988678453a8Sspeer * nxgep 2989678453a8Sspeer * channel The channel to map. 2990678453a8Sspeer * 2991678453a8Sspeer * Notes: 2992678453a8Sspeer * 1. Allocate & initialise a memory pool, if necessary. 2993678453a8Sspeer * 2. Allocate however many receive buffers are required. 2994678453a8Sspeer * 3. Setup buffers, descriptors, and mailbox. 2995678453a8Sspeer * 2996678453a8Sspeer * NPI/NXGE function calls: 2997678453a8Sspeer * nxge_alloc_rx_mem_pool() 2998678453a8Sspeer * nxge_alloc_rbb() 2999678453a8Sspeer * nxge_map_rxdma_channel() 3000678453a8Sspeer * 3001678453a8Sspeer * Registers accessed: 3002678453a8Sspeer * 3003678453a8Sspeer * Context: 3004678453a8Sspeer * Any domain 3005678453a8Sspeer */ 3006678453a8Sspeer static nxge_status_t 3007678453a8Sspeer nxge_map_rxdma(p_nxge_t nxgep, int channel) 3008678453a8Sspeer { 3009678453a8Sspeer nxge_dma_common_t **data; 3010678453a8Sspeer nxge_dma_common_t **control; 3011678453a8Sspeer rx_rbr_ring_t **rbr_ring; 3012678453a8Sspeer rx_rcr_ring_t **rcr_ring; 3013678453a8Sspeer rx_mbox_t **mailbox; 3014678453a8Sspeer uint32_t chunks; 301544961713Sgirish 3016678453a8Sspeer nxge_status_t status; 301744961713Sgirish 3018678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_map_rxdma")); 301944961713Sgirish 3020678453a8Sspeer if (!nxgep->rx_buf_pool_p) { 3021678453a8Sspeer if (nxge_alloc_rx_mem_pool(nxgep) != NXGE_OK) { 3022678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3023678453a8Sspeer "<== nxge_map_rxdma: buf not allocated")); 3024678453a8Sspeer return (NXGE_ERROR); 3025678453a8Sspeer } 302644961713Sgirish } 302744961713Sgirish 3028678453a8Sspeer if (nxge_alloc_rxb(nxgep, channel) != NXGE_OK) 3029678453a8Sspeer return (NXGE_ERROR); 303014ea4bb7Ssd 303114ea4bb7Ssd /* 303214ea4bb7Ssd * Timeout should be set based on the system clock divider. 303314ea4bb7Ssd * The following timeout value of 1 assumes that the 303414ea4bb7Ssd * granularity (1000) is 3 microseconds running at 300MHz. 303514ea4bb7Ssd */ 303614ea4bb7Ssd 303714ea4bb7Ssd nxgep->intr_threshold = RXDMA_RCR_PTHRES_DEFAULT; 303814ea4bb7Ssd nxgep->intr_timeout = RXDMA_RCR_TO_DEFAULT; 303944961713Sgirish 304044961713Sgirish /* 3041678453a8Sspeer * Map descriptors from the buffer polls for each dma channel. 304244961713Sgirish */ 304344961713Sgirish 3044678453a8Sspeer /* 3045678453a8Sspeer * Set up and prepare buffer blocks, descriptors 3046678453a8Sspeer * and mailbox. 3047678453a8Sspeer */ 3048678453a8Sspeer data = &nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 3049678453a8Sspeer rbr_ring = &nxgep->rx_rbr_rings->rbr_rings[channel]; 3050678453a8Sspeer chunks = nxgep->rx_buf_pool_p->num_chunks[channel]; 305144961713Sgirish 3052678453a8Sspeer control = &nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 3053678453a8Sspeer rcr_ring = &nxgep->rx_rcr_rings->rcr_rings[channel]; 305444961713Sgirish 3055678453a8Sspeer mailbox = &nxgep->rx_mbox_areas_p->rxmbox_areas[channel]; 305644961713Sgirish 3057678453a8Sspeer status = nxge_map_rxdma_channel(nxgep, channel, data, rbr_ring, 3058678453a8Sspeer chunks, control, rcr_ring, mailbox); 3059678453a8Sspeer if (status != NXGE_OK) { 3060678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 306152ccf843Smisaki "==> nxge_map_rxdma: nxge_map_rxdma_channel(%d) " 306252ccf843Smisaki "returned 0x%x", 306352ccf843Smisaki channel, status)); 3064678453a8Sspeer return (status); 3065678453a8Sspeer } 3066678453a8Sspeer nxgep->rx_rbr_rings->rbr_rings[channel]->index = (uint16_t)channel; 3067678453a8Sspeer nxgep->rx_rcr_rings->rcr_rings[channel]->index = (uint16_t)channel; 3068678453a8Sspeer nxgep->rx_rcr_rings->rcr_rings[channel]->rdc_stats = 3069678453a8Sspeer &nxgep->statsp->rdc_stats[channel]; 307044961713Sgirish 3071678453a8Sspeer #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3072678453a8Sspeer if (!isLDOMguest(nxgep)) 3073678453a8Sspeer nxge_rdc_hvio_setup(nxgep, channel); 3074678453a8Sspeer #endif 307544961713Sgirish 307644961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3077678453a8Sspeer "<== nxge_map_rxdma: (status 0x%x channel %d)", status, channel)); 307844961713Sgirish 307944961713Sgirish return (status); 308044961713Sgirish } 308144961713Sgirish 308244961713Sgirish static void 3083678453a8Sspeer nxge_unmap_rxdma(p_nxge_t nxgep, int channel) 308444961713Sgirish { 3085678453a8Sspeer rx_rbr_ring_t *rbr_ring; 3086678453a8Sspeer rx_rcr_ring_t *rcr_ring; 3087678453a8Sspeer rx_mbox_t *mailbox; 308844961713Sgirish 3089678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_unmap_rxdma(%d)", channel)); 309044961713Sgirish 3091678453a8Sspeer if (!nxgep->rx_rbr_rings || !nxgep->rx_rcr_rings || 3092678453a8Sspeer !nxgep->rx_mbox_areas_p) 309344961713Sgirish return; 309444961713Sgirish 3095678453a8Sspeer rbr_ring = nxgep->rx_rbr_rings->rbr_rings[channel]; 3096678453a8Sspeer rcr_ring = nxgep->rx_rcr_rings->rcr_rings[channel]; 3097678453a8Sspeer mailbox = nxgep->rx_mbox_areas_p->rxmbox_areas[channel]; 309844961713Sgirish 3099678453a8Sspeer if (!rbr_ring || !rcr_ring || !mailbox) 3100678453a8Sspeer return; 310144961713Sgirish 3102678453a8Sspeer (void) nxge_unmap_rxdma_channel( 310352ccf843Smisaki nxgep, channel, rbr_ring, rcr_ring, mailbox); 310444961713Sgirish 3105678453a8Sspeer nxge_free_rxb(nxgep, channel); 310644961713Sgirish 3107678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_unmap_rxdma")); 310844961713Sgirish } 310944961713Sgirish 311044961713Sgirish nxge_status_t 311144961713Sgirish nxge_map_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 311244961713Sgirish p_nxge_dma_common_t *dma_buf_p, p_rx_rbr_ring_t *rbr_p, 311344961713Sgirish uint32_t num_chunks, 311444961713Sgirish p_nxge_dma_common_t *dma_cntl_p, p_rx_rcr_ring_t *rcr_p, 311544961713Sgirish p_rx_mbox_t *rx_mbox_p) 311644961713Sgirish { 311744961713Sgirish int status = NXGE_OK; 311844961713Sgirish 311944961713Sgirish /* 312044961713Sgirish * Set up and prepare buffer blocks, descriptors 312144961713Sgirish * and mailbox. 312244961713Sgirish */ 312344961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 312452ccf843Smisaki "==> nxge_map_rxdma_channel (channel %d)", channel)); 312544961713Sgirish /* 312644961713Sgirish * Receive buffer blocks 312744961713Sgirish */ 312844961713Sgirish status = nxge_map_rxdma_channel_buf_ring(nxgep, channel, 312952ccf843Smisaki dma_buf_p, rbr_p, num_chunks); 313044961713Sgirish if (status != NXGE_OK) { 313144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 313252ccf843Smisaki "==> nxge_map_rxdma_channel (channel %d): " 313352ccf843Smisaki "map buffer failed 0x%x", channel, status)); 313444961713Sgirish goto nxge_map_rxdma_channel_exit; 313544961713Sgirish } 313644961713Sgirish 313744961713Sgirish /* 313844961713Sgirish * Receive block ring, completion ring and mailbox. 313944961713Sgirish */ 314044961713Sgirish status = nxge_map_rxdma_channel_cfg_ring(nxgep, channel, 314152ccf843Smisaki dma_cntl_p, rbr_p, rcr_p, rx_mbox_p); 314244961713Sgirish if (status != NXGE_OK) { 314344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 314452ccf843Smisaki "==> nxge_map_rxdma_channel (channel %d): " 314552ccf843Smisaki "map config failed 0x%x", channel, status)); 314644961713Sgirish goto nxge_map_rxdma_channel_fail2; 314744961713Sgirish } 314844961713Sgirish 314944961713Sgirish goto nxge_map_rxdma_channel_exit; 315044961713Sgirish 315144961713Sgirish nxge_map_rxdma_channel_fail3: 315244961713Sgirish /* Free rbr, rcr */ 315344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 315452ccf843Smisaki "==> nxge_map_rxdma_channel: free rbr/rcr " 315552ccf843Smisaki "(status 0x%x channel %d)", 315652ccf843Smisaki status, channel)); 315744961713Sgirish nxge_unmap_rxdma_channel_cfg_ring(nxgep, 315852ccf843Smisaki *rcr_p, *rx_mbox_p); 315944961713Sgirish 316044961713Sgirish nxge_map_rxdma_channel_fail2: 316144961713Sgirish /* Free buffer blocks */ 316244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 316352ccf843Smisaki "==> nxge_map_rxdma_channel: free rx buffers" 316452ccf843Smisaki "(nxgep 0x%x status 0x%x channel %d)", 316552ccf843Smisaki nxgep, status, channel)); 316644961713Sgirish nxge_unmap_rxdma_channel_buf_ring(nxgep, *rbr_p); 316744961713Sgirish 316856d930aeSspeer status = NXGE_ERROR; 316956d930aeSspeer 317044961713Sgirish nxge_map_rxdma_channel_exit: 317144961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 317252ccf843Smisaki "<== nxge_map_rxdma_channel: " 317352ccf843Smisaki "(nxgep 0x%x status 0x%x channel %d)", 317452ccf843Smisaki nxgep, status, channel)); 317544961713Sgirish 317644961713Sgirish return (status); 317744961713Sgirish } 317844961713Sgirish 317944961713Sgirish /*ARGSUSED*/ 318044961713Sgirish static void 318144961713Sgirish nxge_unmap_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 318244961713Sgirish p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 318344961713Sgirish { 318444961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 318552ccf843Smisaki "==> nxge_unmap_rxdma_channel (channel %d)", channel)); 318644961713Sgirish 318744961713Sgirish /* 318844961713Sgirish * unmap receive block ring, completion ring and mailbox. 318944961713Sgirish */ 319044961713Sgirish (void) nxge_unmap_rxdma_channel_cfg_ring(nxgep, 319152ccf843Smisaki rcr_p, rx_mbox_p); 319244961713Sgirish 319344961713Sgirish /* unmap buffer blocks */ 319444961713Sgirish (void) nxge_unmap_rxdma_channel_buf_ring(nxgep, rbr_p); 319544961713Sgirish 319644961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_unmap_rxdma_channel")); 319744961713Sgirish } 319844961713Sgirish 319944961713Sgirish /*ARGSUSED*/ 320044961713Sgirish static nxge_status_t 320144961713Sgirish nxge_map_rxdma_channel_cfg_ring(p_nxge_t nxgep, uint16_t dma_channel, 320244961713Sgirish p_nxge_dma_common_t *dma_cntl_p, p_rx_rbr_ring_t *rbr_p, 320344961713Sgirish p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p) 320444961713Sgirish { 320544961713Sgirish p_rx_rbr_ring_t rbrp; 320644961713Sgirish p_rx_rcr_ring_t rcrp; 320744961713Sgirish p_rx_mbox_t mboxp; 320844961713Sgirish p_nxge_dma_common_t cntl_dmap; 320944961713Sgirish p_nxge_dma_common_t dmap; 321044961713Sgirish p_rx_msg_t *rx_msg_ring; 321144961713Sgirish p_rx_msg_t rx_msg_p; 321244961713Sgirish p_rbr_cfig_a_t rcfga_p; 321344961713Sgirish p_rbr_cfig_b_t rcfgb_p; 321444961713Sgirish p_rcrcfig_a_t cfga_p; 321544961713Sgirish p_rcrcfig_b_t cfgb_p; 321644961713Sgirish p_rxdma_cfig1_t cfig1_p; 321744961713Sgirish p_rxdma_cfig2_t cfig2_p; 321844961713Sgirish p_rbr_kick_t kick_p; 321944961713Sgirish uint32_t dmaaddrp; 322044961713Sgirish uint32_t *rbr_vaddrp; 322144961713Sgirish uint32_t bkaddr; 322244961713Sgirish nxge_status_t status = NXGE_OK; 322344961713Sgirish int i; 322444961713Sgirish uint32_t nxge_port_rcr_size; 322544961713Sgirish 322644961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 322752ccf843Smisaki "==> nxge_map_rxdma_channel_cfg_ring")); 322844961713Sgirish 322944961713Sgirish cntl_dmap = *dma_cntl_p; 323044961713Sgirish 323144961713Sgirish /* Map in the receive block ring */ 323244961713Sgirish rbrp = *rbr_p; 323344961713Sgirish dmap = (p_nxge_dma_common_t)&rbrp->rbr_desc; 323444961713Sgirish nxge_setup_dma_common(dmap, cntl_dmap, rbrp->rbb_max, 4); 323544961713Sgirish /* 323644961713Sgirish * Zero out buffer block ring descriptors. 323744961713Sgirish */ 323844961713Sgirish bzero((caddr_t)dmap->kaddrp, dmap->alength); 323944961713Sgirish 324044961713Sgirish rcfga_p = &(rbrp->rbr_cfga); 324144961713Sgirish rcfgb_p = &(rbrp->rbr_cfgb); 324244961713Sgirish kick_p = &(rbrp->rbr_kick); 324344961713Sgirish rcfga_p->value = 0; 324444961713Sgirish rcfgb_p->value = 0; 324544961713Sgirish kick_p->value = 0; 324644961713Sgirish rbrp->rbr_addr = dmap->dma_cookie.dmac_laddress; 324744961713Sgirish rcfga_p->value = (rbrp->rbr_addr & 324852ccf843Smisaki (RBR_CFIG_A_STDADDR_MASK | 324952ccf843Smisaki RBR_CFIG_A_STDADDR_BASE_MASK)); 325044961713Sgirish rcfga_p->value |= ((uint64_t)rbrp->rbb_max << RBR_CFIG_A_LEN_SHIFT); 325144961713Sgirish 325244961713Sgirish rcfgb_p->bits.ldw.bufsz0 = rbrp->pkt_buf_size0; 325344961713Sgirish rcfgb_p->bits.ldw.vld0 = 1; 325444961713Sgirish rcfgb_p->bits.ldw.bufsz1 = rbrp->pkt_buf_size1; 325544961713Sgirish rcfgb_p->bits.ldw.vld1 = 1; 325644961713Sgirish rcfgb_p->bits.ldw.bufsz2 = rbrp->pkt_buf_size2; 325744961713Sgirish rcfgb_p->bits.ldw.vld2 = 1; 325844961713Sgirish rcfgb_p->bits.ldw.bksize = nxgep->rx_bksize_code; 325944961713Sgirish 326044961713Sgirish /* 326144961713Sgirish * For each buffer block, enter receive block address to the ring. 326244961713Sgirish */ 326344961713Sgirish rbr_vaddrp = (uint32_t *)dmap->kaddrp; 326444961713Sgirish rbrp->rbr_desc_vp = (uint32_t *)dmap->kaddrp; 326544961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 326652ccf843Smisaki "==> nxge_map_rxdma_channel_cfg_ring: channel %d " 326752ccf843Smisaki "rbr_vaddrp $%p", dma_channel, rbr_vaddrp)); 326844961713Sgirish 326944961713Sgirish rx_msg_ring = rbrp->rx_msg_ring; 327044961713Sgirish for (i = 0; i < rbrp->tnblocks; i++) { 327144961713Sgirish rx_msg_p = rx_msg_ring[i]; 327244961713Sgirish rx_msg_p->nxgep = nxgep; 327344961713Sgirish rx_msg_p->rx_rbr_p = rbrp; 327444961713Sgirish bkaddr = (uint32_t) 327552ccf843Smisaki ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress 327652ccf843Smisaki >> RBR_BKADDR_SHIFT)); 327744961713Sgirish rx_msg_p->free = B_FALSE; 327844961713Sgirish rx_msg_p->max_usage_cnt = 0xbaddcafe; 327944961713Sgirish 328044961713Sgirish *rbr_vaddrp++ = bkaddr; 328144961713Sgirish } 328244961713Sgirish 328344961713Sgirish kick_p->bits.ldw.bkadd = rbrp->rbb_max; 328444961713Sgirish rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 328544961713Sgirish 328644961713Sgirish rbrp->rbr_rd_index = 0; 328744961713Sgirish 328844961713Sgirish rbrp->rbr_consumed = 0; 328944961713Sgirish rbrp->rbr_use_bcopy = B_TRUE; 329044961713Sgirish rbrp->rbr_bufsize_type = RCR_PKTBUFSZ_0; 329144961713Sgirish /* 329244961713Sgirish * Do bcopy on packets greater than bcopy size once 329344961713Sgirish * the lo threshold is reached. 329444961713Sgirish * This lo threshold should be less than the hi threshold. 329544961713Sgirish * 329644961713Sgirish * Do bcopy on every packet once the hi threshold is reached. 329744961713Sgirish */ 329844961713Sgirish if (nxge_rx_threshold_lo >= nxge_rx_threshold_hi) { 329944961713Sgirish /* default it to use hi */ 330044961713Sgirish nxge_rx_threshold_lo = nxge_rx_threshold_hi; 330144961713Sgirish } 330244961713Sgirish 330344961713Sgirish if (nxge_rx_buf_size_type > NXGE_RBR_TYPE2) { 330444961713Sgirish nxge_rx_buf_size_type = NXGE_RBR_TYPE2; 330544961713Sgirish } 330644961713Sgirish rbrp->rbr_bufsize_type = nxge_rx_buf_size_type; 330744961713Sgirish 330844961713Sgirish switch (nxge_rx_threshold_hi) { 330944961713Sgirish default: 331044961713Sgirish case NXGE_RX_COPY_NONE: 331144961713Sgirish /* Do not do bcopy at all */ 331244961713Sgirish rbrp->rbr_use_bcopy = B_FALSE; 331344961713Sgirish rbrp->rbr_threshold_hi = rbrp->rbb_max; 331444961713Sgirish break; 331544961713Sgirish 331644961713Sgirish case NXGE_RX_COPY_1: 331744961713Sgirish case NXGE_RX_COPY_2: 331844961713Sgirish case NXGE_RX_COPY_3: 331944961713Sgirish case NXGE_RX_COPY_4: 332044961713Sgirish case NXGE_RX_COPY_5: 332144961713Sgirish case NXGE_RX_COPY_6: 332244961713Sgirish case NXGE_RX_COPY_7: 332344961713Sgirish rbrp->rbr_threshold_hi = 332452ccf843Smisaki rbrp->rbb_max * 332552ccf843Smisaki (nxge_rx_threshold_hi)/NXGE_RX_BCOPY_SCALE; 332644961713Sgirish break; 332744961713Sgirish 332844961713Sgirish case NXGE_RX_COPY_ALL: 332944961713Sgirish rbrp->rbr_threshold_hi = 0; 333044961713Sgirish break; 333144961713Sgirish } 333244961713Sgirish 333344961713Sgirish switch (nxge_rx_threshold_lo) { 333444961713Sgirish default: 333544961713Sgirish case NXGE_RX_COPY_NONE: 333644961713Sgirish /* Do not do bcopy at all */ 333744961713Sgirish if (rbrp->rbr_use_bcopy) { 333844961713Sgirish rbrp->rbr_use_bcopy = B_FALSE; 333944961713Sgirish } 334044961713Sgirish rbrp->rbr_threshold_lo = rbrp->rbb_max; 334144961713Sgirish break; 334244961713Sgirish 334344961713Sgirish case NXGE_RX_COPY_1: 334444961713Sgirish case NXGE_RX_COPY_2: 334544961713Sgirish case NXGE_RX_COPY_3: 334644961713Sgirish case NXGE_RX_COPY_4: 334744961713Sgirish case NXGE_RX_COPY_5: 334844961713Sgirish case NXGE_RX_COPY_6: 334944961713Sgirish case NXGE_RX_COPY_7: 335044961713Sgirish rbrp->rbr_threshold_lo = 335152ccf843Smisaki rbrp->rbb_max * 335252ccf843Smisaki (nxge_rx_threshold_lo)/NXGE_RX_BCOPY_SCALE; 335344961713Sgirish break; 335444961713Sgirish 335544961713Sgirish case NXGE_RX_COPY_ALL: 335644961713Sgirish rbrp->rbr_threshold_lo = 0; 335744961713Sgirish break; 335844961713Sgirish } 335944961713Sgirish 336044961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 336152ccf843Smisaki "nxge_map_rxdma_channel_cfg_ring: channel %d " 336252ccf843Smisaki "rbb_max %d " 336352ccf843Smisaki "rbrp->rbr_bufsize_type %d " 336452ccf843Smisaki "rbb_threshold_hi %d " 336552ccf843Smisaki "rbb_threshold_lo %d", 336652ccf843Smisaki dma_channel, 336752ccf843Smisaki rbrp->rbb_max, 336852ccf843Smisaki rbrp->rbr_bufsize_type, 336952ccf843Smisaki rbrp->rbr_threshold_hi, 337052ccf843Smisaki rbrp->rbr_threshold_lo)); 337144961713Sgirish 337244961713Sgirish rbrp->page_valid.value = 0; 337344961713Sgirish rbrp->page_mask_1.value = rbrp->page_mask_2.value = 0; 337444961713Sgirish rbrp->page_value_1.value = rbrp->page_value_2.value = 0; 337544961713Sgirish rbrp->page_reloc_1.value = rbrp->page_reloc_2.value = 0; 337644961713Sgirish rbrp->page_hdl.value = 0; 337744961713Sgirish 337844961713Sgirish rbrp->page_valid.bits.ldw.page0 = 1; 337944961713Sgirish rbrp->page_valid.bits.ldw.page1 = 1; 338044961713Sgirish 338144961713Sgirish /* Map in the receive completion ring */ 338244961713Sgirish rcrp = (p_rx_rcr_ring_t) 338352ccf843Smisaki KMEM_ZALLOC(sizeof (rx_rcr_ring_t), KM_SLEEP); 338444961713Sgirish rcrp->rdc = dma_channel; 338544961713Sgirish 338644961713Sgirish nxge_port_rcr_size = nxgep->nxge_port_rcr_size; 338744961713Sgirish rcrp->comp_size = nxge_port_rcr_size; 338844961713Sgirish rcrp->comp_wrap_mask = nxge_port_rcr_size - 1; 338944961713Sgirish 339044961713Sgirish rcrp->max_receive_pkts = nxge_max_rx_pkts; 339144961713Sgirish 339244961713Sgirish dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 339344961713Sgirish nxge_setup_dma_common(dmap, cntl_dmap, rcrp->comp_size, 339452ccf843Smisaki sizeof (rcr_entry_t)); 339544961713Sgirish rcrp->comp_rd_index = 0; 339644961713Sgirish rcrp->comp_wt_index = 0; 339744961713Sgirish rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 339852ccf843Smisaki (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 3399adfcba55Sjoycey #if defined(__i386) 340052ccf843Smisaki rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 340152ccf843Smisaki (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3402adfcba55Sjoycey #else 340352ccf843Smisaki rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 340452ccf843Smisaki (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3405adfcba55Sjoycey #endif 340644961713Sgirish 340744961713Sgirish rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 340852ccf843Smisaki (nxge_port_rcr_size - 1); 340944961713Sgirish rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 341052ccf843Smisaki (nxge_port_rcr_size - 1); 341144961713Sgirish 341244961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 341352ccf843Smisaki "==> nxge_map_rxdma_channel_cfg_ring: " 341452ccf843Smisaki "channel %d " 341552ccf843Smisaki "rbr_vaddrp $%p " 341652ccf843Smisaki "rcr_desc_rd_head_p $%p " 341752ccf843Smisaki "rcr_desc_rd_head_pp $%p " 341852ccf843Smisaki "rcr_desc_rd_last_p $%p " 341952ccf843Smisaki "rcr_desc_rd_last_pp $%p ", 342052ccf843Smisaki dma_channel, 342152ccf843Smisaki rbr_vaddrp, 342252ccf843Smisaki rcrp->rcr_desc_rd_head_p, 342352ccf843Smisaki rcrp->rcr_desc_rd_head_pp, 342452ccf843Smisaki rcrp->rcr_desc_last_p, 342552ccf843Smisaki rcrp->rcr_desc_last_pp)); 342644961713Sgirish 342744961713Sgirish /* 342844961713Sgirish * Zero out buffer block ring descriptors. 342944961713Sgirish */ 343044961713Sgirish bzero((caddr_t)dmap->kaddrp, dmap->alength); 343114ea4bb7Ssd rcrp->intr_timeout = nxgep->intr_timeout; 343214ea4bb7Ssd rcrp->intr_threshold = nxgep->intr_threshold; 343344961713Sgirish rcrp->full_hdr_flag = B_FALSE; 343444961713Sgirish rcrp->sw_priv_hdr_len = 0; 343544961713Sgirish 343644961713Sgirish cfga_p = &(rcrp->rcr_cfga); 343744961713Sgirish cfgb_p = &(rcrp->rcr_cfgb); 343844961713Sgirish cfga_p->value = 0; 343944961713Sgirish cfgb_p->value = 0; 344044961713Sgirish rcrp->rcr_addr = dmap->dma_cookie.dmac_laddress; 344144961713Sgirish cfga_p->value = (rcrp->rcr_addr & 344252ccf843Smisaki (RCRCFIG_A_STADDR_MASK | 344352ccf843Smisaki RCRCFIG_A_STADDR_BASE_MASK)); 344444961713Sgirish 344544961713Sgirish rcfga_p->value |= ((uint64_t)rcrp->comp_size << 344652ccf843Smisaki RCRCFIG_A_LEN_SHIF); 344744961713Sgirish 344844961713Sgirish /* 344944961713Sgirish * Timeout should be set based on the system clock divider. 345044961713Sgirish * The following timeout value of 1 assumes that the 345144961713Sgirish * granularity (1000) is 3 microseconds running at 300MHz. 345244961713Sgirish */ 345314ea4bb7Ssd cfgb_p->bits.ldw.pthres = rcrp->intr_threshold; 345414ea4bb7Ssd cfgb_p->bits.ldw.timeout = rcrp->intr_timeout; 345544961713Sgirish cfgb_p->bits.ldw.entout = 1; 345644961713Sgirish 345744961713Sgirish /* Map in the mailbox */ 345844961713Sgirish mboxp = (p_rx_mbox_t) 345952ccf843Smisaki KMEM_ZALLOC(sizeof (rx_mbox_t), KM_SLEEP); 346044961713Sgirish dmap = (p_nxge_dma_common_t)&mboxp->rx_mbox; 346144961713Sgirish nxge_setup_dma_common(dmap, cntl_dmap, 1, sizeof (rxdma_mailbox_t)); 346244961713Sgirish cfig1_p = (p_rxdma_cfig1_t)&mboxp->rx_cfg1; 346344961713Sgirish cfig2_p = (p_rxdma_cfig2_t)&mboxp->rx_cfg2; 346444961713Sgirish cfig1_p->value = cfig2_p->value = 0; 346544961713Sgirish 346644961713Sgirish mboxp->mbox_addr = dmap->dma_cookie.dmac_laddress; 346744961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 346852ccf843Smisaki "==> nxge_map_rxdma_channel_cfg_ring: " 346952ccf843Smisaki "channel %d cfg1 0x%016llx cfig2 0x%016llx cookie 0x%016llx", 347052ccf843Smisaki dma_channel, cfig1_p->value, cfig2_p->value, 347152ccf843Smisaki mboxp->mbox_addr)); 347244961713Sgirish 347344961713Sgirish dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress >> 32 347452ccf843Smisaki & 0xfff); 347544961713Sgirish cfig1_p->bits.ldw.mbaddr_h = dmaaddrp; 347644961713Sgirish 347744961713Sgirish 347844961713Sgirish dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 0xffffffff); 347944961713Sgirish dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 348052ccf843Smisaki RXDMA_CFIG2_MBADDR_L_MASK); 348144961713Sgirish 348244961713Sgirish cfig2_p->bits.ldw.mbaddr = (dmaaddrp >> RXDMA_CFIG2_MBADDR_L_SHIFT); 348344961713Sgirish 348444961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 348552ccf843Smisaki "==> nxge_map_rxdma_channel_cfg_ring: " 348652ccf843Smisaki "channel %d damaddrp $%p " 348752ccf843Smisaki "cfg1 0x%016llx cfig2 0x%016llx", 348852ccf843Smisaki dma_channel, dmaaddrp, 348952ccf843Smisaki cfig1_p->value, cfig2_p->value)); 349044961713Sgirish 349144961713Sgirish cfig2_p->bits.ldw.full_hdr = rcrp->full_hdr_flag; 349244961713Sgirish cfig2_p->bits.ldw.offset = rcrp->sw_priv_hdr_len; 349344961713Sgirish 349444961713Sgirish rbrp->rx_rcr_p = rcrp; 349544961713Sgirish rcrp->rx_rbr_p = rbrp; 349644961713Sgirish *rcr_p = rcrp; 349744961713Sgirish *rx_mbox_p = mboxp; 349844961713Sgirish 349944961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 350052ccf843Smisaki "<== nxge_map_rxdma_channel_cfg_ring status 0x%08x", status)); 350144961713Sgirish 350244961713Sgirish return (status); 350344961713Sgirish } 350444961713Sgirish 350544961713Sgirish /*ARGSUSED*/ 350644961713Sgirish static void 350744961713Sgirish nxge_unmap_rxdma_channel_cfg_ring(p_nxge_t nxgep, 350844961713Sgirish p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 350944961713Sgirish { 351044961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 351152ccf843Smisaki "==> nxge_unmap_rxdma_channel_cfg_ring: channel %d", 351252ccf843Smisaki rcr_p->rdc)); 351344961713Sgirish 351444961713Sgirish KMEM_FREE(rcr_p, sizeof (rx_rcr_ring_t)); 351544961713Sgirish KMEM_FREE(rx_mbox_p, sizeof (rx_mbox_t)); 351644961713Sgirish 351744961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 351852ccf843Smisaki "<== nxge_unmap_rxdma_channel_cfg_ring")); 351944961713Sgirish } 352044961713Sgirish 352144961713Sgirish static nxge_status_t 352244961713Sgirish nxge_map_rxdma_channel_buf_ring(p_nxge_t nxgep, uint16_t channel, 352344961713Sgirish p_nxge_dma_common_t *dma_buf_p, 352444961713Sgirish p_rx_rbr_ring_t *rbr_p, uint32_t num_chunks) 352544961713Sgirish { 352644961713Sgirish p_rx_rbr_ring_t rbrp; 352744961713Sgirish p_nxge_dma_common_t dma_bufp, tmp_bufp; 352844961713Sgirish p_rx_msg_t *rx_msg_ring; 352944961713Sgirish p_rx_msg_t rx_msg_p; 353044961713Sgirish p_mblk_t mblk_p; 353144961713Sgirish 353244961713Sgirish rxring_info_t *ring_info; 353344961713Sgirish nxge_status_t status = NXGE_OK; 353444961713Sgirish int i, j, index; 353544961713Sgirish uint32_t size, bsize, nblocks, nmsgs; 353644961713Sgirish 353744961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 353852ccf843Smisaki "==> nxge_map_rxdma_channel_buf_ring: channel %d", 353952ccf843Smisaki channel)); 354044961713Sgirish 354144961713Sgirish dma_bufp = tmp_bufp = *dma_buf_p; 354244961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 354352ccf843Smisaki " nxge_map_rxdma_channel_buf_ring: channel %d to map %d " 354452ccf843Smisaki "chunks bufp 0x%016llx", 354552ccf843Smisaki channel, num_chunks, dma_bufp)); 354644961713Sgirish 354744961713Sgirish nmsgs = 0; 354844961713Sgirish for (i = 0; i < num_chunks; i++, tmp_bufp++) { 354944961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 355052ccf843Smisaki "==> nxge_map_rxdma_channel_buf_ring: channel %d " 355152ccf843Smisaki "bufp 0x%016llx nblocks %d nmsgs %d", 355252ccf843Smisaki channel, tmp_bufp, tmp_bufp->nblocks, nmsgs)); 355344961713Sgirish nmsgs += tmp_bufp->nblocks; 355444961713Sgirish } 355544961713Sgirish if (!nmsgs) { 355656d930aeSspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 355752ccf843Smisaki "<== nxge_map_rxdma_channel_buf_ring: channel %d " 355852ccf843Smisaki "no msg blocks", 355952ccf843Smisaki channel)); 356044961713Sgirish status = NXGE_ERROR; 356144961713Sgirish goto nxge_map_rxdma_channel_buf_ring_exit; 356244961713Sgirish } 356344961713Sgirish 3564007969e0Stm rbrp = (p_rx_rbr_ring_t)KMEM_ZALLOC(sizeof (*rbrp), KM_SLEEP); 356544961713Sgirish 356644961713Sgirish size = nmsgs * sizeof (p_rx_msg_t); 356744961713Sgirish rx_msg_ring = KMEM_ZALLOC(size, KM_SLEEP); 356844961713Sgirish ring_info = (rxring_info_t *)KMEM_ZALLOC(sizeof (rxring_info_t), 356952ccf843Smisaki KM_SLEEP); 357044961713Sgirish 357144961713Sgirish MUTEX_INIT(&rbrp->lock, NULL, MUTEX_DRIVER, 357252ccf843Smisaki (void *)nxgep->interrupt_cookie); 357344961713Sgirish MUTEX_INIT(&rbrp->post_lock, NULL, MUTEX_DRIVER, 357452ccf843Smisaki (void *)nxgep->interrupt_cookie); 357544961713Sgirish rbrp->rdc = channel; 357644961713Sgirish rbrp->num_blocks = num_chunks; 357744961713Sgirish rbrp->tnblocks = nmsgs; 357844961713Sgirish rbrp->rbb_max = nmsgs; 357944961713Sgirish rbrp->rbr_max_size = nmsgs; 358044961713Sgirish rbrp->rbr_wrap_mask = (rbrp->rbb_max - 1); 358144961713Sgirish 358244961713Sgirish /* 358344961713Sgirish * Buffer sizes suggested by NIU architect. 358444961713Sgirish * 256, 512 and 2K. 358544961713Sgirish */ 358644961713Sgirish 358744961713Sgirish rbrp->pkt_buf_size0 = RBR_BUFSZ0_256B; 358844961713Sgirish rbrp->pkt_buf_size0_bytes = RBR_BUFSZ0_256_BYTES; 358944961713Sgirish rbrp->npi_pkt_buf_size0 = SIZE_256B; 359044961713Sgirish 359144961713Sgirish rbrp->pkt_buf_size1 = RBR_BUFSZ1_1K; 359244961713Sgirish rbrp->pkt_buf_size1_bytes = RBR_BUFSZ1_1K_BYTES; 359344961713Sgirish rbrp->npi_pkt_buf_size1 = SIZE_1KB; 359444961713Sgirish 359544961713Sgirish rbrp->block_size = nxgep->rx_default_block_size; 359644961713Sgirish 359714ea4bb7Ssd if (!nxge_jumbo_enable && !nxgep->param_arr[param_accept_jumbo].value) { 359844961713Sgirish rbrp->pkt_buf_size2 = RBR_BUFSZ2_2K; 359944961713Sgirish rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_2K_BYTES; 360044961713Sgirish rbrp->npi_pkt_buf_size2 = SIZE_2KB; 360144961713Sgirish } else { 360244961713Sgirish if (rbrp->block_size >= 0x2000) { 360344961713Sgirish rbrp->pkt_buf_size2 = RBR_BUFSZ2_8K; 360444961713Sgirish rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_8K_BYTES; 360544961713Sgirish rbrp->npi_pkt_buf_size2 = SIZE_8KB; 360644961713Sgirish } else { 360744961713Sgirish rbrp->pkt_buf_size2 = RBR_BUFSZ2_4K; 360844961713Sgirish rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_4K_BYTES; 360944961713Sgirish rbrp->npi_pkt_buf_size2 = SIZE_4KB; 361044961713Sgirish } 361144961713Sgirish } 361244961713Sgirish 361344961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 361452ccf843Smisaki "==> nxge_map_rxdma_channel_buf_ring: channel %d " 361552ccf843Smisaki "actual rbr max %d rbb_max %d nmsgs %d " 361652ccf843Smisaki "rbrp->block_size %d default_block_size %d " 361752ccf843Smisaki "(config nxge_rbr_size %d nxge_rbr_spare_size %d)", 361852ccf843Smisaki channel, rbrp->rbr_max_size, rbrp->rbb_max, nmsgs, 361952ccf843Smisaki rbrp->block_size, nxgep->rx_default_block_size, 362052ccf843Smisaki nxge_rbr_size, nxge_rbr_spare_size)); 362144961713Sgirish 362244961713Sgirish /* Map in buffers from the buffer pool. */ 362344961713Sgirish index = 0; 362444961713Sgirish for (i = 0; i < rbrp->num_blocks; i++, dma_bufp++) { 362544961713Sgirish bsize = dma_bufp->block_size; 362644961713Sgirish nblocks = dma_bufp->nblocks; 3627adfcba55Sjoycey #if defined(__i386) 3628adfcba55Sjoycey ring_info->buffer[i].dvma_addr = (uint32_t)dma_bufp->ioaddr_pp; 3629adfcba55Sjoycey #else 363044961713Sgirish ring_info->buffer[i].dvma_addr = (uint64_t)dma_bufp->ioaddr_pp; 3631adfcba55Sjoycey #endif 363244961713Sgirish ring_info->buffer[i].buf_index = i; 363344961713Sgirish ring_info->buffer[i].buf_size = dma_bufp->alength; 363444961713Sgirish ring_info->buffer[i].start_index = index; 3635adfcba55Sjoycey #if defined(__i386) 3636adfcba55Sjoycey ring_info->buffer[i].kaddr = (uint32_t)dma_bufp->kaddrp; 3637adfcba55Sjoycey #else 363844961713Sgirish ring_info->buffer[i].kaddr = (uint64_t)dma_bufp->kaddrp; 3639adfcba55Sjoycey #endif 364044961713Sgirish 364144961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 364252ccf843Smisaki " nxge_map_rxdma_channel_buf_ring: map channel %d " 364352ccf843Smisaki "chunk %d" 364452ccf843Smisaki " nblocks %d chunk_size %x block_size 0x%x " 364552ccf843Smisaki "dma_bufp $%p", channel, i, 364652ccf843Smisaki dma_bufp->nblocks, ring_info->buffer[i].buf_size, bsize, 364752ccf843Smisaki dma_bufp)); 364844961713Sgirish 364944961713Sgirish for (j = 0; j < nblocks; j++) { 365044961713Sgirish if ((rx_msg_p = nxge_allocb(bsize, BPRI_LO, 365152ccf843Smisaki dma_bufp)) == NULL) { 365256d930aeSspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 365352ccf843Smisaki "allocb failed (index %d i %d j %d)", 365452ccf843Smisaki index, i, j)); 365556d930aeSspeer goto nxge_map_rxdma_channel_buf_ring_fail1; 365644961713Sgirish } 365744961713Sgirish rx_msg_ring[index] = rx_msg_p; 365844961713Sgirish rx_msg_p->block_index = index; 365944961713Sgirish rx_msg_p->shifted_addr = (uint32_t) 366052ccf843Smisaki ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress >> 366152ccf843Smisaki RBR_BKADDR_SHIFT)); 366244961713Sgirish 366344961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 366452ccf843Smisaki "index %d j %d rx_msg_p $%p mblk %p", 366552ccf843Smisaki index, j, rx_msg_p, rx_msg_p->rx_mblk_p)); 366644961713Sgirish 366744961713Sgirish mblk_p = rx_msg_p->rx_mblk_p; 366844961713Sgirish mblk_p->b_wptr = mblk_p->b_rptr + bsize; 3669007969e0Stm 3670007969e0Stm rbrp->rbr_ref_cnt++; 367144961713Sgirish index++; 367244961713Sgirish rx_msg_p->buf_dma.dma_channel = channel; 367344961713Sgirish } 3674678453a8Sspeer 3675678453a8Sspeer rbrp->rbr_alloc_type = DDI_MEM_ALLOC; 3676678453a8Sspeer if (dma_bufp->contig_alloc_type) { 3677678453a8Sspeer rbrp->rbr_alloc_type = CONTIG_MEM_ALLOC; 3678678453a8Sspeer } 3679678453a8Sspeer 3680678453a8Sspeer if (dma_bufp->kmem_alloc_type) { 3681678453a8Sspeer rbrp->rbr_alloc_type = KMEM_ALLOC; 3682678453a8Sspeer } 3683678453a8Sspeer 3684678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3685678453a8Sspeer " nxge_map_rxdma_channel_buf_ring: map channel %d " 3686678453a8Sspeer "chunk %d" 3687678453a8Sspeer " nblocks %d chunk_size %x block_size 0x%x " 3688678453a8Sspeer "dma_bufp $%p", 3689678453a8Sspeer channel, i, 3690678453a8Sspeer dma_bufp->nblocks, ring_info->buffer[i].buf_size, bsize, 3691678453a8Sspeer dma_bufp)); 369244961713Sgirish } 369344961713Sgirish if (i < rbrp->num_blocks) { 369444961713Sgirish goto nxge_map_rxdma_channel_buf_ring_fail1; 369544961713Sgirish } 369644961713Sgirish 369744961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 369852ccf843Smisaki "nxge_map_rxdma_channel_buf_ring: done buf init " 369952ccf843Smisaki "channel %d msg block entries %d", 370052ccf843Smisaki channel, index)); 370144961713Sgirish ring_info->block_size_mask = bsize - 1; 370244961713Sgirish rbrp->rx_msg_ring = rx_msg_ring; 370344961713Sgirish rbrp->dma_bufp = dma_buf_p; 370444961713Sgirish rbrp->ring_info = ring_info; 370544961713Sgirish 370644961713Sgirish status = nxge_rxbuf_index_info_init(nxgep, rbrp); 370744961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 370852ccf843Smisaki " nxge_map_rxdma_channel_buf_ring: " 370952ccf843Smisaki "channel %d done buf info init", channel)); 371044961713Sgirish 3711007969e0Stm /* 3712007969e0Stm * Finally, permit nxge_freeb() to call nxge_post_page(). 3713007969e0Stm */ 3714007969e0Stm rbrp->rbr_state = RBR_POSTING; 3715007969e0Stm 371644961713Sgirish *rbr_p = rbrp; 371744961713Sgirish goto nxge_map_rxdma_channel_buf_ring_exit; 371844961713Sgirish 371944961713Sgirish nxge_map_rxdma_channel_buf_ring_fail1: 372044961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 372152ccf843Smisaki " nxge_map_rxdma_channel_buf_ring: failed channel (0x%x)", 372252ccf843Smisaki channel, status)); 372344961713Sgirish 372444961713Sgirish index--; 372544961713Sgirish for (; index >= 0; index--) { 372644961713Sgirish rx_msg_p = rx_msg_ring[index]; 372744961713Sgirish if (rx_msg_p != NULL) { 372814ea4bb7Ssd freeb(rx_msg_p->rx_mblk_p); 372944961713Sgirish rx_msg_ring[index] = NULL; 373044961713Sgirish } 373144961713Sgirish } 373244961713Sgirish nxge_map_rxdma_channel_buf_ring_fail: 373344961713Sgirish MUTEX_DESTROY(&rbrp->post_lock); 373444961713Sgirish MUTEX_DESTROY(&rbrp->lock); 373544961713Sgirish KMEM_FREE(ring_info, sizeof (rxring_info_t)); 373644961713Sgirish KMEM_FREE(rx_msg_ring, size); 373744961713Sgirish KMEM_FREE(rbrp, sizeof (rx_rbr_ring_t)); 373844961713Sgirish 373956d930aeSspeer status = NXGE_ERROR; 374056d930aeSspeer 374144961713Sgirish nxge_map_rxdma_channel_buf_ring_exit: 374244961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 374352ccf843Smisaki "<== nxge_map_rxdma_channel_buf_ring status 0x%08x", status)); 374444961713Sgirish 374544961713Sgirish return (status); 374644961713Sgirish } 374744961713Sgirish 374844961713Sgirish /*ARGSUSED*/ 374944961713Sgirish static void 375044961713Sgirish nxge_unmap_rxdma_channel_buf_ring(p_nxge_t nxgep, 375144961713Sgirish p_rx_rbr_ring_t rbr_p) 375244961713Sgirish { 375344961713Sgirish p_rx_msg_t *rx_msg_ring; 375444961713Sgirish p_rx_msg_t rx_msg_p; 375544961713Sgirish rxring_info_t *ring_info; 375644961713Sgirish int i; 375744961713Sgirish uint32_t size; 375844961713Sgirish #ifdef NXGE_DEBUG 375944961713Sgirish int num_chunks; 376044961713Sgirish #endif 376144961713Sgirish 376244961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 376352ccf843Smisaki "==> nxge_unmap_rxdma_channel_buf_ring")); 376444961713Sgirish if (rbr_p == NULL) { 376544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 376652ccf843Smisaki "<== nxge_unmap_rxdma_channel_buf_ring: NULL rbrp")); 376744961713Sgirish return; 376844961713Sgirish } 376944961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 377052ccf843Smisaki "==> nxge_unmap_rxdma_channel_buf_ring: channel %d", 377152ccf843Smisaki rbr_p->rdc)); 377244961713Sgirish 377344961713Sgirish rx_msg_ring = rbr_p->rx_msg_ring; 377444961713Sgirish ring_info = rbr_p->ring_info; 377544961713Sgirish 377644961713Sgirish if (rx_msg_ring == NULL || ring_info == NULL) { 377752ccf843Smisaki NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 377852ccf843Smisaki "<== nxge_unmap_rxdma_channel_buf_ring: " 377952ccf843Smisaki "rx_msg_ring $%p ring_info $%p", 378052ccf843Smisaki rx_msg_p, ring_info)); 378144961713Sgirish return; 378244961713Sgirish } 378344961713Sgirish 378444961713Sgirish #ifdef NXGE_DEBUG 378544961713Sgirish num_chunks = rbr_p->num_blocks; 378644961713Sgirish #endif 378744961713Sgirish size = rbr_p->tnblocks * sizeof (p_rx_msg_t); 378844961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 378952ccf843Smisaki " nxge_unmap_rxdma_channel_buf_ring: channel %d chunks %d " 379052ccf843Smisaki "tnblocks %d (max %d) size ptrs %d ", 379152ccf843Smisaki rbr_p->rdc, num_chunks, 379252ccf843Smisaki rbr_p->tnblocks, rbr_p->rbr_max_size, size)); 379344961713Sgirish 379444961713Sgirish for (i = 0; i < rbr_p->tnblocks; i++) { 379544961713Sgirish rx_msg_p = rx_msg_ring[i]; 379644961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 379752ccf843Smisaki " nxge_unmap_rxdma_channel_buf_ring: " 379852ccf843Smisaki "rx_msg_p $%p", 379952ccf843Smisaki rx_msg_p)); 380044961713Sgirish if (rx_msg_p != NULL) { 380114ea4bb7Ssd freeb(rx_msg_p->rx_mblk_p); 380244961713Sgirish rx_msg_ring[i] = NULL; 380344961713Sgirish } 380444961713Sgirish } 380544961713Sgirish 3806007969e0Stm /* 3807007969e0Stm * We no longer may use the mutex <post_lock>. By setting 3808007969e0Stm * <rbr_state> to anything but POSTING, we prevent 3809007969e0Stm * nxge_post_page() from accessing a dead mutex. 3810007969e0Stm */ 3811007969e0Stm rbr_p->rbr_state = RBR_UNMAPPING; 381244961713Sgirish MUTEX_DESTROY(&rbr_p->post_lock); 3813007969e0Stm 381444961713Sgirish MUTEX_DESTROY(&rbr_p->lock); 3815007969e0Stm 3816007969e0Stm if (rbr_p->rbr_ref_cnt == 0) { 3817678453a8Sspeer /* 3818678453a8Sspeer * This is the normal state of affairs. 3819678453a8Sspeer * Need to free the following buffers: 3820678453a8Sspeer * - data buffers 3821678453a8Sspeer * - rx_msg ring 3822678453a8Sspeer * - ring_info 3823678453a8Sspeer * - rbr ring 3824678453a8Sspeer */ 3825678453a8Sspeer NXGE_DEBUG_MSG((nxgep, RX_CTL, 3826678453a8Sspeer "unmap_rxdma_buf_ring: No outstanding - freeing ")); 3827678453a8Sspeer nxge_rxdma_databuf_free(rbr_p); 3828678453a8Sspeer KMEM_FREE(ring_info, sizeof (rxring_info_t)); 3829678453a8Sspeer KMEM_FREE(rx_msg_ring, size); 3830007969e0Stm KMEM_FREE(rbr_p, sizeof (*rbr_p)); 3831007969e0Stm } else { 3832007969e0Stm /* 3833007969e0Stm * Some of our buffers are still being used. 3834007969e0Stm * Therefore, tell nxge_freeb() this ring is 3835007969e0Stm * unmapped, so it may free <rbr_p> for us. 3836007969e0Stm */ 3837007969e0Stm rbr_p->rbr_state = RBR_UNMAPPED; 3838007969e0Stm NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3839007969e0Stm "unmap_rxdma_buf_ring: %d %s outstanding.", 3840007969e0Stm rbr_p->rbr_ref_cnt, 3841007969e0Stm rbr_p->rbr_ref_cnt == 1 ? "msg" : "msgs")); 3842007969e0Stm } 384344961713Sgirish 384444961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 384552ccf843Smisaki "<== nxge_unmap_rxdma_channel_buf_ring")); 384644961713Sgirish } 384744961713Sgirish 3848678453a8Sspeer /* 3849678453a8Sspeer * nxge_rxdma_hw_start_common 3850678453a8Sspeer * 3851678453a8Sspeer * Arguments: 3852678453a8Sspeer * nxgep 3853678453a8Sspeer * 3854678453a8Sspeer * Notes: 3855678453a8Sspeer * 3856678453a8Sspeer * NPI/NXGE function calls: 3857678453a8Sspeer * nxge_init_fzc_rx_common(); 3858678453a8Sspeer * nxge_init_fzc_rxdma_port(); 3859678453a8Sspeer * 3860678453a8Sspeer * Registers accessed: 3861678453a8Sspeer * 3862678453a8Sspeer * Context: 3863678453a8Sspeer * Service domain 3864678453a8Sspeer */ 386544961713Sgirish static nxge_status_t 386644961713Sgirish nxge_rxdma_hw_start_common(p_nxge_t nxgep) 386744961713Sgirish { 386844961713Sgirish nxge_status_t status = NXGE_OK; 386944961713Sgirish 387044961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start_common")); 387144961713Sgirish 387244961713Sgirish /* 387344961713Sgirish * Load the sharable parameters by writing to the 387444961713Sgirish * function zero control registers. These FZC registers 387544961713Sgirish * should be initialized only once for the entire chip. 387644961713Sgirish */ 387744961713Sgirish (void) nxge_init_fzc_rx_common(nxgep); 387844961713Sgirish 387944961713Sgirish /* 388044961713Sgirish * Initialize the RXDMA port specific FZC control configurations. 388144961713Sgirish * These FZC registers are pertaining to each port. 388244961713Sgirish */ 388344961713Sgirish (void) nxge_init_fzc_rxdma_port(nxgep); 388444961713Sgirish 388544961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start_common")); 388644961713Sgirish 388744961713Sgirish return (status); 388844961713Sgirish } 388944961713Sgirish 389044961713Sgirish static nxge_status_t 3891678453a8Sspeer nxge_rxdma_hw_start(p_nxge_t nxgep, int channel) 389244961713Sgirish { 389344961713Sgirish int i, ndmas; 389444961713Sgirish p_rx_rbr_rings_t rx_rbr_rings; 389544961713Sgirish p_rx_rbr_ring_t *rbr_rings; 389644961713Sgirish p_rx_rcr_rings_t rx_rcr_rings; 389744961713Sgirish p_rx_rcr_ring_t *rcr_rings; 389844961713Sgirish p_rx_mbox_areas_t rx_mbox_areas_p; 389944961713Sgirish p_rx_mbox_t *rx_mbox_p; 390044961713Sgirish nxge_status_t status = NXGE_OK; 390144961713Sgirish 390244961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start")); 390344961713Sgirish 390444961713Sgirish rx_rbr_rings = nxgep->rx_rbr_rings; 390544961713Sgirish rx_rcr_rings = nxgep->rx_rcr_rings; 390644961713Sgirish if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 390744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 390852ccf843Smisaki "<== nxge_rxdma_hw_start: NULL ring pointers")); 390944961713Sgirish return (NXGE_ERROR); 391044961713Sgirish } 391144961713Sgirish ndmas = rx_rbr_rings->ndmas; 391244961713Sgirish if (ndmas == 0) { 391344961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 391452ccf843Smisaki "<== nxge_rxdma_hw_start: no dma channel allocated")); 391544961713Sgirish return (NXGE_ERROR); 391644961713Sgirish } 391744961713Sgirish 391844961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 391952ccf843Smisaki "==> nxge_rxdma_hw_start (ndmas %d)", ndmas)); 392044961713Sgirish 392144961713Sgirish rbr_rings = rx_rbr_rings->rbr_rings; 392244961713Sgirish rcr_rings = rx_rcr_rings->rcr_rings; 392344961713Sgirish rx_mbox_areas_p = nxgep->rx_mbox_areas_p; 392444961713Sgirish if (rx_mbox_areas_p) { 392544961713Sgirish rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 392644961713Sgirish } 392744961713Sgirish 3928678453a8Sspeer i = channel; 3929678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 393052ccf843Smisaki "==> nxge_rxdma_hw_start (ndmas %d) channel %d", 393152ccf843Smisaki ndmas, channel)); 3932678453a8Sspeer status = nxge_rxdma_start_channel(nxgep, channel, 3933678453a8Sspeer (p_rx_rbr_ring_t)rbr_rings[i], 3934678453a8Sspeer (p_rx_rcr_ring_t)rcr_rings[i], 3935678453a8Sspeer (p_rx_mbox_t)rx_mbox_p[i]); 3936678453a8Sspeer if (status != NXGE_OK) { 3937678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3938678453a8Sspeer "==> nxge_rxdma_hw_start: disable " 3939678453a8Sspeer "(status 0x%x channel %d)", status, channel)); 3940678453a8Sspeer return (status); 394144961713Sgirish } 394244961713Sgirish 394344961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start: " 394452ccf843Smisaki "rx_rbr_rings 0x%016llx rings 0x%016llx", 394552ccf843Smisaki rx_rbr_rings, rx_rcr_rings)); 394644961713Sgirish 394744961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 394852ccf843Smisaki "==> nxge_rxdma_hw_start: (status 0x%x)", status)); 394944961713Sgirish 395044961713Sgirish return (status); 395144961713Sgirish } 395244961713Sgirish 395344961713Sgirish static void 3954678453a8Sspeer nxge_rxdma_hw_stop(p_nxge_t nxgep, int channel) 395544961713Sgirish { 395644961713Sgirish p_rx_rbr_rings_t rx_rbr_rings; 395744961713Sgirish p_rx_rcr_rings_t rx_rcr_rings; 395844961713Sgirish 395944961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop")); 396044961713Sgirish 396144961713Sgirish rx_rbr_rings = nxgep->rx_rbr_rings; 396244961713Sgirish rx_rcr_rings = nxgep->rx_rcr_rings; 396344961713Sgirish if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 396444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 396552ccf843Smisaki "<== nxge_rxdma_hw_stop: NULL ring pointers")); 396644961713Sgirish return; 396744961713Sgirish } 396844961713Sgirish 396944961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 397052ccf843Smisaki "==> nxge_rxdma_hw_stop(channel %d)", 397152ccf843Smisaki channel)); 3972678453a8Sspeer (void) nxge_rxdma_stop_channel(nxgep, channel); 397344961713Sgirish 397444961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop: " 397552ccf843Smisaki "rx_rbr_rings 0x%016llx rings 0x%016llx", 397652ccf843Smisaki rx_rbr_rings, rx_rcr_rings)); 397744961713Sgirish 397844961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_rxdma_hw_stop")); 397944961713Sgirish } 398044961713Sgirish 398144961713Sgirish 398244961713Sgirish static nxge_status_t 398344961713Sgirish nxge_rxdma_start_channel(p_nxge_t nxgep, uint16_t channel, 398444961713Sgirish p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p) 398544961713Sgirish 398644961713Sgirish { 398744961713Sgirish npi_handle_t handle; 398844961713Sgirish npi_status_t rs = NPI_SUCCESS; 398944961713Sgirish rx_dma_ctl_stat_t cs; 399044961713Sgirish rx_dma_ent_msk_t ent_mask; 399144961713Sgirish nxge_status_t status = NXGE_OK; 399244961713Sgirish 399344961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel")); 399444961713Sgirish 399544961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 399644961713Sgirish 399744961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "nxge_rxdma_start_channel: " 399844961713Sgirish "npi handle addr $%p acc $%p", 399944961713Sgirish nxgep->npi_handle.regp, nxgep->npi_handle.regh)); 400044961713Sgirish 4001678453a8Sspeer /* Reset RXDMA channel, but not if you're a guest. */ 4002678453a8Sspeer if (!isLDOMguest(nxgep)) { 4003678453a8Sspeer rs = npi_rxdma_cfg_rdc_reset(handle, channel); 4004678453a8Sspeer if (rs != NPI_SUCCESS) { 4005678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4006678453a8Sspeer "==> nxge_init_fzc_rdc: " 4007678453a8Sspeer "npi_rxdma_cfg_rdc_reset(%d) returned 0x%08x", 4008678453a8Sspeer channel, rs)); 4009678453a8Sspeer return (NXGE_ERROR | rs); 4010678453a8Sspeer } 4011678453a8Sspeer 4012678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4013678453a8Sspeer "==> nxge_rxdma_start_channel: reset done: channel %d", 4014678453a8Sspeer channel)); 401544961713Sgirish } 401644961713Sgirish 4017678453a8Sspeer #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 4018678453a8Sspeer if (isLDOMguest(nxgep)) 4019678453a8Sspeer (void) nxge_rdc_lp_conf(nxgep, channel); 4020678453a8Sspeer #endif 402144961713Sgirish 402244961713Sgirish /* 402344961713Sgirish * Initialize the RXDMA channel specific FZC control 402444961713Sgirish * configurations. These FZC registers are pertaining 402544961713Sgirish * to each RX channel (logical pages). 402644961713Sgirish */ 4027678453a8Sspeer if (!isLDOMguest(nxgep)) { 4028678453a8Sspeer status = nxge_init_fzc_rxdma_channel(nxgep, channel); 4029678453a8Sspeer if (status != NXGE_OK) { 4030678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4031678453a8Sspeer "==> nxge_rxdma_start_channel: " 4032678453a8Sspeer "init fzc rxdma failed (0x%08x channel %d)", 4033678453a8Sspeer status, channel)); 4034678453a8Sspeer return (status); 4035678453a8Sspeer } 403644961713Sgirish 4037678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4038678453a8Sspeer "==> nxge_rxdma_start_channel: fzc done")); 4039678453a8Sspeer } 404044961713Sgirish 404144961713Sgirish /* Set up the interrupt event masks. */ 404244961713Sgirish ent_mask.value = 0; 404344961713Sgirish ent_mask.value |= RX_DMA_ENT_MSK_RBREMPTY_MASK; 404444961713Sgirish rs = npi_rxdma_event_mask(handle, OP_SET, channel, 4045678453a8Sspeer &ent_mask); 404644961713Sgirish if (rs != NPI_SUCCESS) { 404744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 404844961713Sgirish "==> nxge_rxdma_start_channel: " 4049678453a8Sspeer "init rxdma event masks failed " 4050678453a8Sspeer "(0x%08x channel %d)", 405144961713Sgirish status, channel)); 405244961713Sgirish return (NXGE_ERROR | rs); 405344961713Sgirish } 405444961713Sgirish 4055678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4056678453a8Sspeer "==> nxge_rxdma_start_channel: " 405744961713Sgirish "event done: channel %d (mask 0x%016llx)", 405844961713Sgirish channel, ent_mask.value)); 405944961713Sgirish 406044961713Sgirish /* Initialize the receive DMA control and status register */ 406144961713Sgirish cs.value = 0; 406244961713Sgirish cs.bits.hdw.mex = 1; 406344961713Sgirish cs.bits.hdw.rcrthres = 1; 406444961713Sgirish cs.bits.hdw.rcrto = 1; 406544961713Sgirish cs.bits.hdw.rbr_empty = 1; 406644961713Sgirish status = nxge_init_rxdma_channel_cntl_stat(nxgep, channel, &cs); 406744961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 406844961713Sgirish "channel %d rx_dma_cntl_stat 0x%0016llx", channel, cs.value)); 406944961713Sgirish if (status != NXGE_OK) { 407044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 407144961713Sgirish "==> nxge_rxdma_start_channel: " 407244961713Sgirish "init rxdma control register failed (0x%08x channel %d", 407344961713Sgirish status, channel)); 407444961713Sgirish return (status); 407544961713Sgirish } 407644961713Sgirish 407744961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 407844961713Sgirish "control done - channel %d cs 0x%016llx", channel, cs.value)); 407944961713Sgirish 408044961713Sgirish /* 408144961713Sgirish * Load RXDMA descriptors, buffers, mailbox, 408244961713Sgirish * initialise the receive DMA channels and 408344961713Sgirish * enable each DMA channel. 408444961713Sgirish */ 408544961713Sgirish status = nxge_enable_rxdma_channel(nxgep, 4086678453a8Sspeer channel, rbr_p, rcr_p, mbox_p); 408744961713Sgirish 408844961713Sgirish if (status != NXGE_OK) { 408944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4090678453a8Sspeer " nxge_rxdma_start_channel: " 4091678453a8Sspeer " enable rxdma failed (0x%08x channel %d)", 4092678453a8Sspeer status, channel)); 409344961713Sgirish return (status); 409444961713Sgirish } 409544961713Sgirish 4096678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4097678453a8Sspeer "==> nxge_rxdma_start_channel: enabled channel %d")); 4098678453a8Sspeer 4099678453a8Sspeer if (isLDOMguest(nxgep)) { 4100678453a8Sspeer /* Add interrupt handler for this channel. */ 4101678453a8Sspeer if (nxge_hio_intr_add(nxgep, VP_BOUND_RX, channel) 4102678453a8Sspeer != NXGE_OK) { 4103678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4104678453a8Sspeer " nxge_rxdma_start_channel: " 4105678453a8Sspeer " nxge_hio_intr_add failed (0x%08x channel %d)", 4106678453a8Sspeer status, channel)); 4107678453a8Sspeer } 4108678453a8Sspeer } 4109678453a8Sspeer 411044961713Sgirish ent_mask.value = 0; 411144961713Sgirish ent_mask.value |= (RX_DMA_ENT_MSK_WRED_DROP_MASK | 411244961713Sgirish RX_DMA_ENT_MSK_PTDROP_PKT_MASK); 411344961713Sgirish rs = npi_rxdma_event_mask(handle, OP_SET, channel, 411444961713Sgirish &ent_mask); 411544961713Sgirish if (rs != NPI_SUCCESS) { 411644961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 411744961713Sgirish "==> nxge_rxdma_start_channel: " 411844961713Sgirish "init rxdma event masks failed (0x%08x channel %d)", 411944961713Sgirish status, channel)); 412044961713Sgirish return (NXGE_ERROR | rs); 412144961713Sgirish } 412244961713Sgirish 412344961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 412444961713Sgirish "control done - channel %d cs 0x%016llx", channel, cs.value)); 412544961713Sgirish 412644961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_rxdma_start_channel")); 412744961713Sgirish 412844961713Sgirish return (NXGE_OK); 412944961713Sgirish } 413044961713Sgirish 413144961713Sgirish static nxge_status_t 413244961713Sgirish nxge_rxdma_stop_channel(p_nxge_t nxgep, uint16_t channel) 413344961713Sgirish { 413444961713Sgirish npi_handle_t handle; 413544961713Sgirish npi_status_t rs = NPI_SUCCESS; 413644961713Sgirish rx_dma_ctl_stat_t cs; 413744961713Sgirish rx_dma_ent_msk_t ent_mask; 413844961713Sgirish nxge_status_t status = NXGE_OK; 413944961713Sgirish 414044961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_channel")); 414144961713Sgirish 414244961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 414344961713Sgirish 414444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "nxge_rxdma_stop_channel: " 414552ccf843Smisaki "npi handle addr $%p acc $%p", 414652ccf843Smisaki nxgep->npi_handle.regp, nxgep->npi_handle.regh)); 414744961713Sgirish 4148*330cd344SMichael Speer if (!isLDOMguest(nxgep)) { 4149*330cd344SMichael Speer /* 4150*330cd344SMichael Speer * Stop RxMAC = A.9.2.6 4151*330cd344SMichael Speer */ 4152*330cd344SMichael Speer if (nxge_rx_mac_disable(nxgep) != NXGE_OK) { 4153*330cd344SMichael Speer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4154*330cd344SMichael Speer "nxge_rxdma_stop_channel: " 4155*330cd344SMichael Speer "Failed to disable RxMAC")); 4156*330cd344SMichael Speer } 4157*330cd344SMichael Speer 4158*330cd344SMichael Speer /* 4159*330cd344SMichael Speer * Drain IPP Port = A.9.3.6 4160*330cd344SMichael Speer */ 4161*330cd344SMichael Speer (void) nxge_ipp_drain(nxgep); 4162*330cd344SMichael Speer } 4163*330cd344SMichael Speer 416444961713Sgirish /* Reset RXDMA channel */ 416544961713Sgirish rs = npi_rxdma_cfg_rdc_reset(handle, channel); 416644961713Sgirish if (rs != NPI_SUCCESS) { 416744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 416852ccf843Smisaki " nxge_rxdma_stop_channel: " 416952ccf843Smisaki " reset rxdma failed (0x%08x channel %d)", 417052ccf843Smisaki rs, channel)); 417144961713Sgirish return (NXGE_ERROR | rs); 417244961713Sgirish } 417344961713Sgirish 417444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 417552ccf843Smisaki "==> nxge_rxdma_stop_channel: reset done")); 417644961713Sgirish 417744961713Sgirish /* Set up the interrupt event masks. */ 417844961713Sgirish ent_mask.value = RX_DMA_ENT_MSK_ALL; 417944961713Sgirish rs = npi_rxdma_event_mask(handle, OP_SET, channel, 418052ccf843Smisaki &ent_mask); 418144961713Sgirish if (rs != NPI_SUCCESS) { 418244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 418352ccf843Smisaki "==> nxge_rxdma_stop_channel: " 418452ccf843Smisaki "set rxdma event masks failed (0x%08x channel %d)", 418552ccf843Smisaki rs, channel)); 418644961713Sgirish return (NXGE_ERROR | rs); 418744961713Sgirish } 418844961713Sgirish 418944961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 419052ccf843Smisaki "==> nxge_rxdma_stop_channel: event done")); 419144961713Sgirish 4192*330cd344SMichael Speer /* 4193*330cd344SMichael Speer * Initialize the receive DMA control and status register 4194*330cd344SMichael Speer */ 419544961713Sgirish cs.value = 0; 4196*330cd344SMichael Speer status = nxge_init_rxdma_channel_cntl_stat(nxgep, channel, &cs); 419744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_channel: control " 419852ccf843Smisaki " to default (all 0s) 0x%08x", cs.value)); 419944961713Sgirish if (status != NXGE_OK) { 420044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 420152ccf843Smisaki " nxge_rxdma_stop_channel: init rxdma" 420252ccf843Smisaki " control register failed (0x%08x channel %d", 420352ccf843Smisaki status, channel)); 420444961713Sgirish return (status); 420544961713Sgirish } 420644961713Sgirish 420744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 420852ccf843Smisaki "==> nxge_rxdma_stop_channel: control done")); 420944961713Sgirish 4210*330cd344SMichael Speer /* 4211*330cd344SMichael Speer * Make sure channel is disabled. 4212*330cd344SMichael Speer */ 421344961713Sgirish status = nxge_disable_rxdma_channel(nxgep, channel); 421444961713Sgirish if (status != NXGE_OK) { 421544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 421652ccf843Smisaki " nxge_rxdma_stop_channel: " 421752ccf843Smisaki " init enable rxdma failed (0x%08x channel %d)", 421852ccf843Smisaki status, channel)); 421944961713Sgirish return (status); 422044961713Sgirish } 422144961713Sgirish 4222*330cd344SMichael Speer if (!isLDOMguest(nxgep)) { 4223*330cd344SMichael Speer /* 4224*330cd344SMichael Speer * Enable RxMAC = A.9.2.10 4225*330cd344SMichael Speer */ 4226*330cd344SMichael Speer if (nxge_rx_mac_enable(nxgep) != NXGE_OK) { 4227*330cd344SMichael Speer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4228*330cd344SMichael Speer "nxge_rxdma_stop_channel: Rx MAC still disabled")); 4229*330cd344SMichael Speer } 4230*330cd344SMichael Speer } 4231*330cd344SMichael Speer 423244961713Sgirish NXGE_DEBUG_MSG((nxgep, 423352ccf843Smisaki RX_CTL, "==> nxge_rxdma_stop_channel: disable done")); 423444961713Sgirish 423544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_stop_channel")); 423644961713Sgirish 423744961713Sgirish return (NXGE_OK); 423844961713Sgirish } 423944961713Sgirish 424044961713Sgirish nxge_status_t 424144961713Sgirish nxge_rxdma_handle_sys_errors(p_nxge_t nxgep) 424244961713Sgirish { 424344961713Sgirish npi_handle_t handle; 424444961713Sgirish p_nxge_rdc_sys_stats_t statsp; 424544961713Sgirish rx_ctl_dat_fifo_stat_t stat; 424644961713Sgirish uint32_t zcp_err_status; 424744961713Sgirish uint32_t ipp_err_status; 424844961713Sgirish nxge_status_t status = NXGE_OK; 424944961713Sgirish npi_status_t rs = NPI_SUCCESS; 425044961713Sgirish boolean_t my_err = B_FALSE; 425144961713Sgirish 425244961713Sgirish handle = nxgep->npi_handle; 425344961713Sgirish statsp = (p_nxge_rdc_sys_stats_t)&nxgep->statsp->rdc_sys_stats; 425444961713Sgirish 425544961713Sgirish rs = npi_rxdma_rxctl_fifo_error_intr_get(handle, &stat); 425644961713Sgirish 425744961713Sgirish if (rs != NPI_SUCCESS) 425844961713Sgirish return (NXGE_ERROR | rs); 425944961713Sgirish 426044961713Sgirish if (stat.bits.ldw.id_mismatch) { 426144961713Sgirish statsp->id_mismatch++; 426244961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, nxgep->mac.portnum, NULL, 426352ccf843Smisaki NXGE_FM_EREPORT_RDMC_ID_MISMATCH); 426444961713Sgirish /* Global fatal error encountered */ 426544961713Sgirish } 426644961713Sgirish 426744961713Sgirish if ((stat.bits.ldw.zcp_eop_err) || (stat.bits.ldw.ipp_eop_err)) { 426844961713Sgirish switch (nxgep->mac.portnum) { 426944961713Sgirish case 0: 427044961713Sgirish if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT0) || 427152ccf843Smisaki (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT0)) { 427244961713Sgirish my_err = B_TRUE; 427344961713Sgirish zcp_err_status = stat.bits.ldw.zcp_eop_err; 427444961713Sgirish ipp_err_status = stat.bits.ldw.ipp_eop_err; 427544961713Sgirish } 427644961713Sgirish break; 427744961713Sgirish case 1: 427844961713Sgirish if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT1) || 427952ccf843Smisaki (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT1)) { 428044961713Sgirish my_err = B_TRUE; 428144961713Sgirish zcp_err_status = stat.bits.ldw.zcp_eop_err; 428244961713Sgirish ipp_err_status = stat.bits.ldw.ipp_eop_err; 428344961713Sgirish } 428444961713Sgirish break; 428544961713Sgirish case 2: 428644961713Sgirish if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT2) || 428752ccf843Smisaki (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT2)) { 428844961713Sgirish my_err = B_TRUE; 428944961713Sgirish zcp_err_status = stat.bits.ldw.zcp_eop_err; 429044961713Sgirish ipp_err_status = stat.bits.ldw.ipp_eop_err; 429144961713Sgirish } 429244961713Sgirish break; 429344961713Sgirish case 3: 429444961713Sgirish if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT3) || 429552ccf843Smisaki (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT3)) { 429644961713Sgirish my_err = B_TRUE; 429744961713Sgirish zcp_err_status = stat.bits.ldw.zcp_eop_err; 429844961713Sgirish ipp_err_status = stat.bits.ldw.ipp_eop_err; 429944961713Sgirish } 430044961713Sgirish break; 430144961713Sgirish default: 430244961713Sgirish return (NXGE_ERROR); 430344961713Sgirish } 430444961713Sgirish } 430544961713Sgirish 430644961713Sgirish if (my_err) { 430744961713Sgirish status = nxge_rxdma_handle_port_errors(nxgep, ipp_err_status, 430852ccf843Smisaki zcp_err_status); 430944961713Sgirish if (status != NXGE_OK) 431044961713Sgirish return (status); 431144961713Sgirish } 431244961713Sgirish 431344961713Sgirish return (NXGE_OK); 431444961713Sgirish } 431544961713Sgirish 431644961713Sgirish static nxge_status_t 431744961713Sgirish nxge_rxdma_handle_port_errors(p_nxge_t nxgep, uint32_t ipp_status, 431844961713Sgirish uint32_t zcp_status) 431944961713Sgirish { 432044961713Sgirish boolean_t rxport_fatal = B_FALSE; 432144961713Sgirish p_nxge_rdc_sys_stats_t statsp; 432244961713Sgirish nxge_status_t status = NXGE_OK; 432344961713Sgirish uint8_t portn; 432444961713Sgirish 432544961713Sgirish portn = nxgep->mac.portnum; 432644961713Sgirish statsp = (p_nxge_rdc_sys_stats_t)&nxgep->statsp->rdc_sys_stats; 432744961713Sgirish 432844961713Sgirish if (ipp_status & (0x1 << portn)) { 432944961713Sgirish statsp->ipp_eop_err++; 433044961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 433152ccf843Smisaki NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR); 433244961713Sgirish rxport_fatal = B_TRUE; 433344961713Sgirish } 433444961713Sgirish 433544961713Sgirish if (zcp_status & (0x1 << portn)) { 433644961713Sgirish statsp->zcp_eop_err++; 433744961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 433852ccf843Smisaki NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR); 433944961713Sgirish rxport_fatal = B_TRUE; 434044961713Sgirish } 434144961713Sgirish 434244961713Sgirish if (rxport_fatal) { 434344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 434452ccf843Smisaki " nxge_rxdma_handle_port_error: " 434552ccf843Smisaki " fatal error on Port #%d\n", 434652ccf843Smisaki portn)); 434744961713Sgirish status = nxge_rx_port_fatal_err_recover(nxgep); 434844961713Sgirish if (status == NXGE_OK) { 434944961713Sgirish FM_SERVICE_RESTORED(nxgep); 435044961713Sgirish } 435144961713Sgirish } 435244961713Sgirish 435344961713Sgirish return (status); 435444961713Sgirish } 435544961713Sgirish 435644961713Sgirish static nxge_status_t 435744961713Sgirish nxge_rxdma_fatal_err_recover(p_nxge_t nxgep, uint16_t channel) 435844961713Sgirish { 435944961713Sgirish npi_handle_t handle; 436044961713Sgirish npi_status_t rs = NPI_SUCCESS; 436144961713Sgirish nxge_status_t status = NXGE_OK; 436244961713Sgirish p_rx_rbr_ring_t rbrp; 436344961713Sgirish p_rx_rcr_ring_t rcrp; 436444961713Sgirish p_rx_mbox_t mboxp; 436544961713Sgirish rx_dma_ent_msk_t ent_mask; 436644961713Sgirish p_nxge_dma_common_t dmap; 436744961713Sgirish int ring_idx; 436844961713Sgirish uint32_t ref_cnt; 436944961713Sgirish p_rx_msg_t rx_msg_p; 437044961713Sgirish int i; 437144961713Sgirish uint32_t nxge_port_rcr_size; 437244961713Sgirish 437344961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_fatal_err_recover")); 437444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 437552ccf843Smisaki "Recovering from RxDMAChannel#%d error...", channel)); 437644961713Sgirish 437744961713Sgirish /* 437844961713Sgirish * Stop the dma channel waits for the stop done. 437944961713Sgirish * If the stop done bit is not set, then create 438044961713Sgirish * an error. 438144961713Sgirish */ 438244961713Sgirish 438344961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 438444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "Rx DMA stop...")); 438544961713Sgirish 438644961713Sgirish ring_idx = nxge_rxdma_get_ring_index(nxgep, channel); 438744961713Sgirish rbrp = (p_rx_rbr_ring_t)nxgep->rx_rbr_rings->rbr_rings[ring_idx]; 438844961713Sgirish rcrp = (p_rx_rcr_ring_t)nxgep->rx_rcr_rings->rcr_rings[ring_idx]; 438944961713Sgirish 439044961713Sgirish MUTEX_ENTER(&rcrp->lock); 439144961713Sgirish MUTEX_ENTER(&rbrp->lock); 439244961713Sgirish MUTEX_ENTER(&rbrp->post_lock); 439344961713Sgirish 439444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxDMA channel...")); 439544961713Sgirish 439644961713Sgirish rs = npi_rxdma_cfg_rdc_disable(handle, channel); 439744961713Sgirish if (rs != NPI_SUCCESS) { 439844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 439952ccf843Smisaki "nxge_disable_rxdma_channel:failed")); 440044961713Sgirish goto fail; 440144961713Sgirish } 440244961713Sgirish 440344961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxDMA interrupt...")); 440444961713Sgirish 440544961713Sgirish /* Disable interrupt */ 440644961713Sgirish ent_mask.value = RX_DMA_ENT_MSK_ALL; 440744961713Sgirish rs = npi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 440844961713Sgirish if (rs != NPI_SUCCESS) { 440944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 441052ccf843Smisaki "nxge_rxdma_stop_channel: " 441152ccf843Smisaki "set rxdma event masks failed (channel %d)", 441252ccf843Smisaki channel)); 441344961713Sgirish } 441444961713Sgirish 441544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "RxDMA channel reset...")); 441644961713Sgirish 441744961713Sgirish /* Reset RXDMA channel */ 441844961713Sgirish rs = npi_rxdma_cfg_rdc_reset(handle, channel); 441944961713Sgirish if (rs != NPI_SUCCESS) { 442044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 442152ccf843Smisaki "nxge_rxdma_fatal_err_recover: " 442252ccf843Smisaki " reset rxdma failed (channel %d)", channel)); 442344961713Sgirish goto fail; 442444961713Sgirish } 442544961713Sgirish 442644961713Sgirish nxge_port_rcr_size = nxgep->nxge_port_rcr_size; 442744961713Sgirish 442844961713Sgirish mboxp = 442952ccf843Smisaki (p_rx_mbox_t)nxgep->rx_mbox_areas_p->rxmbox_areas[ring_idx]; 443044961713Sgirish 443144961713Sgirish rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 443244961713Sgirish rbrp->rbr_rd_index = 0; 443344961713Sgirish 443444961713Sgirish rcrp->comp_rd_index = 0; 443544961713Sgirish rcrp->comp_wt_index = 0; 443644961713Sgirish rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 443752ccf843Smisaki (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 4438adfcba55Sjoycey #if defined(__i386) 443952ccf843Smisaki rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 444052ccf843Smisaki (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 4441adfcba55Sjoycey #else 444252ccf843Smisaki rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 444352ccf843Smisaki (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 4444adfcba55Sjoycey #endif 444544961713Sgirish 444644961713Sgirish rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 444752ccf843Smisaki (nxge_port_rcr_size - 1); 444844961713Sgirish rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 444952ccf843Smisaki (nxge_port_rcr_size - 1); 445044961713Sgirish 445144961713Sgirish dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 445244961713Sgirish bzero((caddr_t)dmap->kaddrp, dmap->alength); 445344961713Sgirish 445444961713Sgirish cmn_err(CE_NOTE, "!rbr entries = %d\n", rbrp->rbr_max_size); 445544961713Sgirish 445644961713Sgirish for (i = 0; i < rbrp->rbr_max_size; i++) { 445744961713Sgirish rx_msg_p = rbrp->rx_msg_ring[i]; 445844961713Sgirish ref_cnt = rx_msg_p->ref_cnt; 445944961713Sgirish if (ref_cnt != 1) { 4460a3c5bd6dSspeer if (rx_msg_p->cur_usage_cnt != 446152ccf843Smisaki rx_msg_p->max_usage_cnt) { 446244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 446352ccf843Smisaki "buf[%d]: cur_usage_cnt = %d " 446452ccf843Smisaki "max_usage_cnt = %d\n", i, 446552ccf843Smisaki rx_msg_p->cur_usage_cnt, 446652ccf843Smisaki rx_msg_p->max_usage_cnt)); 4467a3c5bd6dSspeer } else { 4468a3c5bd6dSspeer /* Buffer can be re-posted */ 4469a3c5bd6dSspeer rx_msg_p->free = B_TRUE; 4470a3c5bd6dSspeer rx_msg_p->cur_usage_cnt = 0; 4471a3c5bd6dSspeer rx_msg_p->max_usage_cnt = 0xbaddcafe; 4472a3c5bd6dSspeer rx_msg_p->pkt_buf_size = 0; 4473a3c5bd6dSspeer } 447444961713Sgirish } 447544961713Sgirish } 447644961713Sgirish 447744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "RxDMA channel re-start...")); 447844961713Sgirish 447944961713Sgirish status = nxge_rxdma_start_channel(nxgep, channel, rbrp, rcrp, mboxp); 448044961713Sgirish if (status != NXGE_OK) { 448144961713Sgirish goto fail; 448244961713Sgirish } 448344961713Sgirish 448444961713Sgirish MUTEX_EXIT(&rbrp->post_lock); 448544961713Sgirish MUTEX_EXIT(&rbrp->lock); 448644961713Sgirish MUTEX_EXIT(&rcrp->lock); 448744961713Sgirish 448844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 448952ccf843Smisaki "Recovery Successful, RxDMAChannel#%d Restored", 449052ccf843Smisaki channel)); 449144961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fatal_err_recover")); 449244961713Sgirish 449344961713Sgirish return (NXGE_OK); 449444961713Sgirish fail: 449544961713Sgirish MUTEX_EXIT(&rbrp->post_lock); 449644961713Sgirish MUTEX_EXIT(&rbrp->lock); 449744961713Sgirish MUTEX_EXIT(&rcrp->lock); 449844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Recovery failed")); 449944961713Sgirish 450044961713Sgirish return (NXGE_ERROR | rs); 450144961713Sgirish } 450244961713Sgirish 450344961713Sgirish nxge_status_t 450444961713Sgirish nxge_rx_port_fatal_err_recover(p_nxge_t nxgep) 450544961713Sgirish { 4506678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set; 4507678453a8Sspeer nxge_status_t status = NXGE_OK; 4508678453a8Sspeer int rdc; 450944961713Sgirish 451044961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_port_fatal_err_recover")); 451144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 451252ccf843Smisaki "Recovering from RxPort error...")); 4513678453a8Sspeer NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disabling RxMAC...\n")); 451444961713Sgirish 451544961713Sgirish if (nxge_rx_mac_disable(nxgep) != NXGE_OK) 451644961713Sgirish goto fail; 451744961713Sgirish 451844961713Sgirish NXGE_DELAY(1000); 451944961713Sgirish 4520678453a8Sspeer NXGE_DEBUG_MSG((nxgep, RX_CTL, "Stopping all RxDMA channels...")); 452144961713Sgirish 4522678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 4523678453a8Sspeer if ((1 << rdc) & set->owned.map) { 4524678453a8Sspeer if (nxge_rxdma_fatal_err_recover(nxgep, rdc) 4525678453a8Sspeer != NXGE_OK) { 4526678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4527678453a8Sspeer "Could not recover channel %d", rdc)); 4528678453a8Sspeer } 452944961713Sgirish } 453044961713Sgirish } 453144961713Sgirish 4532678453a8Sspeer NXGE_DEBUG_MSG((nxgep, RX_CTL, "Resetting IPP...")); 453344961713Sgirish 453444961713Sgirish /* Reset IPP */ 453544961713Sgirish if (nxge_ipp_reset(nxgep) != NXGE_OK) { 453644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 453752ccf843Smisaki "nxge_rx_port_fatal_err_recover: " 453852ccf843Smisaki "Failed to reset IPP")); 453944961713Sgirish goto fail; 454044961713Sgirish } 454144961713Sgirish 454244961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "Reset RxMAC...")); 454344961713Sgirish 454444961713Sgirish /* Reset RxMAC */ 454544961713Sgirish if (nxge_rx_mac_reset(nxgep) != NXGE_OK) { 454644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 454752ccf843Smisaki "nxge_rx_port_fatal_err_recover: " 454852ccf843Smisaki "Failed to reset RxMAC")); 454944961713Sgirish goto fail; 455044961713Sgirish } 455144961713Sgirish 455244961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-initialize IPP...")); 455344961713Sgirish 455444961713Sgirish /* Re-Initialize IPP */ 455544961713Sgirish if (nxge_ipp_init(nxgep) != NXGE_OK) { 455644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 455752ccf843Smisaki "nxge_rx_port_fatal_err_recover: " 455852ccf843Smisaki "Failed to init IPP")); 455944961713Sgirish goto fail; 456044961713Sgirish } 456144961713Sgirish 456244961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-initialize RxMAC...")); 456344961713Sgirish 456444961713Sgirish /* Re-Initialize RxMAC */ 456544961713Sgirish if ((status = nxge_rx_mac_init(nxgep)) != NXGE_OK) { 456644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 456752ccf843Smisaki "nxge_rx_port_fatal_err_recover: " 456852ccf843Smisaki "Failed to reset RxMAC")); 456944961713Sgirish goto fail; 457044961713Sgirish } 457144961713Sgirish 457244961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-enable RxMAC...")); 457344961713Sgirish 457444961713Sgirish /* Re-enable RxMAC */ 457544961713Sgirish if ((status = nxge_rx_mac_enable(nxgep)) != NXGE_OK) { 457644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 457752ccf843Smisaki "nxge_rx_port_fatal_err_recover: " 457852ccf843Smisaki "Failed to enable RxMAC")); 457944961713Sgirish goto fail; 458044961713Sgirish } 458144961713Sgirish 458244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 458352ccf843Smisaki "Recovery Successful, RxPort Restored")); 458444961713Sgirish 458544961713Sgirish return (NXGE_OK); 458644961713Sgirish fail: 458744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Recovery failed")); 458844961713Sgirish return (status); 458944961713Sgirish } 459044961713Sgirish 459144961713Sgirish void 459244961713Sgirish nxge_rxdma_inject_err(p_nxge_t nxgep, uint32_t err_id, uint8_t chan) 459344961713Sgirish { 459444961713Sgirish rx_dma_ctl_stat_t cs; 459544961713Sgirish rx_ctl_dat_fifo_stat_t cdfs; 459644961713Sgirish 459744961713Sgirish switch (err_id) { 459844961713Sgirish case NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR: 459944961713Sgirish case NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR: 460044961713Sgirish case NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR: 460144961713Sgirish case NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR: 460244961713Sgirish case NXGE_FM_EREPORT_RDMC_RBR_TMOUT: 460344961713Sgirish case NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR: 460444961713Sgirish case NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS: 460544961713Sgirish case NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR: 460644961713Sgirish case NXGE_FM_EREPORT_RDMC_RCRINCON: 460744961713Sgirish case NXGE_FM_EREPORT_RDMC_RCRFULL: 460844961713Sgirish case NXGE_FM_EREPORT_RDMC_RBRFULL: 460944961713Sgirish case NXGE_FM_EREPORT_RDMC_RBRLOGPAGE: 461044961713Sgirish case NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE: 461144961713Sgirish case NXGE_FM_EREPORT_RDMC_CONFIG_ERR: 461244961713Sgirish RXDMA_REG_READ64(nxgep->npi_handle, RX_DMA_CTL_STAT_DBG_REG, 461352ccf843Smisaki chan, &cs.value); 461444961713Sgirish if (err_id == NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR) 461544961713Sgirish cs.bits.hdw.rcr_ack_err = 1; 461644961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR) 461744961713Sgirish cs.bits.hdw.dc_fifo_err = 1; 461844961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR) 461944961713Sgirish cs.bits.hdw.rcr_sha_par = 1; 462044961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR) 462144961713Sgirish cs.bits.hdw.rbr_pre_par = 1; 462244961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_RBR_TMOUT) 462344961713Sgirish cs.bits.hdw.rbr_tmout = 1; 462444961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR) 462544961713Sgirish cs.bits.hdw.rsp_cnt_err = 1; 462644961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS) 462744961713Sgirish cs.bits.hdw.byte_en_bus = 1; 462844961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR) 462944961713Sgirish cs.bits.hdw.rsp_dat_err = 1; 463044961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_CONFIG_ERR) 463144961713Sgirish cs.bits.hdw.config_err = 1; 463244961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_RCRINCON) 463344961713Sgirish cs.bits.hdw.rcrincon = 1; 463444961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_RCRFULL) 463544961713Sgirish cs.bits.hdw.rcrfull = 1; 463644961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_RBRFULL) 463744961713Sgirish cs.bits.hdw.rbrfull = 1; 463844961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_RBRLOGPAGE) 463944961713Sgirish cs.bits.hdw.rbrlogpage = 1; 464044961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE) 464144961713Sgirish cs.bits.hdw.cfiglogpage = 1; 4642adfcba55Sjoycey #if defined(__i386) 4643adfcba55Sjoycey cmn_err(CE_NOTE, "!Write 0x%llx to RX_DMA_CTL_STAT_DBG_REG\n", 464452ccf843Smisaki cs.value); 4645adfcba55Sjoycey #else 464644961713Sgirish cmn_err(CE_NOTE, "!Write 0x%lx to RX_DMA_CTL_STAT_DBG_REG\n", 464752ccf843Smisaki cs.value); 4648adfcba55Sjoycey #endif 464944961713Sgirish RXDMA_REG_WRITE64(nxgep->npi_handle, RX_DMA_CTL_STAT_DBG_REG, 465052ccf843Smisaki chan, cs.value); 465144961713Sgirish break; 465244961713Sgirish case NXGE_FM_EREPORT_RDMC_ID_MISMATCH: 465344961713Sgirish case NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR: 465444961713Sgirish case NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR: 465544961713Sgirish cdfs.value = 0; 465644961713Sgirish if (err_id == NXGE_FM_EREPORT_RDMC_ID_MISMATCH) 465744961713Sgirish cdfs.bits.ldw.id_mismatch = (1 << nxgep->mac.portnum); 465844961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR) 465944961713Sgirish cdfs.bits.ldw.zcp_eop_err = (1 << nxgep->mac.portnum); 466044961713Sgirish else if (err_id == NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR) 466144961713Sgirish cdfs.bits.ldw.ipp_eop_err = (1 << nxgep->mac.portnum); 4662adfcba55Sjoycey #if defined(__i386) 4663adfcba55Sjoycey cmn_err(CE_NOTE, 466452ccf843Smisaki "!Write 0x%llx to RX_CTL_DAT_FIFO_STAT_DBG_REG\n", 466552ccf843Smisaki cdfs.value); 4666adfcba55Sjoycey #else 466744961713Sgirish cmn_err(CE_NOTE, 466852ccf843Smisaki "!Write 0x%lx to RX_CTL_DAT_FIFO_STAT_DBG_REG\n", 466952ccf843Smisaki cdfs.value); 4670adfcba55Sjoycey #endif 4671678453a8Sspeer NXGE_REG_WR64(nxgep->npi_handle, 4672678453a8Sspeer RX_CTL_DAT_FIFO_STAT_DBG_REG, cdfs.value); 467344961713Sgirish break; 467444961713Sgirish case NXGE_FM_EREPORT_RDMC_DCF_ERR: 467544961713Sgirish break; 467653f3d8ecSyc case NXGE_FM_EREPORT_RDMC_RCR_ERR: 467744961713Sgirish break; 467844961713Sgirish } 467944961713Sgirish } 4680678453a8Sspeer 4681678453a8Sspeer static void 4682678453a8Sspeer nxge_rxdma_databuf_free(p_rx_rbr_ring_t rbr_p) 4683678453a8Sspeer { 4684678453a8Sspeer rxring_info_t *ring_info; 4685678453a8Sspeer int index; 4686678453a8Sspeer uint32_t chunk_size; 4687678453a8Sspeer uint64_t kaddr; 4688678453a8Sspeer uint_t num_blocks; 4689678453a8Sspeer 4690678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, "==> nxge_rxdma_databuf_free")); 4691678453a8Sspeer 4692678453a8Sspeer if (rbr_p == NULL) { 4693678453a8Sspeer NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 4694678453a8Sspeer "==> nxge_rxdma_databuf_free: NULL rbr pointer")); 4695678453a8Sspeer return; 4696678453a8Sspeer } 4697678453a8Sspeer 4698678453a8Sspeer if (rbr_p->rbr_alloc_type == DDI_MEM_ALLOC) { 4699678453a8Sspeer NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 4700678453a8Sspeer "==> nxge_rxdma_databuf_free: DDI")); 4701678453a8Sspeer return; 4702678453a8Sspeer } 4703678453a8Sspeer 4704678453a8Sspeer ring_info = rbr_p->ring_info; 4705678453a8Sspeer if (ring_info == NULL) { 4706678453a8Sspeer NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 4707678453a8Sspeer "==> nxge_rxdma_databuf_free: NULL ring info")); 4708678453a8Sspeer return; 4709678453a8Sspeer } 4710678453a8Sspeer num_blocks = rbr_p->num_blocks; 4711678453a8Sspeer for (index = 0; index < num_blocks; index++) { 4712678453a8Sspeer kaddr = ring_info->buffer[index].kaddr; 4713678453a8Sspeer chunk_size = ring_info->buffer[index].buf_size; 4714678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, 4715678453a8Sspeer "==> nxge_rxdma_databuf_free: free chunk %d " 4716678453a8Sspeer "kaddrp $%p chunk size %d", 4717678453a8Sspeer index, kaddr, chunk_size)); 4718678453a8Sspeer if (kaddr == NULL) continue; 4719678453a8Sspeer nxge_free_buf(rbr_p->rbr_alloc_type, kaddr, chunk_size); 4720678453a8Sspeer ring_info->buffer[index].kaddr = NULL; 4721678453a8Sspeer } 4722678453a8Sspeer 4723678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_databuf_free")); 4724678453a8Sspeer } 4725678453a8Sspeer 4726678453a8Sspeer #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 4727678453a8Sspeer extern void contig_mem_free(void *, size_t); 4728678453a8Sspeer #endif 4729678453a8Sspeer 4730678453a8Sspeer void 4731678453a8Sspeer nxge_free_buf(buf_alloc_type_t alloc_type, uint64_t kaddr, uint32_t buf_size) 4732678453a8Sspeer { 4733678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, "==> nxge_free_buf")); 4734678453a8Sspeer 4735678453a8Sspeer if (kaddr == NULL || !buf_size) { 4736678453a8Sspeer NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 4737678453a8Sspeer "==> nxge_free_buf: invalid kaddr $%p size to free %d", 4738678453a8Sspeer kaddr, buf_size)); 4739678453a8Sspeer return; 4740678453a8Sspeer } 4741678453a8Sspeer 4742678453a8Sspeer switch (alloc_type) { 4743678453a8Sspeer case KMEM_ALLOC: 4744678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, 4745678453a8Sspeer "==> nxge_free_buf: freeing kmem $%p size %d", 4746678453a8Sspeer kaddr, buf_size)); 4747678453a8Sspeer #if defined(__i386) 4748678453a8Sspeer KMEM_FREE((void *)(uint32_t)kaddr, buf_size); 4749678453a8Sspeer #else 4750678453a8Sspeer KMEM_FREE((void *)kaddr, buf_size); 4751678453a8Sspeer #endif 4752678453a8Sspeer break; 4753678453a8Sspeer 4754678453a8Sspeer #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 4755678453a8Sspeer case CONTIG_MEM_ALLOC: 4756678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, 4757678453a8Sspeer "==> nxge_free_buf: freeing contig_mem kaddr $%p size %d", 4758678453a8Sspeer kaddr, buf_size)); 4759678453a8Sspeer contig_mem_free((void *)kaddr, buf_size); 4760678453a8Sspeer break; 4761678453a8Sspeer #endif 4762678453a8Sspeer 4763678453a8Sspeer default: 4764678453a8Sspeer NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 4765678453a8Sspeer "<== nxge_free_buf: unsupported alloc type %d", 4766678453a8Sspeer alloc_type)); 4767678453a8Sspeer return; 4768678453a8Sspeer } 4769678453a8Sspeer 4770678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_free_buf")); 4771678453a8Sspeer } 4772