xref: /illumos-gate/usr/src/uts/common/io/nxge/nxge_ndd.c (revision 86ef0a63)
144961713Sgirish /*
244961713Sgirish  * CDDL HEADER START
344961713Sgirish  *
444961713Sgirish  * The contents of this file are subject to the terms of the
544961713Sgirish  * Common Development and Distribution License (the "License").
644961713Sgirish  * You may not use this file except in compliance with the License.
744961713Sgirish  *
844961713Sgirish  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
944961713Sgirish  * or http://www.opensolaris.org/os/licensing.
1044961713Sgirish  * See the License for the specific language governing permissions
1144961713Sgirish  * and limitations under the License.
1244961713Sgirish  *
1344961713Sgirish  * When distributing Covered Code, include this CDDL HEADER in each
1444961713Sgirish  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1544961713Sgirish  * If applicable, add the following below this CDDL HEADER, with the
1644961713Sgirish  * fields enclosed by brackets "[]" replaced with your own identifying
1744961713Sgirish  * information: Portions Copyright [yyyy] [name of copyright owner]
1844961713Sgirish  *
1944961713Sgirish  * CDDL HEADER END
2044961713Sgirish  */
2144961713Sgirish /*
227b26d9ffSSantwona Behera  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
2344961713Sgirish  * Use is subject to license terms.
2444961713Sgirish  */
2544961713Sgirish 
2644961713Sgirish #include <sys/nxge/nxge_impl.h>
27678453a8Sspeer #include <sys/nxge/nxge_hio.h>
28678453a8Sspeer 
2944961713Sgirish #include <inet/common.h>
3044961713Sgirish #include <inet/mi.h>
3144961713Sgirish #include <inet/nd.h>
3244961713Sgirish 
3344961713Sgirish extern uint64_t npi_debug_level;
3444961713Sgirish 
35a3c5bd6dSspeer #define	NXGE_PARAM_MAC_RW \
36a3c5bd6dSspeer 	NXGE_PARAM_RW | NXGE_PARAM_MAC | \
3744961713Sgirish 	NXGE_PARAM_NDD_WR_OK | NXGE_PARAM_READ_PROP
3844961713Sgirish 
39a3c5bd6dSspeer #define	NXGE_PARAM_MAC_DONT_SHOW \
40a3c5bd6dSspeer 	NXGE_PARAM_RW | NXGE_PARAM_MAC | NXGE_PARAM_DONT_SHOW
4144961713Sgirish 
42a3c5bd6dSspeer #define	NXGE_PARAM_RXDMA_RW \
43a3c5bd6dSspeer 	NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_NDD_WR_OK | \
44a3c5bd6dSspeer 	NXGE_PARAM_READ_PROP
4544961713Sgirish 
46a3c5bd6dSspeer #define	NXGE_PARAM_RXDMA_RWC \
47a3c5bd6dSspeer 	NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_INIT_ONLY | \
48a3c5bd6dSspeer 	NXGE_PARAM_READ_PROP
4944961713Sgirish 
50a3c5bd6dSspeer #define	NXGE_PARAM_L2CLASS_CFG \
51a3c5bd6dSspeer 	NXGE_PARAM_RW | NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_READ_PROP | \
52a3c5bd6dSspeer 	NXGE_PARAM_NDD_WR_OK
5344961713Sgirish 
54a3c5bd6dSspeer #define	NXGE_PARAM_CLASS_RWS \
55a3c5bd6dSspeer 	NXGE_PARAM_RWS |  NXGE_PARAM_READ_PROP
5644961713Sgirish 
5744961713Sgirish #define	NXGE_PARAM_ARRAY_INIT_SIZE	0x20ULL
5844961713Sgirish 
5944961713Sgirish #define	SET_RX_INTR_TIME_DISABLE 0
6044961713Sgirish #define	SET_RX_INTR_TIME_ENABLE 1
6144961713Sgirish #define	SET_RX_INTR_PKTS 2
6244961713Sgirish 
6344961713Sgirish #define	BASE_ANY	0
64*86ef0a63SRichard Lowe #define	BASE_BINARY	2
6544961713Sgirish #define	BASE_HEX	16
6644961713Sgirish #define	BASE_DECIMAL	10
6744961713Sgirish #define	ALL_FF_64	0xFFFFFFFFFFFFFFFFULL
6844961713Sgirish #define	ALL_FF_32	0xFFFFFFFFUL
6944961713Sgirish 
7044961713Sgirish #define	NXGE_NDD_INFODUMP_BUFF_SIZE	2048 /* is 2k enough? */
7144961713Sgirish #define	NXGE_NDD_INFODUMP_BUFF_8K	8192
7244961713Sgirish #define	NXGE_NDD_INFODUMP_BUFF_16K	0x2000
7344961713Sgirish #define	NXGE_NDD_INFODUMP_BUFF_64K	0x8000
7444961713Sgirish 
7544961713Sgirish #define	PARAM_OUTOF_RANGE(vptr, eptr, rval, pa)	\
7644961713Sgirish 	((vptr == eptr) || (rval < pa->minimum) || (rval > pa->maximum))
7744961713Sgirish 
7844961713Sgirish #define	ADVANCE_PRINT_BUFFER(pmp, plen, rlen) { \
7944961713Sgirish 	((mblk_t *)pmp)->b_wptr += plen; \
8044961713Sgirish 	rlen -= plen; \
81a3c5bd6dSspeer }
8244961713Sgirish 
834045d941Ssowmini int nxge_param_set_mac(p_nxge_t, queue_t *,
84a3c5bd6dSspeer 	mblk_t *, char *, caddr_t);
8544961713Sgirish static int nxge_param_set_port_rdc(p_nxge_t, queue_t *,
86a3c5bd6dSspeer 	mblk_t *, char *, caddr_t);
8744961713Sgirish static int nxge_param_set_grp_rdc(p_nxge_t, queue_t *,
88a3c5bd6dSspeer 	mblk_t *, char *, caddr_t);
8944961713Sgirish static int nxge_param_set_ether_usr(p_nxge_t,
90a3c5bd6dSspeer 	queue_t *, mblk_t *, char *, caddr_t);
9144961713Sgirish static int nxge_param_set_ip_usr(p_nxge_t,
92a3c5bd6dSspeer 	queue_t *, mblk_t *, char *, caddr_t);
9344961713Sgirish static int nxge_param_set_vlan_rdcgrp(p_nxge_t,
94a3c5bd6dSspeer 	queue_t *, mblk_t *, char *, caddr_t);
9544961713Sgirish static int nxge_param_set_mac_rdcgrp(p_nxge_t,
96a3c5bd6dSspeer 	queue_t *, mblk_t *, char *, caddr_t);
9744961713Sgirish static int nxge_param_fflp_hash_init(p_nxge_t,
98a3c5bd6dSspeer 	queue_t *, mblk_t *, char *, caddr_t);
9944961713Sgirish static int nxge_param_llc_snap_enable(p_nxge_t, queue_t *,
100a3c5bd6dSspeer 	mblk_t *, char *, caddr_t);
10144961713Sgirish static int nxge_param_hash_lookup_enable(p_nxge_t, queue_t *,
102a3c5bd6dSspeer 	mblk_t *, char *, caddr_t);
10344961713Sgirish static int nxge_param_tcam_enable(p_nxge_t, queue_t *,
104a3c5bd6dSspeer 	mblk_t *, char *, caddr_t);
10556d930aeSspeer static int nxge_param_get_fw_ver(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
1062e59129aSraghus static int nxge_param_get_port_mode(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
10744961713Sgirish static int nxge_param_get_rxdma_info(p_nxge_t, queue_t *q,
108a3c5bd6dSspeer 	p_mblk_t, caddr_t);
10944961713Sgirish static int nxge_param_get_txdma_info(p_nxge_t, queue_t *q,
110a3c5bd6dSspeer 	p_mblk_t, caddr_t);
11144961713Sgirish static int nxge_param_get_vlan_rdcgrp(p_nxge_t, queue_t *,
112a3c5bd6dSspeer 	p_mblk_t, caddr_t);
11344961713Sgirish static int nxge_param_get_mac_rdcgrp(p_nxge_t, queue_t *,
114a3c5bd6dSspeer 	p_mblk_t, caddr_t);
11544961713Sgirish static int nxge_param_get_rxdma_rdcgrp_info(p_nxge_t, queue_t *,
116a3c5bd6dSspeer 	p_mblk_t, caddr_t);
117c1f9c6e5SSantwona Behera static int nxge_param_get_rx_intr_time(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
118c1f9c6e5SSantwona Behera static int nxge_param_get_rx_intr_pkts(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
11944961713Sgirish static int nxge_param_get_ip_opt(p_nxge_t, queue_t *, mblk_t *, caddr_t);
120a3c5bd6dSspeer static int nxge_param_get_mac(p_nxge_t, queue_t *q, p_mblk_t, caddr_t);
12144961713Sgirish static int nxge_param_get_debug_flag(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
12244961713Sgirish static int nxge_param_set_nxge_debug_flag(p_nxge_t, queue_t *, mblk_t *,
123a3c5bd6dSspeer 	char *, caddr_t);
12444961713Sgirish static int nxge_param_set_npi_debug_flag(p_nxge_t,
125a3c5bd6dSspeer 	queue_t *, mblk_t *, char *, caddr_t);
12644961713Sgirish static int nxge_param_dump_rdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t);
12744961713Sgirish static int nxge_param_dump_tdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t);
12844961713Sgirish static int nxge_param_dump_mac_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
12944961713Sgirish static int nxge_param_dump_ipp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
13044961713Sgirish static int nxge_param_dump_fflp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
13144961713Sgirish static int nxge_param_dump_vlan_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
13244961713Sgirish static int nxge_param_dump_rdc_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
13344961713Sgirish static int nxge_param_dump_ptrs(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
1341bd6825cSml static void nxge_param_sync(p_nxge_t);
13544961713Sgirish 
13644961713Sgirish /*
13744961713Sgirish  * Global array of Neptune changable parameters.
13844961713Sgirish  * This array is initialized to correspond to the default
13944961713Sgirish  * Neptune 4 port configuration. This array would be copied
14044961713Sgirish  * into each port's parameter structure and modifed per
14144961713Sgirish  * fcode and nxge.conf configuration. Later, the parameters are
14244961713Sgirish  * exported to ndd to display and run-time configuration (at least
14344961713Sgirish  * some of them).
14444961713Sgirish  *
14500161856Syc  * Parameters with DONT_SHOW are not shown by ndd.
14600161856Syc  *
14744961713Sgirish  */
14844961713Sgirish 
149a3c5bd6dSspeer static nxge_param_t	nxge_param_arr[] = {
150a3c5bd6dSspeer 	/*
151a3c5bd6dSspeer 	 * min	max	value	old	hw-name	conf-name
152a3c5bd6dSspeer 	 */
153846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
154a3c5bd6dSspeer 		0, 999, 1000, 0, "instance", "instance"},
155a3c5bd6dSspeer 
156846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
157a3c5bd6dSspeer 		0, 999, 1000, 0, "main-instance", "main_instance"},
158a3c5bd6dSspeer 
159a3c5bd6dSspeer 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ,
160a3c5bd6dSspeer 		0, 3, 0, 0, "function-number", "function_number"},
161a3c5bd6dSspeer 
162a3c5bd6dSspeer 	/* Partition Id */
163846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
164a3c5bd6dSspeer 		0, 8, 0, 0, "partition-id", "partition_id"},
165a3c5bd6dSspeer 
166a3c5bd6dSspeer 	/* Read Write Permission Mode */
167846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
168a3c5bd6dSspeer 		0, 2, 0, 0, "read-write-mode", "read_write_mode"},
169a3c5bd6dSspeer 
17056d930aeSspeer 	{ nxge_param_get_fw_ver, NULL, NXGE_PARAM_READ,
17156d930aeSspeer 		0, 32, 0, 0, "version",	"fw_version"},
17256d930aeSspeer 
1732e59129aSraghus 	{ nxge_param_get_port_mode, NULL, NXGE_PARAM_READ,
1742e59129aSraghus 		0, 32, 0, 0, "port-mode", "port_mode"},
1752e59129aSraghus 
176a3c5bd6dSspeer 	/* hw cfg types */
177a3c5bd6dSspeer 	/* control the DMA config of Neptune/NIU */
178846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
179a3c5bd6dSspeer 		CFG_DEFAULT, CFG_CUSTOM, CFG_DEFAULT, CFG_DEFAULT,
180a3c5bd6dSspeer 		"niu-cfg-type", "niu_cfg_type"},
181a3c5bd6dSspeer 
182a3c5bd6dSspeer 	/* control the TXDMA config of the Port controlled by tx-quick-cfg */
183846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
184a3c5bd6dSspeer 		CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT,
185a3c5bd6dSspeer 		"tx-qcfg-type", "tx_qcfg_type"},
186a3c5bd6dSspeer 
187a3c5bd6dSspeer 	/* control the RXDMA config of the Port controlled by rx-quick-cfg */
188846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
189a3c5bd6dSspeer 		CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT,
190a3c5bd6dSspeer 		"rx-qcfg-type", "rx_qcfg_type"},
191a3c5bd6dSspeer 
192a3c5bd6dSspeer 	{ nxge_param_get_mac, nxge_param_set_mac,
193a3c5bd6dSspeer 		NXGE_PARAM_RW  | NXGE_PARAM_DONT_SHOW,
194a3c5bd6dSspeer 		0, 1, 0, 0, "master-cfg-enable", "master_cfg_enable"},
195a3c5bd6dSspeer 
196a3c5bd6dSspeer 	{ nxge_param_get_mac, nxge_param_set_mac,
197846a903dSml 		NXGE_PARAM_DONT_SHOW,
198a3c5bd6dSspeer 		0, 1, 0, 0, "master-cfg-value", "master_cfg_value"},
199a3c5bd6dSspeer 
200a3c5bd6dSspeer 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
201a3c5bd6dSspeer 		0, 1, 1, 1, "adv-autoneg-cap", "adv_autoneg_cap"},
202a3c5bd6dSspeer 
203a3c5bd6dSspeer 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
204a3c5bd6dSspeer 		0, 1, 1, 1, "adv-10gfdx-cap", "adv_10gfdx_cap"},
205a3c5bd6dSspeer 
206a3c5bd6dSspeer 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
207a3c5bd6dSspeer 		0, 1, 0, 0, "adv-10ghdx-cap", "adv_10ghdx_cap"},
208a3c5bd6dSspeer 
209a3c5bd6dSspeer 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
210a3c5bd6dSspeer 		0, 1, 1, 1, "adv-1000fdx-cap", "adv_1000fdx_cap"},
211a3c5bd6dSspeer 
212a3c5bd6dSspeer 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
213a3c5bd6dSspeer 		0, 1, 0, 0, "adv-1000hdx-cap",	"adv_1000hdx_cap"},
214a3c5bd6dSspeer 
215a3c5bd6dSspeer 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
216a3c5bd6dSspeer 		0, 1, 0, 0, "adv-100T4-cap", "adv_100T4_cap"},
217a3c5bd6dSspeer 
218a3c5bd6dSspeer 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
219a3c5bd6dSspeer 		0, 1, 1, 1, "adv-100fdx-cap", "adv_100fdx_cap"},
220a3c5bd6dSspeer 
221a3c5bd6dSspeer 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
222a3c5bd6dSspeer 		0, 1, 0, 0, "adv-100hdx-cap", "adv_100hdx_cap"},
223a3c5bd6dSspeer 
224a3c5bd6dSspeer 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
225a3c5bd6dSspeer 		0, 1, 1, 1, "adv-10fdx-cap", "adv_10fdx_cap"},
226a3c5bd6dSspeer 
227a3c5bd6dSspeer 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
228a3c5bd6dSspeer 		0, 1, 0, 0, "adv-10hdx-cap", "adv_10hdx_cap"},
229a3c5bd6dSspeer 
230846a903dSml 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
231a3c5bd6dSspeer 		0, 1, 0, 0, "adv-asmpause-cap",	"adv_asmpause_cap"},
232a3c5bd6dSspeer 
233a3c5bd6dSspeer 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
234a3c5bd6dSspeer 		0, 1, 0, 0, "adv-pause-cap", "adv_pause_cap"},
235a3c5bd6dSspeer 
236846a903dSml 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
237a3c5bd6dSspeer 		0, 1, 0, 0, "use-int-xcvr", "use_int_xcvr"},
238a3c5bd6dSspeer 
239846a903dSml 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
240a3c5bd6dSspeer 		0, 1, 1, 1, "enable-ipg0", "enable_ipg0"},
241a3c5bd6dSspeer 
242846a903dSml 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
243a3c5bd6dSspeer 		0, 255,	8, 8, "ipg0", "ipg0"},
244a3c5bd6dSspeer 
245846a903dSml 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
246a3c5bd6dSspeer 		0, 255,	8, 8, "ipg1", "ipg1"},
247a3c5bd6dSspeer 
248846a903dSml 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
249a3c5bd6dSspeer 		0, 255,	4, 4, "ipg2", "ipg2"},
250a3c5bd6dSspeer 
251a3c5bd6dSspeer 	/* Transmit DMA channels */
252846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ |
253846a903dSml 		NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
254a3c5bd6dSspeer 		0, 3, 0, 0, "tx-dma-weight", "tx_dma_weight"},
255a3c5bd6dSspeer 
256846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ |
257846a903dSml 		NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
258a3c5bd6dSspeer 		0, 31, 0, 0, "tx-dma-channels-begin", "tx_dma_channels_begin"},
259a3c5bd6dSspeer 
260846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ |
261846a903dSml 		NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
262a3c5bd6dSspeer 		0, 32, 0, 0, "tx-dma-channels", "tx_dma_channels"},
263a3c5bd6dSspeer 	{ nxge_param_get_txdma_info, NULL,
264846a903dSml 		NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
265a3c5bd6dSspeer 		0, 32, 0, 0, "tx-dma-info", "tx_dma_info"},
266a3c5bd6dSspeer 
267a3c5bd6dSspeer 	/* Receive DMA channels */
268a3c5bd6dSspeer 	{ nxge_param_get_generic, NULL,
269846a903dSml 		NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
270a3c5bd6dSspeer 		0, 31, 0, 0, "rx-dma-channels-begin", "rx_dma_channels_begin"},
271a3c5bd6dSspeer 
272846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ |
273846a903dSml 		NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
274a3c5bd6dSspeer 		0, 32, 0, 0, "rx-dma-channels",	"rx_dma_channels"},
275a3c5bd6dSspeer 
276846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ |
277846a903dSml 		NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
278a3c5bd6dSspeer 		0, 65535, PT_DRR_WT_DEFAULT_10G, 0,
279a3c5bd6dSspeer 		"rx-drr-weight", "rx_drr_weight"},
280a3c5bd6dSspeer 
281846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ |
282846a903dSml 		NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
283a3c5bd6dSspeer 		0, 1, 1, 0, "rx-full-header", "rx_full_header"},
284a3c5bd6dSspeer 
285846a903dSml 	{ nxge_param_get_rxdma_info, NULL, NXGE_PARAM_READ |
286846a903dSml 		NXGE_PARAM_DONT_SHOW,
287a3c5bd6dSspeer 		0, 32, 0, 0, "rx-dma-info", "rx_dma_info"},
288a3c5bd6dSspeer 
289a3c5bd6dSspeer 	{ nxge_param_get_rxdma_info, NULL,
290a3c5bd6dSspeer 		NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
291a3c5bd6dSspeer 		NXGE_RBR_RBB_MIN, NXGE_RBR_RBB_MAX, NXGE_RBR_RBB_DEFAULT, 0,
292a3c5bd6dSspeer 		"rx-rbr-size", "rx_rbr_size"},
293a3c5bd6dSspeer 
294a3c5bd6dSspeer 	{ nxge_param_get_rxdma_info, NULL,
295a3c5bd6dSspeer 		NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
296a3c5bd6dSspeer 		NXGE_RCR_MIN, NXGE_RCR_MAX, NXGE_RCR_DEFAULT, 0,
297a3c5bd6dSspeer 		"rx-rcr-size", "rx_rcr_size"},
298a3c5bd6dSspeer 
299846a903dSml 	{ nxge_param_get_generic, nxge_param_set_port_rdc,
300846a903dSml 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
301a3c5bd6dSspeer 		0, 15, 0, 0, "default-port-rdc", "default_port_rdc"},
302a3c5bd6dSspeer 
303c1f9c6e5SSantwona Behera 	{ nxge_param_get_rx_intr_time, nxge_param_rx_intr_time,
304c1f9c6e5SSantwona Behera 		NXGE_PARAM_RXDMA_RW,
305a3c5bd6dSspeer 		NXGE_RDC_RCR_TIMEOUT_MIN, NXGE_RDC_RCR_TIMEOUT_MAX,
3067b26d9ffSSantwona Behera 		NXGE_RDC_RCR_TIMEOUT, 0, "rxdma-intr-time", "rxdma_intr_time"},
307a3c5bd6dSspeer 
308c1f9c6e5SSantwona Behera 	{ nxge_param_get_rx_intr_pkts, nxge_param_rx_intr_pkts,
309c1f9c6e5SSantwona Behera 		NXGE_PARAM_RXDMA_RW,
310a3c5bd6dSspeer 		NXGE_RDC_RCR_THRESHOLD_MIN, NXGE_RDC_RCR_THRESHOLD_MAX,
3117b26d9ffSSantwona Behera 		NXGE_RDC_RCR_THRESHOLD, 0,
312a3c5bd6dSspeer 		"rxdma-intr-pkts", "rxdma_intr_pkts"},
313a3c5bd6dSspeer 
314846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP |
315846a903dSml 		NXGE_PARAM_DONT_SHOW,
316a3c5bd6dSspeer 		0, 8, 0, 0, "rx-rdc-grps-begin", "rx_rdc_grps_begin"},
317a3c5bd6dSspeer 
318846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP |
319846a903dSml 		NXGE_PARAM_DONT_SHOW,
320a3c5bd6dSspeer 		0, 8, 0, 0, "rx-rdc-grps", "rx_rdc_grps"},
321a3c5bd6dSspeer 
322846a903dSml 	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
323846a903dSml 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
324a3c5bd6dSspeer 		0, 15, 0, 0, "default-grp0-rdc", "default_grp0_rdc"},
325a3c5bd6dSspeer 
326846a903dSml 	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
327846a903dSml 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
328a3c5bd6dSspeer 		0, 15,	2, 0, "default-grp1-rdc", "default_grp1_rdc"},
329a3c5bd6dSspeer 
330846a903dSml 	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
331846a903dSml 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
332a3c5bd6dSspeer 		0, 15, 4, 0, "default-grp2-rdc", "default_grp2_rdc"},
333a3c5bd6dSspeer 
334846a903dSml 	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
335846a903dSml 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
336a3c5bd6dSspeer 		0, 15, 6, 0, "default-grp3-rdc", "default_grp3_rdc"},
337a3c5bd6dSspeer 
338846a903dSml 	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
339846a903dSml 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
340a3c5bd6dSspeer 		0, 15, 8, 0, "default-grp4-rdc", "default_grp4_rdc"},
341a3c5bd6dSspeer 
342846a903dSml 	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
343846a903dSml 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
344a3c5bd6dSspeer 		0, 15, 10, 0, "default-grp5-rdc", "default_grp5_rdc"},
345a3c5bd6dSspeer 
346846a903dSml 	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
347846a903dSml 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
348a3c5bd6dSspeer 		0, 15, 12, 0, "default-grp6-rdc", "default_grp6_rdc"},
349a3c5bd6dSspeer 
350846a903dSml 	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
351846a903dSml 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
352a3c5bd6dSspeer 		0, 15, 14, 0, "default-grp7-rdc", "default_grp7_rdc"},
353a3c5bd6dSspeer 
354a3c5bd6dSspeer 	{ nxge_param_get_rxdma_rdcgrp_info, NULL,
355846a903dSml 		NXGE_PARAM_READ | NXGE_PARAM_CMPLX | NXGE_PARAM_DONT_SHOW,
356a3c5bd6dSspeer 		0, 8, 0, 0, "rdc-groups-info", "rdc_groups_info"},
357a3c5bd6dSspeer 
358a3c5bd6dSspeer 	/* Logical device groups */
359846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
360a3c5bd6dSspeer 		0, 63, 0, 0, "start-ldg", "start_ldg"},
361a3c5bd6dSspeer 
362846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
363a3c5bd6dSspeer 		0, 64, 0, 0, "max-ldg", "max_ldg" },
364a3c5bd6dSspeer 
365a3c5bd6dSspeer 	/* MAC table information */
366a3c5bd6dSspeer 	{ nxge_param_get_mac_rdcgrp, nxge_param_set_mac_rdcgrp,
367846a903dSml 		NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW,
368a3c5bd6dSspeer 		0, 31, 0, 0, "mac-2rdc-grp", "mac_2rdc_grp"},
369a3c5bd6dSspeer 
370a3c5bd6dSspeer 	/* VLAN table information */
371a3c5bd6dSspeer 	{ nxge_param_get_vlan_rdcgrp, nxge_param_set_vlan_rdcgrp,
372846a903dSml 		NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW,
373a3c5bd6dSspeer 		0, 31, 0, 0, "vlan-2rdc-grp", "vlan_2rdc_grp"},
374a3c5bd6dSspeer 
375a3c5bd6dSspeer 	{ nxge_param_get_generic, NULL,
376846a903dSml 		NXGE_PARAM_READ_PROP | NXGE_PARAM_READ |
377846a903dSml 		NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_DONT_SHOW,
378a3c5bd6dSspeer 		0, 0x0ffff, 0x0ffff, 0, "fcram-part-cfg", "fcram_part_cfg"},
379a3c5bd6dSspeer 
380846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS |
381846a903dSml 		NXGE_PARAM_DONT_SHOW,
382a3c5bd6dSspeer 		0, 0x10, 0xa, 0, "fcram-access-ratio", "fcram_access_ratio"},
383a3c5bd6dSspeer 
384846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS |
385846a903dSml 		NXGE_PARAM_DONT_SHOW,
386a3c5bd6dSspeer 		0, 0x10, 0xa, 0, "tcam-access-ratio", "tcam_access_ratio"},
387a3c5bd6dSspeer 
388a3c5bd6dSspeer 	{ nxge_param_get_generic, nxge_param_tcam_enable,
389846a903dSml 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
390a3c5bd6dSspeer 		0, 0x1, 0x0, 0, "tcam-enable", "tcam_enable"},
391a3c5bd6dSspeer 
392a3c5bd6dSspeer 	{ nxge_param_get_generic, nxge_param_hash_lookup_enable,
393846a903dSml 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
394a3c5bd6dSspeer 		0, 0x01, 0x0, 0, "hash-lookup-enable", "hash_lookup_enable"},
395a3c5bd6dSspeer 
396a3c5bd6dSspeer 	{ nxge_param_get_generic, nxge_param_llc_snap_enable,
397846a903dSml 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
398a3c5bd6dSspeer 		0, 0x01, 0x01, 0, "llc-snap-enable", "llc_snap_enable"},
399a3c5bd6dSspeer 
400a3c5bd6dSspeer 	{ nxge_param_get_generic, nxge_param_fflp_hash_init,
401846a903dSml 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
402a3c5bd6dSspeer 		0, ALL_FF_32, ALL_FF_32, 0, "h1-init-value", "h1_init_value"},
403a3c5bd6dSspeer 
404a3c5bd6dSspeer 	{ nxge_param_get_generic,	nxge_param_fflp_hash_init,
405846a903dSml 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
406a3c5bd6dSspeer 		0, 0x0ffff, 0x0ffff, 0, "h2-init-value", "h2_init_value"},
407a3c5bd6dSspeer 
408a3c5bd6dSspeer 	{ nxge_param_get_generic, nxge_param_set_ether_usr,
409a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
410a3c5bd6dSspeer 		0, ALL_FF_32, 0x0, 0,
411a3c5bd6dSspeer 		"class-cfg-ether-usr1", "class_cfg_ether_usr1"},
412a3c5bd6dSspeer 
413a3c5bd6dSspeer 	{ nxge_param_get_generic, nxge_param_set_ether_usr,
414a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
415a3c5bd6dSspeer 		0, ALL_FF_32, 0x0, 0,
416a3c5bd6dSspeer 		"class-cfg-ether-usr2", "class_cfg_ether_usr2"},
417a3c5bd6dSspeer 
418a3c5bd6dSspeer 	{ nxge_param_get_generic, nxge_param_set_ip_usr,
419a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
420a3c5bd6dSspeer 		0, ALL_FF_32, 0x0, 0,
421a3c5bd6dSspeer 		"class-cfg-ip-usr4", "class_cfg_ip_usr4"},
422a3c5bd6dSspeer 
423a3c5bd6dSspeer 	{ nxge_param_get_generic, nxge_param_set_ip_usr,
424a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
425a3c5bd6dSspeer 		0, ALL_FF_32, 0x0, 0,
426a3c5bd6dSspeer 		"class-cfg-ip-usr5", "class_cfg_ip_usr5"},
427a3c5bd6dSspeer 
428a3c5bd6dSspeer 	{ nxge_param_get_generic, nxge_param_set_ip_usr,
429a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
430a3c5bd6dSspeer 		0, ALL_FF_32, 0x0, 0,
431a3c5bd6dSspeer 		"class-cfg-ip-usr6", "class_cfg_ip_usr6"},
432a3c5bd6dSspeer 
433a3c5bd6dSspeer 	{ nxge_param_get_generic, nxge_param_set_ip_usr,
434a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
435a3c5bd6dSspeer 		0, ALL_FF_32, 0x0, 0,
436a3c5bd6dSspeer 		"class-cfg-ip-usr7", "class_cfg_ip_usr7"},
437a3c5bd6dSspeer 
438a3c5bd6dSspeer 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
439a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
440a3c5bd6dSspeer 		0, ALL_FF_32, 0x0, 0,
441a3c5bd6dSspeer 		"class-opt-ip-usr4", "class_opt_ip_usr4"},
442a3c5bd6dSspeer 
443a3c5bd6dSspeer 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
444a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
445a3c5bd6dSspeer 		0, ALL_FF_32, 0x0, 0,
446a3c5bd6dSspeer 		"class-opt-ip-usr5", "class_opt_ip_usr5"},
447a3c5bd6dSspeer 
448a3c5bd6dSspeer 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
449a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
450a3c5bd6dSspeer 		0, ALL_FF_32, 0x0, 0,
451a3c5bd6dSspeer 		"class-opt-ip-usr6", "class_opt_ip_usr6"},
452a3c5bd6dSspeer 
453a3c5bd6dSspeer 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
454a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
455a3c5bd6dSspeer 		0, ALL_FF_32, 0x0, 0,
456a3c5bd6dSspeer 		"class-opt-ip-usr7", "class_opt_ip_usr7"},
457a3c5bd6dSspeer 
458a3c5bd6dSspeer 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
459a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS,
460a3c5bd6dSspeer 		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
461a3c5bd6dSspeer 		"class-opt-ipv4-tcp", "class_opt_ipv4_tcp"},
462a3c5bd6dSspeer 
463a3c5bd6dSspeer 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
464a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS,
465a3c5bd6dSspeer 		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
466a3c5bd6dSspeer 		"class-opt-ipv4-udp", "class_opt_ipv4_udp"},
467a3c5bd6dSspeer 
468a3c5bd6dSspeer 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
469a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS,
470a3c5bd6dSspeer 		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
471a3c5bd6dSspeer 		"class-opt-ipv4-ah", "class_opt_ipv4_ah"},
472a3c5bd6dSspeer 
473a3c5bd6dSspeer 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
474a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS,
475a3c5bd6dSspeer 		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
476a3c5bd6dSspeer 		"class-opt-ipv4-sctp", "class_opt_ipv4_sctp"},
477a3c5bd6dSspeer 
478a3c5bd6dSspeer 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS,
479a3c5bd6dSspeer 		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
480a3c5bd6dSspeer 		"class-opt-ipv6-tcp", "class_opt_ipv6_tcp"},
481a3c5bd6dSspeer 
482a3c5bd6dSspeer 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS,
483a3c5bd6dSspeer 		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
484a3c5bd6dSspeer 		"class-opt-ipv6-udp", "class_opt_ipv6_udp"},
485a3c5bd6dSspeer 
486a3c5bd6dSspeer 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS,
487a3c5bd6dSspeer 		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
488a3c5bd6dSspeer 		"class-opt-ipv6-ah", "class_opt_ipv6_ah"},
489a3c5bd6dSspeer 
490a3c5bd6dSspeer 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS,
491a3c5bd6dSspeer 		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
492a3c5bd6dSspeer 		"class-opt-ipv6-sctp",	"class_opt_ipv6_sctp"},
493a3c5bd6dSspeer 
494a3c5bd6dSspeer 	{ nxge_param_get_debug_flag, nxge_param_set_nxge_debug_flag,
495846a903dSml 		NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW,
496a3c5bd6dSspeer 		0ULL, ALL_FF_64, 0ULL, 0ULL,
497a3c5bd6dSspeer 		"nxge-debug-flag", "nxge_debug_flag"},
498a3c5bd6dSspeer 
499a3c5bd6dSspeer 	{ nxge_param_get_debug_flag, nxge_param_set_npi_debug_flag,
500846a903dSml 		NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW,
501a3c5bd6dSspeer 		0ULL, ALL_FF_64, 0ULL, 0ULL,
502a3c5bd6dSspeer 		"npi-debug-flag", "npi_debug_flag"},
503a3c5bd6dSspeer 
504846a903dSml 	{ nxge_param_dump_tdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
505a3c5bd6dSspeer 		0, 0x0fffffff, 0x0fffffff, 0, "dump-tdc", "dump_tdc"},
506a3c5bd6dSspeer 
507846a903dSml 	{ nxge_param_dump_rdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
508a3c5bd6dSspeer 		0, 0x0fffffff, 0x0fffffff, 0, "dump-rdc", "dump_rdc"},
509a3c5bd6dSspeer 
510846a903dSml 	{ nxge_param_dump_mac_regs, NULL, NXGE_PARAM_READ |
511846a903dSml 		NXGE_PARAM_DONT_SHOW,
512a3c5bd6dSspeer 		0, 0x0fffffff, 0x0fffffff, 0, "dump-mac-regs", "dump_mac_regs"},
513a3c5bd6dSspeer 
514846a903dSml 	{ nxge_param_dump_ipp_regs, NULL, NXGE_PARAM_READ |
515846a903dSml 		NXGE_PARAM_DONT_SHOW,
516a3c5bd6dSspeer 		0, 0x0fffffff, 0x0fffffff, 0, "dump-ipp-regs", "dump_ipp_regs"},
517a3c5bd6dSspeer 
518846a903dSml 	{ nxge_param_dump_fflp_regs, NULL, NXGE_PARAM_READ |
519846a903dSml 		NXGE_PARAM_DONT_SHOW,
520a3c5bd6dSspeer 		0, 0x0fffffff, 0x0fffffff, 0,
521a3c5bd6dSspeer 		"dump-fflp-regs", "dump_fflp_regs"},
522a3c5bd6dSspeer 
523846a903dSml 	{ nxge_param_dump_vlan_table, NULL, NXGE_PARAM_READ |
524846a903dSml 		NXGE_PARAM_DONT_SHOW,
525a3c5bd6dSspeer 		0, 0x0fffffff, 0x0fffffff, 0,
526a3c5bd6dSspeer 		"dump-vlan-table", "dump_vlan_table"},
527a3c5bd6dSspeer 
528846a903dSml 	{ nxge_param_dump_rdc_table, NULL, NXGE_PARAM_READ |
529846a903dSml 		NXGE_PARAM_DONT_SHOW,
530a3c5bd6dSspeer 		0, 0x0fffffff, 0x0fffffff, 0,
531a3c5bd6dSspeer 		"dump-rdc-table", "dump_rdc_table"},
532a3c5bd6dSspeer 
533846a903dSml 	{ nxge_param_dump_ptrs,	NULL, NXGE_PARAM_READ |
534846a903dSml 		NXGE_PARAM_DONT_SHOW,
535a3c5bd6dSspeer 		0, 0x0fffffff, 0x0fffffff, 0, "dump-ptrs", "dump_ptrs"},
536a3c5bd6dSspeer 
537a3c5bd6dSspeer 	{  NULL, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
538a3c5bd6dSspeer 		0, 0x0fffffff, 0x0fffffff, 0, "end", "end"},
53944961713Sgirish };
54044961713Sgirish 
541*86ef0a63SRichard Lowe extern void		*nxge_list;
54244961713Sgirish 
54344961713Sgirish void
nxge_get_param_soft_properties(p_nxge_t nxgep)54444961713Sgirish nxge_get_param_soft_properties(p_nxge_t nxgep)
54544961713Sgirish {
54644961713Sgirish 
547*86ef0a63SRichard Lowe 	p_nxge_param_t		param_arr;
548*86ef0a63SRichard Lowe 	uint_t			prop_len;
549*86ef0a63SRichard Lowe 	int			i, j;
550a3c5bd6dSspeer 	uint32_t		param_count;
551a3c5bd6dSspeer 	uint32_t		*int_prop_val;
55244961713Sgirish 
55344961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, " ==> nxge_get_param_soft_properties"));
55444961713Sgirish 
55544961713Sgirish 	param_arr = nxgep->param_arr;
55644961713Sgirish 	param_count = nxgep->param_count;
55744961713Sgirish 	for (i = 0; i < param_count; i++) {
55844961713Sgirish 		if ((param_arr[i].type & NXGE_PARAM_READ_PROP) == 0)
55944961713Sgirish 			continue;
56044961713Sgirish 		if ((param_arr[i].type & NXGE_PARAM_PROP_STR))
56144961713Sgirish 			continue;
56244961713Sgirish 		if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) ||
5634045d941Ssowmini 		    (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) {
56444961713Sgirish 			if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY,
5654045d941Ssowmini 			    nxgep->dip, 0, param_arr[i].fcode_name,
5664045d941Ssowmini 			    (int **)&int_prop_val,
5674045d941Ssowmini 			    (uint_t *)&prop_len)
5684045d941Ssowmini 			    == DDI_PROP_SUCCESS) {
56944961713Sgirish 				uint32_t *cfg_value;
57044961713Sgirish 				uint64_t prop_count;
571a3c5bd6dSspeer 
57244961713Sgirish 				if (prop_len > NXGE_PARAM_ARRAY_INIT_SIZE)
57344961713Sgirish 					prop_len = NXGE_PARAM_ARRAY_INIT_SIZE;
57444961713Sgirish 				cfg_value = (uint32_t *)param_arr[i].value;
57544961713Sgirish 				for (j = 0; j < prop_len; j++) {
57644961713Sgirish 					cfg_value[j] = int_prop_val[j];
57744961713Sgirish 				}
57844961713Sgirish 				prop_count = prop_len;
57944961713Sgirish 				param_arr[i].type |=
58044961713Sgirish 				    (prop_count << NXGE_PARAM_ARRAY_CNT_SHIFT);
58144961713Sgirish 				ddi_prop_free(int_prop_val);
58244961713Sgirish 			}
58344961713Sgirish 			continue;
58444961713Sgirish 		}
58544961713Sgirish 
58644961713Sgirish 		if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
5874045d941Ssowmini 		    param_arr[i].fcode_name,
5884045d941Ssowmini 		    (int **)&int_prop_val,
5894045d941Ssowmini 		    &prop_len) == DDI_PROP_SUCCESS) {
59044961713Sgirish 			if ((*int_prop_val >= param_arr[i].minimum) &&
5914045d941Ssowmini 			    (*int_prop_val <= param_arr[i].maximum))
59244961713Sgirish 				param_arr[i].value = *int_prop_val;
59344961713Sgirish #ifdef NXGE_DEBUG_ERROR
59444961713Sgirish 			else {
59544961713Sgirish 				NXGE_DEBUG_MSG((nxgep, OBP_CTL,
5964045d941Ssowmini 				    "nxge%d: 'prom' file parameter error\n",
5974045d941Ssowmini 				    nxgep->instance));
59844961713Sgirish 				NXGE_DEBUG_MSG((nxgep, OBP_CTL,
5994045d941Ssowmini 				    "Parameter keyword '%s'"
6004045d941Ssowmini 				    " is outside valid range\n",
6014045d941Ssowmini 				    param_arr[i].name));
60244961713Sgirish 			}
60344961713Sgirish #endif
60444961713Sgirish 			ddi_prop_free(int_prop_val);
60544961713Sgirish 		}
60644961713Sgirish 
60744961713Sgirish 		if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
6084045d941Ssowmini 		    param_arr[i].name,
6094045d941Ssowmini 		    (int **)&int_prop_val,
6104045d941Ssowmini 		    &prop_len) == DDI_PROP_SUCCESS) {
61144961713Sgirish 			if ((*int_prop_val >= param_arr[i].minimum) &&
6124045d941Ssowmini 			    (*int_prop_val <= param_arr[i].maximum))
61344961713Sgirish 				param_arr[i].value = *int_prop_val;
61444961713Sgirish #ifdef NXGE_DEBUG_ERROR
61544961713Sgirish 			else {
61644961713Sgirish 				NXGE_DEBUG_MSG((nxgep, OBP_CTL,
6174045d941Ssowmini 				    "nxge%d: 'conf' file parameter error\n",
6184045d941Ssowmini 				    nxgep->instance));
61944961713Sgirish 				NXGE_DEBUG_MSG((nxgep, OBP_CTL,
6204045d941Ssowmini 				    "Parameter keyword '%s'"
6214045d941Ssowmini 				    "is outside valid range\n",
6224045d941Ssowmini 				    param_arr[i].name));
62344961713Sgirish 			}
62444961713Sgirish #endif
62544961713Sgirish 			ddi_prop_free(int_prop_val);
62644961713Sgirish 		}
62744961713Sgirish 	}
62844961713Sgirish }
62944961713Sgirish 
63044961713Sgirish static int
nxge_private_param_register(p_nxge_t nxgep,p_nxge_param_t param_arr)63144961713Sgirish nxge_private_param_register(p_nxge_t nxgep, p_nxge_param_t param_arr)
63244961713Sgirish {
63344961713Sgirish 	int status = B_TRUE;
63444961713Sgirish 	int channel;
63544961713Sgirish 	uint8_t grp;
63644961713Sgirish 	char *prop_name;
63744961713Sgirish 	char *end;
63844961713Sgirish 	uint32_t name_chars;
63944961713Sgirish 
64044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD2_CTL,
6414045d941Ssowmini 	    "nxge_private_param_register %s", param_arr->name));
64244961713Sgirish 
64344961713Sgirish 	if ((param_arr->type & NXGE_PARAM_PRIV) != NXGE_PARAM_PRIV)
64444961713Sgirish 		return (B_TRUE);
645a3c5bd6dSspeer 
64644961713Sgirish 	prop_name =  param_arr->name;
64744961713Sgirish 	if (param_arr->type & NXGE_PARAM_RXDMA) {
64844961713Sgirish 		if (strncmp("rxdma_intr", prop_name, 10) == 0)
64944961713Sgirish 			return (B_TRUE);
65044961713Sgirish 		name_chars = strlen("default_grp");
65144961713Sgirish 		if (strncmp("default_grp", prop_name, name_chars) == 0) {
65244961713Sgirish 			prop_name += name_chars;
65344961713Sgirish 			grp = mi_strtol(prop_name, &end, 10);
65444961713Sgirish 				/* now check if this rdcgrp is in config */
65544961713Sgirish 			return (nxge_check_rdcgrp_port_member(nxgep, grp));
65644961713Sgirish 		}
65744961713Sgirish 		name_chars = strlen(prop_name);
65844961713Sgirish 		if (strncmp("default_port_rdc", prop_name, name_chars) == 0) {
65944961713Sgirish 			return (B_TRUE);
66044961713Sgirish 		}
66144961713Sgirish 		return (B_FALSE);
66244961713Sgirish 	}
66344961713Sgirish 
66444961713Sgirish 	if (param_arr->type & NXGE_PARAM_TXDMA) {
66544961713Sgirish 		name_chars = strlen("txdma");
66644961713Sgirish 		if (strncmp("txdma", prop_name, name_chars) == 0) {
66744961713Sgirish 			prop_name += name_chars;
66844961713Sgirish 			channel = mi_strtol(prop_name, &end, 10);
66944961713Sgirish 				/* now check if this rdc is in config */
67044961713Sgirish 			NXGE_DEBUG_MSG((nxgep, NDD2_CTL,
6714045d941Ssowmini 			    " nxge_private_param_register: %d",
6724045d941Ssowmini 			    channel));
67344961713Sgirish 			return (nxge_check_txdma_port_member(nxgep, channel));
67444961713Sgirish 		}
67544961713Sgirish 		return (B_FALSE);
67644961713Sgirish 	}
67744961713Sgirish 
67844961713Sgirish 	status = B_FALSE;
67944961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD2_CTL, "<== nxge_private_param_register"));
68044961713Sgirish 
68144961713Sgirish 	return (status);
68244961713Sgirish }
68344961713Sgirish 
68444961713Sgirish void
nxge_setup_param(p_nxge_t nxgep)68544961713Sgirish nxge_setup_param(p_nxge_t nxgep)
68644961713Sgirish {
68744961713Sgirish 	p_nxge_param_t param_arr;
68844961713Sgirish 	int i;
68944961713Sgirish 	pfi_t set_pfi;
69044961713Sgirish 
69144961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_setup_param"));
692a3c5bd6dSspeer 
69344961713Sgirish 	/*
69444961713Sgirish 	 * Make sure the param_instance is set to a valid device instance.
69544961713Sgirish 	 */
69644961713Sgirish 	if (nxge_param_arr[param_instance].value == 1000)
69744961713Sgirish 		nxge_param_arr[param_instance].value = nxgep->instance;
69844961713Sgirish 
69944961713Sgirish 	param_arr = nxgep->param_arr;
70044961713Sgirish 	param_arr[param_instance].value = nxgep->instance;
70144961713Sgirish 	param_arr[param_function_number].value = nxgep->function_num;
70244961713Sgirish 
70344961713Sgirish 	for (i = 0; i < nxgep->param_count; i++) {
70444961713Sgirish 		if ((param_arr[i].type & NXGE_PARAM_PRIV) &&
7054045d941Ssowmini 		    (nxge_private_param_register(nxgep,
7064045d941Ssowmini 		    &param_arr[i]) == B_FALSE)) {
70744961713Sgirish 			param_arr[i].setf = NULL;
70844961713Sgirish 			param_arr[i].getf = NULL;
70944961713Sgirish 		}
71044961713Sgirish 
71144961713Sgirish 		if (param_arr[i].type & NXGE_PARAM_CMPLX)
71244961713Sgirish 			param_arr[i].setf = NULL;
71344961713Sgirish 
71444961713Sgirish 		if (param_arr[i].type & NXGE_PARAM_DONT_SHOW) {
71544961713Sgirish 			param_arr[i].setf = NULL;
71644961713Sgirish 			param_arr[i].getf = NULL;
71744961713Sgirish 		}
71844961713Sgirish 
71944961713Sgirish 		set_pfi = (pfi_t)param_arr[i].setf;
72044961713Sgirish 
721a3c5bd6dSspeer 		if ((set_pfi) && (param_arr[i].type & NXGE_PARAM_INIT_ONLY)) {
72244961713Sgirish 			set_pfi = NULL;
72344961713Sgirish 		}
72444961713Sgirish 
72544961713Sgirish 	}
72644961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_setup_param"));
72744961713Sgirish }
72844961713Sgirish 
72944961713Sgirish void
nxge_init_param(p_nxge_t nxgep)73044961713Sgirish nxge_init_param(p_nxge_t nxgep)
73144961713Sgirish {
73244961713Sgirish 	p_nxge_param_t param_arr;
73344961713Sgirish 	int i, alloc_size;
73444961713Sgirish 	uint64_t alloc_count;
73544961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_init_param"));
73644961713Sgirish 	/*
73744961713Sgirish 	 * Make sure the param_instance is set to a valid device instance.
73844961713Sgirish 	 */
73944961713Sgirish 	if (nxge_param_arr[param_instance].value == 1000)
74044961713Sgirish 		nxge_param_arr[param_instance].value = nxgep->instance;
74144961713Sgirish 
74244961713Sgirish 	param_arr = nxgep->param_arr;
74344961713Sgirish 	if (param_arr == NULL) {
744a3c5bd6dSspeer 		param_arr = (p_nxge_param_t)
7454045d941Ssowmini 		    KMEM_ZALLOC(sizeof (nxge_param_arr), KM_SLEEP);
74644961713Sgirish 	}
747a3c5bd6dSspeer 
74844961713Sgirish 	for (i = 0; i < sizeof (nxge_param_arr)/sizeof (nxge_param_t); i++) {
74944961713Sgirish 		param_arr[i] = nxge_param_arr[i];
75044961713Sgirish 		if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) ||
7514045d941Ssowmini 		    (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) {
75244961713Sgirish 			alloc_count = NXGE_PARAM_ARRAY_INIT_SIZE;
75344961713Sgirish 			alloc_size = alloc_count * sizeof (uint64_t);
75444961713Sgirish 			param_arr[i].value =
755*86ef0a63SRichard Lowe 			    (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP);
75644961713Sgirish 			param_arr[i].old_value =
757*86ef0a63SRichard Lowe 			    (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP);
75844961713Sgirish 			param_arr[i].type |=
7594045d941Ssowmini 			    (alloc_count << NXGE_PARAM_ARRAY_ALLOC_SHIFT);
76044961713Sgirish 		}
76144961713Sgirish 	}
76244961713Sgirish 
76344961713Sgirish 	nxgep->param_arr = param_arr;
76444961713Sgirish 	nxgep->param_count = sizeof (nxge_param_arr)/sizeof (nxge_param_t);
7651bd6825cSml 
7661bd6825cSml 	nxge_param_sync(nxgep);
7671bd6825cSml 
76844961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init_param: count %d",
7694045d941Ssowmini 	    nxgep->param_count));
77044961713Sgirish }
77144961713Sgirish 
77244961713Sgirish void
nxge_destroy_param(p_nxge_t nxgep)77344961713Sgirish nxge_destroy_param(p_nxge_t nxgep)
77444961713Sgirish {
77544961713Sgirish 	int i;
77644961713Sgirish 	uint64_t free_size, free_count;
77744961713Sgirish 
77844961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_param"));
779a3c5bd6dSspeer 
78059ac0c16Sdavemq 	if (nxgep->param_arr == NULL)
78159ac0c16Sdavemq 		return;
78244961713Sgirish 	/*
78344961713Sgirish 	 * Make sure the param_instance is set to a valid device instance.
78444961713Sgirish 	 */
78544961713Sgirish 	if (nxge_param_arr[param_instance].value == nxgep->instance) {
78644961713Sgirish 		for (i = 0; i <= nxge_param_arr[param_instance].maximum; i++) {
78744961713Sgirish 			if ((ddi_get_soft_state(nxge_list, i) != NULL) &&
7884045d941Ssowmini 			    (i != nxgep->instance))
78944961713Sgirish 				break;
79044961713Sgirish 		}
79144961713Sgirish 		nxge_param_arr[param_instance].value = i;
79244961713Sgirish 	}
79344961713Sgirish 
79444961713Sgirish 	for (i = 0; i < nxgep->param_count; i++)
79544961713Sgirish 		if ((nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR32) ||
7964045d941Ssowmini 		    (nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR64)) {
79744961713Sgirish 			free_count = ((nxgep->param_arr[i].type &
7984045d941Ssowmini 			    NXGE_PARAM_ARRAY_ALLOC_MASK) >>
7994045d941Ssowmini 			    NXGE_PARAM_ARRAY_ALLOC_SHIFT);
80044961713Sgirish 			free_count = NXGE_PARAM_ARRAY_INIT_SIZE;
80144961713Sgirish 			free_size = sizeof (uint64_t) * free_count;
80244961713Sgirish 			KMEM_FREE((void *)nxgep->param_arr[i].value, free_size);
80344961713Sgirish 			KMEM_FREE((void *)nxgep->param_arr[i].old_value,
8044045d941Ssowmini 			    free_size);
80544961713Sgirish 		}
80644961713Sgirish 
80744961713Sgirish 	KMEM_FREE(nxgep->param_arr, sizeof (nxge_param_arr));
80844961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_param"));
80944961713Sgirish }
81044961713Sgirish 
81144961713Sgirish /*
81244961713Sgirish  * Extracts the value from the 'nxge' parameter array and prints the
81344961713Sgirish  * parameter value. cp points to the required parameter.
81444961713Sgirish  */
815a3c5bd6dSspeer 
81644961713Sgirish /* ARGSUSED */
81744961713Sgirish int
nxge_param_get_generic(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)81844961713Sgirish nxge_param_get_generic(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
81944961713Sgirish {
82044961713Sgirish 	p_nxge_param_t pa = (p_nxge_param_t)cp;
82144961713Sgirish 
822a3c5bd6dSspeer 	NXGE_DEBUG_MSG((nxgep, NDD_CTL,
8234045d941Ssowmini 	    "==> nxge_param_get_generic name %s ", pa->name));
82444961713Sgirish 
82544961713Sgirish 	if (pa->value > 0xffffffff)
826a3c5bd6dSspeer 		(void) mi_mpprintf(mp, "%x%x",
8274045d941Ssowmini 		    (int)(pa->value >> 32), (int)(pa->value & 0xffffffff));
82844961713Sgirish 	else
82944961713Sgirish 		(void) mi_mpprintf(mp, "%x", (int)pa->value);
83044961713Sgirish 
83144961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_generic"));
83244961713Sgirish 	return (0);
83344961713Sgirish }
83444961713Sgirish 
83544961713Sgirish /* ARGSUSED */
83644961713Sgirish static int
nxge_param_get_mac(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)83744961713Sgirish nxge_param_get_mac(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
83844961713Sgirish {
83944961713Sgirish 	p_nxge_param_t pa = (p_nxge_param_t)cp;
84044961713Sgirish 
84144961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac"));
84244961713Sgirish 
84344961713Sgirish 	(void) mi_mpprintf(mp, "%d", (uint32_t)pa->value);
84444961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_mac"));
84544961713Sgirish 	return (0);
84644961713Sgirish }
84744961713Sgirish 
84856d930aeSspeer /* ARGSUSED */
84956d930aeSspeer static int
nxge_param_get_fw_ver(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)85056d930aeSspeer nxge_param_get_fw_ver(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
85156d930aeSspeer {
85256d930aeSspeer 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_fw_ver"));
85356d930aeSspeer 
85456d930aeSspeer 	(void) mi_mpprintf(mp, "Firmware version for nxge%d:  %s\n",
85556d930aeSspeer 	    nxgep->instance, nxgep->vpd_info.ver);
85656d930aeSspeer 
85756d930aeSspeer 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_fw_ver"));
85856d930aeSspeer 	return (0);
85956d930aeSspeer }
86056d930aeSspeer 
8612e59129aSraghus /* ARGSUSED */
8622e59129aSraghus static int
nxge_param_get_port_mode(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)8632e59129aSraghus nxge_param_get_port_mode(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
8642e59129aSraghus {
8652e59129aSraghus 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_port_mode"));
8662e59129aSraghus 
8672e59129aSraghus 	switch (nxgep->mac.portmode) {
8682e59129aSraghus 	case PORT_1G_COPPER:
8692d17280bSsbehera 		(void) mi_mpprintf(mp, "Port mode for nxge%d:  1G Copper %s\n",
8702d17280bSsbehera 		    nxgep->instance,
8712d17280bSsbehera 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
8722e59129aSraghus 		break;
8732e59129aSraghus 	case PORT_1G_FIBER:
8742d17280bSsbehera 		(void) mi_mpprintf(mp, "Port mode for nxge%d:  1G Fiber %s\n",
8752d17280bSsbehera 		    nxgep->instance,
8762d17280bSsbehera 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
8772e59129aSraghus 		break;
8782e59129aSraghus 	case PORT_10G_COPPER:
8792d17280bSsbehera 		(void) mi_mpprintf(mp, "Port mode for nxge%d:  10G Copper "
8802d17280bSsbehera 		    "%s\n", nxgep->instance,
8812d17280bSsbehera 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
8822e59129aSraghus 		break;
8832e59129aSraghus 	case PORT_10G_FIBER:
8842d17280bSsbehera 		(void) mi_mpprintf(mp, "Port mode for nxge%d:  10G Fiber %s\n",
8852d17280bSsbehera 		    nxgep->instance,
8862d17280bSsbehera 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
8872e59129aSraghus 		break;
8882e59129aSraghus 	case PORT_10G_SERDES:
8892d17280bSsbehera 		(void) mi_mpprintf(mp, "Port mode for nxge%d:  10G Serdes "
8902d17280bSsbehera 		    "%s\n", nxgep->instance,
8912d17280bSsbehera 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
8922e59129aSraghus 		break;
8932e59129aSraghus 	case PORT_1G_SERDES:
8942d17280bSsbehera 		(void) mi_mpprintf(mp, "Port mode for nxge%d:  1G Serdes %s\n",
8952d17280bSsbehera 		    nxgep->instance,
8962d17280bSsbehera 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
8972e59129aSraghus 		break;
8982e59129aSraghus 	case PORT_1G_RGMII_FIBER:
8992e59129aSraghus 		(void) mi_mpprintf(mp, "Port mode for nxge%d:  1G RGMII "
9002d17280bSsbehera 		    "Fiber %s\n", nxgep->instance,
9012d17280bSsbehera 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
9022d17280bSsbehera 		break;
9032d17280bSsbehera 	case PORT_HSP_MODE:
9042d17280bSsbehera 		(void) mi_mpprintf(mp, "Port mode for nxge%d:  Hot Swappable "
9052d17280bSsbehera 		    "PHY, Currently NOT present\n", nxgep->instance);
9062e59129aSraghus 		break;
90700161856Syc 	case PORT_10G_TN1010:
90800161856Syc 		(void) mi_mpprintf(mp, "Port mode for nxge%d:"
90900161856Syc 		    " 10G Copper with TN1010 %s\n", nxgep->instance,
91000161856Syc 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
91100161856Syc 		break;
91200161856Syc 	case PORT_1G_TN1010:
913c6e5ef56Syc 		(void) mi_mpprintf(mp, "Port mode for nxge%d:"
91400161856Syc 		    " 1G Copper with TN1010 %s\n", nxgep->instance,
91500161856Syc 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
91600161856Syc 		break;
9172e59129aSraghus 	default:
9182d17280bSsbehera 		(void) mi_mpprintf(mp, "Port mode for nxge%d:  Unknown %s\n",
9192d17280bSsbehera 		    nxgep->instance,
9202d17280bSsbehera 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
9212e59129aSraghus 		break;
9222e59129aSraghus 	}
9232e59129aSraghus 
9243d16f8e7Sml 	(void) mi_mpprintf(mp, "Software LSO for nxge%d: %s\n",
9253d16f8e7Sml 	    nxgep->instance,
9263d16f8e7Sml 	    nxgep->soft_lso_enable ? "enable" : "disable");
9273d16f8e7Sml 
9282e59129aSraghus 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_port_mode"));
9292e59129aSraghus 	return (0);
9302e59129aSraghus }
9312e59129aSraghus 
932c1f9c6e5SSantwona Behera /* ARGSUSED */
933c1f9c6e5SSantwona Behera static int
nxge_param_get_rx_intr_time(p_nxge_t nxgep,queue_t * q,mblk_t * mp,caddr_t cp)934c1f9c6e5SSantwona Behera nxge_param_get_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, caddr_t cp)
935c1f9c6e5SSantwona Behera {
936c1f9c6e5SSantwona Behera 	p_nxge_param_t pa = (p_nxge_param_t)cp;
937c1f9c6e5SSantwona Behera 
938c1f9c6e5SSantwona Behera 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rx_intr_time"));
939c1f9c6e5SSantwona Behera 
940c1f9c6e5SSantwona Behera 	pa->value = (uint32_t)nxgep->intr_timeout;
941c1f9c6e5SSantwona Behera 	(void) mi_mpprintf(mp, "%d", (uint32_t)nxgep->intr_timeout);
942c1f9c6e5SSantwona Behera 
943c1f9c6e5SSantwona Behera 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rx_intr_time"));
944c1f9c6e5SSantwona Behera 	return (0);
945c1f9c6e5SSantwona Behera }
946c1f9c6e5SSantwona Behera 
947c1f9c6e5SSantwona Behera /* ARGSUSED */
948c1f9c6e5SSantwona Behera static int
nxge_param_get_rx_intr_pkts(p_nxge_t nxgep,queue_t * q,mblk_t * mp,caddr_t cp)949c1f9c6e5SSantwona Behera nxge_param_get_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, caddr_t cp)
950c1f9c6e5SSantwona Behera {
951c1f9c6e5SSantwona Behera 	p_nxge_param_t pa = (p_nxge_param_t)cp;
952c1f9c6e5SSantwona Behera 
953c1f9c6e5SSantwona Behera 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rx_intr_pkts"));
954c1f9c6e5SSantwona Behera 
955c1f9c6e5SSantwona Behera 	pa->value = (uint32_t)nxgep->intr_threshold;
956c1f9c6e5SSantwona Behera 	(void) mi_mpprintf(mp, "%d", (uint32_t)nxgep->intr_threshold);
957c1f9c6e5SSantwona Behera 
958c1f9c6e5SSantwona Behera 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rx_intr_pkts"));
959c1f9c6e5SSantwona Behera 	return (0);
960c1f9c6e5SSantwona Behera }
961c1f9c6e5SSantwona Behera 
96244961713Sgirish /* ARGSUSED */
96344961713Sgirish int
nxge_param_get_txdma_info(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)96444961713Sgirish nxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
96544961713Sgirish {
96644961713Sgirish 
967678453a8Sspeer 	uint_t print_len, buf_len;
96844961713Sgirish 	p_mblk_t np;
96944961713Sgirish 
97044961713Sgirish 	int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE;
971678453a8Sspeer 	int tdc;
972678453a8Sspeer 
973678453a8Sspeer 	nxge_grp_set_t *set;
974678453a8Sspeer 
97544961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_txdma_info"));
97644961713Sgirish 
977a3c5bd6dSspeer 	(void) mi_mpprintf(mp, "TXDMA Information for Port\t %d \n",
9784045d941Ssowmini 	    nxgep->function_num);
97944961713Sgirish 
98044961713Sgirish 	if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
98144961713Sgirish 		(void) mi_mpprintf(mp, "%s\n", "out of buffer");
98244961713Sgirish 		return (0);
98344961713Sgirish 	}
98444961713Sgirish 
98544961713Sgirish 	buf_len = buff_alloc_size;
98644961713Sgirish 	mp->b_cont = np;
987678453a8Sspeer 	print_len = 0;
98844961713Sgirish 
98944961713Sgirish 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
9904045d941Ssowmini 	    "TDC\t HW TDC\t\n");
99144961713Sgirish 	((mblk_t *)np)->b_wptr += print_len;
99244961713Sgirish 	buf_len -= print_len;
993678453a8Sspeer 
994678453a8Sspeer 	set = &nxgep->tx_set;
995da14cebeSEric Cheng 	for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) {
996678453a8Sspeer 		if ((1 << tdc) & set->owned.map) {
997678453a8Sspeer 			print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
998678453a8Sspeer 			    buf_len, "%d\n", tdc);
999678453a8Sspeer 			((mblk_t *)np)->b_wptr += print_len;
1000678453a8Sspeer 			buf_len -= print_len;
1001678453a8Sspeer 		}
100244961713Sgirish 	}
1003a3c5bd6dSspeer 
100444961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_txdma_info"));
100544961713Sgirish 	return (0);
100644961713Sgirish }
100744961713Sgirish 
100844961713Sgirish /* ARGSUSED */
100944961713Sgirish int
nxge_param_get_rxdma_info(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)101044961713Sgirish nxge_param_get_rxdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
101144961713Sgirish {
1012a3c5bd6dSspeer 	uint_t			print_len, buf_len;
1013a3c5bd6dSspeer 	p_mblk_t		np;
1014a3c5bd6dSspeer 	int			rdc;
101544961713Sgirish 	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
101644961713Sgirish 	p_nxge_hw_pt_cfg_t	p_cfgp;
1017a3c5bd6dSspeer 	int			buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE;
1018*86ef0a63SRichard Lowe 	p_rx_rcr_rings_t	rx_rcr_rings;
101944961713Sgirish 	p_rx_rcr_ring_t		*rcr_rings;
1020*86ef0a63SRichard Lowe 	p_rx_rbr_rings_t	rx_rbr_rings;
102144961713Sgirish 	p_rx_rbr_ring_t		*rbr_rings;
1022678453a8Sspeer 	nxge_grp_set_t		*set;
102344961713Sgirish 
102444961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rxdma_info"));
102544961713Sgirish 
1026a3c5bd6dSspeer 	(void) mi_mpprintf(mp, "RXDMA Information for Port\t %d \n",
10274045d941Ssowmini 	    nxgep->function_num);
102844961713Sgirish 
102944961713Sgirish 	if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
103044961713Sgirish 		/* The following may work even if we cannot get a large buf. */
103144961713Sgirish 		(void) mi_mpprintf(mp, "%s\n", "out of buffer");
103244961713Sgirish 		return (0);
103344961713Sgirish 	}
103444961713Sgirish 
103544961713Sgirish 	buf_len = buff_alloc_size;
103644961713Sgirish 	mp->b_cont = np;
103744961713Sgirish 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
103844961713Sgirish 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
103944961713Sgirish 
104044961713Sgirish 	rx_rcr_rings = nxgep->rx_rcr_rings;
104144961713Sgirish 	rcr_rings = rx_rcr_rings->rcr_rings;
104244961713Sgirish 	rx_rbr_rings = nxgep->rx_rbr_rings;
104344961713Sgirish 	rbr_rings = rx_rbr_rings->rbr_rings;
104444961713Sgirish 
104544961713Sgirish 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
10464045d941Ssowmini 	    "Total RDCs\t %d\n", p_cfgp->max_rdcs);
104744961713Sgirish 
104844961713Sgirish 	((mblk_t *)np)->b_wptr += print_len;
104944961713Sgirish 	buf_len -= print_len;
105044961713Sgirish 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
10514045d941Ssowmini 	    "RDC\t HW RDC\t Timeout\t Packets RBR ptr \t"
10524045d941Ssowmini 	    "chunks\t RCR ptr\n");
1053a3c5bd6dSspeer 
105444961713Sgirish 	((mblk_t *)np)->b_wptr += print_len;
105544961713Sgirish 	buf_len -= print_len;
1056678453a8Sspeer 
1057678453a8Sspeer 	set = &nxgep->rx_set;
1058678453a8Sspeer 	for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) {
1059678453a8Sspeer 		if ((1 << rdc) & set->owned.map) {
1060678453a8Sspeer 			print_len = snprintf((char *)
1061678453a8Sspeer 			    ((mblk_t *)np)->b_wptr, buf_len,
1062678453a8Sspeer 			    " %d\t   %x\t\t %x\t $%p\t 0x%x\t $%p\n",
1063678453a8Sspeer 			    rdc,
1064678453a8Sspeer 			    p_dma_cfgp->rcr_timeout[rdc],
1065678453a8Sspeer 			    p_dma_cfgp->rcr_threshold[rdc],
10668793b36bSNick Todd 			    (void *)rbr_rings[rdc],
10678793b36bSNick Todd 			    rbr_rings[rdc]->num_blocks, (void *)rcr_rings[rdc]);
1068a3c5bd6dSspeer 			((mblk_t *)np)->b_wptr += print_len;
1069a3c5bd6dSspeer 			buf_len -= print_len;
1070678453a8Sspeer 		}
107144961713Sgirish 	}
1072a3c5bd6dSspeer 
107344961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rxdma_info"));
107444961713Sgirish 	return (0);
107544961713Sgirish }
107644961713Sgirish 
107744961713Sgirish /* ARGSUSED */
107844961713Sgirish int
nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)107944961713Sgirish nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep, queue_t *q,
1080fe054a6cSToomas Soome     p_mblk_t mp, caddr_t cp)
108144961713Sgirish {
1082a3c5bd6dSspeer 	uint_t			print_len, buf_len;
1083a3c5bd6dSspeer 	p_mblk_t		np;
1084a3c5bd6dSspeer 	int			offset, rdc, i, rdc_grp;
108544961713Sgirish 	p_nxge_rdc_grp_t	rdc_grp_p;
108644961713Sgirish 	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
108744961713Sgirish 	p_nxge_hw_pt_cfg_t	p_cfgp;
108844961713Sgirish 
108944961713Sgirish 	int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE;
109044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL,
10914045d941Ssowmini 	    "==> nxge_param_get_rxdma_rdcgrp_info"));
109244961713Sgirish 
109344961713Sgirish 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
109444961713Sgirish 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
109544961713Sgirish 
1096a3c5bd6dSspeer 	(void) mi_mpprintf(mp, "RXDMA RDC Group Information for Port\t %d \n",
10974045d941Ssowmini 	    nxgep->function_num);
109844961713Sgirish 
1099678453a8Sspeer 	rdc_grp = p_cfgp->def_mac_rxdma_grpid;
110044961713Sgirish 	if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
110144961713Sgirish 		/* The following may work even if we cannot get a large buf. */
110244961713Sgirish 		(void) mi_mpprintf(mp, "%s\n", "out of buffer");
110344961713Sgirish 		return (0);
110444961713Sgirish 	}
110544961713Sgirish 
110644961713Sgirish 	buf_len = buff_alloc_size;
110744961713Sgirish 	mp->b_cont = np;
110844961713Sgirish 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
11094045d941Ssowmini 	    "Total RDC Groups\t %d \n"
11104045d941Ssowmini 	    "default RDC group\t %d\n",
11114045d941Ssowmini 	    p_cfgp->max_rdc_grpids,
11124045d941Ssowmini 	    p_cfgp->def_mac_rxdma_grpid);
111344961713Sgirish 
111444961713Sgirish 	((mblk_t *)np)->b_wptr += print_len;
111544961713Sgirish 	buf_len -= print_len;
111644961713Sgirish 
11177b26d9ffSSantwona Behera 	for (i = 0; i < NXGE_MAX_RDC_GROUPS; i++) {
1118678453a8Sspeer 		if (p_cfgp->grpids[i]) {
1119678453a8Sspeer 			rdc_grp_p = &p_dma_cfgp->rdc_grps[i];
112044961713Sgirish 			print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1121678453a8Sspeer 			    buf_len,
1122678453a8Sspeer 			    "\nRDC Group Info for Group [%d] %d\n"
1123678453a8Sspeer 			    "RDC Count %d\tstart RDC %d\n"
1124678453a8Sspeer 			    "RDC Group Population Information"
1125678453a8Sspeer 			    " (offsets 0 - 15)\n",
1126678453a8Sspeer 			    i, rdc_grp, rdc_grp_p->max_rdcs,
1127678453a8Sspeer 			    rdc_grp_p->start_rdc);
1128678453a8Sspeer 
1129678453a8Sspeer 			((mblk_t *)np)->b_wptr += print_len;
1130678453a8Sspeer 			buf_len -= print_len;
1131678453a8Sspeer 			print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1132678453a8Sspeer 			    buf_len, "\n");
1133678453a8Sspeer 			((mblk_t *)np)->b_wptr += print_len;
1134678453a8Sspeer 			buf_len -= print_len;
1135678453a8Sspeer 
1136678453a8Sspeer 			for (rdc = 0; rdc < rdc_grp_p->max_rdcs; rdc++) {
1137678453a8Sspeer 				print_len = snprintf(
11384045d941Ssowmini 				    (char *)((mblk_t *)np)->b_wptr,
11394045d941Ssowmini 				    buf_len, "[%d]=%d ", rdc,
1140