144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 227b26d9ffSSantwona Behera * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 2344961713Sgirish * Use is subject to license terms. 2444961713Sgirish */ 2544961713Sgirish 2644961713Sgirish #include <sys/nxge/nxge_impl.h> 27678453a8Sspeer #include <sys/nxge/nxge_hio.h> 28678453a8Sspeer 2944961713Sgirish #include <inet/common.h> 3044961713Sgirish #include <inet/mi.h> 3144961713Sgirish #include <inet/nd.h> 3244961713Sgirish 3344961713Sgirish extern uint64_t npi_debug_level; 3444961713Sgirish 35a3c5bd6dSspeer #define NXGE_PARAM_MAC_RW \ 36a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_MAC | \ 3744961713Sgirish NXGE_PARAM_NDD_WR_OK | NXGE_PARAM_READ_PROP 3844961713Sgirish 39a3c5bd6dSspeer #define NXGE_PARAM_MAC_DONT_SHOW \ 40a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_MAC | NXGE_PARAM_DONT_SHOW 4144961713Sgirish 42a3c5bd6dSspeer #define NXGE_PARAM_RXDMA_RW \ 43a3c5bd6dSspeer NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_NDD_WR_OK | \ 44a3c5bd6dSspeer NXGE_PARAM_READ_PROP 4544961713Sgirish 46a3c5bd6dSspeer #define NXGE_PARAM_RXDMA_RWC \ 47a3c5bd6dSspeer NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_INIT_ONLY | \ 48a3c5bd6dSspeer NXGE_PARAM_READ_PROP 4944961713Sgirish 50a3c5bd6dSspeer #define NXGE_PARAM_L2CLASS_CFG \ 51a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_READ_PROP | \ 52a3c5bd6dSspeer NXGE_PARAM_NDD_WR_OK 5344961713Sgirish 54a3c5bd6dSspeer #define NXGE_PARAM_CLASS_RWS \ 55a3c5bd6dSspeer NXGE_PARAM_RWS | NXGE_PARAM_READ_PROP 5644961713Sgirish 5744961713Sgirish #define NXGE_PARAM_ARRAY_INIT_SIZE 0x20ULL 5844961713Sgirish 5944961713Sgirish #define SET_RX_INTR_TIME_DISABLE 0 6044961713Sgirish #define SET_RX_INTR_TIME_ENABLE 1 6144961713Sgirish #define SET_RX_INTR_PKTS 2 6244961713Sgirish 6344961713Sgirish #define BASE_ANY 0 64a3c5bd6dSspeer #define BASE_BINARY 2 6544961713Sgirish #define BASE_HEX 16 6644961713Sgirish #define BASE_DECIMAL 10 6744961713Sgirish #define ALL_FF_64 0xFFFFFFFFFFFFFFFFULL 6844961713Sgirish #define ALL_FF_32 0xFFFFFFFFUL 6944961713Sgirish 7044961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_SIZE 2048 /* is 2k enough? */ 7144961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_8K 8192 7244961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_16K 0x2000 7344961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_64K 0x8000 7444961713Sgirish 7544961713Sgirish #define PARAM_OUTOF_RANGE(vptr, eptr, rval, pa) \ 7644961713Sgirish ((vptr == eptr) || (rval < pa->minimum) || (rval > pa->maximum)) 7744961713Sgirish 7844961713Sgirish #define ADVANCE_PRINT_BUFFER(pmp, plen, rlen) { \ 7944961713Sgirish ((mblk_t *)pmp)->b_wptr += plen; \ 8044961713Sgirish rlen -= plen; \ 81a3c5bd6dSspeer } 8244961713Sgirish 834045d941Ssowmini int nxge_param_set_mac(p_nxge_t, queue_t *, 84a3c5bd6dSspeer mblk_t *, char *, caddr_t); 8544961713Sgirish static int nxge_param_set_port_rdc(p_nxge_t, queue_t *, 86a3c5bd6dSspeer mblk_t *, char *, caddr_t); 8744961713Sgirish static int nxge_param_set_grp_rdc(p_nxge_t, queue_t *, 88a3c5bd6dSspeer mblk_t *, char *, caddr_t); 8944961713Sgirish static int nxge_param_set_ether_usr(p_nxge_t, 90a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 9144961713Sgirish static int nxge_param_set_ip_usr(p_nxge_t, 92a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 9344961713Sgirish static int nxge_param_set_vlan_rdcgrp(p_nxge_t, 94a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 9544961713Sgirish static int nxge_param_set_mac_rdcgrp(p_nxge_t, 96a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 9744961713Sgirish static int nxge_param_fflp_hash_init(p_nxge_t, 98a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 9944961713Sgirish static int nxge_param_llc_snap_enable(p_nxge_t, queue_t *, 100a3c5bd6dSspeer mblk_t *, char *, caddr_t); 10144961713Sgirish static int nxge_param_hash_lookup_enable(p_nxge_t, queue_t *, 102a3c5bd6dSspeer mblk_t *, char *, caddr_t); 10344961713Sgirish static int nxge_param_tcam_enable(p_nxge_t, queue_t *, 104a3c5bd6dSspeer mblk_t *, char *, caddr_t); 10556d930aeSspeer static int nxge_param_get_fw_ver(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 1062e59129aSraghus static int nxge_param_get_port_mode(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 10744961713Sgirish static int nxge_param_get_rxdma_info(p_nxge_t, queue_t *q, 108a3c5bd6dSspeer p_mblk_t, caddr_t); 10944961713Sgirish static int nxge_param_get_txdma_info(p_nxge_t, queue_t *q, 110a3c5bd6dSspeer p_mblk_t, caddr_t); 11144961713Sgirish static int nxge_param_get_vlan_rdcgrp(p_nxge_t, queue_t *, 112a3c5bd6dSspeer p_mblk_t, caddr_t); 11344961713Sgirish static int nxge_param_get_mac_rdcgrp(p_nxge_t, queue_t *, 114a3c5bd6dSspeer p_mblk_t, caddr_t); 11544961713Sgirish static int nxge_param_get_rxdma_rdcgrp_info(p_nxge_t, queue_t *, 116a3c5bd6dSspeer p_mblk_t, caddr_t); 117*c1f9c6e5SSantwona Behera static int nxge_param_get_rx_intr_time(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 118*c1f9c6e5SSantwona Behera static int nxge_param_get_rx_intr_pkts(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 11944961713Sgirish static int nxge_param_get_ip_opt(p_nxge_t, queue_t *, mblk_t *, caddr_t); 120a3c5bd6dSspeer static int nxge_param_get_mac(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 12144961713Sgirish static int nxge_param_get_debug_flag(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 12244961713Sgirish static int nxge_param_set_nxge_debug_flag(p_nxge_t, queue_t *, mblk_t *, 123a3c5bd6dSspeer char *, caddr_t); 12444961713Sgirish static int nxge_param_set_npi_debug_flag(p_nxge_t, 125a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 12644961713Sgirish static int nxge_param_dump_rdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 12744961713Sgirish static int nxge_param_dump_tdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 12844961713Sgirish static int nxge_param_dump_mac_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 12944961713Sgirish static int nxge_param_dump_ipp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13044961713Sgirish static int nxge_param_dump_fflp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13144961713Sgirish static int nxge_param_dump_vlan_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13244961713Sgirish static int nxge_param_dump_rdc_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13344961713Sgirish static int nxge_param_dump_ptrs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 1341bd6825cSml static void nxge_param_sync(p_nxge_t); 13544961713Sgirish 13644961713Sgirish /* 13744961713Sgirish * Global array of Neptune changable parameters. 13844961713Sgirish * This array is initialized to correspond to the default 13944961713Sgirish * Neptune 4 port configuration. This array would be copied 14044961713Sgirish * into each port's parameter structure and modifed per 14144961713Sgirish * fcode and nxge.conf configuration. Later, the parameters are 14244961713Sgirish * exported to ndd to display and run-time configuration (at least 14344961713Sgirish * some of them). 14444961713Sgirish * 14500161856Syc * Parameters with DONT_SHOW are not shown by ndd. 14600161856Syc * 14744961713Sgirish */ 14844961713Sgirish 149a3c5bd6dSspeer static nxge_param_t nxge_param_arr[] = { 150a3c5bd6dSspeer /* 151a3c5bd6dSspeer * min max value old hw-name conf-name 152a3c5bd6dSspeer */ 153846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 154a3c5bd6dSspeer 0, 999, 1000, 0, "instance", "instance"}, 155a3c5bd6dSspeer 156846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 157a3c5bd6dSspeer 0, 999, 1000, 0, "main-instance", "main_instance"}, 158a3c5bd6dSspeer 159a3c5bd6dSspeer { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 160a3c5bd6dSspeer 0, 3, 0, 0, "function-number", "function_number"}, 161a3c5bd6dSspeer 162a3c5bd6dSspeer /* Partition Id */ 163846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 164a3c5bd6dSspeer 0, 8, 0, 0, "partition-id", "partition_id"}, 165a3c5bd6dSspeer 166a3c5bd6dSspeer /* Read Write Permission Mode */ 167846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 168a3c5bd6dSspeer 0, 2, 0, 0, "read-write-mode", "read_write_mode"}, 169a3c5bd6dSspeer 17056d930aeSspeer { nxge_param_get_fw_ver, NULL, NXGE_PARAM_READ, 17156d930aeSspeer 0, 32, 0, 0, "version", "fw_version"}, 17256d930aeSspeer 1732e59129aSraghus { nxge_param_get_port_mode, NULL, NXGE_PARAM_READ, 1742e59129aSraghus 0, 32, 0, 0, "port-mode", "port_mode"}, 1752e59129aSraghus 176a3c5bd6dSspeer /* hw cfg types */ 177a3c5bd6dSspeer /* control the DMA config of Neptune/NIU */ 178846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 179a3c5bd6dSspeer CFG_DEFAULT, CFG_CUSTOM, CFG_DEFAULT, CFG_DEFAULT, 180a3c5bd6dSspeer "niu-cfg-type", "niu_cfg_type"}, 181a3c5bd6dSspeer 182a3c5bd6dSspeer /* control the TXDMA config of the Port controlled by tx-quick-cfg */ 183846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 184a3c5bd6dSspeer CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 185a3c5bd6dSspeer "tx-qcfg-type", "tx_qcfg_type"}, 186a3c5bd6dSspeer 187a3c5bd6dSspeer /* control the RXDMA config of the Port controlled by rx-quick-cfg */ 188846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 189a3c5bd6dSspeer CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 190a3c5bd6dSspeer "rx-qcfg-type", "rx_qcfg_type"}, 191a3c5bd6dSspeer 192a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, 193a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 194a3c5bd6dSspeer 0, 1, 0, 0, "master-cfg-enable", "master_cfg_enable"}, 195a3c5bd6dSspeer 196a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, 197846a903dSml NXGE_PARAM_DONT_SHOW, 198a3c5bd6dSspeer 0, 1, 0, 0, "master-cfg-value", "master_cfg_value"}, 199a3c5bd6dSspeer 200a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 201a3c5bd6dSspeer 0, 1, 1, 1, "adv-autoneg-cap", "adv_autoneg_cap"}, 202a3c5bd6dSspeer 203a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 204a3c5bd6dSspeer 0, 1, 1, 1, "adv-10gfdx-cap", "adv_10gfdx_cap"}, 205a3c5bd6dSspeer 206a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 207a3c5bd6dSspeer 0, 1, 0, 0, "adv-10ghdx-cap", "adv_10ghdx_cap"}, 208a3c5bd6dSspeer 209a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 210a3c5bd6dSspeer 0, 1, 1, 1, "adv-1000fdx-cap", "adv_1000fdx_cap"}, 211a3c5bd6dSspeer 212a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 213a3c5bd6dSspeer 0, 1, 0, 0, "adv-1000hdx-cap", "adv_1000hdx_cap"}, 214a3c5bd6dSspeer 215a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 216a3c5bd6dSspeer 0, 1, 0, 0, "adv-100T4-cap", "adv_100T4_cap"}, 217a3c5bd6dSspeer 218a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 219a3c5bd6dSspeer 0, 1, 1, 1, "adv-100fdx-cap", "adv_100fdx_cap"}, 220a3c5bd6dSspeer 221a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 222a3c5bd6dSspeer 0, 1, 0, 0, "adv-100hdx-cap", "adv_100hdx_cap"}, 223a3c5bd6dSspeer 224a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 225a3c5bd6dSspeer 0, 1, 1, 1, "adv-10fdx-cap", "adv_10fdx_cap"}, 226a3c5bd6dSspeer 227a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 228a3c5bd6dSspeer 0, 1, 0, 0, "adv-10hdx-cap", "adv_10hdx_cap"}, 229a3c5bd6dSspeer 230846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 231a3c5bd6dSspeer 0, 1, 0, 0, "adv-asmpause-cap", "adv_asmpause_cap"}, 232a3c5bd6dSspeer 233a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 234a3c5bd6dSspeer 0, 1, 0, 0, "adv-pause-cap", "adv_pause_cap"}, 235a3c5bd6dSspeer 236846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 237a3c5bd6dSspeer 0, 1, 0, 0, "use-int-xcvr", "use_int_xcvr"}, 238a3c5bd6dSspeer 239846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 240a3c5bd6dSspeer 0, 1, 1, 1, "enable-ipg0", "enable_ipg0"}, 241a3c5bd6dSspeer 242846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 243a3c5bd6dSspeer 0, 255, 8, 8, "ipg0", "ipg0"}, 244a3c5bd6dSspeer 245846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 246a3c5bd6dSspeer 0, 255, 8, 8, "ipg1", "ipg1"}, 247a3c5bd6dSspeer 248846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 249a3c5bd6dSspeer 0, 255, 4, 4, "ipg2", "ipg2"}, 250a3c5bd6dSspeer 251a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 252a3c5bd6dSspeer 0, 1, 0, 0, "accept-jumbo", "accept_jumbo"}, 253a3c5bd6dSspeer 254a3c5bd6dSspeer /* Transmit DMA channels */ 255846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 256846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 257a3c5bd6dSspeer 0, 3, 0, 0, "tx-dma-weight", "tx_dma_weight"}, 258a3c5bd6dSspeer 259846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 260846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 261a3c5bd6dSspeer 0, 31, 0, 0, "tx-dma-channels-begin", "tx_dma_channels_begin"}, 262a3c5bd6dSspeer 263846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 264846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 265a3c5bd6dSspeer 0, 32, 0, 0, "tx-dma-channels", "tx_dma_channels"}, 266a3c5bd6dSspeer { nxge_param_get_txdma_info, NULL, 267846a903dSml NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 268a3c5bd6dSspeer 0, 32, 0, 0, "tx-dma-info", "tx_dma_info"}, 269a3c5bd6dSspeer 270a3c5bd6dSspeer /* Receive DMA channels */ 271a3c5bd6dSspeer { nxge_param_get_generic, NULL, 272846a903dSml NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 273a3c5bd6dSspeer 0, 31, 0, 0, "rx-dma-channels-begin", "rx_dma_channels_begin"}, 274a3c5bd6dSspeer 275846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 276846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 277a3c5bd6dSspeer 0, 32, 0, 0, "rx-dma-channels", "rx_dma_channels"}, 278a3c5bd6dSspeer 279846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 280846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 281a3c5bd6dSspeer 0, 65535, PT_DRR_WT_DEFAULT_10G, 0, 282a3c5bd6dSspeer "rx-drr-weight", "rx_drr_weight"}, 283a3c5bd6dSspeer 284846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 285846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 286a3c5bd6dSspeer 0, 1, 1, 0, "rx-full-header", "rx_full_header"}, 287a3c5bd6dSspeer 288846a903dSml { nxge_param_get_rxdma_info, NULL, NXGE_PARAM_READ | 289846a903dSml NXGE_PARAM_DONT_SHOW, 290a3c5bd6dSspeer 0, 32, 0, 0, "rx-dma-info", "rx_dma_info"}, 291a3c5bd6dSspeer 292a3c5bd6dSspeer { nxge_param_get_rxdma_info, NULL, 293a3c5bd6dSspeer NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 294a3c5bd6dSspeer NXGE_RBR_RBB_MIN, NXGE_RBR_RBB_MAX, NXGE_RBR_RBB_DEFAULT, 0, 295a3c5bd6dSspeer "rx-rbr-size", "rx_rbr_size"}, 296a3c5bd6dSspeer 297a3c5bd6dSspeer { nxge_param_get_rxdma_info, NULL, 298a3c5bd6dSspeer NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 299a3c5bd6dSspeer NXGE_RCR_MIN, NXGE_RCR_MAX, NXGE_RCR_DEFAULT, 0, 300a3c5bd6dSspeer "rx-rcr-size", "rx_rcr_size"}, 301a3c5bd6dSspeer 302846a903dSml { nxge_param_get_generic, nxge_param_set_port_rdc, 303846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 304a3c5bd6dSspeer 0, 15, 0, 0, "default-port-rdc", "default_port_rdc"}, 305a3c5bd6dSspeer 306*c1f9c6e5SSantwona Behera { nxge_param_get_rx_intr_time, nxge_param_rx_intr_time, 307*c1f9c6e5SSantwona Behera NXGE_PARAM_RXDMA_RW, 308a3c5bd6dSspeer NXGE_RDC_RCR_TIMEOUT_MIN, NXGE_RDC_RCR_TIMEOUT_MAX, 3097b26d9ffSSantwona Behera NXGE_RDC_RCR_TIMEOUT, 0, "rxdma-intr-time", "rxdma_intr_time"}, 310a3c5bd6dSspeer 311*c1f9c6e5SSantwona Behera { nxge_param_get_rx_intr_pkts, nxge_param_rx_intr_pkts, 312*c1f9c6e5SSantwona Behera NXGE_PARAM_RXDMA_RW, 313a3c5bd6dSspeer NXGE_RDC_RCR_THRESHOLD_MIN, NXGE_RDC_RCR_THRESHOLD_MAX, 3147b26d9ffSSantwona Behera NXGE_RDC_RCR_THRESHOLD, 0, 315a3c5bd6dSspeer "rxdma-intr-pkts", "rxdma_intr_pkts"}, 316a3c5bd6dSspeer 317846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 318846a903dSml NXGE_PARAM_DONT_SHOW, 319a3c5bd6dSspeer 0, 8, 0, 0, "rx-rdc-grps-begin", "rx_rdc_grps_begin"}, 320a3c5bd6dSspeer 321846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 322846a903dSml NXGE_PARAM_DONT_SHOW, 323a3c5bd6dSspeer 0, 8, 0, 0, "rx-rdc-grps", "rx_rdc_grps"}, 324a3c5bd6dSspeer 325846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 326846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 327a3c5bd6dSspeer 0, 15, 0, 0, "default-grp0-rdc", "default_grp0_rdc"}, 328a3c5bd6dSspeer 329846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 330846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 331a3c5bd6dSspeer 0, 15, 2, 0, "default-grp1-rdc", "default_grp1_rdc"}, 332a3c5bd6dSspeer 333846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 334846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 335a3c5bd6dSspeer 0, 15, 4, 0, "default-grp2-rdc", "default_grp2_rdc"}, 336a3c5bd6dSspeer 337846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 338846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 339a3c5bd6dSspeer 0, 15, 6, 0, "default-grp3-rdc", "default_grp3_rdc"}, 340a3c5bd6dSspeer 341846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 342846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 343a3c5bd6dSspeer 0, 15, 8, 0, "default-grp4-rdc", "default_grp4_rdc"}, 344a3c5bd6dSspeer 345846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 346846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 347a3c5bd6dSspeer 0, 15, 10, 0, "default-grp5-rdc", "default_grp5_rdc"}, 348a3c5bd6dSspeer 349846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 350846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 351a3c5bd6dSspeer 0, 15, 12, 0, "default-grp6-rdc", "default_grp6_rdc"}, 352a3c5bd6dSspeer 353846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 354846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 355a3c5bd6dSspeer 0, 15, 14, 0, "default-grp7-rdc", "default_grp7_rdc"}, 356a3c5bd6dSspeer 357a3c5bd6dSspeer { nxge_param_get_rxdma_rdcgrp_info, NULL, 358846a903dSml NXGE_PARAM_READ | NXGE_PARAM_CMPLX | NXGE_PARAM_DONT_SHOW, 359a3c5bd6dSspeer 0, 8, 0, 0, "rdc-groups-info", "rdc_groups_info"}, 360a3c5bd6dSspeer 361a3c5bd6dSspeer /* Logical device groups */ 362846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 363a3c5bd6dSspeer 0, 63, 0, 0, "start-ldg", "start_ldg"}, 364a3c5bd6dSspeer 365846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 366a3c5bd6dSspeer 0, 64, 0, 0, "max-ldg", "max_ldg" }, 367a3c5bd6dSspeer 368a3c5bd6dSspeer /* MAC table information */ 369a3c5bd6dSspeer { nxge_param_get_mac_rdcgrp, nxge_param_set_mac_rdcgrp, 370846a903dSml NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 371a3c5bd6dSspeer 0, 31, 0, 0, "mac-2rdc-grp", "mac_2rdc_grp"}, 372a3c5bd6dSspeer 373a3c5bd6dSspeer /* VLAN table information */ 374a3c5bd6dSspeer { nxge_param_get_vlan_rdcgrp, nxge_param_set_vlan_rdcgrp, 375846a903dSml NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 376a3c5bd6dSspeer 0, 31, 0, 0, "vlan-2rdc-grp", "vlan_2rdc_grp"}, 377a3c5bd6dSspeer 378a3c5bd6dSspeer { nxge_param_get_generic, NULL, 379846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_READ | 380846a903dSml NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_DONT_SHOW, 381a3c5bd6dSspeer 0, 0x0ffff, 0x0ffff, 0, "fcram-part-cfg", "fcram_part_cfg"}, 382a3c5bd6dSspeer 383846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 384846a903dSml NXGE_PARAM_DONT_SHOW, 385a3c5bd6dSspeer 0, 0x10, 0xa, 0, "fcram-access-ratio", "fcram_access_ratio"}, 386a3c5bd6dSspeer 387846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 388846a903dSml NXGE_PARAM_DONT_SHOW, 389a3c5bd6dSspeer 0, 0x10, 0xa, 0, "tcam-access-ratio", "tcam_access_ratio"}, 390a3c5bd6dSspeer 391a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_tcam_enable, 392846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 393a3c5bd6dSspeer 0, 0x1, 0x0, 0, "tcam-enable", "tcam_enable"}, 394a3c5bd6dSspeer 395a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_hash_lookup_enable, 396846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 397a3c5bd6dSspeer 0, 0x01, 0x0, 0, "hash-lookup-enable", "hash_lookup_enable"}, 398a3c5bd6dSspeer 399a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_llc_snap_enable, 400846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 401a3c5bd6dSspeer 0, 0x01, 0x01, 0, "llc-snap-enable", "llc_snap_enable"}, 402a3c5bd6dSspeer 403a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_fflp_hash_init, 404846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 405a3c5bd6dSspeer 0, ALL_FF_32, ALL_FF_32, 0, "h1-init-value", "h1_init_value"}, 406a3c5bd6dSspeer 407a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_fflp_hash_init, 408846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 409a3c5bd6dSspeer 0, 0x0ffff, 0x0ffff, 0, "h2-init-value", "h2_init_value"}, 410a3c5bd6dSspeer 411a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ether_usr, 412a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 413a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 414a3c5bd6dSspeer "class-cfg-ether-usr1", "class_cfg_ether_usr1"}, 415a3c5bd6dSspeer 416a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ether_usr, 417a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 418a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 419a3c5bd6dSspeer "class-cfg-ether-usr2", "class_cfg_ether_usr2"}, 420a3c5bd6dSspeer 421a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 422a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 423a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 424a3c5bd6dSspeer "class-cfg-ip-usr4", "class_cfg_ip_usr4"}, 425a3c5bd6dSspeer 426a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 427a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 428a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 429a3c5bd6dSspeer "class-cfg-ip-usr5", "class_cfg_ip_usr5"}, 430a3c5bd6dSspeer 431a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 432a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 433a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 434a3c5bd6dSspeer "class-cfg-ip-usr6", "class_cfg_ip_usr6"}, 435a3c5bd6dSspeer 436a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 437a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 438a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 439a3c5bd6dSspeer "class-cfg-ip-usr7", "class_cfg_ip_usr7"}, 440a3c5bd6dSspeer 441a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 442a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 443a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 444a3c5bd6dSspeer "class-opt-ip-usr4", "class_opt_ip_usr4"}, 445a3c5bd6dSspeer 446a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 447a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 448a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 449a3c5bd6dSspeer "class-opt-ip-usr5", "class_opt_ip_usr5"}, 450a3c5bd6dSspeer 451a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 452a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 453a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 454a3c5bd6dSspeer "class-opt-ip-usr6", "class_opt_ip_usr6"}, 455a3c5bd6dSspeer 456a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 457a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 458a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 459a3c5bd6dSspeer "class-opt-ip-usr7", "class_opt_ip_usr7"}, 460a3c5bd6dSspeer 461a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 462a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 463a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 464a3c5bd6dSspeer "class-opt-ipv4-tcp", "class_opt_ipv4_tcp"}, 465a3c5bd6dSspeer 466a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 467a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 468a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 469a3c5bd6dSspeer "class-opt-ipv4-udp", "class_opt_ipv4_udp"}, 470a3c5bd6dSspeer 471a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 472a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 473a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 474a3c5bd6dSspeer "class-opt-ipv4-ah", "class_opt_ipv4_ah"}, 475a3c5bd6dSspeer 476a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 477a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 478a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 479a3c5bd6dSspeer "class-opt-ipv4-sctp", "class_opt_ipv4_sctp"}, 480a3c5bd6dSspeer 481a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 482a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 483a3c5bd6dSspeer "class-opt-ipv6-tcp", "class_opt_ipv6_tcp"}, 484a3c5bd6dSspeer 485a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 486a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 487a3c5bd6dSspeer "class-opt-ipv6-udp", "class_opt_ipv6_udp"}, 488a3c5bd6dSspeer 489a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 490a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 491a3c5bd6dSspeer "class-opt-ipv6-ah", "class_opt_ipv6_ah"}, 492a3c5bd6dSspeer 493a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 494a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 495a3c5bd6dSspeer "class-opt-ipv6-sctp", "class_opt_ipv6_sctp"}, 496a3c5bd6dSspeer 497a3c5bd6dSspeer { nxge_param_get_debug_flag, nxge_param_set_nxge_debug_flag, 498846a903dSml NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 499a3c5bd6dSspeer 0ULL, ALL_FF_64, 0ULL, 0ULL, 500a3c5bd6dSspeer "nxge-debug-flag", "nxge_debug_flag"}, 501a3c5bd6dSspeer 502a3c5bd6dSspeer { nxge_param_get_debug_flag, nxge_param_set_npi_debug_flag, 503846a903dSml NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 504a3c5bd6dSspeer 0ULL, ALL_FF_64, 0ULL, 0ULL, 505a3c5bd6dSspeer "npi-debug-flag", "npi_debug_flag"}, 506a3c5bd6dSspeer 507846a903dSml { nxge_param_dump_tdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 508a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-tdc", "dump_tdc"}, 509a3c5bd6dSspeer 510846a903dSml { nxge_param_dump_rdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 511a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-rdc", "dump_rdc"}, 512a3c5bd6dSspeer 513846a903dSml { nxge_param_dump_mac_regs, NULL, NXGE_PARAM_READ | 514846a903dSml NXGE_PARAM_DONT_SHOW, 515a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-mac-regs", "dump_mac_regs"}, 516a3c5bd6dSspeer 517846a903dSml { nxge_param_dump_ipp_regs, NULL, NXGE_PARAM_READ | 518846a903dSml NXGE_PARAM_DONT_SHOW, 519a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-ipp-regs", "dump_ipp_regs"}, 520a3c5bd6dSspeer 521846a903dSml { nxge_param_dump_fflp_regs, NULL, NXGE_PARAM_READ | 522846a903dSml NXGE_PARAM_DONT_SHOW, 523a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, 524a3c5bd6dSspeer "dump-fflp-regs", "dump_fflp_regs"}, 525a3c5bd6dSspeer 526846a903dSml { nxge_param_dump_vlan_table, NULL, NXGE_PARAM_READ | 527846a903dSml NXGE_PARAM_DONT_SHOW, 528a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, 529a3c5bd6dSspeer "dump-vlan-table", "dump_vlan_table"}, 530a3c5bd6dSspeer 531846a903dSml { nxge_param_dump_rdc_table, NULL, NXGE_PARAM_READ | 532846a903dSml NXGE_PARAM_DONT_SHOW, 533a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, 534a3c5bd6dSspeer "dump-rdc-table", "dump_rdc_table"}, 535a3c5bd6dSspeer 536846a903dSml { nxge_param_dump_ptrs, NULL, NXGE_PARAM_READ | 537846a903dSml NXGE_PARAM_DONT_SHOW, 538a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-ptrs", "dump_ptrs"}, 539a3c5bd6dSspeer 540a3c5bd6dSspeer { NULL, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 541a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "end", "end"}, 54244961713Sgirish }; 54344961713Sgirish 54444961713Sgirish extern void *nxge_list; 54544961713Sgirish 54644961713Sgirish void 54744961713Sgirish nxge_get_param_soft_properties(p_nxge_t nxgep) 54844961713Sgirish { 54944961713Sgirish 55044961713Sgirish p_nxge_param_t param_arr; 55144961713Sgirish uint_t prop_len; 55244961713Sgirish int i, j; 553a3c5bd6dSspeer uint32_t param_count; 554a3c5bd6dSspeer uint32_t *int_prop_val; 55544961713Sgirish 55644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, " ==> nxge_get_param_soft_properties")); 55744961713Sgirish 55844961713Sgirish param_arr = nxgep->param_arr; 55944961713Sgirish param_count = nxgep->param_count; 56044961713Sgirish for (i = 0; i < param_count; i++) { 56144961713Sgirish if ((param_arr[i].type & NXGE_PARAM_READ_PROP) == 0) 56244961713Sgirish continue; 56344961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PROP_STR)) 56444961713Sgirish continue; 56544961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 5664045d941Ssowmini (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 56744961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 5684045d941Ssowmini nxgep->dip, 0, param_arr[i].fcode_name, 5694045d941Ssowmini (int **)&int_prop_val, 5704045d941Ssowmini (uint_t *)&prop_len) 5714045d941Ssowmini == DDI_PROP_SUCCESS) { 57244961713Sgirish uint32_t *cfg_value; 57344961713Sgirish uint64_t prop_count; 574a3c5bd6dSspeer 57544961713Sgirish if (prop_len > NXGE_PARAM_ARRAY_INIT_SIZE) 57644961713Sgirish prop_len = NXGE_PARAM_ARRAY_INIT_SIZE; 577adfcba55Sjoycey #if defined(__i386) 578adfcba55Sjoycey cfg_value = 5794045d941Ssowmini (uint32_t *)(int32_t)param_arr[i].value; 580adfcba55Sjoycey #else 58144961713Sgirish cfg_value = (uint32_t *)param_arr[i].value; 582adfcba55Sjoycey #endif 58344961713Sgirish for (j = 0; j < prop_len; j++) { 58444961713Sgirish cfg_value[j] = int_prop_val[j]; 58544961713Sgirish } 58644961713Sgirish prop_count = prop_len; 58744961713Sgirish param_arr[i].type |= 58844961713Sgirish (prop_count << NXGE_PARAM_ARRAY_CNT_SHIFT); 58944961713Sgirish ddi_prop_free(int_prop_val); 59044961713Sgirish } 59144961713Sgirish continue; 59244961713Sgirish } 59344961713Sgirish 59444961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 5954045d941Ssowmini param_arr[i].fcode_name, 5964045d941Ssowmini (int **)&int_prop_val, 5974045d941Ssowmini &prop_len) == DDI_PROP_SUCCESS) { 59844961713Sgirish if ((*int_prop_val >= param_arr[i].minimum) && 5994045d941Ssowmini (*int_prop_val <= param_arr[i].maximum)) 60044961713Sgirish param_arr[i].value = *int_prop_val; 60144961713Sgirish #ifdef NXGE_DEBUG_ERROR 60244961713Sgirish else { 60344961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 6044045d941Ssowmini "nxge%d: 'prom' file parameter error\n", 6054045d941Ssowmini nxgep->instance)); 60644961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 6074045d941Ssowmini "Parameter keyword '%s'" 6084045d941Ssowmini " is outside valid range\n", 6094045d941Ssowmini param_arr[i].name)); 61044961713Sgirish } 61144961713Sgirish #endif 61244961713Sgirish ddi_prop_free(int_prop_val); 61344961713Sgirish } 61444961713Sgirish 61544961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 6164045d941Ssowmini param_arr[i].name, 6174045d941Ssowmini (int **)&int_prop_val, 6184045d941Ssowmini &prop_len) == DDI_PROP_SUCCESS) { 61944961713Sgirish if ((*int_prop_val >= param_arr[i].minimum) && 6204045d941Ssowmini (*int_prop_val <= param_arr[i].maximum)) 62144961713Sgirish param_arr[i].value = *int_prop_val; 62244961713Sgirish #ifdef NXGE_DEBUG_ERROR 62344961713Sgirish else { 62444961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 6254045d941Ssowmini "nxge%d: 'conf' file parameter error\n", 6264045d941Ssowmini nxgep->instance)); 62744961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 6284045d941Ssowmini "Parameter keyword '%s'" 6294045d941Ssowmini "is outside valid range\n", 6304045d941Ssowmini param_arr[i].name)); 63144961713Sgirish } 63244961713Sgirish #endif 63344961713Sgirish ddi_prop_free(int_prop_val); 63444961713Sgirish } 63544961713Sgirish } 63644961713Sgirish } 63744961713Sgirish 63844961713Sgirish static int 63944961713Sgirish nxge_private_param_register(p_nxge_t nxgep, p_nxge_param_t param_arr) 64044961713Sgirish { 64144961713Sgirish int status = B_TRUE; 64244961713Sgirish int channel; 64344961713Sgirish uint8_t grp; 64444961713Sgirish char *prop_name; 64544961713Sgirish char *end; 64644961713Sgirish uint32_t name_chars; 64744961713Sgirish 64844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 6494045d941Ssowmini "nxge_private_param_register %s", param_arr->name)); 65044961713Sgirish 65144961713Sgirish if ((param_arr->type & NXGE_PARAM_PRIV) != NXGE_PARAM_PRIV) 65244961713Sgirish return (B_TRUE); 653a3c5bd6dSspeer 65444961713Sgirish prop_name = param_arr->name; 65544961713Sgirish if (param_arr->type & NXGE_PARAM_RXDMA) { 65644961713Sgirish if (strncmp("rxdma_intr", prop_name, 10) == 0) 65744961713Sgirish return (B_TRUE); 65844961713Sgirish name_chars = strlen("default_grp"); 65944961713Sgirish if (strncmp("default_grp", prop_name, name_chars) == 0) { 66044961713Sgirish prop_name += name_chars; 66144961713Sgirish grp = mi_strtol(prop_name, &end, 10); 66244961713Sgirish /* now check if this rdcgrp is in config */ 66344961713Sgirish return (nxge_check_rdcgrp_port_member(nxgep, grp)); 66444961713Sgirish } 66544961713Sgirish name_chars = strlen(prop_name); 66644961713Sgirish if (strncmp("default_port_rdc", prop_name, name_chars) == 0) { 66744961713Sgirish return (B_TRUE); 66844961713Sgirish } 66944961713Sgirish return (B_FALSE); 67044961713Sgirish } 67144961713Sgirish 67244961713Sgirish if (param_arr->type & NXGE_PARAM_TXDMA) { 67344961713Sgirish name_chars = strlen("txdma"); 67444961713Sgirish if (strncmp("txdma", prop_name, name_chars) == 0) { 67544961713Sgirish prop_name += name_chars; 67644961713Sgirish channel = mi_strtol(prop_name, &end, 10); 67744961713Sgirish /* now check if this rdc is in config */ 67844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 6794045d941Ssowmini " nxge_private_param_register: %d", 6804045d941Ssowmini channel)); 68144961713Sgirish return (nxge_check_txdma_port_member(nxgep, channel)); 68244961713Sgirish } 68344961713Sgirish return (B_FALSE); 68444961713Sgirish } 68544961713Sgirish 68644961713Sgirish status = B_FALSE; 68744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, "<== nxge_private_param_register")); 68844961713Sgirish 68944961713Sgirish return (status); 69044961713Sgirish } 69144961713Sgirish 69244961713Sgirish void 69344961713Sgirish nxge_setup_param(p_nxge_t nxgep) 69444961713Sgirish { 69544961713Sgirish p_nxge_param_t param_arr; 69644961713Sgirish int i; 69744961713Sgirish pfi_t set_pfi; 69844961713Sgirish 69944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_setup_param")); 700a3c5bd6dSspeer 70144961713Sgirish /* 70244961713Sgirish * Make sure the param_instance is set to a valid device instance. 70344961713Sgirish */ 70444961713Sgirish if (nxge_param_arr[param_instance].value == 1000) 70544961713Sgirish nxge_param_arr[param_instance].value = nxgep->instance; 70644961713Sgirish 70744961713Sgirish param_arr = nxgep->param_arr; 70844961713Sgirish param_arr[param_instance].value = nxgep->instance; 70944961713Sgirish param_arr[param_function_number].value = nxgep->function_num; 71044961713Sgirish 71144961713Sgirish for (i = 0; i < nxgep->param_count; i++) { 71244961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PRIV) && 7134045d941Ssowmini (nxge_private_param_register(nxgep, 7144045d941Ssowmini ¶m_arr[i]) == B_FALSE)) { 71544961713Sgirish param_arr[i].setf = NULL; 71644961713Sgirish param_arr[i].getf = NULL; 71744961713Sgirish } 71844961713Sgirish 71944961713Sgirish if (param_arr[i].type & NXGE_PARAM_CMPLX) 72044961713Sgirish param_arr[i].setf = NULL; 72144961713Sgirish 72244961713Sgirish if (param_arr[i].type & NXGE_PARAM_DONT_SHOW) { 72344961713Sgirish param_arr[i].setf = NULL; 72444961713Sgirish param_arr[i].getf = NULL; 72544961713Sgirish } 72644961713Sgirish 72744961713Sgirish set_pfi = (pfi_t)param_arr[i].setf; 72844961713Sgirish 729a3c5bd6dSspeer if ((set_pfi) && (param_arr[i].type & NXGE_PARAM_INIT_ONLY)) { 73044961713Sgirish set_pfi = NULL; 73144961713Sgirish } 73244961713Sgirish 73344961713Sgirish } 73444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_setup_param")); 73544961713Sgirish } 73644961713Sgirish 73744961713Sgirish void 73844961713Sgirish nxge_init_param(p_nxge_t nxgep) 73944961713Sgirish { 74044961713Sgirish p_nxge_param_t param_arr; 74144961713Sgirish int i, alloc_size; 74244961713Sgirish uint64_t alloc_count; 74344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_init_param")); 74444961713Sgirish /* 74544961713Sgirish * Make sure the param_instance is set to a valid device instance. 74644961713Sgirish */ 74744961713Sgirish if (nxge_param_arr[param_instance].value == 1000) 74844961713Sgirish nxge_param_arr[param_instance].value = nxgep->instance; 74944961713Sgirish 75044961713Sgirish param_arr = nxgep->param_arr; 75144961713Sgirish if (param_arr == NULL) { 752a3c5bd6dSspeer param_arr = (p_nxge_param_t) 7534045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_param_arr), KM_SLEEP); 75444961713Sgirish } 755a3c5bd6dSspeer 75644961713Sgirish for (i = 0; i < sizeof (nxge_param_arr)/sizeof (nxge_param_t); i++) { 75744961713Sgirish param_arr[i] = nxge_param_arr[i]; 75844961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 7594045d941Ssowmini (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 76044961713Sgirish alloc_count = NXGE_PARAM_ARRAY_INIT_SIZE; 76144961713Sgirish alloc_size = alloc_count * sizeof (uint64_t); 76244961713Sgirish param_arr[i].value = 763adfcba55Sjoycey #if defined(__i386) 7644045d941Ssowmini (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size, 7654045d941Ssowmini KM_SLEEP); 766adfcba55Sjoycey #else 7671bd6825cSml (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 768adfcba55Sjoycey #endif 76944961713Sgirish param_arr[i].old_value = 770adfcba55Sjoycey #if defined(__i386) 7714045d941Ssowmini (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size, 7724045d941Ssowmini KM_SLEEP); 773adfcba55Sjoycey #else 7744045d941Ssowmini (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 775adfcba55Sjoycey #endif 77644961713Sgirish param_arr[i].type |= 7774045d941Ssowmini (alloc_count << NXGE_PARAM_ARRAY_ALLOC_SHIFT); 77844961713Sgirish } 77944961713Sgirish } 78044961713Sgirish 78144961713Sgirish nxgep->param_arr = param_arr; 78244961713Sgirish nxgep->param_count = sizeof (nxge_param_arr)/sizeof (nxge_param_t); 7831bd6825cSml 7841bd6825cSml nxge_param_sync(nxgep); 7851bd6825cSml 78644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init_param: count %d", 7874045d941Ssowmini nxgep->param_count)); 78844961713Sgirish } 78944961713Sgirish 79044961713Sgirish void 79144961713Sgirish nxge_destroy_param(p_nxge_t nxgep) 79244961713Sgirish { 79344961713Sgirish int i; 79444961713Sgirish uint64_t free_size, free_count; 79544961713Sgirish 79644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_param")); 797a3c5bd6dSspeer 79859ac0c16Sdavemq if (nxgep->param_arr == NULL) 79959ac0c16Sdavemq return; 80044961713Sgirish /* 80144961713Sgirish * Make sure the param_instance is set to a valid device instance. 80244961713Sgirish */ 80344961713Sgirish if (nxge_param_arr[param_instance].value == nxgep->instance) { 80444961713Sgirish for (i = 0; i <= nxge_param_arr[param_instance].maximum; i++) { 80544961713Sgirish if ((ddi_get_soft_state(nxge_list, i) != NULL) && 8064045d941Ssowmini (i != nxgep->instance)) 80744961713Sgirish break; 80844961713Sgirish } 80944961713Sgirish nxge_param_arr[param_instance].value = i; 81044961713Sgirish } 81144961713Sgirish 81244961713Sgirish for (i = 0; i < nxgep->param_count; i++) 81344961713Sgirish if ((nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 8144045d941Ssowmini (nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 81544961713Sgirish free_count = ((nxgep->param_arr[i].type & 8164045d941Ssowmini NXGE_PARAM_ARRAY_ALLOC_MASK) >> 8174045d941Ssowmini NXGE_PARAM_ARRAY_ALLOC_SHIFT); 81844961713Sgirish free_count = NXGE_PARAM_ARRAY_INIT_SIZE; 81944961713Sgirish free_size = sizeof (uint64_t) * free_count; 820adfcba55Sjoycey #if defined(__i386) 821adfcba55Sjoycey KMEM_FREE((void *)(uint32_t)nxgep->param_arr[i].value, 8224045d941Ssowmini free_size); 823adfcba55Sjoycey #else 82444961713Sgirish KMEM_FREE((void *)nxgep->param_arr[i].value, free_size); 825adfcba55Sjoycey #endif 826adfcba55Sjoycey #if defined(__i386) 827adfcba55Sjoycey KMEM_FREE((void *)(uint32_t) 8284045d941Ssowmini nxgep->param_arr[i].old_value, free_size); 829adfcba55Sjoycey #else 83044961713Sgirish KMEM_FREE((void *)nxgep->param_arr[i].old_value, 8314045d941Ssowmini free_size); 832adfcba55Sjoycey #endif 83344961713Sgirish } 83444961713Sgirish 83544961713Sgirish KMEM_FREE(nxgep->param_arr, sizeof (nxge_param_arr)); 83644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_param")); 83744961713Sgirish } 83844961713Sgirish 83944961713Sgirish /* 84044961713Sgirish * Extracts the value from the 'nxge' parameter array and prints the 84144961713Sgirish * parameter value. cp points to the required parameter. 84244961713Sgirish */ 843a3c5bd6dSspeer 84444961713Sgirish /* ARGSUSED */ 84544961713Sgirish int 84644961713Sgirish nxge_param_get_generic(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 84744961713Sgirish { 84844961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 84944961713Sgirish 850a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, 8514045d941Ssowmini "==> nxge_param_get_generic name %s ", pa->name)); 85244961713Sgirish 85344961713Sgirish if (pa->value > 0xffffffff) 854a3c5bd6dSspeer (void) mi_mpprintf(mp, "%x%x", 8554045d941Ssowmini (int)(pa->value >> 32), (int)(pa->value & 0xffffffff)); 85644961713Sgirish else 85744961713Sgirish (void) mi_mpprintf(mp, "%x", (int)pa->value); 85844961713Sgirish 85944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_generic")); 86044961713Sgirish return (0); 86144961713Sgirish } 86244961713Sgirish 86344961713Sgirish /* ARGSUSED */ 86444961713Sgirish static int 86544961713Sgirish nxge_param_get_mac(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 86644961713Sgirish { 86744961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 86844961713Sgirish 86944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac")); 87044961713Sgirish 87144961713Sgirish (void) mi_mpprintf(mp, "%d", (uint32_t)pa->value); 87244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_mac")); 87344961713Sgirish return (0); 87444961713Sgirish } 87544961713Sgirish 87656d930aeSspeer /* ARGSUSED */ 87756d930aeSspeer static int 87856d930aeSspeer nxge_param_get_fw_ver(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 87956d930aeSspeer { 88056d930aeSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_fw_ver")); 88156d930aeSspeer 88256d930aeSspeer (void) mi_mpprintf(mp, "Firmware version for nxge%d: %s\n", 88356d930aeSspeer nxgep->instance, nxgep->vpd_info.ver); 88456d930aeSspeer 88556d930aeSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_fw_ver")); 88656d930aeSspeer return (0); 88756d930aeSspeer } 88856d930aeSspeer 8892e59129aSraghus /* ARGSUSED */ 8902e59129aSraghus static int 8912e59129aSraghus nxge_param_get_port_mode(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 8922e59129aSraghus { 8932e59129aSraghus NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_port_mode")); 8942e59129aSraghus 8952e59129aSraghus switch (nxgep->mac.portmode) { 8962e59129aSraghus case PORT_1G_COPPER: 8972d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Copper %s\n", 8982d17280bSsbehera nxgep->instance, 8992d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9002e59129aSraghus break; 9012e59129aSraghus case PORT_1G_FIBER: 9022d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Fiber %s\n", 9032d17280bSsbehera nxgep->instance, 9042d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9052e59129aSraghus break; 9062e59129aSraghus case PORT_10G_COPPER: 9072d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Copper " 9082d17280bSsbehera "%s\n", nxgep->instance, 9092d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9102e59129aSraghus break; 9112e59129aSraghus case PORT_10G_FIBER: 9122d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Fiber %s\n", 9132d17280bSsbehera nxgep->instance, 9142d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9152e59129aSraghus break; 9162e59129aSraghus case PORT_10G_SERDES: 9172d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Serdes " 9182d17280bSsbehera "%s\n", nxgep->instance, 9192d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9202e59129aSraghus break; 9212e59129aSraghus case PORT_1G_SERDES: 9222d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Serdes %s\n", 9232d17280bSsbehera nxgep->instance, 9242d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9252e59129aSraghus break; 9262e59129aSraghus case PORT_1G_RGMII_FIBER: 9272e59129aSraghus (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G RGMII " 9282d17280bSsbehera "Fiber %s\n", nxgep->instance, 9292d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9302d17280bSsbehera break; 9312d17280bSsbehera case PORT_HSP_MODE: 9322d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: Hot Swappable " 9332d17280bSsbehera "PHY, Currently NOT present\n", nxgep->instance); 9342e59129aSraghus break; 93500161856Syc case PORT_10G_TN1010: 93600161856Syc (void) mi_mpprintf(mp, "Port mode for nxge%d:" 93700161856Syc " 10G Copper with TN1010 %s\n", nxgep->instance, 93800161856Syc nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 93900161856Syc break; 94000161856Syc case PORT_1G_TN1010: 941c6e5ef56Syc (void) mi_mpprintf(mp, "Port mode for nxge%d:" 94200161856Syc " 1G Copper with TN1010 %s\n", nxgep->instance, 94300161856Syc nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 94400161856Syc break; 9452e59129aSraghus default: 9462d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: Unknown %s\n", 9472d17280bSsbehera nxgep->instance, 9482d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9492e59129aSraghus break; 9502e59129aSraghus } 9512e59129aSraghus 9523d16f8e7Sml (void) mi_mpprintf(mp, "Software LSO for nxge%d: %s\n", 9533d16f8e7Sml nxgep->instance, 9543d16f8e7Sml nxgep->soft_lso_enable ? "enable" : "disable"); 9553d16f8e7Sml 9562e59129aSraghus NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_port_mode")); 9572e59129aSraghus return (0); 9582e59129aSraghus } 9592e59129aSraghus 960*c1f9c6e5SSantwona Behera /* ARGSUSED */ 961*c1f9c6e5SSantwona Behera static int 962*c1f9c6e5SSantwona Behera nxge_param_get_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, caddr_t cp) 963*c1f9c6e5SSantwona Behera { 964*c1f9c6e5SSantwona Behera p_nxge_param_t pa = (p_nxge_param_t)cp; 965*c1f9c6e5SSantwona Behera 966*c1f9c6e5SSantwona Behera NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rx_intr_time")); 967*c1f9c6e5SSantwona Behera 968*c1f9c6e5SSantwona Behera pa->value = (uint32_t)nxgep->intr_timeout; 969*c1f9c6e5SSantwona Behera (void) mi_mpprintf(mp, "%d", (uint32_t)nxgep->intr_timeout); 970*c1f9c6e5SSantwona Behera 971*c1f9c6e5SSantwona Behera NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rx_intr_time")); 972*c1f9c6e5SSantwona Behera return (0); 973*c1f9c6e5SSantwona Behera } 974*c1f9c6e5SSantwona Behera 975*c1f9c6e5SSantwona Behera /* ARGSUSED */ 976*c1f9c6e5SSantwona Behera static int 977*c1f9c6e5SSantwona Behera nxge_param_get_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, caddr_t cp) 978*c1f9c6e5SSantwona Behera { 979*c1f9c6e5SSantwona Behera p_nxge_param_t pa = (p_nxge_param_t)cp; 980*c1f9c6e5SSantwona Behera 981*c1f9c6e5SSantwona Behera NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rx_intr_pkts")); 982*c1f9c6e5SSantwona Behera 983*c1f9c6e5SSantwona Behera pa->value = (uint32_t)nxgep->intr_threshold; 984*c1f9c6e5SSantwona Behera (void) mi_mpprintf(mp, "%d", (uint32_t)nxgep->intr_threshold); 985*c1f9c6e5SSantwona Behera 986*c1f9c6e5SSantwona Behera NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rx_intr_pkts")); 987*c1f9c6e5SSantwona Behera return (0); 988*c1f9c6e5SSantwona Behera } 989*c1f9c6e5SSantwona Behera 99044961713Sgirish /* ARGSUSED */ 99144961713Sgirish int 99244961713Sgirish nxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 99344961713Sgirish { 99444961713Sgirish 995678453a8Sspeer uint_t print_len, buf_len; 99644961713Sgirish p_mblk_t np; 99744961713Sgirish 99844961713Sgirish int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 999678453a8Sspeer int tdc; 1000678453a8Sspeer 1001678453a8Sspeer nxge_grp_set_t *set; 1002678453a8Sspeer 100344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_txdma_info")); 100444961713Sgirish 1005a3c5bd6dSspeer (void) mi_mpprintf(mp, "TXDMA Information for Port\t %d \n", 10064045d941Ssowmini nxgep->function_num); 100744961713Sgirish 100844961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 100944961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 101044961713Sgirish return (0); 101144961713Sgirish } 101244961713Sgirish 101344961713Sgirish buf_len = buff_alloc_size; 101444961713Sgirish mp->b_cont = np; 1015678453a8Sspeer print_len = 0; 101644961713Sgirish 101744961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 10184045d941Ssowmini "TDC\t HW TDC\t\n"); 101944961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 102044961713Sgirish buf_len -= print_len; 1021678453a8Sspeer 1022678453a8Sspeer set = &nxgep->tx_set; 1023da14cebeSEric Cheng for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { 1024678453a8Sspeer if ((1 << tdc) & set->owned.map) { 1025678453a8Sspeer print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1026678453a8Sspeer buf_len, "%d\n", tdc); 1027678453a8Sspeer ((mblk_t *)np)->b_wptr += print_len; 1028678453a8Sspeer buf_len -= print_len; 1029678453a8Sspeer } 103044961713Sgirish } 1031a3c5bd6dSspeer 103244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_txdma_info")); 103344961713Sgirish return (0); 103444961713Sgirish } 103544961713Sgirish 103644961713Sgirish /* ARGSUSED */ 103744961713Sgirish int 103844961713Sgirish nxge_param_get_rxdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 103944961713Sgirish { 1040a3c5bd6dSspeer uint_t print_len, buf_len; 1041a3c5bd6dSspeer p_mblk_t np; 1042a3c5bd6dSspeer int rdc; 104344961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 104444961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1045a3c5bd6dSspeer int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 104644961713Sgirish p_rx_rcr_rings_t rx_rcr_rings; 104744961713Sgirish p_rx_rcr_ring_t *rcr_rings; 104844961713Sgirish p_rx_rbr_rings_t rx_rbr_rings; 104944961713Sgirish p_rx_rbr_ring_t *rbr_rings; 1050678453a8Sspeer nxge_grp_set_t *set; 105144961713Sgirish 105244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rxdma_info")); 105344961713Sgirish 1054a3c5bd6dSspeer (void) mi_mpprintf(mp, "RXDMA Information for Port\t %d \n", 10554045d941Ssowmini nxgep->function_num); 105644961713Sgirish 105744961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 105844961713Sgirish /* The following may work even if we cannot get a large buf. */ 105944961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 106044961713Sgirish return (0); 106144961713Sgirish } 106244961713Sgirish 106344961713Sgirish buf_len = buff_alloc_size; 106444961713Sgirish mp->b_cont = np; 106544961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 106644961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 106744961713Sgirish 106844961713Sgirish rx_rcr_rings = nxgep->rx_rcr_rings; 106944961713Sgirish rcr_rings = rx_rcr_rings->rcr_rings; 107044961713Sgirish rx_rbr_rings = nxgep->rx_rbr_rings; 107144961713Sgirish rbr_rings = rx_rbr_rings->rbr_rings; 107244961713Sgirish 107344961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 10744045d941Ssowmini "Total RDCs\t %d\n", p_cfgp->max_rdcs); 107544961713Sgirish 107644961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 107744961713Sgirish buf_len -= print_len; 107844961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 10794045d941Ssowmini "RDC\t HW RDC\t Timeout\t Packets RBR ptr \t" 10804045d941Ssowmini "chunks\t RCR ptr\n"); 1081a3c5bd6dSspeer 108244961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 108344961713Sgirish buf_len -= print_len; 1084678453a8Sspeer 1085678453a8Sspeer set = &nxgep->rx_set; 1086678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1087678453a8Sspeer if ((1 << rdc) & set->owned.map) { 1088678453a8Sspeer print_len = snprintf((char *) 1089678453a8Sspeer ((mblk_t *)np)->b_wptr, buf_len, 1090678453a8Sspeer " %d\t %x\t\t %x\t $%p\t 0x%x\t $%p\n", 1091678453a8Sspeer rdc, 1092678453a8Sspeer p_dma_cfgp->rcr_timeout[rdc], 1093678453a8Sspeer p_dma_cfgp->rcr_threshold[rdc], 10948793b36bSNick Todd (void *)rbr_rings[rdc], 10958793b36bSNick Todd rbr_rings[rdc]->num_blocks, (void *)rcr_rings[rdc]); 1096a3c5bd6dSspeer ((mblk_t *)np)->b_wptr += print_len; 1097a3c5bd6dSspeer buf_len -= print_len; 1098678453a8Sspeer } 109944961713Sgirish } 1100a3c5bd6dSspeer 110144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rxdma_info")); 110244961713Sgirish return (0); 110344961713Sgirish } 110444961713Sgirish 110544961713Sgirish /* ARGSUSED */ 110644961713Sgirish int 110744961713Sgirish nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep, queue_t *q, 1108a3c5bd6dSspeer p_mblk_t mp, caddr_t cp) 110944961713Sgirish { 1110a3c5bd6dSspeer uint_t print_len, buf_len; 1111a3c5bd6dSspeer p_mblk_t np; 1112a3c5bd6dSspeer int offset, rdc, i, rdc_grp; 111344961713Sgirish p_nxge_rdc_grp_t rdc_grp_p; 111444961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 111544961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 111644961713Sgirish 111744961713Sgirish int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 111844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 11194045d941Ssowmini "==> nxge_param_get_rxdma_rdcgrp_info")); 112044961713Sgirish 112144961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 112244961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 112344961713Sgirish 1124a3c5bd6dSspeer (void) mi_mpprintf(mp, "RXDMA RDC Group Information for Port\t %d \n", 11254045d941Ssowmini nxgep->function_num); 112644961713Sgirish 1127678453a8Sspeer rdc_grp = p_cfgp->def_mac_rxdma_grpid; 112844961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 112944961713Sgirish /* The following may work even if we cannot get a large buf. */ 113044961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 113144961713Sgirish return (0); 113244961713Sgirish } 113344961713Sgirish 113444961713Sgirish buf_len = buff_alloc_size; 113544961713Sgirish mp->b_cont = np; 113644961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 11374045d941Ssowmini "Total RDC Groups\t %d \n" 11384045d941Ssowmini "default RDC group\t %d\n", 11394045d941Ssowmini p_cfgp->max_rdc_grpids, 11404045d941Ssowmini p_cfgp->def_mac_rxdma_grpid); 114144961713Sgirish 114244961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 114344961713Sgirish buf_len -= print_len; 114444961713Sgirish 11457b26d9ffSSantwona Behera for (i = 0; i < NXGE_MAX_RDC_GROUPS; i++) { 1146678453a8Sspeer if (p_cfgp->grpids[i]) { 1147678453a8Sspeer rdc_grp_p = &p_dma_cfgp->rdc_grps[i]; 114844961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1149678453a8Sspeer buf_len, 1150678453a8Sspeer "\nRDC Group Info for Group [%d] %d\n" 1151678453a8Sspeer "RDC Count %d\tstart RDC %d\n" 1152678453a8Sspeer "RDC Group Population Information" 1153678453a8Sspeer " (offsets 0 - 15)\n", 1154678453a8Sspeer i, rdc_grp, rdc_grp_p->max_rdcs, 1155678453a8Sspeer rdc_grp_p->start_rdc); 1156678453a8Sspeer 1157678453a8Sspeer ((mblk_t *)np)->b_wptr += print_len; 1158678453a8Sspeer buf_len -= print_len; 1159678453a8Sspeer print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1160678453a8Sspeer buf_len, "\n"); 1161678453a8Sspeer ((mblk_t *)np)->b_wptr += print_len; 1162678453a8Sspeer buf_len -= print_len; 1163678453a8Sspeer 1164678453a8Sspeer for (rdc = 0; rdc < rdc_grp_p->max_rdcs; rdc++) { 1165678453a8Sspeer print_len = snprintf( 11664045d941Ssowmini (char *)((mblk_t *)np)->b_wptr, 11674045d941Ssowmini buf_len, "[%d]=%d ", rdc, 11684045d941Ssowmini rdc_grp_p->start_rdc + rdc); 1169678453a8Sspeer ((mblk_t *)np)->b_wptr += print_len; 1170678453a8Sspeer buf_len -= print_len; 1171678453a8Sspeer } 1172678453a8Sspeer print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1173678453a8Sspeer buf_len, "\n"); 117444961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 117544961713Sgirish buf_len -= print_len; 117644961713Sgirish 1177678453a8Sspeer for (offset = 0; offset < 16; offset++) { 1178678453a8Sspeer print_len = snprintf( 11794045d941Ssowmini (char *)((mblk_t *)np)->b_wptr, 11804045d941Ssowmini buf_len, " %c", 11814045d941Ssowmini rdc_grp_p->map & (1 << offset) ? 11824045d941Ssowmini '1' : '0'); 1183678453a8Sspeer ((mblk_t *)np)->b_wptr += print_len; 1184678453a8Sspeer buf_len -= print_len; 1185678453a8Sspeer } 118644961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1187678453a8Sspeer buf_len, "\n"); 118844961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 118944961713Sgirish buf_len -= print_len; 119044961713Sgirish } 119144961713Sgirish } 119244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 11934045d941Ssowmini "<== nxge_param_get_rxdma_rdcgrp_info")); 119444961713Sgirish return (0); 119544961713Sgirish } 119644961713Sgirish 119744961713Sgirish int 119844961713Sgirish nxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size) 119944961713Sgirish { 120044961713Sgirish p_mblk_t tmp; 120144961713Sgirish 120244961713Sgirish tmp = mp; 120344961713Sgirish while (tmp->b_cont) 120444961713Sgirish tmp = tmp->b_cont; 120544961713Sgirish if ((tmp->b_wptr + size) >= tmp->b_datap->db_lim) { 120644961713Sgirish tmp->b_cont = allocb(1024, BPRI_HI); 120744961713Sgirish tmp = tmp->b_cont; 120844961713Sgirish if (!tmp) 120944961713Sgirish return (ENOMEM); 121044961713Sgirish } 1211a3c5bd6dSspeer 121244961713Sgirish *nmp = tmp; 121344961713Sgirish return (0); 121444961713Sgirish } 121544961713Sgirish 1216a3c5bd6dSspeer 121744961713Sgirish /* ARGSUSED */ 121844961713Sgirish int 121944961713Sgirish nxge_param_set_generic(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 122044961713Sgirish char *value, caddr_t cp) 122144961713Sgirish { 122244961713Sgirish char *end; 122344961713Sgirish uint32_t new_value; 122444961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 122544961713Sgirish 122644961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, " ==> nxge_param_set_generic")); 122744961713Sgirish new_value = (uint32_t)mi_strtol(value, &end, 10); 122844961713Sgirish if (end == value || new_value < pa->minimum || 12294045d941Ssowmini new_value > pa->maximum) { 123044961713Sgirish return (EINVAL); 123144961713Sgirish } 123244961713Sgirish pa->value = new_value; 123344961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, " <== nxge_param_set_generic")); 123444961713Sgirish return (0); 123544961713Sgirish } 123644961713Sgirish 123744961713Sgirish 1238a3c5bd6dSspeer /* ARGSUSED */ 123944961713Sgirish int 1240a3c5bd6dSspeer nxge_param_set_instance(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1241a3c5bd6dSspeer char *value, caddr_t cp) 124244961713Sgirish { 124344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " ==> nxge_param_set_instance")); 124444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_set_instance")); 124544961713Sgirish return (0); 124644961713Sgirish } 124744961713Sgirish 124844961713Sgirish 1249a3c5bd6dSspeer /* ARGSUSED */ 125044961713Sgirish int 1251a3c5bd6dSspeer nxge_param_set_mac(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1252a3c5bd6dSspeer char *value, caddr_t cp) 125344961713Sgirish { 1254a3c5bd6dSspeer char *end; 1255a3c5bd6dSspeer uint32_t new_value; 1256a3c5bd6dSspeer int status = 0; 1257a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 125844961713Sgirish 125944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac")); 126044961713Sgirish new_value = (uint32_t)mi_strtol(value, &end, BASE_DECIMAL); 126144961713Sgirish if (PARAM_OUTOF_RANGE(value, end, new_value, pa)) { 126244961713Sgirish return (EINVAL); 126344961713Sgirish } 126444961713Sgirish 126544961713Sgirish if (pa->value != new_value) { 126644961713Sgirish pa->old_value = pa->value; 126744961713Sgirish pa->value = new_value; 126844961713Sgirish } 126944961713Sgirish 127044961713Sgirish if (!nxge_param_link_update(nxgep)) { 127144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 12724045d941Ssowmini " false ret from nxge_param_link_update")); 127344961713Sgirish status = EINVAL; 127444961713Sgirish } 127544961713Sgirish 127644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac")); 127744961713Sgirish return (status); 127844961713Sgirish } 127944961713Sgirish 128044961713Sgirish /* ARGSUSED */ 12811bd6825cSml int 1282a3c5bd6dSspeer nxge_param_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1283a3c5bd6dSspeer char *value, caddr_t cp) 128444961713Sgirish { 1285a3c5bd6dSspeer char *end; 1286a3c5bd6dSspeer uint32_t cfg_value; 1287a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 128814ea4bb7Ssd 128944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_pkts")); 129044961713Sgirish 129114ea4bb7Ssd cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 129244961713Sgirish 129314ea4bb7Ssd if ((cfg_value > NXGE_RDC_RCR_THRESHOLD_MAX) || 12944045d941Ssowmini (cfg_value < NXGE_RDC_RCR_THRESHOLD_MIN)) { 129544961713Sgirish return (EINVAL); 129644961713Sgirish } 129714ea4bb7Ssd 129814ea4bb7Ssd if ((pa->value != cfg_value)) { 129914ea4bb7Ssd pa->old_value = pa->value; 130014ea4bb7Ssd pa->value = cfg_value; 130114ea4bb7Ssd nxgep->intr_threshold = pa->value; 130244961713Sgirish } 130314ea4bb7Ssd 130444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_pkts")); 130544961713Sgirish return (0); 130644961713Sgirish } 130744961713Sgirish 130844961713Sgirish /* ARGSUSED */ 13091bd6825cSml int 1310a3c5bd6dSspeer nxge_param_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1311a3c5bd6dSspeer char *value, caddr_t cp) 131244961713Sgirish { 1313a3c5bd6dSspeer char *end; 1314a3c5bd6dSspeer uint32_t cfg_value; 1315a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 131644961713Sgirish 131744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_time")); 131844961713Sgirish 131914ea4bb7Ssd cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 132044961713Sgirish 132114ea4bb7Ssd if ((cfg_value > NXGE_RDC_RCR_TIMEOUT_MAX) || 13224045d941Ssowmini (cfg_value < NXGE_RDC_RCR_TIMEOUT_MIN)) { 132344961713Sgirish return (EINVAL); 132444961713Sgirish } 132544961713Sgirish 132614ea4bb7Ssd if ((pa->value != cfg_value)) { 132714ea4bb7Ssd pa->old_value = pa->value; 132814ea4bb7Ssd pa->value = cfg_value; 132914ea4bb7Ssd nxgep->intr_timeout = pa->value; 133044961713Sgirish } 133144961713Sgirish 133244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_time")); 133344961713Sgirish return (0); 133444961713Sgirish } 133544961713Sgirish 133644961713Sgirish /* ARGSUSED */ 133744961713Sgirish static int 133844961713Sgirish nxge_param_set_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1339a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 134044961713Sgirish { 1341a3c5bd6dSspeer char *end; 1342a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1343a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1344a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 134544961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 134644961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1347a3c5bd6dSspeer uint32_t *val_ptr, *old_val_ptr; 1348a3c5bd6dSspeer nxge_param_map_t *mac_map; 1349a3c5bd6dSspeer p_nxge_class_pt_cfg_t p_class_cfgp; 1350a3c5bd6dSspeer nxge_mv_cfg_t *mac_host_info; 135144961713Sgirish 135244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac_rdcgrp ")); 135344961713Sgirish 135444961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 135544961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 135644961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 135744961713Sgirish mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 135844961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1359a3c5bd6dSspeer 1360a3c5bd6dSspeer /* 1361a3c5bd6dSspeer * now do decoding 1362a3c5bd6dSspeer */ 136344961713Sgirish mac_map = (nxge_param_map_t *)&cfg_value; 1364a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, " cfg_value %x id %x map_to %x", 13654045d941Ssowmini cfg_value, mac_map->param_id, mac_map->map_to)); 136644961713Sgirish 136744961713Sgirish if ((mac_map->param_id < p_cfgp->max_macs) && 1368678453a8Sspeer p_cfgp->grpids[mac_map->map_to]) { 136944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1370678453a8Sspeer " nxge_param_set_mac_rdcgrp mapping" 1371678453a8Sspeer " id %d grp %d", mac_map->param_id, mac_map->map_to)); 1372adfcba55Sjoycey #if defined(__i386) 1373adfcba55Sjoycey val_ptr = (uint32_t *)(uint32_t)pa->value; 1374adfcba55Sjoycey #else 137544961713Sgirish val_ptr = (uint32_t *)pa->value; 1376adfcba55Sjoycey #endif 1377adfcba55Sjoycey #if defined(__i386) 1378adfcba55Sjoycey old_val_ptr = (uint32_t *)(uint32_t)pa->old_value; 1379adfcba55Sjoycey #else 138044961713Sgirish old_val_ptr = (uint32_t *)pa->old_value; 1381adfcba55Sjoycey #endif 138244961713Sgirish if (val_ptr[mac_map->param_id] != cfg_value) { 138344961713Sgirish old_val_ptr[mac_map->param_id] = 1384678453a8Sspeer val_ptr[mac_map->param_id]; 138544961713Sgirish val_ptr[mac_map->param_id] = cfg_value; 138644961713Sgirish mac_host_info[mac_map->param_id].mpr_npr = 1387678453a8Sspeer mac_map->pref; 138844961713Sgirish mac_host_info[mac_map->param_id].flag = 1; 138944961713Sgirish mac_host_info[mac_map->param_id].rdctbl = 1390678453a8Sspeer mac_map->map_to; 139144961713Sgirish cfg_it = B_TRUE; 139244961713Sgirish } 139344961713Sgirish } else { 139444961713Sgirish return (EINVAL); 139544961713Sgirish } 139644961713Sgirish 139744961713Sgirish if (cfg_it == B_TRUE) { 139844961713Sgirish status = nxge_logical_mac_assign_rdc_table(nxgep, 1399678453a8Sspeer (uint8_t)mac_map->param_id); 140044961713Sgirish if (status != NXGE_OK) 140144961713Sgirish return (EINVAL); 140244961713Sgirish } 140344961713Sgirish 140444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac_rdcgrp")); 140544961713Sgirish return (0); 140644961713Sgirish } 140744961713Sgirish 140844961713Sgirish /* ARGSUSED */ 140944961713Sgirish static int 141044961713Sgirish nxge_param_set_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1411a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 141244961713Sgirish { 1413a3c5bd6dSspeer char *end; 1414a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1415a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1416a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 141744961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 141844961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1419a3c5bd6dSspeer uint32_t *val_ptr, *old_val_ptr; 1420a3c5bd6dSspeer nxge_param_map_t *vmap, *old_map; 1421a3c5bd6dSspeer p_nxge_class_pt_cfg_t p_class_cfgp; 1422a3c5bd6dSspeer uint64_t cfgd_vlans; 1423a3c5bd6dSspeer int i, inc = 0, cfg_position; 1424a3c5bd6dSspeer nxge_mv_cfg_t *vlan_tbl; 142544961713Sgirish 142644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 142744961713Sgirish 142844961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 142944961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 143044961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 143144961713Sgirish vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 143244961713Sgirish 143344961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1434a3c5bd6dSspeer 1435a3c5bd6dSspeer /* now do decoding */ 143644961713Sgirish cfgd_vlans = ((pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 14374045d941Ssowmini NXGE_PARAM_ARRAY_CNT_SHIFT); 143844961713Sgirish 143944961713Sgirish if (cfgd_vlans == NXGE_PARAM_ARRAY_INIT_SIZE) { 144044961713Sgirish /* 144144961713Sgirish * for now, we process only upto max 144244961713Sgirish * NXGE_PARAM_ARRAY_INIT_SIZE parameters 144344961713Sgirish * In the future, we may want to expand 144444961713Sgirish * the storage array and continue 144544961713Sgirish */ 144644961713Sgirish return (EINVAL); 144744961713Sgirish } 1448a3c5bd6dSspeer 144944961713Sgirish vmap = (nxge_param_map_t *)&cfg_value; 145044961713Sgirish if ((vmap->param_id) && 14514045d941Ssowmini (vmap->param_id < NXGE_MAX_VLANS) && 14524045d941Ssowmini (vmap->map_to < p_cfgp->max_rdc_grpids)) { 145344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 14544045d941Ssowmini "nxge_param_set_vlan_rdcgrp mapping" 14554045d941Ssowmini " id %d grp %d", 14564045d941Ssowmini vmap->param_id, vmap->map_to)); 1457adfcba55Sjoycey #if defined(__i386) 1458adfcba55Sjoycey val_ptr = (uint32_t *)(uint32_t)pa->value; 1459adfcba55Sjoycey #else 146044961713Sgirish val_ptr = (uint32_t *)pa->value; 1461adfcba55Sjoycey #endif 1462adfcba55Sjoycey #if defined(__i386) 1463adfcba55Sjoycey old_val_ptr = (uint32_t *)(uint32_t)pa->old_value; 1464adfcba55Sjoycey #else 146544961713Sgirish old_val_ptr = (uint32_t *)pa->old_value; 1466adfcba55Sjoycey #endif 146744961713Sgirish 146844961713Sgirish /* search to see if this vlan id is already configured */ 146944961713Sgirish for (i = 0; i < cfgd_vlans; i++) { 147044961713Sgirish old_map = (nxge_param_map_t *)&val_ptr[i]; 147144961713Sgirish if ((old_map->param_id == 0) || 14724045d941Ssowmini (vmap->param_id == old_map->param_id) || 14734045d941Ssowmini (vlan_tbl[vmap->param_id].flag)) { 147444961713Sgirish cfg_position = i; 147544961713Sgirish break; 147644961713Sgirish } 147744961713Sgirish } 147844961713Sgirish 147944961713Sgirish if (cfgd_vlans == 0) { 148044961713Sgirish cfg_position = 0; 148144961713Sgirish inc++; 148244961713Sgirish } 148344961713Sgirish 148444961713Sgirish if (i == cfgd_vlans) { 148544961713Sgirish cfg_position = i; 148644961713Sgirish inc++; 148744961713Sgirish } 148844961713Sgirish 148944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 14904045d941Ssowmini "set_vlan_rdcgrp mapping" 14914045d941Ssowmini " i %d cfgd_vlans %llx position %d ", 14924045d941Ssowmini i, cfgd_vlans, cfg_position)); 149344961713Sgirish if (val_ptr[cfg_position] != cfg_value) { 149444961713Sgirish old_val_ptr[cfg_position] = val_ptr[cfg_position]; 149544961713Sgirish val_ptr[cfg_position] = cfg_value; 149644961713Sgirish vlan_tbl[vmap->param_id].mpr_npr = vmap->pref; 149744961713Sgirish vlan_tbl[vmap->param_id].flag = 1; 149844961713Sgirish vlan_tbl[vmap->param_id].rdctbl = 1499678453a8Sspeer vmap->map_to + p_cfgp->def_mac_rxdma_grpid; 150044961713Sgirish cfg_it = B_TRUE; 150144961713Sgirish if (inc) { 150244961713Sgirish cfgd_vlans++; 150344961713Sgirish pa->type &= ~NXGE_PARAM_ARRAY_CNT_MASK; 150444961713Sgirish pa->type |= (cfgd_vlans << 15054045d941Ssowmini NXGE_PARAM_ARRAY_CNT_SHIFT); 150644961713Sgirish 150744961713Sgirish } 150844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 15094045d941Ssowmini "after: param_set_vlan_rdcgrp " 15104045d941Ssowmini " cfg_vlans %llx position %d \n", 15114045d941Ssowmini cfgd_vlans, cfg_position)); 151244961713Sgirish } 151344961713Sgirish } else { 151444961713Sgirish return (EINVAL); 151544961713Sgirish } 151644961713Sgirish 151744961713Sgirish if (cfg_it == B_TRUE) { 151844961713Sgirish status = nxge_fflp_config_vlan_table(nxgep, 15194045d941Ssowmini (uint16_t)vmap->param_id); 152044961713Sgirish if (status != NXGE_OK) 152144961713Sgirish return (EINVAL); 152244961713Sgirish } 152344961713Sgirish 152444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_vlan_rdcgrp")); 152544961713Sgirish return (0); 152644961713Sgirish } 152744961713Sgirish 152844961713Sgirish /* ARGSUSED */ 152944961713Sgirish static int 153044961713Sgirish nxge_param_get_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1531a3c5bd6dSspeer mblk_t *mp, caddr_t cp) 153244961713Sgirish { 153344961713Sgirish 1534a3c5bd6dSspeer uint_t print_len, buf_len; 1535a3c5bd6dSspeer p_mblk_t np; 1536a3c5bd6dSspeer int i; 1537a3c5bd6dSspeer uint32_t *val_ptr; 1538a3c5bd6dSspeer nxge_param_map_t *vmap; 1539a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 154044961713Sgirish p_nxge_class_pt_cfg_t p_class_cfgp; 154144961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 154244961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1543a3c5bd6dSspeer uint64_t cfgd_vlans = 0; 1544a3c5bd6dSspeer nxge_mv_cfg_t *vlan_tbl; 1545a3c5bd6dSspeer int buff_alloc_size = 15464045d941Ssowmini NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 154744961713Sgirish 154844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1549a3c5bd6dSspeer (void) mi_mpprintf(mp, "VLAN RDC Mapping Information for Port\t %d \n", 15504045d941Ssowmini nxgep->function_num); 155144961713Sgirish 155244961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 155344961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 155444961713Sgirish return (0); 155544961713Sgirish } 1556a3c5bd6dSspeer 155744961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 155844961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 155944961713Sgirish 156044961713Sgirish buf_len = buff_alloc_size; 156144961713Sgirish mp->b_cont = np; 156244961713Sgirish cfgd_vlans = (pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 15634045d941Ssowmini NXGE_PARAM_ARRAY_CNT_SHIFT; 156444961713Sgirish 156544961713Sgirish i = (int)cfgd_vlans; 156644961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 156744961713Sgirish vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 156844961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 15694045d941Ssowmini "Configured VLANs %d\n" 15704045d941Ssowmini "VLAN ID\t RDC GRP (Actual/Port)\t" 15714045d941Ssowmini " Prefernce\n", i); 157244961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 157344961713Sgirish buf_len -= print_len; 1574adfcba55Sjoycey #if defined(__i386) 1575adfcba55Sjoycey val_ptr = (uint32_t *)(uint32_t)pa->value; 1576adfcba55Sjoycey #else 157744961713Sgirish val_ptr = (uint32_t *)pa->value; 1578adfcba55Sjoycey #endif 157944961713Sgirish 158044961713Sgirish for (i = 0; i < cfgd_vlans; i++) { 158144961713Sgirish vmap = (nxge_param_map_t *)&val_ptr[i]; 158244961713Sgirish if (p_class_cfgp->vlan_tbl[vmap->param_id].flag) { 158344961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 15844045d941Ssowmini buf_len, 15854045d941Ssowmini " %d\t\t %d/%d\t\t %d\n", 15864045d941Ssowmini vmap->param_id, 15874045d941Ssowmini vlan_tbl[vmap->param_id].rdctbl, 15884045d941Ssowmini vlan_tbl[vmap->param_id].rdctbl - 15894045d941Ssowmini p_cfgp->def_mac_rxdma_grpid, 15904045d941Ssowmini vlan_tbl[vmap->param_id].mpr_npr); 159144961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 159244961713Sgirish buf_len -= print_len; 159344961713Sgirish } 159444961713Sgirish } 159544961713Sgirish 159644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_vlan_rdcgrp")); 159744961713Sgirish return (0); 159844961713Sgirish } 159944961713Sgirish 160044961713Sgirish /* ARGSUSED */ 160144961713Sgirish static int 160244961713Sgirish nxge_param_get_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1603a3c5bd6dSspeer mblk_t *mp, caddr_t cp) 160444961713Sgirish { 1605a3c5bd6dSspeer uint_t print_len, buf_len; 1606a3c5bd6dSspeer p_mblk_t np; 1607a3c5bd6dSspeer int i; 160844961713Sgirish p_nxge_class_pt_cfg_t p_class_cfgp; 160944961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 161044961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1611a3c5bd6dSspeer nxge_mv_cfg_t *mac_host_info; 161244961713Sgirish 161344961713Sgirish int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 161444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac_rdcgrp ")); 161544961713Sgirish (void) mi_mpprintf(mp, 16164045d941Ssowmini "MAC ADDR RDC Mapping Information for Port\t %d\n", 16174045d941Ssowmini nxgep->function_num); 161844961713Sgirish 161944961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 162044961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 162144961713Sgirish return (0); 162244961713Sgirish } 162344961713Sgirish 162444961713Sgirish buf_len = buff_alloc_size; 162544961713Sgirish mp->b_cont = np; 162644961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 162744961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 162844961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 162944961713Sgirish mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 163044961713Sgirish print_len = snprintf((char *)np->b_wptr, buf_len, 16314045d941Ssowmini "MAC ID\t RDC GRP (Actual/Port)\t" 16324045d941Ssowmini " Prefernce\n"); 163344961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 163444961713Sgirish buf_len -= print_len; 163544961713Sgirish for (i = 0; i < p_cfgp->max_macs; i++) { 163644961713Sgirish if (mac_host_info[i].flag) { 163744961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 16384045d941Ssowmini buf_len, 16394045d941Ssowmini " %d\t %d/%d\t\t %d\n", 16404045d941Ssowmini i, mac_host_info[i].rdctbl, 16414045d941Ssowmini mac_host_info[i].rdctbl - 16424045d941Ssowmini p_cfgp->def_mac_rxdma_grpid, 16434045d941Ssowmini mac_host_info[i].mpr_npr); 164444961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 164544961713Sgirish buf_len -= print_len; 164644961713Sgirish } 164744961713Sgirish } 164844961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 16494045d941Ssowmini "Done Info Dumping \n"); 165044961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 165144961713Sgirish buf_len -= print_len; 165244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_macrdcgrp")); 165344961713Sgirish return (0); 165444961713Sgirish } 165544961713Sgirish 165644961713Sgirish /* ARGSUSED */ 165744961713Sgirish static int 165844961713Sgirish nxge_param_tcam_enable(p_nxge_t nxgep, queue_t *q, 1659a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 166044961713Sgirish { 1661a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1662a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1663a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 1664a3c5bd6dSspeer char *end; 166544961713Sgirish 166644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_tcam_enable")); 166744961713Sgirish 166844961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 166944961713Sgirish if (pa->value != cfg_value) { 167044961713Sgirish pa->old_value = pa->value; 167144961713Sgirish pa->value = cfg_value; 167244961713Sgirish cfg_it = B_TRUE; 167344961713Sgirish } 167444961713Sgirish 167544961713Sgirish if (cfg_it == B_TRUE) { 167644961713Sgirish if (pa->value) 167744961713Sgirish status = nxge_fflp_config_tcam_enable(nxgep); 167844961713Sgirish else 167944961713Sgirish status = nxge_fflp_config_tcam_disable(nxgep); 168044961713Sgirish if (status != NXGE_OK) 168144961713Sgirish return (EINVAL); 168244961713Sgirish } 168344961713Sgirish 168444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_tcam_enable")); 168544961713Sgirish return (0); 168644961713Sgirish } 168744961713Sgirish 168844961713Sgirish /* ARGSUSED */ 168944961713Sgirish static int 169044961713Sgirish nxge_param_hash_lookup_enable(p_nxge_t nxgep, queue_t *q, 1691a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 169244961713Sgirish { 1693a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1694a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1695a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 1696a3c5bd6dSspeer char *end; 169744961713Sgirish 169844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_hash_lookup_enable")); 169944961713Sgirish 170044961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 170144961713Sgirish if (pa->value != cfg_value) { 170244961713Sgirish pa->old_value = pa->value; 170344961713Sgirish pa->value = cfg_value; 170444961713Sgirish cfg_it = B_TRUE; 170544961713Sgirish } 170644961713Sgirish 170744961713Sgirish if (cfg_it == B_TRUE) { 170844961713Sgirish if (pa->value) 170944961713Sgirish status = nxge_fflp_config_hash_lookup_enable(nxgep); 171044961713Sgirish else 171144961713Sgirish status = nxge_fflp_config_hash_lookup_disable(nxgep); 171244961713Sgirish if (status != NXGE_OK) 171344961713Sgirish return (EINVAL); 171444961713Sgirish } 171544961713Sgirish 171644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_hash_lookup_enable")); 171744961713Sgirish return (0); 171844961713Sgirish } 171944961713Sgirish 172044961713Sgirish /* ARGSUSED */ 172144961713Sgirish static int 172244961713Sgirish nxge_param_llc_snap_enable(p_nxge_t nxgep, queue_t *q, 1723a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 172444961713Sgirish { 1725a3c5bd6dSspeer char *end; 1726a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1727a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1728a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 172944961713Sgirish 173044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_llc_snap_enable")); 173144961713Sgirish 173244961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 173344961713Sgirish if (pa->value != cfg_value) { 173444961713Sgirish pa->old_value = pa->value; 173544961713Sgirish pa->value = cfg_value; 173644961713Sgirish cfg_it = B_TRUE; 173744961713Sgirish } 173844961713Sgirish 173944961713Sgirish if (cfg_it == B_TRUE) { 174044961713Sgirish if (pa->value) 174144961713Sgirish status = nxge_fflp_config_tcam_enable(nxgep); 174244961713Sgirish else 174344961713Sgirish status = nxge_fflp_config_tcam_disable(nxgep); 174444961713Sgirish if (status != NXGE_OK) 174544961713Sgirish return (EINVAL); 174644961713Sgirish } 174744961713Sgirish 174844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_llc_snap_enable")); 174944961713Sgirish return (0); 175044961713Sgirish } 175144961713Sgirish 175244961713Sgirish /* ARGSUSED */ 175344961713Sgirish static int 175444961713Sgirish nxge_param_set_ether_usr(p_nxge_t nxgep, queue_t *q, 1755a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 175644961713Sgirish { 1757a3c5bd6dSspeer char *end; 1758a3c5bd6dSspeer uint8_t ether_class; 1759a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1760a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1761a3c5bd6dSspeer uint8_t cfg_it = B_FALSE; 176244961713Sgirish 176344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ether_usr")); 176444961713Sgirish 176544961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 176644961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 176744961713Sgirish return (EINVAL); 176844961713Sgirish } 1769a3c5bd6dSspeer 177044961713Sgirish if (pa->value != cfg_value) { 177144961713Sgirish pa->old_value = pa->value; 177244961713Sgirish pa->value = cfg_value; 177344961713Sgirish cfg_it = B_TRUE; 177444961713Sgirish } 177544961713Sgirish 177644961713Sgirish /* do the actual hw setup */ 177744961713Sgirish if (cfg_it == B_TRUE) { 177844961713Sgirish ether_class = mi_strtol(pa->name, &end, 10); 177944961713Sgirish #ifdef lint 178044961713Sgirish ether_class = ether_class; 178144961713Sgirish #endif 178244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_ether_usr")); 178344961713Sgirish } 1784a3c5bd6dSspeer 178544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ether_usr")); 178644961713Sgirish return (status); 178744961713Sgirish } 178844961713Sgirish 178944961713Sgirish /* ARGSUSED */ 179044961713Sgirish static int 179144961713Sgirish nxge_param_set_ip_usr(p_nxge_t nxgep, queue_t *q, 1792a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 179344961713Sgirish { 1794a3c5bd6dSspeer char *end; 1795a3c5bd6dSspeer tcam_class_t class; 1796a3c5bd6dSspeer uint32_t status, cfg_value; 1797a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1798a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 179944961713Sgirish 180044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_usr")); 180144961713Sgirish 180244961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 180344961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 180444961713Sgirish return (EINVAL); 180544961713Sgirish } 180644961713Sgirish 180744961713Sgirish if (pa->value != cfg_value) { 180844961713Sgirish pa->old_value = pa->value; 180944961713Sgirish pa->value = cfg_value; 181044961713Sgirish cfg_it = B_TRUE; 181144961713Sgirish } 181244961713Sgirish 181344961713Sgirish /* do the actual hw setup with cfg_value. */ 181444961713Sgirish if (cfg_it == B_TRUE) { 181544961713Sgirish class = mi_strtol(pa->name, &end, 10); 181644961713Sgirish status = nxge_fflp_ip_usr_class_config(nxgep, class, pa->value); 181744961713Sgirish } 181844961713Sgirish 181944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_usr")); 182044961713Sgirish return (status); 182144961713Sgirish } 182244961713Sgirish 1823a3c5bd6dSspeer /* ARGSUSED */ 182444961713Sgirish static int 182544961713Sgirish nxge_class_name_2value(p_nxge_t nxgep, char *name) 182644961713Sgirish { 1827a3c5bd6dSspeer int i; 1828a3c5bd6dSspeer int class_instance = param_class_opt_ip_usr4; 1829a3c5bd6dSspeer p_nxge_param_t param_arr; 1830a3c5bd6dSspeer 183144961713Sgirish param_arr = nxgep->param_arr; 183244961713Sgirish for (i = TCAM_CLASS_IP_USER_4; i <= TCAM_CLASS_SCTP_IPV6; i++) { 183344961713Sgirish if (strcmp(param_arr[class_instance].name, name) == 0) 183444961713Sgirish return (i); 183544961713Sgirish class_instance++; 183644961713Sgirish } 183744961713Sgirish return (-1); 183844961713Sgirish } 183944961713Sgirish 184044961713Sgirish /* ARGSUSED */ 18411bd6825cSml int 184244961713Sgirish nxge_param_set_ip_opt(p_nxge_t nxgep, queue_t *q, 1843a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 184444961713Sgirish { 1845a3c5bd6dSspeer char *end; 1846a3c5bd6dSspeer uint32_t status, cfg_value; 1847a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1848a3c5bd6dSspeer tcam_class_t class; 1849a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 185044961713Sgirish 185144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_opt")); 185244961713Sgirish 185344961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 185444961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 185544961713Sgirish return (EINVAL); 185644961713Sgirish } 185744961713Sgirish 185844961713Sgirish if (pa->value != cfg_value) { 185944961713Sgirish pa->old_value = pa->value; 186044961713Sgirish pa->value = cfg_value; 186144961713Sgirish cfg_it = B_TRUE; 186244961713Sgirish } 186344961713Sgirish 186444961713Sgirish if (cfg_it == B_TRUE) { 1865a3c5bd6dSspeer /* do the actual hw setup */ 186644961713Sgirish class = nxge_class_name_2value(nxgep, pa->name); 186744961713Sgirish if (class == -1) 186844961713Sgirish return (EINVAL); 186944961713Sgirish 1870*c1f9c6e5SSantwona Behera /* Filter out the allowed bits */ 1871*c1f9c6e5SSantwona Behera pa->value &= (NXGE_CLASS_FLOW_USE_PORTNUM | 1872*c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_L2DA | NXGE_CLASS_FLOW_USE_VLAN | 1873*c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_PROTO | NXGE_CLASS_FLOW_USE_IPSRC | 1874*c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_IPDST | NXGE_CLASS_FLOW_USE_SRC_PORT | 1875*c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_DST_PORT); 1876*c1f9c6e5SSantwona Behera 187744961713Sgirish status = nxge_fflp_ip_class_config(nxgep, class, pa->value); 187844961713Sgirish if (status != NXGE_OK) 187944961713Sgirish return (EINVAL); 188044961713Sgirish } 188144961713Sgirish 188244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_opt")); 188344961713Sgirish return (0); 188444961713Sgirish } 188544961713Sgirish 188644961713Sgirish /* ARGSUSED */ 188744961713Sgirish static int 188844961713Sgirish nxge_param_get_ip_opt(p_nxge_t nxgep, queue_t *q, 1889a3c5bd6dSspeer mblk_t *mp, caddr_t cp) 189044961713Sgirish { 189144961713Sgirish uint32_t status, cfg_value; 189244961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 189344961713Sgirish tcam_class_t class; 189444961713Sgirish 189544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_ip_opt")); 189644961713Sgirish 1897a3c5bd6dSspeer /* do the actual hw setup */ 189844961713Sgirish class = nxge_class_name_2value(nxgep, pa->name); 189944961713Sgirish if (class == -1) 190044961713Sgirish return (EINVAL); 1901a3c5bd6dSspeer 190244961713Sgirish cfg_value = 0; 190344961713Sgirish status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 190444961713Sgirish if (status != NXGE_OK) 190544961713Sgirish return (EINVAL); 1906a3c5bd6dSspeer 1907*c1f9c6e5SSantwona Behera /* Filter out the allowed bits */ 1908*c1f9c6e5SSantwona Behera cfg_value &= (NXGE_CLASS_FLOW_USE_PORTNUM | NXGE_CLASS_FLOW_USE_L2DA | 1909*c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_VLAN | NXGE_CLASS_FLOW_USE_PROTO | 1910*c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_IPDST | 1911*c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_DST_PORT); 1912*c1f9c6e5SSantwona Behera 191344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 19144045d941Ssowmini "nxge_param_get_ip_opt_get %x ", cfg_value)); 191544961713Sgirish 1916a3c5bd6dSspeer pa->value = cfg_value; 191744961713Sgirish (void) mi_mpprintf(mp, "%x", cfg_value); 1918a3c5bd6dSspeer 191944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 192044961713Sgirish return (0); 192144961713Sgirish } 192244961713Sgirish 192344961713Sgirish /* ARGSUSED */ 192444961713Sgirish static int 192544961713Sgirish nxge_param_fflp_hash_init(p_nxge_t nxgep, queue_t *q, 1926a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 192744961713Sgirish { 1928a3c5bd6dSspeer char *end; 1929a3c5bd6dSspeer uint32_t status, cfg_value; 1930a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1931a3c5bd6dSspeer tcam_class_t class; 1932a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 193344961713Sgirish 193444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_fflp_hash_init")); 193544961713Sgirish 193644961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 193744961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 193844961713Sgirish return (EINVAL); 193944961713Sgirish } 194044961713Sgirish 194144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 19424045d941Ssowmini "nxge_param_fflp_hash_init value %x", cfg_value)); 1943a3c5bd6dSspeer 194444961713Sgirish if (pa->value != cfg_value) { 194544961713Sgirish pa->old_value = pa->value; 194644961713Sgirish pa->value = cfg_value; 194744961713Sgirish cfg_it = B_TRUE; 194844961713Sgirish } 194944961713Sgirish 195044961713Sgirish if (cfg_it == B_TRUE) { 195144961713Sgirish char *h_name; 1952a3c5bd6dSspeer 195344961713Sgirish /* do the actual hw setup */ 195444961713Sgirish h_name = pa->name; 195544961713Sgirish h_name++; 195644961713Sgirish class = mi_strtol(h_name, &end, 10); 195744961713Sgirish switch (class) { 195844961713Sgirish case 1: 195944961713Sgirish status = nxge_fflp_set_hash1(nxgep, 19604045d941Ssowmini (uint32_t)pa->value); 196144961713Sgirish break; 196244961713Sgirish case 2: 196344961713Sgirish status = nxge_fflp_set_hash2(nxgep, 19644045d941Ssowmini (uint16_t)pa->value); 196544961713Sgirish break; 196644961713Sgirish 196744961713Sgirish default: 196844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 19694045d941Ssowmini " nxge_param_fflp_hash_init" 19704045d941Ssowmini " %s Wrong hash var %d", 19714045d941Ssowmini pa->name, class)); 197244961713Sgirish return (EINVAL); 197344961713Sgirish } 197444961713Sgirish if (status != NXGE_OK) 197544961713Sgirish return (EINVAL); 197644961713Sgirish } 197744961713Sgirish 197844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_fflp_hash_init")); 197944961713Sgirish return (0); 198044961713Sgirish } 198144961713Sgirish 198244961713Sgirish /* ARGSUSED */ 198344961713Sgirish static int 198444961713Sgirish nxge_param_set_grp_rdc(p_nxge_t nxgep, queue_t *q, 1985a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 198644961713Sgirish { 1987a3c5bd6dSspeer char *end; 1988a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1989a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1990a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 1991a3c5bd6dSspeer int rdc_grp; 1992a3c5bd6dSspeer uint8_t real_rdc; 199344961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 199444961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 199544961713Sgirish p_nxge_rdc_grp_t rdc_grp_p; 199644961713Sgirish 199744961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 199844961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 199944961713Sgirish 200044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_grp_rdc")); 200144961713Sgirish 200244961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 200344961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 200444961713Sgirish return (EINVAL); 200544961713Sgirish } 2006a3c5bd6dSspeer 200744961713Sgirish if (cfg_value >= p_cfgp->max_rdcs) { 200844961713Sgirish return (EINVAL); 200944961713Sgirish } 2010a3c5bd6dSspeer 201144961713Sgirish if (pa->value != cfg_value) { 201244961713Sgirish pa->old_value = pa->value; 201344961713Sgirish pa->value = cfg_value; 201444961713Sgirish cfg_it = B_TRUE; 201544961713Sgirish } 201644961713Sgirish 201744961713Sgirish if (cfg_it == B_TRUE) { 201844961713Sgirish char *grp_name; 201944961713Sgirish grp_name = pa->name; 202044961713Sgirish grp_name += strlen("default-grp"); 202144961713Sgirish rdc_grp = mi_strtol(grp_name, &end, 10); 202244961713Sgirish rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp]; 202344961713Sgirish real_rdc = rdc_grp_p->start_rdc + cfg_value; 202444961713Sgirish if (nxge_check_rxdma_rdcgrp_member(nxgep, rdc_grp, 20254045d941Ssowmini cfg_value) == B_FALSE) { 202644961713Sgirish pa->value = pa->old_value; 202744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 20284045d941Ssowmini " nxge_param_set_grp_rdc" 20294045d941Ssowmini " %d read %d actual %d outof range", 20304045d941Ssowmini rdc_grp, cfg_value, real_rdc)); 203144961713Sgirish return (EINVAL); 203244961713Sgirish } 203344961713Sgirish status = nxge_rxdma_cfg_rdcgrp_default_rdc(nxgep, rdc_grp, 20344045d941Ssowmini real_rdc); 203544961713Sgirish if (status != NXGE_OK) 203644961713Sgirish return (EINVAL); 203744961713Sgirish } 203844961713Sgirish 203944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_grp_rdc")); 204044961713Sgirish return (0); 204144961713Sgirish } 204244961713Sgirish 204344961713Sgirish /* ARGSUSED */ 204444961713Sgirish static int 204544961713Sgirish nxge_param_set_port_rdc(p_nxge_t nxgep, queue_t *q, 2046a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 204744961713Sgirish { 2048a3c5bd6dSspeer char *end; 2049a3c5bd6dSspeer uint32_t status = B_TRUE, cfg_value; 2050a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 2051a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 205244961713Sgirish 205344961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 205444961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 205544961713Sgirish 205644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_port_rdc")); 205744961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 205844961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 205944961713Sgirish 206044961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 206144961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 206244961713Sgirish return (EINVAL); 206344961713Sgirish } 2064a3c5bd6dSspeer 206544961713Sgirish if (pa->value != cfg_value) { 206644961713Sgirish if (cfg_value >= p_cfgp->max_rdcs) 206744961713Sgirish return (EINVAL); 206844961713Sgirish pa->old_value = pa->value; 206944961713Sgirish pa->value = cfg_value; 207044961713Sgirish cfg_it = B_TRUE; 207144961713Sgirish } 207244961713Sgirish 207344961713Sgirish if (cfg_it == B_TRUE) { 2074678453a8Sspeer int rdc; 2075678453a8Sspeer if ((rdc = nxge_dci_map(nxgep, VP_BOUND_RX, cfg_value)) < 0) 2076678453a8Sspeer return (EINVAL); 207744961713Sgirish status = nxge_rxdma_cfg_port_default_rdc(nxgep, 2078678453a8Sspeer nxgep->function_num, rdc); 207944961713Sgirish if (status != NXGE_OK) 208044961713Sgirish return (EINVAL); 208144961713Sgirish } 208244961713Sgirish 208344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_port_rdc")); 208444961713Sgirish return (0); 208544961713Sgirish } 208644961713Sgirish 208744961713Sgirish /* ARGSUSED */ 208844961713Sgirish static int 208944961713Sgirish nxge_param_set_nxge_debug_flag(p_nxge_t nxgep, queue_t *q, 2090a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 209144961713Sgirish { 209244961713Sgirish char *end; 209344961713Sgirish uint32_t status = 0; 209444961713Sgirish uint64_t cfg_value = 0; 209544961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 209644961713Sgirish uint32_t cfg_it = B_FALSE; 209744961713Sgirish 209844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_nxge_debug_flag")); 209944961713Sgirish cfg_value = mi_strtol(value, &end, BASE_HEX); 210044961713Sgirish 210144961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 210244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 21034045d941Ssowmini " nxge_param_set_nxge_debug_flag" 21044045d941Ssowmini " outof range %llx", cfg_value)); 210544961713Sgirish return (EINVAL); 210644961713Sgirish } 210744961713Sgirish if (pa->value != cfg_value) { 210844961713Sgirish pa->old_value = pa->value; 210944961713Sgirish pa->value = cfg_value; 211044961713Sgirish cfg_it = B_TRUE; 211144961713Sgirish } 211244961713Sgirish 211344961713Sgirish if (cfg_it == B_TRUE) { 211444961713Sgirish nxgep->nxge_debug_level = pa->value; 211544961713Sgirish } 2116a3c5bd6dSspeer 211744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_nxge_debug_flag")); 211844961713Sgirish return (status); 211944961713Sgirish } 212044961713Sgirish 212144961713Sgirish /* ARGSUSED */ 212244961713Sgirish static int 212344961713Sgirish nxge_param_get_debug_flag(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 212444961713Sgirish { 2125a3c5bd6dSspeer int status = 0; 2126a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 212744961713Sgirish 212844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_debug_flag")); 212944961713Sgirish 213044961713Sgirish if (pa->value > 0xffffffff) 213144961713Sgirish (void) mi_mpprintf(mp, "%x%x", (int)(pa->value >> 32), 21324045d941Ssowmini (int)(pa->value & 0xffffffff)); 213344961713Sgirish else 213444961713Sgirish (void) mi_mpprintf(mp, "%x", (int)pa->value); 213544961713Sgirish 213644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_debug_flag")); 213744961713Sgirish return (status); 213844961713Sgirish } 213944961713Sgirish 214044961713Sgirish /* ARGSUSED */ 214144961713Sgirish static int 214244961713Sgirish nxge_param_set_npi_debug_flag(p_nxge_t nxgep, queue_t *q, 2143a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 214444961713Sgirish { 2145a3c5bd6dSspeer char *end; 2146a3c5bd6dSspeer uint32_t status = 0; 2147a3c5bd6dSspeer uint64_t cfg_value = 0; 2148a3c5bd6dSspeer p_nxge_param_t pa; 2149a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 215044961713Sgirish 215144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_npi_debug_flag")); 215244961713Sgirish cfg_value = mi_strtol(value, &end, BASE_HEX); 215344961713Sgirish pa = (p_nxge_param_t)cp; 215444961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 215544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_npi_debug_flag" 21564045d941Ssowmini " outof range %llx", cfg_value)); 215744961713Sgirish return (EINVAL); 215844961713Sgirish } 215944961713Sgirish if (pa->value != cfg_value) { 216044961713Sgirish pa->old_value = pa->value; 216144961713Sgirish pa->value = cfg_value; 216244961713Sgirish cfg_it = B_TRUE; 216344961713Sgirish } 216444961713Sgirish 216544961713Sgirish if (cfg_it == B_TRUE) { 216644961713Sgirish npi_debug_level = pa->value; 216744961713Sgirish } 216844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_debug_flag")); 216944961713Sgirish return (status); 217044961713Sgirish } 217144961713Sgirish 217244961713Sgirish /* ARGSUSED */ 217344961713Sgirish static int 217444961713Sgirish nxge_param_dump_rdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 217544961713Sgirish { 2176678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set; 2177678453a8Sspeer int rdc; 217844961713Sgirish 217944961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_rdc")); 218044961713Sgirish 2181678453a8Sspeer if (!isLDOMguest(nxgep)) 21824045d941Ssowmini (void) npi_rxdma_dump_fzc_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2183678453a8Sspeer 2184678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_TDCS; rdc++) { 2185678453a8Sspeer if ((1 << rdc) & set->owned.map) { 2186678453a8Sspeer (void) nxge_dump_rxdma_channel(nxgep, rdc); 2187678453a8Sspeer } 2188678453a8Sspeer } 218944961713Sgirish 219044961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_rdc")); 219144961713Sgirish return (0); 219244961713Sgirish } 219344961713Sgirish 219444961713Sgirish /* ARGSUSED */ 219544961713Sgirish static int 219644961713Sgirish nxge_param_dump_tdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 219744961713Sgirish { 2198678453a8Sspeer nxge_grp_set_t *set = &nxgep->tx_set; 2199678453a8Sspeer int tdc; 220044961713Sgirish 220144961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_tdc")); 220244961713Sgirish 2203678453a8Sspeer for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { 2204678453a8Sspeer if ((1 << tdc) & set->owned.map) { 2205678453a8Sspeer (void) nxge_txdma_regs_dump(nxgep, tdc); 2206678453a8Sspeer } 2207678453a8Sspeer } 220844961713Sgirish 220944961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_tdc")); 221044961713Sgirish return (0); 221144961713Sgirish } 221244961713Sgirish 221344961713Sgirish /* ARGSUSED */ 221444961713Sgirish static int 221544961713Sgirish nxge_param_dump_fflp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 221644961713Sgirish { 221744961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_fflp_regs")); 221844961713Sgirish 221944961713Sgirish (void) npi_fflp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 222044961713Sgirish 222144961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_fflp_regs")); 222244961713Sgirish return (0); 222344961713Sgirish } 222444961713Sgirish 222544961713Sgirish /* ARGSUSED */ 222644961713Sgirish static int 222744961713Sgirish nxge_param_dump_mac_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 222844961713Sgirish { 222944961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_mac_regs")); 223044961713Sgirish 223144961713Sgirish (void) npi_mac_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 22324045d941Ssowmini nxgep->function_num); 223344961713Sgirish 223444961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_mac_regs")); 223544961713Sgirish return (0); 223644961713Sgirish } 223744961713Sgirish 223844961713Sgirish /* ARGSUSED */ 223944961713Sgirish static int 224044961713Sgirish nxge_param_dump_ipp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 224144961713Sgirish { 224244961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_ipp_regs")); 224344961713Sgirish 2244a3c5bd6dSspeer (void) npi_ipp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 22454045d941Ssowmini nxgep->function_num); 224644961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ipp_regs")); 224744961713Sgirish return (0); 224844961713Sgirish } 224944961713Sgirish 225044961713Sgirish /* ARGSUSED */ 225144961713Sgirish static int 225244961713Sgirish nxge_param_dump_vlan_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 225344961713Sgirish { 225444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_vlan_table")); 225544961713Sgirish 225644961713Sgirish (void) npi_fflp_vlan_tbl_dump(NXGE_DEV_NPI_HANDLE(nxgep)); 225744961713Sgirish 225844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_vlan_table")); 225944961713Sgirish return (0); 226044961713Sgirish } 226144961713Sgirish 226244961713Sgirish /* ARGSUSED */ 226344961713Sgirish static int 226444961713Sgirish nxge_param_dump_rdc_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 226544961713Sgirish { 2266a3c5bd6dSspeer uint8_t table; 226744961713Sgirish 226844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_rdc_table")); 226944961713Sgirish for (table = 0; table < NXGE_MAX_RDC_GROUPS; table++) { 227044961713Sgirish (void) npi_rxdma_dump_rdc_table(NXGE_DEV_NPI_HANDLE(nxgep), 22714045d941Ssowmini table); 227244961713Sgirish } 2273a3c5bd6dSspeer 227444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_rdc_table")); 227544961713Sgirish return (0); 227644961713Sgirish } 227744961713Sgirish 227844961713Sgirish typedef struct block_info { 227944961713Sgirish char *name; 228044961713Sgirish uint32_t offset; 228144961713Sgirish } block_info_t; 228244961713Sgirish 228344961713Sgirish block_info_t reg_block[] = { 228444961713Sgirish {"PIO", PIO}, 228544961713Sgirish {"FZC_PIO", FZC_PIO}, 228644961713Sgirish {"FZC_XMAC", FZC_MAC}, 228744961713Sgirish {"FZC_IPP", FZC_IPP}, 228844961713Sgirish {"FFLP", FFLP}, 228944961713Sgirish {"FZC_FFLP", FZC_FFLP}, 229044961713Sgirish {"PIO_VADDR", PIO_VADDR}, 229144961713Sgirish {"ZCP", ZCP}, 229244961713Sgirish {"FZC_ZCP", FZC_ZCP}, 229344961713Sgirish {"DMC", DMC}, 229444961713Sgirish {"FZC_DMC", FZC_DMC}, 229544961713Sgirish {"TXC", TXC}, 229644961713Sgirish {"FZC_TXC", FZC_TXC}, 229744961713Sgirish {"PIO_LDSV", PIO_LDSV}, 229844961713Sgirish {"PIO_LDGIM", PIO_LDGIM}, 229944961713Sgirish {"PIO_IMASK0", PIO_IMASK0}, 230044961713Sgirish {"PIO_IMASK1", PIO_IMASK1}, 230144961713Sgirish {"FZC_PROM", FZC_PROM}, 230244961713Sgirish {"END", ALL_FF_32}, 230344961713Sgirish }; 230444961713Sgirish 230544961713Sgirish /* ARGSUSED */ 230644961713Sgirish static int 230744961713Sgirish nxge_param_dump_ptrs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 230844961713Sgirish { 2309a3c5bd6dSspeer uint_t print_len, buf_len; 2310a3c5bd6dSspeer p_mblk_t np; 2311a3c5bd6dSspeer int rdc, tdc, block; 2312a3c5bd6dSspeer uint64_t base; 231344961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 231444961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 2315a3c5bd6dSspeer int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_8K; 231644961713Sgirish p_tx_ring_t *tx_rings; 231744961713Sgirish p_rx_rcr_rings_t rx_rcr_rings; 231844961713Sgirish p_rx_rcr_ring_t *rcr_rings; 231944961713Sgirish p_rx_rbr_rings_t rx_rbr_rings; 232044961713Sgirish p_rx_rbr_ring_t *rbr_rings; 232144961713Sgirish 2322a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, IOC_CTL, 23234045d941Ssowmini "==> nxge_param_dump_ptrs")); 232444961713Sgirish 2325a3c5bd6dSspeer (void) mi_mpprintf(mp, "ptr information for Port\t %d \n", 23264045d941Ssowmini nxgep->function_num); 232744961713Sgirish 232844961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 232944961713Sgirish /* The following may work even if we cannot get a large buf. */ 233044961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 233144961713Sgirish return (0); 233244961713Sgirish } 233344961713Sgirish 233444961713Sgirish buf_len = buff_alloc_size; 233544961713Sgirish mp->b_cont = np; 233644961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 233744961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 233844961713Sgirish 233944961713Sgirish rx_rcr_rings = nxgep->rx_rcr_rings; 234044961713Sgirish rcr_rings = rx_rcr_rings->rcr_rings; 234144961713Sgirish rx_rbr_rings = nxgep->rx_rbr_rings; 234244961713Sgirish rbr_rings = rx_rbr_rings->rbr_rings; 234344961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 23444045d941Ssowmini "nxgep (nxge_t) $%p\n" 23454045d941Ssowmini "dev_regs (dev_regs_t) $%p\n", 23468793b36bSNick Todd (void *)nxgep, (void *)nxgep->dev_regs); 234744961713Sgirish 234844961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2349a3c5bd6dSspeer 2350a3c5bd6dSspeer /* do register pointers */ 235144961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 23524045d941Ssowmini "reg base (npi_reg_ptr_t) $%p\t " 23534045d941Ssowmini "pci reg (npi_reg_ptr_t) $%p\n", 23548793b36bSNick Todd (void *)nxgep->dev_regs->nxge_regp, 23558793b36bSNick Todd (void *)nxgep->dev_regs->nxge_pciregp); 235644961713Sgirish 235744961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 235844961713Sgirish 235944961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 23604045d941Ssowmini "\nBlock \t Offset \n"); 236144961713Sgirish 236244961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 236344961713Sgirish block = 0; 2364adfcba55Sjoycey #if defined(__i386) 2365adfcba55Sjoycey base = (uint64_t)(uint32_t)nxgep->dev_regs->nxge_regp; 2366adfcba55Sjoycey #else 236744961713Sgirish base = (uint64_t)nxgep->dev_regs->nxge_regp; 2368adfcba55Sjoycey #endif 236944961713Sgirish while (reg_block[block].offset != ALL_FF_32) { 237044961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 23714045d941Ssowmini "%9s\t 0x%llx\n", 23724045d941Ssowmini reg_block[block].name, 23734045d941Ssowmini (unsigned long long)(reg_block[block].offset + base)); 237444961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 237544961713Sgirish block++; 237644961713Sgirish } 237744961713Sgirish 237844961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 23794045d941Ssowmini "\nRDC\t rcrp (rx_rcr_ring_t)\t " 23804045d941Ssowmini "rbrp (rx_rbr_ring_t)\n"); 238144961713Sgirish 238244961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 238344961713Sgirish 238444961713Sgirish for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 238544961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 23864045d941Ssowmini " %d\t $%p\t\t $%p\n", 23878793b36bSNick Todd rdc, (void *)rcr_rings[rdc], 23888793b36bSNick Todd (void *)rbr_rings[rdc]); 238944961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 239044961713Sgirish } 239144961713Sgirish 239244961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 23934045d941Ssowmini "\nTDC\t tdcp (tx_ring_t)\n"); 239444961713Sgirish 239544961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 239644961713Sgirish tx_rings = nxgep->tx_rings->rings; 2397678453a8Sspeer for (tdc = 0; tdc < p_cfgp->tdc.count; tdc++) { 239844961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 23998793b36bSNick Todd " %d\t $%p\n", tdc, (void *)tx_rings[tdc]); 240044961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 240144961713Sgirish } 240244961713Sgirish 2403a3c5bd6dSspeer print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, "\n\n"); 240444961713Sgirish 240544961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 240644961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ptrs")); 240744961713Sgirish return (0); 240844961713Sgirish } 240944961713Sgirish 241044961713Sgirish 241144961713Sgirish /* ARGSUSED */ 241244961713Sgirish int 241344961713Sgirish nxge_nd_get_names(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t param) 241444961713Sgirish { 2415a3c5bd6dSspeer ND *nd; 2416a3c5bd6dSspeer NDE *nde; 2417a3c5bd6dSspeer char *rwtag; 2418a3c5bd6dSspeer boolean_t get_ok, set_ok; 2419a3c5bd6dSspeer size_t param_len; 2420a3c5bd6dSspeer int status = 0; 242144961713Sgirish 242244961713Sgirish nd = (ND *)param; 242344961713Sgirish if (!nd) 242444961713Sgirish return (ENOENT); 242544961713Sgirish 242644961713Sgirish for (nde = nd->nd_tbl; nde->nde_name; nde++) { 242744961713Sgirish get_ok = (nde->nde_get_pfi != nxge_get_default) && 24284045d941Ssowmini (nde->nde_get_pfi != NULL); 242944961713Sgirish set_ok = (nde->nde_set_pfi != nxge_set_default) && 24304045d941Ssowmini (nde->nde_set_pfi != NULL); 243144961713Sgirish if (get_ok) { 243244961713Sgirish if (set_ok) 243344961713Sgirish rwtag = "read and write"; 243444961713Sgirish else 243544961713Sgirish rwtag = "read only"; 243644961713Sgirish } else if (set_ok) 243744961713Sgirish rwtag = "write only"; 243844961713Sgirish else { 243944961713Sgirish continue; 244044961713Sgirish } 244144961713Sgirish param_len = strlen(rwtag); 244244961713Sgirish param_len += strlen(nde->nde_name); 244344961713Sgirish param_len += 4; 244444961713Sgirish 244544961713Sgirish (void) mi_mpprintf(mp, "%s (%s)", nde->nde_name, rwtag); 244644961713Sgirish } 244744961713Sgirish return (status); 244844961713Sgirish } 244944961713Sgirish 245044961713Sgirish /* ARGSUSED */ 245144961713Sgirish int 245244961713Sgirish nxge_get_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t data) 245344961713Sgirish { 245444961713Sgirish return (EACCES); 245544961713Sgirish } 245644961713Sgirish 245744961713Sgirish /* ARGSUSED */ 245844961713Sgirish int 245944961713Sgirish nxge_set_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, char *value, 2460a3c5bd6dSspeer caddr_t data) 246144961713Sgirish { 246244961713Sgirish return (EACCES); 246344961713Sgirish } 246444961713Sgirish 24651bd6825cSml boolean_t 246644961713Sgirish nxge_param_link_update(p_nxge_t nxgep) 246744961713Sgirish { 246844961713Sgirish p_nxge_param_t param_arr; 246944961713Sgirish nxge_param_index_t i; 247044961713Sgirish boolean_t update_xcvr; 247144961713Sgirish boolean_t update_dev; 247244961713Sgirish int instance; 247344961713Sgirish boolean_t status = B_TRUE; 247444961713Sgirish 24751bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_link_update")); 247644961713Sgirish 247744961713Sgirish param_arr = nxgep->param_arr; 247844961713Sgirish instance = nxgep->instance; 247944961713Sgirish update_xcvr = B_FALSE; 248044961713Sgirish for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) { 248144961713Sgirish update_xcvr |= param_arr[i].value; 248244961713Sgirish } 248344961713Sgirish 248444961713Sgirish if (update_xcvr) { 248544961713Sgirish update_xcvr = B_FALSE; 248644961713Sgirish for (i = param_autoneg; i < param_enable_ipg0; i++) { 248744961713Sgirish update_xcvr |= 24884045d941Ssowmini (param_arr[i].value != param_arr[i].old_value); 248944961713Sgirish param_arr[i].old_value = param_arr[i].value; 249044961713Sgirish } 249144961713Sgirish if (update_xcvr) { 24921bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL, 24931bd6825cSml "==> nxge_param_link_update: update xcvr")); 249444961713Sgirish RW_ENTER_WRITER(&nxgep->filter_lock); 249544961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 249644961713Sgirish (void) nxge_link_init(nxgep); 249744961713Sgirish (void) nxge_mac_init(nxgep); 249844961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 249944961713Sgirish RW_EXIT(&nxgep->filter_lock); 250044961713Sgirish } 250144961713Sgirish } else { 250244961713Sgirish cmn_err(CE_WARN, " Last setting will leave nxge%d with " 25034045d941Ssowmini " no link capabilities.", instance); 250444961713Sgirish cmn_err(CE_WARN, " Restoring previous setting."); 250544961713Sgirish for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) 250644961713Sgirish param_arr[i].value = param_arr[i].old_value; 250744961713Sgirish } 2508a3c5bd6dSspeer 250944961713Sgirish update_dev = B_FALSE; 251044961713Sgirish 251144961713Sgirish if (update_dev) { 251244961713Sgirish RW_ENTER_WRITER(&nxgep->filter_lock); 25131bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL, 25141bd6825cSml "==> nxge_param_link_update: update dev")); 251544961713Sgirish (void) nxge_rx_mac_disable(nxgep); 251644961713Sgirish (void) nxge_tx_mac_disable(nxgep); 251744961713Sgirish (void) nxge_tx_mac_enable(nxgep); 251844961713Sgirish (void) nxge_rx_mac_enable(nxgep); 251944961713Sgirish RW_EXIT(&nxgep->filter_lock); 252044961713Sgirish } 252144961713Sgirish 252244961713Sgirish nxge_param_hw_update_exit: 252344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 25244045d941Ssowmini "<== nxge_param_link_update status = 0x%08x", status)); 252544961713Sgirish return (status); 252644961713Sgirish } 25271bd6825cSml 25281bd6825cSml /* 25291bd6825cSml * synchronize the adv* and en* parameters. 25301bd6825cSml * 25311bd6825cSml * See comments in <sys/dld.h> for details of the *_en_* 25321bd6825cSml * parameters. The usage of ndd for setting adv parameters will 25331bd6825cSml * synchronize all the en parameters with the nxge parameters, 25341bd6825cSml * implicitly disabling any settings made via dladm. 25351bd6825cSml */ 25361bd6825cSml static void 25371bd6825cSml nxge_param_sync(p_nxge_t nxgep) 25381bd6825cSml { 25391bd6825cSml p_nxge_param_t param_arr; 25401bd6825cSml param_arr = nxgep->param_arr; 25411bd6825cSml 25421bd6825cSml nxgep->param_en_pause = param_arr[param_anar_pause].value; 25431bd6825cSml nxgep->param_en_1000fdx = param_arr[param_anar_1000fdx].value; 25441bd6825cSml nxgep->param_en_100fdx = param_arr[param_anar_100fdx].value; 25451bd6825cSml nxgep->param_en_10fdx = param_arr[param_anar_10fdx].value; 25461bd6825cSml } 25471bd6825cSml 25481bd6825cSml /* ARGSUSED */ 25491bd6825cSml int 25501bd6825cSml nxge_dld_get_ip_opt(p_nxge_t nxgep, caddr_t cp) 25511bd6825cSml { 25521bd6825cSml uint32_t status, cfg_value; 25531bd6825cSml p_nxge_param_t pa = (p_nxge_param_t)cp; 25541bd6825cSml tcam_class_t class; 25551bd6825cSml 25561bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_dld_get_ip_opt")); 25571bd6825cSml 25581bd6825cSml /* do the actual hw setup */ 25591bd6825cSml class = nxge_class_name_2value(nxgep, pa->name); 25601bd6825cSml if (class == -1) 25611bd6825cSml return (EINVAL); 25621bd6825cSml 25631bd6825cSml cfg_value = 0; 25641bd6825cSml status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 25651bd6825cSml if (status != NXGE_OK) 25661bd6825cSml return (EINVAL); 25671bd6825cSml 2568*c1f9c6e5SSantwona Behera /* Filter out the allowed bits */ 2569*c1f9c6e5SSantwona Behera cfg_value &= (NXGE_CLASS_FLOW_USE_PORTNUM | NXGE_CLASS_FLOW_USE_L2DA | 2570*c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_VLAN | NXGE_CLASS_FLOW_USE_PROTO | 2571*c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_IPDST | 2572*c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_DST_PORT); 2573*c1f9c6e5SSantwona Behera 25741bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL, 25751bd6825cSml "nxge_param_get_ip_opt_get %x ", cfg_value)); 25761bd6825cSml 25771bd6825cSml pa->value = cfg_value; 25781bd6825cSml 25791bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 25801bd6825cSml return (0); 25811bd6825cSml } 2582