144961713Sgirish /*
244961713Sgirish * CDDL HEADER START
344961713Sgirish *
444961713Sgirish * The contents of this file are subject to the terms of the
544961713Sgirish * Common Development and Distribution License (the "License").
644961713Sgirish * You may not use this file except in compliance with the License.
744961713Sgirish *
844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
944961713Sgirish * or http://www.opensolaris.org/os/licensing.
1044961713Sgirish * See the License for the specific language governing permissions
1144961713Sgirish * and limitations under the License.
1244961713Sgirish *
1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each
1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the
1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying
1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner]
1844961713Sgirish *
1944961713Sgirish * CDDL HEADER END
2044961713Sgirish */
2144961713Sgirish /*
227b26d9ffSSantwona Behera * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
2344961713Sgirish * Use is subject to license terms.
2444961713Sgirish */
2544961713Sgirish
2644961713Sgirish #include <sys/nxge/nxge_impl.h>
27678453a8Sspeer #include <sys/nxge/nxge_hio.h>
28678453a8Sspeer
2944961713Sgirish #include <inet/common.h>
3044961713Sgirish #include <inet/mi.h>
3144961713Sgirish #include <inet/nd.h>
3244961713Sgirish
3344961713Sgirish extern uint64_t npi_debug_level;
3444961713Sgirish
35a3c5bd6dSspeer #define NXGE_PARAM_MAC_RW \
36a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_MAC | \
3744961713Sgirish NXGE_PARAM_NDD_WR_OK | NXGE_PARAM_READ_PROP
3844961713Sgirish
39a3c5bd6dSspeer #define NXGE_PARAM_MAC_DONT_SHOW \
40a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_MAC | NXGE_PARAM_DONT_SHOW
4144961713Sgirish
42a3c5bd6dSspeer #define NXGE_PARAM_RXDMA_RW \
43a3c5bd6dSspeer NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_NDD_WR_OK | \
44a3c5bd6dSspeer NXGE_PARAM_READ_PROP
4544961713Sgirish
46a3c5bd6dSspeer #define NXGE_PARAM_RXDMA_RWC \
47a3c5bd6dSspeer NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_INIT_ONLY | \
48a3c5bd6dSspeer NXGE_PARAM_READ_PROP
4944961713Sgirish
50a3c5bd6dSspeer #define NXGE_PARAM_L2CLASS_CFG \
51a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_READ_PROP | \
52a3c5bd6dSspeer NXGE_PARAM_NDD_WR_OK
5344961713Sgirish
54a3c5bd6dSspeer #define NXGE_PARAM_CLASS_RWS \
55a3c5bd6dSspeer NXGE_PARAM_RWS | NXGE_PARAM_READ_PROP
5644961713Sgirish
5744961713Sgirish #define NXGE_PARAM_ARRAY_INIT_SIZE 0x20ULL
5844961713Sgirish
5944961713Sgirish #define SET_RX_INTR_TIME_DISABLE 0
6044961713Sgirish #define SET_RX_INTR_TIME_ENABLE 1
6144961713Sgirish #define SET_RX_INTR_PKTS 2
6244961713Sgirish
6344961713Sgirish #define BASE_ANY 0
64*86ef0a63SRichard Lowe #define BASE_BINARY 2
6544961713Sgirish #define BASE_HEX 16
6644961713Sgirish #define BASE_DECIMAL 10
6744961713Sgirish #define ALL_FF_64 0xFFFFFFFFFFFFFFFFULL
6844961713Sgirish #define ALL_FF_32 0xFFFFFFFFUL
6944961713Sgirish
7044961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_SIZE 2048 /* is 2k enough? */
7144961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_8K 8192
7244961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_16K 0x2000
7344961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_64K 0x8000
7444961713Sgirish
7544961713Sgirish #define PARAM_OUTOF_RANGE(vptr, eptr, rval, pa) \
7644961713Sgirish ((vptr == eptr) || (rval < pa->minimum) || (rval > pa->maximum))
7744961713Sgirish
7844961713Sgirish #define ADVANCE_PRINT_BUFFER(pmp, plen, rlen) { \
7944961713Sgirish ((mblk_t *)pmp)->b_wptr += plen; \
8044961713Sgirish rlen -= plen; \
81a3c5bd6dSspeer }
8244961713Sgirish
834045d941Ssowmini int nxge_param_set_mac(p_nxge_t, queue_t *,
84a3c5bd6dSspeer mblk_t *, char *, caddr_t);
8544961713Sgirish static int nxge_param_set_port_rdc(p_nxge_t, queue_t *,
86a3c5bd6dSspeer mblk_t *, char *, caddr_t);
8744961713Sgirish static int nxge_param_set_grp_rdc(p_nxge_t, queue_t *,
88a3c5bd6dSspeer mblk_t *, char *, caddr_t);
8944961713Sgirish static int nxge_param_set_ether_usr(p_nxge_t,
90a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t);
9144961713Sgirish static int nxge_param_set_ip_usr(p_nxge_t,
92a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t);
9344961713Sgirish static int nxge_param_set_vlan_rdcgrp(p_nxge_t,
94a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t);
9544961713Sgirish static int nxge_param_set_mac_rdcgrp(p_nxge_t,
96a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t);
9744961713Sgirish static int nxge_param_fflp_hash_init(p_nxge_t,
98a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t);
9944961713Sgirish static int nxge_param_llc_snap_enable(p_nxge_t, queue_t *,
100a3c5bd6dSspeer mblk_t *, char *, caddr_t);
10144961713Sgirish static int nxge_param_hash_lookup_enable(p_nxge_t, queue_t *,
102a3c5bd6dSspeer mblk_t *, char *, caddr_t);
10344961713Sgirish static int nxge_param_tcam_enable(p_nxge_t, queue_t *,
104a3c5bd6dSspeer mblk_t *, char *, caddr_t);
10556d930aeSspeer static int nxge_param_get_fw_ver(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
1062e59129aSraghus static int nxge_param_get_port_mode(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
10744961713Sgirish static int nxge_param_get_rxdma_info(p_nxge_t, queue_t *q,
108a3c5bd6dSspeer p_mblk_t, caddr_t);
10944961713Sgirish static int nxge_param_get_txdma_info(p_nxge_t, queue_t *q,
110a3c5bd6dSspeer p_mblk_t, caddr_t);
11144961713Sgirish static int nxge_param_get_vlan_rdcgrp(p_nxge_t, queue_t *,
112a3c5bd6dSspeer p_mblk_t, caddr_t);
11344961713Sgirish static int nxge_param_get_mac_rdcgrp(p_nxge_t, queue_t *,
114a3c5bd6dSspeer p_mblk_t, caddr_t);
11544961713Sgirish static int nxge_param_get_rxdma_rdcgrp_info(p_nxge_t, queue_t *,
116a3c5bd6dSspeer p_mblk_t, caddr_t);
117c1f9c6e5SSantwona Behera static int nxge_param_get_rx_intr_time(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
118c1f9c6e5SSantwona Behera static int nxge_param_get_rx_intr_pkts(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
11944961713Sgirish static int nxge_param_get_ip_opt(p_nxge_t, queue_t *, mblk_t *, caddr_t);
120a3c5bd6dSspeer static int nxge_param_get_mac(p_nxge_t, queue_t *q, p_mblk_t, caddr_t);
12144961713Sgirish static int nxge_param_get_debug_flag(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
12244961713Sgirish static int nxge_param_set_nxge_debug_flag(p_nxge_t, queue_t *, mblk_t *,
123a3c5bd6dSspeer char *, caddr_t);
12444961713Sgirish static int nxge_param_set_npi_debug_flag(p_nxge_t,
125a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t);
12644961713Sgirish static int nxge_param_dump_rdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t);
12744961713Sgirish static int nxge_param_dump_tdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t);
12844961713Sgirish static int nxge_param_dump_mac_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
12944961713Sgirish static int nxge_param_dump_ipp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
13044961713Sgirish static int nxge_param_dump_fflp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
13144961713Sgirish static int nxge_param_dump_vlan_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
13244961713Sgirish static int nxge_param_dump_rdc_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
13344961713Sgirish static int nxge_param_dump_ptrs(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
1341bd6825cSml static void nxge_param_sync(p_nxge_t);
13544961713Sgirish
13644961713Sgirish /*
13744961713Sgirish * Global array of Neptune changable parameters.
13844961713Sgirish * This array is initialized to correspond to the default
13944961713Sgirish * Neptune 4 port configuration. This array would be copied
14044961713Sgirish * into each port's parameter structure and modifed per
14144961713Sgirish * fcode and nxge.conf configuration. Later, the parameters are
14244961713Sgirish * exported to ndd to display and run-time configuration (at least
14344961713Sgirish * some of them).
14444961713Sgirish *
14500161856Syc * Parameters with DONT_SHOW are not shown by ndd.
14600161856Syc *
14744961713Sgirish */
14844961713Sgirish
149a3c5bd6dSspeer static nxge_param_t nxge_param_arr[] = {
150a3c5bd6dSspeer /*
151a3c5bd6dSspeer * min max value old hw-name conf-name
152a3c5bd6dSspeer */
153846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
154a3c5bd6dSspeer 0, 999, 1000, 0, "instance", "instance"},
155a3c5bd6dSspeer
156846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
157a3c5bd6dSspeer 0, 999, 1000, 0, "main-instance", "main_instance"},
158a3c5bd6dSspeer
159a3c5bd6dSspeer { nxge_param_get_generic, NULL, NXGE_PARAM_READ,
160a3c5bd6dSspeer 0, 3, 0, 0, "function-number", "function_number"},
161a3c5bd6dSspeer
162a3c5bd6dSspeer /* Partition Id */
163846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
164a3c5bd6dSspeer 0, 8, 0, 0, "partition-id", "partition_id"},
165a3c5bd6dSspeer
166a3c5bd6dSspeer /* Read Write Permission Mode */
167846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
168a3c5bd6dSspeer 0, 2, 0, 0, "read-write-mode", "read_write_mode"},
169a3c5bd6dSspeer
17056d930aeSspeer { nxge_param_get_fw_ver, NULL, NXGE_PARAM_READ,
17156d930aeSspeer 0, 32, 0, 0, "version", "fw_version"},
17256d930aeSspeer
1732e59129aSraghus { nxge_param_get_port_mode, NULL, NXGE_PARAM_READ,
1742e59129aSraghus 0, 32, 0, 0, "port-mode", "port_mode"},
1752e59129aSraghus
176a3c5bd6dSspeer /* hw cfg types */
177a3c5bd6dSspeer /* control the DMA config of Neptune/NIU */
178846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
179a3c5bd6dSspeer CFG_DEFAULT, CFG_CUSTOM, CFG_DEFAULT, CFG_DEFAULT,
180a3c5bd6dSspeer "niu-cfg-type", "niu_cfg_type"},
181a3c5bd6dSspeer
182a3c5bd6dSspeer /* control the TXDMA config of the Port controlled by tx-quick-cfg */
183846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
184a3c5bd6dSspeer CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT,
185a3c5bd6dSspeer "tx-qcfg-type", "tx_qcfg_type"},
186a3c5bd6dSspeer
187a3c5bd6dSspeer /* control the RXDMA config of the Port controlled by rx-quick-cfg */
188846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
189a3c5bd6dSspeer CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT,
190a3c5bd6dSspeer "rx-qcfg-type", "rx_qcfg_type"},
191a3c5bd6dSspeer
192a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac,
193a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW,
194a3c5bd6dSspeer 0, 1, 0, 0, "master-cfg-enable", "master_cfg_enable"},
195a3c5bd6dSspeer
196a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac,
197846a903dSml NXGE_PARAM_DONT_SHOW,
198a3c5bd6dSspeer 0, 1, 0, 0, "master-cfg-value", "master_cfg_value"},
199a3c5bd6dSspeer
200a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
201a3c5bd6dSspeer 0, 1, 1, 1, "adv-autoneg-cap", "adv_autoneg_cap"},
202a3c5bd6dSspeer
203a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
204a3c5bd6dSspeer 0, 1, 1, 1, "adv-10gfdx-cap", "adv_10gfdx_cap"},
205a3c5bd6dSspeer
206a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
207a3c5bd6dSspeer 0, 1, 0, 0, "adv-10ghdx-cap", "adv_10ghdx_cap"},
208a3c5bd6dSspeer
209a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
210a3c5bd6dSspeer 0, 1, 1, 1, "adv-1000fdx-cap", "adv_1000fdx_cap"},
211a3c5bd6dSspeer
212a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
213a3c5bd6dSspeer 0, 1, 0, 0, "adv-1000hdx-cap", "adv_1000hdx_cap"},
214a3c5bd6dSspeer
215a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
216a3c5bd6dSspeer 0, 1, 0, 0, "adv-100T4-cap", "adv_100T4_cap"},
217a3c5bd6dSspeer
218a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
219a3c5bd6dSspeer 0, 1, 1, 1, "adv-100fdx-cap", "adv_100fdx_cap"},
220a3c5bd6dSspeer
221a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
222a3c5bd6dSspeer 0, 1, 0, 0, "adv-100hdx-cap", "adv_100hdx_cap"},
223a3c5bd6dSspeer
224a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
225a3c5bd6dSspeer 0, 1, 1, 1, "adv-10fdx-cap", "adv_10fdx_cap"},
226a3c5bd6dSspeer
227a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
228a3c5bd6dSspeer 0, 1, 0, 0, "adv-10hdx-cap", "adv_10hdx_cap"},
229a3c5bd6dSspeer
230846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
231a3c5bd6dSspeer 0, 1, 0, 0, "adv-asmpause-cap", "adv_asmpause_cap"},
232a3c5bd6dSspeer
233a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
234a3c5bd6dSspeer 0, 1, 0, 0, "adv-pause-cap", "adv_pause_cap"},
235a3c5bd6dSspeer
236846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
237a3c5bd6dSspeer 0, 1, 0, 0, "use-int-xcvr", "use_int_xcvr"},
238a3c5bd6dSspeer
239846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
240a3c5bd6dSspeer 0, 1, 1, 1, "enable-ipg0", "enable_ipg0"},
241a3c5bd6dSspeer
242846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
243a3c5bd6dSspeer 0, 255, 8, 8, "ipg0", "ipg0"},
244a3c5bd6dSspeer
245846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
246a3c5bd6dSspeer 0, 255, 8, 8, "ipg1", "ipg1"},
247a3c5bd6dSspeer
248846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
249a3c5bd6dSspeer 0, 255, 4, 4, "ipg2", "ipg2"},
250a3c5bd6dSspeer
251a3c5bd6dSspeer /* Transmit DMA channels */
252846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ |
253846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
254a3c5bd6dSspeer 0, 3, 0, 0, "tx-dma-weight", "tx_dma_weight"},
255a3c5bd6dSspeer
256846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ |
257846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
258a3c5bd6dSspeer 0, 31, 0, 0, "tx-dma-channels-begin", "tx_dma_channels_begin"},
259a3c5bd6dSspeer
260846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ |
261846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
262a3c5bd6dSspeer 0, 32, 0, 0, "tx-dma-channels", "tx_dma_channels"},
263a3c5bd6dSspeer { nxge_param_get_txdma_info, NULL,
264846a903dSml NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
265a3c5bd6dSspeer 0, 32, 0, 0, "tx-dma-info", "tx_dma_info"},
266a3c5bd6dSspeer
267a3c5bd6dSspeer /* Receive DMA channels */
268a3c5bd6dSspeer { nxge_param_get_generic, NULL,
269846a903dSml NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
270a3c5bd6dSspeer 0, 31, 0, 0, "rx-dma-channels-begin", "rx_dma_channels_begin"},
271a3c5bd6dSspeer
272846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ |
273846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
274a3c5bd6dSspeer 0, 32, 0, 0, "rx-dma-channels", "rx_dma_channels"},
275a3c5bd6dSspeer
276846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ |
277846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
278a3c5bd6dSspeer 0, 65535, PT_DRR_WT_DEFAULT_10G, 0,
279a3c5bd6dSspeer "rx-drr-weight", "rx_drr_weight"},
280a3c5bd6dSspeer
281846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ |
282846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
283a3c5bd6dSspeer 0, 1, 1, 0, "rx-full-header", "rx_full_header"},
284a3c5bd6dSspeer
285846a903dSml { nxge_param_get_rxdma_info, NULL, NXGE_PARAM_READ |
286846a903dSml NXGE_PARAM_DONT_SHOW,
287a3c5bd6dSspeer 0, 32, 0, 0, "rx-dma-info", "rx_dma_info"},
288a3c5bd6dSspeer
289a3c5bd6dSspeer { nxge_param_get_rxdma_info, NULL,
290a3c5bd6dSspeer NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
291a3c5bd6dSspeer NXGE_RBR_RBB_MIN, NXGE_RBR_RBB_MAX, NXGE_RBR_RBB_DEFAULT, 0,
292a3c5bd6dSspeer "rx-rbr-size", "rx_rbr_size"},
293a3c5bd6dSspeer
294a3c5bd6dSspeer { nxge_param_get_rxdma_info, NULL,
295a3c5bd6dSspeer NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
296a3c5bd6dSspeer NXGE_RCR_MIN, NXGE_RCR_MAX, NXGE_RCR_DEFAULT, 0,
297a3c5bd6dSspeer "rx-rcr-size", "rx_rcr_size"},
298a3c5bd6dSspeer
299846a903dSml { nxge_param_get_generic, nxge_param_set_port_rdc,
300846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
301a3c5bd6dSspeer 0, 15, 0, 0, "default-port-rdc", "default_port_rdc"},
302a3c5bd6dSspeer
303c1f9c6e5SSantwona Behera { nxge_param_get_rx_intr_time, nxge_param_rx_intr_time,
304c1f9c6e5SSantwona Behera NXGE_PARAM_RXDMA_RW,
305a3c5bd6dSspeer NXGE_RDC_RCR_TIMEOUT_MIN, NXGE_RDC_RCR_TIMEOUT_MAX,
3067b26d9ffSSantwona Behera NXGE_RDC_RCR_TIMEOUT, 0, "rxdma-intr-time", "rxdma_intr_time"},
307a3c5bd6dSspeer
308c1f9c6e5SSantwona Behera { nxge_param_get_rx_intr_pkts, nxge_param_rx_intr_pkts,
309c1f9c6e5SSantwona Behera NXGE_PARAM_RXDMA_RW,
310a3c5bd6dSspeer NXGE_RDC_RCR_THRESHOLD_MIN, NXGE_RDC_RCR_THRESHOLD_MAX,
3117b26d9ffSSantwona Behera NXGE_RDC_RCR_THRESHOLD, 0,
312a3c5bd6dSspeer "rxdma-intr-pkts", "rxdma_intr_pkts"},
313a3c5bd6dSspeer
314846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP |
315846a903dSml NXGE_PARAM_DONT_SHOW,
316a3c5bd6dSspeer 0, 8, 0, 0, "rx-rdc-grps-begin", "rx_rdc_grps_begin"},
317a3c5bd6dSspeer
318846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP |
319846a903dSml NXGE_PARAM_DONT_SHOW,
320a3c5bd6dSspeer 0, 8, 0, 0, "rx-rdc-grps", "rx_rdc_grps"},
321a3c5bd6dSspeer
322846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc,
323846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
324a3c5bd6dSspeer 0, 15, 0, 0, "default-grp0-rdc", "default_grp0_rdc"},
325a3c5bd6dSspeer
326846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc,
327846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
328a3c5bd6dSspeer 0, 15, 2, 0, "default-grp1-rdc", "default_grp1_rdc"},
329a3c5bd6dSspeer
330846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc,
331846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
332a3c5bd6dSspeer 0, 15, 4, 0, "default-grp2-rdc", "default_grp2_rdc"},
333a3c5bd6dSspeer
334846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc,
335846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
336a3c5bd6dSspeer 0, 15, 6, 0, "default-grp3-rdc", "default_grp3_rdc"},
337a3c5bd6dSspeer
338846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc,
339846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
340a3c5bd6dSspeer 0, 15, 8, 0, "default-grp4-rdc", "default_grp4_rdc"},
341a3c5bd6dSspeer
342846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc,
343846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
344a3c5bd6dSspeer 0, 15, 10, 0, "default-grp5-rdc", "default_grp5_rdc"},
345a3c5bd6dSspeer
346846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc,
347846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
348a3c5bd6dSspeer 0, 15, 12, 0, "default-grp6-rdc", "default_grp6_rdc"},
349a3c5bd6dSspeer
350846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc,
351846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
352a3c5bd6dSspeer 0, 15, 14, 0, "default-grp7-rdc", "default_grp7_rdc"},
353a3c5bd6dSspeer
354a3c5bd6dSspeer { nxge_param_get_rxdma_rdcgrp_info, NULL,
355846a903dSml NXGE_PARAM_READ | NXGE_PARAM_CMPLX | NXGE_PARAM_DONT_SHOW,
356a3c5bd6dSspeer 0, 8, 0, 0, "rdc-groups-info", "rdc_groups_info"},
357a3c5bd6dSspeer
358a3c5bd6dSspeer /* Logical device groups */
359846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
360a3c5bd6dSspeer 0, 63, 0, 0, "start-ldg", "start_ldg"},
361a3c5bd6dSspeer
362846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
363a3c5bd6dSspeer 0, 64, 0, 0, "max-ldg", "max_ldg" },
364a3c5bd6dSspeer
365a3c5bd6dSspeer /* MAC table information */
366a3c5bd6dSspeer { nxge_param_get_mac_rdcgrp, nxge_param_set_mac_rdcgrp,
367846a903dSml NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW,
368a3c5bd6dSspeer 0, 31, 0, 0, "mac-2rdc-grp", "mac_2rdc_grp"},
369a3c5bd6dSspeer
370a3c5bd6dSspeer /* VLAN table information */
371a3c5bd6dSspeer { nxge_param_get_vlan_rdcgrp, nxge_param_set_vlan_rdcgrp,
372846a903dSml NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW,
373a3c5bd6dSspeer 0, 31, 0, 0, "vlan-2rdc-grp", "vlan_2rdc_grp"},
374a3c5bd6dSspeer
375a3c5bd6dSspeer { nxge_param_get_generic, NULL,
376846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_READ |
377846a903dSml NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_DONT_SHOW,
378a3c5bd6dSspeer 0, 0x0ffff, 0x0ffff, 0, "fcram-part-cfg", "fcram_part_cfg"},
379a3c5bd6dSspeer
380846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS |
381846a903dSml NXGE_PARAM_DONT_SHOW,
382a3c5bd6dSspeer 0, 0x10, 0xa, 0, "fcram-access-ratio", "fcram_access_ratio"},
383a3c5bd6dSspeer
384846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS |
385846a903dSml NXGE_PARAM_DONT_SHOW,
386a3c5bd6dSspeer 0, 0x10, 0xa, 0, "tcam-access-ratio", "tcam_access_ratio"},
387a3c5bd6dSspeer
388a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_tcam_enable,
389846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
390a3c5bd6dSspeer 0, 0x1, 0x0, 0, "tcam-enable", "tcam_enable"},
391a3c5bd6dSspeer
392a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_hash_lookup_enable,
393846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
394a3c5bd6dSspeer 0, 0x01, 0x0, 0, "hash-lookup-enable", "hash_lookup_enable"},
395a3c5bd6dSspeer
396a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_llc_snap_enable,
397846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
398a3c5bd6dSspeer 0, 0x01, 0x01, 0, "llc-snap-enable", "llc_snap_enable"},
399a3c5bd6dSspeer
400a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_fflp_hash_init,
401846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
402a3c5bd6dSspeer 0, ALL_FF_32, ALL_FF_32, 0, "h1-init-value", "h1_init_value"},
403a3c5bd6dSspeer
404a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_fflp_hash_init,
405846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
406a3c5bd6dSspeer 0, 0x0ffff, 0x0ffff, 0, "h2-init-value", "h2_init_value"},
407a3c5bd6dSspeer
408a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ether_usr,
409a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
410a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0,
411a3c5bd6dSspeer "class-cfg-ether-usr1", "class_cfg_ether_usr1"},
412a3c5bd6dSspeer
413a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ether_usr,
414a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
415a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0,
416a3c5bd6dSspeer "class-cfg-ether-usr2", "class_cfg_ether_usr2"},
417a3c5bd6dSspeer
418a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr,
419a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
420a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0,
421a3c5bd6dSspeer "class-cfg-ip-usr4", "class_cfg_ip_usr4"},
422a3c5bd6dSspeer
423a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr,
424a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
425a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0,
426a3c5bd6dSspeer "class-cfg-ip-usr5", "class_cfg_ip_usr5"},
427a3c5bd6dSspeer
428a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr,
429a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
430a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0,
431a3c5bd6dSspeer "class-cfg-ip-usr6", "class_cfg_ip_usr6"},
432a3c5bd6dSspeer
433a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr,
434a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
435a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0,
436a3c5bd6dSspeer "class-cfg-ip-usr7", "class_cfg_ip_usr7"},
437a3c5bd6dSspeer
438a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt,
439a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
440a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0,
441a3c5bd6dSspeer "class-opt-ip-usr4", "class_opt_ip_usr4"},
442a3c5bd6dSspeer
443a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt,
444a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
445a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0,
446a3c5bd6dSspeer "class-opt-ip-usr5", "class_opt_ip_usr5"},
447a3c5bd6dSspeer
448a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt,
449a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
450a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0,
451a3c5bd6dSspeer "class-opt-ip-usr6", "class_opt_ip_usr6"},
452a3c5bd6dSspeer
453a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt,
454a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
455a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0,
456a3c5bd6dSspeer "class-opt-ip-usr7", "class_opt_ip_usr7"},
457a3c5bd6dSspeer
458a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt,
459a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS,
460a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
461a3c5bd6dSspeer "class-opt-ipv4-tcp", "class_opt_ipv4_tcp"},
462a3c5bd6dSspeer
463a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt,
464a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS,
465a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
466a3c5bd6dSspeer "class-opt-ipv4-udp", "class_opt_ipv4_udp"},
467a3c5bd6dSspeer
468a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt,
469a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS,
470a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
471a3c5bd6dSspeer "class-opt-ipv4-ah", "class_opt_ipv4_ah"},
472a3c5bd6dSspeer
473a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt,
474a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS,
475a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
476a3c5bd6dSspeer "class-opt-ipv4-sctp", "class_opt_ipv4_sctp"},
477a3c5bd6dSspeer
478a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS,
479a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
480a3c5bd6dSspeer "class-opt-ipv6-tcp", "class_opt_ipv6_tcp"},
481a3c5bd6dSspeer
482a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS,
483a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
484a3c5bd6dSspeer "class-opt-ipv6-udp", "class_opt_ipv6_udp"},
485a3c5bd6dSspeer
486a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS,
487a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
488a3c5bd6dSspeer "class-opt-ipv6-ah", "class_opt_ipv6_ah"},
489a3c5bd6dSspeer
490a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS,
491a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
492a3c5bd6dSspeer "class-opt-ipv6-sctp", "class_opt_ipv6_sctp"},
493a3c5bd6dSspeer
494a3c5bd6dSspeer { nxge_param_get_debug_flag, nxge_param_set_nxge_debug_flag,
495846a903dSml NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW,
496a3c5bd6dSspeer 0ULL, ALL_FF_64, 0ULL, 0ULL,
497a3c5bd6dSspeer "nxge-debug-flag", "nxge_debug_flag"},
498a3c5bd6dSspeer
499a3c5bd6dSspeer { nxge_param_get_debug_flag, nxge_param_set_npi_debug_flag,
500846a903dSml NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW,
501a3c5bd6dSspeer 0ULL, ALL_FF_64, 0ULL, 0ULL,
502a3c5bd6dSspeer "npi-debug-flag", "npi_debug_flag"},
503a3c5bd6dSspeer
504846a903dSml { nxge_param_dump_tdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
505a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-tdc", "dump_tdc"},
506a3c5bd6dSspeer
507846a903dSml { nxge_param_dump_rdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
508a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-rdc", "dump_rdc"},
509a3c5bd6dSspeer
510846a903dSml { nxge_param_dump_mac_regs, NULL, NXGE_PARAM_READ |
511846a903dSml NXGE_PARAM_DONT_SHOW,
512a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-mac-regs", "dump_mac_regs"},
513a3c5bd6dSspeer
514846a903dSml { nxge_param_dump_ipp_regs, NULL, NXGE_PARAM_READ |
515846a903dSml NXGE_PARAM_DONT_SHOW,
516a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-ipp-regs", "dump_ipp_regs"},
517a3c5bd6dSspeer
518846a903dSml { nxge_param_dump_fflp_regs, NULL, NXGE_PARAM_READ |
519846a903dSml NXGE_PARAM_DONT_SHOW,
520a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0,
521a3c5bd6dSspeer "dump-fflp-regs", "dump_fflp_regs"},
522a3c5bd6dSspeer
523846a903dSml { nxge_param_dump_vlan_table, NULL, NXGE_PARAM_READ |
524846a903dSml NXGE_PARAM_DONT_SHOW,
525a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0,
526a3c5bd6dSspeer "dump-vlan-table", "dump_vlan_table"},
527a3c5bd6dSspeer
528846a903dSml { nxge_param_dump_rdc_table, NULL, NXGE_PARAM_READ |
529846a903dSml NXGE_PARAM_DONT_SHOW,
530a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0,
531a3c5bd6dSspeer "dump-rdc-table", "dump_rdc_table"},
532a3c5bd6dSspeer
533846a903dSml { nxge_param_dump_ptrs, NULL, NXGE_PARAM_READ |
534846a903dSml NXGE_PARAM_DONT_SHOW,
535a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-ptrs", "dump_ptrs"},
536a3c5bd6dSspeer
537a3c5bd6dSspeer { NULL, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
538a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "end", "end"},
53944961713Sgirish };
54044961713Sgirish
541*86ef0a63SRichard Lowe extern void *nxge_list;
54244961713Sgirish
54344961713Sgirish void
nxge_get_param_soft_properties(p_nxge_t nxgep)54444961713Sgirish nxge_get_param_soft_properties(p_nxge_t nxgep)
54544961713Sgirish {
54644961713Sgirish
547*86ef0a63SRichard Lowe p_nxge_param_t param_arr;
548*86ef0a63SRichard Lowe uint_t prop_len;
549*86ef0a63SRichard Lowe int i, j;
550a3c5bd6dSspeer uint32_t param_count;
551a3c5bd6dSspeer uint32_t *int_prop_val;
55244961713Sgirish
55344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, " ==> nxge_get_param_soft_properties"));
55444961713Sgirish
55544961713Sgirish param_arr = nxgep->param_arr;
55644961713Sgirish param_count = nxgep->param_count;
55744961713Sgirish for (i = 0; i < param_count; i++) {
55844961713Sgirish if ((param_arr[i].type & NXGE_PARAM_READ_PROP) == 0)
55944961713Sgirish continue;
56044961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PROP_STR))
56144961713Sgirish continue;
56244961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) ||
5634045d941Ssowmini (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) {
56444961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY,
5654045d941Ssowmini nxgep->dip, 0, param_arr[i].fcode_name,
5664045d941Ssowmini (int **)&int_prop_val,
5674045d941Ssowmini (uint_t *)&prop_len)
5684045d941Ssowmini == DDI_PROP_SUCCESS) {
56944961713Sgirish uint32_t *cfg_value;
57044961713Sgirish uint64_t prop_count;
571a3c5bd6dSspeer
57244961713Sgirish if (prop_len > NXGE_PARAM_ARRAY_INIT_SIZE)
57344961713Sgirish prop_len = NXGE_PARAM_ARRAY_INIT_SIZE;
57444961713Sgirish cfg_value = (uint32_t *)param_arr[i].value;
57544961713Sgirish for (j = 0; j < prop_len; j++) {
57644961713Sgirish cfg_value[j] = int_prop_val[j];
57744961713Sgirish }
57844961713Sgirish prop_count = prop_len;
57944961713Sgirish param_arr[i].type |=
58044961713Sgirish (prop_count << NXGE_PARAM_ARRAY_CNT_SHIFT);
58144961713Sgirish ddi_prop_free(int_prop_val);
58244961713Sgirish }
58344961713Sgirish continue;
58444961713Sgirish }
58544961713Sgirish
58644961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
5874045d941Ssowmini param_arr[i].fcode_name,
5884045d941Ssowmini (int **)&int_prop_val,
5894045d941Ssowmini &prop_len) == DDI_PROP_SUCCESS) {
59044961713Sgirish if ((*int_prop_val >= param_arr[i].minimum) &&
5914045d941Ssowmini (*int_prop_val <= param_arr[i].maximum))
59244961713Sgirish param_arr[i].value = *int_prop_val;
59344961713Sgirish #ifdef NXGE_DEBUG_ERROR
59444961713Sgirish else {
59544961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL,
5964045d941Ssowmini "nxge%d: 'prom' file parameter error\n",
5974045d941Ssowmini nxgep->instance));
59844961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL,
5994045d941Ssowmini "Parameter keyword '%s'"
6004045d941Ssowmini " is outside valid range\n",
6014045d941Ssowmini param_arr[i].name));
60244961713Sgirish }
60344961713Sgirish #endif
60444961713Sgirish ddi_prop_free(int_prop_val);
60544961713Sgirish }
60644961713Sgirish
60744961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
6084045d941Ssowmini param_arr[i].name,
6094045d941Ssowmini (int **)&int_prop_val,
6104045d941Ssowmini &prop_len) == DDI_PROP_SUCCESS) {
61144961713Sgirish if ((*int_prop_val >= param_arr[i].minimum) &&
6124045d941Ssowmini (*int_prop_val <= param_arr[i].maximum))
61344961713Sgirish param_arr[i].value = *int_prop_val;
61444961713Sgirish #ifdef NXGE_DEBUG_ERROR
61544961713Sgirish else {
61644961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL,
6174045d941Ssowmini "nxge%d: 'conf' file parameter error\n",
6184045d941Ssowmini nxgep->instance));
61944961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL,
6204045d941Ssowmini "Parameter keyword '%s'"
6214045d941Ssowmini "is outside valid range\n",
6224045d941Ssowmini param_arr[i].name));
62344961713Sgirish }
62444961713Sgirish #endif
62544961713Sgirish ddi_prop_free(int_prop_val);
62644961713Sgirish }
62744961713Sgirish }
62844961713Sgirish }
62944961713Sgirish
63044961713Sgirish static int
nxge_private_param_register(p_nxge_t nxgep,p_nxge_param_t param_arr)63144961713Sgirish nxge_private_param_register(p_nxge_t nxgep, p_nxge_param_t param_arr)
63244961713Sgirish {
63344961713Sgirish int status = B_TRUE;
63444961713Sgirish int channel;
63544961713Sgirish uint8_t grp;
63644961713Sgirish char *prop_name;
63744961713Sgirish char *end;
63844961713Sgirish uint32_t name_chars;
63944961713Sgirish
64044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL,
6414045d941Ssowmini "nxge_private_param_register %s", param_arr->name));
64244961713Sgirish
64344961713Sgirish if ((param_arr->type & NXGE_PARAM_PRIV) != NXGE_PARAM_PRIV)
64444961713Sgirish return (B_TRUE);
645a3c5bd6dSspeer
64644961713Sgirish prop_name = param_arr->name;
64744961713Sgirish if (param_arr->type & NXGE_PARAM_RXDMA) {
64844961713Sgirish if (strncmp("rxdma_intr", prop_name, 10) == 0)
64944961713Sgirish return (B_TRUE);
65044961713Sgirish name_chars = strlen("default_grp");
65144961713Sgirish if (strncmp("default_grp", prop_name, name_chars) == 0) {
65244961713Sgirish prop_name += name_chars;
65344961713Sgirish grp = mi_strtol(prop_name, &end, 10);
65444961713Sgirish /* now check if this rdcgrp is in config */
65544961713Sgirish return (nxge_check_rdcgrp_port_member(nxgep, grp));
65644961713Sgirish }
65744961713Sgirish name_chars = strlen(prop_name);
65844961713Sgirish if (strncmp("default_port_rdc", prop_name, name_chars) == 0) {
65944961713Sgirish return (B_TRUE);
66044961713Sgirish }
66144961713Sgirish return (B_FALSE);
66244961713Sgirish }
66344961713Sgirish
66444961713Sgirish if (param_arr->type & NXGE_PARAM_TXDMA) {
66544961713Sgirish name_chars = strlen("txdma");
66644961713Sgirish if (strncmp("txdma", prop_name, name_chars) == 0) {
66744961713Sgirish prop_name += name_chars;
66844961713Sgirish channel = mi_strtol(prop_name, &end, 10);
66944961713Sgirish /* now check if this rdc is in config */
67044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL,
6714045d941Ssowmini " nxge_private_param_register: %d",
6724045d941Ssowmini channel));
67344961713Sgirish return (nxge_check_txdma_port_member(nxgep, channel));
67444961713Sgirish }
67544961713Sgirish return (B_FALSE);
67644961713Sgirish }
67744961713Sgirish
67844961713Sgirish status = B_FALSE;
67944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, "<== nxge_private_param_register"));
68044961713Sgirish
68144961713Sgirish return (status);
68244961713Sgirish }
68344961713Sgirish
68444961713Sgirish void
nxge_setup_param(p_nxge_t nxgep)68544961713Sgirish nxge_setup_param(p_nxge_t nxgep)
68644961713Sgirish {
68744961713Sgirish p_nxge_param_t param_arr;
68844961713Sgirish int i;
68944961713Sgirish pfi_t set_pfi;
69044961713Sgirish
69144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_setup_param"));
692a3c5bd6dSspeer
69344961713Sgirish /*
69444961713Sgirish * Make sure the param_instance is set to a valid device instance.
69544961713Sgirish */
69644961713Sgirish if (nxge_param_arr[param_instance].value == 1000)
69744961713Sgirish nxge_param_arr[param_instance].value = nxgep->instance;
69844961713Sgirish
69944961713Sgirish param_arr = nxgep->param_arr;
70044961713Sgirish param_arr[param_instance].value = nxgep->instance;
70144961713Sgirish param_arr[param_function_number].value = nxgep->function_num;
70244961713Sgirish
70344961713Sgirish for (i = 0; i < nxgep->param_count; i++) {
70444961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PRIV) &&
7054045d941Ssowmini (nxge_private_param_register(nxgep,
7064045d941Ssowmini ¶m_arr[i]) == B_FALSE)) {
70744961713Sgirish param_arr[i].setf = NULL;
70844961713Sgirish param_arr[i].getf = NULL;
70944961713Sgirish }
71044961713Sgirish
71144961713Sgirish if (param_arr[i].type & NXGE_PARAM_CMPLX)
71244961713Sgirish param_arr[i].setf = NULL;
71344961713Sgirish
71444961713Sgirish if (param_arr[i].type & NXGE_PARAM_DONT_SHOW) {
71544961713Sgirish param_arr[i].setf = NULL;
71644961713Sgirish param_arr[i].getf = NULL;
71744961713Sgirish }
71844961713Sgirish
71944961713Sgirish set_pfi = (pfi_t)param_arr[i].setf;
72044961713Sgirish
721a3c5bd6dSspeer if ((set_pfi) && (param_arr[i].type & NXGE_PARAM_INIT_ONLY)) {
72244961713Sgirish set_pfi = NULL;
72344961713Sgirish }
72444961713Sgirish
72544961713Sgirish }
72644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_setup_param"));
72744961713Sgirish }
72844961713Sgirish
72944961713Sgirish void
nxge_init_param(p_nxge_t nxgep)73044961713Sgirish nxge_init_param(p_nxge_t nxgep)
73144961713Sgirish {
73244961713Sgirish p_nxge_param_t param_arr;
73344961713Sgirish int i, alloc_size;
73444961713Sgirish uint64_t alloc_count;
73544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_init_param"));
73644961713Sgirish /*
73744961713Sgirish * Make sure the param_instance is set to a valid device instance.
73844961713Sgirish */
73944961713Sgirish if (nxge_param_arr[param_instance].value == 1000)
74044961713Sgirish nxge_param_arr[param_instance].value = nxgep->instance;
74144961713Sgirish
74244961713Sgirish param_arr = nxgep->param_arr;
74344961713Sgirish if (param_arr == NULL) {
744a3c5bd6dSspeer param_arr = (p_nxge_param_t)
7454045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_param_arr), KM_SLEEP);
74644961713Sgirish }
747a3c5bd6dSspeer
74844961713Sgirish for (i = 0; i < sizeof (nxge_param_arr)/sizeof (nxge_param_t); i++) {
74944961713Sgirish param_arr[i] = nxge_param_arr[i];
75044961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) ||
7514045d941Ssowmini (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) {
75244961713Sgirish alloc_count = NXGE_PARAM_ARRAY_INIT_SIZE;
75344961713Sgirish alloc_size = alloc_count * sizeof (uint64_t);
75444961713Sgirish param_arr[i].value =
755*86ef0a63SRichard Lowe (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP);
75644961713Sgirish param_arr[i].old_value =
757*86ef0a63SRichard Lowe (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP);
75844961713Sgirish param_arr[i].type |=
7594045d941Ssowmini (alloc_count << NXGE_PARAM_ARRAY_ALLOC_SHIFT);
76044961713Sgirish }
76144961713Sgirish }
76244961713Sgirish
76344961713Sgirish nxgep->param_arr = param_arr;
76444961713Sgirish nxgep->param_count = sizeof (nxge_param_arr)/sizeof (nxge_param_t);
7651bd6825cSml
7661bd6825cSml nxge_param_sync(nxgep);
7671bd6825cSml
76844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init_param: count %d",
7694045d941Ssowmini nxgep->param_count));
77044961713Sgirish }
77144961713Sgirish
77244961713Sgirish void
nxge_destroy_param(p_nxge_t nxgep)77344961713Sgirish nxge_destroy_param(p_nxge_t nxgep)
77444961713Sgirish {
77544961713Sgirish int i;
77644961713Sgirish uint64_t free_size, free_count;
77744961713Sgirish
77844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_param"));
779a3c5bd6dSspeer
78059ac0c16Sdavemq if (nxgep->param_arr == NULL)
78159ac0c16Sdavemq return;
78244961713Sgirish /*
78344961713Sgirish * Make sure the param_instance is set to a valid device instance.
78444961713Sgirish */
78544961713Sgirish if (nxge_param_arr[param_instance].value == nxgep->instance) {
78644961713Sgirish for (i = 0; i <= nxge_param_arr[param_instance].maximum; i++) {
78744961713Sgirish if ((ddi_get_soft_state(nxge_list, i) != NULL) &&
7884045d941Ssowmini (i != nxgep->instance))
78944961713Sgirish break;
79044961713Sgirish }
79144961713Sgirish nxge_param_arr[param_instance].value = i;
79244961713Sgirish }
79344961713Sgirish
79444961713Sgirish for (i = 0; i < nxgep->param_count; i++)
79544961713Sgirish if ((nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR32) ||
7964045d941Ssowmini (nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR64)) {
79744961713Sgirish free_count = ((nxgep->param_arr[i].type &
7984045d941Ssowmini NXGE_PARAM_ARRAY_ALLOC_MASK) >>
7994045d941Ssowmini NXGE_PARAM_ARRAY_ALLOC_SHIFT);
80044961713Sgirish free_count = NXGE_PARAM_ARRAY_INIT_SIZE;
80144961713Sgirish free_size = sizeof (uint64_t) * free_count;
80244961713Sgirish KMEM_FREE((void *)nxgep->param_arr[i].value, free_size);
80344961713Sgirish KMEM_FREE((void *)nxgep->param_arr[i].old_value,
8044045d941Ssowmini free_size);
80544961713Sgirish }
80644961713Sgirish
80744961713Sgirish KMEM_FREE(nxgep->param_arr, sizeof (nxge_param_arr));
80844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_param"));
80944961713Sgirish }
81044961713Sgirish
81144961713Sgirish /*
81244961713Sgirish * Extracts the value from the 'nxge' parameter array and prints the
81344961713Sgirish * parameter value. cp points to the required parameter.
81444961713Sgirish */
815a3c5bd6dSspeer
81644961713Sgirish /* ARGSUSED */
81744961713Sgirish int
nxge_param_get_generic(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)81844961713Sgirish nxge_param_get_generic(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
81944961713Sgirish {
82044961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp;
82144961713Sgirish
822a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL,
8234045d941Ssowmini "==> nxge_param_get_generic name %s ", pa->name));
82444961713Sgirish
82544961713Sgirish if (pa->value > 0xffffffff)
826a3c5bd6dSspeer (void) mi_mpprintf(mp, "%x%x",
8274045d941Ssowmini (int)(pa->value >> 32), (int)(pa->value & 0xffffffff));
82844961713Sgirish else
82944961713Sgirish (void) mi_mpprintf(mp, "%x", (int)pa->value);
83044961713Sgirish
83144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_generic"));
83244961713Sgirish return (0);
83344961713Sgirish }
83444961713Sgirish
83544961713Sgirish /* ARGSUSED */
83644961713Sgirish static int
nxge_param_get_mac(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)83744961713Sgirish nxge_param_get_mac(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
83844961713Sgirish {
83944961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp;
84044961713Sgirish
84144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac"));
84244961713Sgirish
84344961713Sgirish (void) mi_mpprintf(mp, "%d", (uint32_t)pa->value);
84444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_mac"));
84544961713Sgirish return (0);
84644961713Sgirish }
84744961713Sgirish
84856d930aeSspeer /* ARGSUSED */
84956d930aeSspeer static int
nxge_param_get_fw_ver(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)85056d930aeSspeer nxge_param_get_fw_ver(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
85156d930aeSspeer {
85256d930aeSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_fw_ver"));
85356d930aeSspeer
85456d930aeSspeer (void) mi_mpprintf(mp, "Firmware version for nxge%d: %s\n",
85556d930aeSspeer nxgep->instance, nxgep->vpd_info.ver);
85656d930aeSspeer
85756d930aeSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_fw_ver"));
85856d930aeSspeer return (0);
85956d930aeSspeer }
86056d930aeSspeer
8612e59129aSraghus /* ARGSUSED */
8622e59129aSraghus static int
nxge_param_get_port_mode(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)8632e59129aSraghus nxge_param_get_port_mode(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
8642e59129aSraghus {
8652e59129aSraghus NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_port_mode"));
8662e59129aSraghus
8672e59129aSraghus switch (nxgep->mac.portmode) {
8682e59129aSraghus case PORT_1G_COPPER:
8692d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Copper %s\n",
8702d17280bSsbehera nxgep->instance,
8712d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
8722e59129aSraghus break;
8732e59129aSraghus case PORT_1G_FIBER:
8742d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Fiber %s\n",
8752d17280bSsbehera nxgep->instance,
8762d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
8772e59129aSraghus break;
8782e59129aSraghus case PORT_10G_COPPER:
8792d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Copper "
8802d17280bSsbehera "%s\n", nxgep->instance,
8812d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
8822e59129aSraghus break;
8832e59129aSraghus case PORT_10G_FIBER:
8842d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Fiber %s\n",
8852d17280bSsbehera nxgep->instance,
8862d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
8872e59129aSraghus break;
8882e59129aSraghus case PORT_10G_SERDES:
8892d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Serdes "
8902d17280bSsbehera "%s\n", nxgep->instance,
8912d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
8922e59129aSraghus break;
8932e59129aSraghus case PORT_1G_SERDES:
8942d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Serdes %s\n",
8952d17280bSsbehera nxgep->instance,
8962d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
8972e59129aSraghus break;
8982e59129aSraghus case PORT_1G_RGMII_FIBER:
8992e59129aSraghus (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G RGMII "
9002d17280bSsbehera "Fiber %s\n", nxgep->instance,
9012d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
9022d17280bSsbehera break;
9032d17280bSsbehera case PORT_HSP_MODE:
9042d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: Hot Swappable "
9052d17280bSsbehera "PHY, Currently NOT present\n", nxgep->instance);
9062e59129aSraghus break;
90700161856Syc case PORT_10G_TN1010:
90800161856Syc (void) mi_mpprintf(mp, "Port mode for nxge%d:"
90900161856Syc " 10G Copper with TN1010 %s\n", nxgep->instance,
91000161856Syc nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
91100161856Syc break;
91200161856Syc case PORT_1G_TN1010:
913c6e5ef56Syc (void) mi_mpprintf(mp, "Port mode for nxge%d:"
91400161856Syc " 1G Copper with TN1010 %s\n", nxgep->instance,
91500161856Syc nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
91600161856Syc break;
9172e59129aSraghus default:
9182d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: Unknown %s\n",
9192d17280bSsbehera nxgep->instance,
9202d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
9212e59129aSraghus break;
9222e59129aSraghus }
9232e59129aSraghus
9243d16f8e7Sml (void) mi_mpprintf(mp, "Software LSO for nxge%d: %s\n",
9253d16f8e7Sml nxgep->instance,
9263d16f8e7Sml nxgep->soft_lso_enable ? "enable" : "disable");
9273d16f8e7Sml
9282e59129aSraghus NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_port_mode"));
9292e59129aSraghus return (0);
9302e59129aSraghus }
9312e59129aSraghus
932c1f9c6e5SSantwona Behera /* ARGSUSED */
933c1f9c6e5SSantwona Behera static int
nxge_param_get_rx_intr_time(p_nxge_t nxgep,queue_t * q,mblk_t * mp,caddr_t cp)934c1f9c6e5SSantwona Behera nxge_param_get_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, caddr_t cp)
935c1f9c6e5SSantwona Behera {
936c1f9c6e5SSantwona Behera p_nxge_param_t pa = (p_nxge_param_t)cp;
937c1f9c6e5SSantwona Behera
938c1f9c6e5SSantwona Behera NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rx_intr_time"));
939c1f9c6e5SSantwona Behera
940c1f9c6e5SSantwona Behera pa->value = (uint32_t)nxgep->intr_timeout;
941c1f9c6e5SSantwona Behera (void) mi_mpprintf(mp, "%d", (uint32_t)nxgep->intr_timeout);
942c1f9c6e5SSantwona Behera
943c1f9c6e5SSantwona Behera NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rx_intr_time"));
944c1f9c6e5SSantwona Behera return (0);
945c1f9c6e5SSantwona Behera }
946c1f9c6e5SSantwona Behera
947c1f9c6e5SSantwona Behera /* ARGSUSED */
948c1f9c6e5SSantwona Behera static int
nxge_param_get_rx_intr_pkts(p_nxge_t nxgep,queue_t * q,mblk_t * mp,caddr_t cp)949c1f9c6e5SSantwona Behera nxge_param_get_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, caddr_t cp)
950c1f9c6e5SSantwona Behera {
951c1f9c6e5SSantwona Behera p_nxge_param_t pa = (p_nxge_param_t)cp;
952c1f9c6e5SSantwona Behera
953c1f9c6e5SSantwona Behera NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rx_intr_pkts"));
954c1f9c6e5SSantwona Behera
955c1f9c6e5SSantwona Behera pa->value = (uint32_t)nxgep->intr_threshold;
956c1f9c6e5SSantwona Behera (void) mi_mpprintf(mp, "%d", (uint32_t)nxgep->intr_threshold);
957c1f9c6e5SSantwona Behera
958c1f9c6e5SSantwona Behera NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rx_intr_pkts"));
959c1f9c6e5SSantwona Behera return (0);
960c1f9c6e5SSantwona Behera }
961c1f9c6e5SSantwona Behera
96244961713Sgirish /* ARGSUSED */
96344961713Sgirish int
nxge_param_get_txdma_info(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)96444961713Sgirish nxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
96544961713Sgirish {
96644961713Sgirish
967678453a8Sspeer uint_t print_len, buf_len;
96844961713Sgirish p_mblk_t np;
96944961713Sgirish
97044961713Sgirish int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE;
971678453a8Sspeer int tdc;
972678453a8Sspeer
973678453a8Sspeer nxge_grp_set_t *set;
974678453a8Sspeer
97544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_txdma_info"));
97644961713Sgirish
977a3c5bd6dSspeer (void) mi_mpprintf(mp, "TXDMA Information for Port\t %d \n",
9784045d941Ssowmini nxgep->function_num);
97944961713Sgirish
98044961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
98144961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer");
98244961713Sgirish return (0);
98344961713Sgirish }
98444961713Sgirish
98544961713Sgirish buf_len = buff_alloc_size;
98644961713Sgirish mp->b_cont = np;
987678453a8Sspeer print_len = 0;
98844961713Sgirish
98944961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
9904045d941Ssowmini "TDC\t HW TDC\t\n");
99144961713Sgirish ((mblk_t *)np)->b_wptr += print_len;
99244961713Sgirish buf_len -= print_len;
993678453a8Sspeer
994678453a8Sspeer set = &nxgep->tx_set;
995da14cebeSEric Cheng for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) {
996678453a8Sspeer if ((1 << tdc) & set->owned.map) {
997678453a8Sspeer print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
998678453a8Sspeer buf_len, "%d\n", tdc);
999678453a8Sspeer ((mblk_t *)np)->b_wptr += print_len;
1000678453a8Sspeer buf_len -= print_len;
1001678453a8Sspeer }
100244961713Sgirish }
1003a3c5bd6dSspeer
100444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_txdma_info"));
100544961713Sgirish return (0);
100644961713Sgirish }
100744961713Sgirish
100844961713Sgirish /* ARGSUSED */
100944961713Sgirish int
nxge_param_get_rxdma_info(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)101044961713Sgirish nxge_param_get_rxdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
101144961713Sgirish {
1012a3c5bd6dSspeer uint_t print_len, buf_len;
1013a3c5bd6dSspeer p_mblk_t np;
1014a3c5bd6dSspeer int rdc;
101544961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp;
101644961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp;
1017a3c5bd6dSspeer int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE;
1018*86ef0a63SRichard Lowe p_rx_rcr_rings_t rx_rcr_rings;
101944961713Sgirish p_rx_rcr_ring_t *rcr_rings;
1020*86ef0a63SRichard Lowe p_rx_rbr_rings_t rx_rbr_rings;
102144961713Sgirish p_rx_rbr_ring_t *rbr_rings;
1022678453a8Sspeer nxge_grp_set_t *set;
102344961713Sgirish
102444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rxdma_info"));
102544961713Sgirish
1026a3c5bd6dSspeer (void) mi_mpprintf(mp, "RXDMA Information for Port\t %d \n",
10274045d941Ssowmini nxgep->function_num);
102844961713Sgirish
102944961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
103044961713Sgirish /* The following may work even if we cannot get a large buf. */
103144961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer");
103244961713Sgirish return (0);
103344961713Sgirish }
103444961713Sgirish
103544961713Sgirish buf_len = buff_alloc_size;
103644961713Sgirish mp->b_cont = np;
103744961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
103844961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
103944961713Sgirish
104044961713Sgirish rx_rcr_rings = nxgep->rx_rcr_rings;
104144961713Sgirish rcr_rings = rx_rcr_rings->rcr_rings;
104244961713Sgirish rx_rbr_rings = nxgep->rx_rbr_rings;
104344961713Sgirish rbr_rings = rx_rbr_rings->rbr_rings;
104444961713Sgirish
104544961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
10464045d941Ssowmini "Total RDCs\t %d\n", p_cfgp->max_rdcs);
104744961713Sgirish
104844961713Sgirish ((mblk_t *)np)->b_wptr += print_len;
104944961713Sgirish buf_len -= print_len;
105044961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
10514045d941Ssowmini "RDC\t HW RDC\t Timeout\t Packets RBR ptr \t"
10524045d941Ssowmini "chunks\t RCR ptr\n");
1053a3c5bd6dSspeer
105444961713Sgirish ((mblk_t *)np)->b_wptr += print_len;
105544961713Sgirish buf_len -= print_len;
1056678453a8Sspeer
1057678453a8Sspeer set = &nxgep->rx_set;
1058678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) {
1059678453a8Sspeer if ((1 << rdc) & set->owned.map) {
1060678453a8Sspeer print_len = snprintf((char *)
1061678453a8Sspeer ((mblk_t *)np)->b_wptr, buf_len,
1062678453a8Sspeer " %d\t %x\t\t %x\t $%p\t 0x%x\t $%p\n",
1063678453a8Sspeer rdc,
1064678453a8Sspeer p_dma_cfgp->rcr_timeout[rdc],
1065678453a8Sspeer p_dma_cfgp->rcr_threshold[rdc],
10668793b36bSNick Todd (void *)rbr_rings[rdc],
10678793b36bSNick Todd rbr_rings[rdc]->num_blocks, (void *)rcr_rings[rdc]);
1068a3c5bd6dSspeer ((mblk_t *)np)->b_wptr += print_len;
1069a3c5bd6dSspeer buf_len -= print_len;
1070678453a8Sspeer }
107144961713Sgirish }
1072a3c5bd6dSspeer
107344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rxdma_info"));
107444961713Sgirish return (0);
107544961713Sgirish }
107644961713Sgirish
107744961713Sgirish /* ARGSUSED */
107844961713Sgirish int
nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)107944961713Sgirish nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep, queue_t *q,
1080fe054a6cSToomas Soome p_mblk_t mp, caddr_t cp)
108144961713Sgirish {
1082a3c5bd6dSspeer uint_t print_len, buf_len;
1083a3c5bd6dSspeer p_mblk_t np;
1084a3c5bd6dSspeer int offset, rdc, i, rdc_grp;
108544961713Sgirish p_nxge_rdc_grp_t rdc_grp_p;
108644961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp;
108744961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp;
108844961713Sgirish
108944961713Sgirish int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE;
109044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL,
10914045d941Ssowmini "==> nxge_param_get_rxdma_rdcgrp_info"));
109244961713Sgirish
109344961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
109444961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
109544961713Sgirish
1096a3c5bd6dSspeer (void) mi_mpprintf(mp, "RXDMA RDC Group Information for Port\t %d \n",
10974045d941Ssowmini nxgep->function_num);
109844961713Sgirish
1099678453a8Sspeer rdc_grp = p_cfgp->def_mac_rxdma_grpid;
110044961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
110144961713Sgirish /* The following may work even if we cannot get a large buf. */
110244961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer");
110344961713Sgirish return (0);
110444961713Sgirish }
110544961713Sgirish
110644961713Sgirish buf_len = buff_alloc_size;
110744961713Sgirish mp->b_cont = np;
110844961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
11094045d941Ssowmini "Total RDC Groups\t %d \n"
11104045d941Ssowmini "default RDC group\t %d\n",
11114045d941Ssowmini p_cfgp->max_rdc_grpids,
11124045d941Ssowmini p_cfgp->def_mac_rxdma_grpid);
111344961713Sgirish
111444961713Sgirish ((mblk_t *)np)->b_wptr += print_len;
111544961713Sgirish buf_len -= print_len;
111644961713Sgirish
11177b26d9ffSSantwona Behera for (i = 0; i < NXGE_MAX_RDC_GROUPS; i++) {
1118678453a8Sspeer if (p_cfgp->grpids[i]) {
1119678453a8Sspeer rdc_grp_p = &p_dma_cfgp->rdc_grps[i];
112044961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1121678453a8Sspeer buf_len,
1122678453a8Sspeer "\nRDC Group Info for Group [%d] %d\n"
1123678453a8Sspeer "RDC Count %d\tstart RDC %d\n"
1124678453a8Sspeer "RDC Group Population Information"
1125678453a8Sspeer " (offsets 0 - 15)\n",
1126678453a8Sspeer i, rdc_grp, rdc_grp_p->max_rdcs,
1127678453a8Sspeer rdc_grp_p->start_rdc);
1128678453a8Sspeer
1129678453a8Sspeer ((mblk_t *)np)->b_wptr += print_len;
1130678453a8Sspeer buf_len -= print_len;
1131678453a8Sspeer print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1132678453a8Sspeer buf_len, "\n");
1133678453a8Sspeer ((mblk_t *)np)->b_wptr += print_len;
1134678453a8Sspeer buf_len -= print_len;
1135678453a8Sspeer
1136678453a8Sspeer for (rdc = 0; rdc < rdc_grp_p->max_rdcs; rdc++) {
1137678453a8Sspeer print_len = snprintf(
11384045d941Ssowmini (char *)((mblk_t *)np)->b_wptr,
11394045d941Ssowmini buf_len, "[%d]=%d ", rdc,
11404045d941Ssowmini rdc_grp_p->start_rdc + rdc);
1141678453a8Sspeer ((mblk_t *)np)->b_wptr += print_len;
1142678453a8Sspeer buf_len -= print_len;
1143678453a8Sspeer }
1144678453a8Sspeer print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1145678453a8Sspeer buf_len, "\n");
114644961713Sgirish ((mblk_t *)np)->b_wptr += print_len;
114744961713Sgirish buf_len -= print_len;
114844961713Sgirish
1149678453a8Sspeer for (offset = 0; offset < 16; offset++) {
1150678453a8Sspeer print_len = snprintf(
11514045d941Ssowmini (char *)((mblk_t *)np)->b_wptr,
11524045d941Ssowmini buf_len, " %c",
11534045d941Ssowmini rdc_grp_p->map & (1 << offset) ?
11544045d941Ssowmini '1' : '0');
1155678453a8Sspeer ((mblk_t *)np)->b_wptr += print_len;
1156678453a8Sspeer buf_len -= print_len;
1157678453a8Sspeer }
115844961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1159678453a8Sspeer buf_len, "\n");
116044961713Sgirish ((mblk_t *)np)->b_wptr += print_len;
116144961713Sgirish buf_len -= print_len;
116244961713Sgirish }
116344961713Sgirish }
116444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL,
11654045d941Ssowmini "<== nxge_param_get_rxdma_rdcgrp_info"));
116644961713Sgirish return (0);
116744961713Sgirish }
116844961713Sgirish
116944961713Sgirish int
nxge_mk_mblk_tail_space(p_mblk_t mp,p_mblk_t * nmp,size_t size)117044961713Sgirish nxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size)
117144961713Sgirish {
117244961713Sgirish p_mblk_t tmp;
117344961713Sgirish
117444961713Sgirish tmp = mp;
117544961713Sgirish while (tmp->b_cont)
117644961713Sgirish tmp = tmp->b_cont;
117744961713Sgirish if ((tmp->b_wptr + size) >= tmp->b_datap->db_lim) {
117844961713Sgirish tmp->b_cont = allocb(1024, BPRI_HI);
117944961713Sgirish tmp = tmp->b_cont;
118044961713Sgirish if (!tmp)
118144961713Sgirish return (ENOMEM);
118244961713Sgirish }
1183a3c5bd6dSspeer
118444961713Sgirish *nmp = tmp;
118544961713Sgirish return (0);
118644961713Sgirish }
118744961713Sgirish
1188a3c5bd6dSspeer
118944961713Sgirish /* ARGSUSED */
119044961713Sgirish int
nxge_param_set_generic(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)119144961713Sgirish nxge_param_set_generic(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1192fe054a6cSToomas Soome char *value, caddr_t cp)
119344961713Sgirish {
119444961713Sgirish char *end;
119544961713Sgirish uint32_t new_value;
119644961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp;
119744961713Sgirish
119844961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, " ==> nxge_param_set_generic"));
119944961713Sgirish new_value = (uint32_t)mi_strtol(value, &end, 10);
120044961713Sgirish if (end == value || new_value < pa->minimum ||
12014045d941Ssowmini new_value > pa->maximum) {
120244961713Sgirish return (EINVAL);
120344961713Sgirish }
120444961713Sgirish pa->value = new_value;
120544961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, " <== nxge_param_set_generic"));
120644961713Sgirish return (0);
120744961713Sgirish }
120844961713Sgirish
120944961713Sgirish
1210a3c5bd6dSspeer /* ARGSUSED */
121144961713Sgirish int
nxge_param_set_instance(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)1212a3c5bd6dSspeer nxge_param_set_instance(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1213fe054a6cSToomas Soome char *value, caddr_t cp)
121444961713Sgirish {
121544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " ==> nxge_param_set_instance"));
121644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_set_instance"));
121744961713Sgirish return (0);
121844961713Sgirish }
121944961713Sgirish
122044961713Sgirish
1221a3c5bd6dSspeer /* ARGSUSED */
122244961713Sgirish int
nxge_param_set_mac(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)1223a3c5bd6dSspeer nxge_param_set_mac(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1224fe054a6cSToomas Soome char *value, caddr_t cp)
122544961713Sgirish {
1226a3c5bd6dSspeer char *end;
1227a3c5bd6dSspeer uint32_t new_value;
1228a3c5bd6dSspeer int status = 0;
1229a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp;
123044961713Sgirish
123144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac"));
123244961713Sgirish new_value = (uint32_t)mi_strtol(value, &end, BASE_DECIMAL);
123344961713Sgirish if (PARAM_OUTOF_RANGE(value, end, new_value, pa)) {
123444961713Sgirish return (EINVAL);
123544961713Sgirish }
123644961713Sgirish
123744961713Sgirish if (pa->value != new_value) {
123844961713Sgirish pa->old_value = pa->value;
123944961713Sgirish pa->value = new_value;
124044961713Sgirish }
124144961713Sgirish
124244961713Sgirish if (!nxge_param_link_update(nxgep)) {
124344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL,
12444045d941Ssowmini " false ret from nxge_param_link_update"));
124544961713Sgirish status = EINVAL;
124644961713Sgirish }
124744961713Sgirish
124844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac"));
124944961713Sgirish return (status);
125044961713Sgirish }
125144961713Sgirish
125244961713Sgirish /* ARGSUSED */
12531bd6825cSml int
nxge_param_rx_intr_pkts(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)1254a3c5bd6dSspeer nxge_param_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1255fe054a6cSToomas Soome char *value, caddr_t cp)
125644961713Sgirish {
1257a3c5bd6dSspeer char *end;
1258a3c5bd6dSspeer uint32_t cfg_value;
1259a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp;
126014ea4bb7Ssd
126144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_pkts"));
126244961713Sgirish
126314ea4bb7Ssd cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY);
126444961713Sgirish
126514ea4bb7Ssd if ((cfg_value > NXGE_RDC_RCR_THRESHOLD_MAX) ||
12664045d941Ssowmini (cfg_value < NXGE_RDC_RCR_THRESHOLD_MIN)) {
126744961713Sgirish return (EINVAL);
126844961713Sgirish }
126914ea4bb7Ssd
127014ea4bb7Ssd if ((pa->value != cfg_value)) {
127114ea4bb7Ssd pa->old_value = pa->value;
127214ea4bb7Ssd pa->value = cfg_value;
127314ea4bb7Ssd nxgep->intr_threshold = pa->value;
127444961713Sgirish }
127514ea4bb7Ssd
127644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_pkts"));
127744961713Sgirish return (0);
127844961713Sgirish }
127944961713Sgirish
128044961713Sgirish /* ARGSUSED */
12811bd6825cSml int
nxge_param_rx_intr_time(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)1282a3c5bd6dSspeer nxge_param_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1283fe054a6cSToomas Soome char *value, caddr_t cp)
128444961713Sgirish {
1285a3c5bd6dSspeer char *end;
1286a3c5bd6dSspeer uint32_t cfg_value;
1287a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp;
128844961713Sgirish
128944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_time"));
129044961713Sgirish
129114ea4bb7Ssd cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY);
129244961713Sgirish
129314ea4bb7Ssd if ((cfg_value > NXGE_RDC_RCR_TIMEOUT_MAX) ||
12944045d941Ssowmini (cfg_value < NXGE_RDC_RCR_TIMEOUT_MIN)) {
129544961713Sgirish return (EINVAL);
129644961713Sgirish }
129744961713Sgirish
129814ea4bb7Ssd if ((pa->value != cfg_value)) {
129914ea4bb7Ssd pa->old_value = pa->value;
130014ea4bb7Ssd pa->value = cfg_value;
130114ea4bb7Ssd nxgep->intr_timeout = pa->value;
130244961713Sgirish }
130344961713Sgirish
130444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_time"));
130544961713Sgirish return (0);
130644961713Sgirish }
130744961713Sgirish
130844961713Sgirish /* ARGSUSED */
130944961713Sgirish static int
nxge_param_set_mac_rdcgrp(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)131044961713Sgirish nxge_param_set_mac_rdcgrp(p_nxge_t nxgep, queue_t *q,
1311fe054a6cSToomas Soome mblk_t *mp, char *value, caddr_t cp)
131244961713Sgirish {
1313a3c5bd6dSspeer char *end;
1314a3c5bd6dSspeer uint32_t status = 0, cfg_value;
1315a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp;
1316a3c5bd6dSspeer uint32_t cfg_it = B_FALSE;
131744961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp;
131844961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp;
1319a3c5bd6dSspeer uint32_t *val_ptr, *old_val_ptr;
1320a3c5bd6dSspeer nxge_param_map_t *mac_map;
1321a3c5bd6dSspeer p_nxge_class_pt_cfg_t p_class_cfgp;
1322a3c5bd6dSspeer nxge_mv_cfg_t *mac_host_info;
132344961713Sgirish
132444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac_rdcgrp "));
132544961713Sgirish
132644961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
132744961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
132844961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
132944961713Sgirish mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0];
133044961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX);
1331a3c5bd6dSspeer
1332a3c5bd6dSspeer /*
1333a3c5bd6dSspeer * now do decoding
1334a3c5bd6dSspeer */
133544961713Sgirish mac_map = (nxge_param_map_t *)&cfg_value;
1336a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, " cfg_value %x id %x map_to %x",
13374045d941Ssowmini cfg_value, mac_map->param_id, mac_map->map_to));
133844961713Sgirish
133944961713Sgirish if ((mac_map->param_id < p_cfgp->max_macs) &&
1340678453a8Sspeer p_cfgp->grpids[mac_map->map_to]) {
134144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1342678453a8Sspeer " nxge_param_set_mac_rdcgrp mapping"
1343678453a8Sspeer " id %d grp %d", mac_map->param_id, mac_map->map_to));
134444961713Sgirish val_ptr = (uint32_t *)pa->value;
134544961713Sgirish old_val_ptr = (uint32_t *)pa->old_value;
134644961713Sgirish if (val_ptr[mac_map->param_id] != cfg_value) {
134744961713Sgirish old_val_ptr[mac_map->param_id] =
1348678453a8Sspeer val_ptr[mac_map->param_id];
134944961713Sgirish val_ptr[mac_map->param_id] = cfg_value;
135044961713Sgirish mac_host_info[mac_map->param_id].mpr_npr =
1351678453a8Sspeer mac_map->pref;
135244961713Sgirish mac_host_info[mac_map->param_id].flag = 1;
135344961713Sgirish mac_host_info[mac_map->param_id].rdctbl =
1354678453a8Sspeer mac_map->map_to;
135544961713Sgirish cfg_it = B_TRUE;
135644961713Sgirish }
135744961713Sgirish } else {
135844961713Sgirish return (EINVAL);
135944961713Sgirish }
136044961713Sgirish
136144961713Sgirish if (cfg_it == B_TRUE) {
136244961713Sgirish status = nxge_logical_mac_assign_rdc_table(nxgep,
1363678453a8Sspeer (uint8_t)mac_map->param_id);
136444961713Sgirish if (status != NXGE_OK)
136544961713Sgirish return (EINVAL);
136644961713Sgirish }
136744961713Sgirish
136844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac_rdcgrp"));
136944961713Sgirish return (0);
137044961713Sgirish }
137144961713Sgirish
137244961713Sgirish /* ARGSUSED */
137344961713Sgirish static int
nxge_param_set_vlan_rdcgrp(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)137444961713Sgirish nxge_param_set_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q,
1375fe054a6cSToomas Soome mblk_t *mp, char *value, caddr_t cp)
137644961713Sgirish {
1377a3c5bd6dSspeer char *end;
1378a3c5bd6dSspeer uint32_t status = 0, cfg_value;
1379a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp;
1380a3c5bd6dSspeer uint32_t cfg_it = B_FALSE;
138144961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp;
138244961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp;
1383a3c5bd6dSspeer uint32_t *val_ptr, *old_val_ptr;
1384a3c5bd6dSspeer nxge_param_map_t *vmap, *old_map;
1385a3c5bd6dSspeer p_nxge_class_pt_cfg_t p_class_cfgp;
1386a3c5bd6dSspeer uint64_t cfgd_vlans;
1387a3c5bd6dSspeer int i, inc = 0, cfg_position;
1388a3c5bd6dSspeer nxge_mv_cfg_t *vlan_tbl;
138944961713Sgirish
139044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp "));
139144961713Sgirish
139244961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
139344961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
139444961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
139544961713Sgirish vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0];
139644961713Sgirish
139744961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX);
1398a3c5bd6dSspeer
1399a3c5bd6dSspeer /* now do decoding */
140044961713Sgirish cfgd_vlans = ((pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >>
14014045d941Ssowmini NXGE_PARAM_ARRAY_CNT_SHIFT);
140244961713Sgirish
140344961713Sgirish if (cfgd_vlans == NXGE_PARAM_ARRAY_INIT_SIZE) {
140444961713Sgirish /*
140544961713Sgirish * for now, we process only upto max
140644961713Sgirish * NXGE_PARAM_ARRAY_INIT_SIZE parameters
140744961713Sgirish * In the future, we may want to expand
140844961713Sgirish * the storage array and continue
140944961713Sgirish */
141044961713Sgirish return (EINVAL);
141144961713Sgirish }
1412a3c5bd6dSspeer
141344961713Sgirish vmap = (nxge_param_map_t *)&cfg_value;
141444961713Sgirish if ((vmap->param_id) &&
14154045d941Ssowmini (vmap->param_id < NXGE_MAX_VLANS) &&
14164045d941Ssowmini (vmap->map_to < p_cfgp->max_rdc_grpids)) {
141744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL,
14184045d941Ssowmini "nxge_param_set_vlan_rdcgrp mapping"
14194045d941Ssowmini " id %d grp %d",
14204045d941Ssowmini vmap->param_id, vmap->map_to));
142144961713Sgirish val_ptr = (uint32_t *)pa->value;
142244961713Sgirish old_val_ptr = (uint32_t *)pa->old_value;
142344961713Sgirish
142444961713Sgirish /* search to see if this vlan id is already configured */
142544961713Sgirish for (i = 0; i < cfgd_vlans; i++) {
142644961713Sgirish old_map = (nxge_param_map_t *)&val_ptr[i];
142744961713Sgirish if ((old_map->param_id == 0) ||
14284045d941Ssowmini (vmap->param_id == old_map->param_id) ||
14294045d941Ssowmini (vlan_tbl[vmap->param_id].flag)) {
143044961713Sgirish cfg_position = i;
143144961713Sgirish break;
143244961713Sgirish }
143344961713Sgirish }
143444961713Sgirish
143544961713Sgirish if (cfgd_vlans == 0) {
143644961713Sgirish cfg_position = 0;
143744961713Sgirish inc++;
143844961713Sgirish }
143944961713Sgirish
144044961713Sgirish if (i == cfgd_vlans) {
144144961713Sgirish cfg_position = i;
144244961713Sgirish inc++;
144344961713Sgirish }
144444961713Sgirish
144544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL,
14464045d941Ssowmini "set_vlan_rdcgrp mapping"
14474045d941Ssowmini " i %d cfgd_vlans %llx position %d ",
14484045d941Ssowmini i, cfgd_vlans, cfg_position));
144944961713Sgirish if (val_ptr[cfg_position] != cfg_value) {
145044961713Sgirish old_val_ptr[cfg_position] = val_ptr[cfg_position];
145144961713Sgirish val_ptr[cfg_position] = cfg_value;
145244961713Sgirish vlan_tbl[vmap->param_id].mpr_npr = vmap->pref;
145344961713Sgirish vlan_tbl[vmap->param_id].flag = 1;
145444961713Sgirish vlan_tbl[vmap->param_id].rdctbl =
1455678453a8Sspeer vmap->map_to + p_cfgp->def_mac_rxdma_grpid;
145644961713Sgirish cfg_it = B_TRUE;
145744961713Sgirish if (inc) {
145844961713Sgirish cfgd_vlans++;
145944961713Sgirish pa->type &= ~NXGE_PARAM_ARRAY_CNT_MASK;
146044961713Sgirish pa->type |= (cfgd_vlans <<
14614045d941Ssowmini NXGE_PARAM_ARRAY_CNT_SHIFT);
146244961713Sgirish
146344961713Sgirish }
146444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL,
14654045d941Ssowmini "after: param_set_vlan_rdcgrp "
14664045d941Ssowmini " cfg_vlans %llx position %d \n",
14674045d941Ssowmini cfgd_vlans, cfg_position));
146844961713Sgirish }
146944961713Sgirish } else {
147044961713Sgirish return (EINVAL);
147144961713Sgirish }
147244961713Sgirish
147344961713Sgirish if (cfg_it == B_TRUE) {
147444961713Sgirish status = nxge_fflp_config_vlan_table(nxgep,
14754045d941Ssowmini (uint16_t)vmap->param_id);
147644961713Sgirish if (status != NXGE_OK)
147744961713Sgirish return (EINVAL);
147844961713Sgirish }
147944961713Sgirish
148044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_vlan_rdcgrp"));
148144961713Sgirish return (0);
148244961713Sgirish }
148344961713Sgirish
148444961713Sgirish /* ARGSUSED */
148544961713Sgirish static int
nxge_param_get_vlan_rdcgrp(p_nxge_t nxgep,queue_t * q,mblk_t * mp,caddr_t cp)148644961713Sgirish nxge_param_get_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q,
1487fe054a6cSToomas Soome mblk_t *mp, caddr_t cp)
148844961713Sgirish {
148944961713Sgirish
1490*86ef0a63SRichard Lowe uint_t print_len, buf_len;
1491a3c5bd6dSspeer p_mblk_t np;
1492a3c5bd6dSspeer int i;
1493a3c5bd6dSspeer uint32_t *val_ptr;
1494a3c5bd6dSspeer nxge_param_map_t *vmap;
1495a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp;
1496*86ef0a63SRichard Lowe p_nxge_class_pt_cfg_t p_class_cfgp;
149744961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp;
149844961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp;
1499a3c5bd6dSspeer uint64_t cfgd_vlans = 0;
1500a3c5bd6dSspeer nxge_mv_cfg_t *vlan_tbl;
1501a3c5bd6dSspeer int buff_alloc_size =
15024045d941Ssowmini NXGE_NDD_INFODUMP_BUFF_SIZE * 32;
150344961713Sgirish
150444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp "));
1505a3c5bd6dSspeer (void) mi_mpprintf(mp, "VLAN RDC Mapping Information for Port\t %d \n",
15064045d941Ssowmini nxgep->function_num);
150744961713Sgirish
150844961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
150944961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer");
151044961713Sgirish return (0);
151144961713Sgirish }
1512a3c5bd6dSspeer
151344961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
151444961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
151544961713Sgirish
151644961713Sgirish buf_len = buff_alloc_size;
151744961713Sgirish mp->b_cont = np;
151844961713Sgirish cfgd_vlans = (pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >>
15194045d941Ssowmini NXGE_PARAM_ARRAY_CNT_SHIFT;
152044961713Sgirish
152144961713Sgirish i = (int)cfgd_vlans;
152244961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
152344961713Sgirish vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0];
152444961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
15254045d941Ssowmini "Configured VLANs %d\n"
15264045d941Ssowmini "VLAN ID\t RDC GRP (Actual/Port)\t"
15274045d941Ssowmini " Prefernce\n", i);
152844961713Sgirish ((mblk_t *)np)->b_wptr += print_len;
152944961713Sgirish buf_len -= print_len;
153044961713Sgirish val_ptr = (uint32_t *)pa->value;
153144961713Sgirish
153244961713Sgirish for (i = 0; i < cfgd_vlans; i++) {
153344961713Sgirish vmap = (nxge_param_map_t *)&val_ptr[i];
153444961713Sgirish if (p_class_cfgp->vlan_tbl[vmap->param_id].flag) {
153544961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
15364045d941Ssowmini buf_len,
15374045d941Ssowmini " %d\t\t %d/%d\t\t %d\n",
15384045d941Ssowmini vmap->param_id,
15394045d941Ssowmini vlan_tbl[vmap->param_id].rdctbl,
15404045d941Ssowmini vlan_tbl[vmap->param_id].rdctbl -
15414045d941Ssowmini p_cfgp->def_mac_rxdma_grpid,
15424045d941Ssowmini vlan_tbl[vmap->param_id].mpr_npr);
154344961713Sgirish ((mblk_t *)np)->b_wptr += print_len;
154444961713Sgirish buf_len -= print_len;
154544961713Sgirish }
154644961713Sgirish }
154744961713Sgirish
154844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_vlan_rdcgrp"));
154944961713Sgirish return (0);
155044961713Sgirish }
155144961713Sgirish
155244961713Sgirish /* ARGSUSED */
155344961713Sgirish static int
nxge_param_get_mac_rdcgrp(p_nxge_t nxgep,queue_t * q,mblk_t * mp,caddr_t cp)155444961713Sgirish nxge_param_get_mac_rdcgrp(p_nxge_t nxgep, queue_t *q,
1555fe054a6cSToomas Soome mblk_t *mp, caddr_t cp)
155644961713Sgirish {
1557a3c5bd6dSspeer uint_t print_len, buf_len;
1558a3c5bd6dSspeer p_mblk_t np;
1559a3c5bd6dSspeer int i;
1560*86ef0a63SRichard Lowe p_nxge_class_pt_cfg_t p_class_cfgp;
156144961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp;
156244961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp;
1563a3c5bd6dSspeer nxge_mv_cfg_t *mac_host_info;
156444961713Sgirish
156544961713Sgirish int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE * 32;
156644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac_rdcgrp "));
156744961713Sgirish (void) mi_mpprintf(mp,
15684045d941Ssowmini "MAC ADDR RDC Mapping Information for Port\t %d\n",
15694045d941Ssowmini nxgep->function_num);
157044961713Sgirish
157144961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
157244961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer");
157344961713Sgirish return (0);
157444961713Sgirish }
157544961713Sgirish
157644961713Sgirish buf_len = buff_alloc_size;
157744961713Sgirish mp->b_cont = np;
157844961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
157944961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
158044961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
158144961713Sgirish mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0];
158244961713Sgirish print_len = snprintf((char *)np->b_wptr, buf_len,
15834045d941Ssowmini "MAC ID\t RDC GRP (Actual/Port)\t"
15844045d941Ssowmini " Prefernce\n");
158544961713Sgirish ((mblk_t *)np)->b_wptr += print_len;
158644961713Sgirish buf_len -= print_len;
158744961713Sgirish for (i = 0; i < p_cfgp->max_macs; i++) {
158844961713Sgirish if (mac_host_info[i].flag) {
158944961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
15904045d941Ssowmini buf_len,
15914045d941Ssowmini " %d\t %d/%d\t\t %d\n",
15924045d941Ssowmini i, mac_host_info[i].rdctbl,
15934045d941Ssowmini mac_host_info[i].rdctbl -
15944045d941Ssowmini p_cfgp->def_mac_rxdma_grpid,
15954045d941Ssowmini mac_host_info[i].mpr_npr);
159644961713Sgirish ((mblk_t *)np)->b_wptr += print_len;
159744961713Sgirish buf_len -= print_len;
159844961713Sgirish }
159944961713Sgirish }
160044961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
16014045d941Ssowmini "Done Info Dumping \n");
160244961713Sgirish ((mblk_t *)np)->b_wptr += print_len;
160344961713Sgirish buf_len -= print_len;
160444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_macrdcgrp"));
160544961713Sgirish return (0);
160644961713Sgirish }
160744961713Sgirish
160844961713Sgirish /* ARGSUSED */
160944961713Sgirish static int
nxge_param_tcam_enable(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)161044961713Sgirish nxge_param_tcam_enable(p_nxge_t nxgep, queue_t *q,
1611fe054a6cSToomas Soome mblk_t *mp, char *value, caddr_t cp)
161244961713Sgirish {
1613a3c5bd6dSspeer uint32_t status = 0, cfg_value;
1614a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp;
1615a3c5bd6dSspeer uint32_t cfg_it = B_FALSE;
1616a3c5bd6dSspeer char *end;
161744961713Sgirish
161844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_tcam_enable"));
161944961713Sgirish
162044961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY);
162144961713Sgirish if (pa->value != cfg_value) {
162244961713Sgirish pa->old_value = pa->value;
162344961713Sgirish pa->value = cfg_value;
162444961713Sgirish cfg_it = B_TRUE;
162544961713Sgirish }
162644961713Sgirish
162744961713Sgirish if (cfg_it == B_TRUE) {
162844961713Sgirish if (pa->value)
162944961713Sgirish status = nxge_fflp_config_tcam_enable(nxgep);
163044961713Sgirish else
163144961713Sgirish status = nxge_fflp_config_tcam_disable(nxgep);
163244961713Sgirish if (status != NXGE_OK)
163344961713Sgirish return (EINVAL);
163444961713Sgirish }
163544961713Sgirish
163644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_tcam_enable"));
163744961713Sgirish return (0);
163844961713Sgirish }
163944961713Sgirish
164044961713Sgirish /* ARGSUSED */
164144961713Sgirish static int
nxge_param_hash_lookup_enable(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)164244961713Sgirish nxge_param_hash_lookup_enable(p_nxge_t nxgep, queue_t *q,
1643fe054a6cSToomas Soome mblk_t *mp, char *value, caddr_t cp)
164444961713Sgirish {
1645a3c5bd6dSspeer uint32_t status = 0, cfg_value;
1646a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp;
1647a3c5bd6dSspeer uint32_t cfg_it = B_FALSE;
1648a3c5bd6dSspeer char *end;
164944961713Sgirish
165044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_hash_lookup_enable"));
165144961713Sgirish
165244961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY);
165344961713Sgirish if (pa->value != cfg_value) {
165444961713Sgirish pa->old_value = pa->value;
165544961713Sgirish pa->value = cfg_value;
165644961713Sgirish cfg_it = B_TRUE;
165744961713Sgirish }
165844961713Sgirish
165944961713Sgirish if (cfg_it == B_TRUE) {
166044961713Sgirish if (pa->value)
166144961713Sgirish status = nxge_fflp_config_hash_lookup_enable(nxgep);
166244961713Sgirish else
166344961713Sgirish status = nxge_fflp_config_hash_lookup_disable(nxgep);
166444961713Sgirish if (status != NXGE_OK)
166544961713Sgirish return (EINVAL);
166644961713Sgirish }
166744961713Sgirish
166844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_hash_lookup_enable"));
166944961713Sgirish return (0);
167044961713Sgirish }
167144961713Sgirish
167244961713Sgirish /* ARGSUSED */
167344961713Sgirish static int
nxge_param_llc_snap_enable(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)167444961713Sgirish nxge_param_llc_snap_enable(p_nxge_t nxgep, queue_t *q,
1675fe054a6cSToomas Soome mblk_t *mp, char *value, caddr_t cp)
167644961713Sgirish {
1677a3c5bd6dSspeer char *end;
1678a3c5bd6dSspeer uint32_t status = 0, cfg_value;
1679a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp;
1680a3c5bd6dSspeer uint32_t cfg_it = B_FALSE;
168144961713Sgirish
168244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_llc_snap_enable"));
168344961713Sgirish
168444961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY);
168544961713Sgirish if (pa->value != cfg_value) {
168644961713Sgirish pa->old_value = pa->value;
168744961713Sgirish pa->value = cfg_value;
168844961713Sgirish cfg_it = B_TRUE;
168944961713Sgirish }
169044961713Sgirish
169144961713Sgirish if (cfg_it == B_TRUE) {
169244961713Sgirish if (pa->value)
169344961713Sgirish status = nxge_fflp_config_tcam_enable(nxgep);
169444961713Sgirish else
169544961713Sgirish status = nxge_fflp_config_tcam_disable(nxgep);
169644961713Sgirish if (status != NXGE_OK)
169744961713Sgirish return (EINVAL);
169844961713Sgirish }
169944961713Sgirish
170044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_llc_snap_enable"));
170144961713Sgirish return (0);
170244961713Sgirish }
170344961713Sgirish
170444961713Sgirish /* ARGSUSED */
170544961713Sgirish static int
nxge_param_set_ether_usr(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)170644961713Sgirish nxge_param_set_ether_usr(p_nxge_t nxgep, queue_t *q,
1707fe054a6cSToomas Soome mblk_t *mp, char *value, caddr_t cp)
170844961713Sgirish {
1709a3c5bd6dSspeer char *end;
1710a3c5bd6dSspeer uint32_t status = 0, cfg_value;
1711a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp;
1712a3c5bd6dSspeer uint8_t cfg_it = B_FALSE;
171344961713Sgirish
171444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ether_usr"));
171544961713Sgirish
171644961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX);
171744961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
171844961713Sgirish return (EINVAL);
171944961713Sgirish }
1720a3c5bd6dSspeer
172144961713Sgirish if (pa->value != cfg_value) {
172244961713Sgirish pa->old_value = pa->value;
172344961713Sgirish pa->value = cfg_value;
172444961713Sgirish cfg_it = B_TRUE;
172544961713Sgirish }
172644961713Sgirish
172744961713Sgirish /* do the actual hw setup */
172844961713Sgirish if (cfg_it == B_TRUE) {
1729fe054a6cSToomas Soome (void) mi_strtol(pa->name, &end, BASE_DECIMAL);
173044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_ether_usr"));
173144961713Sgirish }
1732a3c5bd6dSspeer
173344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ether_usr"));
173444961713Sgirish return (status);
173544961713Sgirish }
173644961713Sgirish
173744961713Sgirish /* ARGSUSED */
173844961713Sgirish static int
nxge_param_set_ip_usr(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)173944961713Sgirish nxge_param_set_ip_usr(p_nxge_t nxgep, queue_t *q,
1740fe054a6cSToomas Soome mblk_t *mp, char *value, caddr_t cp)
174144961713Sgirish {
1742a3c5bd6dSspeer char *end;
1743a3c5bd6dSspeer tcam_class_t class;
1744a3c5bd6dSspeer uint32_t status, cfg_value;
1745a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp;
1746a3c5bd6dSspeer uint32_t cfg_it = B_FALSE;
174744961713Sgirish
174844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_usr"));
174944961713Sgirish
175044961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX);
175144961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
175244961713Sgirish return (EINVAL);
175344961713Sgirish }
175444961713Sgirish
175544961713Sgirish if (pa->value != cfg_value) {
175644961713Sgirish pa->old_value = pa->value;
175744961713Sgirish pa->value = cfg_value;
175844961713Sgirish cfg_it = B_TRUE;
175944961713Sgirish }
176044961713Sgirish
176144961713Sgirish /* do the actual hw setup with cfg_value. */
1762e3d11eeeSToomas Soome status = 0;
176344961713Sgirish if (cfg_it == B_TRUE) {
176444961713Sgirish class = mi_strtol(pa->name, &end, 10);
176544961713Sgirish status = nxge_fflp_ip_usr_class_config(nxgep, class, pa->value);
176644961713Sgirish }
176744961713Sgirish
176844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_usr"));
176944961713Sgirish return (status);
177044961713Sgirish }
177144961713Sgirish
177244961713Sgirish static int
nxge_class_name_2value(p_nxge_t nxgep,char * name)177344961713Sgirish nxge_class_name_2value(p_nxge_t nxgep, char *name)
177444961713Sgirish {
1775a3c5bd6dSspeer int i;
1776a3c5bd6dSspeer int class_instance = param_class_opt_ip_usr4;
1777a3c5bd6dSspeer p_nxge_param_t param_arr;
1778a3c5bd6dSspeer
177944961713Sgirish param_arr = nxgep->param_arr;
178044961713Sgirish for (i = TCAM_CLASS_IP_USER_4; i <= TCAM_CLASS_SCTP_IPV6; i++) {
178144961713Sgirish if (strcmp(param_arr[class_instance].name, name) == 0)
178244961713Sgirish return (i);
178344961713Sgirish class_instance++;
178444961713Sgirish }
178544961713Sgirish return (-1);
178644961713Sgirish }
178744961713Sgirish
17881bd6825cSml int
nxge_param_set_ip_opt(p_nxge_t nxgep,queue_t * q __unused,mblk_t * mp __unused,char * value,caddr_t cp)1789e3d11eeeSToomas Soome nxge_param_set_ip_opt(p_nxge_t nxgep, queue_t *q __unused,
1790e3d11eeeSToomas Soome mblk_t *mp __unused, char *value, caddr_t cp)
179144961713Sgirish {
1792a3c5bd6dSspeer char *end;
1793a3c5bd6dSspeer uint32_t status, cfg_value;
1794a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp;
1795a3c5bd6dSspeer tcam_class_t class;
1796a3c5bd6dSspeer uint32_t cfg_it = B_FALSE;
179744961713Sgirish
179844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_opt"));
179944961713Sgirish
180044961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX);
180144961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
180244961713Sgirish return (EINVAL);
180344961713Sgirish }
180444961713Sgirish
180544961713Sgirish if (pa->value != cfg_value) {
180644961713Sgirish pa->old_value = pa->value;
180744961713Sgirish pa->value = cfg_value;
180844961713Sgirish cfg_it = B_TRUE;
180944961713Sgirish }
181044961713Sgirish
181144961713Sgirish if (cfg_it == B_TRUE) {
1812a3c5bd6dSspeer /* do the actual hw setup */
181344961713Sgirish class = nxge_class_name_2value(nxgep, pa->name);
181444961713Sgirish if (class == -1)
181544961713Sgirish return (EINVAL);
181644961713Sgirish
1817c1f9c6e5SSantwona Behera /* Filter out the allowed bits */
1818c1f9c6e5SSantwona Behera pa->value &= (NXGE_CLASS_FLOW_USE_PORTNUM |
1819c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_L2DA | NXGE_CLASS_FLOW_USE_VLAN |
1820c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_PROTO | NXGE_CLASS_FLOW_USE_IPSRC |
1821c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_IPDST | NXGE_CLASS_FLOW_USE_SRC_PORT |
1822c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_DST_PORT);
1823c1f9c6e5SSantwona Behera
182444961713Sgirish status = nxge_fflp_ip_class_config(nxgep, class, pa->value);
182544961713Sgirish if (status != NXGE_OK)
182644961713Sgirish return (EINVAL);
182744961713Sgirish }
182844961713Sgirish
182944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_opt"));
183044961713Sgirish return (0);
183144961713Sgirish }
183244961713Sgirish
183344961713Sgirish /* ARGSUSED */
183444961713Sgirish static int
nxge_param_get_ip_opt(p_nxge_t nxgep,queue_t * q,mblk_t * mp,caddr_t cp)183544961713Sgirish nxge_param_get_ip_opt(p_nxge_t nxgep, queue_t *q,
1836fe054a6cSToomas Soome mblk_t *mp, caddr_t cp)
183744961713Sgirish {
183844961713Sgirish uint32_t status, cfg_value;
183944961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp;
184044961713Sgirish tcam_class_t class;
184144961713Sgirish
184244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_ip_opt"));
184344961713Sgirish
1844a3c5bd6dSspeer /* do the actual hw setup */
184544961713Sgirish class = nxge_class_name_2value(nxgep, pa->name);
184644961713Sgirish if (class == -1)
184744961713Sgirish return (EINVAL);
1848a3c5bd6dSspeer
184944961713Sgirish cfg_value = 0;
185044961713Sgirish status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value);
185144961713Sgirish if (status != NXGE_OK)
185244961713Sgirish return (EINVAL);
1853a3c5bd6dSspeer
1854c1f9c6e5SSantwona Behera /* Filter out the allowed bits */
1855c1f9c6e5SSantwona Behera cfg_value &= (NXGE_CLASS_FLOW_USE_PORTNUM | NXGE_CLASS_FLOW_USE_L2DA |
1856c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_VLAN | NXGE_CLASS_FLOW_USE_PROTO |
1857c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_IPDST |
1858c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_DST_PORT);
1859c1f9c6e5SSantwona Behera
186044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL,
18614045d941Ssowmini "nxge_param_get_ip_opt_get %x ", cfg_value));
186244961713Sgirish
1863a3c5bd6dSspeer pa->value = cfg_value;
186444961713Sgirish (void) mi_mpprintf(mp, "%x", cfg_value);
1865a3c5bd6dSspeer
186644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status "));
186744961713Sgirish return (0);
186844961713Sgirish }
186944961713Sgirish
187044961713Sgirish /* ARGSUSED */
187144961713Sgirish static int
nxge_param_fflp_hash_init(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)187244961713Sgirish nxge_param_fflp_hash_init(p_nxge_t nxgep, queue_t *q,
1873fe054a6cSToomas Soome mblk_t *mp, char *value, caddr_t cp)
187444961713Sgirish {
1875a3c5bd6dSspeer char *end;
1876a3c5bd6dSspeer uint32_t status, cfg_value;
1877a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp;
1878a3c5bd6dSspeer tcam_class_t class;
1879a3c5bd6dSspeer uint32_t cfg_it = B_FALSE;
188044961713Sgirish
188144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_fflp_hash_init"));
188244961713Sgirish
188344961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX);
188444961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
188544961713Sgirish return (EINVAL);
188644961713Sgirish }
188744961713Sgirish
188844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL,
18894045d941Ssowmini "nxge_param_fflp_hash_init value %x", cfg_value));
1890a3c5bd6dSspeer
189144961713Sgirish if (pa->value != cfg_value) {
189244961713Sgirish pa->old_value = pa->value;
189344961713Sgirish pa->value = cfg_value;
189444961713Sgirish cfg_it = B_TRUE;
189544961713Sgirish }
189644961713Sgirish
189744961713Sgirish if (cfg_it == B_TRUE) {
189844961713Sgirish char *h_name;
1899a3c5bd6dSspeer
190044961713Sgirish /* do the actual hw setup */
190144961713Sgirish h_name = pa->name;
190244961713Sgirish h_name++;
190344961713Sgirish class = mi_strtol(h_name, &end, 10);
190444961713Sgirish switch (class) {
190544961713Sgirish case 1:
190644961713Sgirish status = nxge_fflp_set_hash1(nxgep,
19074045d941Ssowmini (uint32_t)pa->value);
190844961713Sgirish break;
190944961713Sgirish case 2:
191044961713Sgirish status = nxge_fflp_set_hash2(nxgep,
19114045d941Ssowmini (uint16_t)pa->value);
191244961713Sgirish break;
191344961713Sgirish
191444961713Sgirish default:
191544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL,
19164045d941Ssowmini " nxge_param_fflp_hash_init"
19174045d941Ssowmini " %s Wrong hash var %d",
19184045d941Ssowmini pa->name, class));
191944961713Sgirish return (EINVAL);
192044961713Sgirish }
192144961713Sgirish if (status != NXGE_OK)
192244961713Sgirish return (EINVAL);
192344961713Sgirish }
192444961713Sgirish
192544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_fflp_hash_init"));
192644961713Sgirish return (0);
192744961713Sgirish }
192844961713Sgirish
192944961713Sgirish /* ARGSUSED */
193044961713Sgirish static int
nxge_param_set_grp_rdc(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)193144961713Sgirish nxge_param_set_grp_rdc(p_nxge_t nxgep, queue_t *q,
1932fe054a6cSToomas Soome mblk_t *mp, char *value, caddr_t cp)
193344961713Sgirish {
1934a3c5bd6dSspeer char *end;
1935a3c5bd6dSspeer uint32_t status = 0, cfg_value;
1936a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp;
1937a3c5bd6dSspeer uint32_t cfg_it = B_FALSE;
1938a3c5bd6dSspeer int rdc_grp;
1939a3c5bd6dSspeer uint8_t real_rdc;
194044961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp;
194144961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp;
194244961713Sgirish p_nxge_rdc_grp_t rdc_grp_p;
194344961713Sgirish
194444961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
194544961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
194644961713Sgirish
194744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_grp_rdc"));
194844961713Sgirish
194944961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY);
195044961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
195144961713Sgirish return (EINVAL);
195244961713Sgirish }
1953a3c5bd6dSspeer
195444961713Sgirish if (cfg_value >= p_cfgp->max_rdcs) {
195544961713Sgirish return (EINVAL);
195644961713Sgirish }
1957a3c5bd6dSspeer
195844961713Sgirish if (pa->value != cfg_value) {
195944961713Sgirish pa->old_value = pa->value;
196044961713Sgirish pa->value = cfg_value;
196144961713Sgirish cfg_it = B_TRUE;
196244961713Sgirish }
196344961713Sgirish
196444961713Sgirish if (cfg_it == B_TRUE) {
196544961713Sgirish char *grp_name;
196644961713Sgirish grp_name = pa->name;
196744961713Sgirish grp_name += strlen("default-grp");
196844961713Sgirish rdc_grp = mi_strtol(grp_name, &end, 10);
196944961713Sgirish rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp];
197044961713Sgirish real_rdc = rdc_grp_p->start_rdc + cfg_value;
197144961713Sgirish if (nxge_check_rxdma_rdcgrp_member(nxgep, rdc_grp,
19724045d941Ssowmini cfg_value) == B_FALSE) {
197344961713Sgirish pa->value = pa->old_value;
197444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL,
19754045d941Ssowmini " nxge_param_set_grp_rdc"
19764045d941Ssowmini " %d read %d actual %d outof range",
19774045d941Ssowmini rdc_grp, cfg_value, real_rdc));
197844961713Sgirish return (EINVAL);
197944961713Sgirish }
198044961713Sgirish status = nxge_rxdma_cfg_rdcgrp_default_rdc(nxgep, rdc_grp,
19814045d941Ssowmini real_rdc);
198244961713Sgirish if (status != NXGE_OK)
198344961713Sgirish return (EINVAL);
198444961713Sgirish }
198544961713Sgirish
198644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_grp_rdc"));
198744961713Sgirish return (0);
198844961713Sgirish }
198944961713Sgirish
199044961713Sgirish /* ARGSUSED */
199144961713Sgirish static int
nxge_param_set_port_rdc(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)199244961713Sgirish nxge_param_set_port_rdc(p_nxge_t nxgep, queue_t *q,
1993fe054a6cSToomas Soome mblk_t *mp, char *value, caddr_t cp)
199444961713Sgirish {
1995a3c5bd6dSspeer char *end;
1996a3c5bd6dSspeer uint32_t status = B_TRUE, cfg_value;
1997a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp;
1998a3c5bd6dSspeer uint32_t cfg_it = B_FALSE;
199944961713Sgirish
200044961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp;
200144961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp;
200244961713Sgirish
200344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_port_rdc"));
200444961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
200544961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
200644961713Sgirish
200744961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY);
200844961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
200944961713Sgirish return (EINVAL);
201044961713Sgirish }
2011a3c5bd6dSspeer
201244961713Sgirish if (pa->value != cfg_value) {
201344961713Sgirish if (cfg_value >= p_cfgp->max_rdcs)
201444961713Sgirish return (EINVAL);
201544961713Sgirish pa->old_value = pa->value;
201644961713Sgirish pa->value = cfg_value;
201744961713Sgirish cfg_it = B_TRUE;
201844961713Sgirish }
201944961713Sgirish
202044961713Sgirish if (cfg_it == B_TRUE) {
2021678453a8Sspeer int rdc;
2022678453a8Sspeer if ((rdc = nxge_dci_map(nxgep, VP_BOUND_RX, cfg_value)) < 0)
2023678453a8Sspeer return (EINVAL);
202444961713Sgirish status = nxge_rxdma_cfg_port_default_rdc(nxgep,
2025678453a8Sspeer nxgep->function_num, rdc);
202644961713Sgirish if (status != NXGE_OK)
202744961713Sgirish return (EINVAL);
202844961713Sgirish }
202944961713Sgirish
203044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_port_rdc"));
203144961713Sgirish return (0);
203244961713Sgirish }
203344961713Sgirish
203444961713Sgirish /* ARGSUSED */
203544961713Sgirish static int
nxge_param_set_nxge_debug_flag(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)203644961713Sgirish nxge_param_set_nxge_debug_flag(p_nxge_t nxgep, queue_t *q,
2037fe054a6cSToomas Soome mblk_t *mp, char *value, caddr_t cp)
203844961713Sgirish {
203944961713Sgirish char *end;
204044961713Sgirish uint32_t status = 0;
204144961713Sgirish uint64_t cfg_value = 0;
204244961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp;
204344961713Sgirish uint32_t cfg_it = B_FALSE;
204444961713Sgirish
204544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_nxge_debug_flag"));
204644961713Sgirish cfg_value = mi_strtol(value, &end, BASE_HEX);
204744961713Sgirish
204844961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
204944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL,
20504045d941Ssowmini " nxge_param_set_nxge_debug_flag"
20514045d941Ssowmini " outof range %llx", cfg_value));
205244961713Sgirish return (EINVAL);
205344961713Sgirish }
205444961713Sgirish if (pa->value != cfg_value) {
205544961713Sgirish pa->old_value = pa->value;
205644961713Sgirish pa->value = cfg_value;
205744961713Sgirish cfg_it = B_TRUE;
205844961713Sgirish }
205944961713Sgirish
206044961713Sgirish if (cfg_it == B_TRUE) {
206144961713Sgirish nxgep->nxge_debug_level = pa->value;
206244961713Sgirish }
2063a3c5bd6dSspeer
206444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_nxge_debug_flag"));
206544961713Sgirish return (status);
206644961713Sgirish }
206744961713Sgirish
206844961713Sgirish /* ARGSUSED */
206944961713Sgirish static int
nxge_param_get_debug_flag(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)207044961713Sgirish nxge_param_get_debug_flag(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
207144961713Sgirish {
2072a3c5bd6dSspeer int status = 0;
2073a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp;
207444961713Sgirish
207544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_debug_flag"));
207644961713Sgirish
207744961713Sgirish if (pa->value > 0xffffffff)
2078*86ef0a63SRichard Lowe (void) mi_mpprintf(mp, "%x%x", (int)(pa->value >> 32),
20794045d941Ssowmini (int)(pa->value & 0xffffffff));
208044961713Sgirish else
208144961713Sgirish (void) mi_mpprintf(mp, "%x", (int)pa->value);
208244961713Sgirish
208344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_debug_flag"));
208444961713Sgirish return (status);
208544961713Sgirish }
208644961713Sgirish
208744961713Sgirish /* ARGSUSED */
208844961713Sgirish static int
nxge_param_set_npi_debug_flag(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)208944961713Sgirish nxge_param_set_npi_debug_flag(p_nxge_t nxgep, queue_t *q,
2090fe054a6cSToomas Soome mblk_t *mp, char *value, caddr_t cp)
209144961713Sgirish {
2092a3c5bd6dSspeer char *end;
2093a3c5bd6dSspeer uint32_t status = 0;
2094a3c5bd6dSspeer uint64_t cfg_value = 0;
2095a3c5bd6dSspeer p_nxge_param_t pa;
2096a3c5bd6dSspeer uint32_t cfg_it = B_FALSE;
209744961713Sgirish
209844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_npi_debug_flag"));
209944961713Sgirish cfg_value = mi_strtol(value, &end, BASE_HEX);
210044961713Sgirish pa = (p_nxge_param_t)cp;
210144961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
210244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_npi_debug_flag"
21034045d941Ssowmini " outof range %llx", cfg_value));
210444961713Sgirish return (EINVAL);
210544961713Sgirish }
210644961713Sgirish if (pa->value != cfg_value) {
210744961713Sgirish pa->old_value = pa->value;
210844961713Sgirish pa->value = cfg_value;
210944961713Sgirish cfg_it = B_TRUE;
211044961713Sgirish }
211144961713Sgirish
211244961713Sgirish if (cfg_it == B_TRUE) {
211344961713Sgirish npi_debug_level = pa->value;
211444961713Sgirish }
211544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_debug_flag"));
211644961713Sgirish return (status);
211744961713Sgirish }
211844961713Sgirish
211944961713Sgirish /* ARGSUSED */
212044961713Sgirish static int
nxge_param_dump_rdc(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)212144961713Sgirish nxge_param_dump_rdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
212244961713Sgirish {
2123678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set;
2124678453a8Sspeer int rdc;
212544961713Sgirish
212644961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_rdc"));
212744961713Sgirish
2128678453a8Sspeer if (!isLDOMguest(nxgep))
21294045d941Ssowmini (void) npi_rxdma_dump_fzc_regs(NXGE_DEV_NPI_HANDLE(nxgep));
2130678453a8Sspeer
2131678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_TDCS; rdc++) {
2132678453a8Sspeer if ((1 << rdc) & set->owned.map) {
2133678453a8Sspeer (void) nxge_dump_rxdma_channel(nxgep, rdc);
2134678453a8Sspeer }
2135678453a8Sspeer }
213644961713Sgirish
213744961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_rdc"));
213844961713Sgirish return (0);
213944961713Sgirish }
214044961713Sgirish
214144961713Sgirish /* ARGSUSED */
214244961713Sgirish static int
nxge_param_dump_tdc(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)214344961713Sgirish nxge_param_dump_tdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
214444961713Sgirish {
2145678453a8Sspeer nxge_grp_set_t *set = &nxgep->tx_set;
2146678453a8Sspeer int tdc;
214744961713Sgirish
214844961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_tdc"));
214944961713Sgirish
2150678453a8Sspeer for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) {
2151678453a8Sspeer if ((1 << tdc) & set->owned.map) {
2152678453a8Sspeer (void) nxge_txdma_regs_dump(nxgep, tdc);
2153678453a8Sspeer }
2154678453a8Sspeer }
215544961713Sgirish
215644961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_tdc"));
215744961713Sgirish return (0);
215844961713Sgirish }
215944961713Sgirish
216044961713Sgirish /* ARGSUSED */
216144961713Sgirish static int
nxge_param_dump_fflp_regs(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)216244961713Sgirish nxge_param_dump_fflp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
216344961713Sgirish {
216444961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_fflp_regs"));
216544961713Sgirish
216644961713Sgirish (void) npi_fflp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep));
216744961713Sgirish
216844961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_fflp_regs"));
216944961713Sgirish return (0);
217044961713Sgirish }
217144961713Sgirish
217244961713Sgirish /* ARGSUSED */
217344961713Sgirish static int
nxge_param_dump_mac_regs(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)217444961713Sgirish nxge_param_dump_mac_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
217544961713Sgirish {
217644961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_mac_regs"));
217744961713Sgirish
217844961713Sgirish (void) npi_mac_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep),
21794045d941Ssowmini nxgep->function_num);
218044961713Sgirish
218144961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_mac_regs"));
218244961713Sgirish return (0);
218344961713Sgirish }
218444961713Sgirish
218544961713Sgirish /* ARGSUSED */
218644961713Sgirish static int
nxge_param_dump_ipp_regs(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)218744961713Sgirish nxge_param_dump_ipp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
218844961713Sgirish {
218944961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_ipp_regs"));
219044961713Sgirish
2191a3c5bd6dSspeer (void) npi_ipp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep),
21924045d941Ssowmini nxgep->function_num);
219344961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ipp_regs"));
219444961713Sgirish return (0);
219544961713Sgirish }
219644961713Sgirish
219744961713Sgirish /* ARGSUSED */
219844961713Sgirish static int
nxge_param_dump_vlan_table(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)219944961713Sgirish nxge_param_dump_vlan_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
220044961713Sgirish {
220144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_vlan_table"));
220244961713Sgirish
220344961713Sgirish (void) npi_fflp_vlan_tbl_dump(NXGE_DEV_NPI_HANDLE(nxgep));
220444961713Sgirish
220544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_vlan_table"));
220644961713Sgirish return (0);
220744961713Sgirish }
220844961713Sgirish
220944961713Sgirish /* ARGSUSED */
221044961713Sgirish static int
nxge_param_dump_rdc_table(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)221144961713Sgirish nxge_param_dump_rdc_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
221244961713Sgirish {
2213a3c5bd6dSspeer uint8_t table;
221444961713Sgirish
221544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_rdc_table"));
221644961713Sgirish for (table = 0; table < NXGE_MAX_RDC_GROUPS; table++) {
221744961713Sgirish (void) npi_rxdma_dump_rdc_table(NXGE_DEV_NPI_HANDLE(nxgep),
22184045d941Ssowmini table);
221944961713Sgirish }
2220a3c5bd6dSspeer
222144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_rdc_table"));
222244961713Sgirish return (0);
222344961713Sgirish }
222444961713Sgirish
222544961713Sgirish typedef struct block_info {
222644961713Sgirish char *name;
222744961713Sgirish uint32_t offset;
222844961713Sgirish } block_info_t;
222944961713Sgirish
223044961713Sgirish block_info_t reg_block[] = {
223144961713Sgirish {"PIO", PIO},
223244961713Sgirish {"FZC_PIO", FZC_PIO},
223344961713Sgirish {"FZC_XMAC", FZC_MAC},
223444961713Sgirish {"FZC_IPP", FZC_IPP},
223544961713Sgirish {"FFLP", FFLP},
223644961713Sgirish {"FZC_FFLP", FZC_FFLP},
223744961713Sgirish {"PIO_VADDR", PIO_VADDR},
223844961713Sgirish {"ZCP", ZCP},
223944961713Sgirish {"FZC_ZCP", FZC_ZCP},
224044961713Sgirish {"DMC", DMC},
224144961713Sgirish {"FZC_DMC", FZC_DMC},
224244961713Sgirish {"TXC", TXC},
224344961713Sgirish {"FZC_TXC", FZC_TXC},
224444961713Sgirish {"PIO_LDSV", PIO_LDSV},
224544961713Sgirish {"PIO_LDGIM", PIO_LDGIM},
224644961713Sgirish {"PIO_IMASK0", PIO_IMASK0},
224744961713Sgirish {"PIO_IMASK1", PIO_IMASK1},
224844961713Sgirish {"FZC_PROM", FZC_PROM},
224944961713Sgirish {"END", ALL_FF_32},
225044961713Sgirish };
225144961713Sgirish
225244961713Sgirish /* ARGSUSED */
225344961713Sgirish static int
nxge_param_dump_ptrs(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)225444961713Sgirish nxge_param_dump_ptrs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
225544961713Sgirish {
2256a3c5bd6dSspeer uint_t print_len, buf_len;
2257a3c5bd6dSspeer p_mblk_t np;
2258a3c5bd6dSspeer int rdc, tdc, block;
2259a3c5bd6dSspeer uint64_t base;
226044961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp;
226144961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp;
2262a3c5bd6dSspeer int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_8K;
2263*86ef0a63SRichard Lowe p_tx_ring_t *tx_rings;
2264*86ef0a63SRichard Lowe p_rx_rcr_rings_t rx_rcr_rings;
226544961713Sgirish p_rx_rcr_ring_t *rcr_rings;
2266*86ef0a63SRichard Lowe p_rx_rbr_rings_t rx_rbr_rings;
226744961713Sgirish p_rx_rbr_ring_t *rbr_rings;
226844961713Sgirish
2269a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, IOC_CTL,
22704045d941Ssowmini "==> nxge_param_dump_ptrs"));
227144961713Sgirish
2272a3c5bd6dSspeer (void) mi_mpprintf(mp, "ptr information for Port\t %d \n",
22734045d941Ssowmini nxgep->function_num);
227444961713Sgirish
227544961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
227644961713Sgirish /* The following may work even if we cannot get a large buf. */
227744961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer");
227844961713Sgirish return (0);
227944961713Sgirish }
228044961713Sgirish
228144961713Sgirish buf_len = buff_alloc_size;
228244961713Sgirish mp->b_cont = np;
228344961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
228444961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
228544961713Sgirish
228644961713Sgirish rx_rcr_rings = nxgep->rx_rcr_rings;
228744961713Sgirish rcr_rings = rx_rcr_rings->rcr_rings;
228844961713Sgirish rx_rbr_rings = nxgep->rx_rbr_rings;
228944961713Sgirish rbr_rings = rx_rbr_rings->rbr_rings;
229044961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
22914045d941Ssowmini "nxgep (nxge_t) $%p\n"
22924045d941Ssowmini "dev_regs (dev_regs_t) $%p\n",
22938793b36bSNick Todd (void *)nxgep, (void *)nxgep->dev_regs);
229444961713Sgirish
229544961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
2296a3c5bd6dSspeer
2297a3c5bd6dSspeer /* do register pointers */
229844961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
22994045d941Ssowmini "reg base (npi_reg_ptr_t) $%p\t "
23004045d941Ssowmini "pci reg (npi_reg_ptr_t) $%p\n",
23018793b36bSNick Todd (void *)nxgep->dev_regs->nxge_regp,
23028793b36bSNick Todd (void *)nxgep->dev_regs->nxge_pciregp);
230344961713Sgirish
230444961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
230544961713Sgirish
230644961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
23074045d941Ssowmini "\nBlock \t Offset \n");
230844961713Sgirish
230944961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
231044961713Sgirish block = 0;
231144961713Sgirish base = (uint64_t)nxgep->dev_regs->nxge_regp;
231244961713Sgirish while (reg_block[block].offset != ALL_FF_32) {
231344961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
23144045d941Ssowmini "%9s\t 0x%llx\n",
23154045d941Ssowmini reg_block[block].name,
23164045d941Ssowmini (unsigned long long)(reg_block[block].offset + base));
231744961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
231844961713Sgirish block++;
231944961713Sgirish }
232044961713Sgirish
232144961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
23224045d941Ssowmini "\nRDC\t rcrp (rx_rcr_ring_t)\t "
23234045d941Ssowmini "rbrp (rx_rbr_ring_t)\n");
232444961713Sgirish
232544961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
232644961713Sgirish
232744961713Sgirish for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) {
232844961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
23294045d941Ssowmini " %d\t $%p\t\t $%p\n",
23308793b36bSNick Todd rdc, (void *)rcr_rings[rdc],
23318793b36bSNick Todd (void *)rbr_rings[rdc]);
233244961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
233344961713Sgirish }
233444961713Sgirish
233544961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
23364045d941Ssowmini "\nTDC\t tdcp (tx_ring_t)\n");
233744961713Sgirish
233844961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
233944961713Sgirish tx_rings = nxgep->tx_rings->rings;
2340678453a8Sspeer for (tdc = 0; tdc < p_cfgp->tdc.count; tdc++) {
234144961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
23428793b36bSNick Todd " %d\t $%p\n", tdc, (void *)tx_rings[tdc]);
234344961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
234444961713Sgirish }
234544961713Sgirish
2346a3c5bd6dSspeer print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, "\n\n");
234744961713Sgirish
234844961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
234944961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ptrs"));
235044961713Sgirish return (0);
235144961713Sgirish }
235244961713Sgirish
235344961713Sgirish
235444961713Sgirish /* ARGSUSED */
235544961713Sgirish int
nxge_nd_get_names(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t param)235644961713Sgirish nxge_nd_get_names(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t param)
235744961713Sgirish {
2358a3c5bd6dSspeer ND *nd;
2359a3c5bd6dSspeer NDE *nde;
2360a3c5bd6dSspeer char *rwtag;
2361a3c5bd6dSspeer boolean_t get_ok, set_ok;
2362a3c5bd6dSspeer size_t param_len;
2363a3c5bd6dSspeer int status = 0;
236444961713Sgirish
236544961713Sgirish nd = (ND *)param;
236644961713Sgirish if (!nd)
236744961713Sgirish return (ENOENT);
236844961713Sgirish
236944961713Sgirish for (nde = nd->nd_tbl; nde->nde_name; nde++) {
237044961713Sgirish get_ok = (nde->nde_get_pfi != nxge_get_default) &&
23714045d941Ssowmini (nde->nde_get_pfi != NULL);
237244961713Sgirish set_ok = (nde->nde_set_pfi != nxge_set_default) &&
23734045d941Ssowmini (nde->nde_set_pfi != NULL);
237444961713Sgirish if (get_ok) {
237544961713Sgirish if (set_ok)
237644961713Sgirish rwtag = "read and write";
237744961713Sgirish else
237844961713Sgirish rwtag = "read only";
237944961713Sgirish } else if (set_ok)
238044961713Sgirish rwtag = "write only";
238144961713Sgirish else {
238244961713Sgirish continue;
238344961713Sgirish }
238444961713Sgirish param_len = strlen(rwtag);
238544961713Sgirish param_len += strlen(nde->nde_name);
238644961713Sgirish param_len += 4;
238744961713Sgirish
238844961713Sgirish (void) mi_mpprintf(mp, "%s (%s)", nde->nde_name, rwtag);
238944961713Sgirish }
239044961713Sgirish return (status);
239144961713Sgirish }
239244961713Sgirish
239344961713Sgirish /* ARGSUSED */
239444961713Sgirish int
nxge_get_default(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t data)239544961713Sgirish nxge_get_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t data)
239644961713Sgirish {
239744961713Sgirish return (EACCES);
239844961713Sgirish }
239944961713Sgirish
240044961713Sgirish /* ARGSUSED */
240144961713Sgirish int
nxge_set_default(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,char * value,caddr_t data)240244961713Sgirish nxge_set_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, char *value,
2403fe054a6cSToomas Soome caddr_t data)
240444961713Sgirish {
240544961713Sgirish return (EACCES);
240644961713Sgirish }
240744961713Sgirish
24081bd6825cSml boolean_t
nxge_param_link_update(p_nxge_t nxgep)240944961713Sgirish nxge_param_link_update(p_nxge_t nxgep)
241044961713Sgirish {
2411*86ef0a63SRichard Lowe p_nxge_param_t param_arr;
2412*86ef0a63SRichard Lowe nxge_param_index_t i;
2413*86ef0a63SRichard Lowe boolean_t update_xcvr;
2414*86ef0a63SRichard Lowe boolean_t update_dev;
2415*86ef0a63SRichard Lowe int instance;
2416*86ef0a63SRichard Lowe boolean_t status = B_TRUE;
241744961713Sgirish
24181bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_link_update"));
241944961713Sgirish
242044961713Sgirish param_arr = nxgep->param_arr;
242144961713Sgirish instance = nxgep->instance;
242244961713Sgirish update_xcvr = B_FALSE;
242344961713Sgirish for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) {
242444961713Sgirish update_xcvr |= param_arr[i].value;
242544961713Sgirish }
242644961713Sgirish
242744961713Sgirish if (update_xcvr) {
242844961713Sgirish update_xcvr = B_FALSE;
242944961713Sgirish for (i = param_autoneg; i < param_enable_ipg0; i++) {
243044961713Sgirish update_xcvr |=
24314045d941Ssowmini (param_arr[i].value != param_arr[i].old_value);
243244961713Sgirish param_arr[i].old_value = param_arr[i].value;
243344961713Sgirish }
243444961713Sgirish if (update_xcvr) {
24351bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL,
24361bd6825cSml "==> nxge_param_link_update: update xcvr"));
243744961713Sgirish RW_ENTER_WRITER(&nxgep->filter_lock);
243844961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP);
243944961713Sgirish (void) nxge_link_init(nxgep);
244044961713Sgirish (void) nxge_mac_init(nxgep);
244144961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_START);
244244961713Sgirish RW_EXIT(&nxgep->filter_lock);
244344961713Sgirish }
244444961713Sgirish } else {
244544961713Sgirish cmn_err(CE_WARN, " Last setting will leave nxge%d with "
24464045d941Ssowmini " no link capabilities.", instance);
244744961713Sgirish cmn_err(CE_WARN, " Restoring previous setting.");
244844961713Sgirish for (i = param_anar_1000fdx; i < param_anar_asmpause; i++)
244944961713Sgirish param_arr[i].value = param_arr[i].old_value;
245044961713Sgirish }
2451a3c5bd6dSspeer
245244961713Sgirish update_dev = B_FALSE;
245344961713Sgirish
245444961713Sgirish if (update_dev) {
245544961713Sgirish RW_ENTER_WRITER(&nxgep->filter_lock);
24561bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL,
24571bd6825cSml "==> nxge_param_link_update: update dev"));
245844961713Sgirish (void) nxge_rx_mac_disable(nxgep);
245944961713Sgirish (void) nxge_tx_mac_disable(nxgep);
246044961713Sgirish (void) nxge_tx_mac_enable(nxgep);
246144961713Sgirish (void) nxge_rx_mac_enable(nxgep);
246244961713Sgirish RW_EXIT(&nxgep->filter_lock);
246344961713Sgirish }
246444961713Sgirish
246544961713Sgirish nxge_param_hw_update_exit:
246644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL,
24674045d941Ssowmini "<== nxge_param_link_update status = 0x%08x", status));
246844961713Sgirish return (status);
246944961713Sgirish }
24701bd6825cSml
24711bd6825cSml /*
24721bd6825cSml * synchronize the adv* and en* parameters.
24731bd6825cSml *
24741bd6825cSml * See comments in <sys/dld.h> for details of the *_en_*
2475*86ef0a63SRichard Lowe * parameters. The usage of ndd for setting adv parameters will
24761bd6825cSml * synchronize all the en parameters with the nxge parameters,
24771bd6825cSml * implicitly disabling any settings made via dladm.
24781bd6825cSml */
24791bd6825cSml static void
nxge_param_sync(p_nxge_t nxgep)24801bd6825cSml nxge_param_sync(p_nxge_t nxgep)
24811bd6825cSml {
24821bd6825cSml p_nxge_param_t param_arr;
24831bd6825cSml param_arr = nxgep->param_arr;
24841bd6825cSml
24851bd6825cSml nxgep->param_en_pause = param_arr[param_anar_pause].value;
24861bd6825cSml nxgep->param_en_1000fdx = param_arr[param_anar_1000fdx].value;
24871bd6825cSml nxgep->param_en_100fdx = param_arr[param_anar_100fdx].value;
24881bd6825cSml nxgep->param_en_10fdx = param_arr[param_anar_10fdx].value;
24891bd6825cSml }
24901bd6825cSml
24911bd6825cSml /* ARGSUSED */
24921bd6825cSml int
nxge_dld_get_ip_opt(p_nxge_t nxgep,caddr_t cp)24931bd6825cSml nxge_dld_get_ip_opt(p_nxge_t nxgep, caddr_t cp)
24941bd6825cSml {
24951bd6825cSml uint32_t status, cfg_value;
24961bd6825cSml p_nxge_param_t pa = (p_nxge_param_t)cp;
24971bd6825cSml tcam_class_t class;
24981bd6825cSml
24991bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_dld_get_ip_opt"));
25001bd6825cSml
25011bd6825cSml /* do the actual hw setup */
25021bd6825cSml class = nxge_class_name_2value(nxgep, pa->name);
25031bd6825cSml if (class == -1)
25041bd6825cSml return (EINVAL);
25051bd6825cSml
25061bd6825cSml cfg_value = 0;
25071bd6825cSml status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value);
25081bd6825cSml if (status != NXGE_OK)
25091bd6825cSml return (EINVAL);
25101bd6825cSml
2511c1f9c6e5SSantwona Behera /* Filter out the allowed bits */
2512c1f9c6e5SSantwona Behera cfg_value &= (NXGE_CLASS_FLOW_USE_PORTNUM | NXGE_CLASS_FLOW_USE_L2DA |
2513c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_VLAN | NXGE_CLASS_FLOW_USE_PROTO |
2514c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_IPDST |
2515c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_DST_PORT);
2516c1f9c6e5SSantwona Behera
25171bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL,
25181bd6825cSml "nxge_param_get_ip_opt_get %x ", cfg_value));
25191bd6825cSml
25201bd6825cSml pa->value = cfg_value;
25211bd6825cSml
25221bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status "));
25231bd6825cSml return (0);
25241bd6825cSml }
2525