144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 223d16f8e7Sml * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 2344961713Sgirish * Use is subject to license terms. 2444961713Sgirish */ 2544961713Sgirish 2644961713Sgirish #pragma ident "%Z%%M% %I% %E% SMI" 2744961713Sgirish 2844961713Sgirish #include <sys/nxge/nxge_impl.h> 29*678453a8Sspeer #include <sys/nxge/nxge_hio.h> 30*678453a8Sspeer 3144961713Sgirish #include <inet/common.h> 3244961713Sgirish #include <inet/mi.h> 3344961713Sgirish #include <inet/nd.h> 3444961713Sgirish 3544961713Sgirish extern uint64_t npi_debug_level; 3644961713Sgirish 37a3c5bd6dSspeer #define NXGE_PARAM_MAC_RW \ 38a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_MAC | \ 3944961713Sgirish NXGE_PARAM_NDD_WR_OK | NXGE_PARAM_READ_PROP 4044961713Sgirish 41a3c5bd6dSspeer #define NXGE_PARAM_MAC_DONT_SHOW \ 42a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_MAC | NXGE_PARAM_DONT_SHOW 4344961713Sgirish 44a3c5bd6dSspeer #define NXGE_PARAM_RXDMA_RW \ 45a3c5bd6dSspeer NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_NDD_WR_OK | \ 46a3c5bd6dSspeer NXGE_PARAM_READ_PROP 4744961713Sgirish 48a3c5bd6dSspeer #define NXGE_PARAM_RXDMA_RWC \ 49a3c5bd6dSspeer NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_INIT_ONLY | \ 50a3c5bd6dSspeer NXGE_PARAM_READ_PROP 5144961713Sgirish 52a3c5bd6dSspeer #define NXGE_PARAM_L2CLASS_CFG \ 53a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_READ_PROP | \ 54a3c5bd6dSspeer NXGE_PARAM_NDD_WR_OK 5544961713Sgirish 56a3c5bd6dSspeer #define NXGE_PARAM_CLASS_RWS \ 57a3c5bd6dSspeer NXGE_PARAM_RWS | NXGE_PARAM_READ_PROP 5844961713Sgirish 5944961713Sgirish #define NXGE_PARAM_ARRAY_INIT_SIZE 0x20ULL 6044961713Sgirish 6144961713Sgirish #define SET_RX_INTR_TIME_DISABLE 0 6244961713Sgirish #define SET_RX_INTR_TIME_ENABLE 1 6344961713Sgirish #define SET_RX_INTR_PKTS 2 6444961713Sgirish 6544961713Sgirish #define BASE_ANY 0 66a3c5bd6dSspeer #define BASE_BINARY 2 6744961713Sgirish #define BASE_HEX 16 6844961713Sgirish #define BASE_DECIMAL 10 6944961713Sgirish #define ALL_FF_64 0xFFFFFFFFFFFFFFFFULL 7044961713Sgirish #define ALL_FF_32 0xFFFFFFFFUL 7144961713Sgirish 7244961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_SIZE 2048 /* is 2k enough? */ 7344961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_8K 8192 7444961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_16K 0x2000 7544961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_64K 0x8000 7644961713Sgirish 7744961713Sgirish #define PARAM_OUTOF_RANGE(vptr, eptr, rval, pa) \ 7844961713Sgirish ((vptr == eptr) || (rval < pa->minimum) || (rval > pa->maximum)) 7944961713Sgirish 8044961713Sgirish #define ADVANCE_PRINT_BUFFER(pmp, plen, rlen) { \ 8144961713Sgirish ((mblk_t *)pmp)->b_wptr += plen; \ 8244961713Sgirish rlen -= plen; \ 83a3c5bd6dSspeer } 8444961713Sgirish 8544961713Sgirish static int nxge_param_set_mac(p_nxge_t, queue_t *, 86a3c5bd6dSspeer mblk_t *, char *, caddr_t); 8744961713Sgirish static int nxge_param_set_port_rdc(p_nxge_t, queue_t *, 88a3c5bd6dSspeer mblk_t *, char *, caddr_t); 8944961713Sgirish static int nxge_param_set_grp_rdc(p_nxge_t, queue_t *, 90a3c5bd6dSspeer mblk_t *, char *, caddr_t); 9144961713Sgirish static int nxge_param_set_ether_usr(p_nxge_t, 92a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 9344961713Sgirish static int nxge_param_set_ip_usr(p_nxge_t, 94a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 9544961713Sgirish static int nxge_param_set_vlan_rdcgrp(p_nxge_t, 96a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 9744961713Sgirish static int nxge_param_set_mac_rdcgrp(p_nxge_t, 98a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 9944961713Sgirish static int nxge_param_fflp_hash_init(p_nxge_t, 100a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 10144961713Sgirish static int nxge_param_llc_snap_enable(p_nxge_t, queue_t *, 102a3c5bd6dSspeer mblk_t *, char *, caddr_t); 10344961713Sgirish static int nxge_param_hash_lookup_enable(p_nxge_t, queue_t *, 104a3c5bd6dSspeer mblk_t *, char *, caddr_t); 10544961713Sgirish static int nxge_param_tcam_enable(p_nxge_t, queue_t *, 106a3c5bd6dSspeer mblk_t *, char *, caddr_t); 10756d930aeSspeer static int nxge_param_get_fw_ver(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 1082e59129aSraghus static int nxge_param_get_port_mode(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 10944961713Sgirish static int nxge_param_get_rxdma_info(p_nxge_t, queue_t *q, 110a3c5bd6dSspeer p_mblk_t, caddr_t); 11144961713Sgirish static int nxge_param_get_txdma_info(p_nxge_t, queue_t *q, 112a3c5bd6dSspeer p_mblk_t, caddr_t); 11344961713Sgirish static int nxge_param_get_vlan_rdcgrp(p_nxge_t, queue_t *, 114a3c5bd6dSspeer p_mblk_t, caddr_t); 11544961713Sgirish static int nxge_param_get_mac_rdcgrp(p_nxge_t, queue_t *, 116a3c5bd6dSspeer p_mblk_t, caddr_t); 11744961713Sgirish static int nxge_param_get_rxdma_rdcgrp_info(p_nxge_t, queue_t *, 118a3c5bd6dSspeer p_mblk_t, caddr_t); 11944961713Sgirish static int nxge_param_get_ip_opt(p_nxge_t, queue_t *, mblk_t *, caddr_t); 120a3c5bd6dSspeer static int nxge_param_get_mac(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 12144961713Sgirish static int nxge_param_get_debug_flag(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 12244961713Sgirish static int nxge_param_set_nxge_debug_flag(p_nxge_t, queue_t *, mblk_t *, 123a3c5bd6dSspeer char *, caddr_t); 12444961713Sgirish static int nxge_param_set_npi_debug_flag(p_nxge_t, 125a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 12644961713Sgirish static int nxge_param_dump_rdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 12744961713Sgirish static int nxge_param_dump_tdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 12844961713Sgirish static int nxge_param_dump_mac_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 12944961713Sgirish static int nxge_param_dump_ipp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13044961713Sgirish static int nxge_param_dump_fflp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13144961713Sgirish static int nxge_param_dump_vlan_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13244961713Sgirish static int nxge_param_dump_rdc_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13344961713Sgirish static int nxge_param_dump_ptrs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 1341bd6825cSml static void nxge_param_sync(p_nxge_t); 13544961713Sgirish 13644961713Sgirish /* 13744961713Sgirish * Global array of Neptune changable parameters. 13844961713Sgirish * This array is initialized to correspond to the default 13944961713Sgirish * Neptune 4 port configuration. This array would be copied 14044961713Sgirish * into each port's parameter structure and modifed per 14144961713Sgirish * fcode and nxge.conf configuration. Later, the parameters are 14244961713Sgirish * exported to ndd to display and run-time configuration (at least 14344961713Sgirish * some of them). 14444961713Sgirish * 14544961713Sgirish */ 14644961713Sgirish 147a3c5bd6dSspeer static nxge_param_t nxge_param_arr[] = { 148a3c5bd6dSspeer /* 149a3c5bd6dSspeer * min max value old hw-name conf-name 150a3c5bd6dSspeer */ 151846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 152a3c5bd6dSspeer 0, 999, 1000, 0, "instance", "instance"}, 153a3c5bd6dSspeer 154846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 155a3c5bd6dSspeer 0, 999, 1000, 0, "main-instance", "main_instance"}, 156a3c5bd6dSspeer 157a3c5bd6dSspeer { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 158a3c5bd6dSspeer 0, 3, 0, 0, "function-number", "function_number"}, 159a3c5bd6dSspeer 160a3c5bd6dSspeer /* Partition Id */ 161846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 162a3c5bd6dSspeer 0, 8, 0, 0, "partition-id", "partition_id"}, 163a3c5bd6dSspeer 164a3c5bd6dSspeer /* Read Write Permission Mode */ 165846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 166a3c5bd6dSspeer 0, 2, 0, 0, "read-write-mode", "read_write_mode"}, 167a3c5bd6dSspeer 16856d930aeSspeer { nxge_param_get_fw_ver, NULL, NXGE_PARAM_READ, 16956d930aeSspeer 0, 32, 0, 0, "version", "fw_version"}, 17056d930aeSspeer 1712e59129aSraghus { nxge_param_get_port_mode, NULL, NXGE_PARAM_READ, 1722e59129aSraghus 0, 32, 0, 0, "port-mode", "port_mode"}, 1732e59129aSraghus 174a3c5bd6dSspeer /* hw cfg types */ 175a3c5bd6dSspeer /* control the DMA config of Neptune/NIU */ 176846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 177a3c5bd6dSspeer CFG_DEFAULT, CFG_CUSTOM, CFG_DEFAULT, CFG_DEFAULT, 178a3c5bd6dSspeer "niu-cfg-type", "niu_cfg_type"}, 179a3c5bd6dSspeer 180a3c5bd6dSspeer /* control the TXDMA config of the Port controlled by tx-quick-cfg */ 181846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 182a3c5bd6dSspeer CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 183a3c5bd6dSspeer "tx-qcfg-type", "tx_qcfg_type"}, 184a3c5bd6dSspeer 185a3c5bd6dSspeer /* control the RXDMA config of the Port controlled by rx-quick-cfg */ 186846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 187a3c5bd6dSspeer CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 188a3c5bd6dSspeer "rx-qcfg-type", "rx_qcfg_type"}, 189a3c5bd6dSspeer 190a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, 191a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 192a3c5bd6dSspeer 0, 1, 0, 0, "master-cfg-enable", "master_cfg_enable"}, 193a3c5bd6dSspeer 194a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, 195846a903dSml NXGE_PARAM_DONT_SHOW, 196a3c5bd6dSspeer 0, 1, 0, 0, "master-cfg-value", "master_cfg_value"}, 197a3c5bd6dSspeer 198a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 199a3c5bd6dSspeer 0, 1, 1, 1, "adv-autoneg-cap", "adv_autoneg_cap"}, 200a3c5bd6dSspeer 201a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 202a3c5bd6dSspeer 0, 1, 1, 1, "adv-10gfdx-cap", "adv_10gfdx_cap"}, 203a3c5bd6dSspeer 204a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 205a3c5bd6dSspeer 0, 1, 0, 0, "adv-10ghdx-cap", "adv_10ghdx_cap"}, 206a3c5bd6dSspeer 207a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 208a3c5bd6dSspeer 0, 1, 1, 1, "adv-1000fdx-cap", "adv_1000fdx_cap"}, 209a3c5bd6dSspeer 210a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 211a3c5bd6dSspeer 0, 1, 0, 0, "adv-1000hdx-cap", "adv_1000hdx_cap"}, 212a3c5bd6dSspeer 213a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 214a3c5bd6dSspeer 0, 1, 0, 0, "adv-100T4-cap", "adv_100T4_cap"}, 215a3c5bd6dSspeer 216a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 217a3c5bd6dSspeer 0, 1, 1, 1, "adv-100fdx-cap", "adv_100fdx_cap"}, 218a3c5bd6dSspeer 219a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 220a3c5bd6dSspeer 0, 1, 0, 0, "adv-100hdx-cap", "adv_100hdx_cap"}, 221a3c5bd6dSspeer 222a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 223a3c5bd6dSspeer 0, 1, 1, 1, "adv-10fdx-cap", "adv_10fdx_cap"}, 224a3c5bd6dSspeer 225a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 226a3c5bd6dSspeer 0, 1, 0, 0, "adv-10hdx-cap", "adv_10hdx_cap"}, 227a3c5bd6dSspeer 228846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 229a3c5bd6dSspeer 0, 1, 0, 0, "adv-asmpause-cap", "adv_asmpause_cap"}, 230a3c5bd6dSspeer 231a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 232a3c5bd6dSspeer 0, 1, 0, 0, "adv-pause-cap", "adv_pause_cap"}, 233a3c5bd6dSspeer 234846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 235a3c5bd6dSspeer 0, 1, 0, 0, "use-int-xcvr", "use_int_xcvr"}, 236a3c5bd6dSspeer 237846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 238a3c5bd6dSspeer 0, 1, 1, 1, "enable-ipg0", "enable_ipg0"}, 239a3c5bd6dSspeer 240846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 241a3c5bd6dSspeer 0, 255, 8, 8, "ipg0", "ipg0"}, 242a3c5bd6dSspeer 243846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 244a3c5bd6dSspeer 0, 255, 8, 8, "ipg1", "ipg1"}, 245a3c5bd6dSspeer 246846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 247a3c5bd6dSspeer 0, 255, 4, 4, "ipg2", "ipg2"}, 248a3c5bd6dSspeer 249a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 250a3c5bd6dSspeer 0, 1, 0, 0, "accept-jumbo", "accept_jumbo"}, 251a3c5bd6dSspeer 252a3c5bd6dSspeer /* Transmit DMA channels */ 253846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 254846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 255a3c5bd6dSspeer 0, 3, 0, 0, "tx-dma-weight", "tx_dma_weight"}, 256a3c5bd6dSspeer 257846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 258846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 259a3c5bd6dSspeer 0, 31, 0, 0, "tx-dma-channels-begin", "tx_dma_channels_begin"}, 260a3c5bd6dSspeer 261846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 262846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 263a3c5bd6dSspeer 0, 32, 0, 0, "tx-dma-channels", "tx_dma_channels"}, 264a3c5bd6dSspeer { nxge_param_get_txdma_info, NULL, 265846a903dSml NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 266a3c5bd6dSspeer 0, 32, 0, 0, "tx-dma-info", "tx_dma_info"}, 267a3c5bd6dSspeer 268a3c5bd6dSspeer /* Receive DMA channels */ 269a3c5bd6dSspeer { nxge_param_get_generic, NULL, 270846a903dSml NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 271a3c5bd6dSspeer 0, 31, 0, 0, "rx-dma-channels-begin", "rx_dma_channels_begin"}, 272a3c5bd6dSspeer 273846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 274846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 275a3c5bd6dSspeer 0, 32, 0, 0, "rx-dma-channels", "rx_dma_channels"}, 276a3c5bd6dSspeer 277846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 278846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 279a3c5bd6dSspeer 0, 65535, PT_DRR_WT_DEFAULT_10G, 0, 280a3c5bd6dSspeer "rx-drr-weight", "rx_drr_weight"}, 281a3c5bd6dSspeer 282846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 283846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 284a3c5bd6dSspeer 0, 1, 1, 0, "rx-full-header", "rx_full_header"}, 285a3c5bd6dSspeer 286846a903dSml { nxge_param_get_rxdma_info, NULL, NXGE_PARAM_READ | 287846a903dSml NXGE_PARAM_DONT_SHOW, 288a3c5bd6dSspeer 0, 32, 0, 0, "rx-dma-info", "rx_dma_info"}, 289a3c5bd6dSspeer 290a3c5bd6dSspeer { nxge_param_get_rxdma_info, NULL, 291a3c5bd6dSspeer NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 292a3c5bd6dSspeer NXGE_RBR_RBB_MIN, NXGE_RBR_RBB_MAX, NXGE_RBR_RBB_DEFAULT, 0, 293a3c5bd6dSspeer "rx-rbr-size", "rx_rbr_size"}, 294a3c5bd6dSspeer 295a3c5bd6dSspeer { nxge_param_get_rxdma_info, NULL, 296a3c5bd6dSspeer NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 297a3c5bd6dSspeer NXGE_RCR_MIN, NXGE_RCR_MAX, NXGE_RCR_DEFAULT, 0, 298a3c5bd6dSspeer "rx-rcr-size", "rx_rcr_size"}, 299a3c5bd6dSspeer 300846a903dSml { nxge_param_get_generic, nxge_param_set_port_rdc, 301846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 302a3c5bd6dSspeer 0, 15, 0, 0, "default-port-rdc", "default_port_rdc"}, 303a3c5bd6dSspeer 304a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_rx_intr_time, NXGE_PARAM_RXDMA_RW, 305a3c5bd6dSspeer NXGE_RDC_RCR_TIMEOUT_MIN, NXGE_RDC_RCR_TIMEOUT_MAX, 306a3c5bd6dSspeer RXDMA_RCR_TO_DEFAULT, 0, "rxdma-intr-time", "rxdma_intr_time"}, 307a3c5bd6dSspeer 308a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_rx_intr_pkts, NXGE_PARAM_RXDMA_RW, 309a3c5bd6dSspeer NXGE_RDC_RCR_THRESHOLD_MIN, NXGE_RDC_RCR_THRESHOLD_MAX, 310a3c5bd6dSspeer RXDMA_RCR_PTHRES_DEFAULT, 0, 311a3c5bd6dSspeer "rxdma-intr-pkts", "rxdma_intr_pkts"}, 312a3c5bd6dSspeer 313846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 314846a903dSml NXGE_PARAM_DONT_SHOW, 315a3c5bd6dSspeer 0, 8, 0, 0, "rx-rdc-grps-begin", "rx_rdc_grps_begin"}, 316a3c5bd6dSspeer 317846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 318846a903dSml NXGE_PARAM_DONT_SHOW, 319a3c5bd6dSspeer 0, 8, 0, 0, "rx-rdc-grps", "rx_rdc_grps"}, 320a3c5bd6dSspeer 321846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 322846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 323a3c5bd6dSspeer 0, 15, 0, 0, "default-grp0-rdc", "default_grp0_rdc"}, 324a3c5bd6dSspeer 325846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 326846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 327a3c5bd6dSspeer 0, 15, 2, 0, "default-grp1-rdc", "default_grp1_rdc"}, 328a3c5bd6dSspeer 329846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 330846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 331a3c5bd6dSspeer 0, 15, 4, 0, "default-grp2-rdc", "default_grp2_rdc"}, 332a3c5bd6dSspeer 333846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 334846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 335a3c5bd6dSspeer 0, 15, 6, 0, "default-grp3-rdc", "default_grp3_rdc"}, 336a3c5bd6dSspeer 337846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 338846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 339a3c5bd6dSspeer 0, 15, 8, 0, "default-grp4-rdc", "default_grp4_rdc"}, 340a3c5bd6dSspeer 341846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 342846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 343a3c5bd6dSspeer 0, 15, 10, 0, "default-grp5-rdc", "default_grp5_rdc"}, 344a3c5bd6dSspeer 345846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 346846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 347a3c5bd6dSspeer 0, 15, 12, 0, "default-grp6-rdc", "default_grp6_rdc"}, 348a3c5bd6dSspeer 349846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 350846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 351a3c5bd6dSspeer 0, 15, 14, 0, "default-grp7-rdc", "default_grp7_rdc"}, 352a3c5bd6dSspeer 353a3c5bd6dSspeer { nxge_param_get_rxdma_rdcgrp_info, NULL, 354846a903dSml NXGE_PARAM_READ | NXGE_PARAM_CMPLX | NXGE_PARAM_DONT_SHOW, 355a3c5bd6dSspeer 0, 8, 0, 0, "rdc-groups-info", "rdc_groups_info"}, 356a3c5bd6dSspeer 357a3c5bd6dSspeer /* Logical device groups */ 358846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 359a3c5bd6dSspeer 0, 63, 0, 0, "start-ldg", "start_ldg"}, 360a3c5bd6dSspeer 361846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 362a3c5bd6dSspeer 0, 64, 0, 0, "max-ldg", "max_ldg" }, 363a3c5bd6dSspeer 364a3c5bd6dSspeer /* MAC table information */ 365a3c5bd6dSspeer { nxge_param_get_mac_rdcgrp, nxge_param_set_mac_rdcgrp, 366846a903dSml NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 367a3c5bd6dSspeer 0, 31, 0, 0, "mac-2rdc-grp", "mac_2rdc_grp"}, 368a3c5bd6dSspeer 369a3c5bd6dSspeer /* VLAN table information */ 370a3c5bd6dSspeer { nxge_param_get_vlan_rdcgrp, nxge_param_set_vlan_rdcgrp, 371846a903dSml NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 372a3c5bd6dSspeer 0, 31, 0, 0, "vlan-2rdc-grp", "vlan_2rdc_grp"}, 373a3c5bd6dSspeer 374a3c5bd6dSspeer { nxge_param_get_generic, NULL, 375846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_READ | 376846a903dSml NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_DONT_SHOW, 377a3c5bd6dSspeer 0, 0x0ffff, 0x0ffff, 0, "fcram-part-cfg", "fcram_part_cfg"}, 378a3c5bd6dSspeer 379846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 380846a903dSml NXGE_PARAM_DONT_SHOW, 381a3c5bd6dSspeer 0, 0x10, 0xa, 0, "fcram-access-ratio", "fcram_access_ratio"}, 382a3c5bd6dSspeer 383846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 384846a903dSml NXGE_PARAM_DONT_SHOW, 385a3c5bd6dSspeer 0, 0x10, 0xa, 0, "tcam-access-ratio", "tcam_access_ratio"}, 386a3c5bd6dSspeer 387a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_tcam_enable, 388846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 389a3c5bd6dSspeer 0, 0x1, 0x0, 0, "tcam-enable", "tcam_enable"}, 390a3c5bd6dSspeer 391a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_hash_lookup_enable, 392846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 393a3c5bd6dSspeer 0, 0x01, 0x0, 0, "hash-lookup-enable", "hash_lookup_enable"}, 394a3c5bd6dSspeer 395a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_llc_snap_enable, 396846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 397a3c5bd6dSspeer 0, 0x01, 0x01, 0, "llc-snap-enable", "llc_snap_enable"}, 398a3c5bd6dSspeer 399a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_fflp_hash_init, 400846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 401a3c5bd6dSspeer 0, ALL_FF_32, ALL_FF_32, 0, "h1-init-value", "h1_init_value"}, 402a3c5bd6dSspeer 403a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_fflp_hash_init, 404846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 405a3c5bd6dSspeer 0, 0x0ffff, 0x0ffff, 0, "h2-init-value", "h2_init_value"}, 406a3c5bd6dSspeer 407a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ether_usr, 408a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 409a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 410a3c5bd6dSspeer "class-cfg-ether-usr1", "class_cfg_ether_usr1"}, 411a3c5bd6dSspeer 412a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ether_usr, 413a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 414a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 415a3c5bd6dSspeer "class-cfg-ether-usr2", "class_cfg_ether_usr2"}, 416a3c5bd6dSspeer 417a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 418a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 419a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 420a3c5bd6dSspeer "class-cfg-ip-usr4", "class_cfg_ip_usr4"}, 421a3c5bd6dSspeer 422a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 423a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 424a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 425a3c5bd6dSspeer "class-cfg-ip-usr5", "class_cfg_ip_usr5"}, 426a3c5bd6dSspeer 427a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 428a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 429a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 430a3c5bd6dSspeer "class-cfg-ip-usr6", "class_cfg_ip_usr6"}, 431a3c5bd6dSspeer 432a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 433a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 434a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 435a3c5bd6dSspeer "class-cfg-ip-usr7", "class_cfg_ip_usr7"}, 436a3c5bd6dSspeer 437a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 438a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 439a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 440a3c5bd6dSspeer "class-opt-ip-usr4", "class_opt_ip_usr4"}, 441a3c5bd6dSspeer 442a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 443a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 444a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 445a3c5bd6dSspeer "class-opt-ip-usr5", "class_opt_ip_usr5"}, 446a3c5bd6dSspeer 447a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 448a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 449a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 450a3c5bd6dSspeer "class-opt-ip-usr6", "class_opt_ip_usr6"}, 451a3c5bd6dSspeer 452a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 453a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 454a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 455a3c5bd6dSspeer "class-opt-ip-usr7", "class_opt_ip_usr7"}, 456a3c5bd6dSspeer 457a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 458a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 459a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 460a3c5bd6dSspeer "class-opt-ipv4-tcp", "class_opt_ipv4_tcp"}, 461a3c5bd6dSspeer 462a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 463a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 464a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 465a3c5bd6dSspeer "class-opt-ipv4-udp", "class_opt_ipv4_udp"}, 466a3c5bd6dSspeer 467a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 468a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 469a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 470a3c5bd6dSspeer "class-opt-ipv4-ah", "class_opt_ipv4_ah"}, 471a3c5bd6dSspeer 472a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 473a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 474a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 475a3c5bd6dSspeer "class-opt-ipv4-sctp", "class_opt_ipv4_sctp"}, 476a3c5bd6dSspeer 477a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 478a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 479a3c5bd6dSspeer "class-opt-ipv6-tcp", "class_opt_ipv6_tcp"}, 480a3c5bd6dSspeer 481a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 482a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 483a3c5bd6dSspeer "class-opt-ipv6-udp", "class_opt_ipv6_udp"}, 484a3c5bd6dSspeer 485a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 486a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 487a3c5bd6dSspeer "class-opt-ipv6-ah", "class_opt_ipv6_ah"}, 488a3c5bd6dSspeer 489a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 490a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 491a3c5bd6dSspeer "class-opt-ipv6-sctp", "class_opt_ipv6_sctp"}, 492a3c5bd6dSspeer 493a3c5bd6dSspeer { nxge_param_get_debug_flag, nxge_param_set_nxge_debug_flag, 494846a903dSml NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 495a3c5bd6dSspeer 0ULL, ALL_FF_64, 0ULL, 0ULL, 496a3c5bd6dSspeer "nxge-debug-flag", "nxge_debug_flag"}, 497a3c5bd6dSspeer 498a3c5bd6dSspeer { nxge_param_get_debug_flag, nxge_param_set_npi_debug_flag, 499846a903dSml NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 500a3c5bd6dSspeer 0ULL, ALL_FF_64, 0ULL, 0ULL, 501a3c5bd6dSspeer "npi-debug-flag", "npi_debug_flag"}, 502a3c5bd6dSspeer 503846a903dSml { nxge_param_dump_tdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 504a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-tdc", "dump_tdc"}, 505a3c5bd6dSspeer 506846a903dSml { nxge_param_dump_rdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 507a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-rdc", "dump_rdc"}, 508a3c5bd6dSspeer 509846a903dSml { nxge_param_dump_mac_regs, NULL, NXGE_PARAM_READ | 510846a903dSml NXGE_PARAM_DONT_SHOW, 511a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-mac-regs", "dump_mac_regs"}, 512a3c5bd6dSspeer 513846a903dSml { nxge_param_dump_ipp_regs, NULL, NXGE_PARAM_READ | 514846a903dSml NXGE_PARAM_DONT_SHOW, 515a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-ipp-regs", "dump_ipp_regs"}, 516a3c5bd6dSspeer 517846a903dSml { nxge_param_dump_fflp_regs, NULL, NXGE_PARAM_READ | 518846a903dSml NXGE_PARAM_DONT_SHOW, 519a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, 520a3c5bd6dSspeer "dump-fflp-regs", "dump_fflp_regs"}, 521a3c5bd6dSspeer 522846a903dSml { nxge_param_dump_vlan_table, NULL, NXGE_PARAM_READ | 523846a903dSml NXGE_PARAM_DONT_SHOW, 524a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, 525a3c5bd6dSspeer "dump-vlan-table", "dump_vlan_table"}, 526a3c5bd6dSspeer 527846a903dSml { nxge_param_dump_rdc_table, NULL, NXGE_PARAM_READ | 528846a903dSml NXGE_PARAM_DONT_SHOW, 529a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, 530a3c5bd6dSspeer "dump-rdc-table", "dump_rdc_table"}, 531a3c5bd6dSspeer 532846a903dSml { nxge_param_dump_ptrs, NULL, NXGE_PARAM_READ | 533846a903dSml NXGE_PARAM_DONT_SHOW, 534a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-ptrs", "dump_ptrs"}, 535a3c5bd6dSspeer 536a3c5bd6dSspeer { NULL, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 537a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "end", "end"}, 53844961713Sgirish }; 53944961713Sgirish 54044961713Sgirish extern void *nxge_list; 54144961713Sgirish 54244961713Sgirish void 54344961713Sgirish nxge_get_param_soft_properties(p_nxge_t nxgep) 54444961713Sgirish { 54544961713Sgirish 54644961713Sgirish p_nxge_param_t param_arr; 54744961713Sgirish uint_t prop_len; 54844961713Sgirish int i, j; 549a3c5bd6dSspeer uint32_t param_count; 550a3c5bd6dSspeer uint32_t *int_prop_val; 55144961713Sgirish 55244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, " ==> nxge_get_param_soft_properties")); 55344961713Sgirish 55444961713Sgirish param_arr = nxgep->param_arr; 55544961713Sgirish param_count = nxgep->param_count; 55644961713Sgirish for (i = 0; i < param_count; i++) { 55744961713Sgirish if ((param_arr[i].type & NXGE_PARAM_READ_PROP) == 0) 55844961713Sgirish continue; 55944961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PROP_STR)) 56044961713Sgirish continue; 56144961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 5621bd6825cSml (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 56344961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 564a3c5bd6dSspeer nxgep->dip, 0, param_arr[i].fcode_name, 565a3c5bd6dSspeer (int **)&int_prop_val, 566a3c5bd6dSspeer (uint_t *)&prop_len) 567a3c5bd6dSspeer == DDI_PROP_SUCCESS) { 56844961713Sgirish uint32_t *cfg_value; 56944961713Sgirish uint64_t prop_count; 570a3c5bd6dSspeer 57144961713Sgirish if (prop_len > NXGE_PARAM_ARRAY_INIT_SIZE) 57244961713Sgirish prop_len = NXGE_PARAM_ARRAY_INIT_SIZE; 573adfcba55Sjoycey #if defined(__i386) 574adfcba55Sjoycey cfg_value = 575adfcba55Sjoycey (uint32_t *)(int32_t)param_arr[i].value; 576adfcba55Sjoycey #else 57744961713Sgirish cfg_value = (uint32_t *)param_arr[i].value; 578adfcba55Sjoycey #endif 57944961713Sgirish for (j = 0; j < prop_len; j++) { 58044961713Sgirish cfg_value[j] = int_prop_val[j]; 58144961713Sgirish } 58244961713Sgirish prop_count = prop_len; 58344961713Sgirish param_arr[i].type |= 58444961713Sgirish (prop_count << NXGE_PARAM_ARRAY_CNT_SHIFT); 58544961713Sgirish ddi_prop_free(int_prop_val); 58644961713Sgirish } 58744961713Sgirish continue; 58844961713Sgirish } 58944961713Sgirish 59044961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 591a3c5bd6dSspeer param_arr[i].fcode_name, 592a3c5bd6dSspeer (int **)&int_prop_val, 593a3c5bd6dSspeer &prop_len) == DDI_PROP_SUCCESS) { 59444961713Sgirish if ((*int_prop_val >= param_arr[i].minimum) && 595a3c5bd6dSspeer (*int_prop_val <= param_arr[i].maximum)) 59644961713Sgirish param_arr[i].value = *int_prop_val; 59744961713Sgirish #ifdef NXGE_DEBUG_ERROR 59844961713Sgirish else { 59944961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 600a3c5bd6dSspeer "nxge%d: 'prom' file parameter error\n", 601a3c5bd6dSspeer nxgep->instance)); 60244961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 603a3c5bd6dSspeer "Parameter keyword '%s'" 604a3c5bd6dSspeer " is outside valid range\n", 605a3c5bd6dSspeer param_arr[i].name)); 60644961713Sgirish } 60744961713Sgirish #endif 60844961713Sgirish ddi_prop_free(int_prop_val); 60944961713Sgirish } 61044961713Sgirish 61144961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 612a3c5bd6dSspeer param_arr[i].name, 613a3c5bd6dSspeer (int **)&int_prop_val, 614a3c5bd6dSspeer &prop_len) == DDI_PROP_SUCCESS) { 61544961713Sgirish if ((*int_prop_val >= param_arr[i].minimum) && 61644961713Sgirish (*int_prop_val <= param_arr[i].maximum)) 61744961713Sgirish param_arr[i].value = *int_prop_val; 61844961713Sgirish #ifdef NXGE_DEBUG_ERROR 61944961713Sgirish else { 62044961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 621a3c5bd6dSspeer "nxge%d: 'conf' file parameter error\n", 622a3c5bd6dSspeer nxgep->instance)); 62344961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 624a3c5bd6dSspeer "Parameter keyword '%s'" 625a3c5bd6dSspeer "is outside valid range\n", 626a3c5bd6dSspeer param_arr[i].name)); 62744961713Sgirish } 62844961713Sgirish #endif 62944961713Sgirish ddi_prop_free(int_prop_val); 63044961713Sgirish } 63144961713Sgirish } 63244961713Sgirish } 63344961713Sgirish 63444961713Sgirish static int 63544961713Sgirish nxge_private_param_register(p_nxge_t nxgep, p_nxge_param_t param_arr) 63644961713Sgirish { 63744961713Sgirish int status = B_TRUE; 63844961713Sgirish int channel; 63944961713Sgirish uint8_t grp; 64044961713Sgirish char *prop_name; 64144961713Sgirish char *end; 64244961713Sgirish uint32_t name_chars; 64344961713Sgirish 64444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 645a3c5bd6dSspeer "nxge_private_param_register %s", param_arr->name)); 64644961713Sgirish 64744961713Sgirish if ((param_arr->type & NXGE_PARAM_PRIV) != NXGE_PARAM_PRIV) 64844961713Sgirish return (B_TRUE); 649a3c5bd6dSspeer 65044961713Sgirish prop_name = param_arr->name; 65144961713Sgirish if (param_arr->type & NXGE_PARAM_RXDMA) { 65244961713Sgirish if (strncmp("rxdma_intr", prop_name, 10) == 0) 65344961713Sgirish return (B_TRUE); 65444961713Sgirish name_chars = strlen("default_grp"); 65544961713Sgirish if (strncmp("default_grp", prop_name, name_chars) == 0) { 65644961713Sgirish prop_name += name_chars; 65744961713Sgirish grp = mi_strtol(prop_name, &end, 10); 65844961713Sgirish /* now check if this rdcgrp is in config */ 65944961713Sgirish return (nxge_check_rdcgrp_port_member(nxgep, grp)); 66044961713Sgirish } 66144961713Sgirish name_chars = strlen(prop_name); 66244961713Sgirish if (strncmp("default_port_rdc", prop_name, name_chars) == 0) { 66344961713Sgirish return (B_TRUE); 66444961713Sgirish } 66544961713Sgirish return (B_FALSE); 66644961713Sgirish } 66744961713Sgirish 66844961713Sgirish if (param_arr->type & NXGE_PARAM_TXDMA) { 66944961713Sgirish name_chars = strlen("txdma"); 67044961713Sgirish if (strncmp("txdma", prop_name, name_chars) == 0) { 67144961713Sgirish prop_name += name_chars; 67244961713Sgirish channel = mi_strtol(prop_name, &end, 10); 67344961713Sgirish /* now check if this rdc is in config */ 67444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 67544961713Sgirish " nxge_private_param_register: %d", 67644961713Sgirish channel)); 67744961713Sgirish return (nxge_check_txdma_port_member(nxgep, channel)); 67844961713Sgirish } 67944961713Sgirish return (B_FALSE); 68044961713Sgirish } 68144961713Sgirish 68244961713Sgirish status = B_FALSE; 68344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, "<== nxge_private_param_register")); 68444961713Sgirish 68544961713Sgirish return (status); 68644961713Sgirish } 68744961713Sgirish 68844961713Sgirish void 68944961713Sgirish nxge_setup_param(p_nxge_t nxgep) 69044961713Sgirish { 69144961713Sgirish p_nxge_param_t param_arr; 69244961713Sgirish int i; 69344961713Sgirish pfi_t set_pfi; 69444961713Sgirish 69544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_setup_param")); 696a3c5bd6dSspeer 69744961713Sgirish /* 69844961713Sgirish * Make sure the param_instance is set to a valid device instance. 69944961713Sgirish */ 70044961713Sgirish if (nxge_param_arr[param_instance].value == 1000) 70144961713Sgirish nxge_param_arr[param_instance].value = nxgep->instance; 70244961713Sgirish 70344961713Sgirish param_arr = nxgep->param_arr; 70444961713Sgirish param_arr[param_instance].value = nxgep->instance; 70544961713Sgirish param_arr[param_function_number].value = nxgep->function_num; 70644961713Sgirish 70744961713Sgirish for (i = 0; i < nxgep->param_count; i++) { 70844961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PRIV) && 709a3c5bd6dSspeer (nxge_private_param_register(nxgep, 710a3c5bd6dSspeer ¶m_arr[i]) == B_FALSE)) { 71144961713Sgirish param_arr[i].setf = NULL; 71244961713Sgirish param_arr[i].getf = NULL; 71344961713Sgirish } 71444961713Sgirish 71544961713Sgirish if (param_arr[i].type & NXGE_PARAM_CMPLX) 71644961713Sgirish param_arr[i].setf = NULL; 71744961713Sgirish 71844961713Sgirish if (param_arr[i].type & NXGE_PARAM_DONT_SHOW) { 71944961713Sgirish param_arr[i].setf = NULL; 72044961713Sgirish param_arr[i].getf = NULL; 72144961713Sgirish } 72244961713Sgirish 72344961713Sgirish set_pfi = (pfi_t)param_arr[i].setf; 72444961713Sgirish 725a3c5bd6dSspeer if ((set_pfi) && (param_arr[i].type & NXGE_PARAM_INIT_ONLY)) { 72644961713Sgirish set_pfi = NULL; 72744961713Sgirish } 72844961713Sgirish 729a3c5bd6dSspeer if (!nxge_nd_load(&nxgep->param_list, param_arr[i].name, 730a3c5bd6dSspeer (pfi_t)param_arr[i].getf, set_pfi, 73144961713Sgirish (caddr_t)¶m_arr[i])) { 73244961713Sgirish (void) nxge_nd_free(&nxgep->param_list); 73344961713Sgirish break; 73444961713Sgirish } 73544961713Sgirish } 73644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_setup_param")); 73744961713Sgirish } 73844961713Sgirish 73944961713Sgirish void 74044961713Sgirish nxge_init_param(p_nxge_t nxgep) 74144961713Sgirish { 74244961713Sgirish p_nxge_param_t param_arr; 74344961713Sgirish int i, alloc_size; 74444961713Sgirish uint64_t alloc_count; 74544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_init_param")); 74644961713Sgirish /* 74744961713Sgirish * Make sure the param_instance is set to a valid device instance. 74844961713Sgirish */ 74944961713Sgirish if (nxge_param_arr[param_instance].value == 1000) 75044961713Sgirish nxge_param_arr[param_instance].value = nxgep->instance; 75144961713Sgirish 75244961713Sgirish param_arr = nxgep->param_arr; 75344961713Sgirish if (param_arr == NULL) { 754a3c5bd6dSspeer param_arr = (p_nxge_param_t) 755a3c5bd6dSspeer KMEM_ZALLOC(sizeof (nxge_param_arr), KM_SLEEP); 75644961713Sgirish } 757a3c5bd6dSspeer 75844961713Sgirish for (i = 0; i < sizeof (nxge_param_arr)/sizeof (nxge_param_t); i++) { 75944961713Sgirish param_arr[i] = nxge_param_arr[i]; 76044961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 76144961713Sgirish (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 76244961713Sgirish alloc_count = NXGE_PARAM_ARRAY_INIT_SIZE; 76344961713Sgirish alloc_size = alloc_count * sizeof (uint64_t); 76444961713Sgirish param_arr[i].value = 765adfcba55Sjoycey #if defined(__i386) 7661bd6825cSml (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 767adfcba55Sjoycey #else 7681bd6825cSml (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 769adfcba55Sjoycey #endif 77044961713Sgirish param_arr[i].old_value = 771adfcba55Sjoycey #if defined(__i386) 772adfcba55Sjoycey (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size, 773adfcba55Sjoycey KM_SLEEP); 774adfcba55Sjoycey #else 775adfcba55Sjoycey (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 776adfcba55Sjoycey #endif 77744961713Sgirish param_arr[i].type |= 77844961713Sgirish (alloc_count << NXGE_PARAM_ARRAY_ALLOC_SHIFT); 77944961713Sgirish } 78044961713Sgirish } 78144961713Sgirish 78244961713Sgirish nxgep->param_arr = param_arr; 78344961713Sgirish nxgep->param_count = sizeof (nxge_param_arr)/sizeof (nxge_param_t); 7841bd6825cSml 7851bd6825cSml nxge_param_sync(nxgep); 7861bd6825cSml 78744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init_param: count %d", 788a3c5bd6dSspeer nxgep->param_count)); 78944961713Sgirish } 79044961713Sgirish 79144961713Sgirish void 79244961713Sgirish nxge_destroy_param(p_nxge_t nxgep) 79344961713Sgirish { 79444961713Sgirish int i; 79544961713Sgirish uint64_t free_size, free_count; 79644961713Sgirish 79744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_param")); 798a3c5bd6dSspeer 79959ac0c16Sdavemq if (nxgep->param_arr == NULL) 80059ac0c16Sdavemq return; 80144961713Sgirish /* 80244961713Sgirish * Make sure the param_instance is set to a valid device instance. 80344961713Sgirish */ 80444961713Sgirish if (nxge_param_arr[param_instance].value == nxgep->instance) { 80544961713Sgirish for (i = 0; i <= nxge_param_arr[param_instance].maximum; i++) { 80644961713Sgirish if ((ddi_get_soft_state(nxge_list, i) != NULL) && 80744961713Sgirish (i != nxgep->instance)) 80844961713Sgirish break; 80944961713Sgirish } 81044961713Sgirish nxge_param_arr[param_instance].value = i; 81144961713Sgirish } 81244961713Sgirish 81344961713Sgirish if (nxgep->param_list) 81444961713Sgirish nxge_nd_free(&nxgep->param_list); 81544961713Sgirish for (i = 0; i < nxgep->param_count; i++) 81644961713Sgirish if ((nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 81744961713Sgirish (nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 81844961713Sgirish free_count = ((nxgep->param_arr[i].type & 81944961713Sgirish NXGE_PARAM_ARRAY_ALLOC_MASK) >> 82044961713Sgirish NXGE_PARAM_ARRAY_ALLOC_SHIFT); 82144961713Sgirish free_count = NXGE_PARAM_ARRAY_INIT_SIZE; 82244961713Sgirish free_size = sizeof (uint64_t) * free_count; 823adfcba55Sjoycey #if defined(__i386) 824adfcba55Sjoycey KMEM_FREE((void *)(uint32_t)nxgep->param_arr[i].value, 825adfcba55Sjoycey free_size); 826adfcba55Sjoycey #else 82744961713Sgirish KMEM_FREE((void *)nxgep->param_arr[i].value, free_size); 828adfcba55Sjoycey #endif 829adfcba55Sjoycey #if defined(__i386) 830adfcba55Sjoycey KMEM_FREE((void *)(uint32_t) 831adfcba55Sjoycey nxgep->param_arr[i].old_value, free_size); 832adfcba55Sjoycey #else 83344961713Sgirish KMEM_FREE((void *)nxgep->param_arr[i].old_value, 834a3c5bd6dSspeer free_size); 835adfcba55Sjoycey #endif 83644961713Sgirish } 83744961713Sgirish 83844961713Sgirish KMEM_FREE(nxgep->param_arr, sizeof (nxge_param_arr)); 83944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_param")); 84044961713Sgirish } 84144961713Sgirish 84244961713Sgirish /* 84344961713Sgirish * Extracts the value from the 'nxge' parameter array and prints the 84444961713Sgirish * parameter value. cp points to the required parameter. 84544961713Sgirish */ 846a3c5bd6dSspeer 84744961713Sgirish /* ARGSUSED */ 84844961713Sgirish int 84944961713Sgirish nxge_param_get_generic(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 85044961713Sgirish { 85144961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 85244961713Sgirish 853a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, 854a3c5bd6dSspeer "==> nxge_param_get_generic name %s ", pa->name)); 85544961713Sgirish 85644961713Sgirish if (pa->value > 0xffffffff) 857a3c5bd6dSspeer (void) mi_mpprintf(mp, "%x%x", 858a3c5bd6dSspeer (int)(pa->value >> 32), (int)(pa->value & 0xffffffff)); 85944961713Sgirish else 86044961713Sgirish (void) mi_mpprintf(mp, "%x", (int)pa->value); 86144961713Sgirish 86244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_generic")); 86344961713Sgirish return (0); 86444961713Sgirish } 86544961713Sgirish 86644961713Sgirish /* ARGSUSED */ 86744961713Sgirish static int 86844961713Sgirish nxge_param_get_mac(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 86944961713Sgirish { 87044961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 87144961713Sgirish 87244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac")); 87344961713Sgirish 87444961713Sgirish (void) mi_mpprintf(mp, "%d", (uint32_t)pa->value); 87544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_mac")); 87644961713Sgirish return (0); 87744961713Sgirish } 87844961713Sgirish 87956d930aeSspeer /* ARGSUSED */ 88056d930aeSspeer static int 88156d930aeSspeer nxge_param_get_fw_ver(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 88256d930aeSspeer { 88356d930aeSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_fw_ver")); 88456d930aeSspeer 88556d930aeSspeer (void) mi_mpprintf(mp, "Firmware version for nxge%d: %s\n", 88656d930aeSspeer nxgep->instance, nxgep->vpd_info.ver); 88756d930aeSspeer 88856d930aeSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_fw_ver")); 88956d930aeSspeer return (0); 89056d930aeSspeer } 89156d930aeSspeer 8922e59129aSraghus /* ARGSUSED */ 8932e59129aSraghus static int 8942e59129aSraghus nxge_param_get_port_mode(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 8952e59129aSraghus { 8962e59129aSraghus NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_port_mode")); 8972e59129aSraghus 8982e59129aSraghus switch (nxgep->mac.portmode) { 8992e59129aSraghus case PORT_1G_COPPER: 9002d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Copper %s\n", 9012d17280bSsbehera nxgep->instance, 9022d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9032e59129aSraghus break; 9042e59129aSraghus case PORT_1G_FIBER: 9052d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Fiber %s\n", 9062d17280bSsbehera nxgep->instance, 9072d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9082e59129aSraghus break; 9092e59129aSraghus case PORT_10G_COPPER: 9102d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Copper " 9112d17280bSsbehera "%s\n", nxgep->instance, 9122d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9132e59129aSraghus break; 9142e59129aSraghus case PORT_10G_FIBER: 9152d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Fiber %s\n", 9162d17280bSsbehera nxgep->instance, 9172d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9182e59129aSraghus break; 9192e59129aSraghus case PORT_10G_SERDES: 9202d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Serdes " 9212d17280bSsbehera "%s\n", nxgep->instance, 9222d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9232e59129aSraghus break; 9242e59129aSraghus case PORT_1G_SERDES: 9252d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Serdes %s\n", 9262d17280bSsbehera nxgep->instance, 9272d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9282e59129aSraghus break; 9292e59129aSraghus case PORT_1G_RGMII_FIBER: 9302e59129aSraghus (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G RGMII " 9312d17280bSsbehera "Fiber %s\n", nxgep->instance, 9322d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9332d17280bSsbehera break; 9342d17280bSsbehera case PORT_HSP_MODE: 9352d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: Hot Swappable " 9362d17280bSsbehera "PHY, Currently NOT present\n", nxgep->instance); 9372e59129aSraghus break; 9382e59129aSraghus default: 9392d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: Unknown %s\n", 9402d17280bSsbehera nxgep->instance, 9412d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9422e59129aSraghus break; 9432e59129aSraghus } 9442e59129aSraghus 9453d16f8e7Sml (void) mi_mpprintf(mp, "Software LSO for nxge%d: %s\n", 9463d16f8e7Sml nxgep->instance, 9473d16f8e7Sml nxgep->soft_lso_enable ? "enable" : "disable"); 9483d16f8e7Sml 9492e59129aSraghus NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_port_mode")); 9502e59129aSraghus return (0); 9512e59129aSraghus } 9522e59129aSraghus 95344961713Sgirish /* ARGSUSED */ 95444961713Sgirish int 95544961713Sgirish nxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 95644961713Sgirish { 95744961713Sgirish 958*678453a8Sspeer uint_t print_len, buf_len; 95944961713Sgirish p_mblk_t np; 96044961713Sgirish 96144961713Sgirish int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 962*678453a8Sspeer int tdc; 963*678453a8Sspeer 964*678453a8Sspeer nxge_grp_set_t *set; 965*678453a8Sspeer 96644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_txdma_info")); 96744961713Sgirish 968a3c5bd6dSspeer (void) mi_mpprintf(mp, "TXDMA Information for Port\t %d \n", 969a3c5bd6dSspeer nxgep->function_num); 97044961713Sgirish 97144961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 97244961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 97344961713Sgirish return (0); 97444961713Sgirish } 97544961713Sgirish 97644961713Sgirish buf_len = buff_alloc_size; 97744961713Sgirish mp->b_cont = np; 978*678453a8Sspeer print_len = 0; 97944961713Sgirish 98044961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 98144961713Sgirish buf_len -= print_len; 98244961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 983a3c5bd6dSspeer "TDC\t HW TDC\t\n"); 98444961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 98544961713Sgirish buf_len -= print_len; 986*678453a8Sspeer 987*678453a8Sspeer set = &nxgep->tx_set; 988*678453a8Sspeer for (tdc = 0; tdc < NXGE_MAX_RDCS; tdc++) { 989*678453a8Sspeer if ((1 << tdc) & set->owned.map) { 990*678453a8Sspeer print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 991*678453a8Sspeer buf_len, "%d\n", tdc); 992*678453a8Sspeer ((mblk_t *)np)->b_wptr += print_len; 993*678453a8Sspeer buf_len -= print_len; 994*678453a8Sspeer } 99544961713Sgirish } 996a3c5bd6dSspeer 99744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_txdma_info")); 99844961713Sgirish return (0); 99944961713Sgirish } 100044961713Sgirish 100144961713Sgirish /* ARGSUSED */ 100244961713Sgirish int 100344961713Sgirish nxge_param_get_rxdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 100444961713Sgirish { 1005a3c5bd6dSspeer uint_t print_len, buf_len; 1006a3c5bd6dSspeer p_mblk_t np; 1007a3c5bd6dSspeer int rdc; 100844961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 100944961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1010a3c5bd6dSspeer int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 101144961713Sgirish p_rx_rcr_rings_t rx_rcr_rings; 101244961713Sgirish p_rx_rcr_ring_t *rcr_rings; 101344961713Sgirish p_rx_rbr_rings_t rx_rbr_rings; 101444961713Sgirish p_rx_rbr_ring_t *rbr_rings; 1015*678453a8Sspeer nxge_grp_set_t *set; 101644961713Sgirish 101744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rxdma_info")); 101844961713Sgirish 1019a3c5bd6dSspeer (void) mi_mpprintf(mp, "RXDMA Information for Port\t %d \n", 1020a3c5bd6dSspeer nxgep->function_num); 102144961713Sgirish 102244961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 102344961713Sgirish /* The following may work even if we cannot get a large buf. */ 102444961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 102544961713Sgirish return (0); 102644961713Sgirish } 102744961713Sgirish 102844961713Sgirish buf_len = buff_alloc_size; 102944961713Sgirish mp->b_cont = np; 103044961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 103144961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 103244961713Sgirish 103344961713Sgirish rx_rcr_rings = nxgep->rx_rcr_rings; 103444961713Sgirish rcr_rings = rx_rcr_rings->rcr_rings; 103544961713Sgirish rx_rbr_rings = nxgep->rx_rbr_rings; 103644961713Sgirish rbr_rings = rx_rbr_rings->rbr_rings; 103744961713Sgirish 103844961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1039a3c5bd6dSspeer "Total RDCs\t %d\n", p_cfgp->max_rdcs); 104044961713Sgirish 104144961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 104244961713Sgirish buf_len -= print_len; 104344961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1044a3c5bd6dSspeer "RDC\t HW RDC\t Timeout\t Packets RBR ptr \t" 1045a3c5bd6dSspeer "chunks\t RCR ptr\n"); 1046a3c5bd6dSspeer 104744961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 104844961713Sgirish buf_len -= print_len; 1049*678453a8Sspeer 1050*678453a8Sspeer set = &nxgep->rx_set; 1051*678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1052*678453a8Sspeer if ((1 << rdc) & set->owned.map) { 1053*678453a8Sspeer print_len = snprintf((char *) 1054*678453a8Sspeer ((mblk_t *)np)->b_wptr, buf_len, 1055*678453a8Sspeer " %d\t %x\t\t %x\t $%p\t 0x%x\t $%p\n", 1056*678453a8Sspeer rdc, 1057*678453a8Sspeer p_dma_cfgp->rcr_timeout[rdc], 1058*678453a8Sspeer p_dma_cfgp->rcr_threshold[rdc], 1059*678453a8Sspeer rbr_rings[rdc], 1060*678453a8Sspeer rbr_rings[rdc]->num_blocks, rcr_rings[rdc]); 1061a3c5bd6dSspeer ((mblk_t *)np)->b_wptr += print_len; 1062a3c5bd6dSspeer buf_len -= print_len; 1063*678453a8Sspeer } 106444961713Sgirish } 1065a3c5bd6dSspeer 106644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rxdma_info")); 106744961713Sgirish return (0); 106844961713Sgirish } 106944961713Sgirish 107044961713Sgirish /* ARGSUSED */ 107144961713Sgirish int 107244961713Sgirish nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep, queue_t *q, 1073a3c5bd6dSspeer p_mblk_t mp, caddr_t cp) 107444961713Sgirish { 1075a3c5bd6dSspeer uint_t print_len, buf_len; 1076a3c5bd6dSspeer p_mblk_t np; 1077a3c5bd6dSspeer int offset, rdc, i, rdc_grp; 107844961713Sgirish p_nxge_rdc_grp_t rdc_grp_p; 107944961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 108044961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 108144961713Sgirish 108244961713Sgirish int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 108344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1084a3c5bd6dSspeer "==> nxge_param_get_rxdma_rdcgrp_info")); 108544961713Sgirish 108644961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 108744961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 108844961713Sgirish 1089a3c5bd6dSspeer (void) mi_mpprintf(mp, "RXDMA RDC Group Information for Port\t %d \n", 1090a3c5bd6dSspeer nxgep->function_num); 109144961713Sgirish 1092*678453a8Sspeer rdc_grp = p_cfgp->def_mac_rxdma_grpid; 109344961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 109444961713Sgirish /* The following may work even if we cannot get a large buf. */ 109544961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 109644961713Sgirish return (0); 109744961713Sgirish } 109844961713Sgirish 109944961713Sgirish buf_len = buff_alloc_size; 110044961713Sgirish mp->b_cont = np; 110144961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1102a3c5bd6dSspeer "Total RDC Groups\t %d \n" 1103*678453a8Sspeer "default RDC group\t %d\n", 1104a3c5bd6dSspeer p_cfgp->max_rdc_grpids, 1105*678453a8Sspeer p_cfgp->def_mac_rxdma_grpid); 110644961713Sgirish 110744961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 110844961713Sgirish buf_len -= print_len; 110944961713Sgirish 1110*678453a8Sspeer for (i = 0; i < NXGE_MAX_RDCS; i++) { 1111*678453a8Sspeer if (p_cfgp->grpids[i]) { 1112*678453a8Sspeer rdc_grp_p = &p_dma_cfgp->rdc_grps[i]; 111344961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1114*678453a8Sspeer buf_len, 1115*678453a8Sspeer "\nRDC Group Info for Group [%d] %d\n" 1116*678453a8Sspeer "RDC Count %d\tstart RDC %d\n" 1117*678453a8Sspeer "RDC Group Population Information" 1118*678453a8Sspeer " (offsets 0 - 15)\n", 1119*678453a8Sspeer i, rdc_grp, rdc_grp_p->max_rdcs, 1120*678453a8Sspeer rdc_grp_p->start_rdc); 1121*678453a8Sspeer 1122*678453a8Sspeer ((mblk_t *)np)->b_wptr += print_len; 1123*678453a8Sspeer buf_len -= print_len; 1124*678453a8Sspeer print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1125*678453a8Sspeer buf_len, "\n"); 1126*678453a8Sspeer ((mblk_t *)np)->b_wptr += print_len; 1127*678453a8Sspeer buf_len -= print_len; 1128*678453a8Sspeer 1129*678453a8Sspeer for (rdc = 0; rdc < rdc_grp_p->max_rdcs; rdc++) { 1130*678453a8Sspeer print_len = snprintf( 1131*678453a8Sspeer (char *)((mblk_t *)np)->b_wptr, 1132*678453a8Sspeer buf_len, "[%d]=%d ", rdc, 1133*678453a8Sspeer rdc_grp_p->start_rdc + rdc); 1134*678453a8Sspeer ((mblk_t *)np)->b_wptr += print_len; 1135*678453a8Sspeer buf_len -= print_len; 1136*678453a8Sspeer } 1137*678453a8Sspeer print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1138*678453a8Sspeer buf_len, "\n"); 113944961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 114044961713Sgirish buf_len -= print_len; 114144961713Sgirish 1142*678453a8Sspeer for (offset = 0; offset < 16; offset++) { 1143*678453a8Sspeer print_len = snprintf( 1144*678453a8Sspeer (char *)((mblk_t *)np)->b_wptr, 1145*678453a8Sspeer buf_len, " %c", 1146*678453a8Sspeer rdc_grp_p->map & (1 << offset) ? 1147*678453a8Sspeer '1' : '0'); 1148*678453a8Sspeer ((mblk_t *)np)->b_wptr += print_len; 1149*678453a8Sspeer buf_len -= print_len; 1150*678453a8Sspeer } 115144961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1152*678453a8Sspeer buf_len, "\n"); 115344961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 115444961713Sgirish buf_len -= print_len; 115544961713Sgirish } 115644961713Sgirish } 115744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1158a3c5bd6dSspeer "<== nxge_param_get_rxdma_rdcgrp_info")); 115944961713Sgirish return (0); 116044961713Sgirish } 116144961713Sgirish 116244961713Sgirish int 116344961713Sgirish nxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size) 116444961713Sgirish { 116544961713Sgirish p_mblk_t tmp; 116644961713Sgirish 116744961713Sgirish tmp = mp; 116844961713Sgirish while (tmp->b_cont) 116944961713Sgirish tmp = tmp->b_cont; 117044961713Sgirish if ((tmp->b_wptr + size) >= tmp->b_datap->db_lim) { 117144961713Sgirish tmp->b_cont = allocb(1024, BPRI_HI); 117244961713Sgirish tmp = tmp->b_cont; 117344961713Sgirish if (!tmp) 117444961713Sgirish return (ENOMEM); 117544961713Sgirish } 1176a3c5bd6dSspeer 117744961713Sgirish *nmp = tmp; 117844961713Sgirish return (0); 117944961713Sgirish } 118044961713Sgirish 118144961713Sgirish /* 118244961713Sgirish * Sets the ge parameter to the value in the nxge_param_register using 118344961713Sgirish * nxge_nd_load(). 118444961713Sgirish */ 1185a3c5bd6dSspeer 118644961713Sgirish /* ARGSUSED */ 118744961713Sgirish int 118844961713Sgirish nxge_param_set_generic(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 118944961713Sgirish char *value, caddr_t cp) 119044961713Sgirish { 119144961713Sgirish char *end; 119244961713Sgirish uint32_t new_value; 119344961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 119444961713Sgirish 119544961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, " ==> nxge_param_set_generic")); 119644961713Sgirish new_value = (uint32_t)mi_strtol(value, &end, 10); 119744961713Sgirish if (end == value || new_value < pa->minimum || 119844961713Sgirish new_value > pa->maximum) { 119944961713Sgirish return (EINVAL); 120044961713Sgirish } 120144961713Sgirish pa->value = new_value; 120244961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, " <== nxge_param_set_generic")); 120344961713Sgirish return (0); 120444961713Sgirish } 120544961713Sgirish 120644961713Sgirish /* 120744961713Sgirish * Sets the ge parameter to the value in the nxge_param_register using 120844961713Sgirish * nxge_nd_load(). 120944961713Sgirish */ 121044961713Sgirish 1211a3c5bd6dSspeer /* ARGSUSED */ 121244961713Sgirish int 1213a3c5bd6dSspeer nxge_param_set_instance(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1214a3c5bd6dSspeer char *value, caddr_t cp) 121544961713Sgirish { 121644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " ==> nxge_param_set_instance")); 121744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_set_instance")); 121844961713Sgirish return (0); 121944961713Sgirish } 122044961713Sgirish 122144961713Sgirish /* 122244961713Sgirish * Sets the ge parameter to the value in the nxge_param_register using 122344961713Sgirish * nxge_nd_load(). 122444961713Sgirish */ 122544961713Sgirish 1226a3c5bd6dSspeer /* ARGSUSED */ 122744961713Sgirish int 1228a3c5bd6dSspeer nxge_param_set_mac(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1229a3c5bd6dSspeer char *value, caddr_t cp) 123044961713Sgirish { 1231a3c5bd6dSspeer char *end; 1232a3c5bd6dSspeer uint32_t new_value; 1233a3c5bd6dSspeer int status = 0; 1234a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 123544961713Sgirish 123644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac")); 123744961713Sgirish new_value = (uint32_t)mi_strtol(value, &end, BASE_DECIMAL); 123844961713Sgirish if (PARAM_OUTOF_RANGE(value, end, new_value, pa)) { 123944961713Sgirish return (EINVAL); 124044961713Sgirish } 124144961713Sgirish 124244961713Sgirish if (pa->value != new_value) { 124344961713Sgirish pa->old_value = pa->value; 124444961713Sgirish pa->value = new_value; 124544961713Sgirish } 124644961713Sgirish 124744961713Sgirish if (!nxge_param_link_update(nxgep)) { 124844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 124944961713Sgirish " false ret from nxge_param_link_update")); 125044961713Sgirish status = EINVAL; 125144961713Sgirish } 125244961713Sgirish 125344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac")); 125444961713Sgirish return (status); 125544961713Sgirish } 125644961713Sgirish 125744961713Sgirish /* ARGSUSED */ 12581bd6825cSml int 1259a3c5bd6dSspeer nxge_param_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1260a3c5bd6dSspeer char *value, caddr_t cp) 126144961713Sgirish { 1262a3c5bd6dSspeer char *end; 1263a3c5bd6dSspeer uint32_t cfg_value; 1264a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 126514ea4bb7Ssd 126644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_pkts")); 126744961713Sgirish 126814ea4bb7Ssd cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 126944961713Sgirish 127014ea4bb7Ssd if ((cfg_value > NXGE_RDC_RCR_THRESHOLD_MAX) || 127114ea4bb7Ssd (cfg_value < NXGE_RDC_RCR_THRESHOLD_MIN)) { 127244961713Sgirish return (EINVAL); 127344961713Sgirish } 127414ea4bb7Ssd 127514ea4bb7Ssd if ((pa->value != cfg_value)) { 127614ea4bb7Ssd pa->old_value = pa->value; 127714ea4bb7Ssd pa->value = cfg_value; 127814ea4bb7Ssd nxgep->intr_threshold = pa->value; 127944961713Sgirish } 128014ea4bb7Ssd 128144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_pkts")); 128244961713Sgirish return (0); 128344961713Sgirish } 128444961713Sgirish 128544961713Sgirish /* ARGSUSED */ 12861bd6825cSml int 1287a3c5bd6dSspeer nxge_param_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1288a3c5bd6dSspeer char *value, caddr_t cp) 128944961713Sgirish { 1290a3c5bd6dSspeer char *end; 1291a3c5bd6dSspeer uint32_t cfg_value; 1292a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 129344961713Sgirish 129444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_time")); 129544961713Sgirish 129614ea4bb7Ssd cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 129744961713Sgirish 129814ea4bb7Ssd if ((cfg_value > NXGE_RDC_RCR_TIMEOUT_MAX) || 129914ea4bb7Ssd (cfg_value < NXGE_RDC_RCR_TIMEOUT_MIN)) { 130044961713Sgirish return (EINVAL); 130144961713Sgirish } 130244961713Sgirish 130314ea4bb7Ssd if ((pa->value != cfg_value)) { 130414ea4bb7Ssd pa->old_value = pa->value; 130514ea4bb7Ssd pa->value = cfg_value; 130614ea4bb7Ssd nxgep->intr_timeout = pa->value; 130744961713Sgirish } 130844961713Sgirish 130944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_time")); 131044961713Sgirish return (0); 131144961713Sgirish } 131244961713Sgirish 131344961713Sgirish /* ARGSUSED */ 131444961713Sgirish static int 131544961713Sgirish nxge_param_set_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1316a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 131744961713Sgirish { 1318a3c5bd6dSspeer char *end; 1319a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1320a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1321a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 132244961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 132344961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1324a3c5bd6dSspeer uint32_t *val_ptr, *old_val_ptr; 1325a3c5bd6dSspeer nxge_param_map_t *mac_map; 1326a3c5bd6dSspeer p_nxge_class_pt_cfg_t p_class_cfgp; 1327a3c5bd6dSspeer nxge_mv_cfg_t *mac_host_info; 132844961713Sgirish 132944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac_rdcgrp ")); 133044961713Sgirish 133144961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 133244961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 133344961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 133444961713Sgirish mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 133544961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1336a3c5bd6dSspeer 1337a3c5bd6dSspeer /* 1338a3c5bd6dSspeer * now do decoding 1339a3c5bd6dSspeer */ 134044961713Sgirish mac_map = (nxge_param_map_t *)&cfg_value; 1341a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, " cfg_value %x id %x map_to %x", 1342a3c5bd6dSspeer cfg_value, mac_map->param_id, mac_map->map_to)); 134344961713Sgirish 134444961713Sgirish if ((mac_map->param_id < p_cfgp->max_macs) && 1345*678453a8Sspeer p_cfgp->grpids[mac_map->map_to]) { 134644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1347*678453a8Sspeer " nxge_param_set_mac_rdcgrp mapping" 1348*678453a8Sspeer " id %d grp %d", mac_map->param_id, mac_map->map_to)); 1349adfcba55Sjoycey #if defined(__i386) 1350adfcba55Sjoycey val_ptr = (uint32_t *)(uint32_t)pa->value; 1351adfcba55Sjoycey #else 135244961713Sgirish val_ptr = (uint32_t *)pa->value; 1353adfcba55Sjoycey #endif 1354adfcba55Sjoycey #if defined(__i386) 1355adfcba55Sjoycey old_val_ptr = (uint32_t *)(uint32_t)pa->old_value; 1356adfcba55Sjoycey #else 135744961713Sgirish old_val_ptr = (uint32_t *)pa->old_value; 1358adfcba55Sjoycey #endif 135944961713Sgirish if (val_ptr[mac_map->param_id] != cfg_value) { 136044961713Sgirish old_val_ptr[mac_map->param_id] = 1361*678453a8Sspeer val_ptr[mac_map->param_id]; 136244961713Sgirish val_ptr[mac_map->param_id] = cfg_value; 136344961713Sgirish mac_host_info[mac_map->param_id].mpr_npr = 1364*678453a8Sspeer mac_map->pref; 136544961713Sgirish mac_host_info[mac_map->param_id].flag = 1; 136644961713Sgirish mac_host_info[mac_map->param_id].rdctbl = 1367*678453a8Sspeer mac_map->map_to; 136844961713Sgirish cfg_it = B_TRUE; 136944961713Sgirish } 137044961713Sgirish } else { 137144961713Sgirish return (EINVAL); 137244961713Sgirish } 137344961713Sgirish 137444961713Sgirish if (cfg_it == B_TRUE) { 137544961713Sgirish status = nxge_logical_mac_assign_rdc_table(nxgep, 1376*678453a8Sspeer (uint8_t)mac_map->param_id); 137744961713Sgirish if (status != NXGE_OK) 137844961713Sgirish return (EINVAL); 137944961713Sgirish } 138044961713Sgirish 138144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac_rdcgrp")); 138244961713Sgirish return (0); 138344961713Sgirish } 138444961713Sgirish 138544961713Sgirish /* ARGSUSED */ 138644961713Sgirish static int 138744961713Sgirish nxge_param_set_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1388a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 138944961713Sgirish { 1390a3c5bd6dSspeer char *end; 1391a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1392a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1393a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 139444961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 139544961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1396a3c5bd6dSspeer uint32_t *val_ptr, *old_val_ptr; 1397a3c5bd6dSspeer nxge_param_map_t *vmap, *old_map; 1398a3c5bd6dSspeer p_nxge_class_pt_cfg_t p_class_cfgp; 1399a3c5bd6dSspeer uint64_t cfgd_vlans; 1400a3c5bd6dSspeer int i, inc = 0, cfg_position; 1401a3c5bd6dSspeer nxge_mv_cfg_t *vlan_tbl; 140244961713Sgirish 140344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 140444961713Sgirish 140544961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 140644961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 140744961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 140844961713Sgirish vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 140944961713Sgirish 141044961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1411a3c5bd6dSspeer 1412a3c5bd6dSspeer /* now do decoding */ 141344961713Sgirish cfgd_vlans = ((pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1414a3c5bd6dSspeer NXGE_PARAM_ARRAY_CNT_SHIFT); 141544961713Sgirish 141644961713Sgirish if (cfgd_vlans == NXGE_PARAM_ARRAY_INIT_SIZE) { 141744961713Sgirish /* 141844961713Sgirish * for now, we process only upto max 141944961713Sgirish * NXGE_PARAM_ARRAY_INIT_SIZE parameters 142044961713Sgirish * In the future, we may want to expand 142144961713Sgirish * the storage array and continue 142244961713Sgirish */ 142344961713Sgirish return (EINVAL); 142444961713Sgirish } 1425a3c5bd6dSspeer 142644961713Sgirish vmap = (nxge_param_map_t *)&cfg_value; 142744961713Sgirish if ((vmap->param_id) && 142844961713Sgirish (vmap->param_id < NXGE_MAX_VLANS) && 142944961713Sgirish (vmap->map_to < p_cfgp->max_rdc_grpids)) { 143044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1431a3c5bd6dSspeer "nxge_param_set_vlan_rdcgrp mapping" 1432a3c5bd6dSspeer " id %d grp %d", 1433a3c5bd6dSspeer vmap->param_id, vmap->map_to)); 1434adfcba55Sjoycey #if defined(__i386) 1435adfcba55Sjoycey val_ptr = (uint32_t *)(uint32_t)pa->value; 1436adfcba55Sjoycey #else 143744961713Sgirish val_ptr = (uint32_t *)pa->value; 1438adfcba55Sjoycey #endif 1439adfcba55Sjoycey #if defined(__i386) 1440adfcba55Sjoycey old_val_ptr = (uint32_t *)(uint32_t)pa->old_value; 1441adfcba55Sjoycey #else 144244961713Sgirish old_val_ptr = (uint32_t *)pa->old_value; 1443adfcba55Sjoycey #endif 144444961713Sgirish 144544961713Sgirish /* search to see if this vlan id is already configured */ 144644961713Sgirish for (i = 0; i < cfgd_vlans; i++) { 144744961713Sgirish old_map = (nxge_param_map_t *)&val_ptr[i]; 144844961713Sgirish if ((old_map->param_id == 0) || 144944961713Sgirish (vmap->param_id == old_map->param_id) || 145044961713Sgirish (vlan_tbl[vmap->param_id].flag)) { 145144961713Sgirish cfg_position = i; 145244961713Sgirish break; 145344961713Sgirish } 145444961713Sgirish } 145544961713Sgirish 145644961713Sgirish if (cfgd_vlans == 0) { 145744961713Sgirish cfg_position = 0; 145844961713Sgirish inc++; 145944961713Sgirish } 146044961713Sgirish 146144961713Sgirish if (i == cfgd_vlans) { 146244961713Sgirish cfg_position = i; 146344961713Sgirish inc++; 146444961713Sgirish } 146544961713Sgirish 146644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1467a3c5bd6dSspeer "set_vlan_rdcgrp mapping" 1468a3c5bd6dSspeer " i %d cfgd_vlans %llx position %d ", 1469a3c5bd6dSspeer i, cfgd_vlans, cfg_position)); 147044961713Sgirish if (val_ptr[cfg_position] != cfg_value) { 147144961713Sgirish old_val_ptr[cfg_position] = val_ptr[cfg_position]; 147244961713Sgirish val_ptr[cfg_position] = cfg_value; 147344961713Sgirish vlan_tbl[vmap->param_id].mpr_npr = vmap->pref; 147444961713Sgirish vlan_tbl[vmap->param_id].flag = 1; 147544961713Sgirish vlan_tbl[vmap->param_id].rdctbl = 1476*678453a8Sspeer vmap->map_to + p_cfgp->def_mac_rxdma_grpid; 147744961713Sgirish cfg_it = B_TRUE; 147844961713Sgirish if (inc) { 147944961713Sgirish cfgd_vlans++; 148044961713Sgirish pa->type &= ~NXGE_PARAM_ARRAY_CNT_MASK; 148144961713Sgirish pa->type |= (cfgd_vlans << 148244961713Sgirish NXGE_PARAM_ARRAY_CNT_SHIFT); 148344961713Sgirish 148444961713Sgirish } 148544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1486a3c5bd6dSspeer "after: param_set_vlan_rdcgrp " 1487a3c5bd6dSspeer " cfg_vlans %llx position %d \n", 1488a3c5bd6dSspeer cfgd_vlans, cfg_position)); 148944961713Sgirish } 149044961713Sgirish } else { 149144961713Sgirish return (EINVAL); 149244961713Sgirish } 149344961713Sgirish 149444961713Sgirish if (cfg_it == B_TRUE) { 149544961713Sgirish status = nxge_fflp_config_vlan_table(nxgep, 1496a3c5bd6dSspeer (uint16_t)vmap->param_id); 149744961713Sgirish if (status != NXGE_OK) 149844961713Sgirish return (EINVAL); 149944961713Sgirish } 150044961713Sgirish 150144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_vlan_rdcgrp")); 150244961713Sgirish return (0); 150344961713Sgirish } 150444961713Sgirish 150544961713Sgirish /* ARGSUSED */ 150644961713Sgirish static int 150744961713Sgirish nxge_param_get_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1508a3c5bd6dSspeer mblk_t *mp, caddr_t cp) 150944961713Sgirish { 151044961713Sgirish 1511a3c5bd6dSspeer uint_t print_len, buf_len; 1512a3c5bd6dSspeer p_mblk_t np; 1513a3c5bd6dSspeer int i; 1514a3c5bd6dSspeer uint32_t *val_ptr; 1515a3c5bd6dSspeer nxge_param_map_t *vmap; 1516a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 151744961713Sgirish p_nxge_class_pt_cfg_t p_class_cfgp; 151844961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 151944961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1520a3c5bd6dSspeer uint64_t cfgd_vlans = 0; 1521a3c5bd6dSspeer nxge_mv_cfg_t *vlan_tbl; 1522a3c5bd6dSspeer int buff_alloc_size = 1523a3c5bd6dSspeer NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 152444961713Sgirish 152544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1526a3c5bd6dSspeer (void) mi_mpprintf(mp, "VLAN RDC Mapping Information for Port\t %d \n", 1527a3c5bd6dSspeer nxgep->function_num); 152844961713Sgirish 152944961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 153044961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 153144961713Sgirish return (0); 153244961713Sgirish } 1533a3c5bd6dSspeer 153444961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 153544961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 153644961713Sgirish 153744961713Sgirish buf_len = buff_alloc_size; 153844961713Sgirish mp->b_cont = np; 153944961713Sgirish cfgd_vlans = (pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 154044961713Sgirish NXGE_PARAM_ARRAY_CNT_SHIFT; 154144961713Sgirish 154244961713Sgirish i = (int)cfgd_vlans; 154344961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 154444961713Sgirish vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 154544961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1546a3c5bd6dSspeer "Configured VLANs %d\n" 1547a3c5bd6dSspeer "VLAN ID\t RDC GRP (Actual/Port)\t" 1548a3c5bd6dSspeer " Prefernce\n", i); 154944961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 155044961713Sgirish buf_len -= print_len; 1551adfcba55Sjoycey #if defined(__i386) 1552adfcba55Sjoycey val_ptr = (uint32_t *)(uint32_t)pa->value; 1553adfcba55Sjoycey #else 155444961713Sgirish val_ptr = (uint32_t *)pa->value; 1555adfcba55Sjoycey #endif 155644961713Sgirish 155744961713Sgirish for (i = 0; i < cfgd_vlans; i++) { 155844961713Sgirish vmap = (nxge_param_map_t *)&val_ptr[i]; 155944961713Sgirish if (p_class_cfgp->vlan_tbl[vmap->param_id].flag) { 156044961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1561a3c5bd6dSspeer buf_len, 1562a3c5bd6dSspeer " %d\t\t %d/%d\t\t %d\n", 1563a3c5bd6dSspeer vmap->param_id, 1564a3c5bd6dSspeer vlan_tbl[vmap->param_id].rdctbl, 1565a3c5bd6dSspeer vlan_tbl[vmap->param_id].rdctbl - 1566*678453a8Sspeer p_cfgp->def_mac_rxdma_grpid, 1567a3c5bd6dSspeer vlan_tbl[vmap->param_id].mpr_npr); 156844961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 156944961713Sgirish buf_len -= print_len; 157044961713Sgirish } 157144961713Sgirish } 157244961713Sgirish 157344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_vlan_rdcgrp")); 157444961713Sgirish return (0); 157544961713Sgirish } 157644961713Sgirish 157744961713Sgirish /* ARGSUSED */ 157844961713Sgirish static int 157944961713Sgirish nxge_param_get_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1580a3c5bd6dSspeer mblk_t *mp, caddr_t cp) 158144961713Sgirish { 1582a3c5bd6dSspeer uint_t print_len, buf_len; 1583a3c5bd6dSspeer p_mblk_t np; 1584a3c5bd6dSspeer int i; 158544961713Sgirish p_nxge_class_pt_cfg_t p_class_cfgp; 158644961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 158744961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1588a3c5bd6dSspeer nxge_mv_cfg_t *mac_host_info; 158944961713Sgirish 159044961713Sgirish int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 159144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac_rdcgrp ")); 159244961713Sgirish (void) mi_mpprintf(mp, 1593a3c5bd6dSspeer "MAC ADDR RDC Mapping Information for Port\t %d\n", 1594a3c5bd6dSspeer nxgep->function_num); 159544961713Sgirish 159644961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 159744961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 159844961713Sgirish return (0); 159944961713Sgirish } 160044961713Sgirish 160144961713Sgirish buf_len = buff_alloc_size; 160244961713Sgirish mp->b_cont = np; 160344961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 160444961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 160544961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 160644961713Sgirish mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 160744961713Sgirish print_len = snprintf((char *)np->b_wptr, buf_len, 1608a3c5bd6dSspeer "MAC ID\t RDC GRP (Actual/Port)\t" 1609a3c5bd6dSspeer " Prefernce\n"); 161044961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 161144961713Sgirish buf_len -= print_len; 161244961713Sgirish for (i = 0; i < p_cfgp->max_macs; i++) { 161344961713Sgirish if (mac_host_info[i].flag) { 161444961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1615a3c5bd6dSspeer buf_len, 1616a3c5bd6dSspeer " %d\t %d/%d\t\t %d\n", 1617a3c5bd6dSspeer i, mac_host_info[i].rdctbl, 1618a3c5bd6dSspeer mac_host_info[i].rdctbl - 1619*678453a8Sspeer p_cfgp->def_mac_rxdma_grpid, 1620a3c5bd6dSspeer mac_host_info[i].mpr_npr); 162144961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 162244961713Sgirish buf_len -= print_len; 162344961713Sgirish } 162444961713Sgirish } 162544961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1626a3c5bd6dSspeer "Done Info Dumping \n"); 162744961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 162844961713Sgirish buf_len -= print_len; 162944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_macrdcgrp")); 163044961713Sgirish return (0); 163144961713Sgirish } 163244961713Sgirish 163344961713Sgirish /* ARGSUSED */ 163444961713Sgirish static int 163544961713Sgirish nxge_param_tcam_enable(p_nxge_t nxgep, queue_t *q, 1636a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 163744961713Sgirish { 1638a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1639a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1640a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 1641a3c5bd6dSspeer char *end; 164244961713Sgirish 164344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_tcam_enable")); 164444961713Sgirish 164544961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 164644961713Sgirish if (pa->value != cfg_value) { 164744961713Sgirish pa->old_value = pa->value; 164844961713Sgirish pa->value = cfg_value; 164944961713Sgirish cfg_it = B_TRUE; 165044961713Sgirish } 165144961713Sgirish 165244961713Sgirish if (cfg_it == B_TRUE) { 165344961713Sgirish if (pa->value) 165444961713Sgirish status = nxge_fflp_config_tcam_enable(nxgep); 165544961713Sgirish else 165644961713Sgirish status = nxge_fflp_config_tcam_disable(nxgep); 165744961713Sgirish if (status != NXGE_OK) 165844961713Sgirish return (EINVAL); 165944961713Sgirish } 166044961713Sgirish 166144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_tcam_enable")); 166244961713Sgirish return (0); 166344961713Sgirish } 166444961713Sgirish 166544961713Sgirish /* ARGSUSED */ 166644961713Sgirish static int 166744961713Sgirish nxge_param_hash_lookup_enable(p_nxge_t nxgep, queue_t *q, 1668a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 166944961713Sgirish { 1670a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1671a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1672a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 1673a3c5bd6dSspeer char *end; 167444961713Sgirish 167544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_hash_lookup_enable")); 167644961713Sgirish 167744961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 167844961713Sgirish if (pa->value != cfg_value) { 167944961713Sgirish pa->old_value = pa->value; 168044961713Sgirish pa->value = cfg_value; 168144961713Sgirish cfg_it = B_TRUE; 168244961713Sgirish } 168344961713Sgirish 168444961713Sgirish if (cfg_it == B_TRUE) { 168544961713Sgirish if (pa->value) 168644961713Sgirish status = nxge_fflp_config_hash_lookup_enable(nxgep); 168744961713Sgirish else 168844961713Sgirish status = nxge_fflp_config_hash_lookup_disable(nxgep); 168944961713Sgirish if (status != NXGE_OK) 169044961713Sgirish return (EINVAL); 169144961713Sgirish } 169244961713Sgirish 169344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_hash_lookup_enable")); 169444961713Sgirish return (0); 169544961713Sgirish } 169644961713Sgirish 169744961713Sgirish /* ARGSUSED */ 169844961713Sgirish static int 169944961713Sgirish nxge_param_llc_snap_enable(p_nxge_t nxgep, queue_t *q, 1700a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 170144961713Sgirish { 1702a3c5bd6dSspeer char *end; 1703a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1704a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1705a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 170644961713Sgirish 170744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_llc_snap_enable")); 170844961713Sgirish 170944961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 171044961713Sgirish if (pa->value != cfg_value) { 171144961713Sgirish pa->old_value = pa->value; 171244961713Sgirish pa->value = cfg_value; 171344961713Sgirish cfg_it = B_TRUE; 171444961713Sgirish } 171544961713Sgirish 171644961713Sgirish if (cfg_it == B_TRUE) { 171744961713Sgirish if (pa->value) 171844961713Sgirish status = nxge_fflp_config_tcam_enable(nxgep); 171944961713Sgirish else 172044961713Sgirish status = nxge_fflp_config_tcam_disable(nxgep); 172144961713Sgirish if (status != NXGE_OK) 172244961713Sgirish return (EINVAL); 172344961713Sgirish } 172444961713Sgirish 172544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_llc_snap_enable")); 172644961713Sgirish return (0); 172744961713Sgirish } 172844961713Sgirish 172944961713Sgirish /* ARGSUSED */ 173044961713Sgirish static int 173144961713Sgirish nxge_param_set_ether_usr(p_nxge_t nxgep, queue_t *q, 1732a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 173344961713Sgirish { 1734a3c5bd6dSspeer char *end; 1735a3c5bd6dSspeer uint8_t ether_class; 1736a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1737a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1738a3c5bd6dSspeer uint8_t cfg_it = B_FALSE; 173944961713Sgirish 174044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ether_usr")); 174144961713Sgirish 174244961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 174344961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 174444961713Sgirish return (EINVAL); 174544961713Sgirish } 1746a3c5bd6dSspeer 174744961713Sgirish if (pa->value != cfg_value) { 174844961713Sgirish pa->old_value = pa->value; 174944961713Sgirish pa->value = cfg_value; 175044961713Sgirish cfg_it = B_TRUE; 175144961713Sgirish } 175244961713Sgirish 175344961713Sgirish /* do the actual hw setup */ 175444961713Sgirish if (cfg_it == B_TRUE) { 175544961713Sgirish ether_class = mi_strtol(pa->name, &end, 10); 175644961713Sgirish #ifdef lint 175744961713Sgirish ether_class = ether_class; 175844961713Sgirish #endif 175944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_ether_usr")); 176044961713Sgirish } 1761a3c5bd6dSspeer 176244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ether_usr")); 176344961713Sgirish return (status); 176444961713Sgirish } 176544961713Sgirish 176644961713Sgirish /* ARGSUSED */ 176744961713Sgirish static int 176844961713Sgirish nxge_param_set_ip_usr(p_nxge_t nxgep, queue_t *q, 1769a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 177044961713Sgirish { 1771a3c5bd6dSspeer char *end; 1772a3c5bd6dSspeer tcam_class_t class; 1773a3c5bd6dSspeer uint32_t status, cfg_value; 1774a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1775a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 177644961713Sgirish 177744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_usr")); 177844961713Sgirish 177944961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 178044961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 178144961713Sgirish return (EINVAL); 178244961713Sgirish } 178344961713Sgirish 178444961713Sgirish if (pa->value != cfg_value) { 178544961713Sgirish pa->old_value = pa->value; 178644961713Sgirish pa->value = cfg_value; 178744961713Sgirish cfg_it = B_TRUE; 178844961713Sgirish } 178944961713Sgirish 179044961713Sgirish /* do the actual hw setup with cfg_value. */ 179144961713Sgirish if (cfg_it == B_TRUE) { 179244961713Sgirish class = mi_strtol(pa->name, &end, 10); 179344961713Sgirish status = nxge_fflp_ip_usr_class_config(nxgep, class, pa->value); 179444961713Sgirish } 179544961713Sgirish 179644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_usr")); 179744961713Sgirish return (status); 179844961713Sgirish } 179944961713Sgirish 1800a3c5bd6dSspeer /* ARGSUSED */ 180144961713Sgirish static int 180244961713Sgirish nxge_class_name_2value(p_nxge_t nxgep, char *name) 180344961713Sgirish { 1804a3c5bd6dSspeer int i; 1805a3c5bd6dSspeer int class_instance = param_class_opt_ip_usr4; 1806a3c5bd6dSspeer p_nxge_param_t param_arr; 1807a3c5bd6dSspeer 180844961713Sgirish param_arr = nxgep->param_arr; 180944961713Sgirish for (i = TCAM_CLASS_IP_USER_4; i <= TCAM_CLASS_SCTP_IPV6; i++) { 181044961713Sgirish if (strcmp(param_arr[class_instance].name, name) == 0) 181144961713Sgirish return (i); 181244961713Sgirish class_instance++; 181344961713Sgirish } 181444961713Sgirish return (-1); 181544961713Sgirish } 181644961713Sgirish 181744961713Sgirish /* ARGSUSED */ 18181bd6825cSml int 181944961713Sgirish nxge_param_set_ip_opt(p_nxge_t nxgep, queue_t *q, 1820a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 182144961713Sgirish { 1822a3c5bd6dSspeer char *end; 1823a3c5bd6dSspeer uint32_t status, cfg_value; 1824a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1825a3c5bd6dSspeer tcam_class_t class; 1826a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 182744961713Sgirish 182844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_opt")); 182944961713Sgirish 183044961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 183144961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 183244961713Sgirish return (EINVAL); 183344961713Sgirish } 183444961713Sgirish 183544961713Sgirish if (pa->value != cfg_value) { 183644961713Sgirish pa->old_value = pa->value; 183744961713Sgirish pa->value = cfg_value; 183844961713Sgirish cfg_it = B_TRUE; 183944961713Sgirish } 184044961713Sgirish 184144961713Sgirish if (cfg_it == B_TRUE) { 1842a3c5bd6dSspeer /* do the actual hw setup */ 184344961713Sgirish class = nxge_class_name_2value(nxgep, pa->name); 184444961713Sgirish if (class == -1) 184544961713Sgirish return (EINVAL); 184644961713Sgirish 184744961713Sgirish status = nxge_fflp_ip_class_config(nxgep, class, pa->value); 184844961713Sgirish if (status != NXGE_OK) 184944961713Sgirish return (EINVAL); 185044961713Sgirish } 185144961713Sgirish 185244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_opt")); 185344961713Sgirish return (0); 185444961713Sgirish } 185544961713Sgirish 185644961713Sgirish /* ARGSUSED */ 185744961713Sgirish static int 185844961713Sgirish nxge_param_get_ip_opt(p_nxge_t nxgep, queue_t *q, 1859a3c5bd6dSspeer mblk_t *mp, caddr_t cp) 186044961713Sgirish { 186144961713Sgirish uint32_t status, cfg_value; 186244961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 186344961713Sgirish tcam_class_t class; 186444961713Sgirish 186544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_ip_opt")); 186644961713Sgirish 1867a3c5bd6dSspeer /* do the actual hw setup */ 186844961713Sgirish class = nxge_class_name_2value(nxgep, pa->name); 186944961713Sgirish if (class == -1) 187044961713Sgirish return (EINVAL); 1871a3c5bd6dSspeer 187244961713Sgirish cfg_value = 0; 187344961713Sgirish status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 187444961713Sgirish if (status != NXGE_OK) 187544961713Sgirish return (EINVAL); 1876a3c5bd6dSspeer 187744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1878a3c5bd6dSspeer "nxge_param_get_ip_opt_get %x ", cfg_value)); 187944961713Sgirish 1880a3c5bd6dSspeer pa->value = cfg_value; 188144961713Sgirish (void) mi_mpprintf(mp, "%x", cfg_value); 1882a3c5bd6dSspeer 188344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 188444961713Sgirish return (0); 188544961713Sgirish } 188644961713Sgirish 188744961713Sgirish /* ARGSUSED */ 188844961713Sgirish static int 188944961713Sgirish nxge_param_fflp_hash_init(p_nxge_t nxgep, queue_t *q, 1890a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 189144961713Sgirish { 1892a3c5bd6dSspeer char *end; 1893a3c5bd6dSspeer uint32_t status, cfg_value; 1894a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1895a3c5bd6dSspeer tcam_class_t class; 1896a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 189744961713Sgirish 189844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_fflp_hash_init")); 189944961713Sgirish 190044961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 190144961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 190244961713Sgirish return (EINVAL); 190344961713Sgirish } 190444961713Sgirish 190544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1906a3c5bd6dSspeer "nxge_param_fflp_hash_init value %x", cfg_value)); 1907a3c5bd6dSspeer 190844961713Sgirish if (pa->value != cfg_value) { 190944961713Sgirish pa->old_value = pa->value; 191044961713Sgirish pa->value = cfg_value; 191144961713Sgirish cfg_it = B_TRUE; 191244961713Sgirish } 191344961713Sgirish 191444961713Sgirish if (cfg_it == B_TRUE) { 191544961713Sgirish char *h_name; 1916a3c5bd6dSspeer 191744961713Sgirish /* do the actual hw setup */ 191844961713Sgirish h_name = pa->name; 191944961713Sgirish h_name++; 192044961713Sgirish class = mi_strtol(h_name, &end, 10); 192144961713Sgirish switch (class) { 192244961713Sgirish case 1: 192344961713Sgirish status = nxge_fflp_set_hash1(nxgep, 1924a3c5bd6dSspeer (uint32_t)pa->value); 192544961713Sgirish break; 192644961713Sgirish case 2: 192744961713Sgirish status = nxge_fflp_set_hash2(nxgep, 1928a3c5bd6dSspeer (uint16_t)pa->value); 192944961713Sgirish break; 193044961713Sgirish 193144961713Sgirish default: 193244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1933a3c5bd6dSspeer " nxge_param_fflp_hash_init" 1934a3c5bd6dSspeer " %s Wrong hash var %d", 1935a3c5bd6dSspeer pa->name, class)); 193644961713Sgirish return (EINVAL); 193744961713Sgirish } 193844961713Sgirish if (status != NXGE_OK) 193944961713Sgirish return (EINVAL); 194044961713Sgirish } 194144961713Sgirish 194244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_fflp_hash_init")); 194344961713Sgirish return (0); 194444961713Sgirish } 194544961713Sgirish 194644961713Sgirish /* ARGSUSED */ 194744961713Sgirish static int 194844961713Sgirish nxge_param_set_grp_rdc(p_nxge_t nxgep, queue_t *q, 1949a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 195044961713Sgirish { 1951a3c5bd6dSspeer char *end; 1952a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1953a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1954a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 1955a3c5bd6dSspeer int rdc_grp; 1956a3c5bd6dSspeer uint8_t real_rdc; 195744961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 195844961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 195944961713Sgirish p_nxge_rdc_grp_t rdc_grp_p; 196044961713Sgirish 196144961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 196244961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 196344961713Sgirish 196444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_grp_rdc")); 196544961713Sgirish 196644961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 196744961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 196844961713Sgirish return (EINVAL); 196944961713Sgirish } 1970a3c5bd6dSspeer 197144961713Sgirish if (cfg_value >= p_cfgp->max_rdcs) { 197244961713Sgirish return (EINVAL); 197344961713Sgirish } 1974a3c5bd6dSspeer 197544961713Sgirish if (pa->value != cfg_value) { 197644961713Sgirish pa->old_value = pa->value; 197744961713Sgirish pa->value = cfg_value; 197844961713Sgirish cfg_it = B_TRUE; 197944961713Sgirish } 198044961713Sgirish 198144961713Sgirish if (cfg_it == B_TRUE) { 198244961713Sgirish char *grp_name; 198344961713Sgirish grp_name = pa->name; 198444961713Sgirish grp_name += strlen("default-grp"); 198544961713Sgirish rdc_grp = mi_strtol(grp_name, &end, 10); 198644961713Sgirish rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp]; 198744961713Sgirish real_rdc = rdc_grp_p->start_rdc + cfg_value; 198844961713Sgirish if (nxge_check_rxdma_rdcgrp_member(nxgep, rdc_grp, 1989a3c5bd6dSspeer cfg_value) == B_FALSE) { 199044961713Sgirish pa->value = pa->old_value; 199144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1992a3c5bd6dSspeer " nxge_param_set_grp_rdc" 1993a3c5bd6dSspeer " %d read %d actual %d outof range", 1994a3c5bd6dSspeer rdc_grp, cfg_value, real_rdc)); 199544961713Sgirish return (EINVAL); 199644961713Sgirish } 199744961713Sgirish status = nxge_rxdma_cfg_rdcgrp_default_rdc(nxgep, rdc_grp, 199844961713Sgirish real_rdc); 199944961713Sgirish if (status != NXGE_OK) 200044961713Sgirish return (EINVAL); 200144961713Sgirish } 200244961713Sgirish 200344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_grp_rdc")); 200444961713Sgirish return (0); 200544961713Sgirish } 200644961713Sgirish 200744961713Sgirish /* ARGSUSED */ 200844961713Sgirish static int 200944961713Sgirish nxge_param_set_port_rdc(p_nxge_t nxgep, queue_t *q, 2010a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 201144961713Sgirish { 2012a3c5bd6dSspeer char *end; 2013a3c5bd6dSspeer uint32_t status = B_TRUE, cfg_value; 2014a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 2015a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 201644961713Sgirish 201744961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 201844961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 201944961713Sgirish 202044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_port_rdc")); 202144961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 202244961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 202344961713Sgirish 202444961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 202544961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 202644961713Sgirish return (EINVAL); 202744961713Sgirish } 2028a3c5bd6dSspeer 202944961713Sgirish if (pa->value != cfg_value) { 203044961713Sgirish if (cfg_value >= p_cfgp->max_rdcs) 203144961713Sgirish return (EINVAL); 203244961713Sgirish pa->old_value = pa->value; 203344961713Sgirish pa->value = cfg_value; 203444961713Sgirish cfg_it = B_TRUE; 203544961713Sgirish } 203644961713Sgirish 203744961713Sgirish if (cfg_it == B_TRUE) { 2038*678453a8Sspeer int rdc; 2039*678453a8Sspeer if ((rdc = nxge_dci_map(nxgep, VP_BOUND_RX, cfg_value)) < 0) 2040*678453a8Sspeer return (EINVAL); 204144961713Sgirish status = nxge_rxdma_cfg_port_default_rdc(nxgep, 2042*678453a8Sspeer nxgep->function_num, rdc); 204344961713Sgirish if (status != NXGE_OK) 204444961713Sgirish return (EINVAL); 204544961713Sgirish } 204644961713Sgirish 204744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_port_rdc")); 204844961713Sgirish return (0); 204944961713Sgirish } 205044961713Sgirish 205144961713Sgirish /* ARGSUSED */ 205244961713Sgirish static int 205344961713Sgirish nxge_param_set_nxge_debug_flag(p_nxge_t nxgep, queue_t *q, 2054a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 205544961713Sgirish { 205644961713Sgirish char *end; 205744961713Sgirish uint32_t status = 0; 205844961713Sgirish uint64_t cfg_value = 0; 205944961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 206044961713Sgirish uint32_t cfg_it = B_FALSE; 206144961713Sgirish 206244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_nxge_debug_flag")); 206344961713Sgirish cfg_value = mi_strtol(value, &end, BASE_HEX); 206444961713Sgirish 206544961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 206644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2067a3c5bd6dSspeer " nxge_param_set_nxge_debug_flag" 2068a3c5bd6dSspeer " outof range %llx", cfg_value)); 206944961713Sgirish return (EINVAL); 207044961713Sgirish } 207144961713Sgirish if (pa->value != cfg_value) { 207244961713Sgirish pa->old_value = pa->value; 207344961713Sgirish pa->value = cfg_value; 207444961713Sgirish cfg_it = B_TRUE; 207544961713Sgirish } 207644961713Sgirish 207744961713Sgirish if (cfg_it == B_TRUE) { 207844961713Sgirish nxgep->nxge_debug_level = pa->value; 207944961713Sgirish } 2080a3c5bd6dSspeer 208144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_nxge_debug_flag")); 208244961713Sgirish return (status); 208344961713Sgirish } 208444961713Sgirish 208544961713Sgirish /* ARGSUSED */ 208644961713Sgirish static int 208744961713Sgirish nxge_param_get_debug_flag(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 208844961713Sgirish { 2089a3c5bd6dSspeer int status = 0; 2090a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 209144961713Sgirish 209244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_debug_flag")); 209344961713Sgirish 209444961713Sgirish if (pa->value > 0xffffffff) 209544961713Sgirish (void) mi_mpprintf(mp, "%x%x", (int)(pa->value >> 32), 2096a3c5bd6dSspeer (int)(pa->value & 0xffffffff)); 209744961713Sgirish else 209844961713Sgirish (void) mi_mpprintf(mp, "%x", (int)pa->value); 209944961713Sgirish 210044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_debug_flag")); 210144961713Sgirish return (status); 210244961713Sgirish } 210344961713Sgirish 210444961713Sgirish /* ARGSUSED */ 210544961713Sgirish static int 210644961713Sgirish nxge_param_set_npi_debug_flag(p_nxge_t nxgep, queue_t *q, 2107a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 210844961713Sgirish { 2109a3c5bd6dSspeer char *end; 2110a3c5bd6dSspeer uint32_t status = 0; 2111a3c5bd6dSspeer uint64_t cfg_value = 0; 2112a3c5bd6dSspeer p_nxge_param_t pa; 2113a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 211444961713Sgirish 211544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_npi_debug_flag")); 211644961713Sgirish cfg_value = mi_strtol(value, &end, BASE_HEX); 211744961713Sgirish pa = (p_nxge_param_t)cp; 211844961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 211944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_npi_debug_flag" 212044961713Sgirish " outof range %llx", cfg_value)); 212144961713Sgirish return (EINVAL); 212244961713Sgirish } 212344961713Sgirish if (pa->value != cfg_value) { 212444961713Sgirish pa->old_value = pa->value; 212544961713Sgirish pa->value = cfg_value; 212644961713Sgirish cfg_it = B_TRUE; 212744961713Sgirish } 212844961713Sgirish 212944961713Sgirish if (cfg_it == B_TRUE) { 213044961713Sgirish npi_debug_level = pa->value; 213144961713Sgirish } 213244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_debug_flag")); 213344961713Sgirish return (status); 213444961713Sgirish } 213544961713Sgirish 213644961713Sgirish /* ARGSUSED */ 213744961713Sgirish static int 213844961713Sgirish nxge_param_dump_rdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 213944961713Sgirish { 2140*678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set; 2141*678453a8Sspeer int rdc; 214244961713Sgirish 214344961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_rdc")); 214444961713Sgirish 2145*678453a8Sspeer if (!isLDOMguest(nxgep)) 2146*678453a8Sspeer (void) npi_rxdma_dump_fzc_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2147*678453a8Sspeer 2148*678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_TDCS; rdc++) { 2149*678453a8Sspeer if ((1 << rdc) & set->owned.map) { 2150*678453a8Sspeer (void) nxge_dump_rxdma_channel(nxgep, rdc); 2151*678453a8Sspeer } 2152*678453a8Sspeer } 215344961713Sgirish 215444961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_rdc")); 215544961713Sgirish return (0); 215644961713Sgirish } 215744961713Sgirish 215844961713Sgirish /* ARGSUSED */ 215944961713Sgirish static int 216044961713Sgirish nxge_param_dump_tdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 216144961713Sgirish { 2162*678453a8Sspeer nxge_grp_set_t *set = &nxgep->tx_set; 2163*678453a8Sspeer int tdc; 216444961713Sgirish 216544961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_tdc")); 216644961713Sgirish 2167*678453a8Sspeer for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { 2168*678453a8Sspeer if ((1 << tdc) & set->owned.map) { 2169*678453a8Sspeer (void) nxge_txdma_regs_dump(nxgep, tdc); 2170*678453a8Sspeer } 2171*678453a8Sspeer } 217244961713Sgirish 217344961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_tdc")); 217444961713Sgirish return (0); 217544961713Sgirish } 217644961713Sgirish 217744961713Sgirish /* ARGSUSED */ 217844961713Sgirish static int 217944961713Sgirish nxge_param_dump_fflp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 218044961713Sgirish { 218144961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_fflp_regs")); 218244961713Sgirish 218344961713Sgirish (void) npi_fflp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 218444961713Sgirish 218544961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_fflp_regs")); 218644961713Sgirish return (0); 218744961713Sgirish } 218844961713Sgirish 218944961713Sgirish /* ARGSUSED */ 219044961713Sgirish static int 219144961713Sgirish nxge_param_dump_mac_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 219244961713Sgirish { 219344961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_mac_regs")); 219444961713Sgirish 219544961713Sgirish (void) npi_mac_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2196a3c5bd6dSspeer nxgep->function_num); 219744961713Sgirish 219844961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_mac_regs")); 219944961713Sgirish return (0); 220044961713Sgirish } 220144961713Sgirish 220244961713Sgirish /* ARGSUSED */ 220344961713Sgirish static int 220444961713Sgirish nxge_param_dump_ipp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 220544961713Sgirish { 220644961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_ipp_regs")); 220744961713Sgirish 2208a3c5bd6dSspeer (void) npi_ipp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2209a3c5bd6dSspeer nxgep->function_num); 221044961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ipp_regs")); 221144961713Sgirish return (0); 221244961713Sgirish } 221344961713Sgirish 221444961713Sgirish /* ARGSUSED */ 221544961713Sgirish static int 221644961713Sgirish nxge_param_dump_vlan_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 221744961713Sgirish { 221844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_vlan_table")); 221944961713Sgirish 222044961713Sgirish (void) npi_fflp_vlan_tbl_dump(NXGE_DEV_NPI_HANDLE(nxgep)); 222144961713Sgirish 222244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_vlan_table")); 222344961713Sgirish return (0); 222444961713Sgirish } 222544961713Sgirish 222644961713Sgirish /* ARGSUSED */ 222744961713Sgirish static int 222844961713Sgirish nxge_param_dump_rdc_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 222944961713Sgirish { 2230a3c5bd6dSspeer uint8_t table; 223144961713Sgirish 223244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_rdc_table")); 223344961713Sgirish for (table = 0; table < NXGE_MAX_RDC_GROUPS; table++) { 223444961713Sgirish (void) npi_rxdma_dump_rdc_table(NXGE_DEV_NPI_HANDLE(nxgep), 223544961713Sgirish table); 223644961713Sgirish } 2237a3c5bd6dSspeer 223844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_rdc_table")); 223944961713Sgirish return (0); 224044961713Sgirish } 224144961713Sgirish 224244961713Sgirish typedef struct block_info { 224344961713Sgirish char *name; 224444961713Sgirish uint32_t offset; 224544961713Sgirish } block_info_t; 224644961713Sgirish 224744961713Sgirish block_info_t reg_block[] = { 224844961713Sgirish {"PIO", PIO}, 224944961713Sgirish {"FZC_PIO", FZC_PIO}, 225044961713Sgirish {"FZC_XMAC", FZC_MAC}, 225144961713Sgirish {"FZC_IPP", FZC_IPP}, 225244961713Sgirish {"FFLP", FFLP}, 225344961713Sgirish {"FZC_FFLP", FZC_FFLP}, 225444961713Sgirish {"PIO_VADDR", PIO_VADDR}, 225544961713Sgirish {"ZCP", ZCP}, 225644961713Sgirish {"FZC_ZCP", FZC_ZCP}, 225744961713Sgirish {"DMC", DMC}, 225844961713Sgirish {"FZC_DMC", FZC_DMC}, 225944961713Sgirish {"TXC", TXC}, 226044961713Sgirish {"FZC_TXC", FZC_TXC}, 226144961713Sgirish {"PIO_LDSV", PIO_LDSV}, 226244961713Sgirish {"PIO_LDGIM", PIO_LDGIM}, 226344961713Sgirish {"PIO_IMASK0", PIO_IMASK0}, 226444961713Sgirish {"PIO_IMASK1", PIO_IMASK1}, 226544961713Sgirish {"FZC_PROM", FZC_PROM}, 226644961713Sgirish {"END", ALL_FF_32}, 226744961713Sgirish }; 226844961713Sgirish 226944961713Sgirish /* ARGSUSED */ 227044961713Sgirish static int 227144961713Sgirish nxge_param_dump_ptrs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 227244961713Sgirish { 2273a3c5bd6dSspeer uint_t print_len, buf_len; 2274a3c5bd6dSspeer p_mblk_t np; 2275a3c5bd6dSspeer int rdc, tdc, block; 2276a3c5bd6dSspeer uint64_t base; 227744961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 227844961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 2279a3c5bd6dSspeer int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_8K; 228044961713Sgirish p_tx_ring_t *tx_rings; 228144961713Sgirish p_rx_rcr_rings_t rx_rcr_rings; 228244961713Sgirish p_rx_rcr_ring_t *rcr_rings; 228344961713Sgirish p_rx_rbr_rings_t rx_rbr_rings; 228444961713Sgirish p_rx_rbr_ring_t *rbr_rings; 228544961713Sgirish 2286a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2287a3c5bd6dSspeer "==> nxge_param_dump_ptrs")); 228844961713Sgirish 2289a3c5bd6dSspeer (void) mi_mpprintf(mp, "ptr information for Port\t %d \n", 2290a3c5bd6dSspeer nxgep->function_num); 229144961713Sgirish 229244961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 229344961713Sgirish /* The following may work even if we cannot get a large buf. */ 229444961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 229544961713Sgirish return (0); 229644961713Sgirish } 229744961713Sgirish 229844961713Sgirish buf_len = buff_alloc_size; 229944961713Sgirish mp->b_cont = np; 230044961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 230144961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 230244961713Sgirish 230344961713Sgirish rx_rcr_rings = nxgep->rx_rcr_rings; 230444961713Sgirish rcr_rings = rx_rcr_rings->rcr_rings; 230544961713Sgirish rx_rbr_rings = nxgep->rx_rbr_rings; 230644961713Sgirish rbr_rings = rx_rbr_rings->rbr_rings; 230744961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2308a3c5bd6dSspeer "nxgep (nxge_t) $%p\n" 2309a3c5bd6dSspeer "dev_regs (dev_regs_t) $%p\n", 2310a3c5bd6dSspeer nxgep, nxgep->dev_regs); 231144961713Sgirish 231244961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2313a3c5bd6dSspeer 2314a3c5bd6dSspeer /* do register pointers */ 231544961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2316a3c5bd6dSspeer "reg base (npi_reg_ptr_t) $%p\t " 2317a3c5bd6dSspeer "pci reg (npi_reg_ptr_t) $%p\n", 2318a3c5bd6dSspeer nxgep->dev_regs->nxge_regp, 2319a3c5bd6dSspeer nxgep->dev_regs->nxge_pciregp); 232044961713Sgirish 232144961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 232244961713Sgirish 232344961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2324a3c5bd6dSspeer "\nBlock \t Offset \n"); 232544961713Sgirish 232644961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 232744961713Sgirish block = 0; 2328adfcba55Sjoycey #if defined(__i386) 2329adfcba55Sjoycey base = (uint64_t)(uint32_t)nxgep->dev_regs->nxge_regp; 2330adfcba55Sjoycey #else 233144961713Sgirish base = (uint64_t)nxgep->dev_regs->nxge_regp; 2332adfcba55Sjoycey #endif 233344961713Sgirish while (reg_block[block].offset != ALL_FF_32) { 233444961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2335a3c5bd6dSspeer "%9s\t 0x%llx\n", 2336a3c5bd6dSspeer reg_block[block].name, 2337a3c5bd6dSspeer (unsigned long long)(reg_block[block].offset + base)); 233844961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 233944961713Sgirish block++; 234044961713Sgirish } 234144961713Sgirish 234244961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2343a3c5bd6dSspeer "\nRDC\t rcrp (rx_rcr_ring_t)\t " 2344a3c5bd6dSspeer "rbrp (rx_rbr_ring_t)\n"); 234544961713Sgirish 234644961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 234744961713Sgirish 234844961713Sgirish for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 234944961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2350a3c5bd6dSspeer " %d\t $%p\t\t $%p\n", 2351a3c5bd6dSspeer rdc, rcr_rings[rdc], 2352a3c5bd6dSspeer rbr_rings[rdc]); 235344961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 235444961713Sgirish } 235544961713Sgirish 235644961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 235744961713Sgirish "\nTDC\t tdcp (tx_ring_t)\n"); 235844961713Sgirish 235944961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 236044961713Sgirish tx_rings = nxgep->tx_rings->rings; 2361*678453a8Sspeer for (tdc = 0; tdc < p_cfgp->tdc.count; tdc++) { 236244961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2363a3c5bd6dSspeer " %d\t $%p\n", tdc, tx_rings[tdc]); 236444961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 236544961713Sgirish } 236644961713Sgirish 2367a3c5bd6dSspeer print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, "\n\n"); 236844961713Sgirish 236944961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 237044961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ptrs")); 237144961713Sgirish return (0); 237244961713Sgirish } 237344961713Sgirish 237444961713Sgirish /* 237544961713Sgirish * Load 'name' into the named dispatch table pointed to by 'ndp'. 237644961713Sgirish * 'ndp' should be the address of a char pointer cell. If the table 237744961713Sgirish * does not exist (*ndp == 0), a new table is allocated and 'ndp' 237844961713Sgirish * is stuffed. If there is not enough space in the table for a new 237944961713Sgirish * entry, more space is allocated. 238044961713Sgirish */ 2381a3c5bd6dSspeer /* ARGSUSED */ 238244961713Sgirish boolean_t 238344961713Sgirish nxge_nd_load(caddr_t *pparam, char *name, 2384a3c5bd6dSspeer pfi_t get_pfi, pfi_t set_pfi, caddr_t data) 238544961713Sgirish { 238644961713Sgirish ND *nd; 238744961713Sgirish NDE *nde; 238844961713Sgirish 238944961713Sgirish NXGE_DEBUG_MSG((NULL, NDD2_CTL, " ==> nxge_nd_load")); 239044961713Sgirish if (!pparam) 239144961713Sgirish return (B_FALSE); 2392a3c5bd6dSspeer 239344961713Sgirish if ((nd = (ND *)*pparam) == NULL) { 2394a3c5bd6dSspeer if ((nd = (ND *)KMEM_ZALLOC(sizeof (ND), KM_NOSLEEP)) == NULL) 239544961713Sgirish return (B_FALSE); 239644961713Sgirish *pparam = (caddr_t)nd; 239744961713Sgirish } 2398a3c5bd6dSspeer 239944961713Sgirish if (nd->nd_tbl) { 240044961713Sgirish for (nde = nd->nd_tbl; nde->nde_name; nde++) { 240144961713Sgirish if (strcmp(name, nde->nde_name) == 0) 240244961713Sgirish goto fill_it; 240344961713Sgirish } 240444961713Sgirish } 2405a3c5bd6dSspeer 240644961713Sgirish if (nd->nd_free_count <= 1) { 240744961713Sgirish if ((nde = (NDE *)KMEM_ZALLOC(nd->nd_size + 240844961713Sgirish NDE_ALLOC_SIZE, KM_NOSLEEP)) == NULL) 240944961713Sgirish return (B_FALSE); 241044961713Sgirish nd->nd_free_count += NDE_ALLOC_COUNT; 241144961713Sgirish if (nd->nd_tbl) { 241244961713Sgirish bcopy((char *)nd->nd_tbl, (char *)nde, nd->nd_size); 241344961713Sgirish KMEM_FREE((char *)nd->nd_tbl, nd->nd_size); 241444961713Sgirish } else { 241544961713Sgirish nd->nd_free_count--; 241644961713Sgirish nde->nde_name = "?"; 241744961713Sgirish nde->nde_get_pfi = nxge_nd_get_names; 241844961713Sgirish nde->nde_set_pfi = nxge_set_default; 241944961713Sgirish } 242044961713Sgirish nde->nde_data = (caddr_t)nd; 242144961713Sgirish nd->nd_tbl = nde; 242244961713Sgirish nd->nd_size += NDE_ALLOC_SIZE; 242344961713Sgirish } 242444961713Sgirish for (nde = nd->nd_tbl; nde->nde_name; nde++) 242544961713Sgirish noop; 242644961713Sgirish nd->nd_free_count--; 242744961713Sgirish fill_it: 242844961713Sgirish nde->nde_name = name; 242944961713Sgirish nde->nde_get_pfi = get_pfi; 243044961713Sgirish nde->nde_set_pfi = set_pfi; 243144961713Sgirish nde->nde_data = data; 243244961713Sgirish NXGE_DEBUG_MSG((NULL, NDD2_CTL, " <== nxge_nd_load")); 243344961713Sgirish 243444961713Sgirish return (B_TRUE); 243544961713Sgirish } 243644961713Sgirish 243744961713Sgirish /* 243844961713Sgirish * Free the table pointed to by 'pparam' 243944961713Sgirish */ 244044961713Sgirish void 244144961713Sgirish nxge_nd_free(caddr_t *pparam) 244244961713Sgirish { 2443a3c5bd6dSspeer ND *nd; 244444961713Sgirish 244544961713Sgirish if ((nd = (ND *)*pparam) != NULL) { 244644961713Sgirish if (nd->nd_tbl) 244744961713Sgirish KMEM_FREE((char *)nd->nd_tbl, nd->nd_size); 244844961713Sgirish KMEM_FREE((char *)nd, sizeof (ND)); 244944961713Sgirish *pparam = nil(caddr_t); 245044961713Sgirish } 245144961713Sgirish } 245244961713Sgirish 245344961713Sgirish int 245444961713Sgirish nxge_nd_getset(p_nxge_t nxgep, queue_t *q, caddr_t param, p_mblk_t mp) 245544961713Sgirish { 2456a3c5bd6dSspeer int err; 2457a3c5bd6dSspeer IOCP iocp; 2458a3c5bd6dSspeer p_mblk_t mp1, mp2; 2459a3c5bd6dSspeer ND *nd; 2460a3c5bd6dSspeer NDE *nde; 2461a3c5bd6dSspeer char *valp; 2462a3c5bd6dSspeer size_t avail; 246344961713Sgirish 246444961713Sgirish if (!param) { 246544961713Sgirish return (B_FALSE); 246644961713Sgirish } 2467a3c5bd6dSspeer 246844961713Sgirish nd = (ND *)param; 246944961713Sgirish iocp = (IOCP)mp->b_rptr; 247044961713Sgirish if ((iocp->ioc_count == 0) || !(mp1 = mp->b_cont)) { 247144961713Sgirish mp->b_datap->db_type = M_IOCACK; 247244961713Sgirish iocp->ioc_count = 0; 247344961713Sgirish iocp->ioc_error = EINVAL; 247444961713Sgirish return (B_FALSE); 247544961713Sgirish } 2476a3c5bd6dSspeer 247744961713Sgirish /* 247844961713Sgirish * NOTE - logic throughout nd_xxx assumes single data block for ioctl. 247944961713Sgirish * However, existing code sends in some big buffers. 248044961713Sgirish */ 248144961713Sgirish avail = iocp->ioc_count; 248244961713Sgirish if (mp1->b_cont) { 248344961713Sgirish freemsg(mp1->b_cont); 248444961713Sgirish mp1->b_cont = NULL; 248544961713Sgirish } 248644961713Sgirish 248744961713Sgirish mp1->b_datap->db_lim[-1] = '\0'; /* Force null termination */ 248844961713Sgirish for (valp = (char *)mp1->b_rptr; *valp != '\0'; valp++) { 248944961713Sgirish if (*valp == '-') 249044961713Sgirish *valp = '_'; 249144961713Sgirish } 249244961713Sgirish 249344961713Sgirish valp = (char *)mp1->b_rptr; 249444961713Sgirish 249544961713Sgirish for (nde = nd->nd_tbl; /* */; nde++) { 249644961713Sgirish if (!nde->nde_name) 249744961713Sgirish return (B_FALSE); 249844961713Sgirish if (strcmp(nde->nde_name, valp) == 0) 249944961713Sgirish break; 250044961713Sgirish } 250144961713Sgirish err = EINVAL; 250244961713Sgirish while (*valp++) 250344961713Sgirish noop; 250444961713Sgirish if (!*valp || valp >= (char *)mp1->b_wptr) 250544961713Sgirish valp = nilp(char); 250644961713Sgirish switch (iocp->ioc_cmd) { 250744961713Sgirish case ND_GET: 250844961713Sgirish /* 250944961713Sgirish * (temporary) hack: "*valp" is size of user buffer for 251044961713Sgirish * copyout. If result of action routine is too big, free 251144961713Sgirish * excess and return ioc_rval as buffer size needed. 251244961713Sgirish * Return as many mblocks as will fit, free the rest. For 251344961713Sgirish * backward compatibility, assume size of original ioctl 251444961713Sgirish * buffer if "*valp" bad or not given. 251544961713Sgirish */ 251644961713Sgirish if (valp) 251744961713Sgirish avail = mi_strtol(valp, (char **)0, 10); 251844961713Sgirish /* 251944961713Sgirish * We overwrite the name/value with the reply data 252044961713Sgirish */ 252144961713Sgirish mp2 = mp1; 252244961713Sgirish while (mp2) { 252344961713Sgirish mp2->b_wptr = mp2->b_rptr; 252444961713Sgirish mp2 = mp2->b_cont; 252544961713Sgirish } 252644961713Sgirish 2527846a903dSml if (nde->nde_get_pfi) { 2528846a903dSml err = (*nde->nde_get_pfi)(nxgep, q, mp1, nde->nde_data); 2529846a903dSml } 253044961713Sgirish 253144961713Sgirish if (!err) { 253244961713Sgirish size_t size_out = 0; 2533958cea9eSml ssize_t excess; 253444961713Sgirish 253544961713Sgirish iocp->ioc_rval = 0; 253644961713Sgirish 253744961713Sgirish /* Tack on the null */ 253844961713Sgirish err = nxge_mk_mblk_tail_space(mp1, &mp2, 1); 253944961713Sgirish if (!err) { 254044961713Sgirish *mp2->b_wptr++ = '\0'; 254144961713Sgirish size_out = msgdsize(mp1); 254244961713Sgirish excess = size_out - avail; 254344961713Sgirish if (excess > 0) { 254444961713Sgirish iocp->ioc_rval = (int)size_out; 254544961713Sgirish size_out -= excess; 254644961713Sgirish (void) adjmsg(mp1, -(excess + 1)); 254744961713Sgirish err = nxge_mk_mblk_tail_space( 254844961713Sgirish mp1, &mp2, 1); 254944961713Sgirish if (!err) 255044961713Sgirish *mp2->b_wptr++ = '\0'; 255144961713Sgirish else 255244961713Sgirish size_out = 0; 255344961713Sgirish } 255444961713Sgirish } else 255544961713Sgirish size_out = 0; 255644961713Sgirish iocp->ioc_count = size_out; 255744961713Sgirish } 255844961713Sgirish break; 255944961713Sgirish 256044961713Sgirish case ND_SET: 256144961713Sgirish if (valp) { 256244961713Sgirish if (nde->nde_set_pfi) { 256344961713Sgirish err = (*nde->nde_set_pfi)(nxgep, q, mp1, valp, 256444961713Sgirish nde->nde_data); 256544961713Sgirish iocp->ioc_count = 0; 256644961713Sgirish freemsg(mp1); 256744961713Sgirish mp->b_cont = NULL; 256844961713Sgirish } 256944961713Sgirish } 25701bd6825cSml 25711bd6825cSml nxge_param_sync(nxgep); 25721bd6825cSml 257344961713Sgirish break; 257444961713Sgirish 257544961713Sgirish default: 257644961713Sgirish break; 257744961713Sgirish } 257844961713Sgirish iocp->ioc_error = err; 257944961713Sgirish mp->b_datap->db_type = M_IOCACK; 258044961713Sgirish return (B_TRUE); 258144961713Sgirish } 258244961713Sgirish 258344961713Sgirish /* ARGSUSED */ 258444961713Sgirish int 258544961713Sgirish nxge_nd_get_names(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t param) 258644961713Sgirish { 2587a3c5bd6dSspeer ND *nd; 2588a3c5bd6dSspeer NDE *nde; 2589a3c5bd6dSspeer char *rwtag; 2590a3c5bd6dSspeer boolean_t get_ok, set_ok; 2591a3c5bd6dSspeer size_t param_len; 2592a3c5bd6dSspeer int status = 0; 259344961713Sgirish 259444961713Sgirish nd = (ND *)param; 259544961713Sgirish if (!nd) 259644961713Sgirish return (ENOENT); 259744961713Sgirish 259844961713Sgirish for (nde = nd->nd_tbl; nde->nde_name; nde++) { 259944961713Sgirish get_ok = (nde->nde_get_pfi != nxge_get_default) && 260044961713Sgirish (nde->nde_get_pfi != NULL); 260144961713Sgirish set_ok = (nde->nde_set_pfi != nxge_set_default) && 260244961713Sgirish (nde->nde_set_pfi != NULL); 260344961713Sgirish if (get_ok) { 260444961713Sgirish if (set_ok) 260544961713Sgirish rwtag = "read and write"; 260644961713Sgirish else 260744961713Sgirish rwtag = "read only"; 260844961713Sgirish } else if (set_ok) 260944961713Sgirish rwtag = "write only"; 261044961713Sgirish else { 261144961713Sgirish continue; 261244961713Sgirish } 261344961713Sgirish param_len = strlen(rwtag); 261444961713Sgirish param_len += strlen(nde->nde_name); 261544961713Sgirish param_len += 4; 261644961713Sgirish 261744961713Sgirish (void) mi_mpprintf(mp, "%s (%s)", nde->nde_name, rwtag); 261844961713Sgirish } 261944961713Sgirish return (status); 262044961713Sgirish } 262144961713Sgirish 262244961713Sgirish /* ARGSUSED */ 262344961713Sgirish int 262444961713Sgirish nxge_get_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t data) 262544961713Sgirish { 262644961713Sgirish return (EACCES); 262744961713Sgirish } 262844961713Sgirish 262944961713Sgirish /* ARGSUSED */ 263044961713Sgirish int 263144961713Sgirish nxge_set_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, char *value, 2632a3c5bd6dSspeer caddr_t data) 263344961713Sgirish { 263444961713Sgirish return (EACCES); 263544961713Sgirish } 263644961713Sgirish 263744961713Sgirish void 263844961713Sgirish nxge_param_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 263944961713Sgirish { 264044961713Sgirish int cmd; 264144961713Sgirish int status = B_FALSE; 264244961713Sgirish 264344961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_ioctl")); 264444961713Sgirish cmd = iocp->ioc_cmd; 2645a3c5bd6dSspeer 264644961713Sgirish switch (cmd) { 264744961713Sgirish default: 264844961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, 264944961713Sgirish "nxge_param_ioctl: bad cmd 0x%0x", cmd)); 265044961713Sgirish break; 265144961713Sgirish 265244961713Sgirish case ND_GET: 265344961713Sgirish case ND_SET: 265444961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, 265544961713Sgirish "nxge_param_ioctl: cmd 0x%0x", cmd)); 265644961713Sgirish if (!nxge_nd_getset(nxgep, wq, nxgep->param_list, mp)) { 265744961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, 265844961713Sgirish "false ret from nxge_nd_getset")); 265944961713Sgirish break; 266044961713Sgirish } 266144961713Sgirish status = B_TRUE; 266244961713Sgirish break; 266344961713Sgirish } 266444961713Sgirish 266544961713Sgirish if (status) { 266644961713Sgirish qreply(wq, mp); 266744961713Sgirish } else { 266844961713Sgirish miocnak(wq, mp, 0, EINVAL); 266944961713Sgirish } 267044961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_ioctl")); 267144961713Sgirish } 267244961713Sgirish 26731bd6825cSml boolean_t 267444961713Sgirish nxge_param_link_update(p_nxge_t nxgep) 267544961713Sgirish { 267644961713Sgirish p_nxge_param_t param_arr; 267744961713Sgirish nxge_param_index_t i; 267844961713Sgirish boolean_t update_xcvr; 267944961713Sgirish boolean_t update_dev; 268044961713Sgirish int instance; 268144961713Sgirish boolean_t status = B_TRUE; 268244961713Sgirish 26831bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_link_update")); 268444961713Sgirish 268544961713Sgirish param_arr = nxgep->param_arr; 268644961713Sgirish instance = nxgep->instance; 268744961713Sgirish update_xcvr = B_FALSE; 268844961713Sgirish for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) { 268944961713Sgirish update_xcvr |= param_arr[i].value; 269044961713Sgirish } 269144961713Sgirish 269244961713Sgirish if (update_xcvr) { 269344961713Sgirish update_xcvr = B_FALSE; 269444961713Sgirish for (i = param_autoneg; i < param_enable_ipg0; i++) { 269544961713Sgirish update_xcvr |= 269644961713Sgirish (param_arr[i].value != param_arr[i].old_value); 269744961713Sgirish param_arr[i].old_value = param_arr[i].value; 269844961713Sgirish } 269944961713Sgirish if (update_xcvr) { 27001bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL, 27011bd6825cSml "==> nxge_param_link_update: update xcvr")); 270244961713Sgirish RW_ENTER_WRITER(&nxgep->filter_lock); 270344961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 270444961713Sgirish (void) nxge_link_init(nxgep); 270544961713Sgirish (void) nxge_mac_init(nxgep); 270644961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 270744961713Sgirish RW_EXIT(&nxgep->filter_lock); 270844961713Sgirish } 270944961713Sgirish } else { 271044961713Sgirish cmn_err(CE_WARN, " Last setting will leave nxge%d with " 271144961713Sgirish " no link capabilities.", instance); 271244961713Sgirish cmn_err(CE_WARN, " Restoring previous setting."); 271344961713Sgirish for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) 271444961713Sgirish param_arr[i].value = param_arr[i].old_value; 271544961713Sgirish } 2716a3c5bd6dSspeer 271744961713Sgirish update_dev = B_FALSE; 271844961713Sgirish 271944961713Sgirish if (update_dev) { 272044961713Sgirish RW_ENTER_WRITER(&nxgep->filter_lock); 27211bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL, 27221bd6825cSml "==> nxge_param_link_update: update dev")); 272344961713Sgirish (void) nxge_rx_mac_disable(nxgep); 272444961713Sgirish (void) nxge_tx_mac_disable(nxgep); 272544961713Sgirish (void) nxge_tx_mac_enable(nxgep); 272644961713Sgirish (void) nxge_rx_mac_enable(nxgep); 272744961713Sgirish RW_EXIT(&nxgep->filter_lock); 272844961713Sgirish } 272944961713Sgirish 273044961713Sgirish nxge_param_hw_update_exit: 273144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 273244961713Sgirish "<== nxge_param_link_update status = 0x%08x", status)); 273344961713Sgirish return (status); 273444961713Sgirish } 27351bd6825cSml 27361bd6825cSml /* 27371bd6825cSml * synchronize the adv* and en* parameters. 27381bd6825cSml * 27391bd6825cSml * See comments in <sys/dld.h> for details of the *_en_* 27401bd6825cSml * parameters. The usage of ndd for setting adv parameters will 27411bd6825cSml * synchronize all the en parameters with the nxge parameters, 27421bd6825cSml * implicitly disabling any settings made via dladm. 27431bd6825cSml */ 27441bd6825cSml static void 27451bd6825cSml nxge_param_sync(p_nxge_t nxgep) 27461bd6825cSml { 27471bd6825cSml p_nxge_param_t param_arr; 27481bd6825cSml param_arr = nxgep->param_arr; 27491bd6825cSml 27501bd6825cSml nxgep->param_en_pause = param_arr[param_anar_pause].value; 27511bd6825cSml nxgep->param_en_1000fdx = param_arr[param_anar_1000fdx].value; 27521bd6825cSml nxgep->param_en_100fdx = param_arr[param_anar_100fdx].value; 27531bd6825cSml nxgep->param_en_10fdx = param_arr[param_anar_10fdx].value; 27541bd6825cSml } 27551bd6825cSml 27561bd6825cSml /* ARGSUSED */ 27571bd6825cSml int 27581bd6825cSml nxge_dld_get_ip_opt(p_nxge_t nxgep, caddr_t cp) 27591bd6825cSml { 27601bd6825cSml uint32_t status, cfg_value; 27611bd6825cSml p_nxge_param_t pa = (p_nxge_param_t)cp; 27621bd6825cSml tcam_class_t class; 27631bd6825cSml 27641bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_dld_get_ip_opt")); 27651bd6825cSml 27661bd6825cSml /* do the actual hw setup */ 27671bd6825cSml class = nxge_class_name_2value(nxgep, pa->name); 27681bd6825cSml if (class == -1) 27691bd6825cSml return (EINVAL); 27701bd6825cSml 27711bd6825cSml cfg_value = 0; 27721bd6825cSml status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 27731bd6825cSml if (status != NXGE_OK) 27741bd6825cSml return (EINVAL); 27751bd6825cSml 27761bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL, 27771bd6825cSml "nxge_param_get_ip_opt_get %x ", cfg_value)); 27781bd6825cSml 27791bd6825cSml pa->value = cfg_value; 27801bd6825cSml 27811bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 27821bd6825cSml return (0); 27831bd6825cSml } 2784