1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/nxge/nxge_impl.h> 29 #include <inet/common.h> 30 #include <inet/mi.h> 31 #include <inet/nd.h> 32 33 extern uint64_t npi_debug_level; 34 35 #define NXGE_PARAM_MAC_RW NXGE_PARAM_RW | NXGE_PARAM_MAC | \ 36 NXGE_PARAM_NDD_WR_OK | NXGE_PARAM_READ_PROP 37 38 #define NXGE_PARAM_MAC_DONT_SHOW NXGE_PARAM_RW | NXGE_PARAM_MAC | \ 39 NXGE_PARAM_DONT_SHOW 40 41 42 #define NXGE_PARAM_RXDMA_RW NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | \ 43 NXGE_PARAM_NDD_WR_OK | NXGE_PARAM_READ_PROP 44 45 #define NXGE_PARAM_RXDMA_RWC NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | \ 46 NXGE_PARAM_INIT_ONLY | NXGE_PARAM_READ_PROP 47 48 49 #define NXGE_PARAM_L2CLASS_CFG NXGE_PARAM_RW | NXGE_PARAM_PROP_ARR32 | \ 50 NXGE_PARAM_READ_PROP | NXGE_PARAM_NDD_WR_OK 51 52 53 #define NXGE_PARAM_CLASS_RWS NXGE_PARAM_RWS | \ 54 NXGE_PARAM_READ_PROP 55 56 #define NXGE_PARAM_ARRAY_INIT_SIZE 0x20ULL 57 58 #define SET_RX_INTR_TIME_DISABLE 0 59 #define SET_RX_INTR_TIME_ENABLE 1 60 #define SET_RX_INTR_PKTS 2 61 62 #define BASE_ANY 0 63 #define BASE_BINARY 2 64 #define BASE_HEX 16 65 #define BASE_DECIMAL 10 66 #define ALL_FF_64 0xFFFFFFFFFFFFFFFFULL 67 #define ALL_FF_32 0xFFFFFFFFUL 68 69 #define NXGE_NDD_INFODUMP_BUFF_SIZE 2048 /* is 2k enough? */ 70 71 #define NXGE_NDD_INFODUMP_BUFF_8K 8192 72 #define NXGE_NDD_INFODUMP_BUFF_16K 0x2000 73 #define NXGE_NDD_INFODUMP_BUFF_64K 0x8000 74 75 #define PARAM_OUTOF_RANGE(vptr, eptr, rval, pa) \ 76 ((vptr == eptr) || (rval < pa->minimum) || (rval > pa->maximum)) 77 78 #define ADVANCE_PRINT_BUFFER(pmp, plen, rlen) { \ 79 ((mblk_t *)pmp)->b_wptr += plen; \ 80 rlen -= plen; \ 81 } 82 83 static void nxge_set_dev_params(p_nxge_t); 84 static int nxge_param_rx_intr_pkts(p_nxge_t, queue_t *, 85 mblk_t *, char *, caddr_t); 86 static int nxge_param_rx_intr_time(p_nxge_t, queue_t *, 87 mblk_t *, char *, caddr_t); 88 static int nxge_param_set_mac(p_nxge_t, queue_t *, 89 mblk_t *, char *, caddr_t); 90 static int nxge_param_set_port_rdc(p_nxge_t, queue_t *, 91 mblk_t *, char *, caddr_t); 92 93 static int nxge_param_set_grp_rdc(p_nxge_t, queue_t *, 94 mblk_t *, char *, caddr_t); 95 96 static int nxge_param_set_ether_usr(p_nxge_t, 97 queue_t *, mblk_t *, 98 char *, caddr_t); 99 static int nxge_param_set_ip_usr(p_nxge_t, 100 queue_t *, mblk_t *, 101 char *, caddr_t); 102 static int nxge_param_set_ip_opt(p_nxge_t, 103 queue_t *, mblk_t *, 104 char *, caddr_t); 105 static int nxge_param_set_vlan_rdcgrp(p_nxge_t, 106 queue_t *, mblk_t *, 107 char *, caddr_t); 108 static int nxge_param_set_mac_rdcgrp(p_nxge_t, 109 queue_t *, mblk_t *, 110 char *, caddr_t); 111 static int nxge_param_fflp_hash_init(p_nxge_t, 112 queue_t *, mblk_t *, 113 char *, caddr_t); 114 115 static int nxge_param_llc_snap_enable(p_nxge_t, queue_t *, 116 mblk_t *, char *, caddr_t); 117 118 static int nxge_param_hash_lookup_enable(p_nxge_t, queue_t *, 119 mblk_t *, char *, caddr_t); 120 121 static int nxge_param_tcam_enable(p_nxge_t, queue_t *, 122 mblk_t *, char *, caddr_t); 123 124 static int nxge_param_get_rxdma_info(p_nxge_t, queue_t *q, 125 p_mblk_t, caddr_t); 126 static int nxge_param_get_txdma_info(p_nxge_t, queue_t *q, 127 p_mblk_t, caddr_t); 128 129 static int nxge_param_get_vlan_rdcgrp(p_nxge_t, queue_t *, 130 p_mblk_t, caddr_t); 131 static int nxge_param_get_mac_rdcgrp(p_nxge_t, queue_t *, 132 p_mblk_t, caddr_t); 133 static int nxge_param_get_rxdma_rdcgrp_info(p_nxge_t, queue_t *, 134 p_mblk_t, caddr_t); 135 136 static int nxge_param_get_ip_opt(p_nxge_t, queue_t *, mblk_t *, caddr_t); 137 138 static int 139 nxge_param_get_mac(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 140 141 static int nxge_param_get_debug_flag(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 142 143 static int nxge_param_set_nxge_debug_flag(p_nxge_t, queue_t *, mblk_t *, 144 char *, caddr_t); 145 static int nxge_param_set_npi_debug_flag(p_nxge_t, 146 queue_t *, mblk_t *, 147 char *, caddr_t); 148 149 150 static int nxge_param_dump_rdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 151 152 static int nxge_param_dump_tdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 153 154 static int nxge_param_dump_mac_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 155 156 static int nxge_param_dump_ipp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 157 158 static int nxge_param_dump_fflp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 159 160 static int nxge_param_dump_vlan_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 161 162 static int nxge_param_dump_rdc_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 163 164 static int nxge_param_dump_ptrs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 165 166 167 static boolean_t nxge_param_link_update(p_nxge_t); 168 169 /* 170 * Global array of Neptune changable parameters. 171 * This array is initialized to correspond to the default 172 * Neptune 4 port configuration. This array would be copied 173 * into each port's parameter structure and modifed per 174 * fcode and nxge.conf configuration. Later, the parameters are 175 * exported to ndd to display and run-time configuration (at least 176 * some of them). 177 * 178 */ 179 180 static nxge_param_t nxge_param_arr[] = { 181 /* min max value old hw-name conf-name */ 182 183 { nxge_param_get_generic, NULL, 184 NXGE_PARAM_READ, 185 0, 999, 1000, 0, 186 "instance", "instance"}, 187 { nxge_param_get_generic, NULL, 188 NXGE_PARAM_READ, 189 0, 999, 1000, 0, 190 "main-instance", "main_instance"}, 191 192 { nxge_param_get_generic, NULL, 193 NXGE_PARAM_READ, 194 0, 3, 0, 0, 195 "function-number", "function_number"}, 196 /* Partition Id */ 197 { nxge_param_get_generic, NULL, 198 NXGE_PARAM_READ, 199 0, 8, 0, 0, 200 "partition-id", "partition_id"}, 201 /* Read Write Permission Mode */ 202 { nxge_param_get_generic, NULL, 203 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 204 0, 2, 0, 0, 205 "read-write-mode", "read_write_mode"}, 206 /* hw cfg types */ 207 /* control the DMA config of Neptune/NIU */ 208 { nxge_param_get_generic, NULL, 209 NXGE_PARAM_READ, 210 CFG_DEFAULT, CFG_CUSTOM, CFG_DEFAULT, CFG_DEFAULT, 211 "niu-cfg-type", "niu_cfg_type"}, 212 /* control the TXDMA config of the Port controlled by tx-quick-cfg */ 213 { nxge_param_get_generic, NULL, 214 NXGE_PARAM_READ, 215 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 216 "tx-qcfg-type", "tx_qcfg_type"}, 217 /* control the RXDMA config of the Port controlled by rx-quick-cfg */ 218 { nxge_param_get_generic, NULL, 219 NXGE_PARAM_READ, 220 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 221 "rx-qcfg-type", "rx_qcfg_type"}, 222 223 { nxge_param_get_mac, nxge_param_set_mac, 224 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 225 0, 1, 0, 0, 226 "master-cfg-enable", "master_cfg_enable"}, 227 { nxge_param_get_mac, nxge_param_set_mac, 228 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 229 0, 1, 0, 0, 230 "master-cfg-value", "master_cfg_value"}, 231 232 { nxge_param_get_mac, nxge_param_set_mac, 233 NXGE_PARAM_MAC_RW, 234 0, 1, 1, 1, 235 "adv-autoneg-cap", "adv_autoneg_cap"}, 236 { nxge_param_get_mac, nxge_param_set_mac, 237 NXGE_PARAM_MAC_RW, 238 0, 1, 1, 1, 239 "adv-10gfdx-cap", "adv_10gfdx_cap"}, 240 { nxge_param_get_mac, nxge_param_set_mac, 241 NXGE_PARAM_MAC_DONT_SHOW, 242 0, 1, 0, 0, 243 "adv-10ghdx-cap", "adv_10ghdx_cap"}, 244 245 { nxge_param_get_mac, nxge_param_set_mac, 246 NXGE_PARAM_MAC_RW, 247 0, 1, 1, 1, 248 "adv-1000fdx-cap", "adv_1000fdx_cap"}, 249 { nxge_param_get_mac, nxge_param_set_mac, 250 NXGE_PARAM_MAC_DONT_SHOW, 251 0, 1, 0, 0, 252 "adv-1000hdx-cap", "adv_1000hdx_cap"}, 253 { nxge_param_get_mac, nxge_param_set_mac, 254 NXGE_PARAM_MAC_DONT_SHOW, 255 0, 1, 0, 0, 256 "adv-100T4-cap", "adv_100T4_cap" }, 257 { nxge_param_get_mac, nxge_param_set_mac, 258 NXGE_PARAM_MAC_RW, 259 0, 1, 1, 1, 260 "adv-100fdx-cap", "adv_100fdx_cap"}, 261 { nxge_param_get_mac, nxge_param_set_mac, 262 NXGE_PARAM_MAC_DONT_SHOW, 263 0, 1, 0, 0, 264 "adv-100hdx-cap", "adv_100hdx_cap"}, 265 { nxge_param_get_mac, nxge_param_set_mac, 266 NXGE_PARAM_MAC_RW, 267 0, 1, 1, 1, 268 "adv-10fdx-cap", "adv_10fdx_cap" }, 269 { nxge_param_get_mac, nxge_param_set_mac, 270 NXGE_PARAM_MAC_DONT_SHOW, 271 0, 1, 0, 0, 272 "adv-10hdx-cap", "adv_10hdx_cap" }, 273 { nxge_param_get_mac, nxge_param_set_mac, 274 NXGE_PARAM_MAC_RW, 275 0, 1, 0, 0, 276 "adv-asmpause-cap", "adv_asmpause_cap"}, 277 { nxge_param_get_mac, nxge_param_set_mac, 278 NXGE_PARAM_MAC_RW, 279 0, 1, 0, 0, 280 "adv-pause-cap", "adv_pause_cap"}, 281 { nxge_param_get_mac, nxge_param_set_mac, 282 NXGE_PARAM_MAC_RW, 283 0, 1, 0, 0, 284 "use-int-xcvr", "use_int_xcvr"}, 285 { nxge_param_get_mac, nxge_param_set_mac, 286 NXGE_PARAM_MAC_RW, 287 0, 1, 1, 1, 288 "enable-ipg0", "enable_ipg0"}, 289 { nxge_param_get_mac, nxge_param_set_mac, 290 NXGE_PARAM_MAC_RW, 291 0, 255, 8, 8, 292 "ipg0", "ipg0"}, 293 { nxge_param_get_mac, nxge_param_set_mac, 294 NXGE_PARAM_MAC_RW, 295 0, 255, 8, 8, 296 "ipg1", "ipg1"}, 297 { nxge_param_get_mac, nxge_param_set_mac, 298 NXGE_PARAM_MAC_RW, 299 0, 255, 4, 4, 300 "ipg2", "ipg2"}, 301 { nxge_param_get_mac, nxge_param_set_mac, 302 NXGE_PARAM_MAC_RW, 303 0, 1, 0, 0, 304 "accept-jumbo", "accept_jumbo"}, 305 306 /* Transmit DMA channels */ 307 { nxge_param_get_generic, NULL, 308 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 309 0, 3, 0, 0, 310 "tx-dma-weight", "tx_dma_weight"}, 311 { nxge_param_get_generic, NULL, 312 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 313 0, 31, 0, 0, 314 "tx-dma-channels-begin", "tx_dma_channels_begin"}, 315 316 { nxge_param_get_generic, NULL, 317 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 318 0, 32, 0, 0, 319 "tx-dma-channels", "tx_dma_channels"}, 320 { nxge_param_get_txdma_info, NULL, 321 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 322 0, 32, 0, 0, 323 "tx-dma-info", "tx_dma_info"}, 324 /* Receive DMA channels */ 325 { nxge_param_get_generic, NULL, 326 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 327 0, 31, 0, 0, 328 "rx-dma-channels-begin", "rx_dma_channels_begin"}, 329 { nxge_param_get_generic, NULL, 330 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 331 0, 32, 0, 0, 332 "rx-dma-channels", "rx_dma_channels"}, 333 { nxge_param_get_generic, NULL, 334 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 335 0, 65535, PT_DRR_WT_DEFAULT_10G, 0, 336 "rx-drr-weight", "rx_drr_weight" }, 337 { nxge_param_get_generic, NULL, 338 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 339 0, 1, 1, 0, 340 "rx-full-header", "rx_full_header"}, 341 { nxge_param_get_rxdma_info, NULL, 342 NXGE_PARAM_READ, 343 0, 32, 0, 0, 344 "rx-dma-info", "rx_dma_info"}, 345 346 { nxge_param_get_rxdma_info, NULL, 347 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 348 NXGE_RBR_RBB_MIN, NXGE_RBR_RBB_MAX, NXGE_RBR_RBB_DEFAULT, 0, 349 "rx-rbr-size", "rx_rbr_size"}, 350 351 { nxge_param_get_rxdma_info, NULL, 352 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 353 NXGE_RCR_MIN, NXGE_RCR_MAX, NXGE_RCR_DEFAULT, 0, 354 "rx-rcr-size", "rx_rcr_size"}, 355 356 { nxge_param_get_generic, nxge_param_set_port_rdc, 357 NXGE_PARAM_RXDMA_RW, 358 0, 15, 0, 0, 359 "default-port-rdc", "default_port_rdc"}, 360 361 { nxge_param_get_generic, nxge_param_rx_intr_time, 362 NXGE_PARAM_RXDMA_RW, 363 NXGE_RDC_RCR_TIMEOUT_MIN, NXGE_RDC_RCR_TIMEOUT_MAX, 364 RXDMA_RCR_TO_DEFAULT, 0, 365 "rxdma-intr-time", "rxdma_intr_time"}, 366 { nxge_param_get_generic, nxge_param_rx_intr_pkts, 367 NXGE_PARAM_RXDMA_RW, 368 NXGE_RDC_RCR_THRESHOLD_MIN, NXGE_RDC_RCR_THRESHOLD_MAX, 369 RXDMA_RCR_PTHRES_DEFAULT, 0, 370 "rxdma-intr-pkts", "rxdma_intr_pkts"}, 371 372 { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP, 373 0, 8, 0, 0, 374 "rx-rdc-grps-begin", "rx_rdc_grps_begin"}, 375 { nxge_param_get_generic, NULL, 376 NXGE_PARAM_READ_PROP, 377 0, 8, 0, 0, 378 "rx-rdc-grps", "rx_rdc_grps"}, 379 380 { nxge_param_get_generic, nxge_param_set_grp_rdc, 381 NXGE_PARAM_RXDMA_RW, 382 0, 15, 0, 0, 383 "default-grp0-rdc", "default_grp0_rdc"}, 384 { nxge_param_get_generic, nxge_param_set_grp_rdc, 385 NXGE_PARAM_RXDMA_RW, 386 0, 15, 2, 0, 387 "default-grp1-rdc", "default_grp1_rdc"}, 388 { nxge_param_get_generic, nxge_param_set_grp_rdc, 389 NXGE_PARAM_RXDMA_RW, 390 0, 15, 4, 0, 391 "default-grp2-rdc", "default_grp2_rdc"}, 392 { nxge_param_get_generic, nxge_param_set_grp_rdc, 393 NXGE_PARAM_RXDMA_RW, 394 0, 15, 6, 0, 395 "default-grp3-rdc", "default_grp3_rdc"}, 396 { nxge_param_get_generic, nxge_param_set_grp_rdc, 397 NXGE_PARAM_RXDMA_RW, 398 0, 15, 8, 0, 399 "default-grp4-rdc", "default_grp4_rdc"}, 400 { nxge_param_get_generic, nxge_param_set_grp_rdc, 401 NXGE_PARAM_RXDMA_RW, 402 0, 15, 10, 0, 403 "default-grp5-rdc", "default_grp5_rdc"}, 404 { nxge_param_get_generic, nxge_param_set_grp_rdc, 405 NXGE_PARAM_RXDMA_RW, 406 0, 15, 12, 0, "default-grp6-rdc", "default_grp6_rdc"}, 407 { nxge_param_get_generic, nxge_param_set_grp_rdc, 408 NXGE_PARAM_RXDMA_RW, 409 0, 15, 14, 0, 410 "default-grp7-rdc", "default_grp7_rdc"}, 411 412 { nxge_param_get_rxdma_rdcgrp_info, NULL, 413 NXGE_PARAM_READ | NXGE_PARAM_CMPLX, 414 0, 8, 0, 0, 415 "rdc-groups-info", "rdc_groups_info"}, 416 /* Logical device groups */ 417 { nxge_param_get_generic, NULL, 418 NXGE_PARAM_READ, 419 0, 63, 0, 0, 420 "start-ldg", "start_ldg" }, 421 { nxge_param_get_generic, NULL, 422 NXGE_PARAM_READ, 423 0, 64, 0, 0, 424 "max-ldg", "max_ldg" }, 425 426 /* MAC table information */ 427 { nxge_param_get_mac_rdcgrp, nxge_param_set_mac_rdcgrp, 428 NXGE_PARAM_L2CLASS_CFG, 429 0, 31, 0, 0, 430 "mac-2rdc-grp", "mac_2rdc_grp"}, 431 /* VLAN table information */ 432 433 { nxge_param_get_vlan_rdcgrp, nxge_param_set_vlan_rdcgrp, 434 NXGE_PARAM_L2CLASS_CFG, 435 0, 31, 0, 0, 436 "vlan-2rdc-grp", "vlan_2rdc_grp"}, 437 438 { nxge_param_get_generic, NULL, 439 NXGE_PARAM_READ_PROP | NXGE_PARAM_READ | NXGE_PARAM_PROP_ARR32, 440 0, 0x0ffff, 0x0ffff, 0, 441 "fcram-part-cfg", "fcram_part_cfg"}, 442 443 { nxge_param_get_generic, NULL, 444 NXGE_PARAM_CLASS_RWS, 445 0, 0x10, 0xa, 0, 446 "fcram-access-ratio", "fcram_access_ratio"}, 447 448 { nxge_param_get_generic, NULL, 449 NXGE_PARAM_CLASS_RWS, 450 0, 0x10, 0xa, 0, 451 "tcam-access-ratio", "tcam_access_ratio"}, 452 453 454 { nxge_param_get_generic, nxge_param_tcam_enable, 455 NXGE_PARAM_CLASS_RWS, 456 0, 0x1, 0x0, 0, 457 "tcam-enable", "tcam_enable"}, 458 459 { nxge_param_get_generic, nxge_param_hash_lookup_enable, 460 NXGE_PARAM_CLASS_RWS, 461 0, 0x01, 0x0, 0, 462 "hash-lookup-enable", "hash_lookup_enable"}, 463 464 { nxge_param_get_generic, nxge_param_llc_snap_enable, 465 NXGE_PARAM_CLASS_RWS, 466 0, 0x01, 0x01, 0, 467 "llc-snap-enable", "llc_snap_enable"}, 468 469 { nxge_param_get_generic, nxge_param_fflp_hash_init, 470 NXGE_PARAM_CLASS_RWS, 471 0, ALL_FF_32, ALL_FF_32, 0, 472 "h1-init-value", "h1_init_value"}, 473 { nxge_param_get_generic, nxge_param_fflp_hash_init, 474 NXGE_PARAM_CLASS_RWS, 475 0, 0x0ffff, 0x0ffff, 0, 476 "h2-init-value", "h2_init_value"}, 477 478 { nxge_param_get_generic, nxge_param_set_ether_usr, 479 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 480 0, ALL_FF_32, 0x0, 0, 481 "class-cfg-ether-usr1", "class_cfg_ether_usr1"}, 482 483 { nxge_param_get_generic, nxge_param_set_ether_usr, 484 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 485 0, ALL_FF_32, 0x0, 0, 486 "class-cfg-ether-usr2", "class_cfg_ether_usr2"}, 487 { nxge_param_get_generic, nxge_param_set_ip_usr, 488 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 489 0, ALL_FF_32, 0x0, 0, 490 "class-cfg-ip-usr4", "class_cfg_ip_usr4"}, 491 { nxge_param_get_generic, nxge_param_set_ip_usr, 492 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 493 0, ALL_FF_32, 0x0, 0, 494 "class-cfg-ip-usr5", "class_cfg_ip_usr5"}, 495 { nxge_param_get_generic, nxge_param_set_ip_usr, 496 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 497 0, ALL_FF_32, 0x0, 0, 498 "class-cfg-ip-usr6", "class_cfg_ip_usr6"}, 499 { nxge_param_get_generic, nxge_param_set_ip_usr, 500 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 501 0, ALL_FF_32, 0x0, 0, 502 "class-cfg-ip-usr7", "class_cfg_ip_usr7"}, 503 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 504 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 505 0, ALL_FF_32, 0x0, 0, 506 "class-opt-ip-usr4", "class_opt_ip_usr4"}, 507 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 508 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 509 0, ALL_FF_32, 0x0, 0, 510 "class-opt-ip-usr5", "class_opt_ip_usr5"}, 511 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 512 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 513 0, ALL_FF_32, 0x0, 0, 514 "class-opt-ip-usr6", "class_opt_ip_usr6"}, 515 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 516 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 517 0, ALL_FF_32, 0x0, 0, 518 "class-opt-ip-usr7", "class_opt_ip_usr7"}, 519 520 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 521 NXGE_PARAM_CLASS_RWS, 522 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 523 "class-opt-ipv4-tcp", "class_opt_ipv4_tcp"}, 524 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 525 NXGE_PARAM_CLASS_RWS, 526 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 527 "class-opt-ipv4-udp", "class_opt_ipv4_udp"}, 528 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 529 NXGE_PARAM_CLASS_RWS, 530 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 531 "class-opt-ipv4-ah", "class_opt_ipv4_ah"}, 532 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 533 NXGE_PARAM_CLASS_RWS, 534 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 535 "class-opt-ipv4-sctp", "class_opt_ipv4_sctp"}, 536 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 537 NXGE_PARAM_CLASS_RWS, 538 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 539 "class-opt-ipv6-tcp", "class_opt_ipv6_tcp"}, 540 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 541 NXGE_PARAM_CLASS_RWS, 542 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 543 "class-opt-ipv6-udp", "class_opt_ipv6_udp"}, 544 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 545 NXGE_PARAM_CLASS_RWS, 546 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 547 "class-opt-ipv6-ah", "class_opt_ipv6_ah"}, 548 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 549 NXGE_PARAM_CLASS_RWS, 550 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 551 "class-opt-ipv6-sctp", "class_opt_ipv6_sctp"}, 552 553 { nxge_param_get_debug_flag, nxge_param_set_nxge_debug_flag, 554 NXGE_PARAM_RW, 555 0ULL, ALL_FF_64, 0ULL, 0ULL, 556 "nxge-debug-flag", "nxge_debug_flag"}, 557 { nxge_param_get_debug_flag, nxge_param_set_npi_debug_flag, 558 NXGE_PARAM_RW, 559 0ULL, ALL_FF_64, 0ULL, 0ULL, 560 "npi-debug-flag", "npi_debug_flag"}, 561 562 { nxge_param_dump_tdc, NULL, NXGE_PARAM_READ, 563 0, 0x0fffffff, 0x0fffffff, 0, 564 "dump-tdc", "dump_tdc"}, 565 566 { nxge_param_dump_rdc, NULL, NXGE_PARAM_READ, 567 0, 0x0fffffff, 0x0fffffff, 0, 568 "dump-rdc", "dump_rdc"}, 569 570 { nxge_param_dump_mac_regs, NULL, NXGE_PARAM_READ, 571 0, 0x0fffffff, 0x0fffffff, 0, 572 "dump-mac-regs", "dump_mac_regs"}, 573 574 { nxge_param_dump_ipp_regs, NULL, NXGE_PARAM_READ, 575 0, 0x0fffffff, 0x0fffffff, 0, 576 "dump-ipp-regs", "dump_ipp_regs"}, 577 578 { nxge_param_dump_fflp_regs, NULL, NXGE_PARAM_READ, 579 0, 0x0fffffff, 0x0fffffff, 0, 580 "dump-fflp-regs", "dump_fflp_regs"}, 581 582 { nxge_param_dump_vlan_table, NULL, NXGE_PARAM_READ, 583 0, 0x0fffffff, 0x0fffffff, 0, 584 "dump-vlan-table", "dump_vlan_table"}, 585 586 { nxge_param_dump_rdc_table, NULL, NXGE_PARAM_READ, 587 0, 0x0fffffff, 0x0fffffff, 0, 588 "dump-rdc-table", "dump_rdc_table"}, 589 590 { nxge_param_dump_ptrs, NULL, NXGE_PARAM_READ, 591 0, 0x0fffffff, 0x0fffffff, 0, 592 "dump-ptrs", "dump_ptrs"}, 593 594 595 { NULL, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 596 0, 0x0fffffff, 0x0fffffff, 0, "end", "end" }, 597 }; 598 599 extern void *nxge_list; 600 601 602 void 603 nxge_get_param_soft_properties(p_nxge_t nxgep) 604 { 605 606 p_nxge_param_t param_arr; 607 uint_t prop_len; 608 int i, j; 609 uint32_t param_count; 610 uint32_t *int_prop_val; 611 612 NXGE_DEBUG_MSG((nxgep, DDI_CTL, " ==> nxge_get_param_soft_properties")); 613 614 param_arr = nxgep->param_arr; 615 param_count = nxgep->param_count; 616 for (i = 0; i < param_count; i++) { 617 618 if ((param_arr[i].type & NXGE_PARAM_READ_PROP) == 0) 619 continue; 620 621 if ((param_arr[i].type & NXGE_PARAM_PROP_STR)) 622 continue; 623 624 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 625 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 626 627 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 628 nxgep->dip, 0, 629 param_arr[i].fcode_name, 630 (int **)&int_prop_val, 631 (uint_t *)&prop_len) 632 == DDI_PROP_SUCCESS) { 633 uint32_t *cfg_value; 634 uint64_t prop_count; 635 if (prop_len > NXGE_PARAM_ARRAY_INIT_SIZE) 636 prop_len = NXGE_PARAM_ARRAY_INIT_SIZE; 637 638 cfg_value = (uint32_t *)param_arr[i].value; 639 for (j = 0; j < prop_len; j++) { 640 cfg_value[j] = int_prop_val[j]; 641 } 642 prop_count = prop_len; 643 param_arr[i].type |= 644 (prop_count << NXGE_PARAM_ARRAY_CNT_SHIFT); 645 646 ddi_prop_free(int_prop_val); 647 } 648 649 continue; 650 } 651 652 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 653 param_arr[i].fcode_name, 654 (int **)&int_prop_val, 655 &prop_len) == DDI_PROP_SUCCESS) { 656 if ((*int_prop_val >= param_arr[i].minimum) && 657 (*int_prop_val <= param_arr[i].maximum)) 658 param_arr[i].value = *int_prop_val; 659 #ifdef NXGE_DEBUG_ERROR 660 else { 661 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 662 "nxge%d: 'prom' file" 663 " parameter error\n", 664 nxgep->instance)); 665 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 666 "Parameter keyword '%s'" 667 " is outside valid range\n", 668 param_arr[i].name)); 669 } 670 #endif 671 ddi_prop_free(int_prop_val); 672 } 673 674 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 675 param_arr[i].name, 676 (int **)&int_prop_val, 677 &prop_len) == DDI_PROP_SUCCESS) { 678 if ((*int_prop_val >= param_arr[i].minimum) && 679 (*int_prop_val <= param_arr[i].maximum)) 680 param_arr[i].value = *int_prop_val; 681 #ifdef NXGE_DEBUG_ERROR 682 else { 683 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 684 "nxge%d: 'conf' file" 685 " parameter error\n", 686 nxgep->instance)); 687 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 688 "Parameter keyword '%s'" 689 "is outside valid range\n", 690 param_arr[i].name)); 691 } 692 #endif 693 ddi_prop_free(int_prop_val); 694 } 695 } 696 } 697 698 699 700 701 static int 702 nxge_private_param_register(p_nxge_t nxgep, p_nxge_param_t param_arr) 703 { 704 705 int status = B_TRUE; 706 int channel; 707 uint8_t grp; 708 char *prop_name; 709 char *end; 710 uint32_t name_chars; 711 712 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 713 " nxge_private_param_register %s", 714 param_arr->name)); 715 716 if ((param_arr->type & NXGE_PARAM_PRIV) != NXGE_PARAM_PRIV) 717 return (B_TRUE); 718 prop_name = param_arr->name; 719 if (param_arr->type & NXGE_PARAM_RXDMA) { 720 if (strncmp("rxdma_intr", prop_name, 10) == 0) 721 return (B_TRUE); 722 name_chars = strlen("default_grp"); 723 if (strncmp("default_grp", prop_name, name_chars) == 0) { 724 prop_name += name_chars; 725 grp = mi_strtol(prop_name, &end, 10); 726 /* now check if this rdcgrp is in config */ 727 return (nxge_check_rdcgrp_port_member(nxgep, grp)); 728 } 729 name_chars = strlen(prop_name); 730 if (strncmp("default_port_rdc", prop_name, name_chars) == 0) { 731 return (B_TRUE); 732 } 733 734 return (B_FALSE); 735 } 736 737 if (param_arr->type & NXGE_PARAM_TXDMA) { 738 name_chars = strlen("txdma"); 739 if (strncmp("txdma", prop_name, name_chars) == 0) { 740 prop_name += name_chars; 741 channel = mi_strtol(prop_name, &end, 10); 742 /* now check if this rdc is in config */ 743 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 744 " nxge_private_param_register: %d", 745 channel)); 746 return (nxge_check_txdma_port_member(nxgep, channel)); 747 } 748 return (B_FALSE); 749 } 750 751 status = B_FALSE; 752 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, "<== nxge_private_param_register")); 753 754 return (status); 755 } 756 757 void 758 nxge_setup_param(p_nxge_t nxgep) 759 { 760 p_nxge_param_t param_arr; 761 int i; 762 pfi_t set_pfi; 763 764 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_setup_param")); 765 /* 766 * Make sure the param_instance is set to a valid device instance. 767 */ 768 if (nxge_param_arr[param_instance].value == 1000) 769 nxge_param_arr[param_instance].value = nxgep->instance; 770 771 param_arr = nxgep->param_arr; 772 param_arr[param_instance].value = nxgep->instance; 773 param_arr[param_function_number].value = nxgep->function_num; 774 775 for (i = 0; i < nxgep->param_count; i++) { 776 if ((param_arr[i].type & NXGE_PARAM_PRIV) && 777 (nxge_private_param_register(nxgep, 778 ¶m_arr[i]) == 779 B_FALSE)) { 780 param_arr[i].setf = NULL; 781 param_arr[i].getf = NULL; 782 } 783 784 if (param_arr[i].type & NXGE_PARAM_CMPLX) 785 param_arr[i].setf = NULL; 786 787 if (param_arr[i].type & NXGE_PARAM_DONT_SHOW) { 788 param_arr[i].setf = NULL; 789 param_arr[i].getf = NULL; 790 } 791 792 set_pfi = (pfi_t)param_arr[i].setf; 793 794 if ((set_pfi) && 795 (param_arr[i].type & NXGE_PARAM_INIT_ONLY)) { 796 set_pfi = NULL; 797 } 798 799 800 if (!nxge_nd_load(&nxgep->param_list, 801 param_arr[i].name, 802 (pfi_t)param_arr[i].getf, 803 set_pfi, 804 (caddr_t)¶m_arr[i])) { 805 (void) nxge_nd_free(&nxgep->param_list); 806 break; 807 } 808 809 } 810 811 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_setup_param")); 812 } 813 814 815 816 void 817 nxge_init_param(p_nxge_t nxgep) 818 { 819 p_nxge_param_t param_arr; 820 int i, alloc_size; 821 uint64_t alloc_count; 822 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_init_param")); 823 /* 824 * Make sure the param_instance is set to a valid device instance. 825 */ 826 if (nxge_param_arr[param_instance].value == 1000) 827 nxge_param_arr[param_instance].value = nxgep->instance; 828 829 param_arr = nxgep->param_arr; 830 if (param_arr == NULL) { 831 param_arr = (p_nxge_param_t)KMEM_ZALLOC( 832 sizeof (nxge_param_arr), KM_SLEEP); 833 } 834 for (i = 0; i < sizeof (nxge_param_arr)/sizeof (nxge_param_t); i++) { 835 param_arr[i] = nxge_param_arr[i]; 836 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 837 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 838 alloc_count = NXGE_PARAM_ARRAY_INIT_SIZE; 839 alloc_size = alloc_count * sizeof (uint64_t); 840 param_arr[i].value = 841 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 842 param_arr[i].old_value = 843 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 844 param_arr[i].type |= 845 (alloc_count << NXGE_PARAM_ARRAY_ALLOC_SHIFT); 846 } 847 } 848 849 nxgep->param_arr = param_arr; 850 nxgep->param_count = sizeof (nxge_param_arr)/sizeof (nxge_param_t); 851 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init_param: count %d", 852 nxgep->param_count)); 853 } 854 855 void 856 nxge_destroy_param(p_nxge_t nxgep) 857 { 858 int i; 859 uint64_t free_size, free_count; 860 861 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_param")); 862 /* 863 * Make sure the param_instance is set to a valid device instance. 864 */ 865 if (nxge_param_arr[param_instance].value == nxgep->instance) { 866 for (i = 0; i <= nxge_param_arr[param_instance].maximum; i++) { 867 if ((ddi_get_soft_state(nxge_list, i) != NULL) && 868 (i != nxgep->instance)) 869 break; 870 } 871 nxge_param_arr[param_instance].value = i; 872 } 873 874 if (nxgep->param_list) 875 nxge_nd_free(&nxgep->param_list); 876 for (i = 0; i < nxgep->param_count; i++) 877 if ((nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 878 (nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 879 free_count = ((nxgep->param_arr[i].type & 880 NXGE_PARAM_ARRAY_ALLOC_MASK) >> 881 NXGE_PARAM_ARRAY_ALLOC_SHIFT); 882 free_count = NXGE_PARAM_ARRAY_INIT_SIZE; 883 free_size = sizeof (uint64_t) * free_count; 884 KMEM_FREE((void *)nxgep->param_arr[i].value, free_size); 885 KMEM_FREE((void *)nxgep->param_arr[i].old_value, 886 free_size); 887 } 888 889 KMEM_FREE(nxgep->param_arr, sizeof (nxge_param_arr)); 890 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_param")); 891 } 892 893 /* 894 * Extracts the value from the 'nxge' parameter array and prints the 895 * parameter value. cp points to the required parameter. 896 */ 897 /* ARGSUSED */ 898 int 899 900 nxge_param_get_generic(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 901 { 902 p_nxge_param_t pa = (p_nxge_param_t)cp; 903 904 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " ==> nxge_param_get_generic name %s ", 905 pa->name)); 906 907 if (pa->value > 0xffffffff) 908 (void) mi_mpprintf(mp, "%x%x", (int)(pa->value >> 32), 909 (int)(pa->value & 0xffffffff)); 910 else 911 (void) mi_mpprintf(mp, "%x", (int)pa->value); 912 913 914 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_generic")); 915 return (0); 916 } 917 918 919 /* ARGSUSED */ 920 static int 921 nxge_param_get_mac(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 922 { 923 p_nxge_param_t pa = (p_nxge_param_t)cp; 924 925 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac")); 926 927 (void) mi_mpprintf(mp, "%d", (uint32_t)pa->value); 928 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_mac")); 929 return (0); 930 } 931 932 933 /* ARGSUSED */ 934 int 935 nxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 936 { 937 938 uint_t print_len, buf_len; 939 p_mblk_t np; 940 int tdc; 941 942 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 943 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_txdma_info")); 944 945 (void) mi_mpprintf(mp, 946 "TXDMA Information for Port\t %d \n", 947 nxgep->function_num); 948 949 950 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 951 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 952 return (0); 953 } 954 955 buf_len = buff_alloc_size; 956 957 mp->b_cont = np; 958 959 960 961 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 962 "Total TDCs\t %d\n", nxgep->ntdc); 963 964 ((mblk_t *)np)->b_wptr += print_len; 965 buf_len -= print_len; 966 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 967 "TDC\t HW TDC\t\n"); 968 ((mblk_t *)np)->b_wptr += print_len; 969 buf_len -= print_len; 970 for (tdc = 0; tdc < nxgep->ntdc; tdc++) { 971 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 972 buf_len, "%d\t %d\n", 973 tdc, nxgep->tdc[tdc]); 974 ((mblk_t *)np)->b_wptr += print_len; 975 buf_len -= print_len; 976 } 977 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_txdma_info")); 978 return (0); 979 } 980 981 982 /* ARGSUSED */ 983 int 984 nxge_param_get_rxdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 985 { 986 987 uint_t print_len, buf_len; 988 p_mblk_t np; 989 int rdc; 990 p_nxge_dma_pt_cfg_t p_dma_cfgp; 991 p_nxge_hw_pt_cfg_t p_cfgp; 992 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 993 994 p_rx_rcr_rings_t rx_rcr_rings; 995 p_rx_rcr_ring_t *rcr_rings; 996 p_rx_rbr_rings_t rx_rbr_rings; 997 p_rx_rbr_ring_t *rbr_rings; 998 999 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rxdma_info")); 1000 1001 (void) mi_mpprintf(mp, 1002 "RXDMA Information for Port\t %d \n", 1003 nxgep->function_num); 1004 1005 1006 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1007 /* The following may work even if we cannot get a large buf. */ 1008 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1009 return (0); 1010 } 1011 1012 buf_len = buff_alloc_size; 1013 1014 mp->b_cont = np; 1015 1016 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1017 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1018 1019 rx_rcr_rings = nxgep->rx_rcr_rings; 1020 rcr_rings = rx_rcr_rings->rcr_rings; 1021 rx_rbr_rings = nxgep->rx_rbr_rings; 1022 rbr_rings = rx_rbr_rings->rbr_rings; 1023 1024 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1025 "Total RDCs\t %d\n", 1026 p_cfgp->max_rdcs); 1027 1028 ((mblk_t *)np)->b_wptr += print_len; 1029 buf_len -= print_len; 1030 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1031 "RDC\t HW RDC\t Timeout\t Packets RBR ptr \t" 1032 "chunks\t RCR ptr\n"); 1033 ((mblk_t *)np)->b_wptr += print_len; 1034 buf_len -= print_len; 1035 for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 1036 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1037 " %d\t %d\t %x\t\t %x\t $%p\t 0x%x\t $%p\n", 1038 rdc, nxgep->rdc[rdc], 1039 p_dma_cfgp->rcr_timeout[rdc], 1040 p_dma_cfgp->rcr_threshold[rdc], 1041 rbr_rings[rdc], 1042 rbr_rings[rdc]->num_blocks, rcr_rings[rdc]); 1043 1044 ((mblk_t *)np)->b_wptr += print_len; 1045 buf_len -= print_len; 1046 } 1047 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rxdma_info")); 1048 return (0); 1049 } 1050 1051 1052 /* ARGSUSED */ 1053 int 1054 nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep, queue_t *q, 1055 p_mblk_t mp, caddr_t cp) 1056 { 1057 1058 uint_t print_len, buf_len; 1059 p_mblk_t np; 1060 int offset, rdc; 1061 int i, rdc_grp; 1062 p_nxge_rdc_grp_t rdc_grp_p; 1063 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1064 p_nxge_hw_pt_cfg_t p_cfgp; 1065 1066 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 1067 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1068 "==> nxge_param_get_rxdma_rdcgrp_info")); 1069 1070 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1071 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1072 1073 (void) mi_mpprintf(mp, 1074 "RXDMA RDC Group Information for Port\t %d \n", 1075 nxgep->function_num); 1076 1077 rdc_grp = p_cfgp->start_rdc_grpid; 1078 1079 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1080 /* The following may work even if we cannot get a large buf. */ 1081 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1082 return (0); 1083 } 1084 1085 buf_len = buff_alloc_size; 1086 1087 mp->b_cont = np; 1088 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1089 "Total RDC Groups\t %d \n" 1090 "start RDC group\t %d\n", 1091 p_cfgp->max_rdc_grpids, 1092 p_cfgp->start_rdc_grpid); 1093 1094 ((mblk_t *)np)->b_wptr += print_len; 1095 buf_len -= print_len; 1096 1097 for (i = 0, rdc_grp = p_cfgp->start_rdc_grpid; 1098 rdc_grp < (p_cfgp->max_rdc_grpids + p_cfgp->start_rdc_grpid); 1099 rdc_grp++, i++) { 1100 rdc_grp_p = &p_dma_cfgp->rdc_grps[i]; 1101 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1102 "\nRDC Group Info for Group [%d] %d\n" 1103 "RDC Count %d\tstart RDC %d\n" 1104 "RDC Group Population Information" 1105 " (offsets 0 - 15)\n", 1106 i, rdc_grp, rdc_grp_p->max_rdcs, 1107 rdc_grp_p->start_rdc); 1108 1109 ((mblk_t *)np)->b_wptr += print_len; 1110 buf_len -= print_len; 1111 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1112 buf_len, "\n"); 1113 ((mblk_t *)np)->b_wptr += print_len; 1114 buf_len -= print_len; 1115 1116 for (rdc = 0; rdc < rdc_grp_p->max_rdcs; rdc++) { 1117 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1118 buf_len, "[%d]=%d ", rdc, 1119 rdc_grp_p->start_rdc + rdc); 1120 ((mblk_t *)np)->b_wptr += print_len; 1121 buf_len -= print_len; 1122 } 1123 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1124 buf_len, "\n"); 1125 ((mblk_t *)np)->b_wptr += print_len; 1126 buf_len -= print_len; 1127 1128 for (offset = 0; offset < 16; offset++) { 1129 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1130 buf_len, " %2d ", 1131 rdc_grp_p->rdc[offset]); 1132 ((mblk_t *)np)->b_wptr += print_len; 1133 buf_len -= print_len; 1134 } 1135 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1136 buf_len, "\n"); 1137 ((mblk_t *)np)->b_wptr += print_len; 1138 buf_len -= print_len; 1139 } 1140 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1141 "<== nxge_param_get_rxdma_rdcgrp_info")); 1142 return (0); 1143 } 1144 1145 1146 int 1147 nxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size) 1148 { 1149 p_mblk_t tmp; 1150 1151 tmp = mp; 1152 while (tmp->b_cont) 1153 tmp = tmp->b_cont; 1154 if ((tmp->b_wptr + size) >= tmp->b_datap->db_lim) { 1155 tmp->b_cont = allocb(1024, BPRI_HI); 1156 tmp = tmp->b_cont; 1157 if (!tmp) 1158 return (ENOMEM); 1159 } 1160 *nmp = tmp; 1161 return (0); 1162 } 1163 1164 /* 1165 * Sets the ge parameter to the value in the nxge_param_register using 1166 * nxge_nd_load(). 1167 */ 1168 /* ARGSUSED */ 1169 int 1170 nxge_param_set_generic(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1171 char *value, caddr_t cp) 1172 { 1173 char *end; 1174 uint32_t new_value; 1175 p_nxge_param_t pa = (p_nxge_param_t)cp; 1176 1177 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " ==> nxge_param_set_generic")); 1178 new_value = (uint32_t)mi_strtol(value, &end, 10); 1179 if (end == value || new_value < pa->minimum || 1180 new_value > pa->maximum) { 1181 return (EINVAL); 1182 } 1183 pa->value = new_value; 1184 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " <== nxge_param_set_generic")); 1185 return (0); 1186 } 1187 1188 1189 1190 /* 1191 * Sets the ge parameter to the value in the nxge_param_register using 1192 * nxge_nd_load(). 1193 */ 1194 /* ARGSUSED */ 1195 1196 int 1197 nxge_param_set_instance(p_nxge_t nxgep, queue_t *q, 1198 mblk_t *mp, char *value, caddr_t cp) 1199 { 1200 1201 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " ==> nxge_param_set_instance")); 1202 1203 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_set_instance")); 1204 return (0); 1205 } 1206 1207 /* 1208 * Sets the ge parameter to the value in the nxge_param_register using 1209 * nxge_nd_load(). 1210 */ 1211 /* ARGSUSED */ 1212 1213 int 1214 nxge_param_set_mac(p_nxge_t nxgep, queue_t *q, 1215 mblk_t *mp, char *value, caddr_t cp) 1216 { 1217 char *end; 1218 uint32_t new_value; 1219 int status = 0; 1220 p_nxge_param_t pa = (p_nxge_param_t)cp; 1221 1222 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac")); 1223 new_value = (uint32_t)mi_strtol(value, &end, BASE_DECIMAL); 1224 if (PARAM_OUTOF_RANGE(value, end, new_value, pa)) { 1225 return (EINVAL); 1226 } 1227 1228 if (pa->value != new_value) { 1229 pa->old_value = pa->value; 1230 pa->value = new_value; 1231 } 1232 1233 if (!nxge_param_link_update(nxgep)) { 1234 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1235 " false ret from nxge_param_link_update")); 1236 status = EINVAL; 1237 } 1238 1239 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac")); 1240 return (status); 1241 } 1242 1243 /* ARGSUSED */ 1244 static int 1245 nxge_param_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, 1246 mblk_t *mp, char *value, caddr_t cp) 1247 { 1248 char *end; 1249 uint32_t cfg_value; 1250 p_nxge_param_t pa = (p_nxge_param_t)cp; 1251 1252 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_pkts")); 1253 1254 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1255 1256 if ((cfg_value > NXGE_RDC_RCR_THRESHOLD_MAX) || 1257 (cfg_value < NXGE_RDC_RCR_THRESHOLD_MIN)) { 1258 return (EINVAL); 1259 } 1260 1261 if ((pa->value != cfg_value)) { 1262 pa->old_value = pa->value; 1263 pa->value = cfg_value; 1264 nxgep->intr_threshold = pa->value; 1265 } 1266 1267 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_pkts")); 1268 return (0); 1269 } 1270 1271 1272 1273 /* ARGSUSED */ 1274 static int 1275 nxge_param_rx_intr_time(p_nxge_t nxgep, queue_t *q, 1276 mblk_t *mp, char *value, caddr_t cp) 1277 { 1278 char *end; 1279 uint32_t cfg_value; 1280 p_nxge_param_t pa = (p_nxge_param_t)cp; 1281 1282 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_time")); 1283 1284 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1285 1286 if ((cfg_value > NXGE_RDC_RCR_TIMEOUT_MAX) || 1287 (cfg_value < NXGE_RDC_RCR_TIMEOUT_MIN)) { 1288 return (EINVAL); 1289 } 1290 1291 if ((pa->value != cfg_value)) { 1292 pa->old_value = pa->value; 1293 pa->value = cfg_value; 1294 nxgep->intr_timeout = pa->value; 1295 } 1296 1297 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_time")); 1298 return (0); 1299 } 1300 1301 /* ARGSUSED */ 1302 static int 1303 nxge_param_set_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1304 mblk_t *mp, char *value, caddr_t cp) 1305 { 1306 char *end; 1307 uint32_t status = 0, cfg_value; 1308 p_nxge_param_t pa = (p_nxge_param_t)cp; 1309 uint32_t cfg_it = B_FALSE; 1310 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1311 p_nxge_hw_pt_cfg_t p_cfgp; 1312 uint32_t *val_ptr, *old_val_ptr; 1313 nxge_param_map_t *mac_map; 1314 p_nxge_class_pt_cfg_t p_class_cfgp; 1315 nxge_mv_cfg_t *mac_host_info; 1316 1317 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac_rdcgrp ")); 1318 1319 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1320 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1321 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1322 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 1323 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1324 /* now do decoding */ 1325 /* */ 1326 mac_map = (nxge_param_map_t *)&cfg_value; 1327 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1328 " cfg_value %x id %x map_to %x", 1329 cfg_value, mac_map->param_id, 1330 mac_map->map_to)); 1331 1332 if ((mac_map->param_id < p_cfgp->max_macs) && 1333 (mac_map->map_to < 1334 (p_cfgp->max_rdc_grpids + p_cfgp->start_rdc_grpid)) && 1335 (mac_map->map_to >= p_cfgp->start_rdc_grpid)) { 1336 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1337 " nxge_param_set_mac_rdcgrp mapping" 1338 " id %d grp %d", 1339 mac_map->param_id, mac_map->map_to)); 1340 val_ptr = (uint32_t *)pa->value; 1341 old_val_ptr = (uint32_t *)pa->old_value; 1342 if (val_ptr[mac_map->param_id] != cfg_value) { 1343 old_val_ptr[mac_map->param_id] = 1344 val_ptr[mac_map->param_id]; 1345 val_ptr[mac_map->param_id] = cfg_value; 1346 mac_host_info[mac_map->param_id].mpr_npr = 1347 mac_map->pref; 1348 mac_host_info[mac_map->param_id].flag = 1; 1349 mac_host_info[mac_map->param_id].rdctbl = 1350 mac_map->map_to; 1351 cfg_it = B_TRUE; 1352 } 1353 1354 } else { 1355 return (EINVAL); 1356 } 1357 1358 if (cfg_it == B_TRUE) { 1359 status = nxge_logical_mac_assign_rdc_table(nxgep, 1360 (uint8_t)mac_map->param_id); 1361 if (status != NXGE_OK) 1362 return (EINVAL); 1363 } 1364 1365 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac_rdcgrp")); 1366 return (0); 1367 } 1368 1369 /* ARGSUSED */ 1370 static int 1371 nxge_param_set_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1372 mblk_t *mp, char *value, caddr_t cp) 1373 { 1374 char *end; 1375 uint32_t status = 0, cfg_value; 1376 p_nxge_param_t pa = (p_nxge_param_t)cp; 1377 uint32_t cfg_it = B_FALSE; 1378 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1379 p_nxge_hw_pt_cfg_t p_cfgp; 1380 uint32_t *val_ptr, *old_val_ptr; 1381 nxge_param_map_t *vmap, *old_map; 1382 p_nxge_class_pt_cfg_t p_class_cfgp; 1383 uint64_t cfgd_vlans; 1384 int i, inc = 0, cfg_position; 1385 nxge_mv_cfg_t *vlan_tbl; 1386 1387 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1388 1389 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1390 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1391 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1392 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 1393 1394 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1395 /* now do decoding */ 1396 /* */ 1397 cfgd_vlans = ((pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1398 NXGE_PARAM_ARRAY_CNT_SHIFT); 1399 1400 if (cfgd_vlans == NXGE_PARAM_ARRAY_INIT_SIZE) { 1401 /* 1402 * for now, we process only upto max 1403 * NXGE_PARAM_ARRAY_INIT_SIZE parameters 1404 * In the future, we may want to expand 1405 * the storage array and continue 1406 */ 1407 return (EINVAL); 1408 } 1409 vmap = (nxge_param_map_t *)&cfg_value; 1410 if ((vmap->param_id) && 1411 (vmap->param_id < NXGE_MAX_VLANS) && 1412 (vmap->map_to < p_cfgp->max_rdc_grpids)) { 1413 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1414 " nxge_param_set_vlan_rdcgrp mapping" 1415 " id %d grp %d", 1416 vmap->param_id, vmap->map_to)); 1417 val_ptr = (uint32_t *)pa->value; 1418 old_val_ptr = (uint32_t *)pa->old_value; 1419 1420 /* search to see if this vlan id is already configured */ 1421 for (i = 0; i < cfgd_vlans; i++) { 1422 old_map = (nxge_param_map_t *)&val_ptr[i]; 1423 if ((old_map->param_id == 0) || 1424 (vmap->param_id == old_map->param_id) || 1425 (vlan_tbl[vmap->param_id].flag)) { 1426 cfg_position = i; 1427 break; 1428 } 1429 } 1430 1431 if (cfgd_vlans == 0) { 1432 cfg_position = 0; 1433 inc++; 1434 } 1435 1436 if (i == cfgd_vlans) { 1437 cfg_position = i; 1438 inc++; 1439 } 1440 1441 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1442 " set_vlan_rdcgrp mapping" 1443 " i %d cfgd_vlans %llx position %d ", 1444 i, cfgd_vlans, cfg_position)); 1445 if (val_ptr[cfg_position] != cfg_value) { 1446 old_val_ptr[cfg_position] = val_ptr[cfg_position]; 1447 val_ptr[cfg_position] = cfg_value; 1448 vlan_tbl[vmap->param_id].mpr_npr = vmap->pref; 1449 vlan_tbl[vmap->param_id].flag = 1; 1450 vlan_tbl[vmap->param_id].rdctbl = 1451 vmap->map_to + p_cfgp->start_rdc_grpid; 1452 cfg_it = B_TRUE; 1453 if (inc) { 1454 cfgd_vlans++; 1455 pa->type &= ~NXGE_PARAM_ARRAY_CNT_MASK; 1456 pa->type |= (cfgd_vlans << 1457 NXGE_PARAM_ARRAY_CNT_SHIFT); 1458 1459 } 1460 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1461 " after: param_set_vlan_rdcgrp " 1462 " cfg_vlans %llx position %d \n", 1463 cfgd_vlans, cfg_position)); 1464 } 1465 1466 } else { 1467 return (EINVAL); 1468 } 1469 1470 if (cfg_it == B_TRUE) { 1471 status = nxge_fflp_config_vlan_table(nxgep, 1472 (uint16_t)vmap->param_id); 1473 if (status != NXGE_OK) 1474 return (EINVAL); 1475 } 1476 1477 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_vlan_rdcgrp")); 1478 return (0); 1479 } 1480 1481 1482 1483 1484 1485 /* ARGSUSED */ 1486 static int 1487 nxge_param_get_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1488 mblk_t *mp, caddr_t cp) 1489 { 1490 1491 uint_t print_len, buf_len; 1492 p_mblk_t np; 1493 int i; 1494 uint32_t *val_ptr; 1495 nxge_param_map_t *vmap; 1496 p_nxge_param_t pa = (p_nxge_param_t)cp; 1497 p_nxge_class_pt_cfg_t p_class_cfgp; 1498 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1499 p_nxge_hw_pt_cfg_t p_cfgp; 1500 uint64_t cfgd_vlans = 0; 1501 nxge_mv_cfg_t *vlan_tbl; 1502 1503 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 1504 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1505 (void) mi_mpprintf(mp, 1506 "VLAN RDC Mapping Information for Port\t %d \n", 1507 nxgep->function_num); 1508 1509 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1510 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1511 return (0); 1512 } 1513 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1514 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1515 1516 buf_len = buff_alloc_size; 1517 mp->b_cont = np; 1518 cfgd_vlans = (pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1519 NXGE_PARAM_ARRAY_CNT_SHIFT; 1520 1521 i = (int)cfgd_vlans; 1522 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1523 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 1524 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1525 "Configured VLANs %d\n" 1526 "VLAN ID\t RDC GRP (Actual/Port)\t" 1527 " Prefernce\n", i); 1528 ((mblk_t *)np)->b_wptr += print_len; 1529 buf_len -= print_len; 1530 1531 val_ptr = (uint32_t *)pa->value; 1532 1533 for (i = 0; i < cfgd_vlans; i++) { 1534 vmap = (nxge_param_map_t *)&val_ptr[i]; 1535 if (p_class_cfgp->vlan_tbl[vmap->param_id].flag) { 1536 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1537 buf_len, 1538 " %d\t\t %d/%d\t\t %d\n", 1539 vmap->param_id, 1540 vlan_tbl[vmap->param_id].rdctbl, 1541 vlan_tbl[vmap->param_id].rdctbl - 1542 p_cfgp->start_rdc_grpid, 1543 vlan_tbl[vmap->param_id].mpr_npr); 1544 ((mblk_t *)np)->b_wptr += print_len; 1545 buf_len -= print_len; 1546 } 1547 } 1548 1549 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_vlan_rdcgrp")); 1550 return (0); 1551 } 1552 1553 1554 1555 /* ARGSUSED */ 1556 static int 1557 nxge_param_get_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1558 mblk_t *mp, caddr_t cp) 1559 { 1560 1561 uint_t print_len, buf_len; 1562 p_mblk_t np; 1563 int i; 1564 p_nxge_class_pt_cfg_t p_class_cfgp; 1565 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1566 p_nxge_hw_pt_cfg_t p_cfgp; 1567 nxge_mv_cfg_t *mac_host_info; 1568 1569 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 1570 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac_rdcgrp ")); 1571 (void) mi_mpprintf(mp, 1572 " MAC ADDR RDC Mapping Information for Port\t %d\n", 1573 nxgep->function_num); 1574 1575 1576 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1577 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1578 return (0); 1579 } 1580 1581 buf_len = buff_alloc_size; 1582 mp->b_cont = np; 1583 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1584 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1585 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1586 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 1587 print_len = snprintf((char *)np->b_wptr, buf_len, 1588 "MAC ID\t RDC GRP (Actual/Port)\t" 1589 " Prefernce\n"); 1590 1591 ((mblk_t *)np)->b_wptr += print_len; 1592 buf_len -= print_len; 1593 for (i = 0; i < p_cfgp->max_macs; i++) { 1594 if (mac_host_info[i].flag) { 1595 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1596 buf_len, 1597 " %d\t %d/%d\t\t %d\n", 1598 i, 1599 mac_host_info[i].rdctbl, 1600 mac_host_info[i].rdctbl - 1601 p_cfgp->start_rdc_grpid, 1602 mac_host_info[i].mpr_npr); 1603 1604 ((mblk_t *)np)->b_wptr += print_len; 1605 buf_len -= print_len; 1606 } 1607 } 1608 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1609 "Done Info Dumping \n"); 1610 ((mblk_t *)np)->b_wptr += print_len; 1611 buf_len -= print_len; 1612 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_macrdcgrp")); 1613 return (0); 1614 } 1615 1616 1617 1618 /* ARGSUSED */ 1619 static int 1620 nxge_param_tcam_enable(p_nxge_t nxgep, queue_t *q, 1621 mblk_t *mp, char *value, caddr_t cp) 1622 { 1623 uint32_t status = 0, cfg_value; 1624 p_nxge_param_t pa = (p_nxge_param_t)cp; 1625 uint32_t cfg_it = B_FALSE; 1626 char *end; 1627 1628 1629 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_tcam_enable")); 1630 1631 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1632 if (pa->value != cfg_value) { 1633 pa->old_value = pa->value; 1634 pa->value = cfg_value; 1635 cfg_it = B_TRUE; 1636 } 1637 1638 if (cfg_it == B_TRUE) { 1639 if (pa->value) 1640 status = nxge_fflp_config_tcam_enable(nxgep); 1641 else 1642 status = nxge_fflp_config_tcam_disable(nxgep); 1643 if (status != NXGE_OK) 1644 return (EINVAL); 1645 } 1646 1647 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_tcam_enable")); 1648 return (0); 1649 } 1650 1651 /* ARGSUSED */ 1652 static int 1653 nxge_param_hash_lookup_enable(p_nxge_t nxgep, queue_t *q, 1654 mblk_t *mp, char *value, caddr_t cp) 1655 { 1656 uint32_t status = 0, cfg_value; 1657 p_nxge_param_t pa = (p_nxge_param_t)cp; 1658 uint32_t cfg_it = B_FALSE; 1659 char *end; 1660 1661 1662 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_hash_lookup_enable")); 1663 1664 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1665 if (pa->value != cfg_value) { 1666 pa->old_value = pa->value; 1667 pa->value = cfg_value; 1668 cfg_it = B_TRUE; 1669 } 1670 1671 if (cfg_it == B_TRUE) { 1672 if (pa->value) 1673 status = nxge_fflp_config_hash_lookup_enable(nxgep); 1674 else 1675 status = nxge_fflp_config_hash_lookup_disable(nxgep); 1676 if (status != NXGE_OK) 1677 return (EINVAL); 1678 } 1679 1680 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_hash_lookup_enable")); 1681 return (0); 1682 } 1683 1684 /* ARGSUSED */ 1685 static int 1686 nxge_param_llc_snap_enable(p_nxge_t nxgep, queue_t *q, 1687 mblk_t *mp, char *value, caddr_t cp) 1688 { 1689 char *end; 1690 uint32_t status = 0, cfg_value; 1691 p_nxge_param_t pa = (p_nxge_param_t)cp; 1692 uint32_t cfg_it = B_FALSE; 1693 1694 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_llc_snap_enable")); 1695 1696 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1697 if (pa->value != cfg_value) { 1698 pa->old_value = pa->value; 1699 pa->value = cfg_value; 1700 cfg_it = B_TRUE; 1701 } 1702 1703 if (cfg_it == B_TRUE) { 1704 if (pa->value) 1705 status = nxge_fflp_config_tcam_enable(nxgep); 1706 else 1707 status = nxge_fflp_config_tcam_disable(nxgep); 1708 if (status != NXGE_OK) 1709 return (EINVAL); 1710 } 1711 1712 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_llc_snap_enable")); 1713 return (0); 1714 } 1715 1716 1717 /* ARGSUSED */ 1718 1719 static int 1720 nxge_param_set_ether_usr(p_nxge_t nxgep, queue_t *q, 1721 mblk_t *mp, char *value, caddr_t cp) 1722 { 1723 char *end; 1724 uint8_t ether_class; 1725 uint32_t status = 0, cfg_value; 1726 p_nxge_param_t pa = (p_nxge_param_t)cp; 1727 uint8_t cfg_it = B_FALSE; 1728 1729 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ether_usr")); 1730 1731 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1732 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1733 return (EINVAL); 1734 } 1735 if (pa->value != cfg_value) { 1736 pa->old_value = pa->value; 1737 pa->value = cfg_value; 1738 cfg_it = B_TRUE; 1739 } 1740 1741 /* do the actual hw setup */ 1742 if (cfg_it == B_TRUE) { 1743 ether_class = mi_strtol(pa->name, &end, 10); 1744 #ifdef lint 1745 ether_class = ether_class; 1746 #endif 1747 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_ether_usr")); 1748 } 1749 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ether_usr")); 1750 return (status); 1751 } 1752 1753 /* ARGSUSED */ 1754 static int 1755 nxge_param_set_ip_usr(p_nxge_t nxgep, queue_t *q, 1756 mblk_t *mp, char *value, caddr_t cp) 1757 { 1758 char *end; 1759 tcam_class_t class; 1760 uint32_t status, cfg_value; 1761 p_nxge_param_t pa = (p_nxge_param_t)cp; 1762 uint32_t cfg_it = B_FALSE; 1763 1764 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_usr")); 1765 1766 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1767 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1768 return (EINVAL); 1769 } 1770 1771 if (pa->value != cfg_value) { 1772 pa->old_value = pa->value; 1773 pa->value = cfg_value; 1774 cfg_it = B_TRUE; 1775 } 1776 1777 /* do the actual hw setup with cfg_value. */ 1778 if (cfg_it == B_TRUE) { 1779 class = mi_strtol(pa->name, &end, 10); 1780 status = nxge_fflp_ip_usr_class_config(nxgep, class, pa->value); 1781 } 1782 1783 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_usr")); 1784 return (status); 1785 } 1786 1787 static int 1788 nxge_class_name_2value(p_nxge_t nxgep, char *name) 1789 { 1790 int i; 1791 int class_instance = param_class_opt_ip_usr4; 1792 p_nxge_param_t param_arr; 1793 param_arr = nxgep->param_arr; 1794 for (i = TCAM_CLASS_IP_USER_4; i <= TCAM_CLASS_SCTP_IPV6; i++) { 1795 if (strcmp(param_arr[class_instance].name, name) == 0) 1796 return (i); 1797 class_instance++; 1798 } 1799 return (-1); 1800 } 1801 1802 /* ARGSUSED */ 1803 static int 1804 nxge_param_set_ip_opt(p_nxge_t nxgep, queue_t *q, 1805 mblk_t *mp, char *value, caddr_t cp) 1806 { 1807 char *end; 1808 uint32_t status, cfg_value; 1809 p_nxge_param_t pa = (p_nxge_param_t)cp; 1810 tcam_class_t class; 1811 uint32_t cfg_it = B_FALSE; 1812 1813 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_opt")); 1814 1815 1816 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1817 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1818 return (EINVAL); 1819 } 1820 1821 if (pa->value != cfg_value) { 1822 pa->old_value = pa->value; 1823 pa->value = cfg_value; 1824 cfg_it = B_TRUE; 1825 } 1826 1827 if (cfg_it == B_TRUE) { 1828 /* do the actual hw setup */ 1829 class = nxge_class_name_2value(nxgep, pa->name); 1830 if (class == -1) 1831 return (EINVAL); 1832 1833 status = nxge_fflp_ip_class_config(nxgep, class, pa->value); 1834 if (status != NXGE_OK) 1835 return (EINVAL); 1836 } 1837 1838 1839 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_opt")); 1840 return (0); 1841 } 1842 1843 /* ARGSUSED */ 1844 static int 1845 nxge_param_get_ip_opt(p_nxge_t nxgep, queue_t *q, 1846 mblk_t *mp, caddr_t cp) 1847 { 1848 uint32_t status, cfg_value; 1849 p_nxge_param_t pa = (p_nxge_param_t)cp; 1850 tcam_class_t class; 1851 1852 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_ip_opt")); 1853 1854 /* do the actual hw setup */ 1855 class = nxge_class_name_2value(nxgep, pa->name); 1856 if (class == -1) 1857 return (EINVAL); 1858 cfg_value = 0; 1859 status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 1860 if (status != NXGE_OK) 1861 return (EINVAL); 1862 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1863 "nxge_param_get_ip_opt_get %x ", cfg_value)); 1864 pa->value = cfg_value; 1865 1866 (void) mi_mpprintf(mp, "%x", cfg_value); 1867 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 1868 return (0); 1869 } 1870 1871 1872 /* ARGSUSED */ 1873 static int 1874 nxge_param_fflp_hash_init(p_nxge_t nxgep, queue_t *q, 1875 mblk_t *mp, char *value, caddr_t cp) 1876 { 1877 char *end; 1878 uint32_t status, cfg_value; 1879 p_nxge_param_t pa = (p_nxge_param_t)cp; 1880 tcam_class_t class; 1881 uint32_t cfg_it = B_FALSE; 1882 1883 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_fflp_hash_init")); 1884 1885 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1886 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1887 return (EINVAL); 1888 } 1889 1890 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1891 " nxge_param_fflp_hash_init value %x", 1892 cfg_value)); 1893 if (pa->value != cfg_value) { 1894 pa->old_value = pa->value; 1895 pa->value = cfg_value; 1896 cfg_it = B_TRUE; 1897 } 1898 1899 1900 if (cfg_it == B_TRUE) { 1901 char *h_name; 1902 /* do the actual hw setup */ 1903 h_name = pa->name; 1904 h_name++; 1905 class = mi_strtol(h_name, &end, 10); 1906 switch (class) { 1907 case 1: 1908 status = nxge_fflp_set_hash1(nxgep, 1909 (uint32_t)pa->value); 1910 break; 1911 1912 case 2: 1913 status = nxge_fflp_set_hash2(nxgep, 1914 (uint16_t)pa->value); 1915 break; 1916 1917 default: 1918 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1919 " nxge_param_fflp_hash_init" 1920 " %s Wrong hash var %d", 1921 pa->name, class)); 1922 return (EINVAL); 1923 } 1924 if (status != NXGE_OK) 1925 return (EINVAL); 1926 } 1927 1928 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_fflp_hash_init")); 1929 return (0); 1930 } 1931 1932 1933 /* ARGSUSED */ 1934 1935 static int 1936 nxge_param_set_grp_rdc(p_nxge_t nxgep, queue_t *q, 1937 mblk_t *mp, char *value, caddr_t cp) 1938 { 1939 char *end; 1940 uint32_t status = 0, cfg_value; 1941 p_nxge_param_t pa = (p_nxge_param_t)cp; 1942 uint32_t cfg_it = B_FALSE; 1943 int rdc_grp; 1944 uint8_t real_rdc; 1945 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1946 p_nxge_hw_pt_cfg_t p_cfgp; 1947 p_nxge_rdc_grp_t rdc_grp_p; 1948 1949 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1950 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1951 1952 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_grp_rdc")); 1953 1954 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1955 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1956 return (EINVAL); 1957 } 1958 if (cfg_value >= p_cfgp->max_rdcs) { 1959 return (EINVAL); 1960 } 1961 if (pa->value != cfg_value) { 1962 pa->old_value = pa->value; 1963 pa->value = cfg_value; 1964 cfg_it = B_TRUE; 1965 } 1966 1967 if (cfg_it == B_TRUE) { 1968 char *grp_name; 1969 grp_name = pa->name; 1970 grp_name += strlen("default-grp"); 1971 rdc_grp = mi_strtol(grp_name, &end, 10); 1972 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp]; 1973 real_rdc = rdc_grp_p->start_rdc + cfg_value; 1974 if (nxge_check_rxdma_rdcgrp_member(nxgep, rdc_grp, 1975 cfg_value) == B_FALSE) { 1976 pa->value = pa->old_value; 1977 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1978 " nxge_param_set_grp_rdc" 1979 " %d read %d actual %d outof range", 1980 rdc_grp, cfg_value, real_rdc)); 1981 return (EINVAL); 1982 } 1983 status = nxge_rxdma_cfg_rdcgrp_default_rdc(nxgep, rdc_grp, 1984 real_rdc); 1985 if (status != NXGE_OK) 1986 return (EINVAL); 1987 } 1988 1989 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_grp_rdc")); 1990 return (0); 1991 } 1992 1993 /* ARGSUSED */ 1994 static int 1995 nxge_param_set_port_rdc(p_nxge_t nxgep, queue_t *q, 1996 mblk_t *mp, char *value, caddr_t cp) 1997 { 1998 char *end; 1999 uint32_t status = B_TRUE, cfg_value; 2000 p_nxge_param_t pa = (p_nxge_param_t)cp; 2001 uint32_t cfg_it = B_FALSE; 2002 2003 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2004 p_nxge_hw_pt_cfg_t p_cfgp; 2005 2006 2007 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_port_rdc")); 2008 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2009 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2010 2011 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 2012 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2013 return (EINVAL); 2014 } 2015 if (pa->value != cfg_value) { 2016 if (cfg_value >= p_cfgp->max_rdcs) 2017 return (EINVAL); 2018 pa->old_value = pa->value; 2019 pa->value = cfg_value; 2020 cfg_it = B_TRUE; 2021 } 2022 2023 if (cfg_it == B_TRUE) { 2024 status = nxge_rxdma_cfg_port_default_rdc(nxgep, 2025 nxgep->function_num, 2026 nxgep->rdc[cfg_value]); 2027 if (status != NXGE_OK) 2028 return (EINVAL); 2029 } 2030 2031 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_port_rdc")); 2032 return (0); 2033 } 2034 2035 2036 2037 /* ARGSUSED */ 2038 2039 static int 2040 nxge_param_set_nxge_debug_flag(p_nxge_t nxgep, queue_t *q, 2041 mblk_t *mp, char *value, caddr_t cp) 2042 { 2043 char *end; 2044 uint32_t status = 0; 2045 uint64_t cfg_value = 0; 2046 p_nxge_param_t pa = (p_nxge_param_t)cp; 2047 uint32_t cfg_it = B_FALSE; 2048 2049 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_nxge_debug_flag")); 2050 cfg_value = mi_strtol(value, &end, BASE_HEX); 2051 2052 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2053 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2054 " nxge_param_set_nxge_debug_flag" 2055 " outof range %llx", cfg_value)); 2056 return (EINVAL); 2057 } 2058 if (pa->value != cfg_value) { 2059 pa->old_value = pa->value; 2060 pa->value = cfg_value; 2061 cfg_it = B_TRUE; 2062 } 2063 2064 if (cfg_it == B_TRUE) { 2065 nxgep->nxge_debug_level = pa->value; 2066 } 2067 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_nxge_debug_flag")); 2068 return (status); 2069 } 2070 2071 2072 /* ARGSUSED */ 2073 static int 2074 nxge_param_get_debug_flag(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2075 { 2076 2077 int status = 0; 2078 p_nxge_param_t pa = (p_nxge_param_t)cp; 2079 2080 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_debug_flag")); 2081 2082 if (pa->value > 0xffffffff) 2083 (void) mi_mpprintf(mp, "%x%x", (int)(pa->value >> 32), 2084 (int)(pa->value & 0xffffffff)); 2085 else 2086 (void) mi_mpprintf(mp, "%x", (int)pa->value); 2087 2088 2089 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_debug_flag")); 2090 return (status); 2091 } 2092 2093 /* ARGSUSED */ 2094 2095 static int 2096 nxge_param_set_npi_debug_flag(p_nxge_t nxgep, queue_t *q, 2097 mblk_t *mp, char *value, caddr_t cp) 2098 { 2099 char *end; 2100 uint32_t status = 0; 2101 uint64_t cfg_value = 0; 2102 p_nxge_param_t pa; 2103 uint32_t cfg_it = B_FALSE; 2104 2105 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_npi_debug_flag")); 2106 cfg_value = mi_strtol(value, &end, BASE_HEX); 2107 pa = (p_nxge_param_t)cp; 2108 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2109 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_npi_debug_flag" 2110 " outof range %llx", cfg_value)); 2111 return (EINVAL); 2112 } 2113 if (pa->value != cfg_value) { 2114 pa->old_value = pa->value; 2115 pa->value = cfg_value; 2116 cfg_it = B_TRUE; 2117 } 2118 2119 if (cfg_it == B_TRUE) { 2120 npi_debug_level = pa->value; 2121 } 2122 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_debug_flag")); 2123 return (status); 2124 } 2125 2126 2127 /* ARGSUSED */ 2128 2129 2130 2131 /* ARGSUSED */ 2132 static int 2133 nxge_param_dump_rdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2134 { 2135 2136 uint_t rdc; 2137 2138 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_rdc")); 2139 2140 (void) npi_rxdma_dump_fzc_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2141 2142 for (rdc = 0; rdc < nxgep->nrdc; rdc++) 2143 (void) nxge_dump_rxdma_channel(nxgep, nxgep->rdc[rdc]); 2144 2145 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_rdc")); 2146 return (0); 2147 } 2148 2149 /* ARGSUSED */ 2150 static int 2151 nxge_param_dump_tdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2152 { 2153 2154 uint_t tdc; 2155 2156 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_tdc")); 2157 2158 for (tdc = 0; tdc < nxgep->ntdc; tdc++) 2159 (void) nxge_txdma_regs_dump(nxgep, nxgep->tdc[tdc]); 2160 2161 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_tdc")); 2162 return (0); 2163 } 2164 2165 2166 /* ARGSUSED */ 2167 static int 2168 nxge_param_dump_fflp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2169 { 2170 2171 2172 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_fflp_regs")); 2173 2174 (void) npi_fflp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2175 2176 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_fflp_regs")); 2177 return (0); 2178 } 2179 2180 /* ARGSUSED */ 2181 static int 2182 nxge_param_dump_mac_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2183 { 2184 2185 2186 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_mac_regs")); 2187 2188 (void) npi_mac_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2189 nxgep->function_num); 2190 2191 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_mac_regs")); 2192 return (0); 2193 } 2194 2195 /* ARGSUSED */ 2196 static int 2197 nxge_param_dump_ipp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2198 { 2199 2200 2201 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_ipp_regs")); 2202 2203 (void) (void) npi_ipp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2204 nxgep->function_num); 2205 2206 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ipp_regs")); 2207 return (0); 2208 } 2209 2210 /* ARGSUSED */ 2211 static int 2212 nxge_param_dump_vlan_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2213 { 2214 2215 2216 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_vlan_table")); 2217 2218 (void) npi_fflp_vlan_tbl_dump(NXGE_DEV_NPI_HANDLE(nxgep)); 2219 2220 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_vlan_table")); 2221 return (0); 2222 } 2223 2224 /* ARGSUSED */ 2225 static int 2226 nxge_param_dump_rdc_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2227 { 2228 2229 uint8_t table; 2230 2231 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_rdc_table")); 2232 for (table = 0; table < NXGE_MAX_RDC_GROUPS; table++) { 2233 (void) npi_rxdma_dump_rdc_table(NXGE_DEV_NPI_HANDLE(nxgep), 2234 table); 2235 } 2236 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_rdc_table")); 2237 return (0); 2238 } 2239 2240 2241 typedef struct block_info { 2242 char *name; 2243 uint32_t offset; 2244 } block_info_t; 2245 2246 block_info_t reg_block[] = { 2247 {"PIO", PIO}, 2248 {"FZC_PIO", FZC_PIO}, 2249 {"FZC_XMAC", FZC_MAC}, 2250 {"FZC_IPP", FZC_IPP}, 2251 {"FFLP", FFLP}, 2252 {"FZC_FFLP", FZC_FFLP}, 2253 {"PIO_VADDR", PIO_VADDR}, 2254 {"ZCP", ZCP}, 2255 {"FZC_ZCP", FZC_ZCP}, 2256 {"DMC", DMC}, 2257 {"FZC_DMC", FZC_DMC}, 2258 {"TXC", TXC}, 2259 {"FZC_TXC", FZC_TXC}, 2260 {"PIO_LDSV", PIO_LDSV}, 2261 {"PIO_LDGIM", PIO_LDGIM}, 2262 {"PIO_IMASK0", PIO_IMASK0}, 2263 {"PIO_IMASK1", PIO_IMASK1}, 2264 {"FZC_PROM", FZC_PROM}, 2265 {"END", ALL_FF_32}, 2266 }; 2267 2268 /* ARGSUSED */ 2269 static int 2270 nxge_param_dump_ptrs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2271 { 2272 2273 uint_t print_len, buf_len; 2274 p_mblk_t np; 2275 int rdc, tdc, block; 2276 uint64_t base; 2277 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2278 p_nxge_hw_pt_cfg_t p_cfgp; 2279 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_8K; 2280 p_tx_ring_t *tx_rings; 2281 p_rx_rcr_rings_t rx_rcr_rings; 2282 p_rx_rcr_ring_t *rcr_rings; 2283 p_rx_rbr_rings_t rx_rbr_rings; 2284 p_rx_rbr_ring_t *rbr_rings; 2285 2286 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_ptrs")); 2287 2288 (void) mi_mpprintf(mp, 2289 "ptr information for Port\t %d \n", 2290 nxgep->function_num); 2291 2292 2293 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 2294 /* The following may work even if we cannot get a large buf. */ 2295 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 2296 return (0); 2297 } 2298 2299 buf_len = buff_alloc_size; 2300 2301 mp->b_cont = np; 2302 2303 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2304 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2305 2306 rx_rcr_rings = nxgep->rx_rcr_rings; 2307 rcr_rings = rx_rcr_rings->rcr_rings; 2308 rx_rbr_rings = nxgep->rx_rbr_rings; 2309 rbr_rings = rx_rbr_rings->rbr_rings; 2310 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2311 "nxgep (nxge_t) $%p\n" 2312 "dev_regs (dev_regs_t) $%p\n", 2313 nxgep, nxgep->dev_regs); 2314 2315 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2316 /* do register pointers */ 2317 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2318 "reg base (npi_reg_ptr_t) $%p\t " 2319 "pci reg (npi_reg_ptr_t) $%p\n", 2320 nxgep->dev_regs->nxge_regp, 2321 nxgep->dev_regs->nxge_pciregp); 2322 2323 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2324 2325 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2326 "\nBlock \t Offset \n"); 2327 2328 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2329 block = 0; 2330 base = (uint64_t)nxgep->dev_regs->nxge_regp; 2331 while (reg_block[block].offset != ALL_FF_32) { 2332 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2333 "%9s\t 0x%llx\n", 2334 reg_block[block].name, 2335 (unsigned long long)(reg_block[block].offset + 2336 base)); 2337 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2338 block++; 2339 } 2340 2341 2342 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2343 "\nRDC\t rcrp (rx_rcr_ring_t)\t " 2344 "rbrp (rx_rbr_ring_t)\n"); 2345 2346 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2347 2348 for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 2349 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2350 " %d\t $%p\t\t $%p\n", 2351 rdc, rcr_rings[rdc], 2352 rbr_rings[rdc]); 2353 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2354 } 2355 2356 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2357 "\nTDC\t tdcp (tx_ring_t)\n"); 2358 2359 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2360 tx_rings = nxgep->tx_rings->rings; 2361 for (tdc = 0; tdc < p_cfgp->max_tdcs; tdc++) { 2362 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2363 " %d\t $%p\n", 2364 tdc, tx_rings[tdc]); 2365 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2366 } 2367 2368 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2369 "\n\n"); 2370 2371 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2372 2373 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ptrs")); 2374 return (0); 2375 } 2376 2377 2378 2379 /* 2380 * Load 'name' into the named dispatch table pointed to by 'ndp'. 2381 * 'ndp' should be the address of a char pointer cell. If the table 2382 * does not exist (*ndp == 0), a new table is allocated and 'ndp' 2383 * is stuffed. If there is not enough space in the table for a new 2384 * entry, more space is allocated. 2385 */ 2386 boolean_t 2387 nxge_nd_load(caddr_t *pparam, char *name, 2388 pfi_t get_pfi, pfi_t set_pfi, caddr_t data) 2389 { 2390 ND *nd; 2391 NDE *nde; 2392 2393 NXGE_DEBUG_MSG((NULL, NDD2_CTL, " ==> nxge_nd_load")); 2394 if (!pparam) 2395 return (B_FALSE); 2396 if ((nd = (ND *)*pparam) == NULL) { 2397 if ((nd = (ND *)KMEM_ZALLOC(sizeof (ND), KM_NOSLEEP)) 2398 == NULL) 2399 return (B_FALSE); 2400 *pparam = (caddr_t)nd; 2401 } 2402 if (nd->nd_tbl) { 2403 for (nde = nd->nd_tbl; nde->nde_name; nde++) { 2404 if (strcmp(name, nde->nde_name) == 0) 2405 goto fill_it; 2406 } 2407 } 2408 if (nd->nd_free_count <= 1) { 2409 if ((nde = (NDE *)KMEM_ZALLOC(nd->nd_size + 2410 NDE_ALLOC_SIZE, KM_NOSLEEP)) == NULL) 2411 return (B_FALSE); 2412 nd->nd_free_count += NDE_ALLOC_COUNT; 2413 if (nd->nd_tbl) { 2414 bcopy((char *)nd->nd_tbl, (char *)nde, nd->nd_size); 2415 KMEM_FREE((char *)nd->nd_tbl, nd->nd_size); 2416 } else { 2417 nd->nd_free_count--; 2418 nde->nde_name = "?"; 2419 nde->nde_get_pfi = nxge_nd_get_names; 2420 nde->nde_set_pfi = nxge_set_default; 2421 } 2422 nde->nde_data = (caddr_t)nd; 2423 nd->nd_tbl = nde; 2424 nd->nd_size += NDE_ALLOC_SIZE; 2425 } 2426 for (nde = nd->nd_tbl; nde->nde_name; nde++) 2427 noop; 2428 nd->nd_free_count--; 2429 fill_it: 2430 nde->nde_name = name; 2431 nde->nde_get_pfi = get_pfi; 2432 nde->nde_set_pfi = set_pfi; 2433 nde->nde_data = data; 2434 NXGE_DEBUG_MSG((NULL, NDD2_CTL, " <== nxge_nd_load")); 2435 2436 return (B_TRUE); 2437 } 2438 2439 /* 2440 * Free the table pointed to by 'pparam' 2441 */ 2442 void 2443 nxge_nd_free(caddr_t *pparam) 2444 { 2445 ND *nd; 2446 2447 if ((nd = (ND *)*pparam) != NULL) { 2448 if (nd->nd_tbl) 2449 KMEM_FREE((char *)nd->nd_tbl, nd->nd_size); 2450 KMEM_FREE((char *)nd, sizeof (ND)); 2451 *pparam = nil(caddr_t); 2452 } 2453 } 2454 2455 int 2456 nxge_nd_getset(p_nxge_t nxgep, queue_t *q, caddr_t param, p_mblk_t mp) 2457 { 2458 int err; 2459 IOCP iocp; 2460 p_mblk_t mp1, mp2; 2461 ND *nd; 2462 NDE *nde; 2463 char *valp; 2464 size_t avail; 2465 2466 if (!param) { 2467 return (B_FALSE); 2468 } 2469 nd = (ND *)param; 2470 iocp = (IOCP)mp->b_rptr; 2471 if ((iocp->ioc_count == 0) || !(mp1 = mp->b_cont)) { 2472 mp->b_datap->db_type = M_IOCACK; 2473 iocp->ioc_count = 0; 2474 iocp->ioc_error = EINVAL; 2475 return (B_FALSE); 2476 } 2477 /* 2478 * NOTE - logic throughout nd_xxx assumes single data block for ioctl. 2479 * However, existing code sends in some big buffers. 2480 */ 2481 avail = iocp->ioc_count; 2482 if (mp1->b_cont) { 2483 freemsg(mp1->b_cont); 2484 mp1->b_cont = NULL; 2485 } 2486 2487 mp1->b_datap->db_lim[-1] = '\0'; /* Force null termination */ 2488 for (valp = (char *)mp1->b_rptr; *valp != '\0'; valp++) { 2489 if (*valp == '-') 2490 *valp = '_'; 2491 } 2492 2493 valp = (char *)mp1->b_rptr; 2494 2495 for (nde = nd->nd_tbl; /* */; nde++) { 2496 if (!nde->nde_name) 2497 return (B_FALSE); 2498 if (strcmp(nde->nde_name, valp) == 0) 2499 break; 2500 } 2501 err = EINVAL; 2502 while (*valp++) 2503 noop; 2504 if (!*valp || valp >= (char *)mp1->b_wptr) 2505 valp = nilp(char); 2506 switch (iocp->ioc_cmd) { 2507 case ND_GET: 2508 /* 2509 * (temporary) hack: "*valp" is size of user buffer for 2510 * copyout. If result of action routine is too big, free 2511 * excess and return ioc_rval as buffer size needed. 2512 * Return as many mblocks as will fit, free the rest. For 2513 * backward compatibility, assume size of original ioctl 2514 * buffer if "*valp" bad or not given. 2515 */ 2516 if (valp) 2517 avail = mi_strtol(valp, (char **)0, 10); 2518 /* 2519 * We overwrite the name/value with the reply data 2520 */ 2521 mp2 = mp1; 2522 while (mp2) { 2523 mp2->b_wptr = mp2->b_rptr; 2524 mp2 = mp2->b_cont; 2525 } 2526 2527 err = (*nde->nde_get_pfi)(nxgep, q, mp1, nde->nde_data); 2528 2529 if (!err) { 2530 size_t size_out = 0; 2531 size_t excess; 2532 2533 iocp->ioc_rval = 0; 2534 2535 /* Tack on the null */ 2536 err = nxge_mk_mblk_tail_space(mp1, &mp2, 1); 2537 if (!err) { 2538 *mp2->b_wptr++ = '\0'; 2539 size_out = msgdsize(mp1); 2540 excess = size_out - avail; 2541 if (excess > 0) { 2542 iocp->ioc_rval = (int)size_out; 2543 size_out -= excess; 2544 (void) adjmsg(mp1, -(excess + 1)); 2545 err = nxge_mk_mblk_tail_space( 2546 mp1, &mp2, 1); 2547 if (!err) 2548 *mp2->b_wptr++ = '\0'; 2549 else 2550 size_out = 0; 2551 } 2552 } else 2553 size_out = 0; 2554 iocp->ioc_count = size_out; 2555 } 2556 break; 2557 2558 case ND_SET: 2559 if (valp) { 2560 if (nde->nde_set_pfi) { 2561 err = (*nde->nde_set_pfi)(nxgep, q, mp1, valp, 2562 nde->nde_data); 2563 iocp->ioc_count = 0; 2564 freemsg(mp1); 2565 mp->b_cont = NULL; 2566 } 2567 } 2568 break; 2569 2570 default: 2571 break; 2572 } 2573 iocp->ioc_error = err; 2574 mp->b_datap->db_type = M_IOCACK; 2575 return (B_TRUE); 2576 } 2577 2578 /* ARGSUSED */ 2579 int 2580 nxge_nd_get_names(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t param) 2581 { 2582 ND *nd; 2583 NDE *nde; 2584 char *rwtag; 2585 boolean_t get_ok, set_ok; 2586 size_t param_len; 2587 int status = 0; 2588 2589 nd = (ND *)param; 2590 if (!nd) 2591 return (ENOENT); 2592 2593 for (nde = nd->nd_tbl; nde->nde_name; nde++) { 2594 get_ok = (nde->nde_get_pfi != nxge_get_default) && 2595 (nde->nde_get_pfi != NULL); 2596 set_ok = (nde->nde_set_pfi != nxge_set_default) && 2597 (nde->nde_set_pfi != NULL); 2598 if (get_ok) { 2599 if (set_ok) 2600 rwtag = "read and write"; 2601 else 2602 rwtag = "read only"; 2603 } else if (set_ok) 2604 rwtag = "write only"; 2605 else { 2606 continue; 2607 } 2608 param_len = strlen(rwtag); 2609 param_len += strlen(nde->nde_name); 2610 param_len += 4; 2611 2612 (void) mi_mpprintf(mp, "%s (%s)", nde->nde_name, rwtag); 2613 } 2614 return (status); 2615 } 2616 2617 /* ARGSUSED */ 2618 int 2619 nxge_get_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t data) 2620 2621 { 2622 return (EACCES); 2623 } 2624 2625 /* ARGSUSED */ 2626 int 2627 2628 nxge_set_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, char *value, 2629 caddr_t data) 2630 2631 { 2632 return (EACCES); 2633 } 2634 2635 2636 void 2637 nxge_param_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 2638 { 2639 int cmd; 2640 int status = B_FALSE; 2641 2642 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_ioctl")); 2643 cmd = iocp->ioc_cmd; 2644 switch (cmd) { 2645 default: 2646 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2647 "nxge_param_ioctl: bad cmd 0x%0x", cmd)); 2648 break; 2649 2650 case ND_GET: 2651 case ND_SET: 2652 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2653 "nxge_param_ioctl: cmd 0x%0x", cmd)); 2654 if (!nxge_nd_getset(nxgep, wq, nxgep->param_list, mp)) { 2655 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2656 "false ret from nxge_nd_getset")); 2657 break; 2658 } 2659 status = B_TRUE; 2660 break; 2661 } 2662 2663 if (status) { 2664 qreply(wq, mp); 2665 } else { 2666 miocnak(wq, mp, 0, EINVAL); 2667 } 2668 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_ioctl")); 2669 } 2670 2671 /* ARGSUSED */ 2672 static boolean_t 2673 nxge_param_link_update(p_nxge_t nxgep) 2674 { 2675 p_nxge_param_t param_arr; 2676 nxge_param_index_t i; 2677 boolean_t update_xcvr; 2678 boolean_t update_dev; 2679 int instance; 2680 boolean_t status = B_TRUE; 2681 2682 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_link_update")); 2683 2684 param_arr = nxgep->param_arr; 2685 instance = nxgep->instance; 2686 update_xcvr = B_FALSE; 2687 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) { 2688 update_xcvr |= param_arr[i].value; 2689 } 2690 2691 if (update_xcvr) { 2692 update_xcvr = B_FALSE; 2693 for (i = param_autoneg; i < param_enable_ipg0; i++) { 2694 update_xcvr |= 2695 (param_arr[i].value != param_arr[i].old_value); 2696 param_arr[i].old_value = param_arr[i].value; 2697 } 2698 if (update_xcvr) { 2699 RW_ENTER_WRITER(&nxgep->filter_lock); 2700 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 2701 (void) nxge_link_init(nxgep); 2702 (void) nxge_mac_init(nxgep); 2703 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 2704 RW_EXIT(&nxgep->filter_lock); 2705 } 2706 } else { 2707 cmn_err(CE_WARN, " Last setting will leave nxge%d with " 2708 " no link capabilities.", instance); 2709 cmn_err(CE_WARN, " Restoring previous setting."); 2710 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) 2711 param_arr[i].value = param_arr[i].old_value; 2712 2713 } 2714 update_dev = B_FALSE; 2715 2716 if (update_dev) { 2717 RW_ENTER_WRITER(&nxgep->filter_lock); 2718 (void) nxge_rx_mac_disable(nxgep); 2719 (void) nxge_tx_mac_disable(nxgep); 2720 (void) nxge_set_dev_params(nxgep); 2721 2722 (void) nxge_tx_mac_enable(nxgep); 2723 (void) nxge_rx_mac_enable(nxgep); 2724 RW_EXIT(&nxgep->filter_lock); 2725 } 2726 2727 nxge_param_hw_update_exit: 2728 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2729 "<== nxge_param_link_update status = 0x%08x", status)); 2730 return (status); 2731 } 2732 2733 2734 2735 /* ARGSUSED */ 2736 static void 2737 nxge_set_dev_params(p_nxge_t nxgep) 2738 { 2739 2740 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_set_dev_params")); 2741 2742 /* Reinitialize any instance specific parameters. */ 2743 2744 } 2745