xref: /illumos-gate/usr/src/uts/common/io/nxge/nxge_mac.c (revision 86ef0a63)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
23  */
24 
25 #include <sys/nxge/nxge_impl.h>
26 #include <sys/nxge/nxge_mac.h>
27 #include <sys/nxge/nxge_hio.h>
28 
29 #define	LINK_MONITOR_PERIOD	(1000 * 1000)
30 #define	LM_WAIT_MULTIPLIER	8
31 
32 #define	SERDES_RDY_WT_INTERVAL	50
33 #define	MAX_SERDES_RDY_RETRIES	10
34 
35 #define	TN1010_SPEED_1G		1
36 #define	TN1010_SPEED_10G	0
37 #define	TN1010_AN_IN_PROG	0	/* Auto negotiation in progress */
38 #define	TN1010_AN_COMPLETE	1
39 #define	TN1010_AN_RSVD		2
40 #define	TN1010_AN_FAILED	3
41 
42 extern uint32_t nxge_no_link_notify;
43 extern boolean_t nxge_no_msg;
44 extern uint32_t nxge_lb_dbg;
45 extern uint32_t nxge_jumbo_mtu;
46 
47 typedef enum {
48 	CHECK_LINK_RESCHEDULE,
49 	CHECK_LINK_STOP
50 } check_link_state_t;
51 
52 static check_link_state_t nxge_check_link_stop(nxge_t *);
53 
54 /*
55  * Ethernet broadcast address definition.
56  */
57 static ether_addr_st etherbroadcastaddr =
58 				{{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
59 /*
60  * Ethernet zero address definition.
61  */
62 static ether_addr_st etherzeroaddr =
63 				{{0x0, 0x0, 0x0, 0x0, 0x0, 0x0}};
64 /*
65  * Supported chip types
66  */
67 static uint32_t nxge_supported_cl45_ids[] = {
68 	BCM8704_DEV_ID,
69 	MARVELL_88X_201X_DEV_ID,
70 	BCM8706_DEV_ID,
71 	TN1010_DEV_ID
72 };
73 
74 static uint32_t nxge_supported_cl22_ids[] = {
75     BCM5464R_PHY_ID,
76     BCM5482_PHY_ID
77 };
78 
79 #define	NUM_CLAUSE_45_IDS	(sizeof (nxge_supported_cl45_ids) /	\
80 				sizeof (uint32_t))
81 #define	NUM_CLAUSE_22_IDS	(sizeof (nxge_supported_cl22_ids) /	\
82 				sizeof (uint32_t))
83 /*
84  * static functions
85  */
86 static uint32_t nxge_get_cl45_pma_pmd_id(p_nxge_t, int);
87 static uint32_t nxge_get_cl45_pcs_id(p_nxge_t, int);
88 static uint32_t nxge_get_cl22_phy_id(p_nxge_t, int);
89 static boolean_t nxge_is_supported_phy(uint32_t, uint8_t);
90 static boolean_t nxge_hswap_phy_present(p_nxge_t, uint8_t);
91 static boolean_t nxge_is_phy_present(p_nxge_t, int, uint32_t, uint32_t);
92 static nxge_status_t nxge_n2_serdes_init(p_nxge_t);
93 static nxge_status_t nxge_n2_kt_serdes_init(p_nxge_t);
94 static nxge_status_t nxge_neptune_10G_serdes_init(p_nxge_t);
95 static nxge_status_t nxge_1G_serdes_init(p_nxge_t);
96 static nxge_status_t nxge_10G_link_intr_stop(p_nxge_t);
97 static nxge_status_t nxge_10G_link_intr_start(p_nxge_t);
98 static nxge_status_t nxge_1G_copper_link_intr_stop(p_nxge_t);
99 static nxge_status_t nxge_1G_copper_link_intr_start(p_nxge_t);
100 static nxge_status_t nxge_1G_fiber_link_intr_stop(p_nxge_t);
101 static nxge_status_t nxge_1G_fiber_link_intr_start(p_nxge_t);
102 static nxge_status_t nxge_check_mii_link(p_nxge_t);
103 static nxge_status_t nxge_check_10g_link(p_nxge_t);
104 static nxge_status_t nxge_10G_xcvr_init(p_nxge_t);
105 static nxge_status_t nxge_BCM8704_xcvr_init(p_nxge_t);
106 static nxge_status_t nxge_BCM8706_xcvr_init(p_nxge_t);
107 static nxge_status_t nxge_1G_xcvr_init(p_nxge_t);
108 static void nxge_bcm5464_link_led_off(p_nxge_t);
109 static nxge_status_t nxge_check_mrvl88x2011_link(p_nxge_t, boolean_t *);
110 static nxge_status_t nxge_mrvl88x2011_xcvr_init(p_nxge_t);
111 static nxge_status_t nxge_check_nlp2020_link(p_nxge_t, boolean_t *);
112 static nxge_status_t nxge_nlp2020_xcvr_init(p_nxge_t);
113 static int nxge_nlp2020_i2c_read(p_nxge_t, uint8_t, uint16_t, uint16_t,
114 	    uint8_t *);
115 static boolean_t nxge_is_nlp2020_phy(p_nxge_t);
116 static uint8_t nxge_get_nlp2020_connector_type(p_nxge_t);
117 static nxge_status_t nxge_set_nlp2020_param(p_nxge_t);
118 static nxge_status_t nxge_get_num_of_xaui(uint32_t *port_pma_pmd_dev_id,
119 	uint32_t *port_pcs_dev_id, uint32_t *port_phy_id, uint8_t *num_xaui);
120 static nxge_status_t nxge_get_tn1010_speed(p_nxge_t nxgep, uint16_t *speed);
121 static nxge_status_t nxge_set_tn1010_param(p_nxge_t nxgep);
122 static nxge_status_t nxge_tn1010_check(p_nxge_t nxgep,
123 	nxge_link_state_t *link_up);
124 static boolean_t nxge_is_tn1010_phy(p_nxge_t nxgep);
125 static nxge_status_t nxge_tn1010_xcvr_init(p_nxge_t nxgep);
126 
127 nxge_status_t nxge_mac_init(p_nxge_t);
128 static nxge_status_t nxge_mii_get_link_mode(p_nxge_t);
129 
130 #ifdef NXGE_DEBUG
131 static void nxge_mii_dump(p_nxge_t);
132 static nxge_status_t nxge_tn1010_reset(p_nxge_t nxgep);
133 static void nxge_dump_tn1010_status_regs(p_nxge_t nxgep);
134 #endif
135 
136 /*
137  * xcvr tables for supported transceivers
138  */
139 
140 /*
141  * nxge_n2_10G_table is for 10G fiber or serdes on N2-NIU systems.
142  * The Teranetics TN1010 based copper XAUI card can also be used
143  * on N2-NIU systems in 10G mode, but it uses its own table
144  * nxge_n2_10G_tn1010_table below.
145  */
146 static nxge_xcvr_table_t nxge_n2_10G_table = {
147 	nxge_n2_serdes_init,
148 	nxge_10G_xcvr_init,
149 	nxge_10G_link_intr_stop,
150 	nxge_10G_link_intr_start,
151 	nxge_check_10g_link,
152 	PCS_XCVR
153 };
154 
155 /*
156  * For the Teranetics TN1010 based copper XAUI card
157  */
158 static nxge_xcvr_table_t nxge_n2_10G_tn1010_table = {
159 	nxge_n2_serdes_init,		/* Handle both 1G and 10G */
160 	nxge_tn1010_xcvr_init,		/* Handle both 1G and 10G */
161 	nxge_10G_link_intr_stop,
162 	nxge_10G_link_intr_start,
163 	nxge_check_tn1010_link,		/* Will figure out speed */
164 	XPCS_XCVR
165 };
166 
167 static nxge_xcvr_table_t nxge_n2_1G_table = {
168 	nxge_n2_serdes_init,
169 	nxge_1G_xcvr_init,
170 	nxge_1G_fiber_link_intr_stop,
171 	nxge_1G_fiber_link_intr_start,
172 	nxge_check_mii_link,
173 	PCS_XCVR
174 };
175 
176 static nxge_xcvr_table_t nxge_n2_1G_tn1010_table = {
177 	nxge_n2_serdes_init,
178 	nxge_tn1010_xcvr_init,
179 	nxge_1G_fiber_link_intr_stop,	/* TN1010 is a Cu PHY, but it uses */
180 	nxge_1G_fiber_link_intr_start,	/* PCS for 1G, so call fiber func */
181 	nxge_check_tn1010_link,
182 	PCS_XCVR
183 };
184 
185 static nxge_xcvr_table_t nxge_10G_tn1010_table = {
186 	nxge_neptune_10G_serdes_init,
187 	nxge_tn1010_xcvr_init,
188 	nxge_10G_link_intr_stop,
189 	nxge_10G_link_intr_start,
190 	nxge_check_tn1010_link,
191 	XPCS_XCVR
192 };
193 
194 static nxge_xcvr_table_t nxge_1G_tn1010_table = {
195 	nxge_1G_serdes_init,
196 	nxge_tn1010_xcvr_init,
197 	nxge_1G_fiber_link_intr_stop,
198 	nxge_1G_fiber_link_intr_start,
199 	nxge_check_tn1010_link,
200 	PCS_XCVR
201 };
202 
203 static nxge_xcvr_table_t nxge_10G_fiber_table = {
204 	nxge_neptune_10G_serdes_init,
205 	nxge_10G_xcvr_init,
206 	nxge_10G_link_intr_stop,
207 	nxge_10G_link_intr_start,
208 	nxge_check_10g_link,
209 	PCS_XCVR
210 };
211 
212 static nxge_xcvr_table_t nxge_1G_copper_table = {
213 	NULL,
214 	nxge_1G_xcvr_init,
215 	nxge_1G_copper_link_intr_stop,
216 	nxge_1G_copper_link_intr_start,
217 	nxge_check_mii_link,
218 	INT_MII_XCVR
219 };
220 
221 /* This table is for Neptune portmode == PORT_1G_SERDES cases */
222 static nxge_xcvr_table_t nxge_1G_fiber_table = {
223 	nxge_1G_serdes_init,
224 	nxge_1G_xcvr_init,
225 	nxge_1G_fiber_link_intr_stop,
226 	nxge_1G_fiber_link_intr_start,
227 	nxge_check_mii_link,
228 	PCS_XCVR
229 };
230 
231 static nxge_xcvr_table_t nxge_10G_copper_table = {
232 	nxge_neptune_10G_serdes_init,
233 	NULL,
234 	NULL,
235 	NULL,
236 	NULL,
237 	PCS_XCVR
238 };
239 
240 /*
241  * NXGE_PORT_TN1010 is defined as,
242  *      NXGE_PORT_SPD_NONE | (NXGE_PHY_TN1010 << NXGE_PHY_SHIFT)
243  *	= 0 | 5 << 16 = 0x50000
244  *
245  * So NEPTUNE_2_TN1010 =
246  *      (NXGE_PORT_TN1010 |
247  *      (NXGE_PORT_TN1010 << 4) |
248  *      (NXGE_PORT_NONE << 8) |
249  *      (NXGE_PORT_NONE << 12)),
250  *      = 0x50000 | (0x50000 << 4)
251  *	= 0x550000
252  *
253  * This function partitions nxgep->nxge_hw_p->niu_type (which may have
254  * value NEPTUNE_2_TN1010) and checks if a port has type = NXGE_PORT_TN1010
255  * = 0x50000
256  */
nxge_is_tn1010_phy(p_nxge_t nxgep)257 static boolean_t nxge_is_tn1010_phy(p_nxge_t nxgep)
258 {
259 	uint8_t	portn = NXGE_GET_PORT_NUM(nxgep->function_num);
260 
261 	if (((nxgep->nxge_hw_p->niu_type >> (NXGE_PORT_TYPE_SHIFT * portn))
262 	    & NXGE_PHY_MASK) == NXGE_PORT_TN1010) {
263 		return (B_TRUE);
264 	} else {
265 		return (B_FALSE);
266 	}
267 }
268 
269 
270 /*
271  * Figure out nxgep->mac.portmode from nxge.conf, OBP's device properties,
272  * serial EEPROM or VPD if possible.  Note that not all systems could get
273  * the portmode information by calling this function.  For example, the
274  * Maramba system figures out the portmode information by calling function
275  * nxge_setup_xcvr_table.
276  */
277 nxge_status_t
nxge_get_xcvr_type(p_nxge_t nxgep)278 nxge_get_xcvr_type(p_nxge_t nxgep)
279 {
280 	nxge_status_t status = NXGE_OK;
281 	char *phy_type;
282 	char *prop_val;
283 	uint8_t portn = NXGE_GET_PORT_NUM(nxgep->function_num);
284 	uint32_t	val;
285 	npi_status_t	rs;
286 
287 	/* For Opus NEM, skip xcvr checking if 10G Serdes link is up */
288 	if (nxgep->mac.portmode == PORT_10G_SERDES &&
289 	    nxgep->statsp->mac_stats.link_up) {
290 		nxgep->statsp->mac_stats.xcvr_inuse = XPCS_XCVR;
291 		return (status);
292 	}
293 
294 	nxgep->mac.portmode = 0;
295 	nxgep->xcvr_addr = 0;
296 
297 	/*
298 	 * First check for hot swappable phy property.
299 	 */
300 	if (nxgep->hot_swappable_phy == B_TRUE) {
301 		nxgep->statsp->mac_stats.xcvr_inuse = HSP_XCVR;
302 		nxgep->mac.portmode = PORT_HSP_MODE;
303 		NXGE_DEBUG_MSG((nxgep, MAC_CTL, "Other: Hot Swappable"));
304 	} else if (ddi_prop_exists(DDI_DEV_T_ANY, nxgep->dip,
305 	    DDI_PROP_DONTPASS | DDI_PROP_NOTPROM,
306 	    "hot-swappable-phy") == 1) {
307 		nxgep->statsp->mac_stats.xcvr_inuse = HSP_XCVR;
308 		nxgep->mac.portmode = PORT_HSP_MODE;
309 		NXGE_DEBUG_MSG((nxgep, MAC_CTL, ".conf: Hot Swappable"));
310 	} else if (nxgep->niu_type == N2_NIU &&
311 	    ddi_prop_exists(DDI_DEV_T_ANY, nxgep->dip, 0,
312 	    "hot-swappable-phy") == 1) {
313 		nxgep->statsp->mac_stats.xcvr_inuse = HSP_XCVR;
314 		nxgep->mac.portmode = PORT_HSP_MODE;
315 		NXGE_DEBUG_MSG((nxgep, MAC_CTL, "OBP: Hot Swappable"));
316 	}
317 
318 	/*
319 	 * MDIO polling support for Monza RTM card, Goa NEM card
320 	 */
321 	if (nxgep->mac.portmode == PORT_HSP_MODE) {
322 		nxgep->hot_swappable_phy = B_TRUE;
323 		if (portn > 1) {
324 			return (NXGE_ERROR);
325 		}
326 
327 		if (nxge_hswap_phy_present(nxgep, portn))
328 			goto found_phy;
329 
330 		nxgep->phy_absent = B_TRUE;
331 
332 		/* Check Serdes link to detect Opus NEM */
333 		rs = npi_xmac_xpcs_read(nxgep->npi_handle, nxgep->mac.portnum,
334 		    XPCS_REG_STATUS, &val);
335 
336 		if (rs == 0 && val & XPCS_STATUS_LANE_ALIGN) {
337 			nxgep->statsp->mac_stats.xcvr_inuse = XPCS_XCVR;
338 			nxgep->mac.portmode = PORT_10G_SERDES;
339 			NXGE_DEBUG_MSG((nxgep, MAC_CTL,
340 			    "HSP 10G Serdes FOUND!!"));
341 		}
342 		goto check_phy_done;
343 found_phy:
344 		nxgep->statsp->mac_stats.xcvr_inuse = XPCS_XCVR;
345 		nxgep->mac.portmode = PORT_10G_FIBER;
346 		nxgep->phy_absent = B_FALSE;
347 		NXGE_DEBUG_MSG((nxgep, MAC_CTL, "10G Fiber Xcvr "
348 		    "found for hot swappable phy"));
349 check_phy_done:
350 		return (status);
351 	}
352 
353 	/* Get phy-type property (May have been set by nxge.conf) */
354 	if ((ddi_prop_lookup_string(DDI_DEV_T_ANY, nxgep->dip,
355 	    DDI_PROP_DONTPASS | DDI_PROP_NOTPROM,
356 	    "phy-type", &prop_val)) == DDI_PROP_SUCCESS) {
357 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
358 		    "found  conf file: phy-type %s", prop_val));
359 		if (strcmp("xgsd", prop_val) == 0) {
360 			nxgep->statsp->mac_stats.xcvr_inuse = XPCS_XCVR;
361 			nxgep->mac.portmode = PORT_10G_SERDES;
362 			NXGE_DEBUG_MSG((nxgep, MAC_CTL,
363 			    "found: 10G Serdes"));
364 		} else if (strcmp("gsd", prop_val) == 0) {
365 			nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR;
366 			nxgep->mac.portmode = PORT_1G_SERDES;
367 			NXGE_DEBUG_MSG((nxgep, MAC_CTL, "1G Serdes"));
368 		} else if (strcmp("mif", prop_val) == 0) {
369 			nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR;
370 			nxgep->mac.portmode = PORT_1G_COPPER;
371 			NXGE_DEBUG_MSG((nxgep, MAC_CTL, "1G Copper Xcvr"));
372 		} else if (strcmp("pcs", prop_val) == 0) {
373 			nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR;
374 			nxgep->mac.portmode = PORT_1G_FIBER;
375 			NXGE_DEBUG_MSG((nxgep, MAC_CTL, "1G FIBER Xcvr"));
376 		} else if (strcmp("xgf", prop_val) == 0) {
377 			/*
378 			 * Before OBP supports new phy-type property
379 			 * value "xgc", the 10G copper XAUI may carry
380 			 * "xgf" instead of "xgc". If the OBP is
381 			 * upgraded to a newer version which supports
382 			 * "xgc", then the TN1010 related code in this
383 			 * "xgf" case will not be used anymore.
384 			 */
385 			if (nxge_is_tn1010_phy(nxgep)) {
386 				if ((status = nxge_set_tn1010_param(nxgep))
387 				    != NXGE_OK) {
388 					return (status);
389 				}
390 				NXGE_DEBUG_MSG((nxgep, MAC_CTL, "TN1010 Xcvr"));
391 			} else {  /* For Fiber XAUI */
392 				nxgep->statsp->mac_stats.xcvr_inuse = XPCS_XCVR;
393 				nxgep->mac.portmode = PORT_10G_FIBER;
394 				NXGE_DEBUG_MSG((nxgep, MAC_CTL,
395 				    "10G Fiber Xcvr"));
396 			}
397 		} else if (strcmp("xgc", prop_val) == 0) {
398 			if ((status = nxge_set_tn1010_param(nxgep)) != NXGE_OK)
399 				return (status);
400 			NXGE_DEBUG_MSG((nxgep, MAC_CTL, "TN1010 Xcvr"));
401 		}
402 
403 		(void) ddi_prop_update_string(DDI_DEV_T_NONE, nxgep->dip,
404 		    "phy-type", prop_val);
405 		ddi_prop_free(prop_val);
406 
407 		NXGE_DEBUG_MSG((nxgep, MAC_CTL, "nxge_get_xcvr_type: "
408 		    "Got phy type [0x%x] from conf file",
409 		    nxgep->mac.portmode));
410 
411 		return (NXGE_OK);
412 	}
413 
414 	/* Get phy-type property from OBP */
415 	if (nxgep->niu_type == N2_NIU) {
416 		if (ddi_prop_lookup_string(DDI_DEV_T_ANY, nxgep->dip, 0,
417 		    "phy-type", &prop_val) == DDI_PROP_SUCCESS) {
418 			if (strcmp("xgf", prop_val) == 0) {
419 				/*
420 				 * Before OBP supports new phy-type property
421 				 * value "xgc", the 10G copper XAUI may carry
422 				 * "xgf" instead of "xgc". If the OBP is
423 				 * upgraded to a newer version which supports
424 				 * "xgc", then the TN1010 related code in this
425 				 * "xgf" case will not be used anymore.
426 				 */
427 				if (nxge_is_tn1010_phy(nxgep)) {
428 					if ((status =
429 					    nxge_set_tn1010_param(nxgep))
430 					    != NXGE_OK) {
431 						return (status);
432 					}
433 					NXGE_DEBUG_MSG((nxgep, MAC_CTL,
434 					    "TN1010 Xcvr"));
435 				} else if (nxge_is_nlp2020_phy(nxgep)) {
436 					if ((status =
437 					    nxge_set_nlp2020_param(nxgep))
438 					    != NXGE_OK) {
439 						return (status);
440 					}
441 					NXGE_DEBUG_MSG((nxgep, MAC_CTL,
442 					    "NLP2020 Xcvr"));
443 				} else { /* For Fiber XAUI */
444 					nxgep->statsp->mac_stats.xcvr_inuse
445 					    = XPCS_XCVR;
446 					nxgep->mac.portmode = PORT_10G_FIBER;
447 					NXGE_DEBUG_MSG((nxgep, MAC_CTL,
448 					    "10G Fiber Xcvr"));
449 				}
450 			} else if (strcmp("mif", prop_val) == 0) {
451 				nxgep->statsp->mac_stats.xcvr_inuse =
452 				    INT_MII_XCVR;
453 				nxgep->mac.portmode = PORT_1G_COPPER;
454 				NXGE_DEBUG_MSG((nxgep, MAC_CTL,
455 				    "1G Copper Xcvr"));
456 			} else if (strcmp("pcs", prop_val) == 0) {
457 				nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR;
458 				nxgep->mac.portmode = PORT_1G_FIBER;
459 				NXGE_DEBUG_MSG((nxgep, MAC_CTL,
460 				    "1G Fiber Xcvr"));
461 			} else if (strcmp("xgc", prop_val) == 0) {
462 				status = nxge_set_tn1010_param(nxgep);
463 				if (status != NXGE_OK)
464 					return (status);
465 				NXGE_DEBUG_MSG((nxgep, MAC_CTL, "TN1010 Xcvr"));
466 			} else if (strcmp("xgsd", prop_val) == 0) {
467 				nxgep->statsp->mac_stats.xcvr_inuse = XPCS_XCVR;
468 				nxgep->mac.portmode = PORT_10G_SERDES;
469 				NXGE_DEBUG_MSG((nxgep, MAC_CTL,
470 				    "OBP: 10G Serdes"));
471 			} else if (strcmp("gsd", prop_val) == 0) {
472 				nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR;
473 				nxgep->mac.portmode = PORT_1G_SERDES;
474 				NXGE_DEBUG_MSG((nxgep, MAC_CTL,
475 				    "OBP: 1G Serdes"));
476 			} else {
477 				NXGE_DEBUG_MSG((nxgep, MAC_CTL,
478 				    "Unknown phy-type: %s", prop_val));
479 				ddi_prop_free(prop_val);
480 				return (NXGE_ERROR);
481 			}
482 			status = NXGE_OK;
483 			(void) ddi_prop_update_string(DDI_DEV_T_NONE,
484 			    nxgep->dip, "phy-type", prop_val);
485 			ddi_prop_free(prop_val);
486 
487 			NXGE_DEBUG_MSG((nxgep, MAC_CTL, "nxge_get_xcvr_type: "
488 			    "Got phy type [0x%x] from OBP",
489 			    nxgep->mac.portmode));
490 
491 			return (status);
492 		} else {
493 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
494 			    "Exiting...phy-type property not found"));
495 			return (NXGE_ERROR);
496 		}
497 	}
498 
499 
500 	if (!nxgep->vpd_info.present) {
501 		return (NXGE_OK);
502 	}
503 
504 	if (!nxgep->vpd_info.ver_valid) {
505 		goto read_seeprom;
506 	}
507 
508 	NXGE_DEBUG_MSG((nxgep, MAC_CTL,
509 	    "Reading phy type from expansion ROM"));
510 	/*
511 	 * Try to read the phy type from the vpd data read off the
512 	 * expansion ROM.
513 	 */
514 	phy_type = nxgep->vpd_info.phy_type;
515 
516 	if (strncmp(phy_type, "mif", 3) == 0) {
517 		nxgep->mac.portmode = PORT_1G_COPPER;
518 		nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR;
519 	} else if (strncmp(phy_type, "xgf", 3) == 0) {
520 		nxgep->mac.portmode = PORT_10G_FIBER;
521 		nxgep->statsp->mac_stats.xcvr_inuse = XPCS_XCVR;
522 	} else if (strncmp(phy_type, "pcs", 3) == 0) {
523 		nxgep->mac.portmode = PORT_1G_FIBER;
524 		nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR;
525 	} else if (strncmp(phy_type, "xgc", 3) == 0) {
526 		status = nxge_set_tn1010_param(nxgep);
527 		if (status != NXGE_OK) {
528 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
529 			    "nxge_get_xcvr_type: Failed to set TN1010 param"));
530 			goto read_seeprom;
531 		}
532 	} else if (strncmp(phy_type, "xgsd", 4) == 0) {
533 		nxgep->mac.portmode = PORT_10G_SERDES;
534 		nxgep->statsp->mac_stats.xcvr_inuse = XPCS_XCVR;
535 	} else if (strncmp(phy_type, "gsd", 3) == 0) {
536 		nxgep->mac.portmode = PORT_1G_SERDES;
537 		nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR;
538 	} else {
539 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
540 		    "nxge_get_xcvr_type: Unknown phy type [%c%c%c] in EEPROM",
541 		    phy_type[0], phy_type[1], phy_type[2]));
542 		goto read_seeprom;
543 	}
544 
545 	NXGE_DEBUG_MSG((nxgep, MAC_CTL, "nxge_get_xcvr_type: "
546 	    "Got phy type [0x%x] from VPD", nxgep->mac.portmode));
547 
548 	NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_get_xcvr_type"));
549 	return (status);
550 
551 read_seeprom:
552 	/*
553 	 * read the phy type from the SEEPROM - NCR registers
554 	 */
555 	status = nxge_espc_phy_type_get(nxgep);
556 	if (status != NXGE_OK) {
557 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
558 		    "Failed to get phy type"));
559 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "EEPROM version "
560 		    "[%s] invalid...please update", nxgep->vpd_info.ver));
561 	}
562 
563 	return (status);
564 
565 }
566 
567 /* Set up the PHY specific values. */
568 
569 nxge_status_t
nxge_setup_xcvr_table(p_nxge_t nxgep)570 nxge_setup_xcvr_table(p_nxge_t nxgep)
571 {
572 	nxge_status_t	status = NXGE_OK;
573 	uint32_t	port_type;
574 	uint8_t		portn = NXGE_GET_PORT_NUM(nxgep->function_num);
575 	uint32_t	pcs_id = 0;
576 	uint32_t	pma_pmd_id = 0;
577 	uint32_t	phy_id = 0;
578 	uint16_t	chip_id = 0;
579 
580 	NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_setup_xcvr_table: port<%d>",
581 	    portn));
582 
583 	switch (nxgep->niu_type) {
584 	case N2_NIU:
585 		switch (nxgep->mac.portmode) {
586 		case PORT_1G_FIBER:
587 		case PORT_1G_SERDES:
588 			nxgep->xcvr = nxge_n2_1G_table;
589 			nxgep->xcvr_addr = portn;
590 			NXGE_DEBUG_MSG((nxgep, MAC_CTL, "NIU 1G %s Xcvr",
591 			    (nxgep->mac.portmode == PORT_1G_FIBER) ? "Fiber" :
592 			    "Serdes"));
593 			break;
594 		case PORT_10G_FIBER:
595 		case PORT_10G_COPPER:
596 		case PORT_10G_SERDES:
597 			nxgep->xcvr = nxge_n2_10G_table;
598 			if (nxgep->nxge_hw_p->xcvr_addr[portn]) {
599 				nxgep->xcvr_addr =
600 				    nxgep->nxge_hw_p->xcvr_addr[portn];
601 			}
602 			NXGE_DEBUG_MSG((nxgep, MAC_CTL, "NIU 10G %s Xcvr",
603 			    (nxgep->mac.portmode == PORT_10G_FIBER) ? "Fiber" :
604 			    ((nxgep->mac.portmode == PORT_10G_COPPER) ?
605 			    "Copper" : "Serdes")));
606 			break;
607 		case PORT_1G_TN1010:
608 			nxgep->xcvr = nxge_n2_1G_tn1010_table;
609 			nxgep->xcvr_addr = nxgep->nxge_hw_p->xcvr_addr[portn];
610 			NXGE_DEBUG_MSG((nxgep, MAC_CTL,
611 			    "TN1010 Copper Xcvr in 1G"));
612 			break;
613 		case PORT_10G_TN1010:
614 			nxgep->xcvr = nxge_n2_10G_tn1010_table;
615 			nxgep->xcvr_addr = nxgep->nxge_hw_p->xcvr_addr[portn];
616 			NXGE_DEBUG_MSG((nxgep, MAC_CTL,
617 			    "TN1010 Copper Xcvr in 10G"));
618 			break;
619 		case PORT_HSP_MODE:
620 			nxgep->xcvr = nxge_n2_10G_table;
621 			nxgep->xcvr.xcvr_inuse = HSP_XCVR;
622 			NXGE_DEBUG_MSG((nxgep, MAC_CTL, "NIU 10G Hot "
623 			    "Swappable Xcvr (not present)"));
624 			break;
625 		default:
626 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
627 			    "<== nxge_setup_xcvr_table: "
628 			    "Unable to determine NIU portmode"));
629 			return (NXGE_ERROR);
630 		}
631 		break;
632 	default:
633 		if (nxgep->mac.portmode == 0) {
634 			/*
635 			 * Would be the case for platforms like Maramba
636 			 * in which the phy type could not be got from conf
637 			 * file, OBP, VPD or Serial PROM.
638 			 */
639 			if (!NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
640 				NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
641 				    "<== nxge_setup_xcvr_table:"
642 				    " Invalid Neptune type [0x%x]",
643 				    nxgep->niu_type));
644 				return (NXGE_ERROR);
645 			}
646 
647 			port_type = nxgep->niu_type >>
648 			    (NXGE_PORT_TYPE_SHIFT * portn);
649 			port_type = port_type & (NXGE_PORT_TYPE_MASK);
650 
651 			switch (port_type) {
652 
653 			case NXGE_PORT_1G_COPPER:
654 				nxgep->mac.portmode = PORT_1G_COPPER;
655 				break;
656 			case NXGE_PORT_10G_COPPER:
657 				nxgep->mac.portmode = PORT_10G_COPPER;
658 				break;
659 			case NXGE_PORT_1G_FIBRE:
660 				nxgep->mac.portmode = PORT_1G_FIBER;
661 				break;
662 			case NXGE_PORT_10G_FIBRE:
663 				nxgep->mac.portmode = PORT_10G_FIBER;
664 				break;
665 			case NXGE_PORT_1G_SERDES:
666 				nxgep->mac.portmode = PORT_1G_SERDES;
667 				break;
668 			case NXGE_PORT_10G_SERDES:
669 				nxgep->mac.portmode = PORT_10G_SERDES;
670 				break;
671 			/* Ports 2 and 3 of Alonso or ARTM */
672 			case NXGE_PORT_1G_RGMII_FIBER:
673 				nxgep->mac.portmode = PORT_1G_RGMII_FIBER;
674 				break;
675 			case NXGE_PORT_TN1010:
676 				/*
677 				 * If this port uses the TN1010 copper
678 				 * PHY, then its speed is not known yet
679 				 * because nxge_scan_ports_phy could only
680 				 * figure out the vendor of the PHY but
681 				 * not its speed. nxge_set_tn1010_param
682 				 * will read the PHY speed and set
683 				 * portmode accordingly.
684 				 */
685 				if ((status = nxge_set_tn1010_param(nxgep))
686 				    != NXGE_OK) {
687 					NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
688 					    "nxge_set_tn1010_param failed"));
689 					return (status);
690 				}
691 				break;
692 			default:
693 				NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
694 				    "<== nxge_setup_xcvr_table: "
695 				    "Unknown port-type: 0x%x", port_type));
696 				return (NXGE_ERROR);
697 			}
698 		}
699 
700 		/*
701 		 * Above switch has figured out nxge->mac.portmode, now set
702 		 * nxgep->xcvr (the table) and nxgep->xcvr_addr according
703 		 * to portmode.
704 		 */
705 		switch (nxgep->mac.portmode) {
706 		case PORT_1G_COPPER:
707 		case PORT_1G_RGMII_FIBER:
708 			nxgep->xcvr = nxge_1G_copper_table;
709 			nxgep->xcvr_addr = nxgep->nxge_hw_p->xcvr_addr[portn];
710 			/*
711 			 * For Altas 4-1G copper, Xcvr port numbers are
712 			 * swapped with ethernet port number. This is
713 			 * designed for better signal integrity in
714 			 * routing. This is also the case for the
715 			 * on-board Neptune copper ports on the Maramba
716 			 * platform.
717 			 */
718 			switch (nxgep->platform_type) {
719 			case P_NEPTUNE_ATLAS_4PORT:
720 			case P_NEPTUNE_MARAMBA_P0:
721 			case P_NEPTUNE_MARAMBA_P1:
722 				switch (portn) {
723 				case 0:
724 					nxgep->xcvr_addr += 3;
725 					break;
726 				case 1:
727 					nxgep->xcvr_addr += 1;
728 					break;
729 				case 2:
730 					nxgep->xcvr_addr -= 1;
731 					break;
732 				case 3:
733 					nxgep->xcvr_addr -= 3;
734 					break;
735 				default:
736 					return (NXGE_ERROR);
737 				}
738 				break;
739 			default:
740 				break;
741 			}
742 
743 			NXGE_DEBUG_MSG((nxgep, MAC_CTL, "1G %s Xcvr",
744 			    (nxgep->mac.portmode == PORT_1G_COPPER) ?
745 			    "Copper" : "RGMII Fiber"));
746 			break;
747 
748 		case PORT_10G_COPPER:
749 			nxgep->xcvr = nxge_10G_copper_table;
750 			NXGE_DEBUG_MSG((nxgep, MAC_CTL, "10G Copper Xcvr"));
751 			break;
752 
753 		case PORT_1G_TN1010:
754 			nxgep->xcvr = nxge_1G_tn1010_table;
755 			nxgep->xcvr_addr = nxgep->nxge_hw_p->xcvr_addr[portn];
756 			NXGE_DEBUG_MSG((nxgep, MAC_CTL,
757 			    "1G TN1010 copper Xcvr"));
758 			break;
759 
760 		case PORT_10G_TN1010:
761 			nxgep->xcvr = nxge_10G_tn1010_table;
762 			nxgep->xcvr_addr = nxgep->nxge_hw_p->xcvr_addr[portn];
763 			NXGE_DEBUG_MSG((nxgep, MAC_CTL,
764 			    "10G TN1010 copper Xcvr"));
765 			break;
766 
767 		case PORT_1G_FIBER:
768 		case PORT_1G_SERDES:
769 			nxgep->xcvr = nxge_1G_fiber_table;
770 			nxgep->xcvr_addr = portn;
771 			NXGE_DEBUG_MSG((nxgep, MAC_CTL, "1G %s Xcvr",
772 			    (nxgep->mac.portmode == PORT_1G_FIBER) ?
773 			    "Fiber" : "Serdes"));
774 			break;
775 		case PORT_10G_FIBER:
776 		case PORT_10G_SERDES:
777 			nxgep->xcvr = nxge_10G_fiber_table;
778 			NXGE_DEBUG_MSG((nxgep, MAC_CTL, "10G xcvr "
779 			    "nxgep->nxge_hw_p->xcvr_addr[portn] = [%d] "
780 			    "nxgep->xcvr_addr = [%d]",
781 			    nxgep->nxge_hw_p->xcvr_addr[portn],
782 			    nxgep->xcvr_addr));
783 			if (nxgep->nxge_hw_p->xcvr_addr[portn]) {
784 				nxgep->xcvr_addr =
785 				    nxgep->nxge_hw_p->xcvr_addr[portn];
786 			}
787 			switch (nxgep->platform_type) {
788 			case P_NEPTUNE_MARAMBA_P0:
789 			case P_NEPTUNE_MARAMBA_P1:
790 				/*
791 				 * Switch off LED for corresponding copper
792 				 * port
793 				 */
794 				nxge_bcm5464_link_led_off(nxgep);
795 				break;
796 			default:
797 				break;
798 			}
799 			NXGE_DEBUG_MSG((nxgep, MAC_CTL, "10G %s Xcvr",
800 			    (nxgep->mac.portmode == PORT_10G_FIBER) ?
801 			    "Fiber" : "Serdes"));
802 			break;
803 
804 		case PORT_HSP_MODE:
805 			nxgep->xcvr = nxge_10G_fiber_table;
806 			nxgep->xcvr.xcvr_inuse = HSP_XCVR;
807 			NXGE_DEBUG_MSG((nxgep, MAC_CTL, "Neptune 10G Hot "
808 			    "Swappable Xcvr (not present)"));
809 			break;
810 		default:
811 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
812 			    "Unknown port-type: 0x%x", port_type));
813 			return (NXGE_ERROR);
814 		}
815 	}
816 
817 	if (nxgep->mac.portmode == PORT_10G_FIBER ||
818 	    nxgep->mac.portmode == PORT_10G_COPPER) {
819 		uint32_t pma_pmd_id;
820 		pma_pmd_id = nxge_get_cl45_pma_pmd_id(nxgep,
821 		    nxgep->xcvr_addr);
822 		if ((pma_pmd_id & BCM_PHY_ID_MASK) == MARVELL_88X201X_PHY_ID) {
823 			chip_id = MRVL88X201X_CHIP_ID;
824 			NXGE_DEBUG_MSG((nxgep, MAC_CTL,
825 			    "nxge_setup_xcvr_table: "
826 			    "Chip ID  MARVELL [0x%x] for 10G xcvr", chip_id));
827 		} else if ((pma_pmd_id & NLP2020_DEV_ID_MASK) ==
828 		    NLP2020_DEV_ID) {
829 			chip_id = NLP2020_CHIP_ID;
830 			NXGE_DEBUG_MSG((nxgep, MAC_CTL,
831 			    "nxge_setup_xcvr_table: "
832 			    "Chip ID  AEL2020 [0x%x] for 10G xcvr", chip_id));
833 		} else if ((status = nxge_mdio_read(nxgep, nxgep->xcvr_addr,
834 		    BCM8704_PCS_DEV_ADDR, BCM8704_CHIP_ID_REG,
835 		    &chip_id)) == NXGE_OK) {
836 
837 			switch (chip_id) {
838 			case BCM8704_CHIP_ID:
839 				NXGE_DEBUG_MSG((nxgep, MAC_CTL,
840 				    "nxge_setup_xcvr_table: "
841 				    "Chip ID 8704 [0x%x] for 10G xcvr",
842 				    chip_id));
843 				break;
844 			case BCM8706_CHIP_ID:
845 				NXGE_DEBUG_MSG((nxgep, MAC_CTL,
846 				    "nxge_setup_xcvr_table: "
847 				    "Chip ID 8706 [0x%x] for 10G xcvr",
848 				    chip_id));
849 				break;
850 			default:
851 				NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
852 				    "nxge_setup_xcvr_table: "
853 				    "Unknown Chip ID [0x%x] for 10G xcvr",
854 				    chip_id));
855 				break;
856 			}
857 		}
858 	}
859 
860 	nxgep->statsp->mac_stats.xcvr_inuse = nxgep->xcvr.xcvr_inuse;
861 	nxgep->statsp->mac_stats.xcvr_portn = nxgep->xcvr_addr;
862 	nxgep->chip_id = chip_id;
863 
864 	/*
865 	 * Get the actual device ID value returned by MDIO read.
866 	 */
867 	nxgep->statsp->mac_stats.xcvr_id = 0;
868 
869 	pma_pmd_id = nxge_get_cl45_pma_pmd_id(nxgep, nxgep->xcvr_addr);
870 	if (nxge_is_supported_phy(pma_pmd_id, CLAUSE_45_TYPE)) {
871 		nxgep->statsp->mac_stats.xcvr_id = pma_pmd_id;
872 	} else {
873 		pcs_id = nxge_get_cl45_pcs_id(nxgep, nxgep->xcvr_addr);
874 		if (nxge_is_supported_phy(pcs_id, CLAUSE_45_TYPE)) {
875 			nxgep->statsp->mac_stats.xcvr_id = pcs_id;
876 		} else {
877 			phy_id = nxge_get_cl22_phy_id(nxgep,
878 			    nxgep->xcvr_addr);
879 			if (nxge_is_supported_phy(phy_id, CLAUSE_22_TYPE)) {
880 				nxgep->statsp->mac_stats.xcvr_id = phy_id;
881 			}
882 		}
883 	}
884 
885 	nxgep->mac.linkchkmode = LINKCHK_TIMER;
886 
887 	NXGE_DEBUG_MSG((nxgep, MAC_CTL, "nxge_setup_xcvr_table: niu_type"
888 	    "[0x%x] platform type[0x%x] xcvr_addr[%d]", nxgep->niu_type,
889 	    nxgep->platform_type, nxgep->xcvr_addr));
890 
891 	return (status);
892 }
893 
894 /* Initialize the entire MAC and physical layer */
895 
896 nxge_status_t
nxge_mac_init(p_nxge_t nxgep)897 nxge_mac_init(p_nxge_t nxgep)
898 {
899 	uint8_t			portn;
900 	nxge_status_t		status = NXGE_OK;
901 	portn = NXGE_GET_PORT_NUM(nxgep->function_num);
902 
903 	NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_mac_init: port<%d>", portn));
904 
905 	nxgep->mac.portnum = portn;
906 	nxgep->mac.porttype = PORT_TYPE_XMAC;
907 
908 	if ((portn == BMAC_PORT_0) || (portn == BMAC_PORT_1))
909 		nxgep->mac.porttype = PORT_TYPE_BMAC;
910 
911 
912 	/* Initialize XIF to configure a network mode */
913 	if ((status = nxge_xif_init(nxgep)) != NXGE_OK) {
914 		goto fail;
915 	}
916 
917 	if ((status = nxge_pcs_init(nxgep)) != NXGE_OK) {
918 		goto fail;
919 	}
920 
921 	/* Initialize TX and RX MACs */
922 	/*
923 	 * Always perform XIF init first, before TX and RX MAC init
924 	 */
925 	if ((status = nxge_tx_mac_reset(nxgep)) != NXGE_OK)
926 		goto fail;
927 
928 	if ((status = nxge_tx_mac_init(nxgep)) != NXGE_OK)
929 		goto fail;
930 
931 	if ((status = nxge_rx_mac_reset(nxgep)) != NXGE_OK)
932 		goto fail;
933 
934 	if ((status = nxge_rx_mac_init(nxgep)) != NXGE_OK)
935 		goto fail;
936 
937 	if ((status = nxge_tx_mac_enable(nxgep)) != NXGE_OK)
938 		goto fail;
939 
940 	if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) {
941 		if ((status = nxge_rx_mac_enable(nxgep)) != NXGE_OK)
942 			goto fail;
943 	}
944 
945 	/* Initialize MAC control configuration */
946 	if ((status = nxge_mac_ctrl_init(nxgep)) != NXGE_OK) {
947 		goto fail;
948 	}
949 
950 	nxgep->statsp->mac_stats.mac_mtu = nxgep->mac.maxframesize;
951 
952 	/* The Neptune Serdes needs to be reinitialized again */
953 	if ((NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) &&
954 	    ((nxgep->mac.portmode == PORT_1G_SERDES) ||
955 	    (nxgep->mac.portmode == PORT_1G_TN1010) ||
956 	    (nxgep->mac.portmode == PORT_1G_FIBER)) &&
957 	    ((portn == 0) || (portn == 1))) {
958 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
959 		    "nxge_mac_init: reinit Neptune 1G Serdes "));
960 		if ((status = nxge_1G_serdes_init(nxgep)) != NXGE_OK) {
961 			goto fail;
962 		}
963 	}
964 
965 
966 	NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_mac_init: port<%d>", portn));
967 
968 	return (NXGE_OK);
969 fail:
970 	NXGE_DEBUG_MSG((nxgep, MAC_CTL,
971 	    "nxge_mac_init: failed to initialize MAC port<%d>", portn));
972 	return (status);
973 }
974 
975 /* Initialize the Ethernet Link */
976 
977 nxge_status_t
nxge_link_init(p_nxge_t nxgep)978 nxge_link_init(p_nxge_t nxgep)
979 {
980 	nxge_status_t		status = NXGE_OK;
981 	nxge_port_mode_t	portmode;
982 #ifdef	NXGE_DEBUG
983 	uint8_t			portn;
984 
985 	portn = nxgep->mac.portnum;
986 
987 	NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_link_init: port<%d>", portn));
988 #endif
989 	/* For Opus NEM, Serdes always needs to be initialized */
990 
991 	portmode = nxgep->mac.portmode;
992 
993 	/*
994 	 * Workaround to get link up in both NIU ports. Some portmodes require
995 	 * that the xcvr be initialized twice, the first time before calling
996 	 * nxge_serdes_init.
997 	 */
998 	if (nxgep->niu_type == N2_NIU && (portmode != PORT_10G_SERDES) &&
999 	    (portmode != PORT_10G_TN1010) &&
1000 	    (portmode != PORT_1G_TN1010) &&
1001 	    (portmode != PORT_1G_SERDES)) {
1002 		if ((status = nxge_xcvr_init(nxgep)) != NXGE_OK) {
1003 			goto fail;
1004 		}
1005 	}
1006 
1007 	NXGE_DELAY(200000);
1008 	/* Initialize internal serdes */
1009 	if ((status = nxge_serdes_init(nxgep)) != NXGE_OK)
1010 		goto fail;
1011 	NXGE_DELAY(200000);
1012 	if ((status = nxge_xcvr_init(nxgep)) != NXGE_OK)
1013 		goto fail;
1014 
1015 	NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_link_init: port<%d>", portn));
1016 
1017 	return (NXGE_OK);
1018 
1019 fail:
1020 	NXGE_DEBUG_MSG((nxgep, MAC_CTL, "nxge_link_init: ",
1021 	    "failed to initialize Ethernet link on port<%d>", portn));
1022 
1023 	return (status);
1024 }
1025 
1026 
1027 /* Initialize the XIF sub-block within the MAC */
1028 
1029 nxge_status_t
nxge_xif_init(p_nxge_t nxgep)1030 nxge_xif_init(p_nxge_t nxgep)
1031 {
1032 	uint32_t		xif_cfg = 0;
1033 	npi_attr_t		ap;
1034 	uint8_t			portn;
1035 	nxge_port_t		portt;
1036 	nxge_port_mode_t	portmode;
1037 	p_nxge_stats_t		statsp;
1038 	npi_status_t		rs = NPI_SUCCESS;
1039 	npi_handle_t		handle;
1040 
1041 	portn = NXGE_GET_PORT_NUM(nxgep->function_num);
1042 
1043 	NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_xif_init: port<%d>", portn));
1044 
1045 	handle = nxgep->npi_handle;
1046 	portmode = nxgep->mac.portmode;
1047 	portt = nxgep->mac.porttype;
1048 	statsp = nxgep->statsp;
1049 
1050 	if ((NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) &&
1051 	    ((nxgep->mac.portmode == PORT_1G_SERDES) ||
1052 	    (nxgep->mac.portmode == PORT_1G_TN1010) ||
1053 	    (nxgep->mac.portmode == PORT_1G_FIBER)) &&
1054 	    ((portn == 0) || (portn == 1))) {
1055 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1056 		    "nxge_xcvr_init: set ATCA mode"));
1057 		npi_mac_mif_set_atca_mode(nxgep->npi_handle, B_TRUE);
1058 	}
1059 
1060 	if (portt == PORT_TYPE_XMAC) {
1061 
1062 		/* Setup XIF Configuration for XMAC */
1063 
1064 		if ((portmode == PORT_10G_FIBER) ||
1065 		    (portmode == PORT_10G_COPPER) ||
1066 		    (portmode == PORT_10G_TN1010) ||
1067 		    (portmode == PORT_HSP_MODE) ||
1068 		    (portmode == PORT_10G_SERDES))
1069 			xif_cfg |= CFG_XMAC_XIF_LFS;
1070 
1071 		/* Bypass PCS so that RGMII will be used */
1072 		if (portmode == PORT_1G_COPPER) {
1073 			xif_cfg |= CFG_XMAC_XIF_1G_PCS_BYPASS;
1074 		}
1075 
1076 		/* Set MAC Internal Loopback if necessary */
1077 		if (statsp->port_stats.lb_mode == nxge_lb_mac1000)
1078 			xif_cfg |= CFG_XMAC_XIF_LOOPBACK;
1079 
1080 		if (statsp->mac_stats.link_speed == 100)
1081 			xif_cfg |= CFG_XMAC_XIF_SEL_CLK_25MHZ;
1082 
1083 		xif_cfg |= CFG_XMAC_XIF_TX_OUTPUT;
1084 
1085 		if ((portmode == PORT_10G_FIBER) ||
1086 		    (portmode == PORT_10G_COPPER) ||
1087 		    (portmode == PORT_10G_TN1010) ||
1088 		    (portmode == PORT_1G_TN1010) ||
1089 		    (portmode == PORT_HSP_MODE) ||
1090 		    (portmode == PORT_10G_SERDES)) {
1091 			/* Assume LED same for 1G and 10G */
1092 			if (statsp->mac_stats.link_up) {
1093 				xif_cfg |= CFG_XMAC_XIF_LED_POLARITY;
1094 			} else {
1095 				xif_cfg |= CFG_XMAC_XIF_LED_FORCE;
1096 			}
1097 		}
1098 
1099 		rs = npi_xmac_xif_config(handle, INIT, portn, xif_cfg);
1100 		if (rs != NPI_SUCCESS)
1101 			goto fail;
1102 
1103 		nxgep->mac.xif_config = xif_cfg;
1104 
1105 		/* Set Port Mode */
1106 		if ((portmode == PORT_10G_FIBER) ||
1107 		    (portmode == PORT_10G_COPPER) ||
1108 		    (portmode == PORT_10G_TN1010) ||
1109 		    (portmode == PORT_HSP_MODE) ||
1110 		    (portmode == PORT_10G_SERDES)) {
1111 			SET_MAC_ATTR1(handle, ap, portn, MAC_PORT_MODE,
1112 			    MAC_XGMII_MODE, rs);
1113 			if (rs != NPI_SUCCESS)
1114 				goto fail;
1115 			if (statsp->mac_stats.link_up) {
1116 				if (nxge_10g_link_led_on(nxgep) != NXGE_OK)
1117 					goto fail;
1118 			} else {
1119 				if (nxge_10g_link_led_off(nxgep) != NXGE_OK)
1120 					goto fail;
1121 			}
1122 		} else if ((portmode == PORT_1G_FIBER) ||
1123 		    (portmode == PORT_1G_COPPER) ||
1124 		    (portmode == PORT_1G_SERDES) ||
1125 		    (portmode == PORT_1G_TN1010) ||
1126 		    (portmode == PORT_1G_RGMII_FIBER)) {
1127 			NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1128 			    "nxge_xif_init: Port[%d] Mode[%d] Speed[%d]",
1129 			    portn, portmode, statsp->mac_stats.link_speed));
1130 			if (statsp->mac_stats.link_speed == 1000) {
1131 				SET_MAC_ATTR1(handle, ap, portn, MAC_PORT_MODE,
1132 				    MAC_GMII_MODE, rs);
1133 			} else {
1134 				SET_MAC_ATTR1(handle, ap, portn, MAC_PORT_MODE,
1135 				    MAC_MII_MODE, rs);
1136 			}
1137 			if (rs != NPI_SUCCESS)
1138 				goto fail;
1139 		} else {
1140 			NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1141 			    "nxge_xif_init: Unknown port mode (%d)"
1142 			    " for port<%d>", portmode, portn));
1143 			goto fail;
1144 		}
1145 
1146 		/* Enable ATCA mode */
1147 
1148 	} else if (portt == PORT_TYPE_BMAC) {
1149 
1150 		/* Setup XIF Configuration for BMAC */
1151 
1152 		if ((portmode == PORT_1G_COPPER) ||
1153 		    (portmode == PORT_1G_RGMII_FIBER)) {
1154 			if (statsp->mac_stats.link_speed == 100)
1155 				xif_cfg |= CFG_BMAC_XIF_SEL_CLK_25MHZ;
1156 		}
1157 
1158 		if (statsp->port_stats.lb_mode == nxge_lb_mac1000)
1159 			xif_cfg |= CFG_BMAC_XIF_LOOPBACK;
1160 
1161 		if (statsp->mac_stats.link_speed == 1000)
1162 			xif_cfg |= CFG_BMAC_XIF_GMII_MODE;
1163 
1164 		xif_cfg |= CFG_BMAC_XIF_TX_OUTPUT;
1165 
1166 		rs = npi_bmac_xif_config(handle, INIT, portn, xif_cfg);
1167 		if (rs != NPI_SUCCESS)
1168 			goto fail;
1169 		nxgep->mac.xif_config = xif_cfg;
1170 	}
1171 	NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_xif_init: port<%d>", portn));
1172 	return (NXGE_OK);
1173 fail:
1174 	NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1175 	    "nxge_xif_init: Failed to initialize XIF port<%d>", portn));
1176 	return (NXGE_ERROR | rs);
1177 }
1178 
1179 
1180 /*
1181  * Initialize the PCS sub-block in the MAC.  Note that PCS does not
1182  * support loopback like XPCS.
1183  */
1184 nxge_status_t
nxge_pcs_init(p_nxge_t nxgep)1185 nxge_pcs_init(p_nxge_t nxgep)
1186 {
1187 	pcs_cfg_t		pcs_cfg;
1188 	uint32_t		val;
1189 	uint8_t			portn;
1190 	nxge_port_mode_t	portmode;
1191 	npi_handle_t		handle;
1192 	p_nxge_stats_t		statsp;
1193 	pcs_ctrl_t		pcs_ctrl;
1194 	npi_status_t		rs = NPI_SUCCESS;
1195 	uint8_t i;
1196 
1197 	handle = nxgep->npi_handle;
1198 	portmode = nxgep->mac.portmode;
1199 	portn = nxgep->mac.portnum;
1200 	statsp = nxgep->statsp;
1201 
1202 	NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_pcs_init: port<%d>", portn));
1203 
1204 	if (portmode == PORT_1G_FIBER ||
1205 	    portmode == PORT_1G_TN1010 ||
1206 	    portmode == PORT_1G_SERDES) {
1207 		if (portmode == PORT_1G_TN1010) {
1208 			/* Reset PCS multiple time in PORT_1G_TN1010 mode */
1209 			for (i = 0; i < 6; i ++) {
1210 				if ((rs = npi_mac_pcs_reset(handle, portn))
1211 				    != NPI_SUCCESS) {
1212 					goto fail;
1213 				}
1214 			}
1215 		} else {
1216 			if ((rs = npi_mac_pcs_reset(handle, portn))
1217 			    != NPI_SUCCESS)
1218 				goto fail;
1219 		}
1220 
1221 		/* Initialize port's PCS */
1222 		pcs_cfg.value = 0;
1223 		pcs_cfg.bits.w0.enable = 1;
1224 		pcs_cfg.bits.w0.mask = 1;
1225 		PCS_REG_WR(handle, portn, PCS_CONFIG_REG, pcs_cfg.value);
1226 		PCS_REG_WR(handle, portn, PCS_DATAPATH_MODE_REG, 0);
1227 
1228 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1229 		    "==> nxge_pcs_init: (1G) port<%d> write config 0x%llx",
1230 		    portn, pcs_cfg.value));
1231 
1232 		if (portmode == PORT_1G_TN1010) {
1233 			/*
1234 			 * Must disable PCS auto-negotiation when the the driver
1235 			 * is driving the TN1010 based XAUI card  Otherwise the
1236 			 * autonegotiation between the PCS and the TN1010 PCS
1237 			 * will never complete and the Neptune/NIU will not work
1238 			 */
1239 			pcs_ctrl.value = 0;
1240 			PCS_REG_WR(handle, portn, PCS_MII_CTRL_REG,
1241 			    pcs_ctrl.value);
1242 		}
1243 	} else if (portmode == PORT_10G_FIBER ||
1244 	    portmode == PORT_10G_COPPER ||
1245 	    portmode == PORT_10G_TN1010 ||
1246 	    portmode == PORT_HSP_MODE ||
1247 	    portmode == PORT_10G_SERDES) {
1248 		/* Use internal XPCS, bypass 1G PCS */
1249 		XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val);
1250 		val &= ~XMAC_XIF_XPCS_BYPASS;
1251 		XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val);
1252 
1253 		if ((rs = npi_xmac_xpcs_reset(handle, portn)) != NPI_SUCCESS)
1254 			goto fail;
1255 
1256 		/* Set XPCS Internal Loopback if necessary */
1257 		if ((rs = npi_xmac_xpcs_read(handle, portn,
1258 		    XPCS_REG_CONTROL1, &val)) != NPI_SUCCESS)
1259 			goto fail;
1260 
1261 		if ((statsp->port_stats.lb_mode == nxge_lb_mac10g) ||
1262 		    (statsp->port_stats.lb_mode == nxge_lb_mac1000))
1263 			val |= XPCS_CTRL1_LOOPBK;
1264 		else
1265 			val &= ~XPCS_CTRL1_LOOPBK;
1266 		if ((rs = npi_xmac_xpcs_write(handle, portn,
1267 		    XPCS_REG_CONTROL1, val)) != NPI_SUCCESS)
1268 			goto fail;
1269 
1270 		/* Clear descw errors */
1271 		if ((rs = npi_xmac_xpcs_write(handle, portn,
1272 		    XPCS_REG_DESCWERR_COUNTER, 0)) != NPI_SUCCESS)
1273 			goto fail;
1274 		/* Clear symbol errors */
1275 		if ((rs = npi_xmac_xpcs_read(handle, portn,
1276 		    XPCS_REG_SYMBOL_ERR_L0_1_COUNTER, &val)) != NPI_SUCCESS)
1277 			goto fail;
1278 		if ((rs = npi_xmac_xpcs_read(handle, portn,
1279 		    XPCS_REG_SYMBOL_ERR_L2_3_COUNTER, &val)) != NPI_SUCCESS)
1280 			goto fail;
1281 
1282 	} else if ((portmode == PORT_1G_COPPER) ||
1283 	    (portmode == PORT_1G_RGMII_FIBER)) {
1284 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1285 		    "==> nxge_pcs_init: (1G) copper port<%d>", portn));
1286 		if (portn < 4) {
1287 			PCS_REG_WR(handle, portn, PCS_DATAPATH_MODE_REG,
1288 			    PCS_DATAPATH_MODE_MII);
1289 		}
1290 		if ((rs = npi_mac_pcs_reset(handle, portn)) != NPI_SUCCESS)
1291 			goto fail;
1292 
1293 	} else {
1294 		goto fail;
1295 	}
1296 pass:
1297 	NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_pcs_init: port<%d>", portn));
1298 	return (NXGE_OK);
1299 fail:
1300 	NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1301 	    "nxge_pcs_init: Failed to initialize PCS port<%d>", portn));
1302 	return (NXGE_ERROR | rs);
1303 }
1304 
1305 /*
1306  * Initialize the MAC CTRL sub-block within the MAC
1307  * Only the receive-pause-cap is supported.
1308  */
1309 nxge_status_t
nxge_mac_ctrl_init(p_nxge_t nxgep)1310 nxge_mac_ctrl_init(p_nxge_t nxgep)
1311 {
1312 	uint8_t			portn;
1313 	nxge_port_t		portt;
1314 	p_nxge_stats_t		statsp;
1315 	npi_handle_t		handle;
1316 	uint32_t		val;
1317 
1318 	portn = NXGE_GET_PORT_NUM(nxgep->function_num);
1319 
1320 	NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_mac_ctrl_init: port<%d>",
1321 	    portn));
1322 
1323 	handle = nxgep->npi_handle;
1324 	portt = nxgep->mac.porttype;
1325 	statsp = nxgep->statsp;
1326 
1327 	if (portt == PORT_TYPE_XMAC) {
1328 		/* Reading the current XMAC Config Register for XMAC */
1329 		XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val);
1330 
1331 		/*
1332 		 * Setup XMAC Configuration for XMAC
1333 		 * XMAC only supports receive-pause
1334 		 */
1335 		if (statsp->mac_stats.adv_cap_asmpause) {
1336 			if (!statsp->mac_stats.adv_cap_pause) {
1337 				/*
1338 				 * If adv_cap_asmpause is 1 and adv_cap_pause
1339 				 * is 0, enable receive pause.
1340 				 */
1341 				val |= XMAC_RX_CFG_RX_PAUSE_EN;
1342 			} else {
1343 				/*
1344 				 * If adv_cap_asmpause is 1 and adv_cap_pause
1345 				 * is 1, disable receive pause.  Send pause is
1346 				 * not supported.
1347 				 */
1348 				val &= ~XMAC_RX_CFG_RX_PAUSE_EN;
1349 			}
1350 		} else {
1351 			NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1352 			    "==> nxge_mac_ctrl_init: port<%d>: pause",
1353 			    portn));
1354 			if (statsp->mac_stats.adv_cap_pause) {
1355 				NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1356 				    "==> nxge_mac_ctrl_init: port<%d>: "
1357 				    "enable pause", portn));
1358 				/*
1359 				 * If adv_cap_asmpause is 0 and adv_cap_pause
1360 				 * is 1, enable receive pause.
1361 				 */
1362 				val |= XMAC_RX_CFG_RX_PAUSE_EN;
1363 			} else {
1364 				/*
1365 				 * If adv_cap_asmpause is 0 and adv_cap_pause
1366 				 * is 0, disable receive pause. Send pause is
1367 				 * not supported
1368 				 */
1369 				NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1370 				    "==> nxge_mac_ctrl_init: port<%d>: "
1371 				    "disable pause", portn));
1372 				val &= ~XMAC_RX_CFG_RX_PAUSE_EN;
1373 			}
1374 		}
1375 		XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val);
1376 	} else if (portt == PORT_TYPE_BMAC) {
1377 		/* Reading the current MAC CTRL Config Register for BMAC */
1378 		BMAC_REG_RD(handle, portn, MAC_CTRL_CONFIG_REG, &val);
1379 
1380 		/* Setup MAC CTRL Configuration for BMAC */
1381 		if (statsp->mac_stats.adv_cap_asmpause) {
1382 			if (statsp->mac_stats.adv_cap_pause) {
1383 				/*
1384 				 * If adv_cap_asmpause is 1 and adv_cap_pause
1385 				 * is 1, disable receive pause. Send pause
1386 				 * is not supported
1387 				 */
1388 				val &= ~MAC_CTRL_CFG_RECV_PAUSE_EN;
1389 			} else {
1390 				/*
1391 				 * If adv_cap_asmpause is 1 and adv_cap_pause
1392 				 * is 0, enable receive pause and disable
1393 				 * send pause.
1394 				 */
1395 				val |= MAC_CTRL_CFG_RECV_PAUSE_EN;
1396 				val &= ~MAC_CTRL_CFG_SEND_PAUSE_EN;
1397 			}
1398 		} else {
1399 			if (statsp->mac_stats.adv_cap_pause) {
1400 				/*
1401 				 * If adv_cap_asmpause is 0 and adv_cap_pause
1402 				 * is 1, enable receive pause. Send pause is
1403 				 * not supported.
1404 				 */
1405 				val |= MAC_CTRL_CFG_RECV_PAUSE_EN;
1406 			} else {
1407 				/*
1408 				 * If adv_cap_asmpause is 0 and adv_cap_pause
1409 				 * is 0, pause capability is not available in
1410 				 * either direction.
1411 				 */
1412 				val &= (~MAC_CTRL_CFG_SEND_PAUSE_EN &
1413 				    ~MAC_CTRL_CFG_RECV_PAUSE_EN);
1414 			}
1415 		}
1416 		BMAC_REG_WR(handle, portn, MAC_CTRL_CONFIG_REG, val);
1417 	}
1418 
1419 	NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_mac_ctrl_init: port<%d>",
1420 	    portn));
1421 
1422 	return (NXGE_OK);
1423 }
1424 
1425 /* Initialize the Internal Serdes */
1426 
1427 nxge_status_t
nxge_serdes_init(p_nxge_t nxgep)1428 nxge_serdes_init(p_nxge_t nxgep)
1429 {
1430 	p_nxge_stats_t		statsp;
1431 #ifdef	NXGE_DEBUG
1432 	uint8_t			portn;
1433 #endif
1434 	nxge_status_t		status = NXGE_OK;
1435 
1436 #ifdef	NXGE_DEBUG
1437 	portn = nxgep->mac.portnum;
1438 	NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1439 	    "==> nxge_serdes_init port<%d>", portn));
1440 #endif
1441 
1442 	if (nxgep->xcvr.serdes_init) {
1443 		statsp = nxgep->statsp;
1444 		status = nxgep->xcvr.serdes_init(nxgep);
1445 		if (status != NXGE_OK)
1446 			goto fail;
1447 		statsp->mac_stats.serdes_inits++;
1448 	}
1449 
1450 	NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_serdes_init port<%d>",
1451 	    portn));
1452 
1453 	return (NXGE_OK);
1454 
1455 fail:
1456 	NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1457 	    "nxge_serdes_init: Failed to initialize serdes for port<%d>",
1458 	    portn));
1459 
1460 	return (status);
1461 }
1462 
1463 /* Initialize the TI Hedwig Internal Serdes (N2-NIU only) */
1464 
1465 static nxge_status_t
nxge_n2_serdes_init(p_nxge_t nxgep)1466 nxge_n2_serdes_init(p_nxge_t nxgep)
1467 {
1468 	uint8_t portn;
1469 	int chan;
1470 	esr_ti_cfgpll_l_t pll_cfg_l;
1471 	esr_ti_cfgpll_l_t pll_sts_l;
1472 	esr_ti_cfgrx_l_t rx_cfg_l;
1473 	esr_ti_cfgrx_h_t rx_cfg_h;
1474 	esr_ti_cfgtx_l_t tx_cfg_l;
1475 	esr_ti_cfgtx_h_t tx_cfg_h;
1476 #ifdef NXGE_DEBUG
1477 	esr_ti_testcfg_t cfg;
1478 #endif
1479 	esr_ti_testcfg_t test_cfg;
1480 	nxge_status_t status = NXGE_OK;
1481 
1482 	portn = nxgep->mac.portnum;
1483 
1484 	NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_n2_serdes_init port<%d>",
1485 	    portn));
1486 	if (nxgep->niu_hw_type == NIU_HW_TYPE_RF) {
1487 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1488 		    "==> nxge_n2_serdes_init port<%d>: KT-NIU", portn));
1489 		return (nxge_n2_kt_serdes_init(nxgep));
1490 	}
1491 
1492 	tx_cfg_l.value = 0;
1493 	tx_cfg_h.value = 0;
1494 	rx_cfg_l.value = 0;
1495 	rx_cfg_h.value = 0;
1496 	pll_cfg_l.value = 0;
1497 	pll_sts_l.value = 0;
1498 	test_cfg.value = 0;
1499 
1500 	/*
1501 	 * If the nxge driver has been plumbed without a link, then it will
1502 	 * detect a link up when a cable connecting to an anto-negotiation
1503 	 * partner is plugged into the port. Because the TN1010 PHY supports
1504 	 * both 1G and 10G speeds, the driver must re-configure the
1505 	 * Neptune/NIU according to the negotiated speed.  nxge_n2_serdes_init
1506 	 * is called at the post-link-up reconfiguration time. Here it calls
1507 	 * nxge_set_tn1010_param to set portmode before re-initializing
1508 	 * the serdes.
1509 	 */
1510 	if (nxgep->mac.portmode == PORT_1G_TN1010 ||
1511 	    nxgep->mac.portmode == PORT_10G_TN1010) {
1512 		if (nxge_set_tn1010_param(nxgep) != NXGE_OK) {
1513 			goto fail;
1514 		}
1515 	}
1516 
1517 	if (nxgep->mac.portmode == PORT_10G_FIBER ||
1518 	    nxgep->mac.portmode == PORT_10G_COPPER ||
1519 	    nxgep->mac.portmode == PORT_10G_TN1010 ||
1520 	    nxgep->mac.portmode == PORT_HSP_MODE ||
1521 	    nxgep->mac.portmode == PORT_10G_SERDES) {
1522 		/* 0x0E01 */
1523 		tx_cfg_l.bits.entx = 1;
1524 		tx_cfg_l.bits.swing = CFGTX_SWING_1375MV;
1525 
1526 		/* 0x9101 */
1527 		rx_cfg_l.bits.enrx = 1;
1528 		rx_cfg_l.bits.term = CFGRX_TERM_0P8VDDT;
1529 		rx_cfg_l.bits.align = CFGRX_ALIGN_EN;
1530 		rx_cfg_l.bits.los = CFGRX_LOS_LOTHRES;
1531 
1532 		/* 0x0008 */
1533 		rx_cfg_h.bits.eq = CFGRX_EQ_ADAPTIVE_LP_ADAPTIVE_ZF;
1534 
1535 		/* Set loopback mode if necessary */
1536 		if (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes10g) {
1537 			tx_cfg_l.bits.entest = 1;
1538 			rx_cfg_l.bits.entest = 1;
1539 			test_cfg.bits.loopback = TESTCFG_INNER_CML_DIS_LOOPBACK;
1540 			if ((status = nxge_mdio_write(nxgep, portn,
1541 			    ESR_N2_DEV_ADDR,
1542 			    ESR_N2_TEST_CFG_REG, test_cfg.value)) != NXGE_OK)
1543 				goto fail;
1544 		}
1545 
1546 		/* Initialize PLL for 10G */
1547 		pll_cfg_l.bits.mpy = CFGPLL_MPY_10X;
1548 		pll_cfg_l.bits.enpll = 1;
1549 		pll_sts_l.bits.enpll = 1;
1550 		if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR,
1551 		    ESR_N2_PLL_CFG_L_REG, pll_cfg_l.value)) != NXGE_OK)
1552 			goto fail;
1553 
1554 		if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR,
1555 		    ESR_N2_PLL_STS_L_REG, pll_sts_l.value)) != NXGE_OK)
1556 			goto fail;
1557 
1558 #ifdef  NXGE_DEBUG
1559 		nxge_mdio_read(nxgep, portn, ESR_N2_DEV_ADDR,
1560 		    ESR_N2_PLL_CFG_L_REG, &cfg.value);
1561 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1562 		    "==> nxge_n2_serdes_init port<%d>: PLL cfg.l 0x%x (0x%x)",
1563 		    portn, pll_cfg_l.value, cfg.value));
1564 
1565 		nxge_mdio_read(nxgep, portn, ESR_N2_DEV_ADDR,
1566 		    ESR_N2_PLL_STS_L_REG, &cfg.value);
1567 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1568 		    "==> nxge_n2_serdes_init port<%d>: PLL sts.l 0x%x (0x%x)",
1569 		    portn, pll_sts_l.value, cfg.value));
1570 #endif
1571 	} else if (nxgep->mac.portmode == PORT_1G_FIBER ||
1572 	    nxgep->mac.portmode == PORT_1G_TN1010 ||
1573 	    nxgep->mac.portmode == PORT_1G_SERDES) {
1574 		/* 0x0E21 */
1575 		tx_cfg_l.bits.entx = 1;
1576 		tx_cfg_l.bits.rate = CFGTX_RATE_HALF;
1577 		tx_cfg_l.bits.swing = CFGTX_SWING_1375MV;
1578 
1579 		/* 0x9121 */
1580 		rx_cfg_l.bits.enrx = 1;
1581 		rx_cfg_l.bits.rate = CFGRX_RATE_HALF;
1582 		rx_cfg_l.bits.term = CFGRX_TERM_0P8VDDT;
1583 		rx_cfg_l.bits.align = CFGRX_ALIGN_EN;
1584 		rx_cfg_l.bits.los = CFGRX_LOS_LOTHRES;
1585 
1586 		if (portn == 0) {
1587 			/* 0x8 */
1588 			rx_cfg_h.bits.eq = CFGRX_EQ_ADAPTIVE_LP_ADAPTIVE_ZF;
1589 		}
1590 
1591 		/* Initialize PLL for 1G */
1592 		pll_cfg_l.bits.mpy = CFGPLL_MPY_8X;
1593 		pll_cfg_l.bits.enpll = 1;
1594 		pll_sts_l.bits.enpll = 1;
1595 		if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR,
1596 		    ESR_N2_PLL_CFG_L_REG, pll_cfg_l.value)) != NXGE_OK)
1597 			goto fail;
1598 
1599 		if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR,
1600 		    ESR_N2_PLL_STS_L_REG, pll_sts_l.value)) != NXGE_OK)
1601 			goto fail;
1602 
1603 #ifdef  NXGE_DEBUG
1604 		nxge_mdio_read(nxgep, portn, ESR_N2_DEV_ADDR,
1605 		    ESR_N2_PLL_CFG_L_REG, &cfg.value);
1606 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1607 		    "==> nxge_n2_serdes_init port<%d>: PLL cfg.l 0x%x (0x%x)",
1608 		    portn, pll_cfg_l.value, cfg.value));
1609 
1610 		nxge_mdio_read(nxgep, portn, ESR_N2_DEV_ADDR,
1611 		    ESR_N2_PLL_STS_L_REG, &cfg.value);
1612 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1613 		    "==> nxge_n2_serdes_init port<%d>: PLL sts.l 0x%x (0x%x)",
1614 		    portn, pll_sts_l.value, cfg.value));
1615 #endif
1616 
1617 		/* Set loopback mode if necessary */
1618 		if (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes1000) {
1619 			tx_cfg_l.bits.entest = 1;
1620 			rx_cfg_l.bits.entest = 1;
1621 			test_cfg.bits.loopback = TESTCFG_INNER_CML_DIS_LOOPBACK;
1622 			NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1623 			    "==> nxge_n2_serdes_init port<%d>: loopback 0x%x",
1624 			    portn, test_cfg.value));
1625 			if ((status = nxge_mdio_write(nxgep, portn,
1626 			    ESR_N2_DEV_ADDR,
1627 			    ESR_N2_TEST_CFG_REG, test_cfg.value)) != NXGE_OK) {
1628 				goto fail;
1629 			}
1630 		}
1631 	} else {
1632 		goto fail;
1633 	}
1634 
1635 	/*   MIF_REG_WR(handle, MIF_MASK_REG, ~mask); */
1636 
1637 	NXGE_DELAY(20);
1638 
1639 	/* init TX channels */
1640 	for (chan = 0; chan < 4; chan++) {
1641 		if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR,
1642 		    ESR_N2_TX_CFG_L_REG_ADDR(chan), tx_cfg_l.value)) != NXGE_OK)
1643 			goto fail;
1644 
1645 		if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR,
1646 		    ESR_N2_TX_CFG_H_REG_ADDR(chan), tx_cfg_h.value)) != NXGE_OK)
1647 			goto fail;
1648 
1649 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1650 		    "==> nxge_n2_serdes_init port<%d>: chan %d tx_cfg_l 0x%x",
1651 		    portn, chan, tx_cfg_l.value));
1652 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1653 		    "==> nxge_n2_serdes_init port<%d>: chan %d tx_cfg_h 0x%x",
1654 		    portn, chan, tx_cfg_h.value));
1655 	}
1656 
1657 	/* init RX channels */
1658 	for (chan = 0; chan < 4; chan++) {
1659 		if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR,
1660 		    ESR_N2_RX_CFG_L_REG_ADDR(chan), rx_cfg_l.value)) != NXGE_OK)
1661 			goto fail;
1662 
1663 		if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR,
1664 		    ESR_N2_RX_CFG_H_REG_ADDR(chan), rx_cfg_h.value)) != NXGE_OK)
1665 			goto fail;
1666 
1667 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1668 		    "==> nxge_n2_serdes_init port<%d>: chan %d rx_cfg_l 0x%x",
1669 		    portn, chan, rx_cfg_l.value));
1670 
1671 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1672 		    "==> nxge_n2_serdes_init port<%d>: chan %d rx_cfg_h 0x%x",
1673 		    portn, chan, rx_cfg_h.value));
1674 	}
1675 
1676 	NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_n2_serdes_init port<%d>",
1677 	    portn));
1678 
1679 	return (NXGE_OK);
1680 fail:
1681 	NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1682 	    "nxge_n2_serdes_init: Failed to initialize N2 serdes for port<%d>",
1683 	    portn));
1684 
1685 	return (status);
1686 
1687 }
1688 
1689 /* Initialize the TI Hedwig Internal Serdes (N2-KT-NIU only) */
1690 
1691 static nxge_status_t
nxge_n2_kt_serdes_init(p_nxge_t nxgep)1692 nxge_n2_kt_serdes_init(p_nxge_t nxgep)
1693 {
1694 	uint8_t portn;
1695 	int chan, i;
1696 	k_esr_ti_cfgpll_l_t pll_cfg_l;
1697 	k_esr_ti_cfgrx_l_t rx_cfg_l;
1698 	k_esr_ti_cfgrx_h_t rx_cfg_h;
1699 	k_esr_ti_cfgtx_l_t tx_cfg_l;
1700 	k_esr_ti_cfgtx_h_t tx_cfg_h;
1701 #ifdef NXGE_DEBUG
1702 	k_esr_ti_testcfg_t cfg;
1703 #endif
1704 	k_esr_ti_testcfg_t test_cfg;
1705 	nxge_status_t status = NXGE_OK;
1706 	boolean_t mode_1g = B_FALSE;
1707 	uint64_t val;
1708 	npi_handle_t handle;
1709 
1710 	portn = nxgep->mac.portnum;
1711 
1712 	NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1713 	    "==> nxge_n2_kt_serdes_init port<%d>", portn));
1714 	handle = nxgep->npi_handle;
1715 
1716 	tx_cfg_l.value = 0;
1717 	tx_cfg_h.value = 0;
1718 	rx_cfg_l.value = 0;
1719 	rx_cfg_h.value = 0;
1720 	pll_cfg_l.value = 0;
1721 	test_cfg.value = 0;
1722 
1723 	/*
1724 	 * The following setting assumes the reference clock frquency
1725 	 * is 156.25 MHz.
1726 	 */
1727 	/*
1728 	 * If the nxge driver has been plumbed without a link, then it will
1729 	 * detect a link up when a cable connecting to an anto-negotiation
1730 	 * partner is plugged into the port. Because the TN1010 PHY supports
1731 	 * both 1G and 10G speeds, the driver must re-configure the
1732 	 * Neptune/NIU according to the negotiated speed.  nxge_n2_serdes_init
1733 	 * is called at the post-link-up reconfiguration time. Here it calls
1734 	 * nxge_set_tn1010_param to set portmode before re-initializing
1735 	 * the serdes.
1736 	 */
1737 	if (nxgep->mac.portmode == PORT_1G_TN1010 ||
1738 	    nxgep->mac.portmode == PORT_10G_TN1010) {
1739 		if (nxge_set_tn1010_param(nxgep) != NXGE_OK) {
1740 			goto fail;
1741 		}
1742 	}
1743 	if (nxgep->mac.portmode == PORT_10G_FIBER ||
1744 	    nxgep->mac.portmode == PORT_10G_COPPER ||
1745 	    nxgep->mac.portmode == PORT_10G_TN1010 ||
1746 	    nxgep->mac.portmode == PORT_10G_SERDES) {
1747 
1748 		/* Take tunables from OBP if present, otherwise use defaults */
1749 		if (nxgep->srds_prop.prop_set & NXGE_SRDS_TXCFGL) {
1750 			tx_cfg_l.value = nxgep->srds_prop.tx_cfg_l;
1751 		} else {
1752 			tx_cfg_l.bits.entx = K_CFGTX_ENABLE_TX;
1753 			/* 0x1e21 */
1754 			tx_cfg_l.bits.swing = K_CFGTX_SWING_2000MV;
1755 			tx_cfg_l.bits.rate = K_CFGTX_RATE_HALF;
1756 		}
1757 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1758 		    "==> nxge_n2_kt_serdes_init port<%d> tx_cfg_l 0x%x",
1759 		    portn, tx_cfg_l.value));
1760 
1761 		if (nxgep->srds_prop.prop_set & NXGE_SRDS_TXCFGH) {
1762 			tx_cfg_h.value = nxgep->srds_prop.tx_cfg_h;
1763 		} else {
1764 			/* channel 0: enable syn. master */
1765 			/* 0x40 */
1766 			tx_cfg_h.bits.msync = K_CFGTX_ENABLE_MSYNC;
1767 		}
1768 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1769 		    "==> nxge_n2_kt_serdes_init port<%d> tx_cfg_h 0x%x",
1770 		    portn, tx_cfg_h.value));
1771 
1772 		if (nxgep->srds_prop.prop_set & NXGE_SRDS_RXCFGL) {
1773 			rx_cfg_l.value = nxgep->srds_prop.rx_cfg_l;
1774 		} else {
1775 			/* 0x4821 */
1776 			rx_cfg_l.bits.enrx = K_CFGRX_ENABLE_RX;
1777 			rx_cfg_l.bits.rate = K_CFGRX_RATE_HALF;
1778 			rx_cfg_l.bits.align = K_CFGRX_ALIGN_EN;
1779 			rx_cfg_l.bits.los = K_CFGRX_LOS_ENABLE;
1780 		}
1781 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1782 		    "==> nxge_n2_kt_serdes_init port<%d> rx_cfg_l 0x%x",
1783 		    portn, rx_cfg_l.value));
1784 
1785 		if (nxgep->srds_prop.prop_set & NXGE_SRDS_RXCFGH) {
1786 			rx_cfg_h.value = nxgep->srds_prop.rx_cfg_h;
1787 		} else {
1788 			/* 0x0008 */
1789 			rx_cfg_h.bits.eq = K_CFGRX_EQ_ADAPTIVE;
1790 		}
1791 
1792 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1793 		    "==> nxge_n2_kt_serdes_init port<%d> rx_cfg_h 0x%x",
1794 		    portn, rx_cfg_h.value));
1795 
1796 		if (nxgep->srds_prop.prop_set & NXGE_SRDS_PLLCFGL) {
1797 			pll_cfg_l.value = nxgep->srds_prop.pll_cfg_l;
1798 		} else {
1799 			/* 0xa1: Initialize PLL for 10G */
1800 			pll_cfg_l.bits.mpy = K_CFGPLL_MPY_20X;
1801 			pll_cfg_l.bits.enpll = K_CFGPLL_ENABLE_PLL;
1802 		}
1803 
1804 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1805 		    "==> nxge_n2_kt_serdes_init port<%d> pll_cfg_l 0x%x",
1806 		    portn, pll_cfg_l.value));
1807 
1808 		if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR,
1809 		    ESR_N2_PLL_CFG_L_REG, pll_cfg_l.value)) != NXGE_OK)
1810 			goto fail;
1811 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1812 		    "==> nxge_n2_kt_serdes_init port<%d> pll_cfg_l 0x%x",
1813 		    portn, pll_cfg_l.value));
1814 
1815 		/* Set loopback mode if necessary */
1816 		if (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes10g) {
1817 			tx_cfg_h.bits.loopback = K_CFGTX_INNER_CML_ENA_LOOPBACK;
1818 			rx_cfg_h.bits.loopback = K_CFGTX_INNER_CML_ENA_LOOPBACK;
1819 			rx_cfg_l.bits.los = 0;
1820 
1821 			NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1822 			    "==> nxge_n2_kt_serdes_init port<%d>: "
1823 			    "loopback 0x%x", portn, tx_cfg_h.value));
1824 		}
1825 #ifdef  NXGE_DEBUG
1826 		nxge_mdio_read(nxgep, portn, ESR_N2_DEV_ADDR,
1827 		    ESR_N2_PLL_CFG_L_REG, &cfg.value);
1828 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1829 		    "==> nxge_n2_kt_serdes_init port<%d>: "
1830 		    "PLL cfg.l 0x%x (0x%x)",
1831 		    portn, pll_cfg_l.value, cfg.value));
1832 
1833 		nxge_mdio_read(nxgep, portn, ESR_N2_DEV_ADDR,
1834 		    ESR_N2_PLL_STS_L_REG, &cfg.value);
1835 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1836 		    "==> nxge_n2_kt_serdes_init port<%d>: (0x%x)",
1837 		    portn, cfg.value));
1838 #endif
1839 	} else if (nxgep->mac.portmode == PORT_1G_FIBER ||
1840 	    nxgep->mac.portmode == PORT_1G_TN1010 ||
1841 	    nxgep->mac.portmode == PORT_1G_SERDES) {
1842 		mode_1g = B_TRUE;
1843 		/* 0x1e41 */
1844 		tx_cfg_l.bits.entx = 1;
1845 		tx_cfg_l.bits.rate = K_CFGTX_RATE_HALF;
1846 		tx_cfg_l.bits.swing = K_CFGTX_SWING_2000MV;
1847 
1848 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1849 		    "==> nxge_n2_kt_serdes_init port<%d> tx_cfg_l 0x%x",
1850 		    portn, tx_cfg_l.value));
1851 
1852 
1853 		/* channel 0: enable syn. master */
1854 		tx_cfg_h.bits.msync = K_CFGTX_ENABLE_MSYNC;
1855 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1856 		    "==> nxge_n2_kt_serdes_init port<%d> tx_cfg_h 0x%x",
1857 		    portn, tx_cfg_h.value));
1858 
1859 
1860 		/* 0x4841 */
1861 		rx_cfg_l.bits.enrx = 1;
1862 		rx_cfg_l.bits.rate = K_CFGRX_RATE_HALF;
1863 		rx_cfg_l.bits.align = K_CFGRX_ALIGN_EN;
1864 		rx_cfg_l.bits.los = K_CFGRX_LOS_ENABLE;
1865 
1866 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1867 		    "==> nxge_n2_kt_serdes_init port<%d> rx_cfg_l 0x%x",
1868 		    portn, rx_cfg_l.value));
1869 
1870 		/* 0x0008 */
1871 		rx_cfg_h.bits.eq = K_CFGRX_EQ_ADAPTIVE_LF_365MHZ_ZF;
1872 
1873 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1874 		    "==> nxge_n2_kt_serdes_init port<%d> tx_cfg_h 0x%x",
1875 		    portn, rx_cfg_h.value));
1876 
1877 		/* 0xa1: Initialize PLL for 1G */
1878 		pll_cfg_l.bits.mpy = K_CFGPLL_MPY_20X;
1879 		pll_cfg_l.bits.enpll = K_CFGPLL_ENABLE_PLL;
1880 
1881 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1882 		    "==> nxge_n2_kt_serdes_init port<%d> pll_cfg_l 0x%x",
1883 		    portn, pll_cfg_l.value));
1884 
1885 		if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR,
1886 		    ESR_N2_PLL_CFG_L_REG, pll_cfg_l.value))
1887 		    != NXGE_OK)
1888 			goto fail;
1889 
1890 
1891 #ifdef  NXGE_DEBUG
1892 		nxge_mdio_read(nxgep, portn, ESR_N2_DEV_ADDR,
1893 		    ESR_N2_PLL_CFG_L_REG, &cfg.value);
1894 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1895 		    "==> nxge_n2_serdes_init port<%d>: PLL cfg.l 0x%x (0x%x)",
1896 		    portn, pll_cfg_l.value, cfg.value));
1897 
1898 		nxge_mdio_read(nxgep, portn, ESR_N2_DEV_ADDR,
1899 		    ESR_N2_PLL_STS_L_REG, &cfg.value);
1900 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1901 		    "==> nxge_n2_kt_serdes_init port<%d>: (0x%x)",
1902 		    portn, cfg.value));
1903 #endif
1904 
1905 		/* Set loopback mode if necessary */
1906 		if (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes1000) {
1907 			tx_cfg_h.bits.loopback = TESTCFG_INNER_CML_DIS_LOOPBACK;
1908 
1909 			NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1910 			    "==> nxge_n2_kt_serdes_init port<%d>: "
1911 			    "loopback 0x%x", portn, test_cfg.value));
1912 			if ((status = nxge_mdio_write(nxgep, portn,
1913 			    ESR_N2_DEV_ADDR,
1914 			    ESR_N2_TX_CFG_L_REG_ADDR(0),
1915 			    tx_cfg_h.value)) != NXGE_OK) {
1916 				goto fail;
1917 			}
1918 		}
1919 	} else {
1920 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1921 		    "nxge_n2_kt_serdes_init:port<%d> - "
1922 		    "unsupported port mode %d",
1923 		    portn, nxgep->mac.portmode));
1924 		goto fail;
1925 	}
1926 
1927 	NXGE_DELAY(20);
1928 	/* Clear the test register (offset 0x8004) */
1929 	if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR,
1930 	    ESR_N2_TEST_CFG_REG, test_cfg.value)) != NXGE_OK) {
1931 		goto fail;
1932 	}
1933 	NXGE_DELAY(20);
1934 
1935 	/* init TX channels */
1936 	for (chan = 0; chan < 4; chan++) {
1937 		if (mode_1g)
1938 			tx_cfg_l.value = 0;
1939 		if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR,
1940 		    ESR_N2_TX_CFG_L_REG_ADDR(chan), tx_cfg_l.value)) != NXGE_OK)
1941 			goto fail;
1942 
1943 		if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR,
1944 		    ESR_N2_TX_CFG_H_REG_ADDR(chan), tx_cfg_h.value)) != NXGE_OK)
1945 			goto fail;
1946 
1947 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1948 		    "==> nxge_n2_kt_serdes_init port<%d>: "
1949 		    "chan %d tx_cfg_l 0x%x", portn, chan, tx_cfg_l.value));
1950 
1951 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1952 		    "==> nxge_n2_kt_serdes_init port<%d>: "
1953 		    "chan %d tx_cfg_h 0x%x", portn, chan, tx_cfg_h.value));
1954 	}
1955 
1956 	/* init RX channels */
1957 	/* 1G mode only write to the first channel */
1958 	for (chan = 0; chan < 4; chan++) {
1959 		if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR,
1960 		    ESR_N2_RX_CFG_L_REG_ADDR(chan), rx_cfg_l.value))
1961 		    != NXGE_OK)
1962 			goto fail;
1963 
1964 		if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR,
1965 		    ESR_N2_RX_CFG_H_REG_ADDR(chan), rx_cfg_h.value))
1966 		    != NXGE_OK)
1967 			goto fail;
1968 
1969 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1970 		    "==> nxge_n2_kt_serdes_init port<%d>: "
1971 		    "chan %d rx_cfg_l 0x%x", portn, chan, rx_cfg_l.value));
1972 
1973 		NXGE_DEBUG_MSG((nxgep, MAC_CTL,
1974 		    "==> nxge_n2_kt_serdes_init port<%d>: "
1975 		    "chan %d rx_cfg_h 0x%x", portn, chan, rx_cfg_h.value));
1976 	}
1977 
1978 	if (portn == 0) {
1979 		/* Wait for serdes to be ready */
1980 		for (i = 0; i < MAX_SERDES_RDY_RETRIES; i++) {
1981 			ESR_REG_RD(handle, ESR_INTERNAL_SIGNALS_REG, &val);
1982 			if ((val & ESR_SIG_P0_BITS_MASK) !=
1983 			    (ESR_SIG_SERDES_RDY0_P0 | ESR_SIG_DETECT0_P0 |
1984 			    ESR_SIG_XSERDES_RDY_P0 |
1985 			    ESR_SIG_XDETECT_P0_CH3 |
1986 			    ESR_SIG_XDETECT_P0_CH2 |
1987 			    ESR_SIG_XDETECT_P0_CH1 |
1988 			    ESR_SIG_XDETECT_P0_CH0))
1989 
1990 				NXGE_DELAY(SERDES_RDY_WT_INTERVAL);
1991 			else
1992 				break;
1993 		}
1994 
1995 		if (i == MAX_SERDES_RDY_RETRIES) {
1996 			/*
1997 			 * RDY signal stays low may due to the absent of the
1998 			 * external PHY, it is not an error condition.
1999 			 * But still print the message for the debugging
2000 			 * purpose when link stays down
2001 			 */
2002 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2003 			    "nxge_n2_kt_serdes_init: "
2004 			    "Serdes/signal for port<%d> not ready", portn));
2005 			goto done;
2006 		}
2007 	} else if (portn == 1) {
2008 		/* Wait for serdes to be ready */
2009 		for (i = 0; i < MAX_SERDES_RDY_RETRIES; i++) {
2010 			ESR_REG_RD(handle, ESR_INTERNAL_SIGNALS_REG, &val);
2011 			if ((val & ESR_SIG_P1_BITS_MASK) !=
2012 			    (ESR_SIG_SERDES_RDY0_P1 | ESR_SIG_DETECT0_P1 |
2013 			    ESR_SIG_XSERDES_RDY_P1 |
2014 			    ESR_SIG_XDETECT_P1_CH3 |
2015 			    ESR_SIG_XDETECT_P1_CH2 |
2016 			    ESR_SIG_XDETECT_P1_CH1 |
2017 			    ESR_SIG_XDETECT_P1_CH0))
2018 
2019 				NXGE_DELAY(SERDES_RDY_WT_INTERVAL);
2020 			else
2021 				break;
2022 		}
2023 
2024 		if (i == MAX_SERDES_RDY_RETRIES) {
2025 			/*
2026 			 * RDY signal stays low may due to the absent of the
2027 			 * external PHY, it is not an error condition.
2028 			 * But still print the message for the debugging
2029 			 * purpose when link stays down
2030 			 */
2031 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2032 			    "nxge_n2_kt_serdes_init: "
2033 			    "Serdes/signal for port<%d> not ready", portn));
2034 			goto done;
2035 		}
2036 	}
2037 done:
2038 
2039 	NXGE_DEBUG_MSG((nxgep, MAC_CTL,
2040 	    "<== nxge_n2_kt_serdes_init port<%d>", portn));
2041 
2042 	return (NXGE_OK);
2043 fail:
2044 	NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2045 	    "nxge_n2_serdes_init: Failed to initialize N2 serdes for port<%d>",
2046 	    portn));
2047 
2048 	return (status);
2049 }
2050 
2051 /* Initialize the Neptune Internal Serdes for 10G (Neptune only) */
2052 
2053 static nxge_status_t
nxge_neptune_10G_serdes_init(p_nxge_t nxgep)2054 nxge_neptune_10G_serdes_init(p_nxge_t nxgep)
2055 {
2056 	npi_handle_t		handle;
2057 	uint8_t			portn;
2058 	int			chan, i;
2059 	sr_rx_tx_ctrl_l_t	rx_tx_ctrl_l;
2060 	sr_rx_tx_ctrl_h_t	rx_tx_ctrl_h;
2061 	sr_glue_ctrl0_l_t	glue_ctrl0_l;
2062 	sr_glue_ctrl0_h_t	glue_ctrl0_h;
2063 	uint64_t		val;
2064 	uint16_t		val16l;
2065 	uint16_t		val16h;
2066 	nxge_status_t		status = NXGE_OK;
2067 
2068 	portn = nxgep->mac.portnum;
2069 
2070 	if ((portn != 0) && (portn != 1))
2071 		return (NXGE_OK);
2072 
2073 	NXGE_DEBUG_MSG((nxgep, MAC_CTL,
2074 	    "==> nxge_neptune_10G_serdes_init port<%d>", portn));
2075 	handle = nxgep->npi_handle;
2076 	switch (portn) {
2077 	case 0:
2078 		/* Reset Serdes */
2079 		ESR_REG_WR(handle, ESR_RESET_REG, ESR_RESET_0);
2080 		NXGE_DELAY(20);
2081 		ESR_REG_WR(handle, ESR_RESET_REG, 0x0);
2082 		NXGE_DELAY(2000);
2083 
2084 		/* Configure Serdes to 10G mode */
2085 		ESR_REG_WR(handle, ESR_0_PLL_CONFIG_REG,
2086 		    ESR_PLL_CFG_10G_SERDES);
2087 
2088 		ESR_REG_WR(handle, ESR_0_CONTROL_REG,
2089 		    ESR_CTL_EN_SYNCDET_0 | ESR_CTL_EN_SYNCDET_1 |
2090 		    ESR_CTL_EN_SYNCDET_2 | ESR_CTL_EN_SYNCDET_3 |
2091 		    (0x5 << ESR_CTL_OUT_EMPH_0_SHIFT) |
2092 		    (0x5 << ESR_CTL_OUT_EMPH_1_SHIFT) |
2093 		    (0x5 << ESR_CTL_OUT_EMPH_2_SHIFT) |
2094 		    (0x5 << ESR_CTL_OUT_EMPH_3_SHIFT) |
2095 		    (0x5 << ESR_CTL_OUT_EMPH_3_SHIFT) |
2096 		    (0x1 << ESR_CTL_LOSADJ_0_SHIFT) |
2097 		    (0x1 << ESR_CTL_LOSADJ_1_SHIFT) |
2098 		    (0x1 << ESR_CTL_LOSADJ_2_SHIFT) |
2099 		    (0x1 << ESR_CTL_LOSADJ_3_SHIFT));
2100 
2101 		/* Set Serdes0 Internal Loopback if necessary */
2102 		if (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes10g) {
2103 			ESR_REG_WR(handle,
2104 			    ESR_0_TEST_CONFIG_REG,
2105 			    ESR_PAD_LOOPBACK_CH3 |
2106 			    ESR_PAD_LOOPBACK_CH2 |
2107 			    ESR_PAD_LOOPBACK_CH1 |
2108 			    ESR_PAD_LOOPBACK_CH0);
2109 		} else {
2110 			ESR_REG_WR(handle, ESR_0_TEST_CONFIG_REG, 0);
2111 		}
2112 		break;
2113 	case 1:
2114 		/* Reset Serdes */
2115 		ESR_REG_WR(handle, ESR_RESET_REG, ESR_RESET_1);
2116 		NXGE_DELAY(20);
2117 		ESR_REG_WR(handle, ESR_RESET_REG, 0x0);
2118 		NXGE_DELAY(2000);
2119 
2120 		/* Configure Serdes to 10G mode */
2121 		ESR_REG_WR(handle, ESR_1_PLL_CONFIG_REG,
2122 		    ESR_PLL_CFG_10G_SERDES);
2123 
2124 		ESR_REG_WR(handle, ESR_1_CONTROL_REG,
2125 		    ESR_CTL_EN_SYNCDET_0 | ESR_CTL_EN_SYNCDET_1 |
2126 		    ESR_CTL_EN_SYNCDET_2 | ESR_CTL_EN_SYNCDET_3 |
2127 		    (0x5 << ESR_CTL_OUT_EMPH_0_SHIFT) |
2128 		    (0x5 << ESR_CTL_OUT_EMPH_1_SHIFT) |
2129 		    (0x5 << ESR_CTL_OUT_EMPH_2_SHIFT) |
2130 		    (0x5 << ESR_CTL_OUT_EMPH_3_SHIFT) |
2131 		    (0x5 << ESR_CTL_OUT_EMPH_3_SHIFT) |
2132 		    (0x1 << ESR_CTL_LOSADJ_0_SHIFT) |
2133 		    (0x1 << ESR_CTL_LOSADJ_1_SHIFT) |
2134 		    (0x1 << ESR_CTL_LOSADJ_2_SHIFT) |
2135 		    (0x1 << ESR_CTL_LOSADJ_3_SHIFT));
2136 
2137 		/* Set Serdes1 Internal Loopback if necessary */
2138 		if (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes10g) {
2139 			ESR_REG_WR(handle, ESR_1_TEST_CONFIG_REG,
2140 			    ESR_PAD_LOOPBACK_CH3 | ESR_PAD_LOOPBACK_CH2 |
2141 			    ESR_PAD_LOOPBACK_CH1 | ESR_PAD_LOOPBACK_CH0);
2142 		} else {
2143 			ESR_REG_WR(handle, ESR_1_TEST_CONFIG_REG, 0);
2144 		}
2145 		break;
2146 	default:
2147 		/* Nothing to do here */
2148 		goto done;
2149 	}
2150 
2151 	/* init TX RX channels */
2152 	for (chan = 0; chan < 4; chan++) {
2153 		if ((status = nxge_mdio_read(nxgep, portn,
2154 		    ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_CONTROL_L_ADDR(chan),
2155 		    &rx_tx_ctrl_l.value)) != NXGE_OK)
2156 			goto fail;
2157 		if ((status = nxge_mdio_read(nxgep, portn,
2158 		    ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_CONTROL_H_ADDR(chan),
2159 		    &rx_tx_ctrl_h.value)) != NXGE_OK)
2160 			goto fail;
2161 		if ((status = nxge_mdio_read(nxgep, portn,
2162 		    ESR_NEPTUNE_DEV_ADDR, ESR_NEP_GLUE_CONTROL0_L_ADDR(chan),
2163 		    &glue_ctrl0_l.value)) != NXGE_OK)
2164 			goto fail;
2165 		if ((status = nxge_mdio_read(nxgep, portn,
2166 		    ESR_NEPTUNE_DEV_ADDR, ESR_NEP_GLUE_CONTROL0_H_ADDR(chan),
2167 		    &glue_ctrl0_h.value)) != NXGE_OK)
2168 			goto fail;
2169 		rx_tx_ctrl_l.bits.enstretch = 1;
2170 		rx_tx_ctrl_h.bits.vmuxlo = 2;
2171 		rx_tx_ctrl_h.bits.vpulselo = 2;
2172 		glue_ctrl0_l.bits.rxlosenable = 1;
2173 		glue_ctrl0_l.bits.samplerate = 0xF;
2174 		glue_ctrl0_l.bits.thresholdcount = 0xFF;
2175 		glue_ctrl0_h.bits.bitlocktime = BITLOCKTIME_300_CYCLES;
2176 		if ((status = nxge_mdio_write(nxgep, portn,
2177 		    ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_CONTROL_L_ADDR(chan),
2178 		    rx_tx_ctrl_l.value)) != NXGE_OK)
2179 			goto fail;
2180 		if ((status = nxge_mdio_write(nxgep, portn,
2181 		    ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_CONTROL_H_ADDR(chan),
2182 		    rx_tx_ctrl_h.value)) != NXGE_OK)
2183 			goto fail;
2184 		if ((status = nxge_mdio_write(nxgep, portn,
2185 		    ESR_NEPTUNE_DEV_ADDR, ESR_NEP_GLUE_CONTROL0_L_ADDR(chan),
2186 		    glue_ctrl0_l.value)) != NXGE_OK)
2187 			goto fail;
2188 		if ((status = nxge_mdio_write(nxgep, portn,
2189 		    ESR_NEPTUNE_DEV_ADDR, ESR_NEP_GLUE_CONTROL0_H_ADDR(chan),
2190 		    glue_ctrl0_h.value)) != NXGE_OK)
2191 			goto fail;
2192 		}
2193 
2194 	/* Apply Tx core reset */
2195 	if ((status = nxge_mdio_write(nxgep, portn,
2196 	    ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_RESET_CONTROL_L_ADDR(),
2197 	    (uint16_t)0)) != NXGE_OK)
2198 		goto fail;
2199 
2200 	if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR,
2201 	    ESR_NEP_RX_TX_RESET_CONTROL_H_ADDR(), (uint16_t)0xffff)) !=
2202 	    NXGE_OK)
2203 		goto fail;
2204 
2205 	NXGE_DELAY(200);
2206 
2207 	/* Apply Rx core reset */
2208 	if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR,
2209 	    ESR_NEP_RX_TX_RESET_CONTROL_L_ADDR(), (uint16_t)0xffff)) !=
2210 	    NXGE_OK)
2211 		goto fail;
2212 
2213 	NXGE_DELAY(200);
2214 	if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR,
2215 	    ESR_NEP_RX_TX_RESET_CONTROL_H_ADDR(), (uint16_t)0)) != NXGE_OK)
2216 		goto fail;
2217 
2218 	NXGE_DELAY(200);
2219 	if ((status = nxge_mdio_read(nxgep, portn,
2220 	    ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_RESET_CONTROL_L_ADDR(),
2221 	    &val16l)) != NXGE_OK)
2222 		goto fail;
2223 	if ((status = nxge_mdio_read(nxgep, portn, ESR_NEPTUNE_DEV_ADDR,
2224 	    ESR_NEP_RX_TX_RESET_CONTROL_H_ADDR(), &val16h)) != NXGE_OK)
2225 		goto fail;
2226 	if ((val16l != 0) || (val16h != 0)) {
2227 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2228 		    "Failed to reset port<%d> XAUI Serdes "
2229 		    "(val16l 0x%x val16h 0x%x)",
2230 		    portn, val16l, val16h));
2231 	}
2232 
2233 	if (portn == 0) {
2234 		/* Wait for serdes to be ready */
2235 		for (i = 0; i < MAX_SERDES_RDY_RETRIES; i++) {
2236 			ESR_REG_RD(handle, ESR_INTERNAL_SIGNALS_REG, &val);
2237 			if ((val & ESR_SIG_P0_BITS_MASK) !=
2238 			    (ESR_SIG_SERDES_RDY0_P0 | ESR_SIG_DETECT0_P0 |
2239 			    ESR_SIG_XSERDES_RDY_P0 |
2240 			    ESR_SIG_XDETECT_P0_CH3 |
2241 			    ESR_SIG_XDETECT_P0_CH2 |
2242 			    ESR_SIG_XDETECT_P0_CH1 |
2243 			    ESR_SIG_XDETECT_P0_CH0))
2244 
2245 				NXGE_DELAY(SERDES_RDY_WT_INTERVAL);
2246 			else
2247 				break;
2248 		}
2249 
2250 		if (i == MAX_SERDES_RDY_RETRIES) {
2251 			/*
2252 			 * RDY signal stays low may due to the absent of the
2253 			 * external PHY, it is not an error condition. But still
2254 			 * print the message for the debugging purpose when link
2255 			 * stays down
2256 			 */
2257 			NXGE_DEBUG_MSG((nxgep, MAC_CTL,
2258 			    "nxge_neptune_10G_serdes_init: "
2259 			    "Serdes/signal for port<%d> not ready", portn));
2260 				goto done;
2261 		}
2262 	} else if (portn == 1) {
2263 		/* Wait for serdes to be ready */
2264 		for (i = 0; i < MAX_SERDES_RDY_RETRIES; i++) {
2265 			ESR_REG_RD(handle, ESR_INTERNAL_SIGNALS_REG, &val);
2266 			if ((val & ESR_SIG_P1_BITS_MASK) !=
2267 			    (ESR_SIG_SERDES_RDY0_P1 | ESR_SIG_DETECT0_P1 |
2268 			    ESR_SIG_XSERDES_RDY_P1 |
2269 			    ESR_SIG_XDETECT_P1_CH3 |
2270 			    ESR_SIG_XDETECT_P1_CH2 |
2271 			    ESR_SIG_XDETECT_P1_CH1 |
2272 			    ESR_SIG_XDETECT_P1_CH0))
2273 
2274 				NXGE_DELAY(SERDES_RDY_WT_INTERVAL);
2275 			else
2276 				break;
2277 		}
2278 
2279 		if (i == MAX_SERDES_RDY_RETRIES) {
2280 			/*
2281 			 * RDY signal stays low may due to the absent of the
2282 			 * external PHY, it is not an error condition. But still
2283 			 * print the message for the debugging purpose when link
2284 			 * stays down
2285 			 */
2286 			NXGE_DEBUG_MSG((nxgep, MAC_CTL,
2287 			    "nxge_neptune_10G_serdes_init: "
2288 			    "Serdes/signal for port<%d> not ready", portn));
2289 				goto done;
2290 		}
2291 	}
2292 
2293 done:
2294 	NXGE_DEBUG_MSG((nxgep, MAC_CTL,
2295 	    "<== nxge_neptune_10G_serdes_init port<%d>", portn));
2296 
2297 	return (NXGE_OK);
2298 fail:
2299 	NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2300 	    "nxge_neptune_10G_serdes_init: "
2301 	    "Failed to initialize Neptune serdes for port<%d>", portn));
2302 
2303 	return (status);
2304 }
2305 
2306 /* Initialize Neptune Internal Serdes for 1G (Neptune only) */
2307 
2308 static nxge_status_t
nxge_1G_serdes_init(p_nxge_t nxgep)2309 nxge_1G_serdes_init(p_nxge_t nxgep)
2310 {
2311 	npi_handle_t		handle;
2312 	uint8_t			portn;
2313 	int			chan;
2314 	sr_rx_tx_ctrl_l_t	rx_tx_ctrl_l;
2315 	sr_rx_tx_ctrl_h_t	rx_tx_ctrl_h;
2316 	sr_glue_ctrl0_l_t	glue_ctrl0_l;
2317 	sr_glue_ctrl0_h_t	glue_ctrl0_h;
2318 	uint64_t		val;
2319 	uint16_t		val16l;
2320 	uint16_t		val16h;
2321 	nxge_status_t		status = NXGE_OK;
2322 
2323 	portn = nxgep->mac.portnum;
2324 
2325 	NXGE_DEBUG_MSG((nxgep, MAC_CTL,
2326 	    "==> nxge_1G_serdes_init port<%d>", portn));
2327 
2328 	handle = nxgep->npi_handle;
2329 
2330 	switch (portn) {
2331 	case 0:
2332 		/* Assert the reset register */
2333 		ESR_REG_RD(handle, ESR_RESET_REG, &val);
2334 		val |= ESR_RESET_0;
2335 		ESR_REG_WR(handle, ESR_RESET_REG, val);
2336 
2337 		/* Set the PLL register to 0x79 */
2338 		ESR_REG_WR(handle, ESR_0_PLL_CONFIG_REG,
2339 		    ESR_PLL_CFG_1G_SERDES);
2340 
2341 		/* Set the control register to 0x249249f */
2342 		ESR_REG_WR(handle, ESR_0_CONTROL_REG, ESR_CTL_1G_SERDES);
2343 
2344 		/* Set Serdes0 Internal Loopback if necessary */
2345 		if (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes1000) {
2346 			/* Set pad loopback modes 0xaa */
2347 			ESR_REG_WR(handle, ESR_0_TEST_CONFIG_REG,
2348 			    ESR_TSTCFG_LBTEST_PAD);
2349 		} else {
2350 			ESR_REG_WR(handle, ESR_0_TEST_CONFIG_REG, 0);
2351 		}
2352 
2353 		/* Deassert the reset register */
2354 		ESR_REG_RD(handle, ESR_RESET_REG, &val);
2355 		val &= ~ESR_RESET_0;
2356 		ESR_REG_WR(handle, ESR_RESET_REG, val);
2357 		break;
2358 
2359 	case 1:
2360 		/* Assert the reset register */
2361 		ESR_REG_RD(handle, ESR_RESET_REG, &val);
2362 		val |= ESR_RESET_1;
2363 		ESR_REG_WR(handle, ESR_RESET_REG, val);
2364 
2365 		/* Set PLL register to 0x79 */
2366 		ESR_REG_WR(handle, ESR_1_PLL_CONFIG_REG,
2367 		    ESR_PLL_CFG_1G_SERDES);
2368 
2369 		/* Set the control register to 0x249249f */
2370 		ESR_REG_WR(handle, ESR_1_CONTROL_REG, ESR_CTL_1G_SERDES);
2371 
2372 		/* Set Serdes1 Internal Loopback if necessary */
2373 		if (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes1000) {
2374 			/* Set pad loopback mode 0xaa */
2375 			ESR_REG_WR(handle, ESR_1_TEST_CONFIG_REG,
2376 			    ESR_TSTCFG_LBTEST_PAD);
2377 		} else {
2378 			ESR_REG_WR(handle, ESR_1_TEST_CONFIG_REG, 0);
2379 		}
2380 
2381 		/* Deassert the reset register */
2382 		ESR_REG_RD(handle, ESR_RESET_REG, &val);
2383 		val &= ~ESR_RESET_1;
2384 		ESR_REG_WR(handle, ESR_RESET_REG, val);
2385 		break;
2386 
2387 	default:
2388 		/* Nothing to do here */
2389 		goto done;
2390 	}
2391 
2392 	/* init TX RX channels */
2393 	for (chan = 0; chan < 4; chan++) {
2394 		if ((status = nxge_mdio_read(nxgep, portn,
2395 		    ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_CONTROL_L_ADDR(chan),
2396 		    &rx_tx_ctrl_l.value)) != NXGE_OK) {
2397 			goto fail;
2398 		}
2399 		if ((status = nxge_mdio_read(nxgep, portn,
2400 		    ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_CONTROL_H_ADDR(chan),
2401 		    &rx_tx_ctrl_h.value)) != NXGE_OK) {
2402 			goto fail;
2403 		}
2404 		if ((status = nxge_mdio_read(nxgep, portn,
2405 		    ESR_NEPTUNE_DEV_ADDR, ESR_NEP_GLUE_CONTROL0_L_ADDR(chan),
2406 		    &glue_ctrl0_l.value)) != NXGE_OK) {
2407 			goto fail;
2408 		}
2409 		if ((status = nxge_mdio_read(nxgep, portn,
2410 		    ESR_NEPTUNE_DEV_ADDR, ESR_NEP_GLUE_CONTROL0_H_ADDR(chan),
2411 		    &glue_ctrl0_h.value)) != NXGE_OK) {
2412 			goto fail;
2413 		}
2414 
2415 		rx_tx_ctrl_l.bits.enstretch = 1;
2416 		rx_tx_ctrl_h.bits.vmuxlo = 2;
2417 		rx_tx_ctrl_h.bits.vpulselo = 2;
2418 		glue_ctrl0_l.bits.rxlosenable = 1;
2419 		glue_ctrl0_l.bits.samplerate = 0xF;
2420 		glue_ctrl0_l.bits.thresholdcount = 0xFF;
2421 		glue_ctrl0_h.bits.bitlocktime = BITLOCKTIME_300_CYCLES;
2422 		if ((status = nxge_mdio_write(nxgep, portn,
2423 		    ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_CONTROL_L_ADDR(chan),
2424 		    rx_tx_ctrl_l.value)) != NXGE_OK) {
2425 			goto fail;
2426 		}
2427 		if ((status = nxge_mdio_write(nxgep, portn,
2428 		    ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_CONTROL_H_ADDR(chan),
2429 		    rx_tx_ctrl_h.value)) != NXGE_OK) {
2430 			goto fail;
2431 		}
2432 		if ((status = nxge_mdio_write(nxgep, portn,
2433 		    ESR_NEPTUNE_DEV_ADDR, ESR_NEP_GLUE_CONTROL0_L_ADDR(chan),
2434 		    glue_ctrl0_l.value)) != NXGE_OK) {
2435 			goto fail;
2436 		}
2437 		if ((status = nxge_mdio_write(nxgep, portn,
2438 		    ESR_NEPTUNE_DEV_ADDR, ESR_NEP_GLUE_CONTROL0_H_ADDR(chan),
2439 		    glue_ctrl0_h.value)) != NXGE_OK) {
2440 			goto fail;
2441 		}
2442 	}
2443 
2444 	if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR,
2445 	    ESR_NEP_RX_POWER_CONTROL_L_ADDR(), 0xfff)) != NXGE_OK) {
2446 		goto fail;
2447 	}
2448 	if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR,
2449 	    ESR_NEP_RX_POWER_CONTROL_H_ADDR(), 0xfff)) != NXGE_OK) {
2450 		goto fail;
2451 	}
2452 	if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR,
2453 	    ESR_NEP_TX_POWER_CONTROL_L_ADDR(), 0x70)) != NXGE_OK) {
2454 		goto fail;
2455 	}
2456 	if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR,
2457 	    ESR_NEP_TX_POWER_CONTROL_H_ADDR(), 0xfff)) != NXGE_OK) {
2458 		goto fail;
2459 	}
2460 
2461 	/* Apply Tx core reset */
2462 	if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR,
2463 	    ESR_NEP_RX_TX_RESET_CONTROL_L_ADDR(), (uint16_t)0)) != NXGE_OK) {
2464 		goto fail;
2465 	}
2466 
2467 	if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR,
2468 	    ESR_NEP_RX_TX_RESET_CONTROL_H_ADDR(), (uint16_t)0xffff)) !=
2469 	    NXGE_OK) {
2470 		goto fail;
2471 	}
2472 
2473 	NXGE_DELAY(200);
2474 
2475 	/* Apply Rx core reset */
2476 	if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR,
2477 	    ESR_NEP_RX_TX_RESET_CONTROL_L_ADDR(), (uint16_t)0xffff)) !=
2478 	    NXGE_OK) {
2479 		goto fail;
2480 	}
2481 
2482 	NXGE_DELAY(200);
2483 	if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR,
2484 	    ESR_NEP_RX_TX_RESET_CONTROL_H_ADDR(), (uint16_t)0)) != NXGE_OK) {
2485 		goto fail;
2486 	}
2487 
2488 	NXGE_DELAY(200);
2489 	if ((status = nxge_mdio_read(nxgep, portn, ESR_NEPTUNE_DEV_ADDR,
2490 	    ESR_NEP_RX_TX_RESET_CONTROL_L_ADDR(), &val16l)) != NXGE_OK) {
2491 		goto fail;
2492 	}
2493 	if ((status = nxge_mdio_read(nxgep, portn, ESR_NEPTUNE_DEV_ADDR,
2494 	    ESR_NEP_RX_TX_RESET_CONTROL_H_ADDR(), &val16h)) != NXGE_OK) {
2495 		goto fail;
2496 	}
2497 	if ((val16l != 0) || (val16h != 0)) {
2498 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2499 		    "Failed to reset port<%d> XAUI Serdes "
2500 		    "(val16l 0x%x val16h 0x%x)", portn, val16l, val16h));
2501 		status = NXGE_ERROR;
2502 		goto fail;
2503 	}
2504 
2505 	NXGE_DELAY(200);
2506 	ESR_REG_RD(handle, ESR_INTERNAL_SIGNALS_REG, &val);
2507 	NXGE_DEBUG_MSG((nxgep, MAC_CTL,
2508 	    "nxge_neptune_serdes_init: read internal signal reg port<%d> "
2509 	    "val 0x%x", portn, val));
2510 	if (portn == 0) {
2511 		if ((val & ESR_SIG_P0_BITS_MASK_1G) !=
2512 		    (ESR_SIG_SERDES_RDY0_P0 | ESR_SIG_DETECT0_P0)) {
2513 			/*
2514 			 * RDY signal stays low may due to the absent of the
2515 			 * external PHY, it is not an error condition. But still
2516 			 * print the message for the debugging purpose when link
2517 			 * stays down
2518 			 */
2519 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2520 			    "nxge_neptune_1G_serdes_init: "
2521 			    "Serdes/signal for port<%d> not ready", portn));
2522 			goto done;
2523 		}
2524 	} else if (portn == 1) {
2525 		if ((val & ESR_SIG_P1_BITS_MASK_1G) !=
2526 		    (ESR_SIG_SERDES_RDY0_P1 | ESR_SIG_DETECT0_P1)) {
2527 			/*
2528 			 * RDY signal stays low may due to the absent of the
2529 			 * external PHY, it is not an error condition. But still
2530 			 * print the message for the debugging purpose when link
2531 			 * stays down
2532 			 */
2533 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2534 			    "nxge_neptune_1G_serdes_init: "
2535 			    "Serdes/signal for port<%d> not ready", portn));
2536 			goto done;
2537 
2538 		}
2539 	}
2540 done:
2541 
2542 	NXGE_DEBUG_MSG((nxgep, MAC_CTL,
2543 	    "<== nxge_1G_serdes_init port<%d>", portn));
2544 	return (NXGE_OK);
2545 fail:
2546 	NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2547 	    "nxge_1G_serdes_init: "
2548 	    "Failed to initialize Neptune serdes for port<%d>",
2549 	    portn));
2550 
2551 	return (status);
2552 }
2553 
2554 #define	NXGE_SET_PHY_TUNABLES(nxgep, phy_port, stat)			\
2555 {									\
2556 	int i;								\
2557 									\
2558 	if (nxgep->phy_prop.cnt > 0) {					\
2559 		for (i = 0; i < nxgep->phy_prop.cnt; i++) {		\
2560 			if ((stat = nxge_mdio_write(nxgep, phy_port,	\
2561 			    nxgep->phy_prop.arr[i].dev,			\
2562 			    nxgep->phy_prop.arr[i].reg,			\
2563 			    nxgep->phy_prop.arr[i].val)) != NXGE_OK) {	\
2564 				break;					\
2565 			}						\
2566 			NXGE_DEBUG_MSG((nxgep, MAC_CTL,			\
2567 			    "From OBP, write<dev.reg.val> = "		\
2568 			    "<0x%x.0x%x.0x%x>",				\
2569 			    nxgep->phy_prop.arr[i].dev,			\
2570 			    nxgep->phy_prop.arr[i].reg,			\
2571 			    nxgep->phy_prop.arr[i].val));		\
2572 		}							\
2573 	}								\
2574 }
2575 
2576 /* Initialize the BCM 8704 xcvr */
2577 
2578 static nxge_status_t
nxge_BCM8704_xcvr_init(p_nxge_t nxgep)2579 nxge_BCM8704_xcvr_init(p_nxge_t nxgep)
2580 {
2581 	uint16_t		val;
2582 #ifdef	NXGE_DEBUG
2583 	uint8_t			portn;
2584 	uint16_t		val1;
2585 #endif
2586 	uint8_t			phy_port_addr;
2587 	pmd_tx_control_t	tx_ctl;
2588 	control_t		ctl;
2589 	phyxs_control_t		phyxs_ctl;
2590 	pcs_control_t		pcs_ctl;
2591 	uint32_t		delay = 0;
2592 	optics_dcntr_t		op_ctr;
2593 	nxge_status_t		status = NXGE_OK;
2594 #ifdef	NXGE_DEBUG
2595 	portn = nxgep->mac.portnum;
2596 #endif
2597 
2598 	NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_BCM8704_xcvr_init: port<%d>",
2599 	    portn));
2600 
2601 	phy_port_addr = nxgep->statsp->mac_stats.xcvr_portn;
2602 
2603 	/* Reset the transceiver */
2604 	if ((status = nxge_mdio_read(nxgep, phy_port_addr, BCM8704_PHYXS_ADDR,
2605 	    BCM8704_PHYXS_CONTROL_REG, &phyxs_ctl.value)) != NXGE_OK)
2606 		goto fail;
2607 
2608 	phyxs_ctl.bits.reset = 1;
2609 	if ((status = nxge_mdio_write(nxgep, phy_port_addr, BCM8704_PHYXS_ADDR,
2610 	    BCM8704_PHYXS_CONTROL_REG, phyxs_ctl.value)) != NXGE_OK)
2611 		goto fail;
2612 
2613 	do {
2614 		drv_usecwait(500);
2615 		if ((status = nxge_mdio_read(nxgep, phy_port_addr,
2616 		    BCM8704_PHYXS_ADDR, BCM8704_PHYXS_CONTROL_REG,
2617 		    &phyxs_ctl.value)) != NXGE_OK)
2618 			goto fail;
2619 		delay++;
2620 	} while ((phyxs_ctl.bits.reset) && (delay < 100));
2621 	if (delay == 100) {
2622 		NXGE_DEBUG_MSG((nxgep, MAC_CTL, "nxge_xcvr_init: "
2623 		    "failed to reset Transceiver on port<%d>", portn));
2624 		status = NXGE_ERROR;
2625 		goto fail;
2626 	}
2627 
2628 	/* Set to 0x7FBF */
2629 	ctl.value = 0;
2630 	ctl.bits.res1 = 0x3F;
2631 	ctl.bits.optxon_lvl = 1;
2632 	ctl.bits.oprxflt_lvl = 1;
2633 	ctl.bits.optrxlos_lvl = 1;
2634 	ctl.bits.optxflt_lvl = 1;
2635 	ctl.bits.opprflt_lvl = 1;
2636 	ctl.bits.obtmpflt_lvl = 1;
2637 	ctl.bits.opbiasflt_lvl = 1;
2638 	ctl.bits.optxrst_lvl = 1;
2639 	if ((status = nxge_mdio_write(nxgep, phy_port_addr,
2640 	    BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL_REG, ctl.value))
2641 	    != NXGE_OK)
2642 		goto fail;
2643 
2644 	/* Set to 0x164 */
2645 	tx_ctl.value = 0;
2646 	tx_ctl.bits.tsck_lpwren = 1;
2647 	tx_ctl.bits.tx_dac_txck = 0x2;
2648 	tx_ctl.bits.tx_dac_txd = 0x1;
2649 	tx_ctl.bits.xfp_clken = 1;
2650 	if ((status = nxge_mdio_write(nxgep, phy_port_addr,
2651 	    BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL_REG,
2652 	    tx_ctl.value)) != NXGE_OK)
2653 		goto fail;
2654 	/*
2655 	 * According to Broadcom's instruction, SW needs to read
2656 	 * back these registers twice after written.
2657 	 */
2658 	if ((status = nxge_mdio_read(nxgep, phy_port_addr,
2659 	    BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL_REG, &val))
2660 	    != NXGE_OK)
2661 		goto fail;
2662 
2663 	if ((status = nxge_mdio_read(nxgep, phy_port_addr,
2664 	    BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL_REG, &val))
2665 	    != NXGE_OK)
2666 		goto fail;
2667 
2668 	if ((status = nxge_mdio_read(nxgep, phy_port_addr,
2669 	    BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL_REG, &val))
2670 	    != NXGE_OK)
2671 		goto fail;
2672 
2673 	if ((status = nxge_mdio_read(nxgep, phy_port_addr,
2674 	    BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL_REG, &val))
2675 	    != NXGE_OK)
2676 		goto fail;
2677 
2678 	/* Enable Tx and Rx LEDs to be driven by traffic */
2679 	if ((status = nxge_mdio_read(nxgep, phy_port_addr,
2680 	    BCM8704_USER_DEV3_ADDR, BCM8704_USER_OPTICS_DIGITAL_CTRL_REG,
2681 	    &op_ctr.value)) != NXGE_OK)
2682 		goto fail;
2683 	if (NXGE_IS_XAUI_PLATFORM(nxgep)) {
2684 		op_ctr.bits.gpio_sel = 0x1;
2685 	} else {
2686 		op_ctr.bits.gpio_sel = 0x3;
2687 	}
2688 	if ((status = nxge_mdio_write(nxgep, phy_port_addr,
2689 	    BCM8704_USER_DEV3_ADDR, BCM8704_USER_OPTICS_DIGITAL_CTRL_REG,
2690 	    op_ctr.value)) != NXGE_OK)
2691 		goto fail;
2692 
2693 	NXGE_DELAY(1000000);
2694 
2695 	/*
2696 	 * Set XAUI link tunables from OBP if present.
2697 	 */
2698 	NXGE_SET_PHY_TUNABLES(nxgep, phy_port_addr, status);
2699 	if (status != NXGE_OK) {
2700 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2701 		    "nxge_BCM8704_xcvr_init: Failed setting PHY tunables"));
2702 		goto fail;
2703 	}
2704 
2705 	/* Set BCM8704 Internal Loopback mode if necessary */
2706 	if ((status = nxge_mdio_read(nxgep, phy_port_addr,
2707 	    BCM8704_PCS_DEV_ADDR, BCM8704_PCS_CONTROL_REG, &pcs_ctl.value))
2708 	    != NXGE_OK)
2709 		goto fail;
2710 	if (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy10g)
2711 		pcs_ctl.bits.loopback = 1;
2712 	else
2713 		pcs_ctl.bits.loopback = 0;
2714 	if ((status = nxge_mdio_write(nxgep, phy_port_addr,
2715 	    BCM8704_PCS_DEV_ADDR, BCM8704_PCS_CONTROL_REG, pcs_ctl.value))
2716 	    != NXGE_OK)
2717 		goto fail;
2718 
2719 	status = nxge_mdio_read(nxgep, phy_port_addr, 0x1, 0xA, &val);
2720 	if (status != NXGE_OK)
2721 		goto fail;
2722 	NXGE_DEBUG_MSG((nxgep, MAC_CTL,
2723 	    "BCM8704 port<%d> Dev 1 Reg 0xA = 0x%x\n", portn, val));
2724 	status = nxge_mdio_read(nxgep, phy_port_addr, 0x3, 0x20, &val);
2725 	if (status != NXGE_OK)
2726 		goto fail;
2727 	NXGE_DEBUG_MSG((nxgep, MAC_CTL,
2728 	    "BCM8704 port<%d> Dev 3 Reg 0x20 = 0x%x\n", portn, val));
2729 	status = nxge_mdio_read(nxgep, phy_port_addr, 0x4, 0x18, &val);
2730 	if (status != NXGE_OK)
2731 		goto fail;
2732 	NXGE_DEBUG_MSG((nxgep, MAC_CTL,
2733 	    "BCM8704 port<%d> Dev 4 Reg 0x18 = 0x%x\n", portn, val));
2734 
2735 #ifdef	NXGE_DEBUG
2736 	/* Diagnose link issue if link is not up */
2737 	status = nxge_mdio_read(nxgep, phy_port_addr, BCM8704_USER_DEV3_ADDR,
2738 	    BCM8704_USER_ANALOG_STATUS0_REG,
2739 	    &val);
2740 	if (status != NXGE_OK)
2741 		goto fail;
2742 
2743 	status = nxge_mdio_read(nxgep, phy_port_addr,
2744 	    BCM8704_USER_DEV3_ADDR, BCM8704_USER_ANALOG_STATUS0_REG, &val);
2745 	if (status != NXGE_OK)
2746 		goto fail;
2747 
2748 	status = nxge_mdio_read(nxgep, phy_port_addr,
2749 	    BCM8704_USER_DEV3_ADDR, BCM8704_USER_TX_ALARM_STATUS_REG, &val1);
2750 	if (status != NXGE_OK)
2751 		goto fail;
2752 
2753 	status = nxge_mdio_read(nxgep, phy_port_addr,
2754 	    BCM8704_USER_DEV3_ADDR, BCM8704_USER_TX_ALARM_STATUS_REG, &val1);
2755 	if (status != NXGE_OK)
2756 		goto fail;
2757 
2758 	if (val != 0x3FC) {
2759 		if ((val == 0x43BC) && (val1 != 0)) {
2760 			NXGE_DEBUG_MSG((nxgep, MAC_CTL,
2761 			    "Cable not connected to peer or bad"
2762 			    " cable on port<%d>\n", portn));
2763 		} else if (val == 0x639C) {
2764 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2765 			    "Optical module (XFP) is bad or absent"
2766 			    " on port<%d>\n", portn));
2767 		}
2768 	}
2769 #endif
2770 
2771 	NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_BCM8704_xcvr_init: port<%d>",
2772 	    portn));
2773 	return (NXGE_OK);
2774 
2775 fail:
2776 	NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2777 	    "nxge_BCM8704_xcvr_init: failed to initialize transceiver for "
2778 	    "port<%d>", nxgep->mac.portnum));
2779 	return (NXGE_ERROR);
2780 }
2781 
2782 /* Initialize the BCM 8706 Transceiver */
2783 
2784 static nxge_status_t
nxge_BCM8706_xcvr_init(p_nxge_t nxgep)2785 nxge_BCM8706_xcvr_init(p_nxge_t nxgep)
2786 {
2787 	uint8_t			phy_port_addr;
2788 	phyxs_control_t		phyxs_ctl;
2789 	pcs_control_t		pcs_ctl;
2790 	uint32_t		delay = 0;
2791 	optics_dcntr_t		op_ctr;
2792 	nxge_status_t		status = NXGE_OK;
2793 #ifdef	NXGE_DEBUG
2794 	uint8_t			portn = nxgep->mac.portnum;
2795 #endif
2796 
2797 	NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_BCM8706_xcvr_init: port<%d>",
2798 	    portn));
2799 
2800 	phy_port_addr = nxgep->statsp->mac_stats.xcvr_portn;
2801 
2802 	/* Reset the transceiver */
2803 	if ((status = nxge_mdio_read(nxgep, phy_port_addr, BCM8704_PHYXS_ADDR,
2804 	    BCM8704_PHYXS_CONTROL_REG, &phyxs_ctl.value)) != NXGE_OK)
2805 		goto fail;
2806 
2807 	phyxs_ctl.bits.reset = 1;
2808 	if ((status = nxge_mdio_write(nxgep, phy_port_addr, BCM8704_PHYXS_ADDR,
2809 	    BCM8704_PHYXS_CONTROL_REG, phyxs_ctl.value)) != NXGE_OK)
2810 		goto fail;
2811 	do {
2812 		drv_usecwait(500);
2813 		if ((status = nxge_mdio_read(nxgep, phy_port_addr,
2814 		    BCM8704_PHYXS_ADDR, BCM8704_PHYXS_CONTROL_REG,
2815 		    &phyxs_ctl.value)) != NXGE_OK)
2816 			goto fail;
2817 		delay++;
2818 	} while ((phyxs_ctl.bits.reset) && (delay < 100));
2819 
2820 	if (delay == 100) {
2821 		NXGE_DEBUG_MSG((nxgep, MAC_CTL, "nxge_xcvr_init: "
2822 		    "failed to reset Transceiver on port<%d>", portn));
2823 		status = NXGE_ERROR;
2824 		goto fail;
2825 	}
2826 
2827 	NXGE_DELAY(1000000);
2828 
2829 	/*
2830 	 * Set XAUI link tunables from OBP if present.
2831 	 */
2832 	NXGE_SET_PHY_TUNABLES(nxgep, phy_port_addr, status);
2833 	if (status != NXGE_OK) {
2834 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2835 		    "nxge_BCM8706_xcvr_init: Failed setting PHY tunables"));
2836 		goto fail;
2837 	}
2838 
2839 	/* Set BCM8706 Internal Loopback mode if necessary */
2840 	if ((status = nxge_mdio_read(nxgep, phy_port_addr,
2841 	    BCM8704_PCS_DEV_ADDR, BCM8704_PCS_CONTROL_REG, &pcs_ctl.value))
2842 	    != NXGE_OK)
2843 		goto fail;
2844 	if (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy10g)
2845 		pcs_ctl.bits.loopback = 1;
2846 	else
2847 		pcs_ctl.bits.loopback = 0;
2848 	if ((status = nxge_mdio_write(nxgep, phy_port_addr,
2849 	    BCM8704_PCS_DEV_ADDR, BCM8704_PCS_CONTROL_REG, pcs_ctl.value))
2850 	    != NXGE_OK)
2851 		goto fail;
2852 
2853 	/* Enable Tx and Rx LEDs to be driven by traffic */
2854 	if ((status = nxge_mdio_read(nxgep, phy_port_addr,
2855 	    BCM8704_USER_DEV3_ADDR, BCM8704_USER_OPTICS_DIGITAL_CTRL_REG,
2856 	    &op_ctr.value)) != NXGE_OK)
2857 		goto fail;
2858 	op_ctr.bits.gpio_sel = 0x3;
2859 	op_ctr.bits.res2 = 0x1;
2860 
2861 	if ((status = nxge_mdio_write(nxgep, phy_port_addr,
2862 	    BCM8704_USER_DEV3_ADDR, BCM8704_USER_OPTICS_DIGITAL_CTRL_REG,
2863 	    op_ctr.value)) != NXGE_OK)
2864 		goto fail;
2865 
2866 	NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_BCM8706_xcvr_init: port<%d>",
2867 	    portn));
2868 	return (NXGE_OK);
2869 
2870 fail:
2871 	NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2872 	    "nxge_BCM8706_xcvr_init: failed to initialize transceiver for "
2873 	    "port<%d>", nxgep->mac.portnum));
2874 	return (status);
2875 }
2876 
2877 static int
nxge_nlp2020_i2c_read(p_nxge_t nxgep,uint8_t ctrl_port,uint16_t address,uint16_t reg,uint8_t * data)2878 nxge_nlp2020_i2c_read(p_nxge_t nxgep, uint8_t ctrl_port, uint16_t address,
2879     uint16_t reg, uint8_t *data)
2880 {
2881 	int  phy_dev, phy_reg;
2882 	uint16_t phy_data = 0;
2883 	uint16_t stat;
2884 	uint8_t count = 100;
2885 
2886 	/*
2887 	 * NLP2020_I2C_SNOOP_ADDR_REG [15:9][1] - Address
2888 	 * NLP2020_I2C_SNOOP_ADDR_REG[7:0] - register in the xcvr's i2c
2889 	 */
2890 	phy_dev = NLP2020_I2C_SNOOP_DEV_ADDR;
2891 	phy_reg = NLP2020_I2C_SNOOP_ADDR_REG;
2892 	phy_data = ((address + 1) << NLP2020_XCVR_I2C_ADDR_SH) | reg;
2893 	if (nxge_mdio_write(nxgep, ctrl_port,
2894 	    phy_dev, phy_reg, phy_data) != NXGE_OK)
2895 		goto fail;
2896 
2897 	phy_reg = NLP2020_I2C_SNOOP_STAT_REG;
2898 	(void) nxge_mdio_read(nxgep, ctrl_port, phy_dev, phy_reg, &stat);
2899 	while ((stat != 0x01) && (count-- > 0)) {
2900 		(void) nxge_mdio_read(nxgep, ctrl_port, phy_dev, phy_reg,
2901 		    &stat);
2902 	}
2903 	if (count) {
2904 		phy_reg = NLP2020_I2C_SNOOP_DATA_REG;
2905 		(void) nxge_mdio_read(nxgep, ctrl_port, phy_dev, phy_reg,
2906 		    &phy_data);
2907 		*data = (phy_data >> 8);
2908 		return (0);
2909 	}
2910 fail:
2911 	NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2912 	    "nxge_nlp2020_i2c_read: FAILED"));
2913 	return (1);
2914 
2915 }
2916 
2917 /* Initialize the Netlogic AEL2020 Transceiver */
2918 
2919 #define	NLP_INI_WAIT	1
2920 #define	NLP_INI_STOP	0
2921 
2922 static nxge_nlp_initseq_t nlp2020_revC_fiber_init[] = {
2923 	{0x1C003, 0x3101},
2924 	{0x1CC01, 0x488a},
2925 	{0x1CB1B, 0x0200},
2926 	{0x1CB1C, 0x00f0},
2927 	{0x1CC06, 0x00e0},
2928 	{NLP_INI_STOP, 0},
2929 };
2930 
2931 static nxge_nlp_initseq_t nlp2020_revC_copper_init[] = {
2932 
2933 	{0x1C003, 0x3101},
2934 	{0x1CD40, 0x0001},
2935 
2936 	{0x1CA12, 0x0100},
2937 	{0x1CA22, 0x0100},
2938 	{0x1CA42, 0x0100},
2939 	{0x1C20D, 0x0002},
2940 	{NLP_INI_WAIT, 100},
2941 
2942 	{0x1ff28, 0x4001},
2943 	{0x1ff2A, 0x004A},
2944 	{NLP_INI_WAIT, 500},
2945 
2946 	{0x1d000, 0x5200},
2947 	{NLP_INI_WAIT, 500},
2948 
2949 	{0x1d800, 0x4009},
2950 	{0x1d801, 0x2fff},
2951 	{0x1d802, 0x300f},
2952 	{0x1d803, 0x40aa},
2953 	{0x1d804, 0x401c},
2954 	{0x1d805, 0x401e},
2955 	{0x1d806, 0x20c5},
2956 	{0x1d807, 0x3c05},
2957 	{0x1d808, 0x6536},
2958 	{0x1d809, 0x2fe4},
2959 	{0x1d80a, 0x3dc4},
2960 	{0x1d80b, 0x6624},
2961 	{0x1d80c, 0x2ff4},
2962 	{0x1d80d, 0x3dc4},
2963 	{0x1d80e, 0x2035},
2964 	{0x1d80f, 0x30a5},
2965 	{0x1d810, 0x6524},
2966 	{0x1d811, 0x2ca2},
2967 	{0x1d812, 0x3012},
2968 	{0x1d813, 0x1002},
2969 	{0x1d814, 0x2882},
2970 	{0x1d815, 0x3022},
2971 	{0x1d816, 0x1002},
2972 	{0x1d817, 0x2972},
2973 	{0x1d818, 0x3022},
2974 	{0x1d819, 0x1002},
2975 	{0x1d81a, 0x2892},
2976 	{0x1d81b, 0x3012},
2977 	{0x1d81c, 0x1002},
2978 	{0x1d81d, 0x24e2},
2979 	{0x1d81e, 0x3022},
2980 	{0x1d81f, 0x1002},
2981 	{0x1d820, 0x27e2},
2982 	{0x1d821, 0x3012},
2983 	{0x1d822, 0x1002},
2984 	{0x1d823, 0x2422},
2985 	{0x1d824, 0x3022},
2986 	{0x1d825, 0x1002},
2987 	{0x1d826, 0x22cd},
2988 	{0x1d827, 0x301d},
2989 	{0x1d828, 0x2992},
2990 	{0x1d829, 0x3022},
2991 	{0x1d82a, 0x1002},
2992 	{0x1d82b, 0x5553},
2993 	{0x1d82c, 0x0307},
2994 	{0x1d82d, 0x2572},
2995 	{0x1d82e, 0x3022},
2996 	{0x1d82f, 0x1002},
2997 	{0x1d830, 0x21a2},
2998 	{0x1d831, 0x3012},
2999 	{0x1d832, 0x1002},
3000 	{0x1d833, 0x4016},
3001 	{0x1d834, 0x5e63},
3002 	{0x1d835, 0x0344},
3003 	{0x1d836, 0x21a2},
3004 	{0x1d837, 0x3012},
3005 	{0x1d838, 0x1002},
3006 	{0x1d839, 0x400e},
3007 	{0x1d83a, 0x2572},
3008 	{0x1d83b, 0x3022},
3009 	{0x1d83c, 0x1002},
3010 	{0x1d83d, 0x2b22},
3011 	{0x1d83e, 0x3012},
3012 	{0x1d83f, 0x1002},
3013 	{0x1d840, 0x28e2},
3014 	{0x1d841, 0x3022},
3015 	{0x1d842, 0x1002},
3016 	{0x1d843, 0x2782},
3017 	{0x1d844, 0x3022},
3018 	{0x1d845, 0x1002},
3019 	{0x1d846, 0x2fa4},
3020 	{0x1d847, 0x3dc4},
3021 	{0x1d848, 0x6624},
3022 	{0x1d849, 0x2e8b},
3023 	{0x1d84a, 0x303b},
3024 	{0x1d84b, 0x56b3},
3025 	{0x1d84c, 0x03c6},
3026 	{0x1d84d, 0x866b},
3027 	{0x1d84e, 0x400c},
3028 	{0x1d84f, 0x2782},
3029 	{0x1d850, 0x3012},
3030 	{0x1d851, 0x1002},
3031 	{0x1d852, 0x2c4b},
3032 	{0x1d853, 0x309b},
3033 	{0x1d854, 0x56b3},
3034 	{0x1d855, 0x03c3},
3035 	{0x1d856, 0x866b},
3036 	{0x1d857, 0x400c},
3037 	{0x1d858, 0x22a2},
3038 	{0x1d859, 0x3022},
3039 	{0x1d85a, 0x1002},
3040 	{0x1d85b, 0x28e2},
3041 	{0x1d85c, 0x3022},
3042 	{0x1d85d, 0x1002},
3043 	{0x1d85e, 0x2782},
3044 	{0x1d85f, 0x3022},
3045 	{0x1d860, 0x1002},
3046 	{0x1d861, 0x2fb4},
3047 	{0x1d862, 0x3dc4},
3048 	{0x1d863, 0x6624},
3049 	{0x1d864, 0x56b3},
3050 	{0x1d865, 0x03c3},
3051 	{0x1d866, 0x866b},
3052 	{0x1d867, 0x401c},
3053 	{0x1d868, 0x2c45},
3054 	{0x1d869, 0x3095},
3055 	{0x1d86a, 0x5b53},
3056 	{0x1d86b, 0x23d2},
3057 	{0x1d86c, 0x3012},
3058 	{0x1d86d, 0x13c2},
3059 	{0x1d86e, 0x5cc3},
3060 	{0x1d86f, 0x2782},
3061 	{0x1d870, 0x3012},
3062 	{0x1d871, 0x1312},
3063 	{0x1d872, 0x2b22},
3064 	{0x1d873, 0x3012},
3065 	{0x1d874, 0x1002},
3066 	{0x1d875, 0x28e2},
3067 	{0x1d876, 0x3022},
3068 	{0x1d877, 0x1002},
3069 	{0x1d878, 0x2672},
3070 	{0x1d879, 0x3022},
3071 	{0x1d87a, 0x1002},
3072 	{0x1d87b, 0x21a2},
3073 	{0x1d87c, 0x3012},
3074 	{0x1d87d, 0x1002},
3075 	{0x1d87e, 0x628f},
3076 	{0x1d87f, 0x2985},
3077 	{0x1d880, 0x33a5},
3078 	{0x1d881, 0x2782},
3079 	{0x1d882, 0x3022},
3080 	{0x1d883, 0x1002},
3081 	{0x1d884, 0x5653},
3082 	{0x1d885, 0x03d2},
3083 	{0x1d886, 0x401e},
3084 	{0x1d887, 0x6f72},
3085 	{0x1d888, 0x1002},
3086 	{0x1d889, 0x628f},
3087 	{0x1d88a, 0x2304},
3088 	{0x1d88b, 0x3c84},
3089 	{0x1d88c, 0x6436},
3090 	{0x1d88d, 0xdff4},
3091 	{0x1d88e, 0x6436},
3092 	{0x1d88f, 0x2ff5},
3093 	{0x1d890, 0x3005},
3094 	{0x1d891, 0x8656},
3095 	{0x1d892, 0xdfba},
3096 	{0x1d893, 0x56a3},
3097 	{0x1d894, 0xd05a},
3098 	{0x1d895, 0x29e2},
3099 	{0x1d896, 0x3012},
3100 	{0x1d897, 0x1392},
3101 	{0x1d898, 0xd05a},
3102 	{0x1d899, 0x56a3},
3103 	{0x1d89a, 0xdfba},
3104 	{0x1d89b, 0x0383},
3105 	{0x1d89c, 0x6f72},
3106 	{0x1d89d, 0x1002},
3107 	{0x1d89e, 0x2a64},
3108 	{0x1d89f, 0x3014},
3109 	{0x1d8a0, 0x2005},
3110 	{0x1d8a1, 0x3d75},
3111 	{0x1d8a2, 0xc451},
3112 	{0x1d8a3, 0x2a42},
3113 	{0x1d8a4, 0x3022},
3114 	{0x1d8a5, 0x1002},
3115 	{0x1d8a6, 0x178c},
3116 	{0x1d8a7, 0x1898},
3117 	{0x1d8a8, 0x19a4},
3118 	{0x1d8a9, 0x1ab0},
3119 	{0x1d8aa, 0x1bbc},
3120 	{0x1d8ab, 0x1cc8},
3121 	{0x1d8ac, 0x1dd3},
3122 	{0x1d8ad, 0x1ede},
3123 	{0x1d8ae, 0x1fe9},
3124 	{0x1d8af, 0x20f4},
3125 	{0x1d8b0, 0x21ff},
3126 	{0x1d8b1, 0x0000},
3127 	{0x1d8b2, 0x27e1},
3128 	{0x1d8b3, 0x3021},
3129 	{0x1d8b4, 0x1001},
3130 	{0x1d8b5, 0xc620},
3131 	{0x1d8b6, 0x0000},
3132 	{0x1d8b7, 0xc621},
3133 	{0x1d8b8, 0x0000},
3134 	{0x1d8b9, 0xc622},
3135 	{0x1d8ba, 0x00e2},
3136 	{0x1d8bb, 0xc623},
3137 	{0x1d8bc, 0x007f},
3138 	{0x1d8bd, 0xc624},
3139 	{0x1d8be, 0x00ce},
3140 	{0x1d8bf, 0xc625},
3141 	{0x1d8c0, 0x0000},
3142 	{0x1d8c1, 0xc627},
3143 	{0x1d8c2, 0x0000},
3144 	{0x1d8c3, 0xc628},
3145 	{0x1d8c4, 0x0000},
3146 	{0x1d8c5, 0xc90a},
3147 	{0x1d8c6, 0x3a7c},
3148 	{0x1d8c7, 0xc62c},
3149 	{0x1d8c8, 0x0000},
3150 	{0x1d8c9, 0x0000},
3151 	{0x1d8ca, 0x27e1},
3152 	{0x1d8cb, 0x3021},
3153 	{0x1d8cc, 0x1001},
3154 	{0x1d8cd, 0xc502},
3155 	{0x1d8ce, 0x53ac},
3156 	{0x1d8cf, 0xc503},
3157 	{0x1d8d0, 0x2cd3},
3158 	{0x1d8d1, 0xc600},
3159 	{0x1d8d2, 0x2a6e},
3160 	{0x1d8d3, 0xc601},
3161 	{0x1d8d4, 0x2a2c},
3162 	{0x1d8d5, 0xc605},
3163 	{0x1d8d6, 0x5557},
3164 	{0x1d8d7, 0xc60c},
3165 	{0x1d8d8, 0x5400},
3166 	{0x1d8d9, 0xc710},
3167 	{0x1d8da, 0x0700},
3168 	{0x1d8db, 0xc711},
3169 	{0x1d8dc, 0x0f06},
3170 	{0x1d8dd, 0xc718},
3171 	{0x1d8de, 0x0700},
3172 	{0x1d8df, 0xc719},
3173 	{0x1d8e0, 0x0f06},
3174 	{0x1d8e1, 0xc720},
3175 	{0x1d8e2, 0x4700},
3176 	{0x1d8e3, 0xc721},
3177 	{0x1d8e4, 0x0f06},
3178 	{0x1d8e5, 0xc728},
3179 	{0x1d8e6, 0x0700},
3180 	{0x1d8e7, 0xc729},
3181 	{0x1d8e8, 0x1207},
3182 	{0x1d8e9, 0xc801},
3183 	{0x1d8ea, 0x7f50},
3184 	{0x1d8eb, 0xc802},
3185 	{0x1d8ec, 0x7760},
3186 	{0x1d8ed, 0xc803},
3187 	{0x1d8ee, 0x7fce},
3188 	{0x1d8ef, 0xc804},
3189 	{0x1d8f0, 0x520e},
3190 	{0x1d8f1, 0xc805},
3191 	{0x1d8f2, 0x5c11},
3192 	{0x1d8f3, 0xc806},
3193 	{0x1d8f4, 0x3c51},
3194 	{0x1d8f5, 0xc807},
3195 	{0x1d8f6, 0x4061},
3196 	{0x1d8f7, 0xc808},
3197 	{0x1d8f8, 0x49c1},
3198 	{0x1d8f9, 0xc809},
3199 	{0x1d8fa, 0x3840},
3200 	{0x1d8fb, 0xc80a},
3201 	{0x1d8fc, 0x0000},
3202 	{0x1d8fd, 0xc821},
3203 	{0x1d8fe, 0x0002},
3204 	{0x1d8ff, 0xc822},
3205 	{0x1d900, 0x0046},
3206 	{0x1d901, 0xc844},
3207 	{0x1d902, 0x182f},
3208 	{0x1d903, 0xc849},
3209 	{0x1d904, 0x0400},
3210 	{0x1d905, 0xc84a},
3211 	{0x1d906, 0x0002},
3212 	{0x1d907, 0xc013},
3213 	{0x1d908, 0xf341},
3214 	{0x1d909, 0xc084},
3215 	{0x1d90a, 0x0030},
3216 	{0x1d90b, 0xc904},
3217 	{0x1d90c, 0x1401},
3218 	{0x1d90d, 0xcb0c},
3219 	{0x1d90e, 0x0004},
3220 	{0x1d90f, 0xcb0e},
3221 	{0x1d910, 0xa00a},
3222 	{0x1d911, 0xcb0f},
3223 	{0x1d912, 0xc0c0},
3224 	{0x1d913, 0xcb10},
3225 	{0x1d914, 0xc0c0},
3226 	{0x1d915, 0xcb11},
3227 	{0x1d916, 0x00a0},
3228 	{0x1d917, 0xcb12},
3229 	{0x1d918, 0x0007},
3230 	{0x1d919, 0xc241},
3231 	{0x1d91a, 0xa000},
3232 	{0x1d91b, 0xc243},
3233 	{0x1d91c, 0x7fe0},
3234 	{0x1d91d, 0xc604},
3235 	{0x1d91e, 0x000e},
3236 	{0x1d91f, 0xc609},
3237 	{0x1d920, 0x00f5},
3238 	{0x1d921, 0x0c61},
3239 	{0x1d922, 0x000e},
3240 	{0x1d923, 0xc660},
3241 	{0x1d924, 0x9600},
3242 	{0x1d925, 0xc687},
3243 	{0x1d926, 0x0004},
3244 	{0x1d927, 0xc60a},
3245 	{0x1d928, 0x04f5},
3246 	{0x1d929, 0x0000},
3247 	{0x1d92a, 0x27e1},
3248 	{0x1d92b, 0x3021},
3249 	{0x1d92c, 0x1001},
3250 	{0x1d92d, 0xc620},
3251 	{0x1d92e, 0x14e5},
3252 	{0x1d92f, 0xc621},
3253 	{0x1d930, 0xc53d},
3254 	{0x1d931, 0xc622},
3255 	{0x1d932, 0x3cbe},
3256 	{0x1d933, 0xc623},
3257 	{0x1d934, 0x4452},
3258 	{0x1d935, 0xc624},
3259 	{0x1d936, 0xc5c5},
3260 	{0x1d937, 0xc625},
3261 	{0x1d938, 0xe01e},
3262 	{0x1d939, 0xc627},
3263 	{0x1d93a, 0x0000},
3264 	{0x1d93b, 0xc628},
3265 	{0x1d93c, 0x0000},
3266 	{0x1d93d, 0xc62c},
3267 	{0x1d93e, 0x0000},
3268 	{0x1d93f, 0xc90a},
3269 	{0x1d940, 0x3a7c},
3270 	{0x1d941, 0x0000},
3271 	{0x1d942, 0x2b84},
3272 	{0x1d943, 0x3c74},
3273 	{0x1d944, 0x6435},
3274 	{0x1d945, 0xdff4},
3275 	{0x1d946, 0x6435},
3276 	{0x1d947, 0x2806},
3277 	{0x1d948, 0x3006},
3278 	{0x1d949, 0x8565},
3279 	{0x1d94a, 0x2b24},
3280 	{0x1d94b, 0x3c24},
3281 	{0x1d94c, 0x6436},
3282 	{0x1d94d, 0x1002},
3283 	{0x1d94e, 0x2b24},
3284 	{0x1d94f, 0x3c24},
3285 	{0x1d950, 0x6436},
3286 	{0x1d951, 0x4045},
3287 	{0x1d952, 0x8656},
3288 	{0x1d953, 0x5663},
3289 	{0x1d954, 0x0302},
3290 	{0x1d955, 0x401e},
3291 	{0x1d956, 0x1002},
3292 	{0x1d957, 0x2017},
3293 	{0x1d958, 0x3b17},
3294 	{0x1d959, 0x2084},
3295 	{0x1d95a, 0x3c14},
3296 	{0x1d95b, 0x6724},
3297 	{0x1d95c, 0x2807},
3298 	{0x1d95d, 0x31a7},
3299 	{0x1d95e, 0x20c4},
3300 	{0x1d95f, 0x3c24},
3301 	{0x1d960, 0x6724},
3302 	{0x1d961, 0x2ff7},
3303 	{0x1d962, 0x30f7},
3304 	{0x1d963, 0x20c4},
3305 	{0x1d964, 0x3c04},
3306 	{0x1d965, 0x6724},
3307 	{0x1d966, 0x1002},
3308 	{0x1d967, 0x2807},
3309 	{0x1d968, 0x3187},
3310 	{0x1d969, 0x20c4},
3311 	{0x1d96a, 0x3c24},
3312 	{0x1d96b, 0x6724},
3313 	{0x1d96c, 0x2fe4},
3314 	{0x1d96d, 0x3dc4},
3315 	{0x1d96e, 0x6437},
3316 	{0x1d96f, 0x20c4},
3317 	{0x1d970, 0x3c04},
3318 	{0x1d971, 0x6724},
3319 	{0x1d972, 0x2017},
3320 	{0x1d973, 0x3d17},
3321 	{0x1d974, 0x2084},
3322 	{0x1d975, 0x3c14},
3323 	{0x1d976, 0x6724},
3324 	{0x1d977, 0x1002},
3325 	{0x1d978, 0x24f4},
3326 	{0x1d979, 0x3c64},
3327 	{0x1d97a, 0x6436},
3328 	{0x1d97b, 0xdff4},
3329 	{0x1d97c, 0x6436},
3330 	{0x1d97d, 0x1002},
3331 	{0x1d97e, 0x2006},
3332 	{0x1d97f, 0x3d76},
3333 	{0x1d980, 0xc161},
3334 	{0x1d981, 0x6134},
3335 	{0x1d982, 0x6135},
3336 	{0x1d983, 0x5443},
3337 	{0x1d984, 0x0303},
3338 	{0x1d985, 0x6524},
3339 	{0x1d986, 0x00fb},
3340 	{0x1d987, 0x1002},
3341 	{0x1d988, 0x20d4},
3342 	{0x1d989, 0x3c24},
3343 	{0x1d98a, 0x2025},
3344 	{0x1d98b, 0x3005},
3345 	{0x1d98c, 0x6524},
3346 	{0x1d98d, 0x1002},
3347 	{0x1d98e, 0xd019},
3348 	{0x1d98f, 0x2104},
3349 	{0x1d990, 0x3c24},
3350 	{0x1d991, 0x2105},
3351 	{0x1d992, 0x3805},
3352 	{0x1d993, 0x6524},
3353 	{0x1d994, 0xdff4},
3354 	{0x1d995, 0x4005},
3355 	{0x1d996, 0x6524},
3356 	{0x1d997, 0x2e8d},
3357 	{0x1d998, 0x303d},
3358 	{0x1d999, 0x2408},
3359 	{0x1d99a, 0x35d8},
3360 	{0x1d99b, 0x5dd3},
3361 	{0x1d99c, 0x0307},
3362 	{0x1d99d, 0x8887},
3363 	{0x1d99e, 0x63a7},
3364 	{0x1d99f, 0x8887},
3365 	{0x1d9a0, 0x63a7},
3366 	{0x1d9a1, 0xdffd},
3367 	{0x1d9a2, 0x00f9},
3368 	{0x1d9a3, 0x1002},
3369 	{0x1d9a4, 0x866a},
3370 	{0x1d9a5, 0x6138},
3371 	{0x1d9a6, 0x5883},
3372 	{0x1d9a7, 0x2b42},
3373 	{0x1d9a8, 0x3022},
3374 	{0x1d9a9, 0x1302},
3375 	{0x1d9aa, 0x2ff7},
3376 	{0x1d9ab, 0x3007},
3377 	{0x1d9ac, 0x8785},
3378 	{0x1d9ad, 0xb887},
3379 	{0x1d9ae, 0x8786},
3380 	{0x1d9af, 0xb8c6},
3381 	{0x1d9b0, 0x5a53},
3382 	{0x1d9b1, 0x2a52},
3383 	{0x1d9b2, 0x3022},
3384 	{0x1d9b3, 0x13c2},
3385 	{0x1d9b4, 0x2474},
3386 	{0x1d9b5, 0x3c84},
3387 	{0x1d9b6, 0x64d7},
3388 	{0x1d9b7, 0x64d7},
3389 	{0x1d9b8, 0x2ff5},
3390 	{0x1d9b9, 0x3c05},
3391 	{0x1d9ba, 0x8757},
3392 	{0x1d9bb, 0xb886},
3393 	{0x1d9bc, 0x9767},
3394 	{0x1d9bd, 0x67c4},
3395 	{0x1d9be, 0x6f72},
3396 	{0x1d9bf, 0x1002},
3397 	{0x1d9c0, 0x0000},
3398 	{0x1d080, 0x0100},
3399 	{0x1d092, 0x0000},
3400 	{NLP_INI_STOP, 0},
3401 };
3402 
3403 static nxge_status_t
nxge_nlp2020_xcvr_init(p_nxge_t nxgep)3404 nxge_nlp2020_xcvr_init(p_nxge_t nxgep)
3405 {
3406 	uint8_t