144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 22a3c5bd6dSspeer * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 2344961713Sgirish * Use is subject to license terms. 2444961713Sgirish */ 2544961713Sgirish 2644961713Sgirish #pragma ident "%Z%%M% %I% %E% SMI" 2744961713Sgirish 2844961713Sgirish #include <nxge_impl.h> 2944961713Sgirish #include <nxge_ipp.h> 3044961713Sgirish 3114ea4bb7Ssd #define NXGE_IPP_FIFO_SYNC_TRY_COUNT 100 3214ea4bb7Ssd 33a3c5bd6dSspeer /* ARGSUSED */ 3444961713Sgirish nxge_status_t 3544961713Sgirish nxge_ipp_init(p_nxge_t nxgep) 3644961713Sgirish { 37a3c5bd6dSspeer uint8_t portn; 38a3c5bd6dSspeer uint32_t config; 39a3c5bd6dSspeer npi_handle_t handle; 40a3c5bd6dSspeer uint32_t pkt_size; 41a3c5bd6dSspeer ipp_status_t istatus; 42a3c5bd6dSspeer npi_status_t rs = NPI_SUCCESS; 43a3c5bd6dSspeer uint64_t val; 44a3c5bd6dSspeer uint32_t d0, d1, d2, d3, d4; 45a3c5bd6dSspeer int i; 46a3c5bd6dSspeer uint32_t dfifo_entries; 4744961713Sgirish 4844961713Sgirish handle = nxgep->npi_handle; 4944961713Sgirish portn = NXGE_GET_PORT_NUM(nxgep->function_num); 5044961713Sgirish 5144961713Sgirish NXGE_DEBUG_MSG((nxgep, IPP_CTL, "==> nxge_ipp_init: port%d", portn)); 5244961713Sgirish 5344961713Sgirish /* Initialize ECC and parity in SRAM of DFIFO and PFIFO */ 54*59ac0c16Sdavemq if (nxgep->niu_type == N2_NIU) { 55*59ac0c16Sdavemq dfifo_entries = IPP_NIU_DFIFO_ENTRIES; 56*59ac0c16Sdavemq } else if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep->niu_type)) { 5744961713Sgirish if (portn < 2) 5844961713Sgirish dfifo_entries = IPP_P0_P1_DFIFO_ENTRIES; 5944961713Sgirish else 6044961713Sgirish dfifo_entries = IPP_P2_P3_DFIFO_ENTRIES; 61*59ac0c16Sdavemq } else { 6244961713Sgirish goto fail; 63*59ac0c16Sdavemq } 6444961713Sgirish 6544961713Sgirish for (i = 0; i < dfifo_entries; i++) { 66a3c5bd6dSspeer if ((rs = npi_ipp_write_dfifo(handle, 67a3c5bd6dSspeer portn, i, 0, 0, 0, 0, 0)) != NPI_SUCCESS) 6844961713Sgirish goto fail; 69a3c5bd6dSspeer if ((rs = npi_ipp_read_dfifo(handle, portn, 70a3c5bd6dSspeer i, &d0, &d1, &d2, &d3, &d4)) != NPI_SUCCESS) 7144961713Sgirish goto fail; 7244961713Sgirish } 7344961713Sgirish 7444961713Sgirish /* Clear PFIFO DFIFO status bits */ 7544961713Sgirish if ((rs = npi_ipp_get_status(handle, portn, &istatus)) != NPI_SUCCESS) 7644961713Sgirish goto fail; 7744961713Sgirish if ((rs = npi_ipp_get_status(handle, portn, &istatus)) != NPI_SUCCESS) 7844961713Sgirish goto fail; 7944961713Sgirish 8044961713Sgirish /* 8144961713Sgirish * Soft reset to make sure we bring the FIFO pointers back to the 8244961713Sgirish * original initial position. 8344961713Sgirish */ 8444961713Sgirish if ((rs = npi_ipp_reset(handle, portn)) != NPI_SUCCESS) 8544961713Sgirish goto fail; 8644961713Sgirish 8744961713Sgirish /* Clean up ECC counter */ 8844961713Sgirish IPP_REG_RD(nxgep->npi_handle, portn, IPP_ECC_ERR_COUNTER_REG, &val); 8944961713Sgirish IPP_REG_RD(nxgep->npi_handle, portn, IPP_TCP_CKSUM_ERR_CNT_REG, &val); 9044961713Sgirish IPP_REG_RD(nxgep->npi_handle, portn, IPP_DISCARD_PKT_CNT_REG, &val); 9144961713Sgirish 9244961713Sgirish if ((rs = npi_ipp_get_status(handle, portn, &istatus)) != NPI_SUCCESS) 9344961713Sgirish goto fail; 9444961713Sgirish 9544961713Sgirish /* Configure IPP port */ 9644961713Sgirish if ((rs = npi_ipp_iconfig(handle, INIT, portn, ICFG_IPP_ALL)) 97a3c5bd6dSspeer != NPI_SUCCESS) 9844961713Sgirish goto fail; 9944961713Sgirish nxgep->ipp.iconfig = ICFG_IPP_ALL; 10044961713Sgirish 10144961713Sgirish config = CFG_IPP | CFG_IPP_DFIFO_ECC_CORRECT | CFG_IPP_DROP_BAD_CRC | 102a3c5bd6dSspeer CFG_IPP_TCP_UDP_CKSUM; 10344961713Sgirish if ((rs = npi_ipp_config(handle, INIT, portn, config)) != NPI_SUCCESS) 10444961713Sgirish goto fail; 10544961713Sgirish nxgep->ipp.config = config; 10644961713Sgirish 10744961713Sgirish /* Set max packet size */ 10844961713Sgirish pkt_size = IPP_MAX_PKT_SIZE; 109a3c5bd6dSspeer if ((rs = npi_ipp_set_max_pktsize(handle, portn, 110a3c5bd6dSspeer IPP_MAX_PKT_SIZE)) != NPI_SUCCESS) 11144961713Sgirish goto fail; 11244961713Sgirish nxgep->ipp.max_pkt_size = pkt_size; 11344961713Sgirish 11444961713Sgirish NXGE_DEBUG_MSG((nxgep, IPP_CTL, "<== nxge_ipp_init: port%d", portn)); 11544961713Sgirish 11644961713Sgirish return (NXGE_OK); 11744961713Sgirish fail: 11844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 11944961713Sgirish "nxge_ipp_init: Fail to initialize IPP Port #%d\n", 12044961713Sgirish portn)); 12144961713Sgirish return (NXGE_ERROR | rs); 12244961713Sgirish } 12344961713Sgirish 124a3c5bd6dSspeer /* ARGSUSED */ 12544961713Sgirish nxge_status_t 12644961713Sgirish nxge_ipp_disable(p_nxge_t nxgep) 12744961713Sgirish { 128a3c5bd6dSspeer uint8_t portn; 129a3c5bd6dSspeer uint32_t config; 130a3c5bd6dSspeer npi_handle_t handle; 131a3c5bd6dSspeer npi_status_t rs = NPI_SUCCESS; 13214ea4bb7Ssd uint16_t wr_ptr, rd_ptr; 13314ea4bb7Ssd uint32_t try_count; 13444961713Sgirish 13544961713Sgirish handle = nxgep->npi_handle; 13644961713Sgirish portn = NXGE_GET_PORT_NUM(nxgep->function_num); 13744961713Sgirish 13844961713Sgirish NXGE_DEBUG_MSG((nxgep, IPP_CTL, "==> nxge_ipp_disable: port%d", portn)); 13914ea4bb7Ssd (void) nxge_rx_mac_disable(nxgep); 14014ea4bb7Ssd 14114ea4bb7Ssd /* 142a3c5bd6dSspeer * Wait until ip read and write fifo pointers are equal 14314ea4bb7Ssd */ 14414ea4bb7Ssd (void) npi_ipp_get_dfifo_rd_ptr(handle, portn, &rd_ptr); 14514ea4bb7Ssd (void) npi_ipp_get_dfifo_wr_ptr(handle, portn, &wr_ptr); 14614ea4bb7Ssd try_count = NXGE_IPP_FIFO_SYNC_TRY_COUNT; 14714ea4bb7Ssd 14814ea4bb7Ssd while ((try_count > 0) && (rd_ptr != wr_ptr)) { 14914ea4bb7Ssd (void) npi_ipp_get_dfifo_rd_ptr(handle, portn, &rd_ptr); 15014ea4bb7Ssd (void) npi_ipp_get_dfifo_wr_ptr(handle, portn, &wr_ptr); 15114ea4bb7Ssd try_count--; 15214ea4bb7Ssd } 15314ea4bb7Ssd 15414ea4bb7Ssd if (try_count == 0) { 15514ea4bb7Ssd if ((rd_ptr != 0) && (wr_ptr != 1)) { 15614ea4bb7Ssd NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 157a3c5bd6dSspeer " nxge_ipp_disable: port%d failed" 158a3c5bd6dSspeer " rd_fifo != wr_fifo", portn)); 15914ea4bb7Ssd goto fail; 16014ea4bb7Ssd } 16114ea4bb7Ssd } 16244961713Sgirish /* disable the IPP */ 16344961713Sgirish config = nxgep->ipp.config; 164a3c5bd6dSspeer if ((rs = npi_ipp_config(handle, DISABLE, 165a3c5bd6dSspeer portn, config)) != NPI_SUCCESS) 16644961713Sgirish goto fail; 16744961713Sgirish 16844961713Sgirish /* IPP soft reset */ 169a3c5bd6dSspeer if ((rs = npi_ipp_reset(handle, portn)) != NPI_SUCCESS) 17044961713Sgirish goto fail; 17144961713Sgirish 17244961713Sgirish NXGE_DEBUG_MSG((nxgep, IPP_CTL, "<== nxge_ipp_disable: port%d", portn)); 17344961713Sgirish return (NXGE_OK); 17444961713Sgirish fail: 17544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 176a3c5bd6dSspeer "nxge_ipp_disable: Fail to disable IPP Port #%d\n", portn)); 17744961713Sgirish return (NXGE_ERROR | rs); 17844961713Sgirish } 17944961713Sgirish 180a3c5bd6dSspeer /* ARGSUSED */ 18144961713Sgirish nxge_status_t 18244961713Sgirish nxge_ipp_reset(p_nxge_t nxgep) 18344961713Sgirish { 184a3c5bd6dSspeer uint8_t portn; 185a3c5bd6dSspeer uint32_t config; 186a3c5bd6dSspeer npi_handle_t handle; 187a3c5bd6dSspeer npi_status_t rs = NPI_SUCCESS; 18844961713Sgirish uint16_t wr_ptr, rd_ptr; 18944961713Sgirish uint32_t try_count; 190a3c5bd6dSspeer 19144961713Sgirish handle = nxgep->npi_handle; 19244961713Sgirish portn = NXGE_GET_PORT_NUM(nxgep->function_num); 19344961713Sgirish 19444961713Sgirish NXGE_DEBUG_MSG((nxgep, IPP_CTL, "==> nxge_ipp_reset: port%d", portn)); 19544961713Sgirish 19644961713Sgirish /* disable the IPP */ 19744961713Sgirish config = nxgep->ipp.config; 198a3c5bd6dSspeer if ((rs = npi_ipp_config(handle, DISABLE, 199a3c5bd6dSspeer portn, config)) != NPI_SUCCESS) 20044961713Sgirish goto fail; 20144961713Sgirish 20244961713Sgirish /* 203a3c5bd6dSspeer * Wait until ip read and write fifo pointers are equal 20444961713Sgirish */ 20544961713Sgirish (void) npi_ipp_get_dfifo_rd_ptr(handle, portn, &rd_ptr); 20644961713Sgirish (void) npi_ipp_get_dfifo_wr_ptr(handle, portn, &wr_ptr); 20714ea4bb7Ssd try_count = NXGE_IPP_FIFO_SYNC_TRY_COUNT; 20844961713Sgirish 20944961713Sgirish while ((try_count > 0) && (rd_ptr != wr_ptr)) { 21044961713Sgirish (void) npi_ipp_get_dfifo_rd_ptr(handle, portn, &rd_ptr); 21144961713Sgirish (void) npi_ipp_get_dfifo_wr_ptr(handle, portn, &wr_ptr); 21244961713Sgirish try_count--; 21344961713Sgirish } 21444961713Sgirish 21544961713Sgirish if (try_count == 0) { 21614ea4bb7Ssd if ((rd_ptr != 0) && (wr_ptr != 1)) { 21714ea4bb7Ssd NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 218a3c5bd6dSspeer " nxge_ipp_disable: port%d failed" 219a3c5bd6dSspeer " rd_fifo != wr_fifo", portn)); 22014ea4bb7Ssd goto fail; 22114ea4bb7Ssd } 22244961713Sgirish } 22344961713Sgirish 22444961713Sgirish /* IPP soft reset */ 22544961713Sgirish if ((rs = npi_ipp_reset(handle, portn)) != NPI_SUCCESS) { 22644961713Sgirish goto fail; 22744961713Sgirish } 22844961713Sgirish 22944961713Sgirish /* to reset control FIFO */ 230a3c5bd6dSspeer if ((rs = npi_zcp_rest_cfifo_port(handle, portn)) != NPI_SUCCESS) 23144961713Sgirish goto fail; 23244961713Sgirish 23344961713Sgirish /* 234a3c5bd6dSspeer * Making sure that error source is cleared if this is an injected 235a3c5bd6dSspeer * error. 23644961713Sgirish */ 23744961713Sgirish IPP_REG_WR(handle, portn, IPP_ECC_CTRL_REG, 0); 23844961713Sgirish 23944961713Sgirish NXGE_DEBUG_MSG((nxgep, IPP_CTL, "<== nxge_ipp_reset: port%d", portn)); 24044961713Sgirish return (NXGE_OK); 24144961713Sgirish fail: 24244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 24344961713Sgirish "nxge_ipp_init: Fail to Reset IPP Port #%d\n", 24444961713Sgirish portn)); 24544961713Sgirish return (NXGE_ERROR | rs); 24644961713Sgirish } 24744961713Sgirish 248a3c5bd6dSspeer /* ARGSUSED */ 24944961713Sgirish nxge_status_t 25044961713Sgirish nxge_ipp_enable(p_nxge_t nxgep) 25144961713Sgirish { 252a3c5bd6dSspeer uint8_t portn; 253a3c5bd6dSspeer uint32_t config; 254a3c5bd6dSspeer npi_handle_t handle; 255a3c5bd6dSspeer uint32_t pkt_size; 256a3c5bd6dSspeer npi_status_t rs = NPI_SUCCESS; 25744961713Sgirish 25844961713Sgirish handle = nxgep->npi_handle; 25944961713Sgirish portn = NXGE_GET_PORT_NUM(nxgep->function_num); 26044961713Sgirish 26144961713Sgirish NXGE_DEBUG_MSG((nxgep, IPP_CTL, "==> nxge_ipp_enable: port%d", portn)); 26244961713Sgirish 26344961713Sgirish config = CFG_IPP | CFG_IPP_DFIFO_ECC_CORRECT | CFG_IPP_DROP_BAD_CRC | 264a3c5bd6dSspeer CFG_IPP_TCP_UDP_CKSUM; 26544961713Sgirish if ((rs = npi_ipp_config(handle, INIT, portn, config)) != NPI_SUCCESS) 26644961713Sgirish goto fail; 26744961713Sgirish nxgep->ipp.config = config; 26844961713Sgirish 26944961713Sgirish /* Set max packet size */ 27044961713Sgirish pkt_size = IPP_MAX_PKT_SIZE; 271a3c5bd6dSspeer if ((rs = npi_ipp_set_max_pktsize(handle, portn, 272a3c5bd6dSspeer IPP_MAX_PKT_SIZE)) != NPI_SUCCESS) 27344961713Sgirish goto fail; 27444961713Sgirish nxgep->ipp.max_pkt_size = pkt_size; 27544961713Sgirish 27644961713Sgirish NXGE_DEBUG_MSG((nxgep, IPP_CTL, "<== nxge_ipp_enable: port%d", portn)); 27744961713Sgirish return (NXGE_OK); 27844961713Sgirish fail: 27944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 280a3c5bd6dSspeer "nxge_ipp_init: Fail to Enable IPP Port #%d\n", portn)); 28144961713Sgirish return (NXGE_ERROR | rs); 28244961713Sgirish } 28344961713Sgirish 284a3c5bd6dSspeer /* ARGSUSED */ 28544961713Sgirish nxge_status_t 28644961713Sgirish nxge_ipp_handle_sys_errors(p_nxge_t nxgep) 28744961713Sgirish { 288a3c5bd6dSspeer npi_handle_t handle; 289a3c5bd6dSspeer npi_status_t rs = NPI_SUCCESS; 290a3c5bd6dSspeer p_nxge_ipp_stats_t statsp; 291a3c5bd6dSspeer ipp_status_t istatus; 292a3c5bd6dSspeer uint8_t portn; 293a3c5bd6dSspeer p_ipp_errlog_t errlogp; 294a3c5bd6dSspeer boolean_t rxport_fatal = B_FALSE; 295a3c5bd6dSspeer nxge_status_t status = NXGE_OK; 29644961713Sgirish 29744961713Sgirish handle = nxgep->npi_handle; 29844961713Sgirish statsp = (p_nxge_ipp_stats_t)&nxgep->statsp->ipp_stats; 29944961713Sgirish portn = nxgep->mac.portnum; 30044961713Sgirish 30144961713Sgirish errlogp = (p_ipp_errlog_t)&statsp->errlog; 30244961713Sgirish 30344961713Sgirish if ((rs = npi_ipp_get_status(handle, portn, &istatus)) != NPI_SUCCESS) 30444961713Sgirish return (NXGE_ERROR | rs); 30544961713Sgirish 306a3c5bd6dSspeer if (istatus.value == 0) { 30744961713Sgirish /* 30844961713Sgirish * The error is not initiated from this port, so just exit. 30944961713Sgirish */ 31044961713Sgirish return (NXGE_OK); 311a3c5bd6dSspeer } 31244961713Sgirish 31344961713Sgirish if (istatus.bits.w0.dfifo_missed_sop) { 31444961713Sgirish statsp->sop_miss++; 31544961713Sgirish if ((rs = npi_ipp_get_dfifo_eopm_rdptr(handle, portn, 31644961713Sgirish &errlogp->dfifo_rd_ptr)) != NPI_SUCCESS) 31744961713Sgirish return (NXGE_ERROR | rs); 31844961713Sgirish if ((rs = npi_ipp_get_state_mach(handle, portn, 319a3c5bd6dSspeer &errlogp->state_mach)) != NPI_SUCCESS) 32044961713Sgirish return (NXGE_ERROR | rs); 32144961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 322a3c5bd6dSspeer NXGE_FM_EREPORT_IPP_SOP_MISS); 32344961713Sgirish if (statsp->sop_miss < IPP_MAX_ERR_SHOW) 32444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 32544961713Sgirish "nxge_ipp_err_evnts: fatal error: sop_miss\n")); 32644961713Sgirish rxport_fatal = B_TRUE; 32744961713Sgirish } 32844961713Sgirish if (istatus.bits.w0.dfifo_missed_eop) { 32944961713Sgirish statsp->eop_miss++; 33044961713Sgirish if ((rs = npi_ipp_get_dfifo_eopm_rdptr(handle, portn, 331a3c5bd6dSspeer &errlogp->dfifo_rd_ptr)) != NPI_SUCCESS) 33244961713Sgirish return (NXGE_ERROR | rs); 33344961713Sgirish if ((rs = npi_ipp_get_state_mach(handle, portn, 334a3c5bd6dSspeer &errlogp->state_mach)) != NPI_SUCCESS) 33544961713Sgirish return (NXGE_ERROR | rs); 33644961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 337a3c5bd6dSspeer NXGE_FM_EREPORT_IPP_EOP_MISS); 33844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 339a3c5bd6dSspeer "nxge_ipp_err_evnts: fatal error: eop_miss\n")); 34044961713Sgirish rxport_fatal = B_TRUE; 34144961713Sgirish } 34244961713Sgirish if (istatus.bits.w0.dfifo_uncorr_ecc_err) { 34314ea4bb7Ssd boolean_t ue_ecc_valid; 34414ea4bb7Ssd 345a3c5bd6dSspeer if ((status = nxge_ipp_eccue_valid_check(nxgep, 346a3c5bd6dSspeer &ue_ecc_valid)) != NXGE_OK) 34714ea4bb7Ssd return (status); 34814ea4bb7Ssd 34914ea4bb7Ssd if (ue_ecc_valid) { 35014ea4bb7Ssd statsp->dfifo_ue++; 35114ea4bb7Ssd if ((rs = npi_ipp_get_ecc_syndrome(handle, portn, 35244961713Sgirish &errlogp->ecc_syndrome)) != NPI_SUCCESS) 35314ea4bb7Ssd return (NXGE_ERROR | rs); 35414ea4bb7Ssd NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 355a3c5bd6dSspeer NXGE_FM_EREPORT_IPP_DFIFO_UE); 35614ea4bb7Ssd NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 35744961713Sgirish "nxge_ipp_err_evnts: fatal error: dfifo_ue\n")); 35814ea4bb7Ssd rxport_fatal = B_TRUE; 35914ea4bb7Ssd } 36044961713Sgirish } 36144961713Sgirish if (istatus.bits.w0.pre_fifo_perr) { 36244961713Sgirish statsp->pfifo_perr++; 36344961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 364a3c5bd6dSspeer NXGE_FM_EREPORT_IPP_PFIFO_PERR); 36544961713Sgirish if (statsp->pfifo_perr < IPP_MAX_ERR_SHOW) 36644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 367a3c5bd6dSspeer "nxge_ipp_err_evnts: " 368a3c5bd6dSspeer "fatal error: pre_pifo_perr\n")); 36944961713Sgirish rxport_fatal = B_TRUE; 37044961713Sgirish } 37144961713Sgirish if (istatus.bits.w0.pre_fifo_overrun) { 37244961713Sgirish statsp->pfifo_over++; 37344961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 374a3c5bd6dSspeer NXGE_FM_EREPORT_IPP_PFIFO_OVER); 37544961713Sgirish if (statsp->pfifo_over < IPP_MAX_ERR_SHOW) 37644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 377a3c5bd6dSspeer "nxge_ipp_err_evnts: " 378a3c5bd6dSspeer "fatal error: pfifo_over\n")); 37944961713Sgirish rxport_fatal = B_TRUE; 38044961713Sgirish } 38144961713Sgirish if (istatus.bits.w0.pre_fifo_underrun) { 38244961713Sgirish statsp->pfifo_und++; 38344961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 384a3c5bd6dSspeer NXGE_FM_EREPORT_IPP_PFIFO_UND); 38544961713Sgirish if (statsp->pfifo_und < IPP_MAX_ERR_SHOW) 38644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 387a3c5bd6dSspeer "nxge_ipp_err_evnts: " 388a3c5bd6dSspeer "fatal error: pfifo_und\n")); 38944961713Sgirish rxport_fatal = B_TRUE; 39044961713Sgirish } 39144961713Sgirish if (istatus.bits.w0.bad_cksum_cnt_ovfl) { 39244961713Sgirish statsp->bad_cs_cnt += IPP_BAD_CS_CNT_MASK; 39344961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 394a3c5bd6dSspeer NXGE_FM_EREPORT_IPP_BAD_CS_MX); 395a3c5bd6dSspeer if (statsp->bad_cs_cnt < (IPP_MAX_ERR_SHOW * 396a3c5bd6dSspeer IPP_BAD_CS_CNT_MASK)) 39744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 39844961713Sgirish "nxge_ipp_err_evnts: bad_cs_max\n")); 39944961713Sgirish } 40044961713Sgirish if (istatus.bits.w0.pkt_discard_cnt_ovfl) { 40144961713Sgirish statsp->pkt_dis_cnt += IPP_PKT_DIS_CNT_MASK; 40244961713Sgirish NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 403a3c5bd6dSspeer NXGE_FM_EREPORT_IPP_PKT_DIS_MX); 404a3c5bd6dSspeer if (statsp->pkt_dis_cnt < (IPP_MAX_ERR_SHOW * 405a3c5bd6dSspeer IPP_PKT_DIS_CNT_MASK)) 40644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 40744961713Sgirish "nxge_ipp_err_evnts: pkt_dis_max\n")); 40844961713Sgirish } 40944961713Sgirish 41044961713Sgirish /* 411a3c5bd6dSspeer * Making sure that error source is cleared if this is an injected 412a3c5bd6dSspeer * error. 41344961713Sgirish */ 41444961713Sgirish IPP_REG_WR(handle, portn, IPP_ECC_CTRL_REG, 0); 41544961713Sgirish 41644961713Sgirish if (rxport_fatal) { 41744961713Sgirish NXGE_DEBUG_MSG((nxgep, IPP_CTL, 418a3c5bd6dSspeer " nxge_ipp_handle_sys_errors:" 419a3c5bd6dSspeer " fatal Error on Port #%d\n", portn)); 42044961713Sgirish status = nxge_ipp_fatal_err_recover(nxgep); 42144961713Sgirish if (status == NXGE_OK) { 42244961713Sgirish FM_SERVICE_RESTORED(nxgep); 42344961713Sgirish } 42444961713Sgirish } 42544961713Sgirish return (status); 42644961713Sgirish } 42744961713Sgirish 428a3c5bd6dSspeer /* ARGSUSED */ 42944961713Sgirish void 43044961713Sgirish nxge_ipp_inject_err(p_nxge_t nxgep, uint32_t err_id) 43144961713Sgirish { 432a3c5bd6dSspeer ipp_status_t ipps; 433a3c5bd6dSspeer ipp_ecc_ctrl_t ecc_ctrl; 434a3c5bd6dSspeer uint8_t portn = nxgep->mac.portnum; 43544961713Sgirish 43644961713Sgirish switch (err_id) { 43744961713Sgirish case NXGE_FM_EREPORT_IPP_DFIFO_UE: 43844961713Sgirish ecc_ctrl.value = 0; 43944961713Sgirish ecc_ctrl.bits.w0.cor_dbl = 1; 44044961713Sgirish ecc_ctrl.bits.w0.cor_1 = 1; 44144961713Sgirish ecc_ctrl.bits.w0.cor_lst = 1; 44244961713Sgirish cmn_err(CE_NOTE, "!Write 0x%llx to IPP_ECC_CTRL_REG\n", 443a3c5bd6dSspeer (unsigned long long) ecc_ctrl.value); 44444961713Sgirish IPP_REG_WR(nxgep->npi_handle, portn, IPP_ECC_CTRL_REG, 445a3c5bd6dSspeer ecc_ctrl.value); 44644961713Sgirish break; 447a3c5bd6dSspeer 44844961713Sgirish case NXGE_FM_EREPORT_IPP_DFIFO_CE: 44944961713Sgirish ecc_ctrl.value = 0; 45044961713Sgirish ecc_ctrl.bits.w0.cor_sng = 1; 45144961713Sgirish ecc_ctrl.bits.w0.cor_1 = 1; 45244961713Sgirish ecc_ctrl.bits.w0.cor_snd = 1; 45344961713Sgirish cmn_err(CE_NOTE, "!Write 0x%llx to IPP_ECC_CTRL_REG\n", 454a3c5bd6dSspeer (unsigned long long) ecc_ctrl.value); 45544961713Sgirish IPP_REG_WR(nxgep->npi_handle, portn, IPP_ECC_CTRL_REG, 456a3c5bd6dSspeer ecc_ctrl.value); 45744961713Sgirish break; 458a3c5bd6dSspeer 45944961713Sgirish case NXGE_FM_EREPORT_IPP_EOP_MISS: 46044961713Sgirish case NXGE_FM_EREPORT_IPP_SOP_MISS: 46144961713Sgirish case NXGE_FM_EREPORT_IPP_PFIFO_PERR: 46244961713Sgirish case NXGE_FM_EREPORT_IPP_ECC_ERR_MAX: 46344961713Sgirish case NXGE_FM_EREPORT_IPP_PFIFO_OVER: 46444961713Sgirish case NXGE_FM_EREPORT_IPP_PFIFO_UND: 46544961713Sgirish case NXGE_FM_EREPORT_IPP_BAD_CS_MX: 46644961713Sgirish case NXGE_FM_EREPORT_IPP_PKT_DIS_MX: 46744961713Sgirish case NXGE_FM_EREPORT_IPP_RESET_FAIL: 46844961713Sgirish IPP_REG_RD(nxgep->npi_handle, portn, IPP_INT_STATUS_REG, 46944961713Sgirish &ipps.value); 47044961713Sgirish if (err_id == NXGE_FM_EREPORT_IPP_EOP_MISS) 47144961713Sgirish ipps.bits.w0.dfifo_missed_eop = 1; 47244961713Sgirish else if (err_id == NXGE_FM_EREPORT_IPP_SOP_MISS) 47344961713Sgirish ipps.bits.w0.dfifo_missed_sop = 1; 47444961713Sgirish else if (err_id == NXGE_FM_EREPORT_IPP_DFIFO_UE) 47544961713Sgirish ipps.bits.w0.dfifo_uncorr_ecc_err = 1; 47644961713Sgirish else if (err_id == NXGE_FM_EREPORT_IPP_DFIFO_CE) 47744961713Sgirish ipps.bits.w0.dfifo_corr_ecc_err = 1; 47844961713Sgirish else if (err_id == NXGE_FM_EREPORT_IPP_PFIFO_PERR) 47944961713Sgirish ipps.bits.w0.pre_fifo_perr = 1; 48044961713Sgirish else if (err_id == NXGE_FM_EREPORT_IPP_ECC_ERR_MAX) 48144961713Sgirish ipps.bits.w0.ecc_err_cnt_ovfl = 1; 48244961713Sgirish else if (err_id == NXGE_FM_EREPORT_IPP_PFIFO_OVER) 48344961713Sgirish ipps.bits.w0.pre_fifo_overrun = 1; 48444961713Sgirish else if (err_id == NXGE_FM_EREPORT_IPP_PFIFO_UND) 48544961713Sgirish ipps.bits.w0.pre_fifo_underrun = 1; 48644961713Sgirish else if (err_id == NXGE_FM_EREPORT_IPP_BAD_CS_MX) 48744961713Sgirish ipps.bits.w0.bad_cksum_cnt_ovfl = 1; 48844961713Sgirish else if (err_id == NXGE_FM_EREPORT_IPP_PKT_DIS_MX) 48944961713Sgirish ipps.bits.w0.pkt_discard_cnt_ovfl = 1; 49044961713Sgirish cmn_err(CE_NOTE, "!Write 0x%llx to IPP_INT_STATUS_REG\n", 491a3c5bd6dSspeer (unsigned long long) ipps.value); 49244961713Sgirish IPP_REG_WR(nxgep->npi_handle, portn, IPP_INT_STATUS_REG, 493a3c5bd6dSspeer ipps.value); 49444961713Sgirish break; 49544961713Sgirish } 49644961713Sgirish } 49744961713Sgirish 498a3c5bd6dSspeer /* ARGSUSED */ 49944961713Sgirish nxge_status_t 50044961713Sgirish nxge_ipp_fatal_err_recover(p_nxge_t nxgep) 50144961713Sgirish { 502a3c5bd6dSspeer npi_handle_t handle; 503a3c5bd6dSspeer npi_status_t rs = NPI_SUCCESS; 504a3c5bd6dSspeer nxge_status_t status = NXGE_OK; 505a3c5bd6dSspeer uint8_t portn; 506a3c5bd6dSspeer uint16_t wr_ptr; 507a3c5bd6dSspeer uint16_t rd_ptr; 508a3c5bd6dSspeer uint32_t try_count; 509a3c5bd6dSspeer uint32_t dfifo_entries; 510a3c5bd6dSspeer ipp_status_t istatus; 511a3c5bd6dSspeer uint32_t d0, d1, d2, d3, d4; 512a3c5bd6dSspeer int i; 51344961713Sgirish 51444961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_ipp_fatal_err_recover")); 51544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 516a3c5bd6dSspeer "Recovering from RxPort error...")); 51744961713Sgirish 51844961713Sgirish handle = nxgep->npi_handle; 51944961713Sgirish portn = nxgep->mac.portnum; 52044961713Sgirish 52144961713Sgirish /* 522a3c5bd6dSspeer * Making sure that error source is cleared if this is an injected 523a3c5bd6dSspeer * error. 52444961713Sgirish */ 52544961713Sgirish IPP_REG_WR(handle, portn, IPP_ECC_CTRL_REG, 0); 52644961713Sgirish 52744961713Sgirish /* Disable RxMAC */ 52844961713Sgirish if (nxge_rx_mac_disable(nxgep) != NXGE_OK) 52944961713Sgirish goto fail; 53044961713Sgirish 53144961713Sgirish /* When recovering from IPP, RxDMA channel resets are not necessary */ 53244961713Sgirish /* Reset ZCP CFIFO */ 53344961713Sgirish NXGE_DEBUG_MSG((nxgep, IPP_CTL, "port%d Reset ZCP CFIFO...", portn)); 53444961713Sgirish if ((rs = npi_zcp_rest_cfifo_port(handle, portn)) != NPI_SUCCESS) 53544961713Sgirish goto fail; 53644961713Sgirish 53744961713Sgirish /* 538a3c5bd6dSspeer * Wait until ip read and write fifo pointers are equal 53944961713Sgirish */ 54044961713Sgirish (void) npi_ipp_get_dfifo_rd_ptr(handle, portn, &rd_ptr); 54144961713Sgirish (void) npi_ipp_get_dfifo_wr_ptr(handle, portn, &wr_ptr); 54244961713Sgirish try_count = 512; 54344961713Sgirish 54444961713Sgirish while ((try_count > 0) && (rd_ptr != wr_ptr)) { 54544961713Sgirish (void) npi_ipp_get_dfifo_rd_ptr(handle, portn, &rd_ptr); 54644961713Sgirish (void) npi_ipp_get_dfifo_wr_ptr(handle, portn, &wr_ptr); 54744961713Sgirish try_count--; 54844961713Sgirish } 54944961713Sgirish 55044961713Sgirish if (try_count == 0) { 55144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 552a3c5bd6dSspeer " nxge_ipp_reset: port%d IPP stalled..." 553a3c5bd6dSspeer " rd_fifo_ptr = 0x%x wr_fifo_ptr = 0x%x", 554a3c5bd6dSspeer portn, rd_ptr, wr_ptr)); 55544961713Sgirish /* 556a3c5bd6dSspeer * This means the fatal error occurred on the first line of the 557a3c5bd6dSspeer * fifo. In this case, just reset the IPP without draining the 558a3c5bd6dSspeer * PFIFO. 55944961713Sgirish */ 56044961713Sgirish } 56144961713Sgirish 562*59ac0c16Sdavemq if (nxgep->niu_type == N2_NIU) { 563*59ac0c16Sdavemq dfifo_entries = IPP_NIU_DFIFO_ENTRIES; 564*59ac0c16Sdavemq } else if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep->niu_type)) { 56544961713Sgirish if (portn < 2) 56644961713Sgirish dfifo_entries = IPP_P0_P1_DFIFO_ENTRIES; 56744961713Sgirish else 56844961713Sgirish dfifo_entries = IPP_P2_P3_DFIFO_ENTRIES; 569*59ac0c16Sdavemq } else { 57044961713Sgirish goto fail; 571*59ac0c16Sdavemq } 57244961713Sgirish 57344961713Sgirish /* Clean up DFIFO SRAM entries */ 57444961713Sgirish for (i = 0; i < dfifo_entries; i++) { 575a3c5bd6dSspeer if ((rs = npi_ipp_write_dfifo(handle, portn, 576a3c5bd6dSspeer i, 0, 0, 0, 0, 0)) != NPI_SUCCESS) 57744961713Sgirish goto fail; 578a3c5bd6dSspeer if ((rs = npi_ipp_read_dfifo(handle, portn, i, 579a3c5bd6dSspeer &d0, &d1, &d2, &d3, &d4)) != NPI_SUCCESS) 58044961713Sgirish goto fail; 58144961713Sgirish } 58244961713Sgirish 58344961713Sgirish /* Clear PFIFO DFIFO status bits */ 58444961713Sgirish if ((rs = npi_ipp_get_status(handle, portn, &istatus)) != NPI_SUCCESS) 58544961713Sgirish goto fail; 58644961713Sgirish if ((rs = npi_ipp_get_status(handle, portn, &istatus)) != NPI_SUCCESS) 58744961713Sgirish goto fail; 58844961713Sgirish 58944961713Sgirish /* Reset IPP */ 59044961713Sgirish NXGE_DEBUG_MSG((nxgep, IPP_CTL, "port%d Reset IPP...", portn)); 59144961713Sgirish if ((rs = npi_ipp_reset(handle, portn)) != NPI_SUCCESS) 59244961713Sgirish goto fail; 59344961713Sgirish 59444961713Sgirish NXGE_DEBUG_MSG((nxgep, IPP_CTL, "port%d Reset RxMAC...", portn)); 59544961713Sgirish if (nxge_rx_mac_reset(nxgep) != NXGE_OK) 59644961713Sgirish goto fail; 59744961713Sgirish 59844961713Sgirish NXGE_DEBUG_MSG((nxgep, IPP_CTL, "port%d Initialize RxMAC...", portn)); 59944961713Sgirish if ((status = nxge_rx_mac_init(nxgep)) != NXGE_OK) 60044961713Sgirish goto fail; 60144961713Sgirish 60244961713Sgirish NXGE_DEBUG_MSG((nxgep, IPP_CTL, "port%d Enable RxMAC...", portn)); 60344961713Sgirish if (nxge_rx_mac_enable(nxgep) != NXGE_OK) 60444961713Sgirish goto fail; 60544961713Sgirish 60644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 607a3c5bd6dSspeer "Recovery Sucessful, RxPort Restored")); 60844961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_ipp_fatal_err_recover")); 60944961713Sgirish 61044961713Sgirish return (NXGE_OK); 61144961713Sgirish fail: 61244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Recovery failed")); 61344961713Sgirish return (status | rs); 61444961713Sgirish } 61514ea4bb7Ssd 616a3c5bd6dSspeer /* ARGSUSED */ 6171a4557b6Syc /* 6181a4557b6Syc * A hardware bug may cause a faked ECCUE(ECC Uncorrectable Error). 6191a4557b6Syc * This function checks if a ECCUE is real(valid) or not. It is not 6201a4557b6Syc * real if rd_ptr == wr_ptr. 6211a4557b6Syc * The hardware module that has the bug is used not only by the IPP 6221a4557b6Syc * FIFO but also by the ZCP FIFO, therefore this function is also 6231a4557b6Syc * called by nxge_zcp_handle_sys_errors for validating the ZCP FIFO 6241a4557b6Syc * error. 6251a4557b6Syc */ 62614ea4bb7Ssd nxge_status_t 62714ea4bb7Ssd nxge_ipp_eccue_valid_check(p_nxge_t nxgep, boolean_t *valid) 62814ea4bb7Ssd { 62914ea4bb7Ssd npi_handle_t handle; 63014ea4bb7Ssd npi_status_t rs = NPI_SUCCESS; 63114ea4bb7Ssd uint8_t portn; 63214ea4bb7Ssd uint16_t rd_ptr; 63314ea4bb7Ssd uint16_t wr_ptr; 63414ea4bb7Ssd uint16_t curr_rd_ptr; 63514ea4bb7Ssd uint16_t curr_wr_ptr; 63614ea4bb7Ssd uint32_t stall_cnt; 63714ea4bb7Ssd uint32_t d0, d1, d2, d3, d4; 63814ea4bb7Ssd 63914ea4bb7Ssd handle = nxgep->npi_handle; 64014ea4bb7Ssd portn = nxgep->mac.portnum; 64114ea4bb7Ssd *valid = B_TRUE; 64214ea4bb7Ssd 64314ea4bb7Ssd if ((rs = npi_ipp_get_dfifo_rd_ptr(handle, portn, &rd_ptr)) 644a3c5bd6dSspeer != NPI_SUCCESS) 64514ea4bb7Ssd goto fail; 6461a4557b6Syc if ((rs = npi_ipp_get_dfifo_wr_ptr(handle, portn, &wr_ptr)) 647a3c5bd6dSspeer != NPI_SUCCESS) 64814ea4bb7Ssd goto fail; 64914ea4bb7Ssd 65014ea4bb7Ssd if (rd_ptr == wr_ptr) { 6511a4557b6Syc *valid = B_FALSE; /* FIFO not stuck, so it's not a real ECCUE */ 65214ea4bb7Ssd } else { 65314ea4bb7Ssd stall_cnt = 0; 65414ea4bb7Ssd while (stall_cnt < 16) { 655a3c5bd6dSspeer if ((rs = npi_ipp_get_dfifo_rd_ptr(handle, 656a3c5bd6dSspeer portn, &curr_rd_ptr)) != NPI_SUCCESS) 65714ea4bb7Ssd goto fail; 658a3c5bd6dSspeer if ((rs = npi_ipp_get_dfifo_wr_ptr(handle, 659a3c5bd6dSspeer portn, &curr_wr_ptr)) != NPI_SUCCESS) 66014ea4bb7Ssd goto fail; 66114ea4bb7Ssd 66214ea4bb7Ssd if ((rd_ptr == curr_rd_ptr) && (wr_ptr == curr_wr_ptr)) 66314ea4bb7Ssd stall_cnt++; 66414ea4bb7Ssd else { 66514ea4bb7Ssd *valid = B_FALSE; 66614ea4bb7Ssd break; 66714ea4bb7Ssd } 66814ea4bb7Ssd } 66914ea4bb7Ssd 670a3c5bd6dSspeer if (valid) { 671a3c5bd6dSspeer /* futher check to see if ECC UE is valid */ 672a3c5bd6dSspeer if ((rs = npi_ipp_read_dfifo(handle, portn, 673a3c5bd6dSspeer rd_ptr, &d0, &d1, &d2, &d3, 674a3c5bd6dSspeer &d4)) != NPI_SUCCESS) 67514ea4bb7Ssd goto fail; 67614ea4bb7Ssd if ((d4 & 0x1) == 0) /* Not the 1st line */ 67714ea4bb7Ssd *valid = B_FALSE; 67814ea4bb7Ssd } 67914ea4bb7Ssd } 68014ea4bb7Ssd return (NXGE_OK); 68114ea4bb7Ssd fail: 68214ea4bb7Ssd return (NXGE_ERROR | rs); 68314ea4bb7Ssd } 684