144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 22a3c5bd6dSspeer * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 2344961713Sgirish * Use is subject to license terms. 2444961713Sgirish */ 2544961713Sgirish 2644961713Sgirish #pragma ident "%Z%%M% %I% %E% SMI" 2744961713Sgirish 28a3c5bd6dSspeer #include <sys/nxge/nxge_impl.h> 2944961713Sgirish 3044961713Sgirish /* 3144961713Sgirish * Tunable Receive Completion Ring Configuration B parameters. 3244961713Sgirish */ 33a3c5bd6dSspeer uint16_t nxge_rx_pkt_thres; /* 16 bits */ 34a3c5bd6dSspeer uint8_t nxge_rx_pkt_timeout; /* 6 bits based on DMA clock divider */ 35a3c5bd6dSspeer 36a3c5bd6dSspeer lb_property_t lb_normal = {normal, "normal", nxge_lb_normal}; 37a3c5bd6dSspeer lb_property_t lb_external10g = {external, "external10g", nxge_lb_ext10g}; 38a3c5bd6dSspeer lb_property_t lb_external1000 = {external, "external1000", nxge_lb_ext1000}; 39a3c5bd6dSspeer lb_property_t lb_external100 = {external, "external100", nxge_lb_ext100}; 40a3c5bd6dSspeer lb_property_t lb_external10 = {external, "external10", nxge_lb_ext10}; 41a3c5bd6dSspeer lb_property_t lb_phy10g = {internal, "phy10g", nxge_lb_phy10g}; 42a3c5bd6dSspeer lb_property_t lb_phy1000 = {internal, "phy1000", nxge_lb_phy1000}; 43a3c5bd6dSspeer lb_property_t lb_phy = {internal, "phy", nxge_lb_phy}; 44a3c5bd6dSspeer lb_property_t lb_serdes10g = {internal, "serdes10g", nxge_lb_serdes10g}; 45a3c5bd6dSspeer lb_property_t lb_serdes1000 = {internal, "serdes", nxge_lb_serdes1000}; 46a3c5bd6dSspeer lb_property_t lb_mac10g = {internal, "mac10g", nxge_lb_mac10g}; 47a3c5bd6dSspeer lb_property_t lb_mac1000 = {internal, "mac1000", nxge_lb_mac1000}; 48a3c5bd6dSspeer lb_property_t lb_mac = {internal, "mac10/100", nxge_lb_mac}; 4944961713Sgirish 5044961713Sgirish uint32_t nxge_lb_dbg = 1; 5144961713Sgirish void nxge_get_mii(p_nxge_t nxgep, p_mblk_t mp); 5244961713Sgirish void nxge_put_mii(p_nxge_t nxgep, p_mblk_t mp); 53*ee5416c9Syc static nxge_status_t nxge_check_xaui_xfp(p_nxge_t nxgep); 5444961713Sgirish 5544961713Sgirish extern uint32_t nxge_rx_mode; 56a3c5bd6dSspeer extern uint32_t nxge_jumbo_mtu; 57a3c5bd6dSspeer extern boolean_t nxge_jumbo_enable; 5844961713Sgirish 59a3c5bd6dSspeer static void 60a3c5bd6dSspeer nxge_rtrace_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 6144961713Sgirish 62a3c5bd6dSspeer /* ARGSUSED */ 6344961713Sgirish void 6444961713Sgirish nxge_global_reset(p_nxge_t nxgep) 6544961713Sgirish { 6644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_global_reset")); 6744961713Sgirish 6844961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 6944961713Sgirish (void) nxge_intr_hw_disable(nxgep); 7044961713Sgirish 7144961713Sgirish if ((nxgep->suspended) || 72a3c5bd6dSspeer ((nxgep->statsp->port_stats.lb_mode == 73a3c5bd6dSspeer nxge_lb_phy1000) || 74a3c5bd6dSspeer (nxgep->statsp->port_stats.lb_mode == 75a3c5bd6dSspeer nxge_lb_phy10g) || 76a3c5bd6dSspeer (nxgep->statsp->port_stats.lb_mode == 77a3c5bd6dSspeer nxge_lb_serdes1000) || 78a3c5bd6dSspeer (nxgep->statsp->port_stats.lb_mode == 79a3c5bd6dSspeer nxge_lb_serdes10g))) { 8044961713Sgirish (void) nxge_link_init(nxgep); 8144961713Sgirish } 8244961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 8344961713Sgirish (void) nxge_mac_init(nxgep); 8444961713Sgirish (void) nxge_intr_hw_enable(nxgep); 8544961713Sgirish 8644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_global_reset")); 8744961713Sgirish } 8844961713Sgirish 89a3c5bd6dSspeer /* ARGSUSED */ 9044961713Sgirish void 9144961713Sgirish nxge_hw_id_init(p_nxge_t nxgep) 9244961713Sgirish { 9344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_id_init")); 9444961713Sgirish /* 9544961713Sgirish * Set up initial hardware parameters required such as mac mtu size. 9644961713Sgirish */ 9744961713Sgirish nxgep->mac.is_jumbo = B_FALSE; 98a3c5bd6dSspeer nxgep->mac.maxframesize = NXGE_MTU_DEFAULT_MAX; /* 1522 */ 9914ea4bb7Ssd if (nxgep->param_arr[param_accept_jumbo].value || nxge_jumbo_enable) { 10014ea4bb7Ssd nxgep->mac.maxframesize = (uint16_t)nxge_jumbo_mtu; 10144961713Sgirish nxgep->mac.is_jumbo = B_TRUE; 10244961713Sgirish } 10344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 10444961713Sgirish "==> nxge_hw_id_init: maxframesize %d", 10544961713Sgirish nxgep->mac.maxframesize)); 10644961713Sgirish 10744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_id_init")); 10844961713Sgirish } 10944961713Sgirish 110a3c5bd6dSspeer /* ARGSUSED */ 11144961713Sgirish void 11244961713Sgirish nxge_hw_init_niu_common(p_nxge_t nxgep) 11344961713Sgirish { 114a3c5bd6dSspeer p_nxge_hw_list_t hw_p; 11544961713Sgirish 11644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_init_niu_common")); 11744961713Sgirish 11844961713Sgirish if ((hw_p = nxgep->nxge_hw_p) == NULL) { 11944961713Sgirish return; 12044961713Sgirish } 12144961713Sgirish MUTEX_ENTER(&hw_p->nxge_cfg_lock); 12244961713Sgirish if (hw_p->flags & COMMON_INIT_DONE) { 12344961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 12444961713Sgirish "nxge_hw_init_niu_common" 12544961713Sgirish " already done for dip $%p function %d exiting", 126a3c5bd6dSspeer hw_p->parent_devp, nxgep->function_num)); 12744961713Sgirish MUTEX_EXIT(&hw_p->nxge_cfg_lock); 12844961713Sgirish return; 12944961713Sgirish } 13044961713Sgirish 13144961713Sgirish hw_p->flags = COMMON_INIT_START; 13244961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, "nxge_hw_init_niu_common" 13344961713Sgirish " Started for device id %x with function %d", 134a3c5bd6dSspeer hw_p->parent_devp, nxgep->function_num)); 135a3c5bd6dSspeer 136a3c5bd6dSspeer /* per neptune common block init */ 137a3c5bd6dSspeer (void) nxge_fflp_hw_reset(nxgep); 13844961713Sgirish 13944961713Sgirish hw_p->flags = COMMON_INIT_DONE; 14044961713Sgirish MUTEX_EXIT(&hw_p->nxge_cfg_lock); 14144961713Sgirish 14244961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, "nxge_hw_init_niu_common" 14344961713Sgirish " Done for device id %x with function %d", 144a3c5bd6dSspeer hw_p->parent_devp, nxgep->function_num)); 14544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_init_niu_common")); 14644961713Sgirish } 14744961713Sgirish 148a3c5bd6dSspeer /* ARGSUSED */ 14944961713Sgirish uint_t 15044961713Sgirish nxge_intr(void *arg1, void *arg2) 15144961713Sgirish { 152a3c5bd6dSspeer p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 153a3c5bd6dSspeer p_nxge_t nxgep = (p_nxge_t)arg2; 154a3c5bd6dSspeer uint_t serviced = DDI_INTR_UNCLAIMED; 155a3c5bd6dSspeer uint8_t ldv; 156a3c5bd6dSspeer npi_handle_t handle; 157a3c5bd6dSspeer p_nxge_ldgv_t ldgvp; 158a3c5bd6dSspeer p_nxge_ldg_t ldgp, t_ldgp; 159a3c5bd6dSspeer p_nxge_ldv_t t_ldvp; 160a3c5bd6dSspeer uint64_t vector0 = 0, vector1 = 0, vector2 = 0; 161a3c5bd6dSspeer int i, j, nldvs, nintrs = 1; 162a3c5bd6dSspeer npi_status_t rs = NPI_SUCCESS; 16344961713Sgirish 16444961713Sgirish /* DDI interface returns second arg as NULL (n2 niumx driver) !!! */ 165a3c5bd6dSspeer if (arg2 == NULL || (void *) ldvp->nxgep != arg2) { 16644961713Sgirish nxgep = ldvp->nxgep; 16744961713Sgirish } 16844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr")); 16944961713Sgirish 17044961713Sgirish if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 17144961713Sgirish NXGE_ERROR_MSG((nxgep, INT_CTL, 172a3c5bd6dSspeer "<== nxge_intr: not initialized 0x%x", serviced)); 17344961713Sgirish return (serviced); 17444961713Sgirish } 17544961713Sgirish 17644961713Sgirish ldgvp = nxgep->ldgvp; 177a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: ldgvp $%p", ldgvp)); 17844961713Sgirish if (ldvp == NULL && ldgvp) { 17944961713Sgirish t_ldvp = ldvp = ldgvp->ldvp; 18044961713Sgirish } 18144961713Sgirish if (ldvp) { 18244961713Sgirish ldgp = t_ldgp = ldvp->ldgp; 18344961713Sgirish } 18444961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: " 185a3c5bd6dSspeer "ldgvp $%p ldvp $%p ldgp $%p", ldgvp, ldvp, ldgp)); 18644961713Sgirish if (ldgvp == NULL || ldvp == NULL || ldgp == NULL) { 18744961713Sgirish NXGE_ERROR_MSG((nxgep, INT_CTL, "==> nxge_intr: " 188a3c5bd6dSspeer "ldgvp $%p ldvp $%p ldgp $%p", ldgvp, ldvp, ldgp)); 18944961713Sgirish NXGE_ERROR_MSG((nxgep, INT_CTL, "<== nxge_intr: not ready")); 19044961713Sgirish return (DDI_INTR_UNCLAIMED); 19144961713Sgirish } 19244961713Sgirish /* 193a3c5bd6dSspeer * This interrupt handler will have to go through all the logical 194a3c5bd6dSspeer * devices to find out which logical device interrupts us and then call 19544961713Sgirish * its handler to process the events. 19644961713Sgirish */ 19744961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 19844961713Sgirish t_ldgp = ldgp; 19944961713Sgirish t_ldvp = ldgp->ldvp; 20044961713Sgirish 20144961713Sgirish nldvs = ldgp->nldvs; 20244961713Sgirish 20344961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: #ldvs %d #intrs %d", 204a3c5bd6dSspeer nldvs, ldgvp->ldg_intrs)); 20544961713Sgirish 20644961713Sgirish serviced = DDI_INTR_CLAIMED; 20744961713Sgirish for (i = 0; i < nintrs; i++, t_ldgp++) { 20844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr(%d): #ldvs %d " 209a3c5bd6dSspeer " #intrs %d", i, nldvs, nintrs)); 21044961713Sgirish /* Get this group's flag bits. */ 21144961713Sgirish t_ldgp->interrupted = B_FALSE; 21244961713Sgirish rs = npi_ldsv_ldfs_get(handle, t_ldgp->ldg, 213a3c5bd6dSspeer &vector0, &vector1, &vector2); 21444961713Sgirish if (rs) { 21544961713Sgirish continue; 21644961713Sgirish } 21744961713Sgirish if (!vector0 && !vector1 && !vector2) { 21844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: " 21944961713Sgirish "no interrupts on group %d", t_ldgp->ldg)); 22044961713Sgirish continue; 22144961713Sgirish } 22244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: " 22344961713Sgirish "vector0 0x%llx vector1 0x%llx vector2 0x%llx", 22444961713Sgirish vector0, vector1, vector2)); 22544961713Sgirish t_ldgp->interrupted = B_TRUE; 22644961713Sgirish nldvs = t_ldgp->nldvs; 22744961713Sgirish for (j = 0; j < nldvs; j++, t_ldvp++) { 22844961713Sgirish /* 22944961713Sgirish * Call device's handler if flag bits are on. 23044961713Sgirish */ 23144961713Sgirish ldv = t_ldvp->ldv; 23244961713Sgirish if (((ldv < NXGE_MAC_LD_START) && 233a3c5bd6dSspeer (LDV_ON(ldv, vector0) | 23444961713Sgirish (LDV_ON(ldv, vector1)))) || 235a3c5bd6dSspeer (ldv >= NXGE_MAC_LD_START && 236a3c5bd6dSspeer ((LDV2_ON_1(ldv, vector2)) || 237a3c5bd6dSspeer (LDV2_ON_2(ldv, vector2))))) { 23844961713Sgirish (void) (t_ldvp->ldv_intr_handler)( 23944961713Sgirish (caddr_t)t_ldvp, arg2); 24044961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 24144961713Sgirish "==> nxge_intr: " 24244961713Sgirish "calling device %d #ldvs %d #intrs %d", 24344961713Sgirish j, nldvs, nintrs)); 24444961713Sgirish } 24544961713Sgirish } 24644961713Sgirish } 24744961713Sgirish 24844961713Sgirish t_ldgp = ldgp; 24944961713Sgirish for (i = 0; i < nintrs; i++, t_ldgp++) { 25044961713Sgirish /* rearm group interrupts */ 25144961713Sgirish if (t_ldgp->interrupted) { 25244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: arm " 25344961713Sgirish "group %d", t_ldgp->ldg)); 25444961713Sgirish (void) npi_intr_ldg_mgmt_set(handle, t_ldgp->ldg, 25544961713Sgirish t_ldgp->arm, t_ldgp->ldg_timer); 25644961713Sgirish } 25744961713Sgirish } 25844961713Sgirish 25944961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr: serviced 0x%x", 26044961713Sgirish serviced)); 26144961713Sgirish return (serviced); 26244961713Sgirish } 26344961713Sgirish 264*ee5416c9Syc /* ARGSUSED */ 265*ee5416c9Syc static nxge_status_t 266*ee5416c9Syc nxge_check_xaui_xfp(p_nxge_t nxgep) 267*ee5416c9Syc { 268*ee5416c9Syc nxge_status_t status = NXGE_OK; 269*ee5416c9Syc uint8_t phy_port_addr; 270*ee5416c9Syc uint16_t val; 271*ee5416c9Syc uint16_t val1; 272*ee5416c9Syc uint8_t portn; 273*ee5416c9Syc 274*ee5416c9Syc NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_check_xaui_xfp")); 275*ee5416c9Syc 276*ee5416c9Syc portn = nxgep->mac.portnum; 277*ee5416c9Syc phy_port_addr = nxgep->statsp->mac_stats.xcvr_portn; 278*ee5416c9Syc 279*ee5416c9Syc if ((status = nxge_mdio_read(nxgep, phy_port_addr, 280*ee5416c9Syc BCM8704_USER_DEV3_ADDR, 281*ee5416c9Syc BCM8704_USER_ANALOG_STATUS0_REG, &val)) == NXGE_OK) { 282*ee5416c9Syc status = nxge_mdio_read(nxgep, phy_port_addr, 283*ee5416c9Syc BCM8704_USER_DEV3_ADDR, 284*ee5416c9Syc BCM8704_USER_TX_ALARM_STATUS_REG, &val1); 285*ee5416c9Syc } 286*ee5416c9Syc if (status != NXGE_OK) { 287*ee5416c9Syc NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 288*ee5416c9Syc NXGE_FM_EREPORT_XAUI_ERR); 289*ee5416c9Syc NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 290*ee5416c9Syc "XAUI is bad or absent on port<%d>\n", portn)); 291*ee5416c9Syc } else if (nxgep->mac.portmode == PORT_10G_FIBER) { 292*ee5416c9Syc /* 293*ee5416c9Syc * 0x03FC = 0000 0011 1111 1100 294*ee5416c9Syc * 0x639C = 0110 0011 1001 1100 295*ee5416c9Syc * bit14 = 1: PDM loss-of-light indicator 296*ee5416c9Syc * bit13 = 1: PDM Rx loss-of-signal 297*ee5416c9Syc * bit6 = 0: Light is NOT ok 298*ee5416c9Syc * bit5 = 0: PMD Rx signal is NOT ok 299*ee5416c9Syc */ 300*ee5416c9Syc if (val != 0x3FC && val == 0x639C) { 301*ee5416c9Syc NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 302*ee5416c9Syc NXGE_FM_EREPORT_XFP_ERR); 303*ee5416c9Syc NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 304*ee5416c9Syc "XFP is bad or absent on port<%d>\n", portn)); 305*ee5416c9Syc status = NXGE_ERROR; 306*ee5416c9Syc } 307*ee5416c9Syc } 308*ee5416c9Syc NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_check_xaui_xfp")); 309*ee5416c9Syc return (status); 310*ee5416c9Syc } 311*ee5416c9Syc 312*ee5416c9Syc 313a3c5bd6dSspeer /* ARGSUSED */ 31444961713Sgirish uint_t 31544961713Sgirish nxge_syserr_intr(void *arg1, void *arg2) 31644961713Sgirish { 317a3c5bd6dSspeer p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 318a3c5bd6dSspeer p_nxge_t nxgep = (p_nxge_t)arg2; 319a3c5bd6dSspeer p_nxge_ldg_t ldgp = NULL; 320a3c5bd6dSspeer npi_handle_t handle; 321a3c5bd6dSspeer sys_err_stat_t estat; 322a3c5bd6dSspeer uint_t serviced = DDI_INTR_UNCLAIMED; 32344961713Sgirish 32444961713Sgirish if (arg1 == NULL && arg2 == NULL) { 32544961713Sgirish return (serviced); 32644961713Sgirish } 327a3c5bd6dSspeer if (arg2 == NULL || ((ldvp != NULL && (void *) ldvp->nxgep != arg2))) { 32844961713Sgirish if (ldvp != NULL) { 32944961713Sgirish nxgep = ldvp->nxgep; 33044961713Sgirish } 33144961713Sgirish } 33244961713Sgirish NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, 333a3c5bd6dSspeer "==> nxge_syserr_intr: arg2 $%p arg1 $%p", nxgep, ldvp)); 33444961713Sgirish if (ldvp != NULL && ldvp->use_timer == B_FALSE) { 33544961713Sgirish ldgp = ldvp->ldgp; 33644961713Sgirish if (ldgp == NULL) { 33744961713Sgirish NXGE_ERROR_MSG((nxgep, SYSERR_CTL, 33844961713Sgirish "<== nxge_syserrintr(no logical group): " 339a3c5bd6dSspeer "arg2 $%p arg1 $%p", nxgep, ldvp)); 34044961713Sgirish return (DDI_INTR_UNCLAIMED); 34144961713Sgirish } 34244961713Sgirish /* 34344961713Sgirish * Get the logical device state if the function uses interrupt. 34444961713Sgirish */ 34544961713Sgirish } 34644961713Sgirish 34744961713Sgirish /* This interrupt handler is for system error interrupts. */ 34844961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 34944961713Sgirish estat.value = 0; 35044961713Sgirish (void) npi_fzc_sys_err_stat_get(handle, &estat); 35144961713Sgirish NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, 352a3c5bd6dSspeer "==> nxge_syserr_intr: device error 0x%016llx", estat.value)); 35344961713Sgirish 35444961713Sgirish if (estat.bits.ldw.smx) { 35544961713Sgirish /* SMX */ 35644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 35744961713Sgirish "==> nxge_syserr_intr: device error - SMX")); 35844961713Sgirish } else if (estat.bits.ldw.mac) { 35944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 36044961713Sgirish "==> nxge_syserr_intr: device error - MAC")); 36144961713Sgirish /* 362a3c5bd6dSspeer * There is nothing to be done here. All MAC errors go to per 363a3c5bd6dSspeer * MAC port interrupt. MIF interrupt is the only MAC sub-block 364a3c5bd6dSspeer * that can generate status here. MIF status reported will be 365a3c5bd6dSspeer * ignored here. It is checked by per port timer instead. 36644961713Sgirish */ 36744961713Sgirish } else if (estat.bits.ldw.ipp) { 36844961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 36944961713Sgirish "==> nxge_syserr_intr: device error - IPP")); 37044961713Sgirish (void) nxge_ipp_handle_sys_errors(nxgep); 37144961713Sgirish } else if (estat.bits.ldw.zcp) { 37244961713Sgirish /* ZCP */ 37344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 37444961713Sgirish "==> nxge_syserr_intr: device error - ZCP")); 37544961713Sgirish (void) nxge_zcp_handle_sys_errors(nxgep); 37644961713Sgirish } else if (estat.bits.ldw.tdmc) { 37744961713Sgirish /* TDMC */ 37844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 37944961713Sgirish "==> nxge_syserr_intr: device error - TDMC")); 38044961713Sgirish /* 381a3c5bd6dSspeer * There is no TDMC system errors defined in the PRM. All TDMC 382a3c5bd6dSspeer * channel specific errors are reported on a per channel basis. 38344961713Sgirish */ 38444961713Sgirish } else if (estat.bits.ldw.rdmc) { 38544961713Sgirish /* RDMC */ 38644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 38744961713Sgirish "==> nxge_syserr_intr: device error - RDMC")); 38844961713Sgirish (void) nxge_rxdma_handle_sys_errors(nxgep); 38944961713Sgirish } else if (estat.bits.ldw.txc) { 39044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 39144961713Sgirish "==> nxge_syserr_intr: device error - TXC")); 39244961713Sgirish (void) nxge_txc_handle_sys_errors(nxgep); 39344961713Sgirish } else if ((nxgep->niu_type != N2_NIU) && estat.bits.ldw.peu) { 39444961713Sgirish /* PCI-E */ 39544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 39644961713Sgirish "==> nxge_syserr_intr: device error - PCI-E")); 39744961713Sgirish } else if (estat.bits.ldw.meta1) { 39844961713Sgirish /* META1 */ 39944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 40044961713Sgirish "==> nxge_syserr_intr: device error - META1")); 40144961713Sgirish } else if (estat.bits.ldw.meta2) { 40244961713Sgirish /* META2 */ 40344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 40444961713Sgirish "==> nxge_syserr_intr: device error - META2")); 40544961713Sgirish } else if (estat.bits.ldw.fflp) { 40644961713Sgirish /* FFLP */ 40744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 40844961713Sgirish "==> nxge_syserr_intr: device error - FFLP")); 40944961713Sgirish (void) nxge_fflp_handle_sys_errors(nxgep); 41044961713Sgirish } 411*ee5416c9Syc 412*ee5416c9Syc if (nxgep->mac.portmode == PORT_10G_FIBER || 413*ee5416c9Syc nxgep->mac.portmode == PORT_10G_COPPER) { 414*ee5416c9Syc if (nxge_check_xaui_xfp(nxgep) != NXGE_OK) { 415*ee5416c9Syc NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 416*ee5416c9Syc "==> nxge_syserr_intr: device error - XAUI")); 417*ee5416c9Syc } 418*ee5416c9Syc } 419*ee5416c9Syc 42044961713Sgirish serviced = DDI_INTR_CLAIMED; 42144961713Sgirish 42244961713Sgirish if (ldgp != NULL && ldvp != NULL && ldgp->nldvs == 1 && 423a3c5bd6dSspeer !ldvp->use_timer) { 42444961713Sgirish (void) npi_intr_ldg_mgmt_set(handle, ldgp->ldg, 42544961713Sgirish B_TRUE, ldgp->ldg_timer); 42644961713Sgirish } 42744961713Sgirish NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "<== nxge_syserr_intr")); 42844961713Sgirish return (serviced); 42944961713Sgirish } 43044961713Sgirish 431a3c5bd6dSspeer /* ARGSUSED */ 43244961713Sgirish void 43344961713Sgirish nxge_intr_hw_enable(p_nxge_t nxgep) 43444961713Sgirish { 43544961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_hw_enable")); 43644961713Sgirish (void) nxge_intr_mask_mgmt_set(nxgep, B_TRUE); 43744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_hw_enable")); 43844961713Sgirish } 43944961713Sgirish 440a3c5bd6dSspeer /* ARGSUSED */ 44144961713Sgirish void 44244961713Sgirish nxge_intr_hw_disable(p_nxge_t nxgep) 44344961713Sgirish { 44444961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_hw_disable")); 44544961713Sgirish (void) nxge_intr_mask_mgmt_set(nxgep, B_FALSE); 44644961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_hw_disable")); 44744961713Sgirish } 44844961713Sgirish 449a3c5bd6dSspeer /* ARGSUSED */ 45044961713Sgirish void 45144961713Sgirish nxge_rx_hw_blank(void *arg, time_t ticks, uint_t count) 45244961713Sgirish { 453a3c5bd6dSspeer p_nxge_t nxgep = (p_nxge_t)arg; 454a3c5bd6dSspeer uint8_t channel; 455a3c5bd6dSspeer npi_handle_t handle; 456a3c5bd6dSspeer p_nxge_ldgv_t ldgvp; 457a3c5bd6dSspeer p_nxge_ldv_t ldvp; 458a3c5bd6dSspeer int i; 45944961713Sgirish 46044961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_rx_hw_blank")); 46144961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 46244961713Sgirish 46344961713Sgirish if ((ldgvp = nxgep->ldgvp) == NULL) { 46444961713Sgirish NXGE_ERROR_MSG((nxgep, INT_CTL, 46544961713Sgirish "<== nxge_rx_hw_blank (not enabled)")); 46644961713Sgirish return; 46744961713Sgirish } 46844961713Sgirish ldvp = nxgep->ldgvp->ldvp; 46944961713Sgirish if (ldvp == NULL) { 47044961713Sgirish return; 47144961713Sgirish } 47244961713Sgirish for (i = 0; i < ldgvp->nldvs; i++, ldvp++) { 47344961713Sgirish if (ldvp->is_rxdma) { 47444961713Sgirish channel = ldvp->channel; 47544961713Sgirish (void) npi_rxdma_cfg_rdc_rcr_threshold(handle, 47644961713Sgirish channel, count); 47744961713Sgirish (void) npi_rxdma_cfg_rdc_rcr_timeout(handle, 47844961713Sgirish channel, ticks); 47944961713Sgirish } 48044961713Sgirish } 48144961713Sgirish 48244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_rx_hw_blank")); 48344961713Sgirish } 48444961713Sgirish 485a3c5bd6dSspeer /* ARGSUSED */ 48644961713Sgirish void 48744961713Sgirish nxge_hw_stop(p_nxge_t nxgep) 48844961713Sgirish { 48944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_stop")); 49044961713Sgirish 49144961713Sgirish (void) nxge_tx_mac_disable(nxgep); 49244961713Sgirish (void) nxge_rx_mac_disable(nxgep); 49344961713Sgirish (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP); 49444961713Sgirish (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 49544961713Sgirish 49644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_stop")); 49744961713Sgirish } 49844961713Sgirish 499a3c5bd6dSspeer /* ARGSUSED */ 50044961713Sgirish void 50144961713Sgirish nxge_hw_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 50244961713Sgirish { 50344961713Sgirish int cmd; 50444961713Sgirish 50544961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_hw_ioctl")); 50644961713Sgirish 50744961713Sgirish if (nxgep == NULL) { 50844961713Sgirish miocnak(wq, mp, 0, EINVAL); 50944961713Sgirish return; 51044961713Sgirish } 51144961713Sgirish iocp->ioc_error = 0; 51244961713Sgirish cmd = iocp->ioc_cmd; 51344961713Sgirish 51444961713Sgirish switch (cmd) { 51544961713Sgirish default: 51644961713Sgirish miocnak(wq, mp, 0, EINVAL); 51744961713Sgirish return; 51844961713Sgirish 51944961713Sgirish case NXGE_GET_MII: 52044961713Sgirish nxge_get_mii(nxgep, mp->b_cont); 52144961713Sgirish miocack(wq, mp, sizeof (uint16_t), 0); 52244961713Sgirish break; 52344961713Sgirish 52444961713Sgirish case NXGE_PUT_MII: 52544961713Sgirish nxge_put_mii(nxgep, mp->b_cont); 52644961713Sgirish miocack(wq, mp, 0, 0); 52744961713Sgirish break; 52844961713Sgirish 52944961713Sgirish case NXGE_GET64: 53044961713Sgirish nxge_get64(nxgep, mp->b_cont); 53144961713Sgirish miocack(wq, mp, sizeof (uint32_t), 0); 53244961713Sgirish break; 53344961713Sgirish 53444961713Sgirish case NXGE_PUT64: 53544961713Sgirish nxge_put64(nxgep, mp->b_cont); 53644961713Sgirish miocack(wq, mp, 0, 0); 53744961713Sgirish break; 53844961713Sgirish 53944961713Sgirish case NXGE_PUT_TCAM: 54044961713Sgirish nxge_put_tcam(nxgep, mp->b_cont); 54144961713Sgirish miocack(wq, mp, 0, 0); 54244961713Sgirish break; 54344961713Sgirish 54444961713Sgirish case NXGE_GET_TCAM: 54544961713Sgirish nxge_get_tcam(nxgep, mp->b_cont); 54644961713Sgirish miocack(wq, mp, 0, 0); 54744961713Sgirish break; 54844961713Sgirish 54944961713Sgirish case NXGE_TX_REGS_DUMP: 55044961713Sgirish nxge_txdma_regs_dump_channels(nxgep); 55144961713Sgirish miocack(wq, mp, 0, 0); 55244961713Sgirish break; 55344961713Sgirish case NXGE_RX_REGS_DUMP: 55444961713Sgirish nxge_rxdma_regs_dump_channels(nxgep); 55544961713Sgirish miocack(wq, mp, 0, 0); 55644961713Sgirish break; 55744961713Sgirish case NXGE_VIR_INT_REGS_DUMP: 55844961713Sgirish case NXGE_INT_REGS_DUMP: 55944961713Sgirish nxge_virint_regs_dump(nxgep); 56044961713Sgirish miocack(wq, mp, 0, 0); 56144961713Sgirish break; 56244961713Sgirish case NXGE_RTRACE: 56344961713Sgirish nxge_rtrace_ioctl(nxgep, wq, mp, iocp); 56444961713Sgirish break; 56544961713Sgirish } 56644961713Sgirish } 56744961713Sgirish 568a3c5bd6dSspeer /* ARGSUSED */ 56944961713Sgirish void 57044961713Sgirish nxge_loopback_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, 571a3c5bd6dSspeer struct iocblk *iocp) 57244961713Sgirish { 573a3c5bd6dSspeer p_lb_property_t lb_props; 574a3c5bd6dSspeer 575a3c5bd6dSspeer size_t size; 576a3c5bd6dSspeer int i; 57744961713Sgirish 57844961713Sgirish if (mp->b_cont == NULL) { 57944961713Sgirish miocnak(wq, mp, 0, EINVAL); 58044961713Sgirish } 58144961713Sgirish switch (iocp->ioc_cmd) { 58244961713Sgirish case LB_GET_MODE: 58344961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "NXGE_GET_LB_MODE command")); 58444961713Sgirish if (nxgep != NULL) { 58544961713Sgirish *(lb_info_sz_t *)mp->b_cont->b_rptr = 586a3c5bd6dSspeer nxgep->statsp->port_stats.lb_mode; 58744961713Sgirish miocack(wq, mp, sizeof (nxge_lb_t), 0); 588*ee5416c9Syc } else { 58944961713Sgirish miocnak(wq, mp, 0, EINVAL); 590*ee5416c9Syc } 59144961713Sgirish break; 59244961713Sgirish case LB_SET_MODE: 59344961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "NXGE_SET_LB_MODE command")); 59444961713Sgirish if (iocp->ioc_count != sizeof (uint32_t)) { 59544961713Sgirish miocack(wq, mp, 0, 0); 59644961713Sgirish break; 59744961713Sgirish } 59844961713Sgirish if ((nxgep != NULL) && nxge_set_lb(nxgep, wq, mp->b_cont)) { 59944961713Sgirish miocack(wq, mp, 0, 0); 60044961713Sgirish } else { 60144961713Sgirish miocnak(wq, mp, 0, EPROTO); 60244961713Sgirish } 60344961713Sgirish break; 60444961713Sgirish case LB_GET_INFO_SIZE: 60544961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "LB_GET_INFO_SIZE command")); 60644961713Sgirish if (nxgep != NULL) { 60744961713Sgirish size = sizeof (lb_normal); 60844961713Sgirish if (nxgep->statsp->mac_stats.cap_10gfdx) { 60944961713Sgirish size += sizeof (lb_external10g); 61044961713Sgirish size += sizeof (lb_phy10g); 61144961713Sgirish size += sizeof (lb_serdes10g); 61244961713Sgirish size += sizeof (lb_mac10g); 61344961713Sgirish } 61444961713Sgirish if (nxgep->statsp->mac_stats.cap_1000fdx) { 61544961713Sgirish size += sizeof (lb_external1000); 61644961713Sgirish size += sizeof (lb_mac1000); 61744961713Sgirish if (nxgep->mac.portmode == PORT_1G_COPPER) 61844961713Sgirish size += sizeof (lb_phy1000); 61944961713Sgirish } 62044961713Sgirish if (nxgep->statsp->mac_stats.cap_100fdx) 62144961713Sgirish size += sizeof (lb_external100); 62244961713Sgirish if (nxgep->statsp->mac_stats.cap_10fdx) 62344961713Sgirish size += sizeof (lb_external10); 6242e59129aSraghus else if ((nxgep->mac.portmode == PORT_1G_FIBER) || 6252e59129aSraghus (nxgep->mac.portmode == PORT_1G_SERDES)) 62644961713Sgirish size += sizeof (lb_serdes1000); 6272e59129aSraghus 62844961713Sgirish *(lb_info_sz_t *)mp->b_cont->b_rptr = size; 62944961713Sgirish 63044961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, 63144961713Sgirish "NXGE_GET_LB_INFO command: size %d", size)); 63244961713Sgirish miocack(wq, mp, sizeof (lb_info_sz_t), 0); 63344961713Sgirish } else 63444961713Sgirish miocnak(wq, mp, 0, EINVAL); 63544961713Sgirish break; 63644961713Sgirish 63744961713Sgirish case LB_GET_INFO: 63844961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "NXGE_GET_LB_INFO command")); 63944961713Sgirish if (nxgep != NULL) { 64044961713Sgirish size = sizeof (lb_normal); 64144961713Sgirish if (nxgep->statsp->mac_stats.cap_10gfdx) { 64244961713Sgirish size += sizeof (lb_external10g); 64344961713Sgirish size += sizeof (lb_phy10g); 64444961713Sgirish size += sizeof (lb_serdes10g); 64544961713Sgirish size += sizeof (lb_mac10g); 64644961713Sgirish } 64744961713Sgirish if (nxgep->statsp->mac_stats.cap_1000fdx) { 64844961713Sgirish size += sizeof (lb_external1000); 64944961713Sgirish size += sizeof (lb_mac1000); 65044961713Sgirish if (nxgep->mac.portmode == PORT_1G_COPPER) 65144961713Sgirish size += sizeof (lb_phy1000); 65244961713Sgirish } 65344961713Sgirish if (nxgep->statsp->mac_stats.cap_100fdx) 65444961713Sgirish size += sizeof (lb_external100); 65544961713Sgirish if (nxgep->statsp->mac_stats.cap_10fdx) 65644961713Sgirish size += sizeof (lb_external10); 6572e59129aSraghus else if ((nxgep->mac.portmode == PORT_1G_FIBER) || 6582e59129aSraghus (nxgep->mac.portmode == PORT_1G_SERDES)) 65944961713Sgirish size += sizeof (lb_serdes1000); 66044961713Sgirish 66144961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, 66244961713Sgirish "NXGE_GET_LB_INFO command: size %d", size)); 66344961713Sgirish if (size == iocp->ioc_count) { 66444961713Sgirish i = 0; 66544961713Sgirish lb_props = (p_lb_property_t)mp->b_cont->b_rptr; 66644961713Sgirish lb_props[i++] = lb_normal; 66744961713Sgirish if (nxgep->statsp->mac_stats.cap_10gfdx) { 66844961713Sgirish lb_props[i++] = lb_mac10g; 66944961713Sgirish lb_props[i++] = lb_serdes10g; 67044961713Sgirish lb_props[i++] = lb_phy10g; 67144961713Sgirish lb_props[i++] = lb_external10g; 67244961713Sgirish } 67344961713Sgirish if (nxgep->statsp->mac_stats.cap_1000fdx) 67444961713Sgirish lb_props[i++] = lb_external1000; 67544961713Sgirish if (nxgep->statsp->mac_stats.cap_100fdx) 67644961713Sgirish lb_props[i++] = lb_external100; 67744961713Sgirish if (nxgep->statsp->mac_stats.cap_10fdx) 67844961713Sgirish lb_props[i++] = lb_external10; 67944961713Sgirish if (nxgep->statsp->mac_stats.cap_1000fdx) 68044961713Sgirish lb_props[i++] = lb_mac1000; 68144961713Sgirish if (nxgep->mac.portmode == PORT_1G_COPPER) { 68244961713Sgirish if (nxgep->statsp->mac_stats. 683a3c5bd6dSspeer cap_1000fdx) 68444961713Sgirish lb_props[i++] = lb_phy1000; 6852e59129aSraghus } else if ((nxgep->mac.portmode == 6862e59129aSraghus PORT_1G_FIBER) || 6872e59129aSraghus (nxgep->mac.portmode == PORT_1G_SERDES)) { 68844961713Sgirish lb_props[i++] = lb_serdes1000; 6892e59129aSraghus } 69044961713Sgirish miocack(wq, mp, size, 0); 69144961713Sgirish } else 69244961713Sgirish miocnak(wq, mp, 0, EINVAL); 69344961713Sgirish } else { 69444961713Sgirish miocnak(wq, mp, 0, EINVAL); 69544961713Sgirish cmn_err(CE_NOTE, "!nxge_hw_ioctl: invalid command 0x%x", 69644961713Sgirish iocp->ioc_cmd); 69744961713Sgirish } 69844961713Sgirish break; 69944961713Sgirish } 70044961713Sgirish } 70144961713Sgirish 70244961713Sgirish /* 70344961713Sgirish * DMA channel interfaces to access various channel specific 70444961713Sgirish * hardware functions. 70544961713Sgirish */ 706a3c5bd6dSspeer /* ARGSUSED */ 70744961713Sgirish void 70844961713Sgirish nxge_rxdma_channel_put64(nxge_os_acc_handle_t handle, void *reg_addrp, 709a3c5bd6dSspeer uint32_t reg_base, uint16_t channel, uint64_t reg_data) 71044961713Sgirish { 711a3c5bd6dSspeer uint64_t reg_offset; 71244961713Sgirish 71344961713Sgirish NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_put64")); 71444961713Sgirish 71544961713Sgirish /* 716a3c5bd6dSspeer * Channel is assumed to be from 0 to the maximum DMA channel #. If we 717a3c5bd6dSspeer * use the virtual DMA CSR address space from the config space (in PCI 718a3c5bd6dSspeer * case), then the following code need to be use different offset 71944961713Sgirish * computation macro. 72044961713Sgirish */ 72144961713Sgirish reg_offset = reg_base + DMC_OFFSET(channel); 72244961713Sgirish NXGE_PIO_WRITE64(handle, reg_addrp, reg_offset, reg_data); 72344961713Sgirish 72444961713Sgirish NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_put64")); 72544961713Sgirish } 72644961713Sgirish 727a3c5bd6dSspeer /* ARGSUSED */ 72844961713Sgirish uint64_t 72944961713Sgirish nxge_rxdma_channel_get64(nxge_os_acc_handle_t handle, void *reg_addrp, 730a3c5bd6dSspeer uint32_t reg_base, uint16_t channel) 73144961713Sgirish { 732a3c5bd6dSspeer uint64_t reg_offset; 73344961713Sgirish 73444961713Sgirish NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_get64")); 73544961713Sgirish 73644961713Sgirish /* 737a3c5bd6dSspeer * Channel is assumed to be from 0 to the maximum DMA channel #. If we 738a3c5bd6dSspeer * use the virtual DMA CSR address space from the config space (in PCI 739a3c5bd6dSspeer * case), then the following code need to be use different offset 74044961713Sgirish * computation macro. 74144961713Sgirish */ 74244961713Sgirish reg_offset = reg_base + DMC_OFFSET(channel); 74344961713Sgirish 74444961713Sgirish NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_get64")); 74544961713Sgirish 74644961713Sgirish return (NXGE_PIO_READ64(handle, reg_addrp, reg_offset)); 74744961713Sgirish } 74844961713Sgirish 749a3c5bd6dSspeer /* ARGSUSED */ 75044961713Sgirish void 75144961713Sgirish nxge_get32(p_nxge_t nxgep, p_mblk_t mp) 75244961713Sgirish { 753a3c5bd6dSspeer nxge_os_acc_handle_t nxge_regh; 75444961713Sgirish 75544961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_get32")); 75644961713Sgirish nxge_regh = nxgep->dev_regs->nxge_regh; 75744961713Sgirish 75844961713Sgirish *(uint32_t *)mp->b_rptr = NXGE_PIO_READ32(nxge_regh, 759a3c5bd6dSspeer nxgep->dev_regs->nxge_regp, *(uint32_t *)mp->b_rptr); 76044961713Sgirish 76144961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "value = 0x%08X", 762a3c5bd6dSspeer *(uint32_t *)mp->b_rptr)); 76344961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_get32")); 76444961713Sgirish } 76544961713Sgirish 766a3c5bd6dSspeer /* ARGSUSED */ 76744961713Sgirish void 76844961713Sgirish nxge_put32(p_nxge_t nxgep, p_mblk_t mp) 76944961713Sgirish { 77044961713Sgirish nxge_os_acc_handle_t nxge_regh; 77144961713Sgirish uint32_t *buf; 77244961713Sgirish uint8_t *reg; 77344961713Sgirish 77444961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_put32")); 77544961713Sgirish nxge_regh = nxgep->dev_regs->nxge_regh; 77644961713Sgirish 77744961713Sgirish buf = (uint32_t *)mp->b_rptr; 77844961713Sgirish reg = (uint8_t *)(nxgep->dev_regs->nxge_regp) + buf[0]; 77944961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, 780a3c5bd6dSspeer "reg = 0x%016llX index = 0x%08X value = 0x%08X", 781a3c5bd6dSspeer reg, buf[0], buf[1])); 78244961713Sgirish NXGE_PIO_WRITE32(nxge_regh, (uint32_t *)reg, 0, buf[1]); 78344961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_put32")); 78444961713Sgirish } 78544961713Sgirish 78644961713Sgirish /*ARGSUSED*/ 78744961713Sgirish boolean_t 78844961713Sgirish nxge_set_lb(p_nxge_t nxgep, queue_t *wq, p_mblk_t mp) 78944961713Sgirish { 790a3c5bd6dSspeer boolean_t status = B_TRUE; 791a3c5bd6dSspeer uint32_t lb_mode; 792a3c5bd6dSspeer lb_property_t *lb_info; 79344961713Sgirish 79444961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_set_lb")); 79544961713Sgirish lb_mode = nxgep->statsp->port_stats.lb_mode; 79644961713Sgirish if (lb_mode == *(uint32_t *)mp->b_rptr) { 79744961713Sgirish cmn_err(CE_NOTE, 79844961713Sgirish "!nxge%d: Loopback mode already set (lb_mode %d).\n", 79944961713Sgirish nxgep->instance, lb_mode); 80044961713Sgirish status = B_FALSE; 80144961713Sgirish goto nxge_set_lb_exit; 80244961713Sgirish } 80344961713Sgirish lb_mode = *(uint32_t *)mp->b_rptr; 80444961713Sgirish lb_info = NULL; 80544961713Sgirish if (lb_mode == lb_normal.value) 80644961713Sgirish lb_info = &lb_normal; 80744961713Sgirish else if ((lb_mode == lb_external10g.value) && 808a3c5bd6dSspeer (nxgep->statsp->mac_stats.cap_10gfdx)) 80944961713Sgirish lb_info = &lb_external10g; 81044961713Sgirish else if ((lb_mode == lb_external1000.value) && 811a3c5bd6dSspeer (nxgep->statsp->mac_stats.cap_1000fdx)) 81244961713Sgirish lb_info = &lb_external1000; 81344961713Sgirish else if ((lb_mode == lb_external100.value) && 814a3c5bd6dSspeer (nxgep->statsp->mac_stats.cap_100fdx)) 81544961713Sgirish lb_info = &lb_external100; 81644961713Sgirish else if ((lb_mode == lb_external10.value) && 817a3c5bd6dSspeer (nxgep->statsp->mac_stats.cap_10fdx)) 81844961713Sgirish lb_info = &lb_external10; 81944961713Sgirish else if ((lb_mode == lb_phy10g.value) && 82044961713Sgirish ((nxgep->mac.portmode == PORT_10G_COPPER) || 82144961713Sgirish (nxgep->mac.portmode == PORT_10G_FIBER))) 82244961713Sgirish lb_info = &lb_phy10g; 82344961713Sgirish else if ((lb_mode == lb_phy1000.value) && 824a3c5bd6dSspeer (nxgep->mac.portmode == PORT_1G_COPPER)) 82544961713Sgirish lb_info = &lb_phy1000; 82644961713Sgirish else if ((lb_mode == lb_phy.value) && 827a3c5bd6dSspeer (nxgep->mac.portmode == PORT_1G_COPPER)) 82844961713Sgirish lb_info = &lb_phy; 82944961713Sgirish else if ((lb_mode == lb_serdes10g.value) && 8302e59129aSraghus ((nxgep->mac.portmode == PORT_10G_FIBER) || 8312e59129aSraghus (nxgep->mac.portmode == PORT_10G_COPPER) || 8322e59129aSraghus (nxgep->mac.portmode == PORT_10G_SERDES))) 83344961713Sgirish lb_info = &lb_serdes10g; 83444961713Sgirish else if ((lb_mode == lb_serdes1000.value) && 8352e59129aSraghus (nxgep->mac.portmode == PORT_1G_FIBER || 8362e59129aSraghus (nxgep->mac.portmode == PORT_1G_SERDES))) 83744961713Sgirish lb_info = &lb_serdes1000; 83844961713Sgirish else if (lb_mode == lb_mac10g.value) 83944961713Sgirish lb_info = &lb_mac10g; 84044961713Sgirish else if (lb_mode == lb_mac1000.value) 84144961713Sgirish lb_info = &lb_mac1000; 84244961713Sgirish else if (lb_mode == lb_mac.value) 84344961713Sgirish lb_info = &lb_mac; 84444961713Sgirish else { 84544961713Sgirish cmn_err(CE_NOTE, 84644961713Sgirish "!nxge%d: Loopback mode not supported(mode %d).\n", 84744961713Sgirish nxgep->instance, lb_mode); 84844961713Sgirish status = B_FALSE; 84944961713Sgirish goto nxge_set_lb_exit; 85044961713Sgirish } 85144961713Sgirish 85244961713Sgirish if (lb_mode == nxge_lb_normal) { 85344961713Sgirish if (nxge_lb_dbg) { 85444961713Sgirish cmn_err(CE_NOTE, 85544961713Sgirish "!nxge%d: Returning to normal operation", 85644961713Sgirish nxgep->instance); 85744961713Sgirish } 85844961713Sgirish nxge_set_lb_normal(nxgep); 85944961713Sgirish goto nxge_set_lb_exit; 86044961713Sgirish } 86144961713Sgirish nxgep->statsp->port_stats.lb_mode = lb_mode; 86244961713Sgirish 86344961713Sgirish if (nxge_lb_dbg) 86444961713Sgirish cmn_err(CE_NOTE, 86544961713Sgirish "!nxge%d: Adapter now in %s loopback mode", 86644961713Sgirish nxgep->instance, lb_info->key); 86744961713Sgirish nxgep->param_arr[param_autoneg].value = 0; 86844961713Sgirish nxgep->param_arr[param_anar_10gfdx].value = 86944961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10g) || 87044961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac10g) || 87144961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy10g) || 87244961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes10g); 87344961713Sgirish nxgep->param_arr[param_anar_10ghdx].value = 0; 87444961713Sgirish nxgep->param_arr[param_anar_1000fdx].value = 87544961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext1000) || 87644961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac1000) || 87744961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy1000) || 87844961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes1000); 87944961713Sgirish nxgep->param_arr[param_anar_1000hdx].value = 0; 88044961713Sgirish nxgep->param_arr[param_anar_100fdx].value = 88144961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy) || 88244961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac) || 88344961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext100); 88444961713Sgirish nxgep->param_arr[param_anar_100hdx].value = 0; 88544961713Sgirish nxgep->param_arr[param_anar_10fdx].value = 88644961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac) || 88744961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10); 88844961713Sgirish if (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext1000) { 88944961713Sgirish nxgep->param_arr[param_master_cfg_enable].value = 1; 89044961713Sgirish nxgep->param_arr[param_master_cfg_value].value = 1; 89144961713Sgirish } 89244961713Sgirish if ((nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10g) || 89344961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext1000) || 89444961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext100) || 89544961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10) || 89644961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy10g) || 89744961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy1000) || 89844961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy)) { 89944961713Sgirish 90044961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 9012e59129aSraghus (void) nxge_xcvr_find(nxgep); 90244961713Sgirish (void) nxge_link_init(nxgep); 90344961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 90444961713Sgirish } 90544961713Sgirish if (lb_info->lb_type == internal) { 90644961713Sgirish if ((nxgep->statsp->port_stats.lb_mode == nxge_lb_mac10g) || 907a3c5bd6dSspeer (nxgep->statsp->port_stats.lb_mode == 908a3c5bd6dSspeer nxge_lb_phy10g) || 909a3c5bd6dSspeer (nxgep->statsp->port_stats.lb_mode == 910a3c5bd6dSspeer nxge_lb_serdes10g)) { 91144961713Sgirish nxgep->statsp->mac_stats.link_speed = 10000; 912a3c5bd6dSspeer } else if ((nxgep->statsp->port_stats.lb_mode 913a3c5bd6dSspeer == nxge_lb_mac1000) || 914a3c5bd6dSspeer (nxgep->statsp->port_stats.lb_mode == 915a3c5bd6dSspeer nxge_lb_phy1000) || 916a3c5bd6dSspeer (nxgep->statsp->port_stats.lb_mode == 917a3c5bd6dSspeer nxge_lb_serdes1000)) { 91844961713Sgirish nxgep->statsp->mac_stats.link_speed = 1000; 91944961713Sgirish } else { 92044961713Sgirish nxgep->statsp->mac_stats.link_speed = 100; 92144961713Sgirish } 92244961713Sgirish nxgep->statsp->mac_stats.link_duplex = 2; 92344961713Sgirish nxgep->statsp->mac_stats.link_up = 1; 92444961713Sgirish } 92544961713Sgirish nxge_global_reset(nxgep); 92644961713Sgirish 92744961713Sgirish nxge_set_lb_exit: 92844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 929a3c5bd6dSspeer "<== nxge_set_lb status = 0x%08x", status)); 93044961713Sgirish return (status); 93144961713Sgirish } 93244961713Sgirish 933a3c5bd6dSspeer /* ARGSUSED */ 93444961713Sgirish void 93544961713Sgirish nxge_set_lb_normal(p_nxge_t nxgep) 93644961713Sgirish { 93744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_set_lb_normal")); 93844961713Sgirish nxgep->statsp->port_stats.lb_mode = nxge_lb_normal; 93944961713Sgirish nxgep->param_arr[param_autoneg].value = 94044961713Sgirish nxgep->param_arr[param_autoneg].old_value; 94144961713Sgirish nxgep->param_arr[param_anar_1000fdx].value = 94244961713Sgirish nxgep->param_arr[param_anar_1000fdx].old_value; 94344961713Sgirish nxgep->param_arr[param_anar_1000hdx].value = 94444961713Sgirish nxgep->param_arr[param_anar_1000hdx].old_value; 94544961713Sgirish nxgep->param_arr[param_anar_100fdx].value = 94644961713Sgirish nxgep->param_arr[param_anar_100fdx].old_value; 94744961713Sgirish nxgep->param_arr[param_anar_100hdx].value = 94844961713Sgirish nxgep->param_arr[param_anar_100hdx].old_value; 94944961713Sgirish nxgep->param_arr[param_anar_10fdx].value = 95044961713Sgirish nxgep->param_arr[param_anar_10fdx].old_value; 95144961713Sgirish nxgep->param_arr[param_master_cfg_enable].value = 95244961713Sgirish nxgep->param_arr[param_master_cfg_enable].old_value; 95344961713Sgirish nxgep->param_arr[param_master_cfg_value].value = 95444961713Sgirish nxgep->param_arr[param_master_cfg_value].old_value; 95544961713Sgirish 95644961713Sgirish nxge_global_reset(nxgep); 95744961713Sgirish 95844961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 9592e59129aSraghus (void) nxge_xcvr_find(nxgep); 96044961713Sgirish (void) nxge_link_init(nxgep); 96144961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 96244961713Sgirish 96344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_set_lb_normal")); 96444961713Sgirish } 96544961713Sgirish 966a3c5bd6dSspeer /* ARGSUSED */ 96744961713Sgirish void 96844961713Sgirish nxge_get_mii(p_nxge_t nxgep, p_mblk_t mp) 96944961713Sgirish { 97044961713Sgirish uint16_t reg; 97144961713Sgirish 97244961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_get_mii")); 97344961713Sgirish 97444961713Sgirish reg = *(uint16_t *)mp->b_rptr; 97544961713Sgirish (void) nxge_mii_read(nxgep, nxgep->statsp->mac_stats.xcvr_portn, reg, 976a3c5bd6dSspeer (uint16_t *)mp->b_rptr); 97744961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "reg = 0x%08X value = 0x%04X", 978a3c5bd6dSspeer reg, *(uint16_t *)mp->b_rptr)); 97944961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_get_mii")); 98044961713Sgirish } 98144961713Sgirish 982a3c5bd6dSspeer /* ARGSUSED */ 98344961713Sgirish void 98444961713Sgirish nxge_put_mii(p_nxge_t nxgep, p_mblk_t mp) 98544961713Sgirish { 98644961713Sgirish uint16_t *buf; 98744961713Sgirish uint8_t reg; 98844961713Sgirish 98944961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_put_mii")); 99044961713Sgirish buf = (uint16_t *)mp->b_rptr; 99144961713Sgirish reg = (uint8_t)buf[0]; 99244961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, 993a3c5bd6dSspeer "reg = 0x%08X index = 0x%08X value = 0x%08X", 994a3c5bd6dSspeer reg, buf[0], buf[1])); 99544961713Sgirish (void) nxge_mii_write(nxgep, nxgep->statsp->mac_stats.xcvr_portn, 99644961713Sgirish reg, buf[1]); 99744961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_put_mii")); 99844961713Sgirish } 99944961713Sgirish 1000a3c5bd6dSspeer /* ARGSUSED */ 100144961713Sgirish void 100244961713Sgirish nxge_check_hw_state(p_nxge_t nxgep) 100344961713Sgirish { 1004a3c5bd6dSspeer p_nxge_ldgv_t ldgvp; 1005a3c5bd6dSspeer p_nxge_ldv_t t_ldvp; 100644961713Sgirish 100744961713Sgirish NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "==> nxge_check_hw_state")); 100844961713Sgirish 100914ea4bb7Ssd MUTEX_ENTER(nxgep->genlock); 101014ea4bb7Ssd nxgep->nxge_timerid = 0; 101114ea4bb7Ssd if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 101214ea4bb7Ssd goto nxge_check_hw_state_exit; 101314ea4bb7Ssd } 101444961713Sgirish nxge_check_tx_hang(nxgep); 101544961713Sgirish 101644961713Sgirish ldgvp = nxgep->ldgvp; 101744961713Sgirish if (ldgvp == NULL || (ldgvp->ldvp_syserr == NULL)) { 101844961713Sgirish NXGE_ERROR_MSG((nxgep, SYSERR_CTL, "<== nxge_check_hw_state: " 1019a3c5bd6dSspeer "NULL ldgvp (interrupt not ready).")); 102014ea4bb7Ssd goto nxge_check_hw_state_exit; 102144961713Sgirish } 102244961713Sgirish t_ldvp = ldgvp->ldvp_syserr; 102344961713Sgirish if (!t_ldvp->use_timer) { 102444961713Sgirish NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "<== nxge_check_hw_state: " 1025a3c5bd6dSspeer "ldgvp $%p t_ldvp $%p use_timer flag %d", 1026a3c5bd6dSspeer ldgvp, t_ldvp, t_ldvp->use_timer)); 102714ea4bb7Ssd goto nxge_check_hw_state_exit; 102814ea4bb7Ssd } 102914ea4bb7Ssd if (fm_check_acc_handle(nxgep->dev_regs->nxge_regh) != DDI_FM_OK) { 103014ea4bb7Ssd NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 103114ea4bb7Ssd "port%d Bad register acc handle", nxgep->mac.portnum)); 103244961713Sgirish } 1033a3c5bd6dSspeer (void) nxge_syserr_intr((void *) t_ldvp, (void *) nxgep); 103444961713Sgirish 103544961713Sgirish nxgep->nxge_timerid = nxge_start_timer(nxgep, nxge_check_hw_state, 103644961713Sgirish NXGE_CHECK_TIMER); 103744961713Sgirish 103814ea4bb7Ssd nxge_check_hw_state_exit: 103914ea4bb7Ssd MUTEX_EXIT(nxgep->genlock); 104044961713Sgirish NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "<== nxge_check_hw_state")); 104144961713Sgirish } 104244961713Sgirish 104344961713Sgirish /*ARGSUSED*/ 104444961713Sgirish static void 1045a3c5bd6dSspeer nxge_rtrace_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, 1046a3c5bd6dSspeer struct iocblk *iocp) 104744961713Sgirish { 1048a3c5bd6dSspeer ssize_t size; 1049a3c5bd6dSspeer rtrace_t *rtp; 1050a3c5bd6dSspeer mblk_t *nmp; 1051a3c5bd6dSspeer uint32_t i, j; 1052a3c5bd6dSspeer uint32_t start_blk; 1053a3c5bd6dSspeer uint32_t base_entry; 1054a3c5bd6dSspeer uint32_t num_entries; 105544961713Sgirish 105644961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_rtrace_ioctl")); 105744961713Sgirish 105844961713Sgirish size = 1024; 105944961713Sgirish if (mp->b_cont == NULL || MBLKL(mp->b_cont) < size) { 106044961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, 1061a3c5bd6dSspeer "malformed M_IOCTL MBLKL = %d size = %d", 1062a3c5bd6dSspeer MBLKL(mp->b_cont), size)); 106344961713Sgirish miocnak(wq, mp, 0, EINVAL); 106444961713Sgirish return; 106544961713Sgirish } 106644961713Sgirish nmp = mp->b_cont; 106744961713Sgirish rtp = (rtrace_t *)nmp->b_rptr; 106844961713Sgirish start_blk = rtp->next_idx; 106944961713Sgirish num_entries = rtp->last_idx; 107044961713Sgirish base_entry = start_blk * MAX_RTRACE_IOC_ENTRIES; 107144961713Sgirish 107244961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "start_blk = %d\n", start_blk)); 107344961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "num_entries = %d\n", num_entries)); 107444961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "base_entry = %d\n", base_entry)); 107544961713Sgirish 107644961713Sgirish rtp->next_idx = npi_rtracebuf.next_idx; 107744961713Sgirish rtp->last_idx = npi_rtracebuf.last_idx; 107844961713Sgirish rtp->wrapped = npi_rtracebuf.wrapped; 107944961713Sgirish for (i = 0, j = base_entry; i < num_entries; i++, j++) { 108044961713Sgirish rtp->buf[i].ctl_addr = npi_rtracebuf.buf[j].ctl_addr; 108144961713Sgirish rtp->buf[i].val_l32 = npi_rtracebuf.buf[j].val_l32; 108244961713Sgirish rtp->buf[i].val_h32 = npi_rtracebuf.buf[j].val_h32; 108344961713Sgirish } 108444961713Sgirish 108544961713Sgirish nmp->b_wptr = nmp->b_rptr + size; 108644961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "<== nxge_rtrace_ioctl")); 108744961713Sgirish miocack(wq, mp, (int)size, 0); 108844961713Sgirish } 1089