xref: /illumos-gate/usr/src/uts/common/io/nxge/nxge_hw.c (revision 4df55fde)
144961713Sgirish /*
244961713Sgirish  * CDDL HEADER START
344961713Sgirish  *
444961713Sgirish  * The contents of this file are subject to the terms of the
544961713Sgirish  * Common Development and Distribution License (the "License").
644961713Sgirish  * You may not use this file except in compliance with the License.
744961713Sgirish  *
844961713Sgirish  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
944961713Sgirish  * or http://www.opensolaris.org/os/licensing.
1044961713Sgirish  * See the License for the specific language governing permissions
1144961713Sgirish  * and limitations under the License.
1244961713Sgirish  *
1344961713Sgirish  * When distributing Covered Code, include this CDDL HEADER in each
1444961713Sgirish  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1544961713Sgirish  * If applicable, add the following below this CDDL HEADER, with the
1644961713Sgirish  * fields enclosed by brackets "[]" replaced with your own identifying
1744961713Sgirish  * information: Portions Copyright [yyyy] [name of copyright owner]
1844961713Sgirish  *
1944961713Sgirish  * CDDL HEADER END
2044961713Sgirish  */
2148056c53SMichael Speer 
2244961713Sgirish /*
2348056c53SMichael Speer  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
2444961713Sgirish  * Use is subject to license terms.
2544961713Sgirish  */
2644961713Sgirish 
27a3c5bd6dSspeer #include <sys/nxge/nxge_impl.h>
2844961713Sgirish 
2944961713Sgirish /*
3044961713Sgirish  * Tunable Receive Completion Ring Configuration B parameters.
3144961713Sgirish  */
32a3c5bd6dSspeer uint16_t nxge_rx_pkt_thres;	/* 16 bits */
33a3c5bd6dSspeer uint8_t nxge_rx_pkt_timeout;	/* 6 bits based on DMA clock divider */
34a3c5bd6dSspeer 
35a3c5bd6dSspeer lb_property_t lb_normal = {normal, "normal", nxge_lb_normal};
36a3c5bd6dSspeer lb_property_t lb_external10g = {external, "external10g", nxge_lb_ext10g};
37a3c5bd6dSspeer lb_property_t lb_external1000 = {external, "external1000", nxge_lb_ext1000};
38a3c5bd6dSspeer lb_property_t lb_external100 = {external, "external100", nxge_lb_ext100};
39a3c5bd6dSspeer lb_property_t lb_external10 = {external, "external10", nxge_lb_ext10};
40a3c5bd6dSspeer lb_property_t lb_phy10g = {internal, "phy10g", nxge_lb_phy10g};
41a3c5bd6dSspeer lb_property_t lb_phy1000 = {internal, "phy1000", nxge_lb_phy1000};
42a3c5bd6dSspeer lb_property_t lb_phy = {internal, "phy", nxge_lb_phy};
43a3c5bd6dSspeer lb_property_t lb_serdes10g = {internal, "serdes10g", nxge_lb_serdes10g};
44a3c5bd6dSspeer lb_property_t lb_serdes1000 = {internal, "serdes", nxge_lb_serdes1000};
45a3c5bd6dSspeer lb_property_t lb_mac10g = {internal, "mac10g", nxge_lb_mac10g};
46a3c5bd6dSspeer lb_property_t lb_mac1000 = {internal, "mac1000", nxge_lb_mac1000};
47a3c5bd6dSspeer lb_property_t lb_mac = {internal, "mac10/100", nxge_lb_mac};
4844961713Sgirish 
4944961713Sgirish uint32_t nxge_lb_dbg = 1;
5044961713Sgirish void nxge_get_mii(p_nxge_t nxgep, p_mblk_t mp);
5144961713Sgirish void nxge_put_mii(p_nxge_t nxgep, p_mblk_t mp);
52ee5416c9Syc static nxge_status_t nxge_check_xaui_xfp(p_nxge_t nxgep);
5344961713Sgirish 
5444961713Sgirish extern uint32_t nxge_rx_mode;
55a3c5bd6dSspeer extern uint32_t nxge_jumbo_mtu;
56*4df55fdeSJanie Lu extern uint16_t	nxge_rdc_buf_offset;
5744961713Sgirish 
58a3c5bd6dSspeer static void
59a3c5bd6dSspeer nxge_rtrace_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *);
6044961713Sgirish 
61a3c5bd6dSspeer /* ARGSUSED */
62321febdeSsbehera nxge_status_t
6344961713Sgirish nxge_global_reset(p_nxge_t nxgep)
6444961713Sgirish {
65321febdeSsbehera 	nxge_status_t	status = NXGE_OK;
66321febdeSsbehera 
6744961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_global_reset"));
6844961713Sgirish 
69321febdeSsbehera 	if ((status = nxge_link_monitor(nxgep, LINK_MONITOR_STOP)) != NXGE_OK)
70321febdeSsbehera 		return (status);
7144961713Sgirish 	(void) nxge_intr_hw_disable(nxgep);
7244961713Sgirish 
7344961713Sgirish 	if ((nxgep->suspended) ||
7452ccf843Smisaki 	    ((nxgep->statsp->port_stats.lb_mode ==
7552ccf843Smisaki 	    nxge_lb_phy1000) ||
7652ccf843Smisaki 	    (nxgep->statsp->port_stats.lb_mode ==
7752ccf843Smisaki 	    nxge_lb_phy10g) ||
7852ccf843Smisaki 	    (nxgep->statsp->port_stats.lb_mode ==
7952ccf843Smisaki 	    nxge_lb_serdes1000) ||
8052ccf843Smisaki 	    (nxgep->statsp->port_stats.lb_mode ==
8152ccf843Smisaki 	    nxge_lb_serdes10g))) {
82321febdeSsbehera 		if ((status = nxge_link_init(nxgep)) != NXGE_OK)
83321febdeSsbehera 			return (status);
8444961713Sgirish 	}
85321febdeSsbehera 
86321febdeSsbehera 	if ((status = nxge_link_monitor(nxgep, LINK_MONITOR_START)) != NXGE_OK)
87321febdeSsbehera 		return (status);
88321febdeSsbehera 	if ((status = nxge_mac_init(nxgep)) != NXGE_OK)
89321febdeSsbehera 		return (status);
9044961713Sgirish 	(void) nxge_intr_hw_enable(nxgep);
9144961713Sgirish 
9244961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_global_reset"));
93321febdeSsbehera 	return (status);
9444961713Sgirish }
9544961713Sgirish 
96a3c5bd6dSspeer /* ARGSUSED */
9744961713Sgirish void
9844961713Sgirish nxge_hw_id_init(p_nxge_t nxgep)
9944961713Sgirish {
10044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_id_init"));
10148056c53SMichael Speer 
10244961713Sgirish 	/*
10344961713Sgirish 	 * Set up initial hardware parameters required such as mac mtu size.
10444961713Sgirish 	 */
10544961713Sgirish 	nxgep->mac.is_jumbo = B_FALSE;
10648056c53SMichael Speer 
1071bd6825cSml 	/*
1081bd6825cSml 	 * Set the maxframe size to 1522 (1518 + 4) to account for
1091bd6825cSml 	 * VLAN tagged packets.
1101bd6825cSml 	 */
11148056c53SMichael Speer 	nxgep->mac.minframesize = NXGE_MIN_MAC_FRAMESIZE;	/* 64 */
11248056c53SMichael Speer 	nxgep->mac.maxframesize = NXGE_MAX_MAC_FRAMESIZE;	/* 1522 */
11344961713Sgirish 
11448056c53SMichael Speer 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_id_init: maxframesize %d",
11548056c53SMichael Speer 	    nxgep->mac.maxframesize));
11644961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_id_init"));
11744961713Sgirish }
11844961713Sgirish 
119a3c5bd6dSspeer /* ARGSUSED */
12044961713Sgirish void
12144961713Sgirish nxge_hw_init_niu_common(p_nxge_t nxgep)
12244961713Sgirish {
123a3c5bd6dSspeer 	p_nxge_hw_list_t hw_p;
12444961713Sgirish 
12544961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_init_niu_common"));
12644961713Sgirish 
12744961713Sgirish 	if ((hw_p = nxgep->nxge_hw_p) == NULL) {
12844961713Sgirish 		return;
12944961713Sgirish 	}
13044961713Sgirish 	MUTEX_ENTER(&hw_p->nxge_cfg_lock);
13144961713Sgirish 	if (hw_p->flags & COMMON_INIT_DONE) {
13244961713Sgirish 		NXGE_DEBUG_MSG((nxgep, MOD_CTL,
13352ccf843Smisaki 		    "nxge_hw_init_niu_common"
13452ccf843Smisaki 		    " already done for dip $%p function %d exiting",
13552ccf843Smisaki 		    hw_p->parent_devp, nxgep->function_num));
13644961713Sgirish 		MUTEX_EXIT(&hw_p->nxge_cfg_lock);
13744961713Sgirish 		return;
13844961713Sgirish 	}
13944961713Sgirish 
14044961713Sgirish 	hw_p->flags = COMMON_INIT_START;
14144961713Sgirish 	NXGE_DEBUG_MSG((nxgep, MOD_CTL, "nxge_hw_init_niu_common"
14252ccf843Smisaki 	    " Started for device id %x with function %d",
14352ccf843Smisaki 	    hw_p->parent_devp, nxgep->function_num));
144a3c5bd6dSspeer 
145a3c5bd6dSspeer 	/* per neptune common block init */
146a3c5bd6dSspeer 	(void) nxge_fflp_hw_reset(nxgep);
14744961713Sgirish 
148*4df55fdeSJanie Lu 	if (nxgep->niu_hw_type != NIU_HW_TYPE_RF) {
149*4df55fdeSJanie Lu 		switch (nxge_rdc_buf_offset) {
150*4df55fdeSJanie Lu 		case SW_OFFSET_NO_OFFSET:
151*4df55fdeSJanie Lu 		case SW_OFFSET_64:
152*4df55fdeSJanie Lu 		case SW_OFFSET_128:
153*4df55fdeSJanie Lu 			break;
154*4df55fdeSJanie Lu 		default:
155*4df55fdeSJanie Lu 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
156*4df55fdeSJanie Lu 			    "nxge_hw_init_niu_common: Unsupported RDC buffer"
157*4df55fdeSJanie Lu 			    " offset code %d, setting to %d",
158*4df55fdeSJanie Lu 			    nxge_rdc_buf_offset, SW_OFFSET_NO_OFFSET));
159*4df55fdeSJanie Lu 			nxge_rdc_buf_offset = SW_OFFSET_NO_OFFSET;
160*4df55fdeSJanie Lu 			break;
161*4df55fdeSJanie Lu 		}
162*4df55fdeSJanie Lu 	} else {
163*4df55fdeSJanie Lu 		switch (nxge_rdc_buf_offset) {
164*4df55fdeSJanie Lu 		case SW_OFFSET_NO_OFFSET:
165*4df55fdeSJanie Lu 		case SW_OFFSET_64:
166*4df55fdeSJanie Lu 		case SW_OFFSET_128:
167*4df55fdeSJanie Lu 		case SW_OFFSET_192:
168*4df55fdeSJanie Lu 		case SW_OFFSET_256:
169*4df55fdeSJanie Lu 		case SW_OFFSET_320:
170*4df55fdeSJanie Lu 		case SW_OFFSET_384:
171*4df55fdeSJanie Lu 		case SW_OFFSET_448:
172*4df55fdeSJanie Lu 			break;
173*4df55fdeSJanie Lu 		default:
174*4df55fdeSJanie Lu 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
175*4df55fdeSJanie Lu 			    "nxge_hw_init_niu_common: Unsupported RDC buffer"
176*4df55fdeSJanie Lu 			    " offset code %d, setting to %d",
177*4df55fdeSJanie Lu 			    nxge_rdc_buf_offset, SW_OFFSET_NO_OFFSET));
178*4df55fdeSJanie Lu 			nxge_rdc_buf_offset = SW_OFFSET_NO_OFFSET;
179*4df55fdeSJanie Lu 			break;
180*4df55fdeSJanie Lu 		}
181*4df55fdeSJanie Lu 	}
182*4df55fdeSJanie Lu 
18344961713Sgirish 	hw_p->flags = COMMON_INIT_DONE;
18444961713Sgirish 	MUTEX_EXIT(&hw_p->nxge_cfg_lock);
18544961713Sgirish 
18644961713Sgirish 	NXGE_DEBUG_MSG((nxgep, MOD_CTL, "nxge_hw_init_niu_common"
18752ccf843Smisaki 	    " Done for device id %x with function %d",
18852ccf843Smisaki 	    hw_p->parent_devp, nxgep->function_num));
18944961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_init_niu_common"));
19044961713Sgirish }
19144961713Sgirish 
192a3c5bd6dSspeer /* ARGSUSED */
19344961713Sgirish uint_t
19444961713Sgirish nxge_intr(void *arg1, void *arg2)
19544961713Sgirish {
196a3c5bd6dSspeer 	p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1;
197a3c5bd6dSspeer 	p_nxge_t nxgep = (p_nxge_t)arg2;
198a3c5bd6dSspeer 	uint_t serviced = DDI_INTR_UNCLAIMED;
199a3c5bd6dSspeer 	uint8_t ldv;
200a3c5bd6dSspeer 	npi_handle_t handle;
201a3c5bd6dSspeer 	p_nxge_ldgv_t ldgvp;
202a3c5bd6dSspeer 	p_nxge_ldg_t ldgp, t_ldgp;
203a3c5bd6dSspeer 	p_nxge_ldv_t t_ldvp;
204a3c5bd6dSspeer 	uint64_t vector0 = 0, vector1 = 0, vector2 = 0;
205a3c5bd6dSspeer 	int i, j, nldvs, nintrs = 1;
206a3c5bd6dSspeer 	npi_status_t rs = NPI_SUCCESS;
20744961713Sgirish 
20844961713Sgirish 	/* DDI interface returns second arg as NULL (n2 niumx driver) !!! */
209a3c5bd6dSspeer 	if (arg2 == NULL || (void *) ldvp->nxgep != arg2) {
21044961713Sgirish 		nxgep = ldvp->nxgep;
21144961713Sgirish 	}
21244961713Sgirish 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr"));
21344961713Sgirish 
21444961713Sgirish 	if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) {
21544961713Sgirish 		NXGE_ERROR_MSG((nxgep, INT_CTL,
21652ccf843Smisaki 		    "<== nxge_intr: not initialized 0x%x", serviced));
21744961713Sgirish 		return (serviced);
21844961713Sgirish 	}
21944961713Sgirish 
22044961713Sgirish 	ldgvp = nxgep->ldgvp;
221a3c5bd6dSspeer 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: ldgvp $%p", ldgvp));
22244961713Sgirish 	if (ldvp == NULL && ldgvp) {
22344961713Sgirish 		t_ldvp = ldvp = ldgvp->ldvp;
22444961713Sgirish 	}
22544961713Sgirish 	if (ldvp) {
22644961713Sgirish 		ldgp = t_ldgp = ldvp->ldgp;
22744961713Sgirish 	}
22844961713Sgirish 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: "
22952ccf843Smisaki 	    "ldgvp $%p ldvp $%p ldgp $%p", ldgvp, ldvp, ldgp));
23044961713Sgirish 	if (ldgvp == NULL || ldvp == NULL || ldgp == NULL) {
23144961713Sgirish 		NXGE_ERROR_MSG((nxgep, INT_CTL, "==> nxge_intr: "
23252ccf843Smisaki 		    "ldgvp $%p ldvp $%p ldgp $%p", ldgvp, ldvp, ldgp));
23344961713Sgirish 		NXGE_ERROR_MSG((nxgep, INT_CTL, "<== nxge_intr: not ready"));
23444961713Sgirish 		return (DDI_INTR_UNCLAIMED);
23544961713Sgirish 	}
23644961713Sgirish 	/*
237a3c5bd6dSspeer 	 * This interrupt handler will have to go through all the logical
238a3c5bd6dSspeer 	 * devices to find out which logical device interrupts us and then call
23944961713Sgirish 	 * its handler to process the events.
24044961713Sgirish 	 */
24144961713Sgirish 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
24244961713Sgirish 	t_ldgp = ldgp;
24344961713Sgirish 	t_ldvp = ldgp->ldvp;
24444961713Sgirish 
24544961713Sgirish 	nldvs = ldgp->nldvs;
24644961713Sgirish 
24744961713Sgirish 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: #ldvs %d #intrs %d",
24852ccf843Smisaki 	    nldvs, ldgvp->ldg_intrs));
24944961713Sgirish 
25044961713Sgirish 	serviced = DDI_INTR_CLAIMED;
25144961713Sgirish 	for (i = 0; i < nintrs; i++, t_ldgp++) {
25244961713Sgirish 		NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr(%d): #ldvs %d "
25352ccf843Smisaki 		    " #intrs %d", i, nldvs, nintrs));
25444961713Sgirish 		/* Get this group's flag bits.  */
25544961713Sgirish 		rs = npi_ldsv_ldfs_get(handle, t_ldgp->ldg,
25652ccf843Smisaki 		    &vector0, &vector1, &vector2);
25744961713Sgirish 		if (rs) {
25844961713Sgirish 			continue;
25944961713Sgirish 		}
26044961713Sgirish 		if (!vector0 && !vector1 && !vector2) {
26144961713Sgirish 			NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: "
26252ccf843Smisaki 			    "no interrupts on group %d", t_ldgp->ldg));
26344961713Sgirish 			continue;
26444961713Sgirish 		}
26544961713Sgirish 		NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: "
26652ccf843Smisaki 		    "vector0 0x%llx vector1 0x%llx vector2 0x%llx",
26752ccf843Smisaki 		    vector0, vector1, vector2));
26844961713Sgirish 		nldvs = t_ldgp->nldvs;
26944961713Sgirish 		for (j = 0; j < nldvs; j++, t_ldvp++) {
27044961713Sgirish 			/*
27144961713Sgirish 			 * Call device's handler if flag bits are on.
27244961713Sgirish 			 */
27344961713Sgirish 			ldv = t_ldvp->ldv;
27444961713Sgirish 			if (((ldv < NXGE_MAC_LD_START) &&
27552ccf843Smisaki 			    (LDV_ON(ldv, vector0) |
27652ccf843Smisaki 			    (LDV_ON(ldv, vector1)))) ||
27752ccf843Smisaki 			    (ldv >= NXGE_MAC_LD_START &&
27852ccf843Smisaki 			    ((LDV2_ON_1(ldv, vector2)) ||
27952ccf843Smisaki 			    (LDV2_ON_2(ldv, vector2))))) {
28044961713Sgirish 				(void) (t_ldvp->ldv_intr_handler)(
28152ccf843Smisaki 				    (caddr_t)t_ldvp, arg2);
28244961713Sgirish 				NXGE_DEBUG_MSG((nxgep, INT_CTL,
28352ccf843Smisaki 				    "==> nxge_intr: "
28452ccf843Smisaki 				    "calling device %d #ldvs %d #intrs %d",
28552ccf843Smisaki 				    j, nldvs, nintrs));
28644961713Sgirish 			}
28744961713Sgirish 		}
28844961713Sgirish 	}
28944961713Sgirish 
29044961713Sgirish 	t_ldgp = ldgp;
29144961713Sgirish 	for (i = 0; i < nintrs; i++, t_ldgp++) {
29244961713Sgirish 		/* rearm group interrupts */
293da14cebeSEric Cheng 		NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: arm "
294da14cebeSEric Cheng 		    "group %d", t_ldgp->ldg));
295da14cebeSEric Cheng 		(void) npi_intr_ldg_mgmt_set(handle, t_ldgp->ldg,
296da14cebeSEric Cheng 		    t_ldgp->arm, t_ldgp->ldg_timer);
29744961713Sgirish 	}
29844961713Sgirish 
29944961713Sgirish 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr: serviced 0x%x",
30052ccf843Smisaki 	    serviced));
30144961713Sgirish 	return (serviced);
30244961713Sgirish }
30344961713Sgirish 
30400161856Syc 
30500161856Syc /*
30600161856Syc  * XFP Related Status Register Values Under 3 Different Conditions
30700161856Syc  *
30800161856Syc  * -------------+-------------------------+-------------------------
3090cad6a5fSyc  * 		|   Intel XFP and Avago   |	 Picolight XFP
31000161856Syc  * -------------+---------+---------------+---------+---------------
31100161856Syc  *		| STATUS0 | TX_ALARM_STAT | STATUS0 | TX_ALARM_STAT
31200161856Syc  * -------------+---------+---------------+---------+---------------
31300161856Syc  *	No XFP  | 0x639C  |      0x40     | 0x639C  |      0x40
31400161856Syc  * -------------+---------+---------------+---------+---------------
31500161856Syc  * XFP,linkdown | 0x43BC  |      0x40     | 0x639C  |      0x40
31600161856Syc  * -------------+---------+---------------+---------+---------------
31700161856Syc  * XFP,linkup   | 0x03FC  |      0x0      | 0x03FC  |      0x0
31800161856Syc  * -------------+---------+---------------+---------+---------------
31900161856Syc  * Note:
32000161856Syc  *      STATUS0         = BCM8704_USER_ANALOG_STATUS0_REG
32100161856Syc  *      TX_ALARM_STAT   = BCM8704_USER_TX_ALARM_STATUS_REG
32200161856Syc  */
323ee5416c9Syc /* ARGSUSED */
324ee5416c9Syc static nxge_status_t
325ee5416c9Syc nxge_check_xaui_xfp(p_nxge_t nxgep)
326ee5416c9Syc {
327ee5416c9Syc 	nxge_status_t	status = NXGE_OK;
328ee5416c9Syc 	uint8_t		phy_port_addr;
329ee5416c9Syc 	uint16_t	val;
330ee5416c9Syc 	uint16_t	val1;
331ee5416c9Syc 	uint8_t		portn;
332ee5416c9Syc 
333ee5416c9Syc 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_check_xaui_xfp"));
334ee5416c9Syc 
335ee5416c9Syc 	portn = nxgep->mac.portnum;
336ee5416c9Syc 	phy_port_addr = nxgep->statsp->mac_stats.xcvr_portn;
337ee5416c9Syc 
33800161856Syc 	/*
33900161856Syc 	 * Keep the val1 code even though it is not used. Could be
34000161856Syc 	 * used to differenciate the "No XFP" case and "XFP,linkdown"
34100161856Syc 	 * case when a Intel XFP is used.
34200161856Syc 	 */
343ee5416c9Syc 	if ((status = nxge_mdio_read(nxgep, phy_port_addr,
344ee5416c9Syc 	    BCM8704_USER_DEV3_ADDR,
345ee5416c9Syc 	    BCM8704_USER_ANALOG_STATUS0_REG, &val)) == NXGE_OK) {
346ee5416c9Syc 		status = nxge_mdio_read(nxgep, phy_port_addr,
347ee5416c9Syc 		    BCM8704_USER_DEV3_ADDR,
348ee5416c9Syc 		    BCM8704_USER_TX_ALARM_STATUS_REG, &val1);
349ee5416c9Syc 	}
35000161856Syc 
351ee5416c9Syc 	if (status != NXGE_OK) {
352ee5416c9Syc 		NXGE_FM_REPORT_ERROR(nxgep, portn, NULL,
353ee5416c9Syc 		    NXGE_FM_EREPORT_XAUI_ERR);
35400161856Syc 		if (DDI_FM_EREPORT_CAP(nxgep->fm_capabilities)) {
35500161856Syc 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
35600161856Syc 			    "XAUI is bad or absent on port<%d>\n", portn));
35700161856Syc 		}
3580cad6a5fSyc #ifdef NXGE_DEBUG
3590cad6a5fSyc 	/*
3600cad6a5fSyc 	 * As a workaround for CR6693529, do not execute this block of
3610cad6a5fSyc 	 * code for non-debug driver. When a Picolight XFP transceiver
3620cad6a5fSyc 	 * is used, register BCM8704_USER_ANALOG_STATUS0_REG returns
3630cad6a5fSyc 	 * the same 0x639C value in normal link down case, which causes
3640cad6a5fSyc 	 * false FMA messages and link reconnection problem.
3650cad6a5fSyc 	 */
366ee5416c9Syc 	} else if (nxgep->mac.portmode == PORT_10G_FIBER) {
367ee5416c9Syc 		/*
368f6485eecSyc 		 * 0x03FC = 0000 0011 1111 1100 (XFP is normal)
369f6485eecSyc 		 * 0x639C = 0110 0011 1001 1100 (XFP has problem)
370ee5416c9Syc 		 * bit14 = 1: PDM loss-of-light indicator
371ee5416c9Syc 		 * bit13 = 1: PDM Rx loss-of-signal
372ee5416c9Syc 		 * bit6  = 0: Light is NOT ok
373ee5416c9Syc 		 * bit5  = 0: PMD Rx signal is NOT ok
374ee5416c9Syc 		 */
375f6485eecSyc 		if (val == 0x639C) {
376ee5416c9Syc 			NXGE_FM_REPORT_ERROR(nxgep, portn, NULL,
377ee5416c9Syc 			    NXGE_FM_EREPORT_XFP_ERR);
37800161856Syc 			if (DDI_FM_EREPORT_CAP(nxgep->fm_capabilities)) {
37900161856Syc 				NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
38000161856Syc 				    "XFP is bad or absent on port<%d>\n",
38100161856Syc 				    portn));
38200161856Syc 			}
383ee5416c9Syc 			status = NXGE_ERROR;
384ee5416c9Syc 		}
3850cad6a5fSyc #endif
386ee5416c9Syc 	}
387ee5416c9Syc 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_check_xaui_xfp"));
388ee5416c9Syc 	return (status);
389ee5416c9Syc }
390ee5416c9Syc 
391ee5416c9Syc 
392a3c5bd6dSspeer /* ARGSUSED */
39344961713Sgirish uint_t
39444961713Sgirish nxge_syserr_intr(void *arg1, void *arg2)
39544961713Sgirish {
396a3c5bd6dSspeer 	p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1;
397a3c5bd6dSspeer 	p_nxge_t nxgep = (p_nxge_t)arg2;
398a3c5bd6dSspeer 	p_nxge_ldg_t ldgp = NULL;
399a3c5bd6dSspeer 	npi_handle_t handle;
400a3c5bd6dSspeer 	sys_err_stat_t estat;
401a3c5bd6dSspeer 	uint_t serviced = DDI_INTR_UNCLAIMED;
40244961713Sgirish 
40344961713Sgirish 	if (arg1 == NULL && arg2 == NULL) {
40444961713Sgirish 		return (serviced);
40544961713Sgirish 	}
406a3c5bd6dSspeer 	if (arg2 == NULL || ((ldvp != NULL && (void *) ldvp->nxgep != arg2))) {
40744961713Sgirish 		if (ldvp != NULL) {
40844961713Sgirish 			nxgep = ldvp->nxgep;
40944961713Sgirish 		}
41044961713Sgirish 	}
41144961713Sgirish 	NXGE_DEBUG_MSG((nxgep, SYSERR_CTL,
41252ccf843Smisaki 	    "==> nxge_syserr_intr: arg2 $%p arg1 $%p", nxgep, ldvp));
41344961713Sgirish 	if (ldvp != NULL && ldvp->use_timer == B_FALSE) {
41444961713Sgirish 		ldgp = ldvp->ldgp;
41544961713Sgirish 		if (ldgp == NULL) {
41644961713Sgirish 			NXGE_ERROR_MSG((nxgep, SYSERR_CTL,
41752ccf843Smisaki 			    "<== nxge_syserrintr(no logical group): "
41852ccf843Smisaki 			    "arg2 $%p arg1 $%p", nxgep, ldvp));
41944961713Sgirish 			return (DDI_INTR_UNCLAIMED);
42044961713Sgirish 		}
42144961713Sgirish 		/*
42244961713Sgirish 		 * Get the logical device state if the function uses interrupt.
42344961713Sgirish 		 */
42444961713Sgirish 	}
42544961713Sgirish 
42644961713Sgirish 	/* This interrupt handler is for system error interrupts.  */
42744961713Sgirish 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
42844961713Sgirish 	estat.value = 0;
42944961713Sgirish 	(void) npi_fzc_sys_err_stat_get(handle, &estat);
43044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, SYSERR_CTL,
43152ccf843Smisaki 	    "==> nxge_syserr_intr: device error 0x%016llx", estat.value));
43244961713Sgirish 
43344961713Sgirish 	if (estat.bits.ldw.smx) {
43444961713Sgirish 		/* SMX */
43544961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
43652ccf843Smisaki 		    "==> nxge_syserr_intr: device error - SMX"));
43744961713Sgirish 	} else if (estat.bits.ldw.mac) {
43844961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
43952ccf843Smisaki 		    "==> nxge_syserr_intr: device error - MAC"));
44044961713Sgirish 		/*
441a3c5bd6dSspeer 		 * There is nothing to be done here. All MAC errors go to per
442a3c5bd6dSspeer 		 * MAC port interrupt. MIF interrupt is the only MAC sub-block
443a3c5bd6dSspeer 		 * that can generate status here. MIF status reported will be
444a3c5bd6dSspeer 		 * ignored here. It is checked by per port timer instead.
44544961713Sgirish 		 */
44644961713Sgirish 	} else if (estat.bits.ldw.ipp) {
44744961713Sgirish 		NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
44852ccf843Smisaki 		    "==> nxge_syserr_intr: device error - IPP"));
44944961713Sgirish 		(void) nxge_ipp_handle_sys_errors(nxgep);
45044961713Sgirish 	} else if (estat.bits.ldw.zcp) {
45144961713Sgirish 		/* ZCP */
452f6485eecSyc 		NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
45352ccf843Smisaki 		    "==> nxge_syserr_intr: device error - ZCP"));
45444961713Sgirish 		(void) nxge_zcp_handle_sys_errors(nxgep);
45544961713Sgirish 	} else if (estat.bits.ldw.tdmc) {
45644961713Sgirish 		/* TDMC */
45744961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
45852ccf843Smisaki 		    "==> nxge_syserr_intr: device error - TDMC"));
45944961713Sgirish 		/*
460a3c5bd6dSspeer 		 * There is no TDMC system errors defined in the PRM. All TDMC
461a3c5bd6dSspeer 		 * channel specific errors are reported on a per channel basis.
46244961713Sgirish 		 */
46344961713Sgirish 	} else if (estat.bits.ldw.rdmc) {
46444961713Sgirish 		/* RDMC */
46544961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
46652ccf843Smisaki 		    "==> nxge_syserr_intr: device error - RDMC"));
46744961713Sgirish 		(void) nxge_rxdma_handle_sys_errors(nxgep);
46844961713Sgirish 	} else if (estat.bits.ldw.txc) {
46944961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
47052ccf843Smisaki 		    "==> nxge_syserr_intr: device error - TXC"));
47144961713Sgirish 		(void) nxge_txc_handle_sys_errors(nxgep);
47244961713Sgirish 	} else if ((nxgep->niu_type != N2_NIU) && estat.bits.ldw.peu) {
47344961713Sgirish 		/* PCI-E */
47444961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
47552ccf843Smisaki 		    "==> nxge_syserr_intr: device error - PCI-E"));
47644961713Sgirish 	} else if (estat.bits.ldw.meta1) {
47744961713Sgirish 		/* META1 */
47844961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
47952ccf843Smisaki 		    "==> nxge_syserr_intr: device error - META1"));
48044961713Sgirish 	} else if (estat.bits.ldw.meta2) {
48144961713Sgirish 		/* META2 */
48244961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
48352ccf843Smisaki 		    "==> nxge_syserr_intr: device error - META2"));
48444961713Sgirish 	} else if (estat.bits.ldw.fflp) {
48544961713Sgirish 		/* FFLP */
48644961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
48752ccf843Smisaki 		    "==> nxge_syserr_intr: device error - FFLP"));
48844961713Sgirish 		(void) nxge_fflp_handle_sys_errors(nxgep);
48944961713Sgirish 	}
490ee5416c9Syc 
49100161856Syc 	/*
49200161856Syc 	 * nxge_check_xaui_xfg checks XAUI for all of the following
49300161856Syc 	 * portmodes, but checks XFP only if portmode == PORT_10G_FIBER.
49400161856Syc 	 */
495ee5416c9Syc 	if (nxgep->mac.portmode == PORT_10G_FIBER ||
49652ccf843Smisaki 	    nxgep->mac.portmode == PORT_10G_COPPER ||
49752ccf843Smisaki 	    nxgep->mac.portmode == PORT_10G_TN1010 ||
49852ccf843Smisaki 	    nxgep->mac.portmode == PORT_1G_TN1010) {
499ee5416c9Syc 		if (nxge_check_xaui_xfp(nxgep) != NXGE_OK) {
500ee5416c9Syc 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
501ee5416c9Syc 			    "==> nxge_syserr_intr: device error - XAUI"));
502ee5416c9Syc 		}
503ee5416c9Syc 	}
504ee5416c9Syc 
50544961713Sgirish 	serviced = DDI_INTR_CLAIMED;
50644961713Sgirish 
50744961713Sgirish 	if (ldgp != NULL && ldvp != NULL && ldgp->nldvs == 1 &&
50852ccf843Smisaki 	    !ldvp->use_timer) {
50944961713Sgirish 		(void) npi_intr_ldg_mgmt_set(handle, ldgp->ldg,
51052ccf843Smisaki 		    B_TRUE, ldgp->ldg_timer);
51144961713Sgirish 	}
51244961713Sgirish 	NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "<== nxge_syserr_intr"));
51344961713Sgirish 	return (serviced);
51444961713Sgirish }
51544961713Sgirish 
516a3c5bd6dSspeer /* ARGSUSED */
51744961713Sgirish void
51844961713Sgirish nxge_intr_hw_enable(p_nxge_t nxgep)
51944961713Sgirish {
52044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_hw_enable"));
52144961713Sgirish 	(void) nxge_intr_mask_mgmt_set(nxgep, B_TRUE);
52244961713Sgirish 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_hw_enable"));
52344961713Sgirish }
52444961713Sgirish 
525a3c5bd6dSspeer /* ARGSUSED */
52644961713Sgirish void
52744961713Sgirish nxge_intr_hw_disable(p_nxge_t nxgep)
52844961713Sgirish {
52944961713Sgirish 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_hw_disable"));
53044961713Sgirish 	(void) nxge_intr_mask_mgmt_set(nxgep, B_FALSE);
53144961713Sgirish 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_hw_disable"));
53244961713Sgirish }
53344961713Sgirish 
534a3c5bd6dSspeer /* ARGSUSED */
53544961713Sgirish void
53644961713Sgirish nxge_rx_hw_blank(void *arg, time_t ticks, uint_t count)
53744961713Sgirish {
538a3c5bd6dSspeer 	p_nxge_t nxgep = (p_nxge_t)arg;
539a3c5bd6dSspeer 	uint8_t channel;
540a3c5bd6dSspeer 	npi_handle_t handle;
541a3c5bd6dSspeer 	p_nxge_ldgv_t ldgvp;
542a3c5bd6dSspeer 	p_nxge_ldv_t ldvp;
543a3c5bd6dSspeer 	int i;
54444961713Sgirish 
54544961713Sgirish 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_rx_hw_blank"));
54644961713Sgirish 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
54744961713Sgirish 
54844961713Sgirish 	if ((ldgvp = nxgep->ldgvp) == NULL) {
54944961713Sgirish 		NXGE_ERROR_MSG((nxgep, INT_CTL,
55052ccf843Smisaki 		    "<== nxge_rx_hw_blank (not enabled)"));
55144961713Sgirish 		return;
55244961713Sgirish 	}
55344961713Sgirish 	ldvp = nxgep->ldgvp->ldvp;
55444961713Sgirish 	if (ldvp == NULL) {
55544961713Sgirish 		return;
55644961713Sgirish 	}
55744961713Sgirish 	for (i = 0; i < ldgvp->nldvs; i++, ldvp++) {
55844961713Sgirish 		if (ldvp->is_rxdma) {
55944961713Sgirish 			channel = ldvp->channel;
56044961713Sgirish 			(void) npi_rxdma_cfg_rdc_rcr_threshold(handle,
56152ccf843Smisaki 			    channel, count);
56244961713Sgirish 			(void) npi_rxdma_cfg_rdc_rcr_timeout(handle,
56352ccf843Smisaki 			    channel, ticks);
56444961713Sgirish 		}
56544961713Sgirish 	}
56644961713Sgirish 
56744961713Sgirish 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_rx_hw_blank"));
56844961713Sgirish }
56944961713Sgirish 
570a3c5bd6dSspeer /* ARGSUSED */
57144961713Sgirish void
57244961713Sgirish nxge_hw_stop(p_nxge_t nxgep)
57344961713Sgirish {
57444961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_stop"));
57544961713Sgirish 
57644961713Sgirish 	(void) nxge_tx_mac_disable(nxgep);
57744961713Sgirish 	(void) nxge_rx_mac_disable(nxgep);
57844961713Sgirish 	(void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP);
57944961713Sgirish 	(void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP);
58044961713Sgirish 
58144961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_stop"));
58244961713Sgirish }
58344961713Sgirish 
584a3c5bd6dSspeer /* ARGSUSED */
58544961713Sgirish void
58644961713Sgirish nxge_hw_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp)
58744961713Sgirish {
58844961713Sgirish 	int cmd;
58944961713Sgirish 
59044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_hw_ioctl"));
59144961713Sgirish 
59244961713Sgirish 	if (nxgep == NULL) {
59344961713Sgirish 		miocnak(wq, mp, 0, EINVAL);
59444961713Sgirish 		return;
59544961713Sgirish 	}
59644961713Sgirish 	iocp->ioc_error = 0;
59744961713Sgirish 	cmd = iocp->ioc_cmd;
59844961713Sgirish 
59944961713Sgirish 	switch (cmd) {
60044961713Sgirish 	default:
60144961713Sgirish 		miocnak(wq, mp, 0, EINVAL);
60244961713Sgirish 		return;
60344961713Sgirish 
60444961713Sgirish 	case NXGE_GET_MII:
60544961713Sgirish 		nxge_get_mii(nxgep, mp->b_cont);
60644961713Sgirish 		miocack(wq, mp, sizeof (uint16_t), 0);
60744961713Sgirish 		break;
60844961713Sgirish 
60944961713Sgirish 	case NXGE_PUT_MII:
61044961713Sgirish 		nxge_put_mii(nxgep, mp->b_cont);
61144961713Sgirish 		miocack(wq, mp, 0, 0);
61244961713Sgirish 		break;
61344961713Sgirish 
61444961713Sgirish 	case NXGE_GET64:
61544961713Sgirish 		nxge_get64(nxgep, mp->b_cont);
61644961713Sgirish 		miocack(wq, mp, sizeof (uint32_t), 0);
61744961713Sgirish 		break;
61844961713Sgirish 
61944961713Sgirish 	case NXGE_PUT64:
62044961713Sgirish 		nxge_put64(nxgep, mp->b_cont);
62144961713Sgirish 		miocack(wq, mp, 0, 0);
62244961713Sgirish 		break;
62344961713Sgirish 
62444961713Sgirish 	case NXGE_PUT_TCAM:
62544961713Sgirish 		nxge_put_tcam(nxgep, mp->b_cont);
62644961713Sgirish 		miocack(wq, mp, 0, 0);
62744961713Sgirish 		break;
62844961713Sgirish 
62944961713Sgirish 	case NXGE_GET_TCAM:
63044961713Sgirish 		nxge_get_tcam(nxgep, mp->b_cont);
63144961713Sgirish 		miocack(wq, mp, 0, 0);
63244961713Sgirish 		break;
63344961713Sgirish 
63444961713Sgirish 	case NXGE_TX_REGS_DUMP:
63544961713Sgirish 		nxge_txdma_regs_dump_channels(nxgep);
63644961713Sgirish 		miocack(wq, mp, 0, 0);
63744961713Sgirish 		break;
63844961713Sgirish 	case NXGE_RX_REGS_DUMP:
63944961713Sgirish 		nxge_rxdma_regs_dump_channels(nxgep);
64044961713Sgirish 		miocack(wq, mp, 0, 0);
64144961713Sgirish 		break;
64244961713Sgirish 	case NXGE_VIR_INT_REGS_DUMP:
64344961713Sgirish 	case NXGE_INT_REGS_DUMP:
64444961713Sgirish 		nxge_virint_regs_dump(nxgep);
64544961713Sgirish 		miocack(wq, mp, 0, 0);
64644961713Sgirish 		break;
64744961713Sgirish 	case NXGE_RTRACE:
64844961713Sgirish 		nxge_rtrace_ioctl(nxgep, wq, mp, iocp);
64944961713Sgirish 		break;
65044961713Sgirish 	}
65144961713Sgirish }
65244961713Sgirish 
653a3c5bd6dSspeer /* ARGSUSED */
65444961713Sgirish void
65544961713Sgirish nxge_loopback_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp,
656a3c5bd6dSspeer 	struct iocblk *iocp)
65744961713Sgirish {
658a3c5bd6dSspeer 	p_lb_property_t lb_props;
659a3c5bd6dSspeer 
660a3c5bd6dSspeer 	size_t size;
661a3c5bd6dSspeer 	int i;
66244961713Sgirish 
66344961713Sgirish 	if (mp->b_cont == NULL) {
66444961713Sgirish 		miocnak(wq, mp, 0, EINVAL);
66544961713Sgirish 	}
66644961713Sgirish 	switch (iocp->ioc_cmd) {
66744961713Sgirish 	case LB_GET_MODE:
66844961713Sgirish 		NXGE_DEBUG_MSG((nxgep, IOC_CTL, "NXGE_GET_LB_MODE command"));
66944961713Sgirish 		if (nxgep != NULL) {
67044961713Sgirish 			*(lb_info_sz_t *)mp->b_cont->b_rptr =
67152ccf843Smisaki 			    nxgep->statsp->port_stats.lb_mode;
67244961713Sgirish 			miocack(wq, mp, sizeof (nxge_lb_t), 0);
673ee5416c9Syc 		} else {
67444961713Sgirish 			miocnak(wq, mp, 0, EINVAL);
675ee5416c9Syc 		}
67644961713Sgirish 		break;
67744961713Sgirish 	case LB_SET_MODE:
67844961713Sgirish 		NXGE_DEBUG_MSG((nxgep, IOC_CTL, "NXGE_SET_LB_MODE command"));
67944961713Sgirish 		if (iocp->ioc_count != sizeof (uint32_t)) {
68044961713Sgirish 			miocack(wq, mp, 0, 0);
68144961713Sgirish 			break;
68244961713Sgirish 		}
68344961713Sgirish 		if ((nxgep != NULL) && nxge_set_lb(nxgep, wq, mp->b_cont)) {
68444961713Sgirish 			miocack(wq, mp, 0, 0);
68544961713Sgirish 		} else {
68644961713Sgirish 			miocnak(wq, mp, 0, EPROTO);
68744961713Sgirish 		}
68844961713Sgirish 		break;
68944961713Sgirish 	case LB_GET_INFO_SIZE:
69044961713Sgirish 		NXGE_DEBUG_MSG((nxgep, IOC_CTL, "LB_GET_INFO_SIZE command"));
69144961713Sgirish 		if (nxgep != NULL) {
69244961713Sgirish 			size = sizeof (lb_normal);
69344961713Sgirish 			if (nxgep->statsp->mac_stats.cap_10gfdx) {
69400161856Syc 				/* TN1010 does not support external loopback */
69500161856Syc 				if (nxgep->mac.portmode != PORT_1G_TN1010 &&
69600161856Syc 				    nxgep->mac.portmode != PORT_10G_TN1010) {
69700161856Syc 					size += sizeof (lb_external10g);
69800161856Syc 				}
69944961713Sgirish 				size += sizeof (lb_mac10g);
700936117e2Ssbehera 				/* Publish PHY loopback if PHY is present */
701936117e2Ssbehera 				if (nxgep->mac.portmode == PORT_10G_COPPER ||
70200161856Syc 				    nxgep->mac.portmode == PORT_10G_TN1010 ||
703936117e2Ssbehera 				    nxgep->mac.portmode == PORT_10G_FIBER)
704936117e2Ssbehera 					size += sizeof (lb_phy10g);
70544961713Sgirish 			}
70600161856Syc 
70700161856Syc 			/*
70800161856Syc 			 * Even if cap_10gfdx is false, we still do 10G
70900161856Syc 			 * serdes loopback as a part of SunVTS xnetlbtest
71000161856Syc 			 * internal loopback test.
71100161856Syc 			 */
712936117e2Ssbehera 			if (nxgep->mac.portmode == PORT_10G_FIBER ||
71300161856Syc 			    nxgep->mac.portmode == PORT_10G_TN1010 ||
714936117e2Ssbehera 			    nxgep->mac.portmode == PORT_10G_SERDES)
715936117e2Ssbehera 				size += sizeof (lb_serdes10g);
716936117e2Ssbehera 
71744961713Sgirish 			if (nxgep->statsp->mac_stats.cap_1000fdx) {
71800161856Syc 				/* TN1010 does not support external loopback */
71900161856Syc 				if (nxgep->mac.portmode != PORT_1G_TN1010 &&
72000161856Syc 				    nxgep->mac.portmode != PORT_10G_TN1010) {
72100161856Syc 					size += sizeof (lb_external1000);
72200161856Syc 				}
72344961713Sgirish 				size += sizeof (lb_mac1000);
7240cad6a5fSyc 				if (nxgep->mac.portmode == PORT_1G_COPPER ||
72500161856Syc 				    nxgep->mac.portmode == PORT_1G_TN1010 ||
7260cad6a5fSyc 				    nxgep->mac.portmode ==
7270cad6a5fSyc 				    PORT_1G_RGMII_FIBER)
72844961713Sgirish 					size += sizeof (lb_phy1000);
72944961713Sgirish 			}
73044961713Sgirish 			if (nxgep->statsp->mac_stats.cap_100fdx)
73144961713Sgirish 				size += sizeof (lb_external100);
73244961713Sgirish 			if (nxgep->statsp->mac_stats.cap_10fdx)
73344961713Sgirish 				size += sizeof (lb_external10);
734936117e2Ssbehera 			if (nxgep->mac.portmode == PORT_1G_FIBER ||
73500161856Syc 			    nxgep->mac.portmode == PORT_1G_TN1010 ||
736936117e2Ssbehera 			    nxgep->mac.portmode == PORT_1G_SERDES)
73744961713Sgirish 				size += sizeof (lb_serdes1000);
7382e59129aSraghus 
73944961713Sgirish 			*(lb_info_sz_t *)mp->b_cont->b_rptr = size;
74044961713Sgirish 
74144961713Sgirish 			NXGE_DEBUG_MSG((nxgep, IOC_CTL,
74252ccf843Smisaki 			    "NXGE_GET_LB_INFO command: size %d", size));
74344961713Sgirish 			miocack(wq, mp, sizeof (lb_info_sz_t), 0);
74444961713Sgirish 		} else
74544961713Sgirish 			miocnak(wq, mp, 0, EINVAL);
74644961713Sgirish 		break;
74744961713Sgirish 
74844961713Sgirish 	case LB_GET_INFO:
74944961713Sgirish 		NXGE_DEBUG_MSG((nxgep, IOC_CTL, "NXGE_GET_LB_INFO command"));
75044961713Sgirish 		if (nxgep != NULL) {
75144961713Sgirish 			size = sizeof (lb_normal);
75244961713Sgirish 			if (nxgep->statsp->mac_stats.cap_10gfdx) {
75300161856Syc 				/* TN1010 does not support external loopback */
75400161856Syc 				if (nxgep->mac.portmode != PORT_1G_TN1010 &&
75500161856Syc 				    nxgep->mac.portmode != PORT_10G_TN1010) {
75600161856Syc 					size += sizeof (lb_external10g);
75700161856Syc 				}
75844961713Sgirish 				size += sizeof (lb_mac10g);
759936117e2Ssbehera 				/* Publish PHY loopback if PHY is present */
760936117e2Ssbehera 				if (nxgep->mac.portmode == PORT_10G_COPPER ||
76100161856Syc 				    nxgep->mac.portmode == PORT_10G_TN1010 ||
762936117e2Ssbehera 				    nxgep->mac.portmode == PORT_10G_FIBER)
763936117e2Ssbehera 					size += sizeof (lb_phy10g);
76444961713Sgirish 			}
765936117e2Ssbehera 			if (nxgep->mac.portmode == PORT_10G_FIBER ||
76600161856Syc 			    nxgep->mac.portmode == PORT_10G_TN1010 ||
767936117e2Ssbehera 			    nxgep->mac.portmode == PORT_10G_SERDES)
768936117e2Ssbehera 				size += sizeof (lb_serdes10g);
769936117e2Ssbehera 
77044961713Sgirish 			if (nxgep->statsp->mac_stats.cap_1000fdx) {
77100161856Syc 				/* TN1010 does not support external loopback */
77200161856Syc 				if (nxgep->mac.portmode != PORT_1G_TN1010 &&
77300161856Syc 				    nxgep->mac.portmode != PORT_10G_TN1010) {
77400161856Syc 					size += sizeof (lb_external1000);
77500161856Syc 				}
77644961713Sgirish 				size += sizeof (lb_mac1000);
7770cad6a5fSyc 				if (nxgep->mac.portmode == PORT_1G_COPPER ||
77800161856Syc 				    nxgep->mac.portmode == PORT_1G_TN1010 ||
7790cad6a5fSyc 				    nxgep->mac.portmode ==
7800cad6a5fSyc 				    PORT_1G_RGMII_FIBER)
78144961713Sgirish 					size += sizeof (lb_phy1000);
78244961713Sgirish 			}
78344961713Sgirish 			if (nxgep->statsp->mac_stats.cap_100fdx)
78444961713Sgirish 				size += sizeof (lb_external100);
78500161856Syc 
78644961713Sgirish 			if (nxgep->statsp->mac_stats.cap_10fdx)
78744961713Sgirish 				size += sizeof (lb_external10);
78800161856Syc 
789936117e2Ssbehera 			if (nxgep->mac.portmode == PORT_1G_FIBER ||
79000161856Syc 			    nxgep->mac.portmode == PORT_1G_TN1010 ||
791936117e2Ssbehera 			    nxgep->mac.portmode == PORT_1G_SERDES)
79244961713Sgirish 				size += sizeof (lb_serdes1000);
79344961713Sgirish 
79444961713Sgirish 			NXGE_DEBUG_MSG((nxgep, IOC_CTL,
79552ccf843Smisaki 			    "NXGE_GET_LB_INFO command: size %d", size));
79644961713Sgirish 			if (size == iocp->ioc_count) {
79744961713Sgirish 				i = 0;
79844961713Sgirish 				lb_props = (p_lb_property_t)mp->b_cont->b_rptr;
79944961713Sgirish 				lb_props[i++] = lb_normal;
80000161856Syc 
80144961713Sgirish 				if (nxgep->statsp->mac_stats.cap_10gfdx) {
80244961713Sgirish 					lb_props[i++] = lb_mac10g;
803936117e2Ssbehera 					if (nxgep->mac.portmode ==
804936117e2Ssbehera 					    PORT_10G_COPPER ||
805936117e2Ssbehera 					    nxgep->mac.portmode ==
80600161856Syc 					    PORT_10G_TN1010 ||
80700161856Syc 					    nxgep->mac.portmode ==
80800161856Syc 					    PORT_10G_FIBER) {
809936117e2Ssbehera 						lb_props[i++] = lb_phy10g;
81000161856Syc 					}
81100161856Syc 					/* TN1010 does not support ext lb */
81200161856Syc 					if (nxgep->mac.portmode !=
81300161856Syc 					    PORT_10G_TN1010 &&
81400161856Syc 					    nxgep->mac.portmode !=
81500161856Syc 					    PORT_1G_TN1010) {
81600161856Syc 						lb_props[i++] = lb_external10g;
81700161856Syc 					}
81844961713Sgirish 				}
81900161856Syc 
820936117e2Ssbehera 				if (nxgep->mac.portmode == PORT_10G_FIBER ||
82100161856Syc 				    nxgep->mac.portmode == PORT_10G_TN1010 ||
822936117e2Ssbehera 				    nxgep->mac.portmode == PORT_10G_SERDES)
823936117e2Ssbehera 					lb_props[i++] = lb_serdes10g;
824936117e2Ssbehera 
82500161856Syc 				if (nxgep->statsp->mac_stats.cap_1000fdx) {
82600161856Syc 					/* TN1010 does not support ext lb */
82700161856Syc 					if (nxgep->mac.portmode !=
82800161856Syc 					    PORT_10G_TN1010 &&
82900161856Syc 					    nxgep->mac.portmode !=
83000161856Syc 					    PORT_1G_TN1010) {
83100161856Syc 						lb_props[i++] = lb_external1000;
83200161856Syc 					}
83300161856Syc 				}
83400161856Syc 
83544961713Sgirish 				if (nxgep->statsp->mac_stats.cap_100fdx)
83644961713Sgirish 					lb_props[i++] = lb_external100;
83700161856Syc 
83844961713Sgirish 				if (nxgep->statsp->mac_stats.cap_10fdx)
83944961713Sgirish 					lb_props[i++] = lb_external10;
84000161856Syc 
84144961713Sgirish 				if (nxgep->statsp->mac_stats.cap_1000fdx)
84244961713Sgirish 					lb_props[i++] = lb_mac1000;
84300161856Syc 
8440cad6a5fSyc 				if (nxgep->mac.portmode == PORT_1G_COPPER ||
84500161856Syc 				    nxgep->mac.portmode == PORT_1G_TN1010 ||
8460cad6a5fSyc 				    nxgep->mac.portmode ==
8470cad6a5fSyc 				    PORT_1G_RGMII_FIBER) {
84844961713Sgirish 					if (nxgep->statsp->mac_stats.
84952ccf843Smisaki 					    cap_1000fdx)
85044961713Sgirish 						lb_props[i++] = lb_phy1000;
8510cad6a5fSyc 				} else if (nxgep->mac.portmode ==
8520cad6a5fSyc 				    PORT_1G_FIBER ||
8530cad6a5fSyc 				    nxgep->mac.portmode == PORT_1G_TN1010 ||
8540cad6a5fSyc 				    nxgep->mac.portmode == PORT_1G_SERDES) {
85544961713Sgirish 					lb_props[i++] = lb_serdes1000;
8562e59129aSraghus 				}
85744961713Sgirish 				miocack(wq, mp, size, 0);
85844961713Sgirish 			} else
85944961713Sgirish 				miocnak(wq, mp, 0, EINVAL);
86044961713Sgirish 		} else {
86144961713Sgirish 			miocnak(wq, mp, 0, EINVAL);
86244961713Sgirish 			cmn_err(CE_NOTE, "!nxge_hw_ioctl: invalid command 0x%x",
86352ccf843Smisaki 			    iocp->ioc_cmd);
86444961713Sgirish 		}
86544961713Sgirish 		break;
86644961713Sgirish 	}
86744961713Sgirish }
86844961713Sgirish 
86944961713Sgirish /*
87044961713Sgirish  * DMA channel interfaces to access various channel specific
87144961713Sgirish  * hardware functions.
87244961713Sgirish  */
873a3c5bd6dSspeer /* ARGSUSED */
87444961713Sgirish void
87544961713Sgirish nxge_rxdma_channel_put64(nxge_os_acc_handle_t handle, void *reg_addrp,
876a3c5bd6dSspeer 	uint32_t reg_base, uint16_t channel, uint64_t reg_data)
87744961713Sgirish {
878a3c5bd6dSspeer 	uint64_t reg_offset;
87944961713Sgirish 
88044961713Sgirish 	NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_put64"));
88144961713Sgirish 
88244961713Sgirish 	/*
883a3c5bd6dSspeer 	 * Channel is assumed to be from 0 to the maximum DMA channel #. If we
884a3c5bd6dSspeer 	 * use the virtual DMA CSR address space from the config space (in PCI
885a3c5bd6dSspeer 	 * case), then the following code need to be use different offset
88644961713Sgirish 	 * computation macro.
88744961713Sgirish 	 */
88844961713Sgirish 	reg_offset = reg_base + DMC_OFFSET(channel);
88944961713Sgirish 	NXGE_PIO_WRITE64(handle, reg_addrp, reg_offset, reg_data);
89044961713Sgirish 
89144961713Sgirish 	NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_put64"));
89244961713Sgirish }
89344961713Sgirish 
894a3c5bd6dSspeer /* ARGSUSED */
89544961713Sgirish uint64_t
89644961713Sgirish nxge_rxdma_channel_get64(nxge_os_acc_handle_t handle, void *reg_addrp,
897a3c5bd6dSspeer 	uint32_t reg_base, uint16_t channel)
89844961713Sgirish {
899a3c5bd6dSspeer 	uint64_t reg_offset;
90044961713Sgirish 
90144961713Sgirish 	NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_get64"));
90244961713Sgirish 
90344961713Sgirish 	/*
904a3c5bd6dSspeer 	 * Channel is assumed to be from 0 to the maximum DMA channel #. If we
905a3c5bd6dSspeer 	 * use the virtual DMA CSR address space from the config space (in PCI
906a3c5bd6dSspeer 	 * case), then the following code need to be use different offset
90744961713Sgirish 	 * computation macro.
90844961713Sgirish 	 */
90944961713Sgirish 	reg_offset = reg_base + DMC_OFFSET(channel);
91044961713Sgirish 
91144961713Sgirish 	NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_get64"));
91244961713Sgirish 
91344961713Sgirish 	return (NXGE_PIO_READ64(handle, reg_addrp, reg_offset));
91444961713Sgirish }
91544961713Sgirish 
916a3c5bd6dSspeer /* ARGSUSED */
91744961713Sgirish void
91844961713Sgirish nxge_get32(p_nxge_t nxgep, p_mblk_t mp)
91944961713Sgirish {
920a3c5bd6dSspeer 	nxge_os_acc_handle_t nxge_regh;
92144961713Sgirish 
92244961713Sgirish 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_get32"));
92344961713Sgirish 	nxge_regh = nxgep->dev_regs->nxge_regh;
92444961713Sgirish 
92544961713Sgirish 	*(uint32_t *)mp->b_rptr = NXGE_PIO_READ32(nxge_regh,
92652ccf843Smisaki 	    nxgep->dev_regs->nxge_regp, *(uint32_t *)mp->b_rptr);
92744961713Sgirish 
92844961713Sgirish 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "value = 0x%08X",
92952ccf843Smisaki 	    *(uint32_t *)mp->b_rptr));
93044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_get32"));
93144961713Sgirish }
93244961713Sgirish 
933a3c5bd6dSspeer /* ARGSUSED */
93444961713Sgirish void
93544961713Sgirish nxge_put32(p_nxge_t nxgep, p_mblk_t mp)
93644961713Sgirish {
93744961713Sgirish 	nxge_os_acc_handle_t nxge_regh;
93844961713Sgirish 	uint32_t *buf;
93944961713Sgirish 	uint8_t *reg;
94044961713Sgirish 
94144961713Sgirish 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_put32"));
94244961713Sgirish 	nxge_regh = nxgep->dev_regs->nxge_regh;
94344961713Sgirish 
94444961713Sgirish 	buf = (uint32_t *)mp->b_rptr;
94544961713Sgirish 	reg = (uint8_t *)(nxgep->dev_regs->nxge_regp) + buf[0];
94644961713Sgirish 	NXGE_DEBUG_MSG((nxgep, IOC_CTL,
94752ccf843Smisaki 	    "reg = 0x%016llX index = 0x%08X value = 0x%08X",
94852ccf843Smisaki 	    reg, buf[0], buf[1]));
94944961713Sgirish 	NXGE_PIO_WRITE32(nxge_regh, (uint32_t *)reg, 0, buf[1]);
95044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_put32"));
95144961713Sgirish }
95244961713Sgirish 
95344961713Sgirish /*ARGSUSED*/
95444961713Sgirish boolean_t
95544961713Sgirish nxge_set_lb(p_nxge_t nxgep, queue_t *wq, p_mblk_t mp)
95644961713Sgirish {
957a3c5bd6dSspeer 	boolean_t status = B_TRUE;
958a3c5bd6dSspeer 	uint32_t lb_mode;
959a3c5bd6dSspeer 	lb_property_t *lb_info;
96044961713Sgirish 
96144961713Sgirish 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_set_lb"));
96244961713Sgirish 	lb_mode = nxgep->statsp->port_stats.lb_mode;
96344961713Sgirish 	if (lb_mode == *(uint32_t *)mp->b_rptr) {
96444961713Sgirish 		cmn_err(CE_NOTE,
96552ccf843Smisaki 		    "!nxge%d: Loopback mode already set (lb_mode %d).\n",
96652ccf843Smisaki 		    nxgep->instance, lb_mode);
96744961713Sgirish 		status = B_FALSE;
96844961713Sgirish 		goto nxge_set_lb_exit;
96944961713Sgirish 	}
97044961713Sgirish 	lb_mode = *(uint32_t *)mp->b_rptr;
97144961713Sgirish 	lb_info = NULL;
97244961713Sgirish 	if (lb_mode == lb_normal.value)
97344961713Sgirish 		lb_info = &lb_normal;
97444961713Sgirish 	else if ((lb_mode == lb_external10g.value) &&
97552ccf843Smisaki 	    (nxgep->statsp->mac_stats.cap_10gfdx))
97644961713Sgirish 		lb_info = &lb_external10g;
97744961713Sgirish 	else if ((lb_mode == lb_external1000.value) &&
97852ccf843Smisaki 	    (nxgep->statsp->mac_stats.cap_1000fdx))
97944961713Sgirish 		lb_info = &lb_external1000;
98044961713Sgirish 	else if ((lb_mode == lb_external100.value) &&
98152ccf843Smisaki 	    (nxgep->statsp->mac_stats.cap_100fdx))
98244961713Sgirish 		lb_info = &lb_external100;
98344961713Sgirish 	else if ((lb_mode == lb_external10.value) &&
98452ccf843Smisaki 	    (nxgep->statsp->mac_stats.cap_10fdx))
98544961713Sgirish 		lb_info = &lb_external10;
98644961713Sgirish 	else if ((lb_mode == lb_phy10g.value) &&
9870cad6a5fSyc 	    (nxgep->mac.portmode == PORT_10G_COPPER ||
9880cad6a5fSyc 	    nxgep->mac.portmode == PORT_10G_TN1010 ||
9890cad6a5fSyc 	    nxgep->mac.portmode == PORT_10G_FIBER))
99044961713Sgirish 		lb_info = &lb_phy10g;
99144961713Sgirish 	else if ((lb_mode == lb_phy1000.value) &&
9920cad6a5fSyc 	    (nxgep->mac.portmode == PORT_1G_COPPER ||
9930cad6a5fSyc 	    nxgep->mac.portmode == PORT_1G_TN1010 ||
9940cad6a5fSyc 	    nxgep->mac.portmode == PORT_1G_RGMII_FIBER))
99544961713Sgirish 		lb_info = &lb_phy1000;
99644961713Sgirish 	else if ((lb_mode == lb_phy.value) &&
99752ccf843Smisaki 	    (nxgep->mac.portmode == PORT_1G_COPPER))
99844961713Sgirish 		lb_info = &lb_phy;
99944961713Sgirish 	else if ((lb_mode == lb_serdes10g.value) &&
10000cad6a5fSyc 	    (nxgep->mac.portmode == PORT_10G_FIBER ||
10010cad6a5fSyc 	    nxgep->mac.portmode == PORT_10G_COPPER ||
10020cad6a5fSyc 	    nxgep->mac.portmode == PORT_10G_TN1010 ||
10030cad6a5fSyc 	    nxgep->mac.portmode == PORT_10G_SERDES))
100444961713Sgirish 		lb_info = &lb_serdes10g;
100544961713Sgirish 	else if ((lb_mode == lb_serdes1000.value) &&
10060cad6a5fSyc 	    (nxgep->mac.portmode == PORT_1G_FIBER ||
10070cad6a5fSyc 	    nxgep->mac.portmode == PORT_1G_TN1010 ||
10080cad6a5fSyc 	    nxgep->mac.portmode == PORT_1G_SERDES))
100944961713Sgirish 		lb_info = &lb_serdes1000;
101044961713Sgirish 	else if (lb_mode == lb_mac10g.value)
101144961713Sgirish 		lb_info = &lb_mac10g;
101244961713Sgirish 	else if (lb_mode == lb_mac1000.value)
101344961713Sgirish 		lb_info = &lb_mac1000;
101444961713Sgirish 	else if (lb_mode == lb_mac.value)
101544961713Sgirish 		lb_info = &lb_mac;
101644961713Sgirish 	else {
101744961713Sgirish 		cmn_err(CE_NOTE,
101852ccf843Smisaki 		    "!nxge%d: Loopback mode not supported(mode %d).\n",
101952ccf843Smisaki 		    nxgep->instance, lb_mode);
102044961713Sgirish 		status = B_FALSE;
102144961713Sgirish 		goto nxge_set_lb_exit;
102244961713Sgirish 	}
102344961713Sgirish 
102444961713Sgirish 	if (lb_mode == nxge_lb_normal) {
102544961713Sgirish 		if (nxge_lb_dbg) {
102644961713Sgirish 			cmn_err(CE_NOTE,
102752ccf843Smisaki 			    "!nxge%d: Returning to normal operation",
102852ccf843Smisaki 			    nxgep->instance);
102944961713Sgirish 		}
1030321febdeSsbehera 		if (nxge_set_lb_normal(nxgep) != NXGE_OK) {
1031321febdeSsbehera 			status = B_FALSE;
1032321febdeSsbehera 			cmn_err(CE_NOTE,
1033321febdeSsbehera 			    "!nxge%d: Failed to return to normal operation",
1034321febdeSsbehera 			    nxgep->instance);
1035321febdeSsbehera 		}
103644961713Sgirish 		goto nxge_set_lb_exit;
103744961713Sgirish 	}
103844961713Sgirish 	nxgep->statsp->port_stats.lb_mode = lb_mode;
103944961713Sgirish 
104044961713Sgirish 	if (nxge_lb_dbg)
104144961713Sgirish 		cmn_err(CE_NOTE,
104252ccf843Smisaki 		    "!nxge%d: Adapter now in %s loopback mode",
104352ccf843Smisaki 		    nxgep->instance, lb_info->key);
104444961713Sgirish 	nxgep->param_arr[param_autoneg].value = 0;
104544961713Sgirish 	nxgep->param_arr[param_anar_10gfdx].value =
104652ccf843Smisaki 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10g) ||
104752ccf843Smisaki 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac10g) ||
104852ccf843Smisaki 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy10g) ||
104952ccf843Smisaki 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes10g);
105044961713Sgirish 	nxgep->param_arr[param_anar_10ghdx].value = 0;
105144961713Sgirish 	nxgep->param_arr[param_anar_1000fdx].value =
105252ccf843Smisaki 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext1000) ||
105352ccf843Smisaki 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac1000) ||
105452ccf843Smisaki 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy1000) ||
105552ccf843Smisaki 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes1000);
105644961713Sgirish 	nxgep->param_arr[param_anar_1000hdx].value = 0;
105744961713Sgirish 	nxgep->param_arr[param_anar_100fdx].value =
105852ccf843Smisaki 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy) ||
105952ccf843Smisaki 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac) ||
106052ccf843Smisaki 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext100);
106144961713Sgirish 	nxgep->param_arr[param_anar_100hdx].value = 0;
106244961713Sgirish 	nxgep->param_arr[param_anar_10fdx].value =
106352ccf843Smisaki 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac) ||
106452ccf843Smisaki 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10);
106544961713Sgirish 	if (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext1000) {
106644961713Sgirish 		nxgep->param_arr[param_master_cfg_enable].value = 1;
106744961713Sgirish 		nxgep->param_arr[param_master_cfg_value].value = 1;
106844961713Sgirish 	}
106944961713Sgirish 	if ((nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10g) ||
107052ccf843Smisaki 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext1000) ||
107152ccf843Smisaki 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext100) ||
107252ccf843Smisaki 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10) ||
107352ccf843Smisaki 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy10g) ||
107452ccf843Smisaki 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy1000) ||
107552ccf843Smisaki 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy)) {
107644961713Sgirish 
1077321febdeSsbehera 		if (nxge_link_monitor(nxgep, LINK_MONITOR_STOP) != NXGE_OK)
1078321febdeSsbehera 			goto nxge_set_lb_err;
1079321febdeSsbehera 		if (nxge_xcvr_find(nxgep) != NXGE_OK)
1080321febdeSsbehera 			goto nxge_set_lb_err;
1081321febdeSsbehera 		if (nxge_link_init(nxgep) != NXGE_OK)
1082321febdeSsbehera 			goto nxge_set_lb_err;
1083321febdeSsbehera 		if (nxge_link_monitor(nxgep, LINK_MONITOR_START) != NXGE_OK)
1084321febdeSsbehera 			goto nxge_set_lb_err;
108544961713Sgirish 	}
108644961713Sgirish 	if (lb_info->lb_type == internal) {
108744961713Sgirish 		if ((nxgep->statsp->port_stats.lb_mode == nxge_lb_mac10g) ||
108852ccf843Smisaki 		    (nxgep->statsp->port_stats.lb_mode ==
108952ccf843Smisaki 		    nxge_lb_phy10g) ||
109052ccf843Smisaki 		    (nxgep->statsp->port_stats.lb_mode ==
109152ccf843Smisaki 		    nxge_lb_serdes10g)) {
109244961713Sgirish 			nxgep->statsp->mac_stats.link_speed = 10000;
1093a3c5bd6dSspeer 		} else if ((nxgep->statsp->port_stats.lb_mode
109452ccf843Smisaki 		    == nxge_lb_mac1000) ||
109552ccf843Smisaki 		    (nxgep->statsp->port_stats.lb_mode ==
109652ccf843Smisaki 		    nxge_lb_phy1000) ||
109752ccf843Smisaki 		    (nxgep->statsp->port_stats.lb_mode ==
109852ccf843Smisaki 		    nxge_lb_serdes1000)) {
109944961713Sgirish 			nxgep->statsp->mac_stats.link_speed = 1000;
110044961713Sgirish 		} else {
110144961713Sgirish 			nxgep->statsp->mac_stats.link_speed = 100;
110244961713Sgirish 		}
110344961713Sgirish 		nxgep->statsp->mac_stats.link_duplex = 2;
110444961713Sgirish 		nxgep->statsp->mac_stats.link_up = 1;
110544961713Sgirish 	}
1106321febdeSsbehera 	if (nxge_global_reset(nxgep) != NXGE_OK)
1107321febdeSsbehera 		goto nxge_set_lb_err;
110844961713Sgirish 
110944961713Sgirish nxge_set_lb_exit:
111044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DDI_CTL,
111152ccf843Smisaki 	    "<== nxge_set_lb status = 0x%08x", status));
111244961713Sgirish 	return (status);
1113321febdeSsbehera nxge_set_lb_err:
1114321febdeSsbehera 	status = B_FALSE;
1115321febdeSsbehera 	cmn_err(CE_NOTE,
1116321febdeSsbehera 	    "!nxge%d: Failed to put adapter in %s loopback mode",
1117321febdeSsbehera 	    nxgep->instance, lb_info->key);
1118321febdeSsbehera 	return (status);
111944961713Sgirish }
112044961713Sgirish 
112100161856Syc /* Return to normal (no loopback) mode */
1122a3c5bd6dSspeer /* ARGSUSED */
1123321febdeSsbehera nxge_status_t
112444961713Sgirish nxge_set_lb_normal(p_nxge_t nxgep)
112544961713Sgirish {
1126321febdeSsbehera 	nxge_status_t	status = NXGE_OK;
1127321febdeSsbehera 
112844961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_set_lb_normal"));
1129321febdeSsbehera 
113044961713Sgirish 	nxgep->statsp->port_stats.lb_mode = nxge_lb_normal;
113144961713Sgirish 	nxgep->param_arr[param_autoneg].value =
113252ccf843Smisaki 	    nxgep->param_arr[param_autoneg].old_value;
113344961713Sgirish 	nxgep->param_arr[param_anar_1000fdx].value =
113452ccf843Smisaki 	    nxgep->param_arr[param_anar_1000fdx].old_value;
113544961713Sgirish 	nxgep->param_arr[param_anar_1000hdx].value =
113652ccf843Smisaki 	    nxgep->param_arr[param_anar_1000hdx].old_value;
113744961713Sgirish 	nxgep->param_arr[param_anar_100fdx].value =
113852ccf843Smisaki 	    nxgep->param_arr[param_anar_100fdx].old_value;
113944961713Sgirish 	nxgep->param_arr[param_anar_100hdx].value =
114052ccf843Smisaki 	    nxgep->param_arr[param_anar_100hdx].old_value;
114144961713Sgirish 	nxgep->param_arr[param_anar_10fdx].value =
114252ccf843Smisaki 	    nxgep->param_arr[param_anar_10fdx].old_value;
114344961713Sgirish 	nxgep->param_arr[param_master_cfg_enable].value =
114452ccf843Smisaki 	    nxgep->param_arr[param_master_cfg_enable].old_value;
114544961713Sgirish 	nxgep->param_arr[param_master_cfg_value].value =
114652ccf843Smisaki 	    nxgep->param_arr[param_master_cfg_value].old_value;
114744961713Sgirish 
1148321febdeSsbehera 	if ((status = nxge_global_reset(nxgep)) != NXGE_OK)
1149321febdeSsbehera 		return (status);
115044961713Sgirish 
1151321febdeSsbehera 	if ((status = nxge_link_monitor(nxgep, LINK_MONITOR_STOP)) != NXGE_OK)
1152321febdeSsbehera 		return (status);
1153321febdeSsbehera 	if ((status = nxge_xcvr_find(nxgep)) != NXGE_OK)
1154321febdeSsbehera 		return (status);
1155321febdeSsbehera 	if ((status = nxge_link_init(nxgep)) != NXGE_OK)
1156321febdeSsbehera 		return (status);
1157321febdeSsbehera 	status = nxge_link_monitor(nxgep, LINK_MONITOR_START);
115844961713Sgirish 
115944961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_set_lb_normal"));
1160321febdeSsbehera 
1161321febdeSsbehera 	return (status);
116244961713Sgirish }
116344961713Sgirish 
1164a3c5bd6dSspeer /* ARGSUSED */
116544961713Sgirish void
116644961713Sgirish nxge_get_mii(p_nxge_t nxgep, p_mblk_t mp)
116744961713Sgirish {
116844961713Sgirish 	uint16_t reg;
116944961713Sgirish 
117044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_get_mii"));
117144961713Sgirish 
117244961713Sgirish 	reg = *(uint16_t *)mp->b_rptr;
117344961713Sgirish 	(void) nxge_mii_read(nxgep, nxgep->statsp->mac_stats.xcvr_portn, reg,
117452ccf843Smisaki 	    (uint16_t *)mp->b_rptr);
117544961713Sgirish 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "reg = 0x%08X value = 0x%04X",
117652ccf843Smisaki 	    reg, *(uint16_t *)mp->b_rptr));
117744961713Sgirish 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_get_mii"));
117844961713Sgirish }
117944961713Sgirish 
1180a3c5bd6dSspeer /* ARGSUSED */
118144961713Sgirish void
118244961713Sgirish nxge_put_mii(p_nxge_t nxgep, p_mblk_t mp)
118344961713Sgirish {
118444961713Sgirish 	uint16_t *buf;
118544961713Sgirish 	uint8_t reg;
118644961713Sgirish 
118744961713Sgirish 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_put_mii"));
118844961713Sgirish 	buf = (uint16_t *)mp->b_rptr;
118944961713Sgirish 	reg = (uint8_t)buf[0];
119044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, IOC_CTL,
119152ccf843Smisaki 	    "reg = 0x%08X index = 0x%08X value = 0x%08X",
119252ccf843Smisaki 	    reg, buf[0], buf[1]));
119344961713Sgirish 	(void) nxge_mii_write(nxgep, nxgep->statsp->mac_stats.xcvr_portn,
119452ccf843Smisaki 	    reg, buf[1]);
119544961713Sgirish 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_put_mii"));
119644961713Sgirish }
119744961713Sgirish 
1198a3c5bd6dSspeer /* ARGSUSED */
119944961713Sgirish void
120044961713Sgirish nxge_check_hw_state(p_nxge_t nxgep)
120144961713Sgirish {
1202a3c5bd6dSspeer 	p_nxge_ldgv_t ldgvp;
1203a3c5bd6dSspeer 	p_nxge_ldv_t t_ldvp;
120444961713Sgirish 
120544961713Sgirish 	NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "==> nxge_check_hw_state"));
120644961713Sgirish 
120714ea4bb7Ssd 	MUTEX_ENTER(nxgep->genlock);
120814ea4bb7Ssd 	nxgep->nxge_timerid = 0;
120914ea4bb7Ssd 	if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) {
121014ea4bb7Ssd 		goto nxge_check_hw_state_exit;
121114ea4bb7Ssd 	}
121244961713Sgirish 	nxge_check_tx_hang(nxgep);
121344961713Sgirish 
121444961713Sgirish 	ldgvp = nxgep->ldgvp;
121544961713Sgirish 	if (ldgvp == NULL || (ldgvp->ldvp_syserr == NULL)) {
121644961713Sgirish 		NXGE_ERROR_MSG((nxgep, SYSERR_CTL, "<== nxge_check_hw_state: "
121752ccf843Smisaki 		    "NULL ldgvp (interrupt not ready)."));
121814ea4bb7Ssd 		goto nxge_check_hw_state_exit;
121944961713Sgirish 	}
122044961713Sgirish 	t_ldvp = ldgvp->ldvp_syserr;
122144961713Sgirish 	if (!t_ldvp->use_timer) {
122244961713Sgirish 		NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "<== nxge_check_hw_state: "
122352ccf843Smisaki 		    "ldgvp $%p t_ldvp $%p use_timer flag %d",
122452ccf843Smisaki 		    ldgvp, t_ldvp, t_ldvp->use_timer));
122514ea4bb7Ssd 		goto nxge_check_hw_state_exit;
122614ea4bb7Ssd 	}
122714ea4bb7Ssd 	if (fm_check_acc_handle(nxgep->dev_regs->nxge_regh) != DDI_FM_OK) {
122814ea4bb7Ssd 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
122952ccf843Smisaki 		    "port%d Bad register acc handle", nxgep->mac.portnum));
123044961713Sgirish 	}
1231a3c5bd6dSspeer 	(void) nxge_syserr_intr((void *) t_ldvp, (void *) nxgep);
123244961713Sgirish 
123344961713Sgirish 	nxgep->nxge_timerid = nxge_start_timer(nxgep, nxge_check_hw_state,
123452ccf843Smisaki 	    NXGE_CHECK_TIMER);
123544961713Sgirish 
123614ea4bb7Ssd nxge_check_hw_state_exit:
123714ea4bb7Ssd 	MUTEX_EXIT(nxgep->genlock);
123844961713Sgirish 	NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "<== nxge_check_hw_state"));
123944961713Sgirish }
124044961713Sgirish 
124144961713Sgirish /*ARGSUSED*/
124244961713Sgirish static void
1243a3c5bd6dSspeer nxge_rtrace_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp,
1244a3c5bd6dSspeer 	struct iocblk *iocp)
124544961713Sgirish {
1246a3c5bd6dSspeer 	ssize_t size;
1247a3c5bd6dSspeer 	rtrace_t *rtp;
1248a3c5bd6dSspeer 	mblk_t *nmp;
1249a3c5bd6dSspeer 	uint32_t i, j;
1250a3c5bd6dSspeer 	uint32_t start_blk;
1251a3c5bd6dSspeer 	uint32_t base_entry;
1252a3c5bd6dSspeer 	uint32_t num_entries;
125344961713Sgirish 
125444961713Sgirish 	NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_rtrace_ioctl"));
125544961713Sgirish 
125644961713Sgirish 	size = 1024;
125744961713Sgirish 	if (mp->b_cont == NULL || MBLKL(mp->b_cont) < size) {
125844961713Sgirish 		NXGE_DEBUG_MSG((nxgep, STR_CTL,
125952ccf843Smisaki 		    "malformed M_IOCTL MBLKL = %d size = %d",
126052ccf843Smisaki 		    MBLKL(mp->b_cont), size));
126144961713Sgirish 		miocnak(wq, mp, 0, EINVAL);
126244961713Sgirish 		return;
126344961713Sgirish 	}
126444961713Sgirish 	nmp = mp->b_cont;
126544961713Sgirish 	rtp = (rtrace_t *)nmp->b_rptr;
126644961713Sgirish 	start_blk = rtp->next_idx;
126744961713Sgirish 	num_entries = rtp->last_idx;
126844961713Sgirish 	base_entry = start_blk * MAX_RTRACE_IOC_ENTRIES;
126944961713Sgirish 
127044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, STR_CTL, "start_blk = %d\n", start_blk));
127144961713Sgirish 	NXGE_DEBUG_MSG((nxgep, STR_CTL, "num_entries = %d\n", num_entries));
127244961713Sgirish 	NXGE_DEBUG_MSG((nxgep, STR_CTL, "base_entry = %d\n", base_entry));
127344961713Sgirish 
127444961713Sgirish 	rtp->next_idx = npi_rtracebuf.next_idx;
127544961713Sgirish 	rtp->last_idx = npi_rtracebuf.last_idx;
127644961713Sgirish 	rtp->wrapped = npi_rtracebuf.wrapped;
127744961713Sgirish 	for (i = 0, j = base_entry; i < num_entries; i++, j++) {
127844961713Sgirish 		rtp->buf[i].ctl_addr = npi_rtracebuf.buf[j].ctl_addr;
127944961713Sgirish 		rtp->buf[i].val_l32 = npi_rtracebuf.buf[j].val_l32;
128044961713Sgirish 		rtp->buf[i].val_h32 = npi_rtracebuf.buf[j].val_h32;
128144961713Sgirish 	}
128244961713Sgirish 
128344961713Sgirish 	nmp->b_wptr = nmp->b_rptr + size;
128444961713Sgirish 	NXGE_DEBUG_MSG((nxgep, STR_CTL, "<== nxge_rtrace_ioctl"));
128544961713Sgirish 	miocack(wq, mp, (int)size, 0);
128644961713Sgirish }
1287