144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 2289282175SSantwona Behera * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. 2344961713Sgirish */ 2444961713Sgirish 25a3c5bd6dSspeer #include <sys/nxge/nxge_impl.h> 2644961713Sgirish 2744961713Sgirish /* 2844961713Sgirish * Tunable Receive Completion Ring Configuration B parameters. 2944961713Sgirish */ 30a3c5bd6dSspeer uint16_t nxge_rx_pkt_thres; /* 16 bits */ 31a3c5bd6dSspeer uint8_t nxge_rx_pkt_timeout; /* 6 bits based on DMA clock divider */ 32a3c5bd6dSspeer 33a3c5bd6dSspeer lb_property_t lb_normal = {normal, "normal", nxge_lb_normal}; 34a3c5bd6dSspeer lb_property_t lb_external10g = {external, "external10g", nxge_lb_ext10g}; 35a3c5bd6dSspeer lb_property_t lb_external1000 = {external, "external1000", nxge_lb_ext1000}; 36a3c5bd6dSspeer lb_property_t lb_external100 = {external, "external100", nxge_lb_ext100}; 37a3c5bd6dSspeer lb_property_t lb_external10 = {external, "external10", nxge_lb_ext10}; 38a3c5bd6dSspeer lb_property_t lb_phy10g = {internal, "phy10g", nxge_lb_phy10g}; 39a3c5bd6dSspeer lb_property_t lb_phy1000 = {internal, "phy1000", nxge_lb_phy1000}; 40a3c5bd6dSspeer lb_property_t lb_phy = {internal, "phy", nxge_lb_phy}; 41a3c5bd6dSspeer lb_property_t lb_serdes10g = {internal, "serdes10g", nxge_lb_serdes10g}; 42a3c5bd6dSspeer lb_property_t lb_serdes1000 = {internal, "serdes", nxge_lb_serdes1000}; 43a3c5bd6dSspeer lb_property_t lb_mac10g = {internal, "mac10g", nxge_lb_mac10g}; 44a3c5bd6dSspeer lb_property_t lb_mac1000 = {internal, "mac1000", nxge_lb_mac1000}; 45a3c5bd6dSspeer lb_property_t lb_mac = {internal, "mac10/100", nxge_lb_mac}; 4644961713Sgirish 4744961713Sgirish uint32_t nxge_lb_dbg = 1; 4844961713Sgirish void nxge_get_mii(p_nxge_t nxgep, p_mblk_t mp); 4944961713Sgirish void nxge_put_mii(p_nxge_t nxgep, p_mblk_t mp); 50ee5416c9Syc static nxge_status_t nxge_check_xaui_xfp(p_nxge_t nxgep); 5144961713Sgirish 5244961713Sgirish extern uint32_t nxge_rx_mode; 53a3c5bd6dSspeer extern uint32_t nxge_jumbo_mtu; 544df55fdeSJanie Lu extern uint16_t nxge_rdc_buf_offset; 5544961713Sgirish 56a3c5bd6dSspeer static void 57a3c5bd6dSspeer nxge_rtrace_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 5844961713Sgirish 59a3c5bd6dSspeer /* ARGSUSED */ 60321febdeSsbehera nxge_status_t 6144961713Sgirish nxge_global_reset(p_nxge_t nxgep) 6244961713Sgirish { 63321febdeSsbehera nxge_status_t status = NXGE_OK; 64321febdeSsbehera 6544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_global_reset")); 6644961713Sgirish 67321febdeSsbehera if ((status = nxge_link_monitor(nxgep, LINK_MONITOR_STOP)) != NXGE_OK) 68321febdeSsbehera return (status); 6944961713Sgirish (void) nxge_intr_hw_disable(nxgep); 7044961713Sgirish 7144961713Sgirish if ((nxgep->suspended) || 7252ccf843Smisaki ((nxgep->statsp->port_stats.lb_mode == 7352ccf843Smisaki nxge_lb_phy1000) || 7452ccf843Smisaki (nxgep->statsp->port_stats.lb_mode == 7552ccf843Smisaki nxge_lb_phy10g) || 7652ccf843Smisaki (nxgep->statsp->port_stats.lb_mode == 7752ccf843Smisaki nxge_lb_serdes1000) || 7852ccf843Smisaki (nxgep->statsp->port_stats.lb_mode == 7952ccf843Smisaki nxge_lb_serdes10g))) { 80321febdeSsbehera if ((status = nxge_link_init(nxgep)) != NXGE_OK) 81321febdeSsbehera return (status); 8244961713Sgirish } 83321febdeSsbehera 84321febdeSsbehera if ((status = nxge_link_monitor(nxgep, LINK_MONITOR_START)) != NXGE_OK) 85321febdeSsbehera return (status); 86321febdeSsbehera if ((status = nxge_mac_init(nxgep)) != NXGE_OK) 87321febdeSsbehera return (status); 8844961713Sgirish (void) nxge_intr_hw_enable(nxgep); 8944961713Sgirish 9044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_global_reset")); 91321febdeSsbehera return (status); 9244961713Sgirish } 9344961713Sgirish 94a3c5bd6dSspeer /* ARGSUSED */ 9544961713Sgirish void 9644961713Sgirish nxge_hw_id_init(p_nxge_t nxgep) 9744961713Sgirish { 9844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_id_init")); 9948056c53SMichael Speer 10044961713Sgirish /* 10144961713Sgirish * Set up initial hardware parameters required such as mac mtu size. 10244961713Sgirish */ 10344961713Sgirish nxgep->mac.is_jumbo = B_FALSE; 10448056c53SMichael Speer 1051bd6825cSml /* 1061bd6825cSml * Set the maxframe size to 1522 (1518 + 4) to account for 1071bd6825cSml * VLAN tagged packets. 1081bd6825cSml */ 10948056c53SMichael Speer nxgep->mac.minframesize = NXGE_MIN_MAC_FRAMESIZE; /* 64 */ 11048056c53SMichael Speer nxgep->mac.maxframesize = NXGE_MAX_MAC_FRAMESIZE; /* 1522 */ 11144961713Sgirish 11248056c53SMichael Speer NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_id_init: maxframesize %d", 11348056c53SMichael Speer nxgep->mac.maxframesize)); 11444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_id_init")); 11544961713Sgirish } 11644961713Sgirish 117a3c5bd6dSspeer /* ARGSUSED */ 11844961713Sgirish void 11944961713Sgirish nxge_hw_init_niu_common(p_nxge_t nxgep) 12044961713Sgirish { 121a3c5bd6dSspeer p_nxge_hw_list_t hw_p; 12244961713Sgirish 12344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_init_niu_common")); 12444961713Sgirish 12544961713Sgirish if ((hw_p = nxgep->nxge_hw_p) == NULL) { 12644961713Sgirish return; 12744961713Sgirish } 12844961713Sgirish MUTEX_ENTER(&hw_p->nxge_cfg_lock); 12944961713Sgirish if (hw_p->flags & COMMON_INIT_DONE) { 13044961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 13152ccf843Smisaki "nxge_hw_init_niu_common" 13252ccf843Smisaki " already done for dip $%p function %d exiting", 13352ccf843Smisaki hw_p->parent_devp, nxgep->function_num)); 13444961713Sgirish MUTEX_EXIT(&hw_p->nxge_cfg_lock); 13544961713Sgirish return; 13644961713Sgirish } 13744961713Sgirish 13844961713Sgirish hw_p->flags = COMMON_INIT_START; 13944961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, "nxge_hw_init_niu_common" 14052ccf843Smisaki " Started for device id %x with function %d", 14152ccf843Smisaki hw_p->parent_devp, nxgep->function_num)); 142a3c5bd6dSspeer 143a3c5bd6dSspeer /* per neptune common block init */ 144a3c5bd6dSspeer (void) nxge_fflp_hw_reset(nxgep); 14544961713Sgirish 1464df55fdeSJanie Lu if (nxgep->niu_hw_type != NIU_HW_TYPE_RF) { 1474df55fdeSJanie Lu switch (nxge_rdc_buf_offset) { 1484df55fdeSJanie Lu case SW_OFFSET_NO_OFFSET: 1494df55fdeSJanie Lu case SW_OFFSET_64: 1504df55fdeSJanie Lu case SW_OFFSET_128: 1514df55fdeSJanie Lu break; 1524df55fdeSJanie Lu default: 1534df55fdeSJanie Lu NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1544df55fdeSJanie Lu "nxge_hw_init_niu_common: Unsupported RDC buffer" 1554df55fdeSJanie Lu " offset code %d, setting to %d", 1564df55fdeSJanie Lu nxge_rdc_buf_offset, SW_OFFSET_NO_OFFSET)); 1574df55fdeSJanie Lu nxge_rdc_buf_offset = SW_OFFSET_NO_OFFSET; 1584df55fdeSJanie Lu break; 1594df55fdeSJanie Lu } 1604df55fdeSJanie Lu } else { 1614df55fdeSJanie Lu switch (nxge_rdc_buf_offset) { 1624df55fdeSJanie Lu case SW_OFFSET_NO_OFFSET: 1634df55fdeSJanie Lu case SW_OFFSET_64: 1644df55fdeSJanie Lu case SW_OFFSET_128: 1654df55fdeSJanie Lu case SW_OFFSET_192: 1664df55fdeSJanie Lu case SW_OFFSET_256: 1674df55fdeSJanie Lu case SW_OFFSET_320: 1684df55fdeSJanie Lu case SW_OFFSET_384: 1694df55fdeSJanie Lu case SW_OFFSET_448: 1704df55fdeSJanie Lu break; 1714df55fdeSJanie Lu default: 1724df55fdeSJanie Lu NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1734df55fdeSJanie Lu "nxge_hw_init_niu_common: Unsupported RDC buffer" 1744df55fdeSJanie Lu " offset code %d, setting to %d", 1754df55fdeSJanie Lu nxge_rdc_buf_offset, SW_OFFSET_NO_OFFSET)); 1764df55fdeSJanie Lu nxge_rdc_buf_offset = SW_OFFSET_NO_OFFSET; 1774df55fdeSJanie Lu break; 1784df55fdeSJanie Lu } 1794df55fdeSJanie Lu } 1804df55fdeSJanie Lu 18144961713Sgirish hw_p->flags = COMMON_INIT_DONE; 18244961713Sgirish MUTEX_EXIT(&hw_p->nxge_cfg_lock); 18344961713Sgirish 18444961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, "nxge_hw_init_niu_common" 18552ccf843Smisaki " Done for device id %x with function %d", 18652ccf843Smisaki hw_p->parent_devp, nxgep->function_num)); 18744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_init_niu_common")); 18844961713Sgirish } 18944961713Sgirish 190a3c5bd6dSspeer /* ARGSUSED */ 19144961713Sgirish uint_t 19244961713Sgirish nxge_intr(void *arg1, void *arg2) 19344961713Sgirish { 194a3c5bd6dSspeer p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 195a3c5bd6dSspeer p_nxge_t nxgep = (p_nxge_t)arg2; 196a3c5bd6dSspeer uint_t serviced = DDI_INTR_UNCLAIMED; 197a3c5bd6dSspeer uint8_t ldv; 198a3c5bd6dSspeer npi_handle_t handle; 199a3c5bd6dSspeer p_nxge_ldgv_t ldgvp; 200a3c5bd6dSspeer p_nxge_ldg_t ldgp, t_ldgp; 201a3c5bd6dSspeer p_nxge_ldv_t t_ldvp; 202a3c5bd6dSspeer uint64_t vector0 = 0, vector1 = 0, vector2 = 0; 203a3c5bd6dSspeer int i, j, nldvs, nintrs = 1; 204a3c5bd6dSspeer npi_status_t rs = NPI_SUCCESS; 20544961713Sgirish 206*4df3b64dSToomas Soome VERIFY(ldvp != NULL); 207*4df3b64dSToomas Soome 20844961713Sgirish /* DDI interface returns second arg as NULL (n2 niumx driver) !!! */ 209a3c5bd6dSspeer if (arg2 == NULL || (void *) ldvp->nxgep != arg2) { 21044961713Sgirish nxgep = ldvp->nxgep; 21144961713Sgirish } 21244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr")); 21344961713Sgirish 21444961713Sgirish if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 21544961713Sgirish NXGE_ERROR_MSG((nxgep, INT_CTL, 21652ccf843Smisaki "<== nxge_intr: not initialized 0x%x", serviced)); 21744961713Sgirish return (serviced); 21844961713Sgirish } 21944961713Sgirish 22044961713Sgirish ldgvp = nxgep->ldgvp; 221a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: ldgvp $%p", ldgvp)); 22244961713Sgirish if (ldvp == NULL && ldgvp) { 22344961713Sgirish t_ldvp = ldvp = ldgvp->ldvp; 22444961713Sgirish } 22544961713Sgirish if (ldvp) { 22644961713Sgirish ldgp = t_ldgp = ldvp->ldgp; 22744961713Sgirish } 22844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: " 22952ccf843Smisaki "ldgvp $%p ldvp $%p ldgp $%p", ldgvp, ldvp, ldgp)); 23044961713Sgirish if (ldgvp == NULL || ldvp == NULL || ldgp == NULL) { 23144961713Sgirish NXGE_ERROR_MSG((nxgep, INT_CTL, "==> nxge_intr: " 23252ccf843Smisaki "ldgvp $%p ldvp $%p ldgp $%p", ldgvp, ldvp, ldgp)); 23344961713Sgirish NXGE_ERROR_MSG((nxgep, INT_CTL, "<== nxge_intr: not ready")); 23444961713Sgirish return (DDI_INTR_UNCLAIMED); 23544961713Sgirish } 23644961713Sgirish /* 237a3c5bd6dSspeer * This interrupt handler will have to go through all the logical 238a3c5bd6dSspeer * devices to find out which logical device interrupts us and then call 23944961713Sgirish * its handler to process the events. 24044961713Sgirish */ 24144961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 24244961713Sgirish t_ldgp = ldgp; 24344961713Sgirish t_ldvp = ldgp->ldvp; 24444961713Sgirish 24544961713Sgirish nldvs = ldgp->nldvs; 24644961713Sgirish 24744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: #ldvs %d #intrs %d", 24852ccf843Smisaki nldvs, ldgvp->ldg_intrs)); 24944961713Sgirish 25044961713Sgirish serviced = DDI_INTR_CLAIMED; 25144961713Sgirish for (i = 0; i < nintrs; i++, t_ldgp++) { 25244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr(%d): #ldvs %d " 25352ccf843Smisaki " #intrs %d", i, nldvs, nintrs)); 25444961713Sgirish /* Get this group's flag bits. */ 25544961713Sgirish rs = npi_ldsv_ldfs_get(handle, t_ldgp->ldg, 25652ccf843Smisaki &vector0, &vector1, &vector2); 25744961713Sgirish if (rs) { 25844961713Sgirish continue; 25944961713Sgirish } 26044961713Sgirish if (!vector0 && !vector1 && !vector2) { 26144961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: " 26252ccf843Smisaki "no interrupts on group %d", t_ldgp->ldg)); 26344961713Sgirish continue; 26444961713Sgirish } 26544961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: " 26652ccf843Smisaki "vector0 0x%llx vector1 0x%llx vector2 0x%llx", 26752ccf843Smisaki vector0, vector1, vector2)); 26844961713Sgirish nldvs = t_ldgp->nldvs; 26944961713Sgirish for (j = 0; j < nldvs; j++, t_ldvp++) { 27044961713Sgirish /* 27144961713Sgirish * Call device's handler if flag bits are on. 27244961713Sgirish */ 27344961713Sgirish ldv = t_ldvp->ldv; 27444961713Sgirish if (((ldv < NXGE_MAC_LD_START) && 27552ccf843Smisaki (LDV_ON(ldv, vector0) | 27652ccf843Smisaki (LDV_ON(ldv, vector1)))) || 27752ccf843Smisaki (ldv >= NXGE_MAC_LD_START && 27852ccf843Smisaki ((LDV2_ON_1(ldv, vector2)) || 27952ccf843Smisaki (LDV2_ON_2(ldv, vector2))))) { 28044961713Sgirish (void) (t_ldvp->ldv_intr_handler)( 28152ccf843Smisaki (caddr_t)t_ldvp, arg2); 28244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 28352ccf843Smisaki "==> nxge_intr: " 28452ccf843Smisaki "calling device %d #ldvs %d #intrs %d", 28552ccf843Smisaki j, nldvs, nintrs)); 28644961713Sgirish } 28744961713Sgirish } 28844961713Sgirish } 28944961713Sgirish 29044961713Sgirish t_ldgp = ldgp; 29144961713Sgirish for (i = 0; i < nintrs; i++, t_ldgp++) { 29244961713Sgirish /* rearm group interrupts */ 293da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: arm " 294da14cebeSEric Cheng "group %d", t_ldgp->ldg)); 295da14cebeSEric Cheng (void) npi_intr_ldg_mgmt_set(handle, t_ldgp->ldg, 296da14cebeSEric Cheng t_ldgp->arm, t_ldgp->ldg_timer); 29744961713Sgirish } 29844961713Sgirish 29944961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr: serviced 0x%x", 30052ccf843Smisaki serviced)); 30144961713Sgirish return (serviced); 30244961713Sgirish } 30344961713Sgirish 30400161856Syc 30500161856Syc /* 30600161856Syc * XFP Related Status Register Values Under 3 Different Conditions 30700161856Syc * 30800161856Syc * -------------+-------------------------+------------------------- 3090cad6a5fSyc * | Intel XFP and Avago | Picolight XFP 31000161856Syc * -------------+---------+---------------+---------+--------------- 31100161856Syc * | STATUS0 | TX_ALARM_STAT | STATUS0 | TX_ALARM_STAT 31200161856Syc * -------------+---------+---------------+---------+--------------- 31300161856Syc * No XFP | 0x639C | 0x40 | 0x639C | 0x40 31400161856Syc * -------------+---------+---------------+---------+--------------- 31500161856Syc * XFP,linkdown | 0x43BC | 0x40 | 0x639C | 0x40 31600161856Syc * -------------+---------+---------------+---------+--------------- 31700161856Syc * XFP,linkup | 0x03FC | 0x0 | 0x03FC | 0x0 31800161856Syc * -------------+---------+---------------+---------+--------------- 31900161856Syc * Note: 32000161856Syc * STATUS0 = BCM8704_USER_ANALOG_STATUS0_REG 32100161856Syc * TX_ALARM_STAT = BCM8704_USER_TX_ALARM_STATUS_REG 32200161856Syc */ 323ee5416c9Syc /* ARGSUSED */ 324ee5416c9Syc static nxge_status_t 325ee5416c9Syc nxge_check_xaui_xfp(p_nxge_t nxgep) 326ee5416c9Syc { 327ee5416c9Syc nxge_status_t status = NXGE_OK; 328ee5416c9Syc uint8_t phy_port_addr; 329ee5416c9Syc uint16_t val; 330ee5416c9Syc uint16_t val1; 331ee5416c9Syc uint8_t portn; 332ee5416c9Syc 333ee5416c9Syc NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_check_xaui_xfp")); 334ee5416c9Syc 335ee5416c9Syc portn = nxgep->mac.portnum; 336ee5416c9Syc phy_port_addr = nxgep->statsp->mac_stats.xcvr_portn; 337ee5416c9Syc 33800161856Syc /* 33900161856Syc * Keep the val1 code even though it is not used. Could be 34000161856Syc * used to differenciate the "No XFP" case and "XFP,linkdown" 34100161856Syc * case when a Intel XFP is used. 34200161856Syc */ 343ee5416c9Syc if ((status = nxge_mdio_read(nxgep, phy_port_addr, 344ee5416c9Syc BCM8704_USER_DEV3_ADDR, 345ee5416c9Syc BCM8704_USER_ANALOG_STATUS0_REG, &val)) == NXGE_OK) { 346ee5416c9Syc status = nxge_mdio_read(nxgep, phy_port_addr, 347ee5416c9Syc BCM8704_USER_DEV3_ADDR, 348ee5416c9Syc BCM8704_USER_TX_ALARM_STATUS_REG, &val1); 349ee5416c9Syc } 35000161856Syc 351ee5416c9Syc if (status != NXGE_OK) { 352b37cc459SToomas Soome NXGE_FM_REPORT_ERROR(nxgep, portn, 0, 353ee5416c9Syc NXGE_FM_EREPORT_XAUI_ERR); 35400161856Syc if (DDI_FM_EREPORT_CAP(nxgep->fm_capabilities)) { 35500161856Syc NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 35600161856Syc "XAUI is bad or absent on port<%d>\n", portn)); 35700161856Syc } 3580cad6a5fSyc #ifdef NXGE_DEBUG 3590cad6a5fSyc /* 3600cad6a5fSyc * As a workaround for CR6693529, do not execute this block of 3610cad6a5fSyc * code for non-debug driver. When a Picolight XFP transceiver 3620cad6a5fSyc * is used, register BCM8704_USER_ANALOG_STATUS0_REG returns 3630cad6a5fSyc * the same 0x639C value in normal link down case, which causes 3640cad6a5fSyc * false FMA messages and link reconnection problem. 3650cad6a5fSyc */ 366ee5416c9Syc } else if (nxgep->mac.portmode == PORT_10G_FIBER) { 367ee5416c9Syc /* 368f6485eecSyc * 0x03FC = 0000 0011 1111 1100 (XFP is normal) 369f6485eecSyc * 0x639C = 0110 0011 1001 1100 (XFP has problem) 370ee5416c9Syc * bit14 = 1: PDM loss-of-light indicator 371ee5416c9Syc * bit13 = 1: PDM Rx loss-of-signal 372ee5416c9Syc * bit6 = 0: Light is NOT ok 373ee5416c9Syc * bit5 = 0: PMD Rx signal is NOT ok 374ee5416c9Syc */ 375f6485eecSyc if (val == 0x639C) { 376ee5416c9Syc NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 377ee5416c9Syc NXGE_FM_EREPORT_XFP_ERR); 37800161856Syc if (DDI_FM_EREPORT_CAP(nxgep->fm_capabilities)) { 37900161856Syc NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 38000161856Syc "XFP is bad or absent on port<%d>\n", 38100161856Syc portn)); 38200161856Syc } 383ee5416c9Syc status = NXGE_ERROR; 384ee5416c9Syc } 3850cad6a5fSyc #endif 386ee5416c9Syc } 387ee5416c9Syc NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_check_xaui_xfp")); 388ee5416c9Syc return (status); 389ee5416c9Syc } 390ee5416c9Syc 391ee5416c9Syc 392a3c5bd6dSspeer /* ARGSUSED */ 39344961713Sgirish uint_t 39444961713Sgirish nxge_syserr_intr(void *arg1, void *arg2) 39544961713Sgirish { 396a3c5bd6dSspeer p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 397a3c5bd6dSspeer p_nxge_t nxgep = (p_nxge_t)arg2; 398a3c5bd6dSspeer p_nxge_ldg_t ldgp = NULL; 399a3c5bd6dSspeer npi_handle_t handle; 400a3c5bd6dSspeer sys_err_stat_t estat; 401a3c5bd6dSspeer uint_t serviced = DDI_INTR_UNCLAIMED; 40244961713Sgirish 40344961713Sgirish if (arg1 == NULL && arg2 == NULL) { 40444961713Sgirish return (serviced); 40544961713Sgirish } 406a3c5bd6dSspeer if (arg2 == NULL || ((ldvp != NULL && (void *) ldvp->nxgep != arg2))) { 40744961713Sgirish if (ldvp != NULL) { 40844961713Sgirish nxgep = ldvp->nxgep; 40944961713Sgirish } 41044961713Sgirish } 41144961713Sgirish NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, 41252ccf843Smisaki "==> nxge_syserr_intr: arg2 $%p arg1 $%p", nxgep, ldvp)); 41344961713Sgirish if (ldvp != NULL && ldvp->use_timer == B_FALSE) { 41444961713Sgirish ldgp = ldvp->ldgp; 41544961713Sgirish if (ldgp == NULL) { 41644961713Sgirish NXGE_ERROR_MSG((nxgep, SYSERR_CTL, 41752ccf843Smisaki "<== nxge_syserrintr(no logical group): " 41852ccf843Smisaki "arg2 $%p arg1 $%p", nxgep, ldvp)); 41944961713Sgirish return (DDI_INTR_UNCLAIMED); 42044961713Sgirish } 42144961713Sgirish /* 42244961713Sgirish * Get the logical device state if the function uses interrupt. 42344961713Sgirish */ 42444961713Sgirish } 42544961713Sgirish 42644961713Sgirish /* This interrupt handler is for system error interrupts. */ 42744961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 42844961713Sgirish estat.value = 0; 42944961713Sgirish (void) npi_fzc_sys_err_stat_get(handle, &estat); 43044961713Sgirish NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, 43152ccf843Smisaki "==> nxge_syserr_intr: device error 0x%016llx", estat.value)); 43244961713Sgirish 43344961713Sgirish if (estat.bits.ldw.smx) { 43444961713Sgirish /* SMX */ 43544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 43652ccf843Smisaki "==> nxge_syserr_intr: device error - SMX")); 43744961713Sgirish } else if (estat.bits.ldw.mac) { 43844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 43952ccf843Smisaki "==> nxge_syserr_intr: device error - MAC")); 44044961713Sgirish /* 441a3c5bd6dSspeer * There is nothing to be done here. All MAC errors go to per 442a3c5bd6dSspeer * MAC port interrupt. MIF interrupt is the only MAC sub-block 443a3c5bd6dSspeer * that can generate status here. MIF status reported will be 444a3c5bd6dSspeer * ignored here. It is checked by per port timer instead. 44544961713Sgirish */ 44644961713Sgirish } else if (estat.bits.ldw.ipp) { 44744961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 44852ccf843Smisaki "==> nxge_syserr_intr: device error - IPP")); 44944961713Sgirish (void) nxge_ipp_handle_sys_errors(nxgep); 45044961713Sgirish } else if (estat.bits.ldw.zcp) { 45144961713Sgirish /* ZCP */ 452f6485eecSyc NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 45352ccf843Smisaki "==> nxge_syserr_intr: device error - ZCP")); 45444961713Sgirish (void) nxge_zcp_handle_sys_errors(nxgep); 45544961713Sgirish } else if (estat.bits.ldw.tdmc) { 45644961713Sgirish /* TDMC */ 45744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 45852ccf843Smisaki "==> nxge_syserr_intr: device error - TDMC")); 45944961713Sgirish /* 460a3c5bd6dSspeer * There is no TDMC system errors defined in the PRM. All TDMC 461a3c5bd6dSspeer * channel specific errors are reported on a per channel basis. 46244961713Sgirish */ 46344961713Sgirish } else if (estat.bits.ldw.rdmc) { 46444961713Sgirish /* RDMC */ 46544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 46652ccf843Smisaki "==> nxge_syserr_intr: device error - RDMC")); 46744961713Sgirish (void) nxge_rxdma_handle_sys_errors(nxgep); 46844961713Sgirish } else if (estat.bits.ldw.txc) { 46944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 47052ccf843Smisaki "==> nxge_syserr_intr: device error - TXC")); 47144961713Sgirish (void) nxge_txc_handle_sys_errors(nxgep); 47244961713Sgirish } else if ((nxgep->niu_type != N2_NIU) && estat.bits.ldw.peu) { 47344961713Sgirish /* PCI-E */ 47444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 47552ccf843Smisaki "==> nxge_syserr_intr: device error - PCI-E")); 47644961713Sgirish } else if (estat.bits.ldw.meta1) { 47744961713Sgirish /* META1 */ 47844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 47952ccf843Smisaki "==> nxge_syserr_intr: device error - META1")); 48044961713Sgirish } else if (estat.bits.ldw.meta2) { 48144961713Sgirish /* META2 */ 48244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 48352ccf843Smisaki "==> nxge_syserr_intr: device error - META2")); 48444961713Sgirish } else if (estat.bits.ldw.fflp) { 48544961713Sgirish /* FFLP */ 48644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 48752ccf843Smisaki "==> nxge_syserr_intr: device error - FFLP")); 48844961713Sgirish (void) nxge_fflp_handle_sys_errors(nxgep); 48944961713Sgirish } 490ee5416c9Syc 49100161856Syc /* 49200161856Syc * nxge_check_xaui_xfg checks XAUI for all of the following 49300161856Syc * portmodes, but checks XFP only if portmode == PORT_10G_FIBER. 49400161856Syc */ 495ee5416c9Syc if (nxgep->mac.portmode == PORT_10G_FIBER || 49652ccf843Smisaki nxgep->mac.portmode == PORT_10G_COPPER || 49752ccf843Smisaki nxgep->mac.portmode == PORT_10G_TN1010 || 49852ccf843Smisaki nxgep->mac.portmode == PORT_1G_TN1010) { 499ee5416c9Syc if (nxge_check_xaui_xfp(nxgep) != NXGE_OK) { 500ee5416c9Syc NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 501ee5416c9Syc "==> nxge_syserr_intr: device error - XAUI")); 502ee5416c9Syc } 503ee5416c9Syc } 504ee5416c9Syc 50544961713Sgirish serviced = DDI_INTR_CLAIMED; 50644961713Sgirish 50744961713Sgirish if (ldgp != NULL && ldvp != NULL && ldgp->nldvs == 1 && 50852ccf843Smisaki !ldvp->use_timer) { 50944961713Sgirish (void) npi_intr_ldg_mgmt_set(handle, ldgp->ldg, 51052ccf843Smisaki B_TRUE, ldgp->ldg_timer); 51144961713Sgirish } 51244961713Sgirish NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "<== nxge_syserr_intr")); 51344961713Sgirish return (serviced); 51444961713Sgirish } 51544961713Sgirish 516a3c5bd6dSspeer /* ARGSUSED */ 51744961713Sgirish void 51844961713Sgirish nxge_intr_hw_enable(p_nxge_t nxgep) 51944961713Sgirish { 52044961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_hw_enable")); 52144961713Sgirish (void) nxge_intr_mask_mgmt_set(nxgep, B_TRUE); 52244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_hw_enable")); 52344961713Sgirish } 52444961713Sgirish 525a3c5bd6dSspeer /* ARGSUSED */ 52644961713Sgirish void 52744961713Sgirish nxge_intr_hw_disable(p_nxge_t nxgep) 52844961713Sgirish { 52944961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_hw_disable")); 53044961713Sgirish (void) nxge_intr_mask_mgmt_set(nxgep, B_FALSE); 53144961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_hw_disable")); 53244961713Sgirish } 53344961713Sgirish 534a3c5bd6dSspeer /* ARGSUSED */ 53544961713Sgirish void 53644961713Sgirish nxge_rx_hw_blank(void *arg, time_t ticks, uint_t count) 53744961713Sgirish { 538a3c5bd6dSspeer p_nxge_t nxgep = (p_nxge_t)arg; 539a3c5bd6dSspeer uint8_t channel; 540a3c5bd6dSspeer npi_handle_t handle; 541a3c5bd6dSspeer p_nxge_ldgv_t ldgvp; 542a3c5bd6dSspeer p_nxge_ldv_t ldvp; 543a3c5bd6dSspeer int i; 54444961713Sgirish 54544961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_rx_hw_blank")); 54644961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 54744961713Sgirish 54844961713Sgirish if ((ldgvp = nxgep->ldgvp) == NULL) { 54944961713Sgirish NXGE_ERROR_MSG((nxgep, INT_CTL, 55052ccf843Smisaki "<== nxge_rx_hw_blank (not enabled)")); 55144961713Sgirish return; 55244961713Sgirish } 55344961713Sgirish ldvp = nxgep->ldgvp->ldvp; 55444961713Sgirish if (ldvp == NULL) { 55544961713Sgirish return; 55644961713Sgirish } 55744961713Sgirish for (i = 0; i < ldgvp->nldvs; i++, ldvp++) { 55844961713Sgirish if (ldvp->is_rxdma) { 55944961713Sgirish channel = ldvp->channel; 56044961713Sgirish (void) npi_rxdma_cfg_rdc_rcr_threshold(handle, 56152ccf843Smisaki channel, count); 56244961713Sgirish (void) npi_rxdma_cfg_rdc_rcr_timeout(handle, 56352ccf843Smisaki channel, ticks); 56444961713Sgirish } 56544961713Sgirish } 56644961713Sgirish 56744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_rx_hw_blank")); 56844961713Sgirish } 56944961713Sgirish 570a3c5bd6dSspeer /* ARGSUSED */ 57144961713Sgirish void 57244961713Sgirish nxge_hw_stop(p_nxge_t nxgep) 57344961713Sgirish { 57444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_stop")); 57544961713Sgirish 57644961713Sgirish (void) nxge_tx_mac_disable(nxgep); 57744961713Sgirish (void) nxge_rx_mac_disable(nxgep); 57844961713Sgirish (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP); 57944961713Sgirish (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 58044961713Sgirish 58144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_stop")); 58244961713Sgirish } 58344961713Sgirish 584a3c5bd6dSspeer /* ARGSUSED */ 58544961713Sgirish void 58644961713Sgirish nxge_hw_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 58744961713Sgirish { 58844961713Sgirish int cmd; 58944961713Sgirish 59044961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_hw_ioctl")); 59144961713Sgirish 59244961713Sgirish if (nxgep == NULL) { 59344961713Sgirish miocnak(wq, mp, 0, EINVAL); 59444961713Sgirish return; 59544961713Sgirish } 59644961713Sgirish iocp->ioc_error = 0; 59744961713Sgirish cmd = iocp->ioc_cmd; 59844961713Sgirish 59944961713Sgirish switch (cmd) { 60044961713Sgirish default: 60144961713Sgirish miocnak(wq, mp, 0, EINVAL); 60244961713Sgirish return; 60344961713Sgirish 60444961713Sgirish case NXGE_GET_MII: 60544961713Sgirish nxge_get_mii(nxgep, mp->b_cont); 60644961713Sgirish miocack(wq, mp, sizeof (uint16_t), 0); 60744961713Sgirish break; 60844961713Sgirish 60944961713Sgirish case NXGE_PUT_MII: 61044961713Sgirish nxge_put_mii(nxgep, mp->b_cont); 61144961713Sgirish miocack(wq, mp, 0, 0); 61244961713Sgirish break; 61344961713Sgirish 61444961713Sgirish case NXGE_GET64: 61544961713Sgirish nxge_get64(nxgep, mp->b_cont); 61644961713Sgirish miocack(wq, mp, sizeof (uint32_t), 0); 61744961713Sgirish break; 61844961713Sgirish 61944961713Sgirish case NXGE_PUT64: 62044961713Sgirish nxge_put64(nxgep, mp->b_cont); 62144961713Sgirish miocack(wq, mp, 0, 0); 62244961713Sgirish break; 62344961713Sgirish 62444961713Sgirish case NXGE_PUT_TCAM: 62544961713Sgirish nxge_put_tcam(nxgep, mp->b_cont); 62644961713Sgirish miocack(wq, mp, 0, 0); 62744961713Sgirish break; 62844961713Sgirish 62944961713Sgirish case NXGE_GET_TCAM: 63044961713Sgirish nxge_get_tcam(nxgep, mp->b_cont); 63144961713Sgirish miocack(wq, mp, 0, 0); 63244961713Sgirish break; 63344961713Sgirish 63444961713Sgirish case NXGE_TX_REGS_DUMP: 63544961713Sgirish nxge_txdma_regs_dump_channels(nxgep); 63644961713Sgirish miocack(wq, mp, 0, 0); 63744961713Sgirish break; 63844961713Sgirish case NXGE_RX_REGS_DUMP: 63944961713Sgirish nxge_rxdma_regs_dump_channels(nxgep); 64044961713Sgirish miocack(wq, mp, 0, 0); 64144961713Sgirish break; 64244961713Sgirish case NXGE_VIR_INT_REGS_DUMP: 64344961713Sgirish case NXGE_INT_REGS_DUMP: 64444961713Sgirish nxge_virint_regs_dump(nxgep); 64544961713Sgirish miocack(wq, mp, 0, 0); 64644961713Sgirish break; 64744961713Sgirish case NXGE_RTRACE: 64844961713Sgirish nxge_rtrace_ioctl(nxgep, wq, mp, iocp); 64944961713Sgirish break; 65044961713Sgirish } 65144961713Sgirish } 65244961713Sgirish 653a3c5bd6dSspeer /* ARGSUSED */ 65444961713Sgirish void 65544961713Sgirish nxge_loopback_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, 656a3c5bd6dSspeer struct iocblk *iocp) 65744961713Sgirish { 658a3c5bd6dSspeer p_lb_property_t lb_props; 659a3c5bd6dSspeer 660a3c5bd6dSspeer size_t size; 661a3c5bd6dSspeer int i; 66244961713Sgirish 66344961713Sgirish if (mp->b_cont == NULL) { 66444961713Sgirish miocnak(wq, mp, 0, EINVAL); 66544961713Sgirish } 66644961713Sgirish switch (iocp->ioc_cmd) { 66744961713Sgirish case LB_GET_MODE: 66844961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "NXGE_GET_LB_MODE command")); 66944961713Sgirish if (nxgep != NULL) { 67044961713Sgirish *(lb_info_sz_t *)mp->b_cont->b_rptr = 67152ccf843Smisaki nxgep->statsp->port_stats.lb_mode; 67244961713Sgirish miocack(wq, mp, sizeof (nxge_lb_t), 0); 673ee5416c9Syc } else { 67444961713Sgirish miocnak(wq, mp, 0, EINVAL); 675ee5416c9Syc } 67644961713Sgirish break; 67744961713Sgirish case LB_SET_MODE: 67844961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "NXGE_SET_LB_MODE command")); 67944961713Sgirish if (iocp->ioc_count != sizeof (uint32_t)) { 68044961713Sgirish miocack(wq, mp, 0, 0); 68144961713Sgirish break; 68244961713Sgirish } 68344961713Sgirish if ((nxgep != NULL) && nxge_set_lb(nxgep, wq, mp->b_cont)) { 68444961713Sgirish miocack(wq, mp, 0, 0); 68544961713Sgirish } else { 68644961713Sgirish miocnak(wq, mp, 0, EPROTO); 68744961713Sgirish } 68844961713Sgirish break; 68944961713Sgirish case LB_GET_INFO_SIZE: 69044961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "LB_GET_INFO_SIZE command")); 69144961713Sgirish if (nxgep != NULL) { 69244961713Sgirish size = sizeof (lb_normal); 69344961713Sgirish if (nxgep->statsp->mac_stats.cap_10gfdx) { 69400161856Syc /* TN1010 does not support external loopback */ 69500161856Syc if (nxgep->mac.portmode != PORT_1G_TN1010 && 69600161856Syc nxgep->mac.portmode != PORT_10G_TN1010) { 69700161856Syc size += sizeof (lb_external10g); 69800161856Syc } 69944961713Sgirish size += sizeof (lb_mac10g); 700936117e2Ssbehera /* Publish PHY loopback if PHY is present */ 701936117e2Ssbehera if (nxgep->mac.portmode == PORT_10G_COPPER || 70200161856Syc nxgep->mac.portmode == PORT_10G_TN1010 || 703936117e2Ssbehera nxgep->mac.portmode == PORT_10G_FIBER) 704936117e2Ssbehera size += sizeof (lb_phy10g); 70544961713Sgirish } 70600161856Syc 70700161856Syc /* 70800161856Syc * Even if cap_10gfdx is false, we still do 10G 70900161856Syc * serdes loopback as a part of SunVTS xnetlbtest 71000161856Syc * internal loopback test. 71100161856Syc */ 712936117e2Ssbehera if (nxgep->mac.portmode == PORT_10G_FIBER || 71389282175SSantwona Behera nxgep->mac.portmode == PORT_10G_COPPER || 71400161856Syc nxgep->mac.portmode == PORT_10G_TN1010 || 715936117e2Ssbehera nxgep->mac.portmode == PORT_10G_SERDES) 716936117e2Ssbehera size += sizeof (lb_serdes10g); 717936117e2Ssbehera 71844961713Sgirish if (nxgep->statsp->mac_stats.cap_1000fdx) { 71900161856Syc /* TN1010 does not support external loopback */ 72000161856Syc if (nxgep->mac.portmode != PORT_1G_TN1010 && 72100161856Syc nxgep->mac.portmode != PORT_10G_TN1010) { 72200161856Syc size += sizeof (lb_external1000); 72300161856Syc } 72444961713Sgirish size += sizeof (lb_mac1000); 7250cad6a5fSyc if (nxgep->mac.portmode == PORT_1G_COPPER || 72600161856Syc nxgep->mac.portmode == PORT_1G_TN1010 || 7270cad6a5fSyc nxgep->mac.portmode == 7280cad6a5fSyc PORT_1G_RGMII_FIBER) 72944961713Sgirish size += sizeof (lb_phy1000); 73044961713Sgirish } 73144961713Sgirish if (nxgep->statsp->mac_stats.cap_100fdx) 73244961713Sgirish size += sizeof (lb_external100); 73344961713Sgirish if (nxgep->statsp->mac_stats.cap_10fdx) 73444961713Sgirish size += sizeof (lb_external10); 735936117e2Ssbehera if (nxgep->mac.portmode == PORT_1G_FIBER || 73600161856Syc nxgep->mac.portmode == PORT_1G_TN1010 || 737936117e2Ssbehera nxgep->mac.portmode == PORT_1G_SERDES) 73844961713Sgirish size += sizeof (lb_serdes1000); 7392e59129aSraghus 74044961713Sgirish *(lb_info_sz_t *)mp->b_cont->b_rptr = size; 74144961713Sgirish 74244961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, 74352ccf843Smisaki "NXGE_GET_LB_INFO command: size %d", size)); 74444961713Sgirish miocack(wq, mp, sizeof (lb_info_sz_t), 0); 74544961713Sgirish } else 74644961713Sgirish miocnak(wq, mp, 0, EINVAL); 74744961713Sgirish break; 74844961713Sgirish 74944961713Sgirish case LB_GET_INFO: 75044961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "NXGE_GET_LB_INFO command")); 75144961713Sgirish if (nxgep != NULL) { 75244961713Sgirish size = sizeof (lb_normal); 75344961713Sgirish if (nxgep->statsp->mac_stats.cap_10gfdx) { 75400161856Syc /* TN1010 does not support external loopback */ 75500161856Syc if (nxgep->mac.portmode != PORT_1G_TN1010 && 75600161856Syc nxgep->mac.portmode != PORT_10G_TN1010) { 75700161856Syc size += sizeof (lb_external10g); 75800161856Syc } 75944961713Sgirish size += sizeof (lb_mac10g); 760936117e2Ssbehera /* Publish PHY loopback if PHY is present */ 761936117e2Ssbehera if (nxgep->mac.portmode == PORT_10G_COPPER || 76200161856Syc nxgep->mac.portmode == PORT_10G_TN1010 || 763936117e2Ssbehera nxgep->mac.portmode == PORT_10G_FIBER) 764936117e2Ssbehera size += sizeof (lb_phy10g); 76544961713Sgirish } 766936117e2Ssbehera if (nxgep->mac.portmode == PORT_10G_FIBER || 76789282175SSantwona Behera nxgep->mac.portmode == PORT_10G_COPPER || 76800161856Syc nxgep->mac.portmode == PORT_10G_TN1010 || 769936117e2Ssbehera nxgep->mac.portmode == PORT_10G_SERDES) 770936117e2Ssbehera size += sizeof (lb_serdes10g); 771936117e2Ssbehera 77244961713Sgirish if (nxgep->statsp->mac_stats.cap_1000fdx) { 77300161856Syc /* TN1010 does not support external loopback */ 77400161856Syc if (nxgep->mac.portmode != PORT_1G_TN1010 && 77500161856Syc nxgep->mac.portmode != PORT_10G_TN1010) { 77600161856Syc size += sizeof (lb_external1000); 77700161856Syc } 77844961713Sgirish size += sizeof (lb_mac1000); 7790cad6a5fSyc if (nxgep->mac.portmode == PORT_1G_COPPER || 78000161856Syc nxgep->mac.portmode == PORT_1G_TN1010 || 7810cad6a5fSyc nxgep->mac.portmode == 7820cad6a5fSyc PORT_1G_RGMII_FIBER) 78344961713Sgirish size += sizeof (lb_phy1000); 78444961713Sgirish } 78544961713Sgirish if (nxgep->statsp->mac_stats.cap_100fdx) 78644961713Sgirish size += sizeof (lb_external100); 78700161856Syc 78844961713Sgirish if (nxgep->statsp->mac_stats.cap_10fdx) 78944961713Sgirish size += sizeof (lb_external10); 79000161856Syc 791936117e2Ssbehera if (nxgep->mac.portmode == PORT_1G_FIBER || 79200161856Syc nxgep->mac.portmode == PORT_1G_TN1010 || 793936117e2Ssbehera nxgep->mac.portmode == PORT_1G_SERDES) 79444961713Sgirish size += sizeof (lb_serdes1000); 79544961713Sgirish 79644961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, 79752ccf843Smisaki "NXGE_GET_LB_INFO command: size %d", size)); 79844961713Sgirish if (size == iocp->ioc_count) { 79944961713Sgirish i = 0; 80044961713Sgirish lb_props = (p_lb_property_t)mp->b_cont->b_rptr; 80144961713Sgirish lb_props[i++] = lb_normal; 80200161856Syc 80344961713Sgirish if (nxgep->statsp->mac_stats.cap_10gfdx) { 80444961713Sgirish lb_props[i++] = lb_mac10g; 805936117e2Ssbehera if (nxgep->mac.portmode == 806936117e2Ssbehera PORT_10G_COPPER || 807936117e2Ssbehera nxgep->mac.portmode == 80800161856Syc PORT_10G_TN1010 || 80900161856Syc nxgep->mac.portmode == 81000161856Syc PORT_10G_FIBER) { 811936117e2Ssbehera lb_props[i++] = lb_phy10g; 81200161856Syc } 81300161856Syc /* TN1010 does not support ext lb */ 81400161856Syc if (nxgep->mac.portmode != 81500161856Syc PORT_10G_TN1010 && 81600161856Syc nxgep->mac.portmode != 81700161856Syc PORT_1G_TN1010) { 81800161856Syc lb_props[i++] = lb_external10g; 81900161856Syc } 82044961713Sgirish } 82100161856Syc 822936117e2Ssbehera if (nxgep->mac.portmode == PORT_10G_FIBER || 82389282175SSantwona Behera nxgep->mac.portmode == PORT_10G_COPPER || 82400161856Syc nxgep->mac.portmode == PORT_10G_TN1010 || 825936117e2Ssbehera nxgep->mac.portmode == PORT_10G_SERDES) 826936117e2Ssbehera lb_props[i++] = lb_serdes10g; 827936117e2Ssbehera 82800161856Syc if (nxgep->statsp->mac_stats.cap_1000fdx) { 82900161856Syc /* TN1010 does not support ext lb */ 83000161856Syc if (nxgep->mac.portmode != 83100161856Syc PORT_10G_TN1010 && 83200161856Syc nxgep->mac.portmode != 83300161856Syc PORT_1G_TN1010) { 83400161856Syc lb_props[i++] = lb_external1000; 83500161856Syc } 83600161856Syc } 83700161856Syc 83844961713Sgirish if (nxgep->statsp->mac_stats.cap_100fdx) 83944961713Sgirish lb_props[i++] = lb_external100; 84000161856Syc 84144961713Sgirish if (nxgep->statsp->mac_stats.cap_10fdx) 84244961713Sgirish lb_props[i++] = lb_external10; 84300161856Syc 84444961713Sgirish if (nxgep->statsp->mac_stats.cap_1000fdx) 84544961713Sgirish lb_props[i++] = lb_mac1000; 84600161856Syc 8470cad6a5fSyc if (nxgep->mac.portmode == PORT_1G_COPPER || 84800161856Syc nxgep->mac.portmode == PORT_1G_TN1010 || 8490cad6a5fSyc nxgep->mac.portmode == 8500cad6a5fSyc PORT_1G_RGMII_FIBER) { 85144961713Sgirish if (nxgep->statsp->mac_stats. 85252ccf843Smisaki cap_1000fdx) 85344961713Sgirish lb_props[i++] = lb_phy1000; 8540cad6a5fSyc } else if (nxgep->mac.portmode == 8550cad6a5fSyc PORT_1G_FIBER || 8560cad6a5fSyc nxgep->mac.portmode == PORT_1G_TN1010 || 8570cad6a5fSyc nxgep->mac.portmode == PORT_1G_SERDES) { 85844961713Sgirish lb_props[i++] = lb_serdes1000; 8592e59129aSraghus } 86044961713Sgirish miocack(wq, mp, size, 0); 86144961713Sgirish } else 86244961713Sgirish miocnak(wq, mp, 0, EINVAL); 86344961713Sgirish } else { 86444961713Sgirish miocnak(wq, mp, 0, EINVAL); 86544961713Sgirish cmn_err(CE_NOTE, "!nxge_hw_ioctl: invalid command 0x%x", 86652ccf843Smisaki iocp->ioc_cmd); 86744961713Sgirish } 86844961713Sgirish break; 86944961713Sgirish } 87044961713Sgirish } 87144961713Sgirish 87244961713Sgirish /* 87344961713Sgirish * DMA channel interfaces to access various channel specific 87444961713Sgirish * hardware functions. 87544961713Sgirish */ 876a3c5bd6dSspeer /* ARGSUSED */ 87744961713Sgirish void 87844961713Sgirish nxge_rxdma_channel_put64(nxge_os_acc_handle_t handle, void *reg_addrp, 879a3c5bd6dSspeer uint32_t reg_base, uint16_t channel, uint64_t reg_data) 88044961713Sgirish { 881a3c5bd6dSspeer uint64_t reg_offset; 88244961713Sgirish 88344961713Sgirish NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_put64")); 88444961713Sgirish 88544961713Sgirish /* 886a3c5bd6dSspeer * Channel is assumed to be from 0 to the maximum DMA channel #. If we 887a3c5bd6dSspeer * use the virtual DMA CSR address space from the config space (in PCI 888a3c5bd6dSspeer * case), then the following code need to be use different offset 88944961713Sgirish * computation macro. 89044961713Sgirish */ 89144961713Sgirish reg_offset = reg_base + DMC_OFFSET(channel); 89244961713Sgirish NXGE_PIO_WRITE64(handle, reg_addrp, reg_offset, reg_data); 89344961713Sgirish 89444961713Sgirish NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_put64")); 89544961713Sgirish } 89644961713Sgirish 897a3c5bd6dSspeer /* ARGSUSED */ 89844961713Sgirish uint64_t 89944961713Sgirish nxge_rxdma_channel_get64(nxge_os_acc_handle_t handle, void *reg_addrp, 900a3c5bd6dSspeer uint32_t reg_base, uint16_t channel) 90144961713Sgirish { 902a3c5bd6dSspeer uint64_t reg_offset; 90344961713Sgirish 90444961713Sgirish NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_get64")); 90544961713Sgirish 90644961713Sgirish /* 907a3c5bd6dSspeer * Channel is assumed to be from 0 to the maximum DMA channel #. If we 908a3c5bd6dSspeer * use the virtual DMA CSR address space from the config space (in PCI 909a3c5bd6dSspeer * case), then the following code need to be use different offset 91044961713Sgirish * computation macro. 91144961713Sgirish */ 91244961713Sgirish reg_offset = reg_base + DMC_OFFSET(channel); 91344961713Sgirish 91444961713Sgirish NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_get64")); 91544961713Sgirish 91644961713Sgirish return (NXGE_PIO_READ64(handle, reg_addrp, reg_offset)); 91744961713Sgirish } 91844961713Sgirish 919a3c5bd6dSspeer /* ARGSUSED */ 92044961713Sgirish void 92144961713Sgirish nxge_get32(p_nxge_t nxgep, p_mblk_t mp) 92244961713Sgirish { 923a3c5bd6dSspeer nxge_os_acc_handle_t nxge_regh; 92444961713Sgirish 92544961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_get32")); 92644961713Sgirish nxge_regh = nxgep->dev_regs->nxge_regh; 92744961713Sgirish 92844961713Sgirish *(uint32_t *)mp->b_rptr = NXGE_PIO_READ32(nxge_regh, 92952ccf843Smisaki nxgep->dev_regs->nxge_regp, *(uint32_t *)mp->b_rptr); 93044961713Sgirish 93144961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "value = 0x%08X", 93252ccf843Smisaki *(uint32_t *)mp->b_rptr)); 93344961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_get32")); 93444961713Sgirish } 93544961713Sgirish 936a3c5bd6dSspeer /* ARGSUSED */ 93744961713Sgirish void 93844961713Sgirish nxge_put32(p_nxge_t nxgep, p_mblk_t mp) 93944961713Sgirish { 94044961713Sgirish nxge_os_acc_handle_t nxge_regh; 94144961713Sgirish uint32_t *buf; 94244961713Sgirish uint8_t *reg; 94344961713Sgirish 94444961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_put32")); 94544961713Sgirish nxge_regh = nxgep->dev_regs->nxge_regh; 94644961713Sgirish 94744961713Sgirish buf = (uint32_t *)mp->b_rptr; 94844961713Sgirish reg = (uint8_t *)(nxgep->dev_regs->nxge_regp) + buf[0]; 94944961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, 95052ccf843Smisaki "reg = 0x%016llX index = 0x%08X value = 0x%08X", 95152ccf843Smisaki reg, buf[0], buf[1])); 95244961713Sgirish NXGE_PIO_WRITE32(nxge_regh, (uint32_t *)reg, 0, buf[1]); 95344961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_put32")); 95444961713Sgirish } 95544961713Sgirish 95644961713Sgirish /*ARGSUSED*/ 95744961713Sgirish boolean_t 95844961713Sgirish nxge_set_lb(p_nxge_t nxgep, queue_t *wq, p_mblk_t mp) 95944961713Sgirish { 960a3c5bd6dSspeer boolean_t status = B_TRUE; 961a3c5bd6dSspeer uint32_t lb_mode; 962a3c5bd6dSspeer lb_property_t *lb_info; 96344961713Sgirish 96444961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_set_lb")); 96544961713Sgirish lb_mode = nxgep->statsp->port_stats.lb_mode; 96644961713Sgirish if (lb_mode == *(uint32_t *)mp->b_rptr) { 96744961713Sgirish cmn_err(CE_NOTE, 96852ccf843Smisaki "!nxge%d: Loopback mode already set (lb_mode %d).\n", 96952ccf843Smisaki nxgep->instance, lb_mode); 97044961713Sgirish status = B_FALSE; 97144961713Sgirish goto nxge_set_lb_exit; 97244961713Sgirish } 97344961713Sgirish lb_mode = *(uint32_t *)mp->b_rptr; 97444961713Sgirish lb_info = NULL; 97544961713Sgirish if (lb_mode == lb_normal.value) 97644961713Sgirish lb_info = &lb_normal; 97744961713Sgirish else if ((lb_mode == lb_external10g.value) && 97852ccf843Smisaki (nxgep->statsp->mac_stats.cap_10gfdx)) 97944961713Sgirish lb_info = &lb_external10g; 98044961713Sgirish else if ((lb_mode == lb_external1000.value) && 98152ccf843Smisaki (nxgep->statsp->mac_stats.cap_1000fdx)) 98244961713Sgirish lb_info = &lb_external1000; 98344961713Sgirish else if ((lb_mode == lb_external100.value) && 98452ccf843Smisaki (nxgep->statsp->mac_stats.cap_100fdx)) 98544961713Sgirish lb_info = &lb_external100; 98644961713Sgirish else if ((lb_mode == lb_external10.value) && 98752ccf843Smisaki (nxgep->statsp->mac_stats.cap_10fdx)) 98844961713Sgirish lb_info = &lb_external10; 98944961713Sgirish else if ((lb_mode == lb_phy10g.value) && 9900cad6a5fSyc (nxgep->mac.portmode == PORT_10G_COPPER || 9910cad6a5fSyc nxgep->mac.portmode == PORT_10G_TN1010 || 9920cad6a5fSyc nxgep->mac.portmode == PORT_10G_FIBER)) 99344961713Sgirish lb_info = &lb_phy10g; 99444961713Sgirish else if ((lb_mode == lb_phy1000.value) && 9950cad6a5fSyc (nxgep->mac.portmode == PORT_1G_COPPER || 9960cad6a5fSyc nxgep->mac.portmode == PORT_1G_TN1010 || 9970cad6a5fSyc nxgep->mac.portmode == PORT_1G_RGMII_FIBER)) 99844961713Sgirish lb_info = &lb_phy1000; 99944961713Sgirish else if ((lb_mode == lb_phy.value) && 100052ccf843Smisaki (nxgep->mac.portmode == PORT_1G_COPPER)) 100144961713Sgirish lb_info = &lb_phy; 100244961713Sgirish else if ((lb_mode == lb_serdes10g.value) && 10030cad6a5fSyc (nxgep->mac.portmode == PORT_10G_FIBER || 10040cad6a5fSyc nxgep->mac.portmode == PORT_10G_COPPER || 10050cad6a5fSyc nxgep->mac.portmode == PORT_10G_TN1010 || 10060cad6a5fSyc nxgep->mac.portmode == PORT_10G_SERDES)) 100744961713Sgirish lb_info = &lb_serdes10g; 100844961713Sgirish else if ((lb_mode == lb_serdes1000.value) && 10090cad6a5fSyc (nxgep->mac.portmode == PORT_1G_FIBER || 10100cad6a5fSyc nxgep->mac.portmode == PORT_1G_TN1010 || 10110cad6a5fSyc nxgep->mac.portmode == PORT_1G_SERDES)) 101244961713Sgirish lb_info = &lb_serdes1000; 101344961713Sgirish else if (lb_mode == lb_mac10g.value) 101444961713Sgirish lb_info = &lb_mac10g; 101544961713Sgirish else if (lb_mode == lb_mac1000.value) 101644961713Sgirish lb_info = &lb_mac1000; 101744961713Sgirish else if (lb_mode == lb_mac.value) 101844961713Sgirish lb_info = &lb_mac; 101944961713Sgirish else { 102044961713Sgirish cmn_err(CE_NOTE, 102152ccf843Smisaki "!nxge%d: Loopback mode not supported(mode %d).\n", 102252ccf843Smisaki nxgep->instance, lb_mode); 102344961713Sgirish status = B_FALSE; 102444961713Sgirish goto nxge_set_lb_exit; 102544961713Sgirish } 102644961713Sgirish 102744961713Sgirish if (lb_mode == nxge_lb_normal) { 102844961713Sgirish if (nxge_lb_dbg) { 102944961713Sgirish cmn_err(CE_NOTE, 103052ccf843Smisaki "!nxge%d: Returning to normal operation", 103152ccf843Smisaki nxgep->instance); 103244961713Sgirish } 1033321febdeSsbehera if (nxge_set_lb_normal(nxgep) != NXGE_OK) { 1034321febdeSsbehera status = B_FALSE; 1035321febdeSsbehera cmn_err(CE_NOTE, 1036321febdeSsbehera "!nxge%d: Failed to return to normal operation", 1037321febdeSsbehera nxgep->instance); 1038321febdeSsbehera } 103944961713Sgirish goto nxge_set_lb_exit; 104044961713Sgirish } 104144961713Sgirish nxgep->statsp->port_stats.lb_mode = lb_mode; 104244961713Sgirish 104344961713Sgirish if (nxge_lb_dbg) 104444961713Sgirish cmn_err(CE_NOTE, 104552ccf843Smisaki "!nxge%d: Adapter now in %s loopback mode", 104652ccf843Smisaki nxgep->instance, lb_info->key); 104744961713Sgirish nxgep->param_arr[param_autoneg].value = 0; 104844961713Sgirish nxgep->param_arr[param_anar_10gfdx].value = 104952ccf843Smisaki (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10g) || 105052ccf843Smisaki (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac10g) || 105152ccf843Smisaki (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy10g) || 105252ccf843Smisaki (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes10g); 105344961713Sgirish nxgep->param_arr[param_anar_10ghdx].value = 0; 105444961713Sgirish nxgep->param_arr[param_anar_1000fdx].value = 105552ccf843Smisaki (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext1000) || 105652ccf843Smisaki (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac1000) || 105752ccf843Smisaki (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy1000) || 105852ccf843Smisaki (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes1000); 105944961713Sgirish nxgep->param_arr[param_anar_1000hdx].value = 0; 106044961713Sgirish nxgep->param_arr[param_anar_100fdx].value = 106152ccf843Smisaki (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy) || 106252ccf843Smisaki (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac) || 106352ccf843Smisaki (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext100); 106444961713Sgirish nxgep->param_arr[param_anar_100hdx].value = 0; 106544961713Sgirish nxgep->param_arr[param_anar_10fdx].value = 106652ccf843Smisaki (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac) || 106752ccf843Smisaki (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10); 106844961713Sgirish if (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext1000) { 106944961713Sgirish nxgep->param_arr[param_master_cfg_enable].value = 1; 107044961713Sgirish nxgep->param_arr[param_master_cfg_value].value = 1; 107144961713Sgirish } 107244961713Sgirish if ((nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10g) || 107352ccf843Smisaki (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext1000) || 107452ccf843Smisaki (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext100) || 107552ccf843Smisaki (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10) || 107652ccf843Smisaki (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy10g) || 107752ccf843Smisaki (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy1000) || 107852ccf843Smisaki (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy)) { 107944961713Sgirish 1080321febdeSsbehera if (nxge_link_monitor(nxgep, LINK_MONITOR_STOP) != NXGE_OK) 1081321febdeSsbehera goto nxge_set_lb_err; 1082321febdeSsbehera if (nxge_xcvr_find(nxgep) != NXGE_OK) 1083321febdeSsbehera goto nxge_set_lb_err; 1084321febdeSsbehera if (nxge_link_init(nxgep) != NXGE_OK) 1085321febdeSsbehera goto nxge_set_lb_err; 1086321febdeSsbehera if (nxge_link_monitor(nxgep, LINK_MONITOR_START) != NXGE_OK) 1087321febdeSsbehera goto nxge_set_lb_err; 108844961713Sgirish } 108944961713Sgirish if (lb_info->lb_type == internal) { 109044961713Sgirish if ((nxgep->statsp->port_stats.lb_mode == nxge_lb_mac10g) || 109152ccf843Smisaki (nxgep->statsp->port_stats.lb_mode == 109252ccf843Smisaki nxge_lb_phy10g) || 109352ccf843Smisaki (nxgep->statsp->port_stats.lb_mode == 109452ccf843Smisaki nxge_lb_serdes10g)) { 109544961713Sgirish nxgep->statsp->mac_stats.link_speed = 10000; 1096a3c5bd6dSspeer } else if ((nxgep->statsp->port_stats.lb_mode 109752ccf843Smisaki == nxge_lb_mac1000) || 109852ccf843Smisaki (nxgep->statsp->port_stats.lb_mode == 109952ccf843Smisaki nxge_lb_phy1000) || 110052ccf843Smisaki (nxgep->statsp->port_stats.lb_mode == 110152ccf843Smisaki nxge_lb_serdes1000)) { 110244961713Sgirish nxgep->statsp->mac_stats.link_speed = 1000; 110344961713Sgirish } else { 110444961713Sgirish nxgep->statsp->mac_stats.link_speed = 100; 110544961713Sgirish } 110644961713Sgirish nxgep->statsp->mac_stats.link_duplex = 2; 110744961713Sgirish nxgep->statsp->mac_stats.link_up = 1; 110844961713Sgirish } 1109321febdeSsbehera if (nxge_global_reset(nxgep) != NXGE_OK) 1110321febdeSsbehera goto nxge_set_lb_err; 111144961713Sgirish 111244961713Sgirish nxge_set_lb_exit: 111344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 111452ccf843Smisaki "<== nxge_set_lb status = 0x%08x", status)); 111544961713Sgirish return (status); 1116321febdeSsbehera nxge_set_lb_err: 1117321febdeSsbehera status = B_FALSE; 1118321febdeSsbehera cmn_err(CE_NOTE, 1119321febdeSsbehera "!nxge%d: Failed to put adapter in %s loopback mode", 1120321febdeSsbehera nxgep->instance, lb_info->key); 1121321febdeSsbehera return (status); 112244961713Sgirish } 112344961713Sgirish 112400161856Syc /* Return to normal (no loopback) mode */ 1125a3c5bd6dSspeer /* ARGSUSED */ 1126321febdeSsbehera nxge_status_t 112744961713Sgirish nxge_set_lb_normal(p_nxge_t nxgep) 112844961713Sgirish { 1129321febdeSsbehera nxge_status_t status = NXGE_OK; 1130321febdeSsbehera 113144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_set_lb_normal")); 1132321febdeSsbehera 113344961713Sgirish nxgep->statsp->port_stats.lb_mode = nxge_lb_normal; 113444961713Sgirish nxgep->param_arr[param_autoneg].value = 113552ccf843Smisaki nxgep->param_arr[param_autoneg].old_value; 113644961713Sgirish nxgep->param_arr[param_anar_1000fdx].value = 113752ccf843Smisaki nxgep->param_arr[param_anar_1000fdx].old_value; 113844961713Sgirish nxgep->param_arr[param_anar_1000hdx].value = 113952ccf843Smisaki nxgep->param_arr[param_anar_1000hdx].old_value; 114044961713Sgirish nxgep->param_arr[param_anar_100fdx].value = 114152ccf843Smisaki nxgep->param_arr[param_anar_100fdx].old_value; 114244961713Sgirish nxgep->param_arr[param_anar_100hdx].value = 114352ccf843Smisaki nxgep->param_arr[param_anar_100hdx].old_value; 114444961713Sgirish nxgep->param_arr[param_anar_10fdx].value = 114552ccf843Smisaki nxgep->param_arr[param_anar_10fdx].old_value; 114644961713Sgirish nxgep->param_arr[param_master_cfg_enable].value = 114752ccf843Smisaki nxgep->param_arr[param_master_cfg_enable].old_value; 114844961713Sgirish nxgep->param_arr[param_master_cfg_value].value = 114952ccf843Smisaki nxgep->param_arr[param_master_cfg_value].old_value; 115044961713Sgirish 1151321febdeSsbehera if ((status = nxge_global_reset(nxgep)) != NXGE_OK) 1152321febdeSsbehera return (status); 115344961713Sgirish 1154321febdeSsbehera if ((status = nxge_link_monitor(nxgep, LINK_MONITOR_STOP)) != NXGE_OK) 1155321febdeSsbehera return (status); 1156321febdeSsbehera if ((status = nxge_xcvr_find(nxgep)) != NXGE_OK) 1157321febdeSsbehera return (status); 1158321febdeSsbehera if ((status = nxge_link_init(nxgep)) != NXGE_OK) 1159321febdeSsbehera return (status); 1160321febdeSsbehera status = nxge_link_monitor(nxgep, LINK_MONITOR_START); 116144961713Sgirish 116244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_set_lb_normal")); 1163321febdeSsbehera 1164321febdeSsbehera return (status); 116544961713Sgirish } 116644961713Sgirish 1167a3c5bd6dSspeer /* ARGSUSED */ 116844961713Sgirish void 116944961713Sgirish nxge_get_mii(p_nxge_t nxgep, p_mblk_t mp) 117044961713Sgirish { 117144961713Sgirish uint16_t reg; 117244961713Sgirish 117344961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_get_mii")); 117444961713Sgirish 117544961713Sgirish reg = *(uint16_t *)mp->b_rptr; 117644961713Sgirish (void) nxge_mii_read(nxgep, nxgep->statsp->mac_stats.xcvr_portn, reg, 117752ccf843Smisaki (uint16_t *)mp->b_rptr); 117844961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "reg = 0x%08X value = 0x%04X", 117952ccf843Smisaki reg, *(uint16_t *)mp->b_rptr)); 118044961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_get_mii")); 118144961713Sgirish } 118244961713Sgirish 1183a3c5bd6dSspeer /* ARGSUSED */ 118444961713Sgirish void 118544961713Sgirish nxge_put_mii(p_nxge_t nxgep, p_mblk_t mp) 118644961713Sgirish { 118744961713Sgirish uint16_t *buf; 118844961713Sgirish uint8_t reg; 118944961713Sgirish 119044961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_put_mii")); 119144961713Sgirish buf = (uint16_t *)mp->b_rptr; 119244961713Sgirish reg = (uint8_t)buf[0]; 119344961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, 119452ccf843Smisaki "reg = 0x%08X index = 0x%08X value = 0x%08X", 119552ccf843Smisaki reg, buf[0], buf[1])); 119644961713Sgirish (void) nxge_mii_write(nxgep, nxgep->statsp->mac_stats.xcvr_portn, 119752ccf843Smisaki reg, buf[1]); 119844961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_put_mii")); 119944961713Sgirish } 120044961713Sgirish 1201a3c5bd6dSspeer /* ARGSUSED */ 120244961713Sgirish void 120344961713Sgirish nxge_check_hw_state(p_nxge_t nxgep) 120444961713Sgirish { 1205a3c5bd6dSspeer p_nxge_ldgv_t ldgvp; 1206a3c5bd6dSspeer p_nxge_ldv_t t_ldvp; 120744961713Sgirish 120844961713Sgirish NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "==> nxge_check_hw_state")); 120944961713Sgirish 121014ea4bb7Ssd MUTEX_ENTER(nxgep->genlock); 121114ea4bb7Ssd nxgep->nxge_timerid = 0; 121214ea4bb7Ssd if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 121314ea4bb7Ssd goto nxge_check_hw_state_exit; 121414ea4bb7Ssd } 121544961713Sgirish nxge_check_tx_hang(nxgep); 121644961713Sgirish 121744961713Sgirish ldgvp = nxgep->ldgvp; 121844961713Sgirish if (ldgvp == NULL || (ldgvp->ldvp_syserr == NULL)) { 121944961713Sgirish NXGE_ERROR_MSG((nxgep, SYSERR_CTL, "<== nxge_check_hw_state: " 122052ccf843Smisaki "NULL ldgvp (interrupt not ready).")); 122114ea4bb7Ssd goto nxge_check_hw_state_exit; 122244961713Sgirish } 122344961713Sgirish t_ldvp = ldgvp->ldvp_syserr; 122444961713Sgirish if (!t_ldvp->use_timer) { 122544961713Sgirish NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "<== nxge_check_hw_state: " 122652ccf843Smisaki "ldgvp $%p t_ldvp $%p use_timer flag %d", 122752ccf843Smisaki ldgvp, t_ldvp, t_ldvp->use_timer)); 122814ea4bb7Ssd goto nxge_check_hw_state_exit; 122914ea4bb7Ssd } 123014ea4bb7Ssd if (fm_check_acc_handle(nxgep->dev_regs->nxge_regh) != DDI_FM_OK) { 123114ea4bb7Ssd NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 123252ccf843Smisaki "port%d Bad register acc handle", nxgep->mac.portnum)); 123344961713Sgirish } 1234a3c5bd6dSspeer (void) nxge_syserr_intr((void *) t_ldvp, (void *) nxgep); 123544961713Sgirish 123644961713Sgirish nxgep->nxge_timerid = nxge_start_timer(nxgep, nxge_check_hw_state, 123752ccf843Smisaki NXGE_CHECK_TIMER); 123844961713Sgirish 123914ea4bb7Ssd nxge_check_hw_state_exit: 124014ea4bb7Ssd MUTEX_EXIT(nxgep->genlock); 124144961713Sgirish NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "<== nxge_check_hw_state")); 124244961713Sgirish } 124344961713Sgirish 124444961713Sgirish /*ARGSUSED*/ 124544961713Sgirish static void 1246a3c5bd6dSspeer nxge_rtrace_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, 1247a3c5bd6dSspeer struct iocblk *iocp) 124844961713Sgirish { 1249a3c5bd6dSspeer ssize_t size; 1250a3c5bd6dSspeer rtrace_t *rtp; 1251a3c5bd6dSspeer mblk_t *nmp; 1252a3c5bd6dSspeer uint32_t i, j; 1253a3c5bd6dSspeer uint32_t start_blk; 1254a3c5bd6dSspeer uint32_t base_entry; 1255a3c5bd6dSspeer uint32_t num_entries; 125644961713Sgirish 125744961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_rtrace_ioctl")); 125844961713Sgirish 125944961713Sgirish size = 1024; 126044961713Sgirish if (mp->b_cont == NULL || MBLKL(mp->b_cont) < size) { 126144961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, 126252ccf843Smisaki "malformed M_IOCTL MBLKL = %d size = %d", 126352ccf843Smisaki MBLKL(mp->b_cont), size)); 126444961713Sgirish miocnak(wq, mp, 0, EINVAL); 126544961713Sgirish return; 126644961713Sgirish } 126744961713Sgirish nmp = mp->b_cont; 126844961713Sgirish rtp = (rtrace_t *)nmp->b_rptr; 126944961713Sgirish start_blk = rtp->next_idx; 127044961713Sgirish num_entries = rtp->last_idx; 127144961713Sgirish base_entry = start_blk * MAX_RTRACE_IOC_ENTRIES; 127244961713Sgirish 127344961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "start_blk = %d\n", start_blk)); 127444961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "num_entries = %d\n", num_entries)); 127544961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "base_entry = %d\n", base_entry)); 127644961713Sgirish 127744961713Sgirish rtp->next_idx = npi_rtracebuf.next_idx; 127844961713Sgirish rtp->last_idx = npi_rtracebuf.last_idx; 127944961713Sgirish rtp->wrapped = npi_rtracebuf.wrapped; 128044961713Sgirish for (i = 0, j = base_entry; i < num_entries; i++, j++) { 128144961713Sgirish rtp->buf[i].ctl_addr = npi_rtracebuf.buf[j].ctl_addr; 128244961713Sgirish rtp->buf[i].val_l32 = npi_rtracebuf.buf[j].val_l32; 128344961713Sgirish rtp->buf[i].val_h32 = npi_rtracebuf.buf[j].val_h32; 128444961713Sgirish } 128544961713Sgirish 128644961713Sgirish nmp->b_wptr = nmp->b_rptr + size; 128744961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "<== nxge_rtrace_ioctl")); 128844961713Sgirish miocack(wq, mp, (int)size, 0); 128944961713Sgirish } 1290