144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 22a3c5bd6dSspeer * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 2344961713Sgirish * Use is subject to license terms. 2444961713Sgirish */ 2544961713Sgirish 2644961713Sgirish #pragma ident "%Z%%M% %I% %E% SMI" 2744961713Sgirish 28a3c5bd6dSspeer #include <sys/nxge/nxge_impl.h> 2944961713Sgirish 3044961713Sgirish /* 3144961713Sgirish * Tunable Receive Completion Ring Configuration B parameters. 3244961713Sgirish */ 33a3c5bd6dSspeer uint16_t nxge_rx_pkt_thres; /* 16 bits */ 34a3c5bd6dSspeer uint8_t nxge_rx_pkt_timeout; /* 6 bits based on DMA clock divider */ 35a3c5bd6dSspeer 36a3c5bd6dSspeer lb_property_t lb_normal = {normal, "normal", nxge_lb_normal}; 37a3c5bd6dSspeer lb_property_t lb_external10g = {external, "external10g", nxge_lb_ext10g}; 38a3c5bd6dSspeer lb_property_t lb_external1000 = {external, "external1000", nxge_lb_ext1000}; 39a3c5bd6dSspeer lb_property_t lb_external100 = {external, "external100", nxge_lb_ext100}; 40a3c5bd6dSspeer lb_property_t lb_external10 = {external, "external10", nxge_lb_ext10}; 41a3c5bd6dSspeer lb_property_t lb_phy10g = {internal, "phy10g", nxge_lb_phy10g}; 42a3c5bd6dSspeer lb_property_t lb_phy1000 = {internal, "phy1000", nxge_lb_phy1000}; 43a3c5bd6dSspeer lb_property_t lb_phy = {internal, "phy", nxge_lb_phy}; 44a3c5bd6dSspeer lb_property_t lb_serdes10g = {internal, "serdes10g", nxge_lb_serdes10g}; 45a3c5bd6dSspeer lb_property_t lb_serdes1000 = {internal, "serdes", nxge_lb_serdes1000}; 46a3c5bd6dSspeer lb_property_t lb_mac10g = {internal, "mac10g", nxge_lb_mac10g}; 47a3c5bd6dSspeer lb_property_t lb_mac1000 = {internal, "mac1000", nxge_lb_mac1000}; 48a3c5bd6dSspeer lb_property_t lb_mac = {internal, "mac10/100", nxge_lb_mac}; 4944961713Sgirish 5044961713Sgirish uint32_t nxge_lb_dbg = 1; 5144961713Sgirish void nxge_get_mii(p_nxge_t nxgep, p_mblk_t mp); 5244961713Sgirish void nxge_put_mii(p_nxge_t nxgep, p_mblk_t mp); 5344961713Sgirish 5444961713Sgirish extern uint32_t nxge_rx_mode; 55a3c5bd6dSspeer extern uint32_t nxge_jumbo_mtu; 56a3c5bd6dSspeer extern boolean_t nxge_jumbo_enable; 5744961713Sgirish 58a3c5bd6dSspeer static void 59a3c5bd6dSspeer nxge_rtrace_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 6044961713Sgirish 61a3c5bd6dSspeer /* ARGSUSED */ 6244961713Sgirish void 6344961713Sgirish nxge_global_reset(p_nxge_t nxgep) 6444961713Sgirish { 6544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_global_reset")); 6644961713Sgirish 6744961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 6844961713Sgirish (void) nxge_intr_hw_disable(nxgep); 6944961713Sgirish 7044961713Sgirish if ((nxgep->suspended) || 71a3c5bd6dSspeer ((nxgep->statsp->port_stats.lb_mode == 72a3c5bd6dSspeer nxge_lb_phy1000) || 73a3c5bd6dSspeer (nxgep->statsp->port_stats.lb_mode == 74a3c5bd6dSspeer nxge_lb_phy10g) || 75a3c5bd6dSspeer (nxgep->statsp->port_stats.lb_mode == 76a3c5bd6dSspeer nxge_lb_serdes1000) || 77a3c5bd6dSspeer (nxgep->statsp->port_stats.lb_mode == 78a3c5bd6dSspeer nxge_lb_serdes10g))) { 7944961713Sgirish (void) nxge_link_init(nxgep); 8044961713Sgirish } 8144961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 8244961713Sgirish (void) nxge_mac_init(nxgep); 8344961713Sgirish (void) nxge_intr_hw_enable(nxgep); 8444961713Sgirish 8544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_global_reset")); 8644961713Sgirish } 8744961713Sgirish 88a3c5bd6dSspeer /* ARGSUSED */ 8944961713Sgirish void 9044961713Sgirish nxge_hw_id_init(p_nxge_t nxgep) 9144961713Sgirish { 9244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_id_init")); 9344961713Sgirish /* 9444961713Sgirish * Set up initial hardware parameters required such as mac mtu size. 9544961713Sgirish */ 9644961713Sgirish nxgep->mac.is_jumbo = B_FALSE; 97a3c5bd6dSspeer nxgep->mac.maxframesize = NXGE_MTU_DEFAULT_MAX; /* 1522 */ 9814ea4bb7Ssd if (nxgep->param_arr[param_accept_jumbo].value || nxge_jumbo_enable) { 9914ea4bb7Ssd nxgep->mac.maxframesize = (uint16_t)nxge_jumbo_mtu; 10044961713Sgirish nxgep->mac.is_jumbo = B_TRUE; 10144961713Sgirish } 10244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 10344961713Sgirish "==> nxge_hw_id_init: maxframesize %d", 10444961713Sgirish nxgep->mac.maxframesize)); 10544961713Sgirish 10644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_id_init")); 10744961713Sgirish } 10844961713Sgirish 109a3c5bd6dSspeer /* ARGSUSED */ 11044961713Sgirish void 11144961713Sgirish nxge_hw_init_niu_common(p_nxge_t nxgep) 11244961713Sgirish { 113a3c5bd6dSspeer p_nxge_hw_list_t hw_p; 11444961713Sgirish 11544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_init_niu_common")); 11644961713Sgirish 11744961713Sgirish if ((hw_p = nxgep->nxge_hw_p) == NULL) { 11844961713Sgirish return; 11944961713Sgirish } 12044961713Sgirish MUTEX_ENTER(&hw_p->nxge_cfg_lock); 12144961713Sgirish if (hw_p->flags & COMMON_INIT_DONE) { 12244961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 12344961713Sgirish "nxge_hw_init_niu_common" 12444961713Sgirish " already done for dip $%p function %d exiting", 125a3c5bd6dSspeer hw_p->parent_devp, nxgep->function_num)); 12644961713Sgirish MUTEX_EXIT(&hw_p->nxge_cfg_lock); 12744961713Sgirish return; 12844961713Sgirish } 12944961713Sgirish 13044961713Sgirish hw_p->flags = COMMON_INIT_START; 13144961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, "nxge_hw_init_niu_common" 13244961713Sgirish " Started for device id %x with function %d", 133a3c5bd6dSspeer hw_p->parent_devp, nxgep->function_num)); 134a3c5bd6dSspeer 135a3c5bd6dSspeer /* per neptune common block init */ 136a3c5bd6dSspeer (void) nxge_fflp_hw_reset(nxgep); 13744961713Sgirish 13844961713Sgirish hw_p->flags = COMMON_INIT_DONE; 13944961713Sgirish MUTEX_EXIT(&hw_p->nxge_cfg_lock); 14044961713Sgirish 14144961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, "nxge_hw_init_niu_common" 14244961713Sgirish " Done for device id %x with function %d", 143a3c5bd6dSspeer hw_p->parent_devp, nxgep->function_num)); 14444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_init_niu_common")); 14544961713Sgirish } 14644961713Sgirish 147a3c5bd6dSspeer /* ARGSUSED */ 14844961713Sgirish uint_t 14944961713Sgirish nxge_intr(void *arg1, void *arg2) 15044961713Sgirish { 151a3c5bd6dSspeer p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 152a3c5bd6dSspeer p_nxge_t nxgep = (p_nxge_t)arg2; 153a3c5bd6dSspeer uint_t serviced = DDI_INTR_UNCLAIMED; 154a3c5bd6dSspeer uint8_t ldv; 155a3c5bd6dSspeer npi_handle_t handle; 156a3c5bd6dSspeer p_nxge_ldgv_t ldgvp; 157a3c5bd6dSspeer p_nxge_ldg_t ldgp, t_ldgp; 158a3c5bd6dSspeer p_nxge_ldv_t t_ldvp; 159a3c5bd6dSspeer uint64_t vector0 = 0, vector1 = 0, vector2 = 0; 160a3c5bd6dSspeer int i, j, nldvs, nintrs = 1; 161a3c5bd6dSspeer npi_status_t rs = NPI_SUCCESS; 16244961713Sgirish 16344961713Sgirish /* DDI interface returns second arg as NULL (n2 niumx driver) !!! */ 164a3c5bd6dSspeer if (arg2 == NULL || (void *) ldvp->nxgep != arg2) { 16544961713Sgirish nxgep = ldvp->nxgep; 16644961713Sgirish } 16744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr")); 16844961713Sgirish 16944961713Sgirish if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 17044961713Sgirish NXGE_ERROR_MSG((nxgep, INT_CTL, 171a3c5bd6dSspeer "<== nxge_intr: not initialized 0x%x", serviced)); 17244961713Sgirish return (serviced); 17344961713Sgirish } 17444961713Sgirish 17544961713Sgirish ldgvp = nxgep->ldgvp; 176a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: ldgvp $%p", ldgvp)); 17744961713Sgirish if (ldvp == NULL && ldgvp) { 17844961713Sgirish t_ldvp = ldvp = ldgvp->ldvp; 17944961713Sgirish } 18044961713Sgirish if (ldvp) { 18144961713Sgirish ldgp = t_ldgp = ldvp->ldgp; 18244961713Sgirish } 18344961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: " 184a3c5bd6dSspeer "ldgvp $%p ldvp $%p ldgp $%p", ldgvp, ldvp, ldgp)); 18544961713Sgirish if (ldgvp == NULL || ldvp == NULL || ldgp == NULL) { 18644961713Sgirish NXGE_ERROR_MSG((nxgep, INT_CTL, "==> nxge_intr: " 187a3c5bd6dSspeer "ldgvp $%p ldvp $%p ldgp $%p", ldgvp, ldvp, ldgp)); 18844961713Sgirish NXGE_ERROR_MSG((nxgep, INT_CTL, "<== nxge_intr: not ready")); 18944961713Sgirish return (DDI_INTR_UNCLAIMED); 19044961713Sgirish } 19144961713Sgirish /* 192a3c5bd6dSspeer * This interrupt handler will have to go through all the logical 193a3c5bd6dSspeer * devices to find out which logical device interrupts us and then call 19444961713Sgirish * its handler to process the events. 19544961713Sgirish */ 19644961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 19744961713Sgirish t_ldgp = ldgp; 19844961713Sgirish t_ldvp = ldgp->ldvp; 19944961713Sgirish 20044961713Sgirish nldvs = ldgp->nldvs; 20144961713Sgirish 20244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: #ldvs %d #intrs %d", 203a3c5bd6dSspeer nldvs, ldgvp->ldg_intrs)); 20444961713Sgirish 20544961713Sgirish serviced = DDI_INTR_CLAIMED; 20644961713Sgirish for (i = 0; i < nintrs; i++, t_ldgp++) { 20744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr(%d): #ldvs %d " 208a3c5bd6dSspeer " #intrs %d", i, nldvs, nintrs)); 20944961713Sgirish /* Get this group's flag bits. */ 21044961713Sgirish t_ldgp->interrupted = B_FALSE; 21144961713Sgirish rs = npi_ldsv_ldfs_get(handle, t_ldgp->ldg, 212a3c5bd6dSspeer &vector0, &vector1, &vector2); 21344961713Sgirish if (rs) { 21444961713Sgirish continue; 21544961713Sgirish } 21644961713Sgirish if (!vector0 && !vector1 && !vector2) { 21744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: " 21844961713Sgirish "no interrupts on group %d", t_ldgp->ldg)); 21944961713Sgirish continue; 22044961713Sgirish } 22144961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: " 22244961713Sgirish "vector0 0x%llx vector1 0x%llx vector2 0x%llx", 22344961713Sgirish vector0, vector1, vector2)); 22444961713Sgirish t_ldgp->interrupted = B_TRUE; 22544961713Sgirish nldvs = t_ldgp->nldvs; 22644961713Sgirish for (j = 0; j < nldvs; j++, t_ldvp++) { 22744961713Sgirish /* 22844961713Sgirish * Call device's handler if flag bits are on. 22944961713Sgirish */ 23044961713Sgirish ldv = t_ldvp->ldv; 23144961713Sgirish if (((ldv < NXGE_MAC_LD_START) && 232a3c5bd6dSspeer (LDV_ON(ldv, vector0) | 23344961713Sgirish (LDV_ON(ldv, vector1)))) || 234a3c5bd6dSspeer (ldv >= NXGE_MAC_LD_START && 235a3c5bd6dSspeer ((LDV2_ON_1(ldv, vector2)) || 236a3c5bd6dSspeer (LDV2_ON_2(ldv, vector2))))) { 23744961713Sgirish (void) (t_ldvp->ldv_intr_handler)( 23844961713Sgirish (caddr_t)t_ldvp, arg2); 23944961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 24044961713Sgirish "==> nxge_intr: " 24144961713Sgirish "calling device %d #ldvs %d #intrs %d", 24244961713Sgirish j, nldvs, nintrs)); 24344961713Sgirish } 24444961713Sgirish } 24544961713Sgirish } 24644961713Sgirish 24744961713Sgirish t_ldgp = ldgp; 24844961713Sgirish for (i = 0; i < nintrs; i++, t_ldgp++) { 24944961713Sgirish /* rearm group interrupts */ 25044961713Sgirish if (t_ldgp->interrupted) { 25144961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: arm " 25244961713Sgirish "group %d", t_ldgp->ldg)); 25344961713Sgirish (void) npi_intr_ldg_mgmt_set(handle, t_ldgp->ldg, 25444961713Sgirish t_ldgp->arm, t_ldgp->ldg_timer); 25544961713Sgirish } 25644961713Sgirish } 25744961713Sgirish 25844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr: serviced 0x%x", 25944961713Sgirish serviced)); 26044961713Sgirish return (serviced); 26144961713Sgirish } 26244961713Sgirish 263a3c5bd6dSspeer /* ARGSUSED */ 26444961713Sgirish uint_t 26544961713Sgirish nxge_syserr_intr(void *arg1, void *arg2) 26644961713Sgirish { 267a3c5bd6dSspeer p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 268a3c5bd6dSspeer p_nxge_t nxgep = (p_nxge_t)arg2; 269a3c5bd6dSspeer p_nxge_ldg_t ldgp = NULL; 270a3c5bd6dSspeer npi_handle_t handle; 271a3c5bd6dSspeer sys_err_stat_t estat; 272a3c5bd6dSspeer uint_t serviced = DDI_INTR_UNCLAIMED; 27344961713Sgirish 27444961713Sgirish if (arg1 == NULL && arg2 == NULL) { 27544961713Sgirish return (serviced); 27644961713Sgirish } 277a3c5bd6dSspeer if (arg2 == NULL || ((ldvp != NULL && (void *) ldvp->nxgep != arg2))) { 27844961713Sgirish if (ldvp != NULL) { 27944961713Sgirish nxgep = ldvp->nxgep; 28044961713Sgirish } 28144961713Sgirish } 28244961713Sgirish NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, 283a3c5bd6dSspeer "==> nxge_syserr_intr: arg2 $%p arg1 $%p", nxgep, ldvp)); 28444961713Sgirish if (ldvp != NULL && ldvp->use_timer == B_FALSE) { 28544961713Sgirish ldgp = ldvp->ldgp; 28644961713Sgirish if (ldgp == NULL) { 28744961713Sgirish NXGE_ERROR_MSG((nxgep, SYSERR_CTL, 28844961713Sgirish "<== nxge_syserrintr(no logical group): " 289a3c5bd6dSspeer "arg2 $%p arg1 $%p", nxgep, ldvp)); 29044961713Sgirish return (DDI_INTR_UNCLAIMED); 29144961713Sgirish } 29244961713Sgirish /* 29344961713Sgirish * Get the logical device state if the function uses interrupt. 29444961713Sgirish */ 29544961713Sgirish } 29644961713Sgirish 29744961713Sgirish /* This interrupt handler is for system error interrupts. */ 29844961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 29944961713Sgirish estat.value = 0; 30044961713Sgirish (void) npi_fzc_sys_err_stat_get(handle, &estat); 30144961713Sgirish NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, 302a3c5bd6dSspeer "==> nxge_syserr_intr: device error 0x%016llx", estat.value)); 30344961713Sgirish 30444961713Sgirish if (estat.bits.ldw.smx) { 30544961713Sgirish /* SMX */ 30644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 30744961713Sgirish "==> nxge_syserr_intr: device error - SMX")); 30844961713Sgirish } else if (estat.bits.ldw.mac) { 30944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 31044961713Sgirish "==> nxge_syserr_intr: device error - MAC")); 31144961713Sgirish /* 312a3c5bd6dSspeer * There is nothing to be done here. All MAC errors go to per 313a3c5bd6dSspeer * MAC port interrupt. MIF interrupt is the only MAC sub-block 314a3c5bd6dSspeer * that can generate status here. MIF status reported will be 315a3c5bd6dSspeer * ignored here. It is checked by per port timer instead. 31644961713Sgirish */ 31744961713Sgirish } else if (estat.bits.ldw.ipp) { 31844961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 31944961713Sgirish "==> nxge_syserr_intr: device error - IPP")); 32044961713Sgirish (void) nxge_ipp_handle_sys_errors(nxgep); 32144961713Sgirish } else if (estat.bits.ldw.zcp) { 32244961713Sgirish /* ZCP */ 32344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 32444961713Sgirish "==> nxge_syserr_intr: device error - ZCP")); 32544961713Sgirish (void) nxge_zcp_handle_sys_errors(nxgep); 32644961713Sgirish } else if (estat.bits.ldw.tdmc) { 32744961713Sgirish /* TDMC */ 32844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 32944961713Sgirish "==> nxge_syserr_intr: device error - TDMC")); 33044961713Sgirish /* 331a3c5bd6dSspeer * There is no TDMC system errors defined in the PRM. All TDMC 332a3c5bd6dSspeer * channel specific errors are reported on a per channel basis. 33344961713Sgirish */ 33444961713Sgirish } else if (estat.bits.ldw.rdmc) { 33544961713Sgirish /* RDMC */ 33644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 33744961713Sgirish "==> nxge_syserr_intr: device error - RDMC")); 33844961713Sgirish (void) nxge_rxdma_handle_sys_errors(nxgep); 33944961713Sgirish } else if (estat.bits.ldw.txc) { 34044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 34144961713Sgirish "==> nxge_syserr_intr: device error - TXC")); 34244961713Sgirish (void) nxge_txc_handle_sys_errors(nxgep); 34344961713Sgirish } else if ((nxgep->niu_type != N2_NIU) && estat.bits.ldw.peu) { 34444961713Sgirish /* PCI-E */ 34544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 34644961713Sgirish "==> nxge_syserr_intr: device error - PCI-E")); 34744961713Sgirish } else if (estat.bits.ldw.meta1) { 34844961713Sgirish /* META1 */ 34944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 35044961713Sgirish "==> nxge_syserr_intr: device error - META1")); 35144961713Sgirish } else if (estat.bits.ldw.meta2) { 35244961713Sgirish /* META2 */ 35344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 35444961713Sgirish "==> nxge_syserr_intr: device error - META2")); 35544961713Sgirish } else if (estat.bits.ldw.fflp) { 35644961713Sgirish /* FFLP */ 35744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 35844961713Sgirish "==> nxge_syserr_intr: device error - FFLP")); 35944961713Sgirish (void) nxge_fflp_handle_sys_errors(nxgep); 36044961713Sgirish } 36144961713Sgirish serviced = DDI_INTR_CLAIMED; 36244961713Sgirish 36344961713Sgirish if (ldgp != NULL && ldvp != NULL && ldgp->nldvs == 1 && 364a3c5bd6dSspeer !ldvp->use_timer) { 36544961713Sgirish (void) npi_intr_ldg_mgmt_set(handle, ldgp->ldg, 36644961713Sgirish B_TRUE, ldgp->ldg_timer); 36744961713Sgirish } 36844961713Sgirish NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "<== nxge_syserr_intr")); 36944961713Sgirish return (serviced); 37044961713Sgirish } 37144961713Sgirish 372a3c5bd6dSspeer /* ARGSUSED */ 37344961713Sgirish void 37444961713Sgirish nxge_intr_hw_enable(p_nxge_t nxgep) 37544961713Sgirish { 37644961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_hw_enable")); 37744961713Sgirish (void) nxge_intr_mask_mgmt_set(nxgep, B_TRUE); 37844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_hw_enable")); 37944961713Sgirish } 38044961713Sgirish 381a3c5bd6dSspeer /* ARGSUSED */ 38244961713Sgirish void 38344961713Sgirish nxge_intr_hw_disable(p_nxge_t nxgep) 38444961713Sgirish { 38544961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_hw_disable")); 38644961713Sgirish (void) nxge_intr_mask_mgmt_set(nxgep, B_FALSE); 38744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_hw_disable")); 38844961713Sgirish } 38944961713Sgirish 390a3c5bd6dSspeer /* ARGSUSED */ 39144961713Sgirish void 39244961713Sgirish nxge_rx_hw_blank(void *arg, time_t ticks, uint_t count) 39344961713Sgirish { 394a3c5bd6dSspeer p_nxge_t nxgep = (p_nxge_t)arg; 395a3c5bd6dSspeer uint8_t channel; 396a3c5bd6dSspeer npi_handle_t handle; 397a3c5bd6dSspeer p_nxge_ldgv_t ldgvp; 398a3c5bd6dSspeer p_nxge_ldv_t ldvp; 399a3c5bd6dSspeer int i; 40044961713Sgirish 40144961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_rx_hw_blank")); 40244961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 40344961713Sgirish 40444961713Sgirish if ((ldgvp = nxgep->ldgvp) == NULL) { 40544961713Sgirish NXGE_ERROR_MSG((nxgep, INT_CTL, 40644961713Sgirish "<== nxge_rx_hw_blank (not enabled)")); 40744961713Sgirish return; 40844961713Sgirish } 40944961713Sgirish ldvp = nxgep->ldgvp->ldvp; 41044961713Sgirish if (ldvp == NULL) { 41144961713Sgirish return; 41244961713Sgirish } 41344961713Sgirish for (i = 0; i < ldgvp->nldvs; i++, ldvp++) { 41444961713Sgirish if (ldvp->is_rxdma) { 41544961713Sgirish channel = ldvp->channel; 41644961713Sgirish (void) npi_rxdma_cfg_rdc_rcr_threshold(handle, 41744961713Sgirish channel, count); 41844961713Sgirish (void) npi_rxdma_cfg_rdc_rcr_timeout(handle, 41944961713Sgirish channel, ticks); 42044961713Sgirish } 42144961713Sgirish } 42244961713Sgirish 42344961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_rx_hw_blank")); 42444961713Sgirish } 42544961713Sgirish 426a3c5bd6dSspeer /* ARGSUSED */ 42744961713Sgirish void 42844961713Sgirish nxge_hw_stop(p_nxge_t nxgep) 42944961713Sgirish { 43044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_stop")); 43144961713Sgirish 43244961713Sgirish (void) nxge_tx_mac_disable(nxgep); 43344961713Sgirish (void) nxge_rx_mac_disable(nxgep); 43444961713Sgirish (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP); 43544961713Sgirish (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 43644961713Sgirish 43744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_stop")); 43844961713Sgirish } 43944961713Sgirish 440a3c5bd6dSspeer /* ARGSUSED */ 44144961713Sgirish void 44244961713Sgirish nxge_hw_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 44344961713Sgirish { 44444961713Sgirish int cmd; 44544961713Sgirish 44644961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_hw_ioctl")); 44744961713Sgirish 44844961713Sgirish if (nxgep == NULL) { 44944961713Sgirish miocnak(wq, mp, 0, EINVAL); 45044961713Sgirish return; 45144961713Sgirish } 45244961713Sgirish iocp->ioc_error = 0; 45344961713Sgirish cmd = iocp->ioc_cmd; 45444961713Sgirish 45544961713Sgirish switch (cmd) { 45644961713Sgirish default: 45744961713Sgirish miocnak(wq, mp, 0, EINVAL); 45844961713Sgirish return; 45944961713Sgirish 46044961713Sgirish case NXGE_GET_MII: 46144961713Sgirish nxge_get_mii(nxgep, mp->b_cont); 46244961713Sgirish miocack(wq, mp, sizeof (uint16_t), 0); 46344961713Sgirish break; 46444961713Sgirish 46544961713Sgirish case NXGE_PUT_MII: 46644961713Sgirish nxge_put_mii(nxgep, mp->b_cont); 46744961713Sgirish miocack(wq, mp, 0, 0); 46844961713Sgirish break; 46944961713Sgirish 47044961713Sgirish case NXGE_GET64: 47144961713Sgirish nxge_get64(nxgep, mp->b_cont); 47244961713Sgirish miocack(wq, mp, sizeof (uint32_t), 0); 47344961713Sgirish break; 47444961713Sgirish 47544961713Sgirish case NXGE_PUT64: 47644961713Sgirish nxge_put64(nxgep, mp->b_cont); 47744961713Sgirish miocack(wq, mp, 0, 0); 47844961713Sgirish break; 47944961713Sgirish 48044961713Sgirish case NXGE_PUT_TCAM: 48144961713Sgirish nxge_put_tcam(nxgep, mp->b_cont); 48244961713Sgirish miocack(wq, mp, 0, 0); 48344961713Sgirish break; 48444961713Sgirish 48544961713Sgirish case NXGE_GET_TCAM: 48644961713Sgirish nxge_get_tcam(nxgep, mp->b_cont); 48744961713Sgirish miocack(wq, mp, 0, 0); 48844961713Sgirish break; 48944961713Sgirish 49044961713Sgirish case NXGE_TX_REGS_DUMP: 49144961713Sgirish nxge_txdma_regs_dump_channels(nxgep); 49244961713Sgirish miocack(wq, mp, 0, 0); 49344961713Sgirish break; 49444961713Sgirish case NXGE_RX_REGS_DUMP: 49544961713Sgirish nxge_rxdma_regs_dump_channels(nxgep); 49644961713Sgirish miocack(wq, mp, 0, 0); 49744961713Sgirish break; 49844961713Sgirish case NXGE_VIR_INT_REGS_DUMP: 49944961713Sgirish case NXGE_INT_REGS_DUMP: 50044961713Sgirish nxge_virint_regs_dump(nxgep); 50144961713Sgirish miocack(wq, mp, 0, 0); 50244961713Sgirish break; 50344961713Sgirish case NXGE_RTRACE: 50444961713Sgirish nxge_rtrace_ioctl(nxgep, wq, mp, iocp); 50544961713Sgirish break; 50644961713Sgirish } 50744961713Sgirish } 50844961713Sgirish 509a3c5bd6dSspeer /* ARGSUSED */ 51044961713Sgirish void 51144961713Sgirish nxge_loopback_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, 512a3c5bd6dSspeer struct iocblk *iocp) 51344961713Sgirish { 514a3c5bd6dSspeer p_lb_property_t lb_props; 515a3c5bd6dSspeer 516a3c5bd6dSspeer size_t size; 517a3c5bd6dSspeer int i; 51844961713Sgirish 51944961713Sgirish if (mp->b_cont == NULL) { 52044961713Sgirish miocnak(wq, mp, 0, EINVAL); 52144961713Sgirish } 52244961713Sgirish switch (iocp->ioc_cmd) { 52344961713Sgirish case LB_GET_MODE: 52444961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "NXGE_GET_LB_MODE command")); 52544961713Sgirish if (nxgep != NULL) { 52644961713Sgirish *(lb_info_sz_t *)mp->b_cont->b_rptr = 527a3c5bd6dSspeer nxgep->statsp->port_stats.lb_mode; 52844961713Sgirish miocack(wq, mp, sizeof (nxge_lb_t), 0); 52944961713Sgirish } else 53044961713Sgirish miocnak(wq, mp, 0, EINVAL); 53144961713Sgirish break; 53244961713Sgirish case LB_SET_MODE: 53344961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "NXGE_SET_LB_MODE command")); 53444961713Sgirish if (iocp->ioc_count != sizeof (uint32_t)) { 53544961713Sgirish miocack(wq, mp, 0, 0); 53644961713Sgirish break; 53744961713Sgirish } 53844961713Sgirish if ((nxgep != NULL) && nxge_set_lb(nxgep, wq, mp->b_cont)) { 53944961713Sgirish miocack(wq, mp, 0, 0); 54044961713Sgirish } else { 54144961713Sgirish miocnak(wq, mp, 0, EPROTO); 54244961713Sgirish } 54344961713Sgirish break; 54444961713Sgirish case LB_GET_INFO_SIZE: 54544961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "LB_GET_INFO_SIZE command")); 54644961713Sgirish if (nxgep != NULL) { 54744961713Sgirish size = sizeof (lb_normal); 54844961713Sgirish if (nxgep->statsp->mac_stats.cap_10gfdx) { 54944961713Sgirish size += sizeof (lb_external10g); 55044961713Sgirish size += sizeof (lb_phy10g); 55144961713Sgirish size += sizeof (lb_serdes10g); 55244961713Sgirish size += sizeof (lb_mac10g); 55344961713Sgirish } 55444961713Sgirish if (nxgep->statsp->mac_stats.cap_1000fdx) { 55544961713Sgirish size += sizeof (lb_external1000); 55644961713Sgirish size += sizeof (lb_mac1000); 55744961713Sgirish if (nxgep->mac.portmode == PORT_1G_COPPER) 55844961713Sgirish size += sizeof (lb_phy1000); 55944961713Sgirish } 56044961713Sgirish if (nxgep->statsp->mac_stats.cap_100fdx) 56144961713Sgirish size += sizeof (lb_external100); 56244961713Sgirish if (nxgep->statsp->mac_stats.cap_10fdx) 56344961713Sgirish size += sizeof (lb_external10); 564*2e59129aSraghus else if ((nxgep->mac.portmode == PORT_1G_FIBER) || 565*2e59129aSraghus (nxgep->mac.portmode == PORT_1G_SERDES)) 56644961713Sgirish size += sizeof (lb_serdes1000); 567*2e59129aSraghus 56844961713Sgirish *(lb_info_sz_t *)mp->b_cont->b_rptr = size; 56944961713Sgirish 57044961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, 57144961713Sgirish "NXGE_GET_LB_INFO command: size %d", size)); 57244961713Sgirish miocack(wq, mp, sizeof (lb_info_sz_t), 0); 57344961713Sgirish } else 57444961713Sgirish miocnak(wq, mp, 0, EINVAL); 57544961713Sgirish break; 57644961713Sgirish 57744961713Sgirish case LB_GET_INFO: 57844961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "NXGE_GET_LB_INFO command")); 57944961713Sgirish if (nxgep != NULL) { 58044961713Sgirish size = sizeof (lb_normal); 58144961713Sgirish if (nxgep->statsp->mac_stats.cap_10gfdx) { 58244961713Sgirish size += sizeof (lb_external10g); 58344961713Sgirish size += sizeof (lb_phy10g); 58444961713Sgirish size += sizeof (lb_serdes10g); 58544961713Sgirish size += sizeof (lb_mac10g); 58644961713Sgirish } 58744961713Sgirish if (nxgep->statsp->mac_stats.cap_1000fdx) { 58844961713Sgirish size += sizeof (lb_external1000); 58944961713Sgirish size += sizeof (lb_mac1000); 59044961713Sgirish if (nxgep->mac.portmode == PORT_1G_COPPER) 59144961713Sgirish size += sizeof (lb_phy1000); 59244961713Sgirish } 59344961713Sgirish if (nxgep->statsp->mac_stats.cap_100fdx) 59444961713Sgirish size += sizeof (lb_external100); 59544961713Sgirish if (nxgep->statsp->mac_stats.cap_10fdx) 59644961713Sgirish size += sizeof (lb_external10); 597*2e59129aSraghus else if ((nxgep->mac.portmode == PORT_1G_FIBER) || 598*2e59129aSraghus (nxgep->mac.portmode == PORT_1G_SERDES)) 59944961713Sgirish size += sizeof (lb_serdes1000); 60044961713Sgirish 60144961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, 60244961713Sgirish "NXGE_GET_LB_INFO command: size %d", size)); 60344961713Sgirish if (size == iocp->ioc_count) { 60444961713Sgirish i = 0; 60544961713Sgirish lb_props = (p_lb_property_t)mp->b_cont->b_rptr; 60644961713Sgirish lb_props[i++] = lb_normal; 60744961713Sgirish if (nxgep->statsp->mac_stats.cap_10gfdx) { 60844961713Sgirish lb_props[i++] = lb_mac10g; 60944961713Sgirish lb_props[i++] = lb_serdes10g; 61044961713Sgirish lb_props[i++] = lb_phy10g; 61144961713Sgirish lb_props[i++] = lb_external10g; 61244961713Sgirish } 61344961713Sgirish if (nxgep->statsp->mac_stats.cap_1000fdx) 61444961713Sgirish lb_props[i++] = lb_external1000; 61544961713Sgirish if (nxgep->statsp->mac_stats.cap_100fdx) 61644961713Sgirish lb_props[i++] = lb_external100; 61744961713Sgirish if (nxgep->statsp->mac_stats.cap_10fdx) 61844961713Sgirish lb_props[i++] = lb_external10; 61944961713Sgirish if (nxgep->statsp->mac_stats.cap_1000fdx) 62044961713Sgirish lb_props[i++] = lb_mac1000; 62144961713Sgirish if (nxgep->mac.portmode == PORT_1G_COPPER) { 62244961713Sgirish if (nxgep->statsp->mac_stats. 623a3c5bd6dSspeer cap_1000fdx) 62444961713Sgirish lb_props[i++] = lb_phy1000; 625*2e59129aSraghus } else if ((nxgep->mac.portmode == 626*2e59129aSraghus PORT_1G_FIBER) || 627*2e59129aSraghus (nxgep->mac.portmode == PORT_1G_SERDES)) { 62844961713Sgirish lb_props[i++] = lb_serdes1000; 629*2e59129aSraghus } 63044961713Sgirish miocack(wq, mp, size, 0); 63144961713Sgirish } else 63244961713Sgirish miocnak(wq, mp, 0, EINVAL); 63344961713Sgirish } else { 63444961713Sgirish miocnak(wq, mp, 0, EINVAL); 63544961713Sgirish cmn_err(CE_NOTE, "!nxge_hw_ioctl: invalid command 0x%x", 63644961713Sgirish iocp->ioc_cmd); 63744961713Sgirish } 63844961713Sgirish break; 63944961713Sgirish } 64044961713Sgirish } 64144961713Sgirish 64244961713Sgirish /* 64344961713Sgirish * DMA channel interfaces to access various channel specific 64444961713Sgirish * hardware functions. 64544961713Sgirish */ 646a3c5bd6dSspeer /* ARGSUSED */ 64744961713Sgirish void 64844961713Sgirish nxge_rxdma_channel_put64(nxge_os_acc_handle_t handle, void *reg_addrp, 649a3c5bd6dSspeer uint32_t reg_base, uint16_t channel, uint64_t reg_data) 65044961713Sgirish { 651a3c5bd6dSspeer uint64_t reg_offset; 65244961713Sgirish 65344961713Sgirish NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_put64")); 65444961713Sgirish 65544961713Sgirish /* 656a3c5bd6dSspeer * Channel is assumed to be from 0 to the maximum DMA channel #. If we 657a3c5bd6dSspeer * use the virtual DMA CSR address space from the config space (in PCI 658a3c5bd6dSspeer * case), then the following code need to be use different offset 65944961713Sgirish * computation macro. 66044961713Sgirish */ 66144961713Sgirish reg_offset = reg_base + DMC_OFFSET(channel); 66244961713Sgirish NXGE_PIO_WRITE64(handle, reg_addrp, reg_offset, reg_data); 66344961713Sgirish 66444961713Sgirish NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_put64")); 66544961713Sgirish } 66644961713Sgirish 667a3c5bd6dSspeer /* ARGSUSED */ 66844961713Sgirish uint64_t 66944961713Sgirish nxge_rxdma_channel_get64(nxge_os_acc_handle_t handle, void *reg_addrp, 670a3c5bd6dSspeer uint32_t reg_base, uint16_t channel) 67144961713Sgirish { 672a3c5bd6dSspeer uint64_t reg_offset; 67344961713Sgirish 67444961713Sgirish NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_get64")); 67544961713Sgirish 67644961713Sgirish /* 677a3c5bd6dSspeer * Channel is assumed to be from 0 to the maximum DMA channel #. If we 678a3c5bd6dSspeer * use the virtual DMA CSR address space from the config space (in PCI 679a3c5bd6dSspeer * case), then the following code need to be use different offset 68044961713Sgirish * computation macro. 68144961713Sgirish */ 68244961713Sgirish reg_offset = reg_base + DMC_OFFSET(channel); 68344961713Sgirish 68444961713Sgirish NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_get64")); 68544961713Sgirish 68644961713Sgirish return (NXGE_PIO_READ64(handle, reg_addrp, reg_offset)); 68744961713Sgirish } 68844961713Sgirish 689a3c5bd6dSspeer /* ARGSUSED */ 69044961713Sgirish void 69144961713Sgirish nxge_get32(p_nxge_t nxgep, p_mblk_t mp) 69244961713Sgirish { 693a3c5bd6dSspeer nxge_os_acc_handle_t nxge_regh; 69444961713Sgirish 69544961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_get32")); 69644961713Sgirish nxge_regh = nxgep->dev_regs->nxge_regh; 69744961713Sgirish 69844961713Sgirish *(uint32_t *)mp->b_rptr = NXGE_PIO_READ32(nxge_regh, 699a3c5bd6dSspeer nxgep->dev_regs->nxge_regp, *(uint32_t *)mp->b_rptr); 70044961713Sgirish 70144961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "value = 0x%08X", 702a3c5bd6dSspeer *(uint32_t *)mp->b_rptr)); 70344961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_get32")); 70444961713Sgirish } 70544961713Sgirish 706a3c5bd6dSspeer /* ARGSUSED */ 70744961713Sgirish void 70844961713Sgirish nxge_put32(p_nxge_t nxgep, p_mblk_t mp) 70944961713Sgirish { 71044961713Sgirish nxge_os_acc_handle_t nxge_regh; 71144961713Sgirish uint32_t *buf; 71244961713Sgirish uint8_t *reg; 71344961713Sgirish 71444961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_put32")); 71544961713Sgirish nxge_regh = nxgep->dev_regs->nxge_regh; 71644961713Sgirish 71744961713Sgirish buf = (uint32_t *)mp->b_rptr; 71844961713Sgirish reg = (uint8_t *)(nxgep->dev_regs->nxge_regp) + buf[0]; 71944961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, 720a3c5bd6dSspeer "reg = 0x%016llX index = 0x%08X value = 0x%08X", 721a3c5bd6dSspeer reg, buf[0], buf[1])); 72244961713Sgirish NXGE_PIO_WRITE32(nxge_regh, (uint32_t *)reg, 0, buf[1]); 72344961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_put32")); 72444961713Sgirish } 72544961713Sgirish 72644961713Sgirish /*ARGSUSED*/ 72744961713Sgirish boolean_t 72844961713Sgirish nxge_set_lb(p_nxge_t nxgep, queue_t *wq, p_mblk_t mp) 72944961713Sgirish { 730a3c5bd6dSspeer boolean_t status = B_TRUE; 731a3c5bd6dSspeer uint32_t lb_mode; 732a3c5bd6dSspeer lb_property_t *lb_info; 73344961713Sgirish 73444961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_set_lb")); 73544961713Sgirish lb_mode = nxgep->statsp->port_stats.lb_mode; 73644961713Sgirish if (lb_mode == *(uint32_t *)mp->b_rptr) { 73744961713Sgirish cmn_err(CE_NOTE, 73844961713Sgirish "!nxge%d: Loopback mode already set (lb_mode %d).\n", 73944961713Sgirish nxgep->instance, lb_mode); 74044961713Sgirish status = B_FALSE; 74144961713Sgirish goto nxge_set_lb_exit; 74244961713Sgirish } 74344961713Sgirish lb_mode = *(uint32_t *)mp->b_rptr; 74444961713Sgirish lb_info = NULL; 74544961713Sgirish if (lb_mode == lb_normal.value) 74644961713Sgirish lb_info = &lb_normal; 74744961713Sgirish else if ((lb_mode == lb_external10g.value) && 748a3c5bd6dSspeer (nxgep->statsp->mac_stats.cap_10gfdx)) 74944961713Sgirish lb_info = &lb_external10g; 75044961713Sgirish else if ((lb_mode == lb_external1000.value) && 751a3c5bd6dSspeer (nxgep->statsp->mac_stats.cap_1000fdx)) 75244961713Sgirish lb_info = &lb_external1000; 75344961713Sgirish else if ((lb_mode == lb_external100.value) && 754a3c5bd6dSspeer (nxgep->statsp->mac_stats.cap_100fdx)) 75544961713Sgirish lb_info = &lb_external100; 75644961713Sgirish else if ((lb_mode == lb_external10.value) && 757a3c5bd6dSspeer (nxgep->statsp->mac_stats.cap_10fdx)) 75844961713Sgirish lb_info = &lb_external10; 75944961713Sgirish else if ((lb_mode == lb_phy10g.value) && 76044961713Sgirish ((nxgep->mac.portmode == PORT_10G_COPPER) || 76144961713Sgirish (nxgep->mac.portmode == PORT_10G_FIBER))) 76244961713Sgirish lb_info = &lb_phy10g; 76344961713Sgirish else if ((lb_mode == lb_phy1000.value) && 764a3c5bd6dSspeer (nxgep->mac.portmode == PORT_1G_COPPER)) 76544961713Sgirish lb_info = &lb_phy1000; 76644961713Sgirish else if ((lb_mode == lb_phy.value) && 767a3c5bd6dSspeer (nxgep->mac.portmode == PORT_1G_COPPER)) 76844961713Sgirish lb_info = &lb_phy; 76944961713Sgirish else if ((lb_mode == lb_serdes10g.value) && 770*2e59129aSraghus ((nxgep->mac.portmode == PORT_10G_FIBER) || 771*2e59129aSraghus (nxgep->mac.portmode == PORT_10G_COPPER) || 772*2e59129aSraghus (nxgep->mac.portmode == PORT_10G_SERDES))) 77344961713Sgirish lb_info = &lb_serdes10g; 77444961713Sgirish else if ((lb_mode == lb_serdes1000.value) && 775*2e59129aSraghus (nxgep->mac.portmode == PORT_1G_FIBER || 776*2e59129aSraghus (nxgep->mac.portmode == PORT_1G_SERDES))) 77744961713Sgirish lb_info = &lb_serdes1000; 77844961713Sgirish else if (lb_mode == lb_mac10g.value) 77944961713Sgirish lb_info = &lb_mac10g; 78044961713Sgirish else if (lb_mode == lb_mac1000.value) 78144961713Sgirish lb_info = &lb_mac1000; 78244961713Sgirish else if (lb_mode == lb_mac.value) 78344961713Sgirish lb_info = &lb_mac; 78444961713Sgirish else { 78544961713Sgirish cmn_err(CE_NOTE, 78644961713Sgirish "!nxge%d: Loopback mode not supported(mode %d).\n", 78744961713Sgirish nxgep->instance, lb_mode); 78844961713Sgirish status = B_FALSE; 78944961713Sgirish goto nxge_set_lb_exit; 79044961713Sgirish } 79144961713Sgirish 79244961713Sgirish if (lb_mode == nxge_lb_normal) { 79344961713Sgirish if (nxge_lb_dbg) { 79444961713Sgirish cmn_err(CE_NOTE, 79544961713Sgirish "!nxge%d: Returning to normal operation", 79644961713Sgirish nxgep->instance); 79744961713Sgirish } 79844961713Sgirish nxge_set_lb_normal(nxgep); 79944961713Sgirish goto nxge_set_lb_exit; 80044961713Sgirish } 80144961713Sgirish nxgep->statsp->port_stats.lb_mode = lb_mode; 80244961713Sgirish 80344961713Sgirish if (nxge_lb_dbg) 80444961713Sgirish cmn_err(CE_NOTE, 80544961713Sgirish "!nxge%d: Adapter now in %s loopback mode", 80644961713Sgirish nxgep->instance, lb_info->key); 80744961713Sgirish nxgep->param_arr[param_autoneg].value = 0; 80844961713Sgirish nxgep->param_arr[param_anar_10gfdx].value = 80944961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10g) || 81044961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac10g) || 81144961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy10g) || 81244961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes10g); 81344961713Sgirish nxgep->param_arr[param_anar_10ghdx].value = 0; 81444961713Sgirish nxgep->param_arr[param_anar_1000fdx].value = 81544961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext1000) || 81644961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac1000) || 81744961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy1000) || 81844961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes1000); 81944961713Sgirish nxgep->param_arr[param_anar_1000hdx].value = 0; 82044961713Sgirish nxgep->param_arr[param_anar_100fdx].value = 82144961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy) || 82244961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac) || 82344961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext100); 82444961713Sgirish nxgep->param_arr[param_anar_100hdx].value = 0; 82544961713Sgirish nxgep->param_arr[param_anar_10fdx].value = 82644961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac) || 82744961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10); 82844961713Sgirish if (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext1000) { 82944961713Sgirish nxgep->param_arr[param_master_cfg_enable].value = 1; 83044961713Sgirish nxgep->param_arr[param_master_cfg_value].value = 1; 83144961713Sgirish } 83244961713Sgirish if ((nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10g) || 83344961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext1000) || 83444961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext100) || 83544961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10) || 83644961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy10g) || 83744961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy1000) || 83844961713Sgirish (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy)) { 83944961713Sgirish 84044961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 841*2e59129aSraghus (void) nxge_xcvr_find(nxgep); 84244961713Sgirish (void) nxge_link_init(nxgep); 84344961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 84444961713Sgirish } 84544961713Sgirish if (lb_info->lb_type == internal) { 84644961713Sgirish if ((nxgep->statsp->port_stats.lb_mode == nxge_lb_mac10g) || 847a3c5bd6dSspeer (nxgep->statsp->port_stats.lb_mode == 848a3c5bd6dSspeer nxge_lb_phy10g) || 849a3c5bd6dSspeer (nxgep->statsp->port_stats.lb_mode == 850a3c5bd6dSspeer nxge_lb_serdes10g)) { 85144961713Sgirish nxgep->statsp->mac_stats.link_speed = 10000; 852a3c5bd6dSspeer } else if ((nxgep->statsp->port_stats.lb_mode 853a3c5bd6dSspeer == nxge_lb_mac1000) || 854a3c5bd6dSspeer (nxgep->statsp->port_stats.lb_mode == 855a3c5bd6dSspeer nxge_lb_phy1000) || 856a3c5bd6dSspeer (nxgep->statsp->port_stats.lb_mode == 857a3c5bd6dSspeer nxge_lb_serdes1000)) { 85844961713Sgirish nxgep->statsp->mac_stats.link_speed = 1000; 85944961713Sgirish } else { 86044961713Sgirish nxgep->statsp->mac_stats.link_speed = 100; 86144961713Sgirish } 86244961713Sgirish nxgep->statsp->mac_stats.link_duplex = 2; 86344961713Sgirish nxgep->statsp->mac_stats.link_up = 1; 86444961713Sgirish } 86544961713Sgirish nxge_global_reset(nxgep); 86644961713Sgirish 86744961713Sgirish nxge_set_lb_exit: 86844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 869a3c5bd6dSspeer "<== nxge_set_lb status = 0x%08x", status)); 87044961713Sgirish return (status); 87144961713Sgirish } 87244961713Sgirish 873a3c5bd6dSspeer /* ARGSUSED */ 87444961713Sgirish void 87544961713Sgirish nxge_set_lb_normal(p_nxge_t nxgep) 87644961713Sgirish { 87744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_set_lb_normal")); 87844961713Sgirish nxgep->statsp->port_stats.lb_mode = nxge_lb_normal; 87944961713Sgirish nxgep->param_arr[param_autoneg].value = 88044961713Sgirish nxgep->param_arr[param_autoneg].old_value; 88144961713Sgirish nxgep->param_arr[param_anar_1000fdx].value = 88244961713Sgirish nxgep->param_arr[param_anar_1000fdx].old_value; 88344961713Sgirish nxgep->param_arr[param_anar_1000hdx].value = 88444961713Sgirish nxgep->param_arr[param_anar_1000hdx].old_value; 88544961713Sgirish nxgep->param_arr[param_anar_100fdx].value = 88644961713Sgirish nxgep->param_arr[param_anar_100fdx].old_value; 88744961713Sgirish nxgep->param_arr[param_anar_100hdx].value = 88844961713Sgirish nxgep->param_arr[param_anar_100hdx].old_value; 88944961713Sgirish nxgep->param_arr[param_anar_10fdx].value = 89044961713Sgirish nxgep->param_arr[param_anar_10fdx].old_value; 89144961713Sgirish nxgep->param_arr[param_master_cfg_enable].value = 89244961713Sgirish nxgep->param_arr[param_master_cfg_enable].old_value; 89344961713Sgirish nxgep->param_arr[param_master_cfg_value].value = 89444961713Sgirish nxgep->param_arr[param_master_cfg_value].old_value; 89544961713Sgirish 89644961713Sgirish nxge_global_reset(nxgep); 89744961713Sgirish 89844961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 899*2e59129aSraghus (void) nxge_xcvr_find(nxgep); 90044961713Sgirish (void) nxge_link_init(nxgep); 90144961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 90244961713Sgirish 90344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_set_lb_normal")); 90444961713Sgirish } 90544961713Sgirish 906a3c5bd6dSspeer /* ARGSUSED */ 90744961713Sgirish void 90844961713Sgirish nxge_get_mii(p_nxge_t nxgep, p_mblk_t mp) 90944961713Sgirish { 91044961713Sgirish uint16_t reg; 91144961713Sgirish 91244961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_get_mii")); 91344961713Sgirish 91444961713Sgirish reg = *(uint16_t *)mp->b_rptr; 91544961713Sgirish (void) nxge_mii_read(nxgep, nxgep->statsp->mac_stats.xcvr_portn, reg, 916a3c5bd6dSspeer (uint16_t *)mp->b_rptr); 91744961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "reg = 0x%08X value = 0x%04X", 918a3c5bd6dSspeer reg, *(uint16_t *)mp->b_rptr)); 91944961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_get_mii")); 92044961713Sgirish } 92144961713Sgirish 922a3c5bd6dSspeer /* ARGSUSED */ 92344961713Sgirish void 92444961713Sgirish nxge_put_mii(p_nxge_t nxgep, p_mblk_t mp) 92544961713Sgirish { 92644961713Sgirish uint16_t *buf; 92744961713Sgirish uint8_t reg; 92844961713Sgirish 92944961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_put_mii")); 93044961713Sgirish buf = (uint16_t *)mp->b_rptr; 93144961713Sgirish reg = (uint8_t)buf[0]; 93244961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, 933a3c5bd6dSspeer "reg = 0x%08X index = 0x%08X value = 0x%08X", 934a3c5bd6dSspeer reg, buf[0], buf[1])); 93544961713Sgirish (void) nxge_mii_write(nxgep, nxgep->statsp->mac_stats.xcvr_portn, 93644961713Sgirish reg, buf[1]); 93744961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_put_mii")); 93844961713Sgirish } 93944961713Sgirish 940a3c5bd6dSspeer /* ARGSUSED */ 94144961713Sgirish void 94244961713Sgirish nxge_check_hw_state(p_nxge_t nxgep) 94344961713Sgirish { 944a3c5bd6dSspeer p_nxge_ldgv_t ldgvp; 945a3c5bd6dSspeer p_nxge_ldv_t t_ldvp; 94644961713Sgirish 94744961713Sgirish NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "==> nxge_check_hw_state")); 94844961713Sgirish 94914ea4bb7Ssd MUTEX_ENTER(nxgep->genlock); 95014ea4bb7Ssd nxgep->nxge_timerid = 0; 95114ea4bb7Ssd if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 95214ea4bb7Ssd goto nxge_check_hw_state_exit; 95314ea4bb7Ssd } 95444961713Sgirish nxge_check_tx_hang(nxgep); 95544961713Sgirish 95644961713Sgirish ldgvp = nxgep->ldgvp; 95744961713Sgirish if (ldgvp == NULL || (ldgvp->ldvp_syserr == NULL)) { 95844961713Sgirish NXGE_ERROR_MSG((nxgep, SYSERR_CTL, "<== nxge_check_hw_state: " 959a3c5bd6dSspeer "NULL ldgvp (interrupt not ready).")); 96014ea4bb7Ssd goto nxge_check_hw_state_exit; 96144961713Sgirish } 96244961713Sgirish t_ldvp = ldgvp->ldvp_syserr; 96344961713Sgirish if (!t_ldvp->use_timer) { 96444961713Sgirish NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "<== nxge_check_hw_state: " 965a3c5bd6dSspeer "ldgvp $%p t_ldvp $%p use_timer flag %d", 966a3c5bd6dSspeer ldgvp, t_ldvp, t_ldvp->use_timer)); 96714ea4bb7Ssd goto nxge_check_hw_state_exit; 96814ea4bb7Ssd } 96914ea4bb7Ssd if (fm_check_acc_handle(nxgep->dev_regs->nxge_regh) != DDI_FM_OK) { 97014ea4bb7Ssd NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 97114ea4bb7Ssd "port%d Bad register acc handle", nxgep->mac.portnum)); 97244961713Sgirish } 973a3c5bd6dSspeer (void) nxge_syserr_intr((void *) t_ldvp, (void *) nxgep); 97444961713Sgirish 97544961713Sgirish nxgep->nxge_timerid = nxge_start_timer(nxgep, nxge_check_hw_state, 97644961713Sgirish NXGE_CHECK_TIMER); 97744961713Sgirish 97814ea4bb7Ssd nxge_check_hw_state_exit: 97914ea4bb7Ssd MUTEX_EXIT(nxgep->genlock); 98044961713Sgirish NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "<== nxge_check_hw_state")); 98144961713Sgirish } 98244961713Sgirish 98344961713Sgirish /*ARGSUSED*/ 98444961713Sgirish static void 985a3c5bd6dSspeer nxge_rtrace_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, 986a3c5bd6dSspeer struct iocblk *iocp) 98744961713Sgirish { 988a3c5bd6dSspeer ssize_t size; 989a3c5bd6dSspeer rtrace_t *rtp; 990a3c5bd6dSspeer mblk_t *nmp; 991a3c5bd6dSspeer uint32_t i, j; 992a3c5bd6dSspeer uint32_t start_blk; 993a3c5bd6dSspeer uint32_t base_entry; 994a3c5bd6dSspeer uint32_t num_entries; 99544961713Sgirish 99644961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_rtrace_ioctl")); 99744961713Sgirish 99844961713Sgirish size = 1024; 99944961713Sgirish if (mp->b_cont == NULL || MBLKL(mp->b_cont) < size) { 100044961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, 1001a3c5bd6dSspeer "malformed M_IOCTL MBLKL = %d size = %d", 1002a3c5bd6dSspeer MBLKL(mp->b_cont), size)); 100344961713Sgirish miocnak(wq, mp, 0, EINVAL); 100444961713Sgirish return; 100544961713Sgirish } 100644961713Sgirish nmp = mp->b_cont; 100744961713Sgirish rtp = (rtrace_t *)nmp->b_rptr; 100844961713Sgirish start_blk = rtp->next_idx; 100944961713Sgirish num_entries = rtp->last_idx; 101044961713Sgirish base_entry = start_blk * MAX_RTRACE_IOC_ENTRIES; 101144961713Sgirish 101244961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "start_blk = %d\n", start_blk)); 101344961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "num_entries = %d\n", num_entries)); 101444961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "base_entry = %d\n", base_entry)); 101544961713Sgirish 101644961713Sgirish rtp->next_idx = npi_rtracebuf.next_idx; 101744961713Sgirish rtp->last_idx = npi_rtracebuf.last_idx; 101844961713Sgirish rtp->wrapped = npi_rtracebuf.wrapped; 101944961713Sgirish for (i = 0, j = base_entry; i < num_entries; i++, j++) { 102044961713Sgirish rtp->buf[i].ctl_addr = npi_rtracebuf.buf[j].ctl_addr; 102144961713Sgirish rtp->buf[i].val_l32 = npi_rtracebuf.buf[j].val_l32; 102244961713Sgirish rtp->buf[i].val_h32 = npi_rtracebuf.buf[j].val_h32; 102344961713Sgirish } 102444961713Sgirish 102544961713Sgirish nmp->b_wptr = nmp->b_rptr + size; 102644961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "<== nxge_rtrace_ioctl")); 102744961713Sgirish miocack(wq, mp, (int)size, 0); 102844961713Sgirish } 1029