144961713Sgirish/*
244961713Sgirish * CDDL HEADER START
344961713Sgirish *
444961713Sgirish * The contents of this file are subject to the terms of the
544961713Sgirish * Common Development and Distribution License (the "License").
644961713Sgirish * You may not use this file except in compliance with the License.
744961713Sgirish *
844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
944961713Sgirish * or http://www.opensolaris.org/os/licensing.
1044961713Sgirish * See the License for the specific language governing permissions
1144961713Sgirish * and limitations under the License.
1244961713Sgirish *
1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each
1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the
1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying
1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner]
1844961713Sgirish *
1944961713Sgirish * CDDL HEADER END
2044961713Sgirish */
21678453a8Sspeer
2244961713Sgirish/*
23*4df55fdeSJanie Lu * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
2444961713Sgirish * Use is subject to license terms.
2544961713Sgirish */
2644961713Sgirish
2744961713Sgirish/*
2844961713Sgirish * Hypervisor calls called by niu leaf driver.
2952ccf843Smisaki */
3044961713Sgirish
3144961713Sgirish#include <sys/asm_linkage.h>
3244961713Sgirish#include <sys/hypervisor_api.h>
3344961713Sgirish#include <sys/nxge/nxge_impl.h>
3444961713Sgirish
35da14cebeSEric Cheng#if defined(sun4v)
36da14cebeSEric Cheng
37678453a8Sspeer/*
38678453a8Sspeer * NIU HV API v1.0 definitions
39678453a8Sspeer */
40678453a8Sspeer#define	N2NIU_RX_LP_SET		0x142
41678453a8Sspeer#define	N2NIU_RX_LP_GET		0x143
42678453a8Sspeer#define	N2NIU_TX_LP_SET		0x144
43678453a8Sspeer#define	N2NIU_TX_LP_GET		0x145
44678453a8Sspeer
45678453a8Sspeer/*
46678453a8Sspeer * NIU HV API v1.1 definitions
47678453a8Sspeer */
48678453a8Sspeer#define	N2NIU_VR_ASSIGN		0x146
49678453a8Sspeer#define	N2NIU_VR_UNASSIGN	0x147
50678453a8Sspeer#define	N2NIU_VR_GETINFO	0x148
51678453a8Sspeer
52678453a8Sspeer#define	N2NIU_VR_RX_DMA_ASSIGN		0x149
53678453a8Sspeer#define	N2NIU_VR_RX_DMA_UNASSIGN	0x14a
54678453a8Sspeer#define	N2NIU_VR_TX_DMA_ASSIGN		0x14b
55678453a8Sspeer#define	N2NIU_VR_TX_DMA_UNASSIGN	0x14c
56678453a8Sspeer
57678453a8Sspeer#define	N2NIU_VR_GET_RX_MAP	0x14d
58678453a8Sspeer#define	N2NIU_VR_GET_TX_MAP	0x14e
59678453a8Sspeer
6052ccf843Smisaki#define	N2NIU_VRRX_SET_INO	0x150
6152ccf843Smisaki#define	N2NIU_VRTX_SET_INO	0x151
62678453a8Sspeer
63678453a8Sspeer#define	N2NIU_VRRX_GET_INFO	0x152
64678453a8Sspeer#define	N2NIU_VRTX_GET_INFO	0x153
65678453a8Sspeer
66678453a8Sspeer#define	N2NIU_VRRX_LP_SET	0x154
67678453a8Sspeer#define	N2NIU_VRRX_LP_GET	0x155
68678453a8Sspeer#define	N2NIU_VRTX_LP_SET	0x156
69678453a8Sspeer#define	N2NIU_VRTX_LP_GET	0x157
70678453a8Sspeer
7152ccf843Smisaki#define	N2NIU_VRRX_PARAM_GET	0x158
7252ccf843Smisaki#define	N2NIU_VRRX_PARAM_SET	0x159
73678453a8Sspeer
7452ccf843Smisaki#define	N2NIU_VRTX_PARAM_GET	0x15a
7552ccf843Smisaki#define	N2NIU_VRTX_PARAM_SET	0x15b
76678453a8Sspeer
77*4df55fdeSJanie Lu/*
78*4df55fdeSJanie Lu * The new set of HV APIs to provide the ability
79*4df55fdeSJanie Lu * of a domain to manage multiple NIU resources at once to
80*4df55fdeSJanie Lu * support the KT familty chip having up to 4 NIUs
81*4df55fdeSJanie Lu * per system. The trap # will be the same as those defined
82*4df55fdeSJanie Lu * before 2.0
83*4df55fdeSJanie Lu */
84*4df55fdeSJanie Lu#define	N2NIU_CFGH_RX_LP_SET	0x142
85*4df55fdeSJanie Lu#define	N2NIU_CFGH_TX_LP_SET	0x143
86*4df55fdeSJanie Lu#define	N2NIU_CFGH_RX_LP_GET	0x144
87*4df55fdeSJanie Lu#define	N2NIU_CFGH_TX_LP_GET	0x145
88*4df55fdeSJanie Lu#define	N2NIU_CFGH_VR_ASSIGN	0x146
89*4df55fdeSJanie Lu
9044961713Sgirish	/*
9144961713Sgirish	 * hv_niu_rx_logical_page_conf(uint64_t chidx, uint64_t pgidx,
9244961713Sgirish	 *	uint64_t raddr, uint64_t size)
9344961713Sgirish	 */
9444961713Sgirish	ENTRY(hv_niu_rx_logical_page_conf)
9544961713Sgirish	mov	N2NIU_RX_LP_CONF, %o5
9644961713Sgirish	ta	FAST_TRAP
9744961713Sgirish	retl
9844961713Sgirish	nop
9944961713Sgirish	SET_SIZE(hv_niu_rx_logical_page_conf)
10044961713Sgirish
10144961713Sgirish	/*
10244961713Sgirish	 * hv_niu_rx_logical_page_info(uint64_t chidx, uint64_t pgidx,
10344961713Sgirish	 *	uint64_t *raddr, uint64_t *size)
10444961713Sgirish	 */
10544961713Sgirish	ENTRY(hv_niu_rx_logical_page_info)
10644961713Sgirish	mov	%o2, %g1
10744961713Sgirish	mov	%o3, %g2
10844961713Sgirish	mov	N2NIU_RX_LP_INFO, %o5
10944961713Sgirish	ta	FAST_TRAP
11014ea4bb7Ssd	stx	%o1, [%g1]
11144961713Sgirish	retl
11214ea4bb7Ssd	stx	%o2, [%g2]
11344961713Sgirish	SET_SIZE(hv_niu_rx_logical_page_info)
11444961713Sgirish
11544961713Sgirish	/*
11644961713Sgirish	 * hv_niu_tx_logical_page_conf(uint64_t chidx, uint64_t pgidx,
11744961713Sgirish	 *	uint64_t raddr, uint64_t size)
11844961713Sgirish	 */
11944961713Sgirish	ENTRY(hv_niu_tx_logical_page_conf)
12044961713Sgirish	mov	N2NIU_TX_LP_CONF, %o5
12144961713Sgirish	ta	FAST_TRAP
12244961713Sgirish	retl
12344961713Sgirish	nop
12444961713Sgirish	SET_SIZE(hv_niu_tx_logical_page_conf)
12544961713Sgirish
12644961713Sgirish	/*
12744961713Sgirish	 * hv_niu_tx_logical_page_info(uint64_t chidx, uint64_t pgidx,
12844961713Sgirish	 *	uint64_t *raddr, uint64_t *size)
12944961713Sgirish	 */
13044961713Sgirish	ENTRY(hv_niu_tx_logical_page_info)
13144961713Sgirish	mov	%o2, %g1
13244961713Sgirish	mov	%o3, %g2
13344961713Sgirish	mov	N2NIU_TX_LP_INFO, %o5
13444961713Sgirish	ta	FAST_TRAP
13514ea4bb7Ssd	stx	%o1, [%g1]
13644961713Sgirish	retl
13714ea4bb7Ssd	stx	%o2, [%g2]
13844961713Sgirish	SET_SIZE(hv_niu_tx_logical_page_info)
13944961713Sgirish
140678453a8Sspeer	/*
141678453a8Sspeer	 * hv_niu_vr_assign(uint64_t vridx, uint64_t ldc_id,
14252ccf843Smisaki	 *	uint32_t *cookie)
143678453a8Sspeer	 */
144678453a8Sspeer	ENTRY(hv_niu_vr_assign)
145678453a8Sspeer	mov	%o2, %g1
146678453a8Sspeer	mov	N2NIU_VR_ASSIGN, %o5
147678453a8Sspeer	ta	FAST_TRAP
148678453a8Sspeer	retl
149678453a8Sspeer	stw	%o1, [%g1]
150678453a8Sspeer	SET_SIZE(hv_niu_vr_assign)
151678453a8Sspeer
152678453a8Sspeer	/*
153678453a8Sspeer	 * hv_niu_vr_unassign(uint32_t cookie)
154678453a8Sspeer	 */
155678453a8Sspeer	ENTRY(hv_niu_vr_unassign)
156678453a8Sspeer	mov	N2NIU_VR_UNASSIGN, %o5
157678453a8Sspeer	ta	FAST_TRAP
158678453a8Sspeer	retl
159678453a8Sspeer	nop
160678453a8Sspeer	SET_SIZE(hv_niu_vr_unassign)
161678453a8Sspeer
162678453a8Sspeer	/*
163678453a8Sspeer	 * hv_niu_vr_getinfo(uint32_t cookie, uint64_t &real_start,
16452ccf843Smisaki	 *	uint64_t &size)
165678453a8Sspeer	 */
166678453a8Sspeer	ENTRY(hv_niu_vr_getinfo)
167678453a8Sspeer	mov	%o1, %g1
168678453a8Sspeer	mov	%o2, %g2
169678453a8Sspeer	mov	N2NIU_VR_GETINFO, %o5
170678453a8Sspeer	ta	FAST_TRAP
171678453a8Sspeer	stx	%o1, [%g1]
172678453a8Sspeer	retl
173678453a8Sspeer	stx	%o2, [%g2]
174678453a8Sspeer	SET_SIZE(hv_niu_vr_getinfo)
175678453a8Sspeer
176678453a8Sspeer	/*
177678453a8Sspeer	 * hv_niu_vr_get_rxmap(uint32_t cookie, uint64_t *dma_map)
178678453a8Sspeer	 */
179678453a8Sspeer	ENTRY(hv_niu_vr_get_rxmap)
180678453a8Sspeer	mov	%o1, %g1
181678453a8Sspeer	mov	N2NIU_VR_GET_RX_MAP, %o5
182678453a8Sspeer	ta	FAST_TRAP
183678453a8Sspeer	retl
184678453a8Sspeer	stx	%o1, [%g1]
185678453a8Sspeer	SET_SIZE(hv_niu_vr_get_rxmap)
186678453a8Sspeer
187678453a8Sspeer	/*
188678453a8Sspeer	 * hv_niu_vr_get_txmap(uint32_t cookie, uint64_t *dma_map)
189678453a8Sspeer	 */
190678453a8Sspeer	ENTRY(hv_niu_vr_get_txmap)
191678453a8Sspeer	mov	%o1, %g1
192678453a8Sspeer	mov	N2NIU_VR_GET_TX_MAP, %o5
193678453a8Sspeer	ta	FAST_TRAP
194678453a8Sspeer	retl
195678453a8Sspeer	stx	%o1, [%g1]
196678453a8Sspeer	SET_SIZE(hv_niu_vr_get_txmap)
197678453a8Sspeer
198678453a8Sspeer	/*
199678453a8Sspeer	 * hv_niu_rx_dma_assign(uint32_t cookie, uint64_t chidx,
20052ccf843Smisaki	 *	uint64_t *vchidx)
201678453a8Sspeer	 */
202678453a8Sspeer	ENTRY(hv_niu_rx_dma_assign)
203678453a8Sspeer	mov	%o2, %g1
204678453a8Sspeer	mov	N2NIU_VR_RX_DMA_ASSIGN, %o5
205678453a8Sspeer	ta	FAST_TRAP
206678453a8Sspeer	retl
207678453a8Sspeer	stx	%o1, [%g1]
208678453a8Sspeer	SET_SIZE(hv_niu_rx_dma_assign)
209678453a8Sspeer
210678453a8Sspeer	/*
211678453a8Sspeer	 * hv_niu_rx_dma_unassign(uint32_t cookie, uint64_t vchidx)
212678453a8Sspeer	 */
213678453a8Sspeer	ENTRY(hv_niu_rx_dma_unassign)
214678453a8Sspeer	mov	N2NIU_VR_RX_DMA_UNASSIGN, %o5
215678453a8Sspeer	ta	FAST_TRAP
216678453a8Sspeer	retl
217678453a8Sspeer	nop
218678453a8Sspeer	SET_SIZE(hv_niu_rx_dma_unassign)
219678453a8Sspeer
220678453a8Sspeer	/*
221678453a8Sspeer	 * hv_niu_tx_dma_assign(uint32_t cookie, uint64_t chidx,
22252ccf843Smisaki	 *	uint64_t *vchidx)
223678453a8Sspeer	 */
224678453a8Sspeer	ENTRY(hv_niu_tx_dma_assign)
225678453a8Sspeer	mov	%o2, %g1
226678453a8Sspeer	mov	N2NIU_VR_TX_DMA_ASSIGN, %o5
227678453a8Sspeer	ta	FAST_TRAP
228678453a8Sspeer	retl
229678453a8Sspeer	stx	%o1, [%g1]
230678453a8Sspeer	SET_SIZE(hv_niu_tx_dma_assign)
231678453a8Sspeer
232678453a8Sspeer	/*
233678453a8Sspeer	 * hv_niu_tx_dma_unassign(uint32_t cookie, uint64_t vchidx)
234678453a8Sspeer	 */
235678453a8Sspeer	ENTRY(hv_niu_tx_dma_unassign)
236678453a8Sspeer	mov	N2NIU_VR_TX_DMA_UNASSIGN, %o5
237678453a8Sspeer	ta	FAST_TRAP
238678453a8Sspeer	retl
239678453a8Sspeer	nop
240678453a8Sspeer	SET_SIZE(hv_niu_tx_dma_unassign)
241678453a8Sspeer
242678453a8Sspeer	/*
243678453a8Sspeer	 * hv_niu_vrrx_logical_page_conf(uint32_t cookie, uint64_t chidx,
24452ccf843Smisaki	 *	uint64_t pgidx, uint64_t raddr, uint64_t size)
245678453a8Sspeer	 */
246678453a8Sspeer	ENTRY(hv_niu_vrrx_logical_page_conf)
247678453a8Sspeer	mov	N2NIU_VRRX_LP_SET, %o5
248678453a8Sspeer	ta	FAST_TRAP
249678453a8Sspeer	retl
250678453a8Sspeer	nop
251678453a8Sspeer	SET_SIZE(hv_niu_vrrx_logical_page_conf)
252678453a8Sspeer
253678453a8Sspeer	/*
254678453a8Sspeer	 * hv_niu_vrrx_logical_page_info(uint32_t cookie, uint64_t chidx,
25552ccf843Smisaki	 *	uint64_t pgidx, uint64_t *raddr, uint64_t *size)
256678453a8Sspeer	 */
257678453a8Sspeer	ENTRY(hv_niu_vrrx_logical_page_info)
258678453a8Sspeer	mov	%o3, %g1
259678453a8Sspeer	mov	%o4, %g2
260678453a8Sspeer	mov	N2NIU_VRRX_LP_GET, %o5
261678453a8Sspeer	ta	FAST_TRAP
262678453a8Sspeer	stx	%o1, [%g1]
263678453a8Sspeer	retl
264678453a8Sspeer	stx	%o2, [%g2]
265678453a8Sspeer	SET_SIZE(hv_niu_vrrx_logical_page_info)
266678453a8Sspeer
267678453a8Sspeer	/*
268678453a8Sspeer	 * hv_niu_vrtx_logical_page_conf(uint32_t cookie, uint64_t chidx,
26952ccf843Smisaki	 *	uint64_t pgidx, uint64_t raddr, uint64_t size)
270678453a8Sspeer	 */
271678453a8Sspeer	ENTRY(hv_niu_vrtx_logical_page_conf)
272678453a8Sspeer	mov	N2NIU_VRTX_LP_SET, %o5
273678453a8Sspeer	ta	FAST_TRAP
274678453a8Sspeer	retl
275678453a8Sspeer	nop
276678453a8Sspeer	SET_SIZE(hv_niu_vrtx_logical_page_conf)
277678453a8Sspeer
278678453a8Sspeer	/*
279678453a8Sspeer	 * hv_niu_vrtx_logical_page_info(uint32_t cookie, uint64_t chidx,
28052ccf843Smisaki	 *	uint64_t pgidx, uint64_t *raddr, uint64_t *size)
281678453a8Sspeer	 */
282678453a8Sspeer	ENTRY(hv_niu_vrtx_logical_page_info)
283678453a8Sspeer	mov	%o3, %g1
284678453a8Sspeer	mov	%o4, %g2
285678453a8Sspeer	mov	N2NIU_VRTX_LP_GET, %o5
286678453a8Sspeer	ta	FAST_TRAP
287678453a8Sspeer	stx	%o1, [%g1]
288678453a8Sspeer	retl
289678453a8Sspeer	stx	%o2, [%g2]
290678453a8Sspeer	SET_SIZE(hv_niu_vrtx_logical_page_info)
291678453a8Sspeer
292678453a8Sspeer	/*
293678453a8Sspeer	 * hv_niu_vrrx_getinfo(uint32_t cookie, uint64_t vridx,
294678453a8Sspeer	 *	uint64_t *group, uint64_t *logdev)
295678453a8Sspeer	 */
296678453a8Sspeer	ENTRY(hv_niu_vrrx_getinfo)
297678453a8Sspeer	mov	%o2, %g1
298678453a8Sspeer	mov	%o3, %g2
299678453a8Sspeer	mov	N2NIU_VRRX_GET_INFO, %o5
300678453a8Sspeer	ta	FAST_TRAP
301678453a8Sspeer	stx	%o2, [%g2]
302678453a8Sspeer	retl
303678453a8Sspeer	stx	%o1, [%g1]
304678453a8Sspeer	SET_SIZE(hv_niu_vrrx_getinfo)
305678453a8Sspeer
306678453a8Sspeer	/*
307678453a8Sspeer	 * hv_niu_vrtx_getinfo(uint32_t cookie, uint64_t vridx,
308678453a8Sspeer	 *	uint64_t *group, uint64_t *logdev)
309678453a8Sspeer	 */
310678453a8Sspeer	ENTRY(hv_niu_vrtx_getinfo)
311678453a8Sspeer	mov	%o2, %g1
312678453a8Sspeer	mov	%o3, %g2
313678453a8Sspeer	mov	N2NIU_VRTX_GET_INFO, %o5
314678453a8Sspeer	ta	FAST_TRAP
315678453a8Sspeer	stx	%o2, [%g2]
316678453a8Sspeer	retl
317678453a8Sspeer	stx	%o1, [%g1]
318678453a8Sspeer	SET_SIZE(hv_niu_vrtx_getinfo)
319678453a8Sspeer
320678453a8Sspeer	/*
321678453a8Sspeer	 * hv_niu_vrrx_set_ino(uint32_t cookie, uint64_t vridx, uint32_t ino)
322678453a8Sspeer	 */
323678453a8Sspeer	ENTRY(hv_niu_vrrx_set_ino)
324678453a8Sspeer	mov	N2NIU_VRRX_SET_INO, %o5
325678453a8Sspeer	ta	FAST_TRAP
326678453a8Sspeer	retl
327678453a8Sspeer	nop
328678453a8Sspeer	SET_SIZE(hv_niu_vrrx_set_ino)
329678453a8Sspeer
330678453a8Sspeer	/*
331678453a8Sspeer	 * hv_niu_vrtx_set_ino(uint32_t cookie, uint64_t vridx, uint32_t ino)
332678453a8Sspeer	 */
333678453a8Sspeer	ENTRY(hv_niu_vrtx_set_ino)
334678453a8Sspeer	mov	N2NIU_VRTX_SET_INO, %o5
335678453a8Sspeer	ta	FAST_TRAP
336678453a8Sspeer	retl
337678453a8Sspeer	nop
338678453a8Sspeer	SET_SIZE(hv_niu_vrtx_set_ino)
339678453a8Sspeer
340678453a8Sspeer	/*
34152ccf843Smisaki	 * hv_niu_vrrx_param_get(uint32_t cookie, uint64_t vridx,
34252ccf843Smisaki	 *	uint64_t param, uint64_t *value)
343678453a8Sspeer	 *
344678453a8Sspeer	 */
345678453a8Sspeer	ENTRY(hv_niu_vrrx_param_get)
346678453a8Sspeer	mov	%o3, %g1
347678453a8Sspeer	mov	N2NIU_VRRX_PARAM_GET, %o5
348678453a8Sspeer	ta	FAST_TRAP
349678453a8Sspeer	retl
350678453a8Sspeer	stx	%o1, [%g1]
351678453a8Sspeer	SET_SIZE(hv_niu_vrrx_param_get)
352678453a8Sspeer
353678453a8Sspeer	/*
35452ccf843Smisaki	 * hv_niu_vrrx_param_set(uint32_t cookie, uint64_t vridx,
35552ccf843Smisaki	 *	uint64_t param, uint64_t value)
356678453a8Sspeer	 *
357678453a8Sspeer	 */
358678453a8Sspeer	ENTRY(hv_niu_vrrx_param_set)
359678453a8Sspeer	mov	N2NIU_VRRX_PARAM_SET, %o5
360678453a8Sspeer	ta	FAST_TRAP
361678453a8Sspeer	retl
362678453a8Sspeer	nop
363678453a8Sspeer	SET_SIZE(hv_niu_vrrx_param_set)
364678453a8Sspeer
365678453a8Sspeer	/*
36652ccf843Smisaki	 * hv_niu_vrtx_param_get(uint32_t cookie, uint64_t vridx,
36752ccf843Smisaki	 *	uint64_t param, uint64_t *value)
368678453a8Sspeer	 *
369678453a8Sspeer	 */
370678453a8Sspeer	ENTRY(hv_niu_vrtx_param_get)
371678453a8Sspeer	mov	%o3, %g1
372678453a8Sspeer	mov	N2NIU_VRTX_PARAM_GET, %o5
373678453a8Sspeer	ta	FAST_TRAP
374678453a8Sspeer	retl
375678453a8Sspeer	stx	%o1, [%g1]
376678453a8Sspeer	SET_SIZE(hv_niu_vrtx_param_get)
377678453a8Sspeer
378678453a8Sspeer	/*
37952ccf843Smisaki	 * hv_niu_vrtx_param_set(uint32_t cookie, uint64_t vridx,
38052ccf843Smisaki	 *	uint64_t param, uint64_t value)
381678453a8Sspeer	 *
382678453a8Sspeer	 */
383678453a8Sspeer	ENTRY(hv_niu_vrtx_param_set)
384678453a8Sspeer	mov	N2NIU_VRTX_PARAM_SET, %o5
385678453a8Sspeer	ta	FAST_TRAP
386678453a8Sspeer	retl
387678453a8Sspeer	nop
388678453a8Sspeer	SET_SIZE(hv_niu_vrtx_param_set)
389678453a8Sspeer
390*4df55fdeSJanie Lu	/*
391*4df55fdeSJanie Lu	 * Interfaces functions which require the configuration handle.
392*4df55fdeSJanie Lu	 */
393*4df55fdeSJanie Lu	/*
394*4df55fdeSJanie Lu	 * hv_niu__cfgh_rx_logical_page_conf(uint64_t cfgh, uint64_t chidx,
395*4df55fdeSJanie Lu	 *    uint64_t pgidx, uint64_t raddr, uint64_t size)
396*4df55fdeSJanie Lu	 */
397*4df55fdeSJanie Lu	ENTRY(hv_niu_cfgh_rx_logical_page_conf)
398*4df55fdeSJanie Lu	mov	N2NIU_RX_LP_CONF, %o5
399*4df55fdeSJanie Lu	ta	FAST_TRAP
400*4df55fdeSJanie Lu	retl
401*4df55fdeSJanie Lu	nop
402*4df55fdeSJanie Lu	SET_SIZE(hv_niu_cfgh_rx_logical_page_conf)
403*4df55fdeSJanie Lu
404*4df55fdeSJanie Lu	/*
405*4df55fdeSJanie Lu	 * hv_niu__cfgh_rx_logical_page_info(uint64_t cfgh, uint64_t chidx,
406*4df55fdeSJanie Lu	 *    uint64_t pgidx, uint64_t *raddr, uint64_t *size)
407*4df55fdeSJanie Lu	 */
408*4df55fdeSJanie Lu	ENTRY(hv_niu_cfgh_rx_logical_page_info)
409*4df55fdeSJanie Lu	mov	%o3, %g1
410*4df55fdeSJanie Lu	mov	%o4, %g2
411*4df55fdeSJanie Lu	mov	N2NIU_RX_LP_INFO, %o5
412*4df55fdeSJanie Lu	ta	FAST_TRAP
413*4df55fdeSJanie Lu	stx	%o1, [%g1]
414*4df55fdeSJanie Lu	retl
415*4df55fdeSJanie Lu	stx	%o2, [%g2]
416*4df55fdeSJanie Lu	SET_SIZE(hv_niu_cfgh_rx_logical_page_info)
417*4df55fdeSJanie Lu
418*4df55fdeSJanie Lu	/*
419*4df55fdeSJanie Lu	 * hv_niu_cfgh_tx_logical_page_conf(uint64_t cfgh, uint64_t chidx,
420*4df55fdeSJanie Lu	 *    uint64_t pgidx, uint64_t raddr, uint64_t size)
421*4df55fdeSJanie Lu	 */
422*4df55fdeSJanie Lu	ENTRY(hv_niu_cfgh_tx_logical_page_conf)
423*4df55fdeSJanie Lu	mov	N2NIU_TX_LP_CONF, %o5
424*4df55fdeSJanie Lu	ta	FAST_TRAP
425*4df55fdeSJanie Lu	retl
426*4df55fdeSJanie Lu	nop
427*4df55fdeSJanie Lu	SET_SIZE(hv_niu_cfgh_tx_logical_page_conf)
428*4df55fdeSJanie Lu
429*4df55fdeSJanie Lu	/*
430*4df55fdeSJanie Lu	 * hv_niu_cfgh_tx_logical_page_info(uint64_t cfgh, uint64_t chidx,
431*4df55fdeSJanie Lu	 *    uint64_t pgidx, uint64_t *raddr, uint64_t *size)
432*4df55fdeSJanie Lu	 */
433*4df55fdeSJanie Lu	ENTRY(hv_niu_cfgh_tx_logical_page_info)
434*4df55fdeSJanie Lu	mov	%o3, %g1
435*4df55fdeSJanie Lu	mov	%o4, %g2
436*4df55fdeSJanie Lu	mov	N2NIU_TX_LP_INFO, %o5
437*4df55fdeSJanie Lu	ta	FAST_TRAP
438*4df55fdeSJanie Lu	stx	%o1, [%g1]
439*4df55fdeSJanie Lu	retl
440*4df55fdeSJanie Lu	stx	%o2, [%g2]
441*4df55fdeSJanie Lu	SET_SIZE(hv_niu_cfgh_tx_logical_page_info)
442*4df55fdeSJanie Lu
443*4df55fdeSJanie Lu	/*
444*4df55fdeSJanie Lu	 * hv_niu_cfgh_vr_assign(uint64_t cfgh, uint64_t vridx, uint64_t ldc_id,
445*4df55fdeSJanie Lu	 *     uint32_t *cookie)
446*4df55fdeSJanie Lu	 */
447*4df55fdeSJanie Lu	ENTRY(hv_niu_cfgh_vr_assign)
448*4df55fdeSJanie Lu	mov	%o3, %g1
449*4df55fdeSJanie Lu	mov	N2NIU_VR_ASSIGN, %o5
450*4df55fdeSJanie Lu	ta	FAST_TRAP
451*4df55fdeSJanie Lu	retl
452*4df55fdeSJanie Lu	stw	%o1, [%g1]
453*4df55fdeSJanie Lu	SET_SIZE(hv_niu_cfgh_vr_assign)
454*4df55fdeSJanie Lu
455da14cebeSEric Cheng#endif /*defined(sun4v)*/
456