144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 2259ac0c16Sdavemq * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 2344961713Sgirish * Use is subject to license terms. 2444961713Sgirish */ 2544961713Sgirish 2644961713Sgirish #pragma ident "%Z%%M% %I% %E% SMI" 2744961713Sgirish 2844961713Sgirish #include <nxge_impl.h> 2944961713Sgirish #include <npi_mac.h> 3044961713Sgirish #include <npi_rxdma.h> 3144961713Sgirish 3244961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3344961713Sgirish static int nxge_herr2kerr(uint64_t); 3444961713Sgirish #endif 3544961713Sgirish 3644961713Sgirish /* 3744961713Sgirish * The following interfaces are controlled by the 3844961713Sgirish * function control registers. Some global registers 3944961713Sgirish * are to be initialized by only byt one of the 2/4 functions. 4044961713Sgirish * Use the test and set register. 4144961713Sgirish */ 4244961713Sgirish /*ARGSUSED*/ 4344961713Sgirish nxge_status_t 4444961713Sgirish nxge_test_and_set(p_nxge_t nxgep, uint8_t tas) 4544961713Sgirish { 4644961713Sgirish npi_handle_t handle; 4744961713Sgirish npi_status_t rs = NPI_SUCCESS; 4844961713Sgirish 4944961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 5044961713Sgirish if ((rs = npi_dev_func_sr_sr_get_set_clear(handle, tas)) 5144961713Sgirish != NPI_SUCCESS) { 5244961713Sgirish return (NXGE_ERROR | rs); 5344961713Sgirish } 5444961713Sgirish 5544961713Sgirish return (NXGE_OK); 5644961713Sgirish } 5744961713Sgirish 5844961713Sgirish nxge_status_t 5944961713Sgirish nxge_set_fzc_multi_part_ctl(p_nxge_t nxgep, boolean_t mpc) 6044961713Sgirish { 6144961713Sgirish npi_handle_t handle; 6244961713Sgirish npi_status_t rs = NPI_SUCCESS; 6344961713Sgirish 6444961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_set_fzc_multi_part_ctl")); 6544961713Sgirish 6644961713Sgirish /* 6744961713Sgirish * In multi-partitioning, the partition manager 6844961713Sgirish * who owns function zero should set this multi-partition 6944961713Sgirish * control bit. 7044961713Sgirish */ 7144961713Sgirish if (nxgep->use_partition && nxgep->function_num) { 7244961713Sgirish return (NXGE_ERROR); 7344961713Sgirish } 7444961713Sgirish 7544961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 7644961713Sgirish if ((rs = npi_fzc_mpc_set(handle, mpc)) != NPI_SUCCESS) { 7744961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 7844961713Sgirish "<== nxge_set_fzc_multi_part_ctl")); 7944961713Sgirish return (NXGE_ERROR | rs); 8044961713Sgirish } 8144961713Sgirish 8244961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_set_fzc_multi_part_ctl")); 8344961713Sgirish 8444961713Sgirish return (NXGE_OK); 8544961713Sgirish } 8644961713Sgirish 8744961713Sgirish nxge_status_t 8844961713Sgirish nxge_get_fzc_multi_part_ctl(p_nxge_t nxgep, boolean_t *mpc_p) 8944961713Sgirish { 9044961713Sgirish npi_handle_t handle; 9144961713Sgirish npi_status_t rs = NPI_SUCCESS; 9244961713Sgirish 9344961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_get_fzc_multi_part_ctl")); 9444961713Sgirish 9544961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 9644961713Sgirish if ((rs = npi_fzc_mpc_get(handle, mpc_p)) != NPI_SUCCESS) { 9744961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 9844961713Sgirish "<== nxge_set_fzc_multi_part_ctl")); 9944961713Sgirish return (NXGE_ERROR | rs); 10044961713Sgirish } 10144961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_get_fzc_multi_part_ctl")); 10244961713Sgirish 10344961713Sgirish return (NXGE_OK); 10444961713Sgirish } 10544961713Sgirish 10644961713Sgirish /* 10744961713Sgirish * System interrupt registers that are under function zero 10844961713Sgirish * management. 10944961713Sgirish */ 11044961713Sgirish nxge_status_t 11144961713Sgirish nxge_fzc_intr_init(p_nxge_t nxgep) 11244961713Sgirish { 11344961713Sgirish nxge_status_t status = NXGE_OK; 11444961713Sgirish 11544961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_fzc_intr_init")); 11644961713Sgirish 11744961713Sgirish /* Configure the initial timer resolution */ 11844961713Sgirish if ((status = nxge_fzc_intr_tmres_set(nxgep)) != NXGE_OK) { 11944961713Sgirish return (status); 12044961713Sgirish } 12144961713Sgirish 122*2e59129aSraghus if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 12344961713Sgirish /* 12444961713Sgirish * Set up the logical device group's logical devices that 12544961713Sgirish * the group owns. 12644961713Sgirish */ 12759ac0c16Sdavemq if ((status = nxge_fzc_intr_ldg_num_set(nxgep)) != NXGE_OK) 12859ac0c16Sdavemq goto fzc_intr_init_exit; 12944961713Sgirish 13044961713Sgirish /* Configure the system interrupt data */ 13159ac0c16Sdavemq if ((status = nxge_fzc_intr_sid_set(nxgep)) != NXGE_OK) 13259ac0c16Sdavemq goto fzc_intr_init_exit; 13344961713Sgirish } 13444961713Sgirish 13559ac0c16Sdavemq fzc_intr_init_exit: 13659ac0c16Sdavemq 13744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_fzc_intr_init")); 13844961713Sgirish 13944961713Sgirish return (status); 14044961713Sgirish } 14144961713Sgirish 14244961713Sgirish nxge_status_t 14344961713Sgirish nxge_fzc_intr_ldg_num_set(p_nxge_t nxgep) 14444961713Sgirish { 14544961713Sgirish p_nxge_ldg_t ldgp; 14644961713Sgirish p_nxge_ldv_t ldvp; 14744961713Sgirish npi_handle_t handle; 14844961713Sgirish int i, j; 14944961713Sgirish npi_status_t rs = NPI_SUCCESS; 15044961713Sgirish 15144961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_fzc_intr_ldg_num_set")); 15244961713Sgirish 15344961713Sgirish if (nxgep->ldgvp == NULL) { 15444961713Sgirish return (NXGE_ERROR); 15544961713Sgirish } 15644961713Sgirish 15744961713Sgirish ldgp = nxgep->ldgvp->ldgp; 15844961713Sgirish ldvp = nxgep->ldgvp->ldvp; 15944961713Sgirish if (ldgp == NULL || ldvp == NULL) { 16044961713Sgirish return (NXGE_ERROR); 16144961713Sgirish } 16244961713Sgirish 16344961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 16444961713Sgirish 16544961713Sgirish for (i = 0; i < nxgep->ldgvp->ldg_intrs; i++, ldgp++) { 16644961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 16744961713Sgirish "==> nxge_fzc_intr_ldg_num_set " 16844961713Sgirish "<== nxge_f(Neptune): # ldv %d " 16944961713Sgirish "in group %d", ldgp->nldvs, ldgp->ldg)); 17044961713Sgirish 17144961713Sgirish for (j = 0; j < ldgp->nldvs; j++, ldvp++) { 17244961713Sgirish rs = npi_fzc_ldg_num_set(handle, ldvp->ldv, 17344961713Sgirish ldvp->ldg_assigned); 17444961713Sgirish if (rs != NPI_SUCCESS) { 17544961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 17644961713Sgirish "<== nxge_fzc_intr_ldg_num_set failed " 17744961713Sgirish " rs 0x%x ldv %d ldg %d", 17844961713Sgirish rs, ldvp->ldv, ldvp->ldg_assigned)); 17944961713Sgirish return (NXGE_ERROR | rs); 18044961713Sgirish } 18144961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 18244961713Sgirish "<== nxge_fzc_intr_ldg_num_set OK " 18344961713Sgirish " ldv %d ldg %d", 18444961713Sgirish ldvp->ldv, ldvp->ldg_assigned)); 18544961713Sgirish } 18644961713Sgirish } 18744961713Sgirish 18844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_fzc_intr_ldg_num_set")); 18944961713Sgirish 19044961713Sgirish return (NXGE_OK); 19144961713Sgirish } 19244961713Sgirish 19344961713Sgirish nxge_status_t 19444961713Sgirish nxge_fzc_intr_tmres_set(p_nxge_t nxgep) 19544961713Sgirish { 19644961713Sgirish npi_handle_t handle; 19744961713Sgirish npi_status_t rs = NPI_SUCCESS; 19844961713Sgirish 19944961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_fzc_intr_tmrese_set")); 20044961713Sgirish if (nxgep->ldgvp == NULL) { 20144961713Sgirish return (NXGE_ERROR); 20244961713Sgirish } 20344961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 20444961713Sgirish if ((rs = npi_fzc_ldg_timer_res_set(handle, nxgep->ldgvp->tmres))) { 20544961713Sgirish return (NXGE_ERROR | rs); 20644961713Sgirish } 20744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_fzc_intr_tmrese_set")); 20844961713Sgirish 20944961713Sgirish return (NXGE_OK); 21044961713Sgirish } 21144961713Sgirish 21244961713Sgirish nxge_status_t 21344961713Sgirish nxge_fzc_intr_sid_set(p_nxge_t nxgep) 21444961713Sgirish { 21544961713Sgirish npi_handle_t handle; 21644961713Sgirish p_nxge_ldg_t ldgp; 21744961713Sgirish fzc_sid_t sid; 21844961713Sgirish int i; 21944961713Sgirish npi_status_t rs = NPI_SUCCESS; 22044961713Sgirish 22144961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_fzc_intr_sid_set")); 22244961713Sgirish if (nxgep->ldgvp == NULL) { 22344961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 22444961713Sgirish "<== nxge_fzc_intr_sid_set: no ldg")); 22544961713Sgirish return (NXGE_ERROR); 22644961713Sgirish } 22744961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 22844961713Sgirish ldgp = nxgep->ldgvp->ldgp; 22944961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 23044961713Sgirish "==> nxge_fzc_intr_sid_set: #int %d", nxgep->ldgvp->ldg_intrs)); 23144961713Sgirish for (i = 0; i < nxgep->ldgvp->ldg_intrs; i++, ldgp++) { 23244961713Sgirish sid.ldg = ldgp->ldg; 23344961713Sgirish sid.niu = B_FALSE; 23444961713Sgirish sid.func = ldgp->func; 23544961713Sgirish sid.vector = ldgp->vector; 23644961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 23744961713Sgirish "==> nxge_fzc_intr_sid_set(%d): func %d group %d " 23844961713Sgirish "vector %d", 23944961713Sgirish i, sid.func, sid.ldg, sid.vector)); 24044961713Sgirish rs = npi_fzc_sid_set(handle, sid); 24144961713Sgirish if (rs != NPI_SUCCESS) { 24244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 24344961713Sgirish "<== nxge_fzc_intr_sid_set:failed 0x%x", 24444961713Sgirish rs)); 24544961713Sgirish return (NXGE_ERROR | rs); 24644961713Sgirish } 24744961713Sgirish } 24844961713Sgirish 24944961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_fzc_intr_sid_set")); 25044961713Sgirish 25144961713Sgirish return (NXGE_OK); 25244961713Sgirish 25344961713Sgirish } 25444961713Sgirish 25544961713Sgirish /* 25644961713Sgirish * Receive DMA registers that are under function zero 25744961713Sgirish * management. 25844961713Sgirish */ 25944961713Sgirish /*ARGSUSED*/ 26044961713Sgirish nxge_status_t 26144961713Sgirish nxge_init_fzc_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 26244961713Sgirish p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p) 26344961713Sgirish { 26444961713Sgirish nxge_status_t status = NXGE_OK; 26544961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_init_fzc_rxdma_channel")); 26644961713Sgirish 26759ac0c16Sdavemq if (nxgep->niu_type == N2_NIU) { 26844961713Sgirish #ifndef NIU_HV_WORKAROUND 26944961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 27044961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 27159ac0c16Sdavemq "==> nxge_init_fzc_rxdma_channel: N2_NIU - call HV " 27259ac0c16Sdavemq "set up logical pages")); 27344961713Sgirish /* Initialize the RXDMA logical pages */ 27444961713Sgirish status = nxge_init_hv_fzc_rxdma_channel_pages(nxgep, channel, 27544961713Sgirish rbr_p); 27644961713Sgirish if (status != NXGE_OK) { 27744961713Sgirish return (status); 27844961713Sgirish } 27944961713Sgirish #endif 28059ac0c16Sdavemq status = NXGE_OK; 28144961713Sgirish #else 28244961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 28359ac0c16Sdavemq "==> nxge_init_fzc_rxdma_channel: N2_NIU - NEED to " 28459ac0c16Sdavemq "set up logical pages")); 28544961713Sgirish /* Initialize the RXDMA logical pages */ 28644961713Sgirish status = nxge_init_fzc_rxdma_channel_pages(nxgep, channel, 28759ac0c16Sdavemq rbr_p); 28844961713Sgirish if (status != NXGE_OK) { 28944961713Sgirish return (status); 29044961713Sgirish } 29144961713Sgirish #endif 292*2e59129aSraghus } else if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 29359ac0c16Sdavemq /* Initialize the RXDMA logical pages */ 29459ac0c16Sdavemq status = nxge_init_fzc_rxdma_channel_pages(nxgep, 29559ac0c16Sdavemq channel, rbr_p); 29659ac0c16Sdavemq if (status != NXGE_OK) { 29759ac0c16Sdavemq return (status); 29859ac0c16Sdavemq } 29959ac0c16Sdavemq } else { 30059ac0c16Sdavemq return (NXGE_ERROR); 30144961713Sgirish } 30244961713Sgirish 30344961713Sgirish /* Configure RED parameters */ 30444961713Sgirish status = nxge_init_fzc_rxdma_channel_red(nxgep, channel, rcr_p); 30544961713Sgirish 30644961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_init_fzc_rxdma_channel")); 30744961713Sgirish return (status); 30844961713Sgirish } 30944961713Sgirish 31044961713Sgirish /*ARGSUSED*/ 31144961713Sgirish nxge_status_t 31244961713Sgirish nxge_init_fzc_rxdma_channel_pages(p_nxge_t nxgep, 31344961713Sgirish uint16_t channel, p_rx_rbr_ring_t rbrp) 31444961713Sgirish { 31544961713Sgirish npi_handle_t handle; 31644961713Sgirish dma_log_page_t cfg; 31744961713Sgirish npi_status_t rs = NPI_SUCCESS; 31844961713Sgirish 31944961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 32044961713Sgirish "==> nxge_init_fzc_rxdma_channel_pages")); 32144961713Sgirish 32244961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 32344961713Sgirish /* 32444961713Sgirish * Initialize logical page 1. 32544961713Sgirish */ 32644961713Sgirish cfg.func_num = nxgep->function_num; 32744961713Sgirish cfg.page_num = 0; 32844961713Sgirish cfg.valid = rbrp->page_valid.bits.ldw.page0; 32944961713Sgirish cfg.value = rbrp->page_value_1.value; 33044961713Sgirish cfg.mask = rbrp->page_mask_1.value; 33144961713Sgirish cfg.reloc = rbrp->page_reloc_1.value; 33244961713Sgirish rs = npi_rxdma_cfg_logical_page(handle, channel, 33344961713Sgirish (p_dma_log_page_t)&cfg); 33444961713Sgirish if (rs != NPI_SUCCESS) { 33544961713Sgirish return (NXGE_ERROR | rs); 33644961713Sgirish } 33744961713Sgirish 33844961713Sgirish /* 33944961713Sgirish * Initialize logical page 2. 34044961713Sgirish */ 34144961713Sgirish cfg.page_num = 1; 34244961713Sgirish cfg.valid = rbrp->page_valid.bits.ldw.page1; 34344961713Sgirish cfg.value = rbrp->page_value_2.value; 34444961713Sgirish cfg.mask = rbrp->page_mask_2.value; 34544961713Sgirish cfg.reloc = rbrp->page_reloc_2.value; 34644961713Sgirish 34744961713Sgirish rs = npi_rxdma_cfg_logical_page(handle, channel, &cfg); 34844961713Sgirish if (rs != NPI_SUCCESS) { 34944961713Sgirish return (NXGE_ERROR | rs); 35044961713Sgirish } 35144961713Sgirish 35244961713Sgirish /* Initialize the page handle */ 35344961713Sgirish rs = npi_rxdma_cfg_logical_page_handle(handle, channel, 35444961713Sgirish rbrp->page_hdl.bits.ldw.handle); 35544961713Sgirish 35644961713Sgirish if (rs != NPI_SUCCESS) { 35744961713Sgirish return (NXGE_ERROR | rs); 35844961713Sgirish } 35944961713Sgirish 36044961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 36144961713Sgirish "<== nxge_init_fzc_rxdma_channel_pages")); 36244961713Sgirish 36344961713Sgirish return (NXGE_OK); 36444961713Sgirish } 36544961713Sgirish 36644961713Sgirish /*ARGSUSED*/ 36744961713Sgirish nxge_status_t 36844961713Sgirish nxge_init_fzc_rxdma_channel_red(p_nxge_t nxgep, 36944961713Sgirish uint16_t channel, p_rx_rcr_ring_t rcr_p) 37044961713Sgirish { 37144961713Sgirish npi_handle_t handle; 37244961713Sgirish rdc_red_para_t red; 37344961713Sgirish npi_status_t rs = NPI_SUCCESS; 37444961713Sgirish 37544961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_init_fzc_rxdma_channel_red")); 37644961713Sgirish 37744961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 37844961713Sgirish red.value = 0; 37944961713Sgirish red.bits.ldw.win = RXDMA_RED_WINDOW_DEFAULT; 38044961713Sgirish red.bits.ldw.thre = (rcr_p->comp_size - RXDMA_RED_LESS_ENTRIES); 38144961713Sgirish red.bits.ldw.win_syn = RXDMA_RED_WINDOW_DEFAULT; 38244961713Sgirish red.bits.ldw.thre_sync = (rcr_p->comp_size - RXDMA_RED_LESS_ENTRIES); 38344961713Sgirish 38444961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 38544961713Sgirish "==> nxge_init_fzc_rxdma_channel_red(thre_sync %d(%x))", 38644961713Sgirish red.bits.ldw.thre_sync, 38744961713Sgirish red.bits.ldw.thre_sync)); 38844961713Sgirish 38944961713Sgirish rs = npi_rxdma_cfg_wred_param(handle, channel, &red); 39044961713Sgirish if (rs != NPI_SUCCESS) { 39144961713Sgirish return (NXGE_ERROR | rs); 39244961713Sgirish } 39344961713Sgirish 39444961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 39544961713Sgirish "<== nxge_init_fzc_rxdma_channel_red")); 39644961713Sgirish 39744961713Sgirish return (NXGE_OK); 39844961713Sgirish } 39944961713Sgirish 40044961713Sgirish /*ARGSUSED*/ 40144961713Sgirish nxge_status_t 40244961713Sgirish nxge_init_fzc_txdma_channel(p_nxge_t nxgep, uint16_t channel, 40344961713Sgirish p_tx_ring_t tx_ring_p, p_tx_mbox_t mbox_p) 40444961713Sgirish { 40544961713Sgirish nxge_status_t status = NXGE_OK; 40644961713Sgirish 40744961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 40844961713Sgirish "==> nxge_init_fzc_txdma_channel")); 40944961713Sgirish 41059ac0c16Sdavemq if (nxgep->niu_type == N2_NIU) { 41144961713Sgirish #ifndef NIU_HV_WORKAROUND 41244961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 41344961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 41459ac0c16Sdavemq "==> nxge_init_fzc_txdma_channel " 41559ac0c16Sdavemq "N2_NIU: call HV to set up txdma logical pages")); 41644961713Sgirish status = nxge_init_hv_fzc_txdma_channel_pages(nxgep, channel, 41759ac0c16Sdavemq tx_ring_p); 41844961713Sgirish if (status != NXGE_OK) { 41944961713Sgirish return (status); 42044961713Sgirish } 42144961713Sgirish #endif 42259ac0c16Sdavemq status = NXGE_OK; 42344961713Sgirish #else 42444961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 42559ac0c16Sdavemq "==> nxge_init_fzc_txdma_channel " 42659ac0c16Sdavemq "N2_NIU: NEED to set up txdma logical pages")); 42744961713Sgirish /* Initialize the TXDMA logical pages */ 42844961713Sgirish (void) nxge_init_fzc_txdma_channel_pages(nxgep, channel, 42959ac0c16Sdavemq tx_ring_p); 43044961713Sgirish #endif 431*2e59129aSraghus } else if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 43259ac0c16Sdavemq /* Initialize the TXDMA logical pages */ 43359ac0c16Sdavemq (void) nxge_init_fzc_txdma_channel_pages(nxgep, 43459ac0c16Sdavemq channel, tx_ring_p); 43559ac0c16Sdavemq } else { 43659ac0c16Sdavemq return (NXGE_ERROR); 43744961713Sgirish } 43844961713Sgirish 43944961713Sgirish /* 44044961713Sgirish * Configure Transmit DRR Weight parameters 44144961713Sgirish * (It actually programs the TXC max burst register). 44244961713Sgirish */ 44344961713Sgirish (void) nxge_init_fzc_txdma_channel_drr(nxgep, channel, tx_ring_p); 44444961713Sgirish 44544961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 44644961713Sgirish "<== nxge_init_fzc_txdma_channel")); 44744961713Sgirish return (status); 44844961713Sgirish } 44944961713Sgirish 45044961713Sgirish nxge_status_t 45144961713Sgirish nxge_init_fzc_common(p_nxge_t nxgep) 45244961713Sgirish { 45344961713Sgirish nxge_status_t status = NXGE_OK; 45444961713Sgirish 45544961713Sgirish (void) nxge_init_fzc_rx_common(nxgep); 45644961713Sgirish 45744961713Sgirish return (status); 45844961713Sgirish } 45944961713Sgirish 46044961713Sgirish nxge_status_t 46144961713Sgirish nxge_init_fzc_rx_common(p_nxge_t nxgep) 46244961713Sgirish { 46344961713Sgirish npi_handle_t handle; 46444961713Sgirish npi_status_t rs = NPI_SUCCESS; 46544961713Sgirish nxge_status_t status = NXGE_OK; 46644961713Sgirish clock_t lbolt; 46744961713Sgirish 46844961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_init_fzc_rx_common")); 46944961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 47044961713Sgirish if (!handle.regp) { 47144961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 47244961713Sgirish "==> nxge_init_fzc_rx_common null ptr")); 47344961713Sgirish return (NXGE_ERROR); 47444961713Sgirish } 47544961713Sgirish 47644961713Sgirish /* 47744961713Sgirish * Configure the rxdma clock divider 47844961713Sgirish * This is the granularity counter based on 47944961713Sgirish * the hardware system clock (i.e. 300 Mhz) and 48044961713Sgirish * it is running around 3 nanoseconds. 48144961713Sgirish * So, set the clock divider counter to 1000 to get 48244961713Sgirish * microsecond granularity. 48344961713Sgirish * For example, for a 3 microsecond timeout, the timeout 48444961713Sgirish * will be set to 1. 48544961713Sgirish */ 48644961713Sgirish rs = npi_rxdma_cfg_clock_div_set(handle, RXDMA_CK_DIV_DEFAULT); 48744961713Sgirish if (rs != NPI_SUCCESS) 48844961713Sgirish return (NXGE_ERROR | rs); 48944961713Sgirish 49044961713Sgirish #if defined(__i386) 49144961713Sgirish rs = npi_rxdma_cfg_32bitmode_enable(handle); 49244961713Sgirish if (rs != NPI_SUCCESS) 49344961713Sgirish return (NXGE_ERROR | rs); 49444961713Sgirish rs = npi_txdma_mode32_set(handle, B_TRUE); 49544961713Sgirish if (rs != NPI_SUCCESS) 49644961713Sgirish return (NXGE_ERROR | rs); 49744961713Sgirish #endif 49844961713Sgirish 49944961713Sgirish /* 50044961713Sgirish * Enable WRED and program an initial value. 50144961713Sgirish * Use time to set the initial random number. 50244961713Sgirish */ 50344961713Sgirish (void) drv_getparm(LBOLT, &lbolt); 50444961713Sgirish rs = npi_rxdma_cfg_red_rand_init(handle, (uint16_t)lbolt); 50544961713Sgirish if (rs != NPI_SUCCESS) 50644961713Sgirish return (NXGE_ERROR | rs); 50744961713Sgirish 50844961713Sgirish /* Initialize the RDC tables for each group */ 50944961713Sgirish status = nxge_init_fzc_rdc_tbl(nxgep); 51044961713Sgirish 51144961713Sgirish 51244961713Sgirish /* Ethernet Timeout Counter (?) */ 51344961713Sgirish 51444961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 51544961713Sgirish "<== nxge_init_fzc_rx_common:status 0x%08x", status)); 51644961713Sgirish 51744961713Sgirish return (status); 51844961713Sgirish } 51944961713Sgirish 52044961713Sgirish nxge_status_t 52144961713Sgirish nxge_init_fzc_rdc_tbl(p_nxge_t nxgep) 52244961713Sgirish { 52344961713Sgirish npi_handle_t handle; 52444961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 52544961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 52644961713Sgirish p_nxge_rdc_grp_t rdc_grp_p; 52744961713Sgirish uint8_t grp_tbl_id; 52844961713Sgirish int ngrps; 52944961713Sgirish int i; 53044961713Sgirish npi_status_t rs = NPI_SUCCESS; 53144961713Sgirish nxge_status_t status = NXGE_OK; 53244961713Sgirish 53344961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_init_fzc_rdc_tbl")); 53444961713Sgirish 53544961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 53644961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 53744961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 53844961713Sgirish 53944961713Sgirish grp_tbl_id = p_cfgp->start_rdc_grpid; 54044961713Sgirish rdc_grp_p = &p_dma_cfgp->rdc_grps[0]; 54144961713Sgirish ngrps = p_cfgp->max_rdc_grpids; 54244961713Sgirish for (i = 0; i < ngrps; i++, rdc_grp_p++) { 54344961713Sgirish rs = npi_rxdma_cfg_rdc_table(handle, grp_tbl_id++, 54444961713Sgirish rdc_grp_p->rdc); 54544961713Sgirish if (rs != NPI_SUCCESS) { 54644961713Sgirish status = NXGE_ERROR | rs; 54744961713Sgirish break; 54844961713Sgirish } 54944961713Sgirish } 55044961713Sgirish 55144961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_init_fzc_rdc_tbl")); 55244961713Sgirish return (status); 55344961713Sgirish } 55444961713Sgirish 55544961713Sgirish nxge_status_t 55644961713Sgirish nxge_init_fzc_rxdma_port(p_nxge_t nxgep) 55744961713Sgirish { 55844961713Sgirish npi_handle_t handle; 55944961713Sgirish p_nxge_dma_pt_cfg_t p_all_cfgp; 56044961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 56144961713Sgirish hostinfo_t hostinfo; 56244961713Sgirish int i; 56344961713Sgirish npi_status_t rs = NPI_SUCCESS; 56444961713Sgirish p_nxge_class_pt_cfg_t p_class_cfgp; 56544961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_init_fzc_rxdma_port")); 56644961713Sgirish 56744961713Sgirish p_all_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 56844961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_all_cfgp->hw_config; 56944961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 57044961713Sgirish /* 57144961713Sgirish * Initialize the port scheduler DRR weight. 57244961713Sgirish * npi_rxdma_cfg_port_ddr_weight(); 57344961713Sgirish */ 57444961713Sgirish 575*2e59129aSraghus if ((nxgep->mac.portmode == PORT_1G_COPPER) || 576*2e59129aSraghus (nxgep->mac.portmode == PORT_1G_FIBER) || 577*2e59129aSraghus (nxgep->mac.portmode == PORT_1G_SERDES)) { 578*2e59129aSraghus rs = npi_rxdma_cfg_port_ddr_weight(handle, 579*2e59129aSraghus nxgep->function_num, NXGE_RX_DRR_WT_1G); 580*2e59129aSraghus if (rs != NPI_SUCCESS) { 581*2e59129aSraghus return (NXGE_ERROR | rs); 58244961713Sgirish } 58344961713Sgirish } 58444961713Sgirish 58544961713Sgirish /* Program the default RDC of a port */ 58644961713Sgirish rs = npi_rxdma_cfg_default_port_rdc(handle, nxgep->function_num, 58744961713Sgirish p_cfgp->def_rdc); 58844961713Sgirish if (rs != NPI_SUCCESS) { 58944961713Sgirish return (NXGE_ERROR | rs); 59044961713Sgirish } 59144961713Sgirish 59244961713Sgirish /* 59344961713Sgirish * Configure the MAC host info table with RDC tables 59444961713Sgirish */ 59544961713Sgirish hostinfo.value = 0; 59644961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 59744961713Sgirish for (i = 0; i < p_cfgp->max_macs; i++) { 59844961713Sgirish hostinfo.bits.w0.rdc_tbl_num = p_cfgp->start_rdc_grpid; 59944961713Sgirish hostinfo.bits.w0.mac_pref = p_cfgp->mac_pref; 60044961713Sgirish if (p_class_cfgp->mac_host_info[i].flag) { 60144961713Sgirish hostinfo.bits.w0.rdc_tbl_num = 60244961713Sgirish p_class_cfgp->mac_host_info[i].rdctbl; 60344961713Sgirish hostinfo.bits.w0.mac_pref = 60444961713Sgirish p_class_cfgp->mac_host_info[i].mpr_npr; 60544961713Sgirish } 60644961713Sgirish 60744961713Sgirish rs = npi_mac_hostinfo_entry(handle, OP_SET, 60844961713Sgirish nxgep->function_num, i, &hostinfo); 60944961713Sgirish if (rs != NPI_SUCCESS) 61044961713Sgirish return (NXGE_ERROR | rs); 61144961713Sgirish } 61244961713Sgirish 61344961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 61444961713Sgirish "<== nxge_init_fzc_rxdma_port rs 0x%08x", rs)); 61544961713Sgirish 61644961713Sgirish return (NXGE_OK); 61744961713Sgirish 61844961713Sgirish } 61944961713Sgirish 62044961713Sgirish nxge_status_t 62144961713Sgirish nxge_fzc_dmc_def_port_rdc(p_nxge_t nxgep, uint8_t port, uint16_t rdc) 62244961713Sgirish { 62344961713Sgirish npi_status_t rs = NPI_SUCCESS; 62444961713Sgirish rs = npi_rxdma_cfg_default_port_rdc(nxgep->npi_reg_handle, 62544961713Sgirish port, rdc); 62644961713Sgirish if (rs & NPI_FAILURE) 62744961713Sgirish return (NXGE_ERROR | rs); 62844961713Sgirish return (NXGE_OK); 62944961713Sgirish } 63044961713Sgirish 63144961713Sgirish nxge_status_t 63244961713Sgirish nxge_init_fzc_txdma_channel_pages(p_nxge_t nxgep, uint16_t channel, 63344961713Sgirish p_tx_ring_t tx_ring_p) 63444961713Sgirish { 63544961713Sgirish npi_handle_t handle; 63644961713Sgirish dma_log_page_t cfg; 63744961713Sgirish npi_status_t rs = NPI_SUCCESS; 63844961713Sgirish 63944961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 64044961713Sgirish "==> nxge_init_fzc_txdma_channel_pages")); 64144961713Sgirish 64244961713Sgirish #ifndef NIU_HV_WORKAROUND 64344961713Sgirish if (nxgep->niu_type == N2_NIU) { 64444961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 64544961713Sgirish "<== nxge_init_fzc_txdma_channel_pages: " 64644961713Sgirish "N2_NIU: no need to set txdma logical pages")); 64744961713Sgirish return (NXGE_OK); 64844961713Sgirish } 64944961713Sgirish #else 65044961713Sgirish if (nxgep->niu_type == N2_NIU) { 65144961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 65244961713Sgirish "<== nxge_init_fzc_txdma_channel_pages: " 65344961713Sgirish "N2_NIU: NEED to set txdma logical pages")); 65444961713Sgirish } 65544961713Sgirish #endif 65644961713Sgirish 65744961713Sgirish /* 65844961713Sgirish * Initialize logical page 1. 65944961713Sgirish */ 66044961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 66144961713Sgirish cfg.func_num = nxgep->function_num; 66244961713Sgirish cfg.page_num = 0; 66344961713Sgirish cfg.valid = tx_ring_p->page_valid.bits.ldw.page0; 66444961713Sgirish cfg.value = tx_ring_p->page_value_1.value; 66544961713Sgirish cfg.mask = tx_ring_p->page_mask_1.value; 66644961713Sgirish cfg.reloc = tx_ring_p->page_reloc_1.value; 66744961713Sgirish 66844961713Sgirish rs = npi_txdma_log_page_set(handle, channel, 66944961713Sgirish (p_dma_log_page_t)&cfg); 67044961713Sgirish if (rs != NPI_SUCCESS) { 67144961713Sgirish return (NXGE_ERROR | rs); 67244961713Sgirish } 67344961713Sgirish 67444961713Sgirish /* 67544961713Sgirish * Initialize logical page 2. 67644961713Sgirish */ 67744961713Sgirish cfg.page_num = 1; 67844961713Sgirish cfg.valid = tx_ring_p->page_valid.bits.ldw.page1; 67944961713Sgirish cfg.value = tx_ring_p->page_value_2.value; 68044961713Sgirish cfg.mask = tx_ring_p->page_mask_2.value; 68144961713Sgirish cfg.reloc = tx_ring_p->page_reloc_2.value; 68244961713Sgirish 68344961713Sgirish rs = npi_txdma_log_page_set(handle, channel, &cfg); 68444961713Sgirish if (rs != NPI_SUCCESS) { 68544961713Sgirish return (NXGE_ERROR | rs); 68644961713Sgirish } 68744961713Sgirish 68844961713Sgirish /* Initialize the page handle */ 68944961713Sgirish rs = npi_txdma_log_page_handle_set(handle, channel, 69044961713Sgirish &tx_ring_p->page_hdl); 69144961713Sgirish 69244961713Sgirish if (rs == NPI_SUCCESS) { 69344961713Sgirish return (NXGE_OK); 69444961713Sgirish } else { 69544961713Sgirish return (NXGE_ERROR | rs); 69644961713Sgirish } 69744961713Sgirish } 69844961713Sgirish 69944961713Sgirish 70044961713Sgirish nxge_status_t 70144961713Sgirish nxge_init_fzc_txdma_channel_drr(p_nxge_t nxgep, uint16_t channel, 70244961713Sgirish p_tx_ring_t tx_ring_p) 70344961713Sgirish { 70444961713Sgirish npi_status_t rs = NPI_SUCCESS; 70544961713Sgirish npi_handle_t handle; 70644961713Sgirish 70744961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 70844961713Sgirish rs = npi_txc_dma_max_burst_set(handle, channel, 70944961713Sgirish tx_ring_p->max_burst.value); 71044961713Sgirish if (rs == NPI_SUCCESS) { 71144961713Sgirish return (NXGE_OK); 71244961713Sgirish } else { 71344961713Sgirish return (NXGE_ERROR | rs); 71444961713Sgirish } 71544961713Sgirish } 71644961713Sgirish 71744961713Sgirish nxge_status_t 71844961713Sgirish nxge_fzc_sys_err_mask_set(p_nxge_t nxgep, uint64_t mask) 71944961713Sgirish { 72044961713Sgirish npi_status_t rs = NPI_SUCCESS; 72144961713Sgirish npi_handle_t handle; 72244961713Sgirish 72344961713Sgirish handle = NXGE_DEV_NPI_HANDLE(nxgep); 72444961713Sgirish rs = npi_fzc_sys_err_mask_set(handle, mask); 72544961713Sgirish if (rs == NPI_SUCCESS) { 72644961713Sgirish return (NXGE_OK); 72744961713Sgirish } else { 72844961713Sgirish return (NXGE_ERROR | rs); 72944961713Sgirish } 73044961713Sgirish } 73144961713Sgirish 73244961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 73344961713Sgirish nxge_status_t 73444961713Sgirish nxge_init_hv_fzc_txdma_channel_pages(p_nxge_t nxgep, uint16_t channel, 73544961713Sgirish p_tx_ring_t tx_ring_p) 73644961713Sgirish { 73744961713Sgirish int err; 73844961713Sgirish uint64_t hverr; 73944961713Sgirish #ifdef DEBUG 74044961713Sgirish uint64_t ra, size; 74144961713Sgirish #endif 74244961713Sgirish 74344961713Sgirish NXGE_DEBUG_MSG((nxgep, TX_CTL, 74444961713Sgirish "==> nxge_init_hv_fzc_txdma_channel_pages")); 74544961713Sgirish 74644961713Sgirish if (tx_ring_p->hv_set) { 74744961713Sgirish return (NXGE_OK); 74844961713Sgirish } 74944961713Sgirish 75044961713Sgirish /* 75144961713Sgirish * Initialize logical page 1 for data buffers. 75244961713Sgirish */ 75344961713Sgirish hverr = hv_niu_tx_logical_page_conf((uint64_t)channel, 75444961713Sgirish (uint64_t)0, 75544961713Sgirish tx_ring_p->hv_tx_buf_base_ioaddr_pp, 75644961713Sgirish tx_ring_p->hv_tx_buf_ioaddr_size); 75744961713Sgirish 75844961713Sgirish err = (nxge_status_t)nxge_herr2kerr(hverr); 75944961713Sgirish if (err != 0) { 76044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 76144961713Sgirish "<== nxge_init_hv_fzc_txdma_channel_pages: channel %d " 76244961713Sgirish "error status 0x%x " 76344961713Sgirish "(page 0 data buf) hverr 0x%llx " 76444961713Sgirish "ioaddr_pp $%p " 76544961713Sgirish "size 0x%llx ", 76644961713Sgirish channel, 76744961713Sgirish err, 76844961713Sgirish hverr, 76944961713Sgirish tx_ring_p->hv_tx_buf_base_ioaddr_pp, 77044961713Sgirish tx_ring_p->hv_tx_buf_ioaddr_size)); 77144961713Sgirish return (NXGE_ERROR | err); 77244961713Sgirish } 77344961713Sgirish 77444961713Sgirish #ifdef DEBUG 77544961713Sgirish ra = size = 0; 77644961713Sgirish hverr = hv_niu_tx_logical_page_info((uint64_t)channel, 77744961713Sgirish (uint64_t)0, 77844961713Sgirish &ra, 77944961713Sgirish &size); 78044961713Sgirish 78144961713Sgirish NXGE_DEBUG_MSG((nxgep, TX_CTL, 78244961713Sgirish "==> nxge_init_hv_fzc_txdma_channel_pages: channel %d " 78344961713Sgirish "ok status 0x%x " 78444961713Sgirish "(page 0 data buf) hverr 0x%llx " 78544961713Sgirish "set ioaddr_pp $%p " 78644961713Sgirish "set size 0x%llx " 78744961713Sgirish "get ra ioaddr_pp $%p " 78844961713Sgirish "get size 0x%llx ", 78944961713Sgirish channel, 79044961713Sgirish err, 79144961713Sgirish hverr, 79244961713Sgirish tx_ring_p->hv_tx_buf_base_ioaddr_pp, 79344961713Sgirish tx_ring_p->hv_tx_buf_ioaddr_size, 79444961713Sgirish ra, 79544961713Sgirish size)); 79644961713Sgirish #endif 79744961713Sgirish 79844961713Sgirish NXGE_DEBUG_MSG((nxgep, TX_CTL, 79944961713Sgirish "==> nxge_init_hv_fzc_txdma_channel_pages: channel %d " 80044961713Sgirish "(page 0 data buf) hverr 0x%llx " 80144961713Sgirish "ioaddr_pp $%p " 80244961713Sgirish "size 0x%llx ", 80344961713Sgirish channel, 80444961713Sgirish hverr, 80544961713Sgirish tx_ring_p->hv_tx_buf_base_ioaddr_pp, 80644961713Sgirish tx_ring_p->hv_tx_buf_ioaddr_size)); 80744961713Sgirish 80844961713Sgirish /* 80944961713Sgirish * Initialize logical page 2 for control buffers. 81044961713Sgirish */ 81144961713Sgirish hverr = hv_niu_tx_logical_page_conf((uint64_t)channel, 81244961713Sgirish (uint64_t)1, 81344961713Sgirish tx_ring_p->hv_tx_cntl_base_ioaddr_pp, 81444961713Sgirish tx_ring_p->hv_tx_cntl_ioaddr_size); 81544961713Sgirish 81644961713Sgirish err = (nxge_status_t)nxge_herr2kerr(hverr); 81744961713Sgirish 81844961713Sgirish NXGE_DEBUG_MSG((nxgep, TX_CTL, 81944961713Sgirish "==> nxge_init_hv_fzc_txdma_channel_pages: channel %d" 82044961713Sgirish "ok status 0x%x " 82144961713Sgirish "(page 1 cntl buf) hverr 0x%llx " 82244961713Sgirish "ioaddr_pp $%p " 82344961713Sgirish "size 0x%llx ", 82444961713Sgirish channel, 82544961713Sgirish err, 82644961713Sgirish hverr, 82744961713Sgirish tx_ring_p->hv_tx_cntl_base_ioaddr_pp, 82844961713Sgirish tx_ring_p->hv_tx_cntl_ioaddr_size)); 82944961713Sgirish 83044961713Sgirish if (err != 0) { 83144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 83244961713Sgirish "<== nxge_init_hv_fzc_txdma_channel_pages: channel %d" 83344961713Sgirish "error status 0x%x " 83444961713Sgirish "(page 1 cntl buf) hverr 0x%llx " 83544961713Sgirish "ioaddr_pp $%p " 83644961713Sgirish "size 0x%llx ", 83744961713Sgirish channel, 83844961713Sgirish err, 83944961713Sgirish hverr, 84044961713Sgirish tx_ring_p->hv_tx_cntl_base_ioaddr_pp, 84144961713Sgirish tx_ring_p->hv_tx_cntl_ioaddr_size)); 84244961713Sgirish return (NXGE_ERROR | err); 84344961713Sgirish } 84444961713Sgirish 84544961713Sgirish #ifdef DEBUG 84644961713Sgirish ra = size = 0; 84744961713Sgirish hverr = hv_niu_tx_logical_page_info((uint64_t)channel, 84844961713Sgirish (uint64_t)1, 84944961713Sgirish &ra, 85044961713Sgirish &size); 85144961713Sgirish 85244961713Sgirish NXGE_DEBUG_MSG((nxgep, TX_CTL, 85344961713Sgirish "==> nxge_init_hv_fzc_txdma_channel_pages: channel %d " 85444961713Sgirish "(page 1 cntl buf) hverr 0x%llx " 85544961713Sgirish "set ioaddr_pp $%p " 85644961713Sgirish "set size 0x%llx " 85744961713Sgirish "get ra ioaddr_pp $%p " 85844961713Sgirish "get size 0x%llx ", 85944961713Sgirish channel, 86044961713Sgirish hverr, 86144961713Sgirish tx_ring_p->hv_tx_cntl_base_ioaddr_pp, 86244961713Sgirish tx_ring_p->hv_tx_cntl_ioaddr_size, 86344961713Sgirish ra, 86444961713Sgirish size)); 86544961713Sgirish #endif 86644961713Sgirish 86744961713Sgirish tx_ring_p->hv_set = B_TRUE; 86844961713Sgirish 86944961713Sgirish NXGE_DEBUG_MSG((nxgep, TX_CTL, 87044961713Sgirish "<== nxge_init_hv_fzc_txdma_channel_pages")); 87144961713Sgirish 87244961713Sgirish return (NXGE_OK); 87344961713Sgirish } 87444961713Sgirish 87544961713Sgirish /*ARGSUSED*/ 87644961713Sgirish nxge_status_t 87744961713Sgirish nxge_init_hv_fzc_rxdma_channel_pages(p_nxge_t nxgep, 87844961713Sgirish uint16_t channel, p_rx_rbr_ring_t rbrp) 87944961713Sgirish { 88044961713Sgirish int err; 88144961713Sgirish uint64_t hverr; 88244961713Sgirish #ifdef DEBUG 88344961713Sgirish uint64_t ra, size; 88444961713Sgirish #endif 88544961713Sgirish 88644961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 88744961713Sgirish "==> nxge_init_hv_fzc_rxdma_channel_pages")); 88844961713Sgirish 88944961713Sgirish if (rbrp->hv_set) { 89044961713Sgirish return (NXGE_OK); 89144961713Sgirish } 89244961713Sgirish 89344961713Sgirish /* Initialize data buffers for page 0 */ 89444961713Sgirish hverr = hv_niu_rx_logical_page_conf((uint64_t)channel, 89544961713Sgirish (uint64_t)0, 89644961713Sgirish rbrp->hv_rx_buf_base_ioaddr_pp, 89744961713Sgirish rbrp->hv_rx_buf_ioaddr_size); 89844961713Sgirish err = (nxge_status_t)nxge_herr2kerr(hverr); 89944961713Sgirish if (err != 0) { 90044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 90144961713Sgirish "<== nxge_init_hv_fzc_rxdma_channel_pages: channel %d" 90244961713Sgirish "error status 0x%x " 90344961713Sgirish "(page 0 data buf) hverr 0x%llx " 90444961713Sgirish "ioaddr_pp $%p " 90544961713Sgirish "size 0x%llx ", 90644961713Sgirish channel, 90744961713Sgirish err, 90844961713Sgirish hverr, 90944961713Sgirish rbrp->hv_rx_buf_base_ioaddr_pp, 91044961713Sgirish rbrp->hv_rx_buf_ioaddr_size)); 91144961713Sgirish 91244961713Sgirish return (NXGE_ERROR | err); 91344961713Sgirish } 91444961713Sgirish 91544961713Sgirish #ifdef DEBUG 91644961713Sgirish ra = size = 0; 91744961713Sgirish (void) hv_niu_rx_logical_page_info((uint64_t)channel, 91844961713Sgirish (uint64_t)0, 91944961713Sgirish &ra, 92044961713Sgirish &size); 92144961713Sgirish 92244961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 92344961713Sgirish "==> nxge_init_hv_fzc_rxdma_channel_pages: channel %d " 92444961713Sgirish "ok status 0x%x " 92544961713Sgirish "(page 0 data buf) hverr 0x%llx " 92644961713Sgirish "set databuf ioaddr_pp $%p " 92744961713Sgirish "set databuf size 0x%llx " 92844961713Sgirish "get databuf ra ioaddr_pp %p " 92944961713Sgirish "get databuf size 0x%llx", 93044961713Sgirish channel, 93144961713Sgirish err, 93244961713Sgirish hverr, 93344961713Sgirish rbrp->hv_rx_buf_base_ioaddr_pp, 93444961713Sgirish rbrp->hv_rx_buf_ioaddr_size, 93544961713Sgirish ra, 93644961713Sgirish size)); 93744961713Sgirish #endif 93844961713Sgirish 93944961713Sgirish /* Initialize control buffers for logical page 1. */ 94044961713Sgirish hverr = hv_niu_rx_logical_page_conf((uint64_t)channel, 94144961713Sgirish (uint64_t)1, 94244961713Sgirish rbrp->hv_rx_cntl_base_ioaddr_pp, 94344961713Sgirish rbrp->hv_rx_cntl_ioaddr_size); 94444961713Sgirish 94544961713Sgirish err = (nxge_status_t)nxge_herr2kerr(hverr); 94644961713Sgirish if (err != 0) { 94744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 94844961713Sgirish "<== nxge_init_hv_fzc_rxdma_channel_pages: channel %d" 94944961713Sgirish "error status 0x%x " 95044961713Sgirish "(page 1 cntl buf) hverr 0x%llx " 95144961713Sgirish "ioaddr_pp $%p " 95244961713Sgirish "size 0x%llx ", 95344961713Sgirish channel, 95444961713Sgirish err, 95544961713Sgirish hverr, 95644961713Sgirish rbrp->hv_rx_buf_base_ioaddr_pp, 95744961713Sgirish rbrp->hv_rx_buf_ioaddr_size)); 95844961713Sgirish 95944961713Sgirish return (NXGE_ERROR | err); 96044961713Sgirish } 96144961713Sgirish 96244961713Sgirish #ifdef DEBUG 96344961713Sgirish ra = size = 0; 96444961713Sgirish (void) hv_niu_rx_logical_page_info((uint64_t)channel, 96544961713Sgirish (uint64_t)1, 96644961713Sgirish &ra, 96744961713Sgirish &size); 96844961713Sgirish 96944961713Sgirish 97044961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 97144961713Sgirish "==> nxge_init_hv_fzc_rxdma_channel_pages: channel %d " 97244961713Sgirish "error status 0x%x " 97344961713Sgirish "(page 1 cntl buf) hverr 0x%llx " 97444961713Sgirish "set cntl ioaddr_pp $%p " 97544961713Sgirish "set cntl size 0x%llx " 97644961713Sgirish "get cntl ioaddr_pp $%p " 97744961713Sgirish "get cntl size 0x%llx ", 97844961713Sgirish channel, 97944961713Sgirish err, 98044961713Sgirish hverr, 98144961713Sgirish rbrp->hv_rx_cntl_base_ioaddr_pp, 98244961713Sgirish rbrp->hv_rx_cntl_ioaddr_size, 98344961713Sgirish ra, 98444961713Sgirish size)); 98544961713Sgirish #endif 98644961713Sgirish 98744961713Sgirish rbrp->hv_set = B_FALSE; 98844961713Sgirish 98944961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, 99044961713Sgirish "<== nxge_init_hv_fzc_rxdma_channel_pages")); 99144961713Sgirish 99244961713Sgirish return (NXGE_OK); 99344961713Sgirish } 99444961713Sgirish 99544961713Sgirish /* 99644961713Sgirish * Map hypervisor error code to errno. Only 99744961713Sgirish * H_ENORADDR, H_EBADALIGN and H_EINVAL are meaningful 99844961713Sgirish * for niu driver. Any other error codes are mapped to EINVAL. 99944961713Sgirish */ 100044961713Sgirish static int 100144961713Sgirish nxge_herr2kerr(uint64_t hv_errcode) 100244961713Sgirish { 100344961713Sgirish int s_errcode; 100444961713Sgirish 100544961713Sgirish switch (hv_errcode) { 100644961713Sgirish case H_ENORADDR: 100744961713Sgirish case H_EBADALIGN: 100844961713Sgirish s_errcode = EFAULT; 100944961713Sgirish break; 101044961713Sgirish case H_EOK: 101144961713Sgirish s_errcode = 0; 101244961713Sgirish break; 101344961713Sgirish default: 101444961713Sgirish s_errcode = EINVAL; 101544961713Sgirish break; 101644961713Sgirish } 101744961713Sgirish return (s_errcode); 101844961713Sgirish } 101944961713Sgirish 102044961713Sgirish #endif /* sun4v and NIU_LP_WORKAROUND */ 1021