xref: /illumos-gate/usr/src/uts/common/io/nxge/nxge_fflp.c (revision 86ef0a63)
144961713Sgirish /*
244961713Sgirish  * CDDL HEADER START
344961713Sgirish  *
444961713Sgirish  * The contents of this file are subject to the terms of the
544961713Sgirish  * Common Development and Distribution License (the "License").
644961713Sgirish  * You may not use this file except in compliance with the License.
744961713Sgirish  *
844961713Sgirish  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
944961713Sgirish  * or http://www.opensolaris.org/os/licensing.
1044961713Sgirish  * See the License for the specific language governing permissions
1144961713Sgirish  * and limitations under the License.
1244961713Sgirish  *
1344961713Sgirish  * When distributing Covered Code, include this CDDL HEADER in each
1444961713Sgirish  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1544961713Sgirish  * If applicable, add the following below this CDDL HEADER, with the
1644961713Sgirish  * fields enclosed by brackets "[]" replaced with your own identifying
1744961713Sgirish  * information: Portions Copyright [yyyy] [name of copyright owner]
1844961713Sgirish  *
1944961713Sgirish  * CDDL HEADER END
2044961713Sgirish  */
210dc2366fSVenugopal Iyer 
2244961713Sgirish /*
230dc2366fSVenugopal Iyer  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
2444961713Sgirish  * Use is subject to license terms.
2544961713Sgirish  */
2644961713Sgirish 
2744961713Sgirish #include <npi_fflp.h>
2844961713Sgirish #include <npi_mac.h>
2944961713Sgirish #include <nxge_defs.h>
3044961713Sgirish #include <nxge_flow.h>
3144961713Sgirish #include <nxge_fflp.h>
3244961713Sgirish #include <nxge_impl.h>
3344961713Sgirish #include <nxge_fflp_hash.h>
3444961713Sgirish #include <nxge_common.h>
3544961713Sgirish 
3644961713Sgirish 
37a3c5bd6dSspeer /*
38a3c5bd6dSspeer  * Function prototypes
39a3c5bd6dSspeer  */
4044961713Sgirish static nxge_status_t nxge_fflp_vlan_tbl_clear_all(p_nxge_t);
4144961713Sgirish static nxge_status_t nxge_fflp_tcam_invalidate_all(p_nxge_t);
4244961713Sgirish static nxge_status_t nxge_fflp_tcam_init(p_nxge_t);
4344961713Sgirish static nxge_status_t nxge_fflp_fcram_invalidate_all(p_nxge_t);
4444961713Sgirish static nxge_status_t nxge_fflp_fcram_init(p_nxge_t);
4544961713Sgirish static int nxge_flow_need_hash_lookup(p_nxge_t, flow_resource_t *);
46a3c5bd6dSspeer static void nxge_fill_tcam_entry_tcp(p_nxge_t, flow_spec_t *, tcam_entry_t *);
47a3c5bd6dSspeer static void nxge_fill_tcam_entry_udp(p_nxge_t, flow_spec_t *, tcam_entry_t *);
48a3c5bd6dSspeer static void nxge_fill_tcam_entry_sctp(p_nxge_t, flow_spec_t *, tcam_entry_t *);
4944961713Sgirish static void nxge_fill_tcam_entry_tcp_ipv6(p_nxge_t, flow_spec_t *,
50a3c5bd6dSspeer 	tcam_entry_t *);
51a3c5bd6dSspeer static void nxge_fill_tcam_entry_udp_ipv6(p_nxge_t, flow_spec_t *,
52a3c5bd6dSspeer 	tcam_entry_t *);
53a3c5bd6dSspeer static void nxge_fill_tcam_entry_sctp_ipv6(p_nxge_t, flow_spec_t *,
54a3c5bd6dSspeer 	tcam_entry_t *);
554df55fdeSJanie Lu static uint8_t nxge_get_rdc_offset(p_nxge_t, uint8_t, uint64_t);
564df55fdeSJanie Lu static uint8_t nxge_get_rdc_group(p_nxge_t, uint8_t, uint64_t);
574df55fdeSJanie Lu static uint16_t nxge_tcam_get_index(p_nxge_t, uint16_t);
584df55fdeSJanie Lu static uint32_t nxge_tcam_cls_to_flow(uint32_t);
594df55fdeSJanie Lu static uint8_t nxge_iptun_pkt_type_to_pid(uint8_t);
604df55fdeSJanie Lu static npi_status_t nxge_set_iptun_usr_cls_reg(p_nxge_t, uint64_t,
614df55fdeSJanie Lu 					iptun_cfg_t *);
624df55fdeSJanie Lu static boolean_t nxge_is_iptun_cls_present(p_nxge_t, uint8_t, int *);
6344961713Sgirish 
64a3c5bd6dSspeer /*
65a3c5bd6dSspeer  * functions used outside this file
66a3c5bd6dSspeer  */
6744961713Sgirish nxge_status_t nxge_fflp_config_vlan_table(p_nxge_t, uint16_t);
6844961713Sgirish nxge_status_t nxge_fflp_ip_class_config_all(p_nxge_t);
6944961713Sgirish nxge_status_t nxge_add_flow(p_nxge_t, flow_resource_t *);
7014ea4bb7Ssd static nxge_status_t nxge_tcam_handle_ip_fragment(p_nxge_t);
7144961713Sgirish nxge_status_t nxge_add_tcam_entry(p_nxge_t, flow_resource_t *);
7244961713Sgirish nxge_status_t nxge_add_fcram_entry(p_nxge_t, flow_resource_t *);
7344961713Sgirish nxge_status_t nxge_flow_get_hash(p_nxge_t, flow_resource_t *,
74a3c5bd6dSspeer 	uint32_t *, uint16_t *);
754df55fdeSJanie Lu int nxge_get_valid_tcam_cnt(p_nxge_t);
764df55fdeSJanie Lu void nxge_get_tcam_entry_all(p_nxge_t, rx_class_cfg_t *);
774df55fdeSJanie Lu void nxge_get_tcam_entry(p_nxge_t, flow_resource_t *);
784df55fdeSJanie Lu void nxge_del_tcam_entry(p_nxge_t, uint32_t);
794df55fdeSJanie Lu void nxge_add_iptun_class(p_nxge_t, iptun_cfg_t *, uint8_t *);
804df55fdeSJanie Lu void nxge_cfg_iptun_hash(p_nxge_t, iptun_cfg_t *, uint8_t);
814df55fdeSJanie Lu void nxge_del_iptun_class(p_nxge_t, uint8_t);
824df55fdeSJanie Lu void nxge_get_iptun_class(p_nxge_t, iptun_cfg_t *, uint8_t);
834df55fdeSJanie Lu void nxge_set_ip_cls_sym(p_nxge_t, uint8_t, uint8_t);
844df55fdeSJanie Lu void nxge_get_ip_cls_sym(p_nxge_t, uint8_t, uint8_t *);
854df55fdeSJanie Lu 
8644961713Sgirish 
8744961713Sgirish nxge_status_t
nxge_tcam_dump_entry(p_nxge_t nxgep,uint32_t location)8844961713Sgirish nxge_tcam_dump_entry(p_nxge_t nxgep, uint32_t location)
8944961713Sgirish {
9044961713Sgirish 	tcam_entry_t tcam_rdptr;
9144961713Sgirish 	uint64_t asc_ram = 0;
9244961713Sgirish 	npi_handle_t handle;
9344961713Sgirish 	npi_status_t status;
9444961713Sgirish 
9544961713Sgirish 	handle = nxgep->npi_reg_handle;
9644961713Sgirish 
9744961713Sgirish 	bzero((char *)&tcam_rdptr, sizeof (struct tcam_entry));
9844961713Sgirish 	status = npi_fflp_tcam_entry_read(handle, (tcam_location_t)location,
9952ccf843Smisaki 	    (struct tcam_entry *)&tcam_rdptr);
10044961713Sgirish 	if (status & NPI_FAILURE) {
10144961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
10252ccf843Smisaki 		    " nxge_tcam_dump_entry:"
10352ccf843Smisaki 		    "  tcam read failed at location %d ", location));
10444961713Sgirish 		return (NXGE_ERROR);
10544961713Sgirish 	}
10644961713Sgirish 	status = npi_fflp_tcam_asc_ram_entry_read(handle,
10752ccf843Smisaki 	    (tcam_location_t)location, &asc_ram);
10844961713Sgirish 
10944961713Sgirish 	NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "location %x\n"
11052ccf843Smisaki 	    " key:  %llx %llx %llx %llx \n"
11152ccf843Smisaki 	    " mask: %llx %llx %llx %llx \n"
11252ccf843Smisaki 	    " ASC RAM %llx \n", location,
11352ccf843Smisaki 	    tcam_rdptr.key0, tcam_rdptr.key1,
11452ccf843Smisaki 	    tcam_rdptr.key2, tcam_rdptr.key3,
11552ccf843Smisaki 	    tcam_rdptr.mask0, tcam_rdptr.mask1,
11652ccf843Smisaki 	    tcam_rdptr.mask2, tcam_rdptr.mask3, asc_ram));
11744961713Sgirish 	return (NXGE_OK);
11844961713Sgirish }
11944961713Sgirish 
12044961713Sgirish void
nxge_get_tcam(p_nxge_t nxgep,p_mblk_t mp)12144961713Sgirish nxge_get_tcam(p_nxge_t nxgep, p_mblk_t mp)
12244961713Sgirish {
12344961713Sgirish 	uint32_t tcam_loc;
12444961713Sgirish 	int *lptr;
12544961713Sgirish 	int location;
12644961713Sgirish 
12744961713Sgirish 	uint32_t start_location = 0;
12844961713Sgirish 	uint32_t stop_location = nxgep->classifier.tcam_size;
12944961713Sgirish 	lptr = (int *)mp->b_rptr;
13044961713Sgirish 	location = *lptr;
13144961713Sgirish 
13244961713Sgirish 	if ((location >= nxgep->classifier.tcam_size) || (location < -1)) {
13344961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
13452ccf843Smisaki 		    "nxge_tcam_dump: Invalid location %d \n", location));
13544961713Sgirish 		return;
13644961713Sgirish 	}
13744961713Sgirish 	if (location == -1) {
13844961713Sgirish 		start_location = 0;
13944961713Sgirish 		stop_location = nxgep->classifier.tcam_size;
14044961713Sgirish 	} else {
14144961713Sgirish 		start_location = location;
142a3c5bd6dSspeer 		stop_location = location + 1;
14344961713Sgirish 	}
14444961713Sgirish 	for (tcam_loc = start_location; tcam_loc < stop_location; tcam_loc++)
14544961713Sgirish 		(void) nxge_tcam_dump_entry(nxgep, tcam_loc);
14644961713Sgirish }
14744961713Sgirish 
14844961713Sgirish /*
14944961713Sgirish  * nxge_fflp_vlan_table_invalidate_all
15044961713Sgirish  * invalidates the vlan RDC table entries.
15144961713Sgirish  * INPUT
15244961713Sgirish  * nxge    soft state data structure
15344961713Sgirish  * Return
15444961713Sgirish  *      NXGE_OK
15544961713Sgirish  *      NXGE_ERROR
15644961713Sgirish  *
15744961713Sgirish  */
158a3c5bd6dSspeer 
15944961713Sgirish static nxge_status_t
nxge_fflp_vlan_tbl_clear_all(p_nxge_t nxgep)16044961713Sgirish nxge_fflp_vlan_tbl_clear_all(p_nxge_t nxgep)
16144961713Sgirish {
16244961713Sgirish 	vlan_id_t vlan_id;
16344961713Sgirish 	npi_handle_t handle;
16444961713Sgirish 	npi_status_t rs = NPI_SUCCESS;
16544961713Sgirish 	vlan_id_t start = 0, stop = NXGE_MAX_VLANS;
16644961713Sgirish 
16744961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "==> nxge_fflp_vlan_tbl_clear_all "));
16844961713Sgirish 	handle = nxgep->npi_reg_handle;
16944961713Sgirish 	for (vlan_id = start; vlan_id < stop; vlan_id++) {
17044961713Sgirish 		rs = npi_fflp_cfg_vlan_table_clear(handle, vlan_id);
17144961713Sgirish 		if (rs != NPI_SUCCESS) {
17244961713Sgirish 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
17352ccf843Smisaki 			    "VLAN Table invalidate failed for vlan id %d ",
17452ccf843Smisaki 			    vlan_id));
17544961713Sgirish 			return (NXGE_ERROR | rs);
17644961713Sgirish 		}
17744961713Sgirish 	}
17844961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "<== nxge_fflp_vlan_tbl_clear_all "));
17944961713Sgirish 	return (NXGE_OK);
18044961713Sgirish }
18144961713Sgirish 
18244961713Sgirish /*
18344961713Sgirish  * The following functions are used by other modules to init
18444961713Sgirish  * the fflp module.
18544961713Sgirish  * these functions are the basic API used to init
18644961713Sgirish  * the fflp modules (tcam, fcram etc ......)
18744961713Sgirish  *
18844961713Sgirish  * The TCAM search future would be disabled  by default.
18944961713Sgirish  */
19044961713Sgirish 
19144961713Sgirish static nxge_status_t
nxge_fflp_tcam_init(p_nxge_t nxgep)19244961713Sgirish nxge_fflp_tcam_init(p_nxge_t nxgep)
19344961713Sgirish {
19444961713Sgirish 	uint8_t access_ratio;
19544961713Sgirish 	tcam_class_t class;
19644961713Sgirish 	npi_status_t rs = NPI_SUCCESS;
19744961713Sgirish 	npi_handle_t handle;
19844961713Sgirish 
19944961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "==> nxge_fflp_tcam_init"));
20044961713Sgirish 	handle = nxgep->npi_reg_handle;
20144961713Sgirish 
20244961713Sgirish 	rs = npi_fflp_cfg_tcam_disable(handle);
20344961713Sgirish 	if (rs != NPI_SUCCESS) {
20444961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "failed TCAM Disable\n"));
20544961713Sgirish 		return (NXGE_ERROR | rs);
20644961713Sgirish 	}
20744961713Sgirish 
20844961713Sgirish 	access_ratio = nxgep->param_arr[param_tcam_access_ratio].value;
20944961713Sgirish 	rs = npi_fflp_cfg_tcam_access(handle, access_ratio);
21044961713Sgirish 	if (rs != NPI_SUCCESS) {
21144961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
21252ccf843Smisaki 		    "failed TCAM Access cfg\n"));
21344961713Sgirish 		return (NXGE_ERROR | rs);
21444961713Sgirish 	}
21544961713Sgirish 
216a3c5bd6dSspeer 	/* disable configurable classes */
217a3c5bd6dSspeer 	/* disable the configurable ethernet classes; */
21844961713Sgirish 	for (class = TCAM_CLASS_ETYPE_1;
21952ccf843Smisaki 	    class <= TCAM_CLASS_ETYPE_2; class++) {
22044961713Sgirish 		rs = npi_fflp_cfg_enet_usr_cls_disable(handle, class);
22144961713Sgirish 		if (rs != NPI_SUCCESS) {
22244961713Sgirish 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
22352ccf843Smisaki 			    "TCAM USR Ether Class config failed."));
22444961713Sgirish 			return (NXGE_ERROR | rs);
22544961713Sgirish 		}
22644961713Sgirish 	}
22744961713Sgirish 
228a3c5bd6dSspeer 	/* disable the configurable ip classes; */
22944961713Sgirish 	for (class = TCAM_CLASS_IP_USER_4;
23052ccf843Smisaki 	    class <= TCAM_CLASS_IP_USER_7; class++) {
23144961713Sgirish 		rs = npi_fflp_cfg_ip_usr_cls_disable(handle, class);
23244961713Sgirish 		if (rs != NPI_SUCCESS) {
23344961713Sgirish 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
23452ccf843Smisaki 			    "TCAM USR IP Class cnfg failed."));
23544961713Sgirish 			return (NXGE_ERROR | rs);
23644961713Sgirish 		}
23744961713Sgirish 	}
23844961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "<== nxge_fflp_tcam_init"));
23944961713Sgirish 	return (NXGE_OK);
24044961713Sgirish }
24144961713Sgirish 
24244961713Sgirish /*
24344961713Sgirish  * nxge_fflp_tcam_invalidate_all
24444961713Sgirish  * invalidates all the tcam entries.
24544961713Sgirish  * INPUT
24644961713Sgirish  * nxge    soft state data structure
24744961713Sgirish  * Return
24844961713Sgirish  *      NXGE_OK
24944961713Sgirish  *      NXGE_ERROR
25044961713Sgirish  *
25144961713Sgirish  */
252a3c5bd6dSspeer 
253a3c5bd6dSspeer 
25444961713Sgirish static nxge_status_t
nxge_fflp_tcam_invalidate_all(p_nxge_t nxgep)25544961713Sgirish nxge_fflp_tcam_invalidate_all(p_nxge_t nxgep)
25644961713Sgirish {
25744961713Sgirish 	uint16_t location;
25844961713Sgirish 	npi_status_t rs = NPI_SUCCESS;
25944961713Sgirish 	npi_handle_t handle;
26044961713Sgirish 	uint16_t start = 0, stop = nxgep->classifier.tcam_size;
261a3c5bd6dSspeer 	p_nxge_hw_list_t hw_p;
26244961713Sgirish 
26344961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
26452ccf843Smisaki 	    "==> nxge_fflp_tcam_invalidate_all"));
26544961713Sgirish 	handle = nxgep->npi_reg_handle;
26644961713Sgirish 	if ((hw_p = nxgep->nxge_hw_p) == NULL) {
26744961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
26852ccf843Smisaki 		    " nxge_fflp_tcam_invalidate_all:"
26952ccf843Smisaki 		    " common hardware not set", nxgep->niu_type));
27044961713Sgirish 		return (NXGE_ERROR);
27144961713Sgirish 	}
27244961713Sgirish 	MUTEX_ENTER(&hw_p->nxge_tcam_lock);
27344961713Sgirish 	for (location = start; location < stop; location++) {
27444961713Sgirish 		rs = npi_fflp_tcam_entry_invalidate(handle, location);
27544961713Sgirish 		if (rs != NPI_SUCCESS) {
27644961713Sgirish 			MUTEX_EXIT(&hw_p->nxge_tcam_lock);
27744961713Sgirish 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
27852ccf843Smisaki 			    "TCAM invalidate failed at loc %d ", location));
27944961713Sgirish 			return (NXGE_ERROR | rs);
28044961713Sgirish 		}
28144961713Sgirish 	}
28244961713Sgirish 	MUTEX_EXIT(&hw_p->nxge_tcam_lock);
28344961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
28452ccf843Smisaki 	    "<== nxge_fflp_tcam_invalidate_all"));
28544961713Sgirish 	return (NXGE_OK);
28644961713Sgirish }
28744961713Sgirish 
28844961713Sgirish /*
28944961713Sgirish  * nxge_fflp_fcram_entry_invalidate_all
29044961713Sgirish  * invalidates all the FCRAM entries.
29144961713Sgirish  * INPUT
29244961713Sgirish  * nxge    soft state data structure
29344961713Sgirish  * Return
29444961713Sgirish  *      NXGE_OK
29544961713Sgirish  *      NXGE_ERROR
29644961713Sgirish  *
29744961713Sgirish  */
298a3c5bd6dSspeer 
29944961713Sgirish static nxge_status_t
nxge_fflp_fcram_invalidate_all(p_nxge_t nxgep)30044961713Sgirish nxge_fflp_fcram_invalidate_all(p_nxge_t nxgep)
30144961713Sgirish {
302a3c5bd6dSspeer 	npi_handle_t handle;
303a3c5bd6dSspeer 	npi_status_t rs = NPI_SUCCESS;
304a3c5bd6dSspeer 	part_id_t pid = 0;
305a3c5bd6dSspeer 	uint8_t base_mask, base_reloc;
306a3c5bd6dSspeer 	fcram_entry_t fc;
307a3c5bd6dSspeer 	uint32_t location;
308a3c5bd6dSspeer 	uint32_t increment, last_location;
30944961713Sgirish 
310a3c5bd6dSspeer 	/*
311a3c5bd6dSspeer 	 * (1) configure and enable partition 0 with no relocation
312a3c5bd6dSspeer 	 * (2) Assume the FCRAM is used as IPv4 exact match entry cells
313a3c5bd6dSspeer 	 * (3) Invalidate these cells by clearing the valid bit in
314a3c5bd6dSspeer 	 * the subareas 0 and 4
315a3c5bd6dSspeer 	 * (4) disable the partition
316a3c5bd6dSspeer 	 *
317a3c5bd6dSspeer 	 */
31844961713Sgirish 
31944961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "==> nxge_fflp_fcram_invalidate_all"));
32044961713Sgirish 
32144961713Sgirish 	base_mask = base_reloc = 0x0;
32244961713Sgirish 	handle = nxgep->npi_reg_handle;
323a3c5bd6dSspeer 	rs = npi_fflp_cfg_fcram_partition(handle, pid, base_mask, base_reloc);
32444961713Sgirish 
32544961713Sgirish 	if (rs != NPI_SUCCESS) {
326a3c5bd6dSspeer 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "failed partition cfg\n"));
32744961713Sgirish 		return (NXGE_ERROR | rs);
32844961713Sgirish 	}
329a3c5bd6dSspeer 	rs = npi_fflp_cfg_fcram_partition_disable(handle, pid);
33044961713Sgirish 
33144961713Sgirish 	if (rs != NPI_SUCCESS) {
33244961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
33352ccf843Smisaki 		    "failed partition enable\n"));
33444961713Sgirish 		return (NXGE_ERROR | rs);
33544961713Sgirish 	}
336a3c5bd6dSspeer 	fc.dreg[0].value = 0;
337a3c5bd6dSspeer 	fc.hash_hdr_valid = 0;
338a3c5bd6dSspeer 	fc.hash_hdr_ext = 1;	/* specify as IPV4 exact match entry */
339a3c5bd6dSspeer 	increment = sizeof (hash_ipv4_t);
340a3c5bd6dSspeer 	last_location = FCRAM_SIZE * 0x40;
34144961713Sgirish 
342a3c5bd6dSspeer 	for (location = 0; location < last_location; location += increment) {
34344961713Sgirish 		rs = npi_fflp_fcram_subarea_write(handle, pid,
34452ccf843Smisaki 		    location, fc.value[0]);
34544961713Sgirish 		if (rs != NPI_SUCCESS) {
34644961713Sgirish 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
34752ccf843Smisaki 			    "failed write at location %x ", location));
34844961713Sgirish 			return (NXGE_ERROR | rs);
34944961713Sgirish 		}
35044961713Sgirish 	}
35144961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "<== nxge_fflp_fcram_invalidate_all"));
352a3c5bd6dSspeer 	return (NXGE_OK);
35344961713Sgirish }
35444961713Sgirish 
35544961713Sgirish static nxge_status_t
nxge_fflp_fcram_init(p_nxge_t nxgep)35644961713Sgirish nxge_fflp_fcram_init(p_nxge_t nxgep)
35744961713Sgirish {
35844961713Sgirish 	fflp_fcram_output_drive_t strength;
35944961713Sgirish 	fflp_fcram_qs_t qs;
36044961713Sgirish 	npi_status_t rs = NPI_SUCCESS;
36144961713Sgirish 	uint8_t access_ratio;
362a3c5bd6dSspeer 	int partition;
36344961713Sgirish 	npi_handle_t handle;
364a3c5bd6dSspeer 	uint32_t min_time, max_time, sys_time;
36544961713Sgirish 
36644961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "==> nxge_fflp_fcram_init"));
36744961713Sgirish 
368a3c5bd6dSspeer 	/*
369a3c5bd6dSspeer 	 * Recommended values are needed.
370a3c5bd6dSspeer 	 */
37144961713Sgirish 	min_time = FCRAM_REFRESH_DEFAULT_MIN_TIME;
37244961713Sgirish 	max_time = FCRAM_REFRESH_DEFAULT_MAX_TIME;
37344961713Sgirish 	sys_time = FCRAM_REFRESH_DEFAULT_SYS_TIME;
374a3c5bd6dSspeer 
37544961713Sgirish 	handle = nxgep->npi_reg_handle;
37644961713Sgirish 	strength = FCRAM_OUTDR_NORMAL;
37744961713Sgirish 	qs = FCRAM_QS_MODE_QS;
37844961713Sgirish 	rs = npi_fflp_cfg_fcram_reset(handle, strength, qs);
37944961713Sgirish 	if (rs != NPI_SUCCESS) {
38044961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "failed FCRAM Reset. "));
38144961713Sgirish 		return (NXGE_ERROR | rs);
38244961713Sgirish 	}
38344961713Sgirish 
384a3c5bd6dSspeer 	access_ratio = nxgep->param_arr[param_fcram_access_ratio].value;
385a3c5bd6dSspeer 	rs = npi_fflp_cfg_fcram_access(handle, access_ratio);
386a3c5bd6dSspeer 	if (rs != NPI_SUCCESS) {
38744961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "failed FCRAM Access ratio"
38852ccf843Smisaki 		    "configuration \n"));
38944961713Sgirish 		return (NXGE_ERROR | rs);
39044961713Sgirish 	}
39144961713Sgirish 	rs = npi_fflp_cfg_fcram_refresh_time(handle, min_time,
39252ccf843Smisaki 	    max_time, sys_time);
39344961713Sgirish 	if (rs != NPI_SUCCESS) {
39444961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
39552ccf843Smisaki 		    "failed FCRAM refresh cfg"));
39644961713Sgirish 		return (NXGE_ERROR);
39744961713Sgirish 	}
39844961713Sgirish 
39944961713Sgirish 	/* disable all the partitions until explicitly enabled */
40044961713Sgirish 	for (partition = 0; partition < FFLP_FCRAM_MAX_PARTITION; partition++) {
401a3c5bd6dSspeer 		rs = npi_fflp_cfg_fcram_partition_disable(handle, partition);
40244961713Sgirish 		if (rs != NPI_SUCCESS) {
40344961713Sgirish 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
40452ccf843Smisaki 			    "failed FCRAM partition"
40552ccf843Smisaki 			    " enable for partition %d ", partition));
40644961713Sgirish 			return (NXGE_ERROR | rs);
40744961713Sgirish 		}
40844961713Sgirish 	}
40944961713Sgirish 
41044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "<== nxge_fflp_fcram_init"));
411a3c5bd6dSspeer 	return (NXGE_OK);
41244961713Sgirish }
41344961713Sgirish 
41444961713Sgirish nxge_status_t
nxge_logical_mac_assign_rdc_table(p_nxge_t nxgep,uint8_t alt_mac)41544961713Sgirish nxge_logical_mac_assign_rdc_table(p_nxge_t nxgep, uint8_t alt_mac)
41644961713Sgirish {
41744961713Sgirish 	npi_status_t rs = NPI_SUCCESS;
41844961713Sgirish 	hostinfo_t mac_rdc;
41944961713Sgirish 	npi_handle_t handle;
420a3c5bd6dSspeer 	p_nxge_class_pt_cfg_t p_class_cfgp;
42144961713Sgirish 
422a3c5bd6dSspeer 	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
42344961713Sgirish 	if (p_class_cfgp->mac_host_info[alt_mac].flag == 0) {
424a3c5bd6dSspeer 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
42552ccf843Smisaki 		    " nxge_logical_mac_assign_rdc_table"
42652ccf843Smisaki 		    " unconfigured alt MAC addr %d ", alt_mac));
42744961713Sgirish 		return (NXGE_ERROR);
42844961713Sgirish 	}
42944961713Sgirish 	handle = nxgep->npi_reg_handle;
43044961713Sgirish 	mac_rdc.value = 0;
43144961713Sgirish 	mac_rdc.bits.w0.rdc_tbl_num =
43252ccf843Smisaki 	    p_class_cfgp->mac_host_info[alt_mac].rdctbl;
43344961713Sgirish 	mac_rdc.bits.w0.mac_pref = p_class_cfgp->mac_host_info[alt_mac].mpr_npr;
43444961713Sgirish 
43544961713Sgirish 	rs = npi_mac_hostinfo_entry(handle, OP_SET,
43652ccf843Smisaki 	    nxgep->function_num, alt_mac, &mac_rdc);
43744961713Sgirish 
43844961713Sgirish 	if (rs != NPI_SUCCESS) {
43944961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
44052ccf843Smisaki 		    "failed Assign RDC table"));
44144961713Sgirish 		return (NXGE_ERROR | rs);
44244961713Sgirish 	}
44344961713Sgirish 	return (NXGE_OK);
44444961713Sgirish }
44544961713Sgirish 
44644961713Sgirish nxge_status_t
nxge_main_mac_assign_rdc_table(p_nxge_t nxgep)44744961713Sgirish nxge_main_mac_assign_rdc_table(p_nxge_t nxgep)
44844961713Sgirish {
44944961713Sgirish 	npi_status_t rs = NPI_SUCCESS;
45044961713Sgirish 	hostinfo_t mac_rdc;
45144961713Sgirish 	npi_handle_t handle;
4520dc2366fSVenugopal Iyer 	int i;
45344961713Sgirish 
45444961713Sgirish 	handle = nxgep->npi_reg_handle;
45544961713Sgirish 	mac_rdc.value = 0;
45644961713Sgirish 	mac_rdc.bits.w0.rdc_tbl_num = nxgep->class_config.mac_rdcgrp;
45744961713Sgirish 	mac_rdc.bits.w0.mac_pref = 1;
45844961713Sgirish 	switch (nxgep->function_num) {
459a3c5bd6dSspeer 	case 0:
460a3c5bd6dSspeer 	case 1:
4610dc2366fSVenugopal Iyer 		/*
4620dc2366fSVenugopal Iyer 		 * Tests indicate that it is OK not to re-initialize the
4630dc2366fSVenugopal Iyer 		 * hostinfo registers for the XMAC's alternate MAC
4640dc2366fSVenugopal Iyer 		 * addresses. But that is necessary for BMAC (case 2
4650dc2366fSVenugopal Iyer 		 * and case 3 below)
4660dc2366fSVenugopal Iyer 		 */
467a3c5bd6dSspeer 		rs = npi_mac_hostinfo_entry(handle, OP_SET,
46852ccf843Smisaki 		    nxgep->function_num, XMAC_UNIQUE_HOST_INFO_ENTRY, &mac_rdc);
469a3c5bd6dSspeer 		break;
470a3c5bd6dSspeer 	case 2:
471a3c5bd6dSspeer 	case 3:
472a3c5bd6dSspeer 		rs = npi_mac_hostinfo_entry(handle, OP_SET,
47352ccf843Smisaki 		    nxgep->function_num, BMAC_UNIQUE_HOST_INFO_ENTRY, &mac_rdc);
4740dc2366fSVenugopal Iyer 		for (i = 1; i <= BMAC_MAX_ALT_ADDR_ENTRY; i++)
4750dc2366fSVenugopal Iyer 			rs |= npi_mac_hostinfo_entry(handle, OP_SET,
4760dc2366fSVenugopal Iyer 			    nxgep->function_num, i, &mac_rdc);
477a3c5bd6dSspeer 		break;
478a3c5bd6dSspeer 	default:
479a3c5bd6dSspeer 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
48052ccf843Smisaki 		    "failed Assign RDC table (invalid function #)"));
481a3c5bd6dSspeer 		return (NXGE_ERROR);
48244961713Sgirish 	}
48344961713Sgirish 
48444961713Sgirish 	if (rs != NPI_SUCCESS) {
48544961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
48652ccf843Smisaki 		    "failed Assign RDC table"));
48744961713Sgirish 		return (NXGE_ERROR | rs);
48844961713Sgirish 	}
48944961713Sgirish 	return (NXGE_OK);
49044961713Sgirish }
49144961713Sgirish 
49258324dfcSspeer /*
49358324dfcSspeer  * Initialize hostinfo registers for alternate MAC addresses and
49458324dfcSspeer  * multicast MAC address.
49558324dfcSspeer  */
49644961713Sgirish nxge_status_t
nxge_alt_mcast_mac_assign_rdc_table(p_nxge_t nxgep)49758324dfcSspeer nxge_alt_mcast_mac_assign_rdc_table(p_nxge_t nxgep)
49844961713Sgirish {
49944961713Sgirish 	npi_status_t rs = NPI_SUCCESS;
50044961713Sgirish 	hostinfo_t mac_rdc;
50144961713Sgirish 	npi_handle_t handle;
50244961713Sgirish 
50344961713Sgirish 	handle = nxgep->npi_reg_handle;
50444961713Sgirish 	mac_rdc.value = 0;
50544961713Sgirish 	mac_rdc.bits.w0.rdc_tbl_num = nxgep->class_config.mcast_rdcgrp;
50644961713Sgirish 	mac_rdc.bits.w0.mac_pref = 1;
50744961713Sgirish 	switch (nxgep->function_num) {
508a3c5bd6dSspeer 	case 0:
509a3c5bd6dSspeer 	case 1:
510a3c5bd6dSspeer 		rs = npi_mac_hostinfo_entry(handle, OP_SET,
5110dc2366fSVenugopal Iyer 		    nxgep->function_num, XMAC_MULTI_HOST_INFO_ENTRY, &mac_rdc);
512a3c5bd6dSspeer 		break;
513a3c5bd6dSspeer 	case 2:
514a3c5bd6dSspeer 	case 3:
5150dc2366fSVenugopal Iyer 		rs = npi_mac_hostinfo_entry(handle, OP_SET,
5160dc2366fSVenugopal Iyer 		    nxgep->function_num, BMAC_MULTI_HOST_INFO_ENTRY, &mac_rdc);
517a3c5bd6dSspeer 		break;
518a3c5bd6dSspeer 	default:
519a3c5bd6dSspeer 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
52052ccf843Smisaki 		    "failed Assign RDC table (invalid function #)"));
521a3c5bd6dSspeer 		return (NXGE_ERROR);
52244961713Sgirish 	}
52344961713Sgirish 
52444961713Sgirish 	if (rs != NPI_SUCCESS) {
52544961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
52652ccf843Smisaki 		    "failed Assign RDC table"));
52744961713Sgirish 		return (NXGE_ERROR | rs);
52844961713Sgirish 	}
52944961713Sgirish 	return (NXGE_OK);
53044961713Sgirish }
53144961713Sgirish 
53244961713Sgirish nxge_status_t
nxge_fflp_init_hostinfo(p_nxge_t nxgep)53344961713Sgirish nxge_fflp_init_hostinfo(p_nxge_t nxgep)
53444961713Sgirish {
53544961713Sgirish 	nxge_status_t status = NXGE_OK;
536a3c5bd6dSspeer 
53758324dfcSspeer 	status = nxge_alt_mcast_mac_assign_rdc_table(nxgep);
53858324dfcSspeer 	status |= nxge_main_mac_assign_rdc_table(nxgep);
53944961713Sgirish 	return (status);
54044961713Sgirish }
54144961713Sgirish 
54244961713Sgirish nxge_status_t
nxge_fflp_hw_reset(p_nxge_t nxgep)54344961713Sgirish nxge_fflp_hw_reset(p_nxge_t nxgep)
54444961713Sgirish {
54544961713Sgirish 	npi_handle_t handle;
54644961713Sgirish 	npi_status_t rs = NPI_SUCCESS;
54744961713Sgirish 	nxge_status_t status = NXGE_OK;
54844961713Sgirish 
54944961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL, " ==> nxge_fflp_hw_reset"));
55044961713Sgirish 
5512e59129aSraghus 	if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
55244961713Sgirish 		status = nxge_fflp_fcram_init(nxgep);
553a3c5bd6dSspeer 		if (status != NXGE_OK) {
55444961713Sgirish 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
55552ccf843Smisaki 			    " failed FCRAM init. "));
55644961713Sgirish 			return (status);
55744961713Sgirish 		}
55844961713Sgirish 	}
55944961713Sgirish 
56044961713Sgirish 	status = nxge_fflp_tcam_init(nxgep);
56144961713Sgirish 	if (status != NXGE_OK) {
562a3c5bd6dSspeer 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
56352ccf843Smisaki 		    "failed TCAM init."));
564a3c5bd6dSspeer 		return (status);
56544961713Sgirish 	}
56644961713Sgirish 
56744961713Sgirish 	handle = nxgep->npi_reg_handle;
56844961713Sgirish 	rs = npi_fflp_cfg_llcsnap_enable(handle);
56944961713Sgirish 	if (rs != NPI_SUCCESS) {
570a3c5bd6dSspeer 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
57152ccf843Smisaki 		    "failed LLCSNAP enable. "));
572a3c5bd6dSspeer 		return (NXGE_ERROR | rs);
57344961713Sgirish 	}
57444961713Sgirish 
57544961713Sgirish 	rs = npi_fflp_cfg_cam_errorcheck_disable(handle);
57644961713Sgirish 	if (rs != NPI_SUCCESS) {
57744961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
57852ccf843Smisaki 		    "failed CAM Error Check enable. "));
57944961713Sgirish 		return (NXGE_ERROR | rs);
58044961713Sgirish 	}
58144961713Sgirish 
582a3c5bd6dSspeer 	/* init the hash generators */
58344961713Sgirish 	rs = npi_fflp_cfg_hash_h1poly(handle, 0);
58444961713Sgirish 	if (rs != NPI_SUCCESS) {
585a3c5bd6dSspeer 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
58652ccf843Smisaki 		    "failed H1 Poly Init. "));
587a3c5bd6dSspeer 		return (NXGE_ERROR | rs);
58844961713Sgirish 	}
58944961713Sgirish 
59044961713Sgirish 	rs = npi_fflp_cfg_hash_h2poly(handle, 0);
59144961713Sgirish 	if (rs != NPI_SUCCESS) {
592a3c5bd6dSspeer 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
59352ccf843Smisaki 		    "failed H2 Poly Init. "));
594a3c5bd6dSspeer 		return (NXGE_ERROR | rs);
59544961713Sgirish 	}
59644961713Sgirish 
597a3c5bd6dSspeer 	/* invalidate TCAM entries */
59844961713Sgirish 	status = nxge_fflp_tcam_invalidate_all(nxgep);
59944961713Sgirish 	if (status != NXGE_OK) {
60044961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
60152ccf843Smisaki 		    "failed TCAM Entry Invalidate. "));
60244961713Sgirish 		return (status);
60344961713Sgirish 	}
60444961713Sgirish 
605a3c5bd6dSspeer 	/* invalidate FCRAM entries */
6062e59129aSraghus 	if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
60744961713Sgirish 		status = nxge_fflp_fcram_invalidate_all(nxgep);
60844961713Sgirish 		if (status != NXGE_OK) {
60944961713Sgirish 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
61052ccf843Smisaki 			    "failed FCRAM Entry Invalidate."));
61144961713Sgirish 			return (status);
61244961713Sgirish 		}
61344961713Sgirish 	}
61444961713Sgirish 
615a3c5bd6dSspeer 	/* invalidate VLAN RDC tables */
61644961713Sgirish 	status = nxge_fflp_vlan_tbl_clear_all(nxgep);
61744961713Sgirish 	if (status != NXGE_OK) {
61844961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
61952ccf843Smisaki 		    "failed VLAN Table Invalidate. "));
62044961713Sgirish 		return (status);
62144961713Sgirish 	}
62244961713Sgirish 	nxgep->classifier.state |= NXGE_FFLP_HW_RESET;
62344961713Sgirish 
62444961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "<== nxge_fflp_hw_reset"));
62544961713Sgirish 	return (NXGE_OK);
62644961713Sgirish }
62744961713Sgirish 
62844961713Sgirish nxge_status_t
nxge_cfg_ip_cls_flow_key(p_nxge_t nxgep,tcam_class_t l3_class,uint32_t class_config)62944961713Sgirish nxge_cfg_ip_cls_flow_key(p_nxge_t nxgep, tcam_class_t l3_class,
630*86ef0a63SRichard Lowe     uint32_t class_config)
63144961713Sgirish {
63244961713Sgirish 	flow_key_cfg_t fcfg;
63344961713Sgirish 	npi_handle_t handle;
63444961713Sgirish 	npi_status_t rs = NPI_SUCCESS;
63544961713Sgirish 
63644961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL, " ==> nxge_cfg_ip_cls_flow_key"));
63744961713Sgirish 	handle = nxgep->npi_reg_handle;
63844961713Sgirish 	bzero(&fcfg, sizeof (flow_key_cfg_t));
63944961713Sgirish 
640a3c5bd6dSspeer 	if (class_config & NXGE_CLASS_FLOW_USE_PROTO)
64144961713Sgirish 		fcfg.use_proto = 1;
64244961713Sgirish 	if (class_config & NXGE_CLASS_FLOW_USE_DST_PORT)
64344961713Sgirish 		fcfg.use_dport = 1;
64444961713Sgirish 	if (class_config & NXGE_CLASS_FLOW_USE_SRC_PORT)
64544961713Sgirish 		fcfg.use_sport = 1;
64644961713Sgirish 	if (class_config & NXGE_CLASS_FLOW_USE_IPDST)
64744961713Sgirish 		fcfg.use_daddr = 1;
64844961713Sgirish 	if (class_config & NXGE_CLASS_FLOW_USE_IPSRC)
64944961713Sgirish 		fcfg.use_saddr = 1;
65044961713Sgirish 	if (class_config & NXGE_CLASS_FLOW_USE_VLAN)
65144961713Sgirish 		fcfg.use_vlan = 1;
65244961713Sgirish 	if (class_config & NXGE_CLASS_FLOW_USE_L2DA)
65344961713Sgirish 		fcfg.use_l2da = 1;
65444961713Sgirish 	if (class_config & NXGE_CLASS_FLOW_USE_PORTNUM)
65544961713Sgirish 		fcfg.use_portnum = 1;
65644961713Sgirish 	fcfg.ip_opts_exist = 0;
65744961713Sgirish 
65844961713Sgirish 	rs = npi_fflp_cfg_ip_cls_flow_key(handle, l3_class, &fcfg);
65944961713Sgirish 	if (rs & NPI_FFLP_ERROR) {
66044961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, " nxge_cfg_ip_cls_flow_key"
66152ccf843Smisaki 		    " opt %x for class %d failed ", class_config, l3_class));
66244961713Sgirish 		return (NXGE_ERROR | rs);
66344961713Sgirish 	}
66444961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL, " <== nxge_cfg_ip_cls_flow_key"));
66544961713Sgirish 	return (NXGE_OK);
66644961713Sgirish }
66744961713Sgirish 
66844961713Sgirish nxge_status_t
nxge_cfg_ip_cls_flow_key_get(p_nxge_t nxgep,tcam_class_t l3_class,uint32_t * class_config)66944961713Sgirish nxge_cfg_ip_cls_flow_key_get(p_nxge_t nxgep, tcam_class_t l3_class,
670*86ef0a63SRichard Lowe     uint32_t *class_config)
67144961713Sgirish {
67244961713Sgirish 	flow_key_cfg_t fcfg;
67344961713Sgirish 	npi_handle_t handle;
67444961713Sgirish 	npi_status_t rs = NPI_SUCCESS;
67544961713Sgirish 	uint32_t ccfg = 0;
676a3c5bd6dSspeer 
67744961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL, " ==> nxge_cfg_ip_cls_flow_key_get"));
67844961713Sgirish 	handle = nxgep->npi_reg_handle;
67944961713Sgirish 	bzero(&fcfg, sizeof (flow_key_cfg_t));
68044961713Sgirish 
68144961713Sgirish 	rs = npi_fflp_cfg_ip_cls_flow_key_get(handle, l3_class, &fcfg);
68244961713Sgirish 	if (rs & NPI_FFLP_ERROR) {
68344961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, " nxge_cfg_ip_cls_flow_key"
68452ccf843Smisaki 		    " opt %x for class %d failed ", class_config, l3_class));
68544961713Sgirish 		return (NXGE_ERROR | rs);
68644961713Sgirish 	}
68744961713Sgirish 
68844961713Sgirish 	if (fcfg.use_proto)
68944961713Sgirish 		ccfg |= NXGE_CLASS_FLOW_USE_PROTO;
69044961713Sgirish 	if (fcfg.use_dport)
69144961713Sgirish 		ccfg |= NXGE_CLASS_FLOW_USE_DST_PORT;
69244961713Sgirish 	if (fcfg.use_sport)
69344961713Sgirish 		ccfg |= NXGE_CLASS_FLOW_USE_SRC_PORT;
69444961713Sgirish 	if (fcfg.use_daddr)
69544961713Sgirish 		ccfg |= NXGE_CLASS_FLOW_USE_IPDST;
69644961713Sgirish 	if (fcfg.use_saddr)
69744961713Sgirish 		ccfg |= NXGE_CLASS_FLOW_USE_IPSRC;
69844961713Sgirish 	if (fcfg.use_vlan)
69944961713Sgirish 		ccfg |= NXGE_CLASS_FLOW_USE_VLAN;
70044961713Sgirish 	if (fcfg.use_l2da)
70144961713Sgirish 		ccfg |= NXGE_CLASS_FLOW_USE_L2DA;
70244961713Sgirish 	if (fcfg.use_portnum)
703a3c5bd6dSspeer 		ccfg |= NXGE_CLASS_FLOW_USE_PORTNUM;
70444961713Sgirish 
70544961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
70652ccf843Smisaki 	    " nxge_cfg_ip_cls_flow_key_get %x", ccfg));
70744961713Sgirish 	*class_config = ccfg;
70844961713Sgirish 
70944961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
71052ccf843Smisaki 	    " <== nxge_cfg_ip_cls_flow_key_get"));
71144961713Sgirish 	return (NXGE_OK);
71244961713Sgirish }
71344961713Sgirish 
71444961713Sgirish static nxge_status_t
nxge_cfg_tcam_ip_class_get(p_nxge_t nxgep,tcam_class_t class,uint32_t * class_config)71544961713Sgirish nxge_cfg_tcam_ip_class_get(p_nxge_t nxgep, tcam_class_t class,
716*86ef0a63SRichard Lowe     uint32_t *class_config)
71744961713Sgirish {
71844961713Sgirish 	npi_status_t rs = NPI_SUCCESS;
71944961713Sgirish 	tcam_key_cfg_t cfg;
72044961713Sgirish 	npi_handle_t handle;
72144961713Sgirish 	uint32_t ccfg = 0;
72244961713Sgirish 
72344961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "==> nxge_cfg_tcam_ip_class"));
72444961713Sgirish 
72544961713Sgirish 	bzero(&cfg, sizeof (tcam_key_cfg_t));
72644961713Sgirish 	handle = nxgep->npi_reg_handle;
72744961713Sgirish 
72844961713Sgirish 	rs = npi_fflp_cfg_ip_cls_tcam_key_get(handle, class, &cfg);
72944961713Sgirish 	if (rs & NPI_FFLP_ERROR) {
73044961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, " nxge_cfg_tcam_ip_class"
73152ccf843Smisaki 		    " opt %x for class %d failed ", class_config, class));
73244961713Sgirish 		return (NXGE_ERROR | rs);
73344961713Sgirish 	}
73444961713Sgirish 	if (cfg.discard)
735a3c5bd6dSspeer 		ccfg |= NXGE_CLASS_DISCARD;
73644961713Sgirish 	if (cfg.lookup_enable)
73744961713Sgirish 		ccfg |= NXGE_CLASS_TCAM_LOOKUP;
73844961713Sgirish 	if (cfg.use_ip_daddr)
739a3c5bd6dSspeer 		ccfg |= NXGE_CLASS_TCAM_USE_SRC_ADDR;
74044961713Sgirish 	*class_config = ccfg;
74144961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
74252ccf843Smisaki 	    " ==> nxge_cfg_tcam_ip_class %x", ccfg));
74344961713Sgirish 	return (NXGE_OK);
74444961713Sgirish }
74544961713Sgirish 
74644961713Sgirish static nxge_status_t
nxge_cfg_tcam_ip_class(p_nxge_t nxgep,tcam_class_t class,uint32_t class_config)74744961713Sgirish nxge_cfg_tcam_ip_class(p_nxge_t nxgep, tcam_class_t class,
748*86ef0a63SRichard Lowe     uint32_t class_config)
74944961713Sgirish {
75044961713Sgirish 	npi_status_t rs = NPI_SUCCESS;
75144961713Sgirish 	tcam_key_cfg_t cfg;
75244961713Sgirish 	npi_handle_t handle;
753a3c5bd6dSspeer 	p_nxge_class_pt_cfg_t p_class_cfgp;
75444961713Sgirish 
75544961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "==> nxge_cfg_tcam_ip_class"));
756a3c5bd6dSspeer 
75744961713Sgirish 	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
75844961713Sgirish 	p_class_cfgp->class_cfg[class] = class_config;
75944961713Sgirish 
76044961713Sgirish 	bzero(&cfg, sizeof (tcam_key_cfg_t));
76144961713Sgirish 	handle = nxgep->npi_reg_handle;
76244961713Sgirish 	cfg.discard = 0;
76344961713Sgirish 	cfg.lookup_enable = 0;
76444961713Sgirish 	cfg.use_ip_daddr = 0;
76544961713Sgirish 	if (class_config & NXGE_CLASS_DISCARD)
76644961713Sgirish 		cfg.discard = 1;
76744961713Sgirish 	if (class_config & NXGE_CLASS_TCAM_LOOKUP)
76844961713Sgirish 		cfg.lookup_enable = 1;
769a3c5bd6dSspeer 	if (class_config & NXGE_CLASS_TCAM_USE_SRC_ADDR)
77044961713Sgirish 		cfg.use_ip_daddr = 1;
77144961713Sgirish 
77244961713Sgirish 	rs = npi_fflp_cfg_ip_cls_tcam_key(handle, class, &cfg);
77344961713Sgirish 	if (rs & NPI_FFLP_ERROR) {
77444961713Sgirish 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, " nxge_cfg_tcam_ip_class"
77552ccf843Smisaki 		    " opt %x for class %d failed ", class_config, class));
77644961713Sgirish 		return (NXGE_ERROR | rs);
77744961713Sgirish 	}
77844961713Sgirish 	return (NXGE_OK);
77944961713Sgirish }
78044961713Sgirish 
78144961713Sgirish nxge_status_t
nxge_fflp_set_hash1(p_nxge_t nxgep,uint32_t h1)78244961713Sgirish nxge_fflp_set_hash1(p_nxge_t nxgep, uint32_t h1)
78344961713Sgirish {
78444961713Sgirish 	npi_status_t rs = NPI_SUCCESS;
78544961713Sgirish 	npi_handle_t handle;
786a3c5bd6dSspeer 	p_nxge_class_pt_cfg_t p_class_cfgp;
78744961713Sgirish 
78844961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL, " ==> nxge_fflp_init_h1"));
78944961713Sgirish 	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
79044961713Sgirish 	p_class_cfgp->init_h1 = h1;
79144961713Sgirish 	handle = nxgep->npi_reg_handle;
79244961713Sgirish 	rs = npi_fflp_cfg_hash_h1poly(handle, h1);
79344961713Sgirish 	if (rs & NPI_FFLP_ERROR) {
794a3c5bd6dSspeer 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
79552ccf843Smisaki 		    " nxge_fflp_init_h1 %x failed ", h1));
79644961713Sgirish 		return (NXGE_ERROR | rs);
79744961713Sgirish 	}
79844961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL, " <== nxge_fflp_init_h1"));
79944961713Sgirish 	return (NXGE_OK);
80044961713Sgirish }
80144961713Sgirish 
80244961713Sgirish nxge_status_t
nxge_fflp_set_hash2(p_nxge_t nxgep,uint16_t h2)80344961713Sgirish nxge_fflp_set_hash2(p_nxge_t nxgep, uint16_t h2)
80444961713Sgirish {
80544961713Sgirish 	npi_status_t rs = NPI_SUCCESS;
80644961713Sgirish 	npi_handle_t handle;
807a3c5bd6dSspeer 	p_nxge_class_pt_cfg_t p_class_cfgp;
80844961713Sgirish 
80944961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL, " ==> nxge_fflp_init_h2"));
81044961713Sgirish 	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
81144961713Sgirish 	p_class_cfgp->init_h2 = h2;
81244961713Sgirish 
81344961713Sgirish 	handle = nxgep->npi_reg_handle;
81444961713Sgirish 	rs = npi_fflp_cfg_hash_h2poly(handle, h2);
81544961713Sgirish 	if (rs & NPI_FFLP_ERROR) {
816a3c5bd6dSspeer 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
81752ccf843Smisaki 		    " nxge_fflp_init_h2 %x failed ", h2));
81844961713Sgirish 		return (NXGE_ERROR | rs);
81944961713Sgirish 	}
82044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL, " <== nxge_fflp_init_h2"));
82144961713Sgirish 	return (NXGE_OK);
82244961713Sgirish }
82344961713Sgirish 
82444961713Sgirish nxge_status_t
nxge_classify_init_sw(p_nxge_t nxgep)82544961713Sgirish nxge_classify_init_sw(p_nxge_t nxgep)
82644961713Sgirish {
82744961713Sgirish 	nxge_classify_t *classify_ptr;
82844961713Sgirish 
82944961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "==> nxge_classify_init_sw"));
83044961713Sgirish 	classify_ptr = &nxgep->classifier;
83144961713Sgirish 
83244961713Sgirish 	if (classify_ptr->state & NXGE_FFLP_SW_INIT) {
83344961713Sgirish 		NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
83452ccf843Smisaki 		    "nxge_classify_init_sw already init"));
83544961713Sgirish 		return (NXGE_OK);
83644961713Sgirish 	}
837a3c5bd6dSspeer 
8384df55fdeSJanie Lu 	classify_ptr->tcam_size = nxgep->nxge_hw_p->tcam_size / nxgep->nports;
8394df55fdeSJanie Lu 	classify_ptr->tcam_entries = (tcam_flow_spec_t *)nxgep->nxge_hw_p->tcam;
8404df55fdeSJanie Lu 	classify_ptr->tcam_top = nxgep->function_num;
84144961713Sgirish 
842a3c5bd6dSspeer 	/* Init defaults */
843a3c5bd6dSspeer 	/*
844a3c5bd6dSspeer 	 * add hacks required for HW shortcomings for example, code to handle
845a3c5bd6dSspeer 	 * fragmented packets
846a3c5bd6dSspeer 	 */
84744961713Sgirish 	nxge_init_h1_table();
84844961713Sgirish 	nxge_crc_ccitt_init();
84944961713Sgirish 	nxgep->classifier.tcam_location = nxgep->function_num;
85044961713Sgirish 	nxgep->classifier.fragment_bug = 1;
85144961713Sgirish 	classify_ptr->state |= NXGE_FFLP_SW_INIT;
85244961713Sgirish 
85344961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "<== nxge_classify_init_sw"));
85444961713Sgirish 	return (NXGE_OK);
85544961713Sgirish }
85644961713Sgirish 
85744961713Sgirish nxge_status_t
nxge_classify_exit_sw(p_nxge_t nxgep)85844961713Sgirish nxge_classify_exit_sw(p_nxge_t nxgep)
85944961713Sgirish {
86044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "==> nxge_classify_exit_sw"));
861b37cc459SToomas Soome 	nxgep->classifier.state = 0;
86244961713Sgirish 	NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "<== nxge_classify_exit_sw"));
86344961713Sgirish 	return (NXGE_OK);
86444961713Sgirish }
86544961713Sgirish 
86644961713Sgirish /*
86744961713Sgirish  * Figures out the RDC Group for the entry
86844961713Sgirish  *
86944961713Sgirish  * The current implementation is just a place holder and it
87044961713Sgirish  * returns 0.
87144961713Sgirish  * The real location determining algorithm would consider
87244961713Sgirish  * the partition etc ... before deciding w
87344961713Sgirish  *
87444961713Sgirish  */
875a3c5bd6dSspeer 
8760a8e077aSspeer /* ARGSUSED */
87744961713Sgirish static uint8_t
nxge_get_rdc_group(p_nxge_t nxgep,uint8_t class,uint64_t cookie)8784df55fdeSJanie Lu nxge_get_rdc_group(p_nxge_t nxgep, uint8_t class, uint64_t cookie)
87944961713Sgirish {
88044961713Sgirish 	int use_port_rdc_grp = 0;
88144961713Sgirish 	uint8_t rdc_grp = 0;
882a3c5bd6dSspeer 	p_nxge_dma_pt_cfg_t p_dma_cfgp;
883a3c5bd6dSspeer 	p_nxge_hw_pt_cfg_t p_cfgp;
884a3c5bd6dSspeer 	p_nxge_rdc_grp_t rdc_grp_p;
885a3c5bd6dSspeer 
88644961713Sgirish 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
88744961713Sgirish 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
88844961713Sgirish 	rdc_grp_p = &p_dma_cfgp->rdc_grps[use_port_rdc_grp];
889678453a8Sspeer 	rdc_grp = p_cfgp->def_mac_rxdma_grpid;
890a3c5bd6dSspeer 
89144961713Sgirish 	NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
89252ccf843Smisaki 	    "nxge_get_rdc_group: grp 0x%x real_grp %x grpp $%p\n",
89352ccf843Smisaki 	    cookie, rdc_grp, rdc_grp_p));
89444961713Sgirish 	return (rdc_grp);
89544961713Sgirish }
89644961713Sgirish 
89744961713Sgirish /* ARGSUSED */
89844961713Sgirish static uint8_t
nxge_get_rdc_offset(p_nxge_t nxgep,uint8_t class,uint64_t cookie)8994df55fdeSJanie Lu nxge_get_rdc_offset(p_nxge_t nxgep, uint8_t class, uint64_t cookie)
90044961713Sgirish {
90144961713Sgirish 	return ((uint8_t)cookie);
90244961713Sgirish }
90344961713Sgirish 
9040a8e077aSspeer /* ARGSUSED */
90544961713Sgirish static void
nxge_fill_tcam_entry_udp(p_nxge_t nxgep,flow_spec_t * flow_spec,tcam_entry_t * tcam_ptr)90644961713Sgirish nxge_fill_tcam_entry_udp(p_nxge_t nxgep, flow_spec_t *flow_spec,
907*86ef0a63SRichard Lowe     tcam_entry_t *tcam_ptr)
90844961713Sgirish {
909e3d11eeeSToomas Soome #define	fspec_key (flow_spec->uh.udpip4spec)
910e3d11eeeSToomas Soome #define	fspec_mask (flow_spec->um.udpip4spec)
911e3d11eeeSToomas Soome 
912e3d11eeeSToomas Soome 	TCAM_IPV4_ADDR(tcam_ptr->ip4_dest_key, fspec_key.ip4dst);
913e3d11eeeSToomas Soome 	TCAM_IPV4_ADDR(tcam_ptr->ip4_dest_mask, fspec_mask.ip4dst);
914e3d11eeeSToomas Soome 	TCAM_IPV4_ADDR(tcam_ptr->ip4_src_key, fspec_key.ip4src);
915e3d11eeeSToomas Soome 	TCAM_IPV4_ADDR(tcam_ptr->ip4_src_mask, fspec_mask.ip4src);
91644961713Sgirish 	TCAM_IP_PORTS(tcam_ptr->ip4_port_key,
917e3d11eeeSToomas Soome 	    fspec_key.pdst, fspec_key.psrc);
91844961713Sgirish 	TCAM_IP_PORTS(tcam_ptr->ip4_port_mask,
919e3d11eeeSToomas Soome 	    fspec_mask.pdst, fspec_mask.psrc);
92044961713Sgirish 	TCAM_IP_CLASS(tcam_ptr->ip4_class_key,
92152ccf843Smisaki 	    tcam_ptr->ip4_class_mask,
92252ccf843Smisaki 	    TCAM_CLASS_UDP_IPV4);
92344961713Sgirish 	TCAM_IP_PROTO(tcam_ptr->ip4_proto_key,
92452ccf843Smisaki 	    tcam_ptr->ip4_proto_mask,
92552ccf843Smisaki 	    IPPROTO_UDP);
926e3d11eeeSToomas Soome 	tcam_ptr->ip4_tos_key = fspec_key.tos;
927e3d11eeeSToomas Soome 	tcam_ptr->ip4_tos_mask = fspec_mask.tos;
928e3d11eeeSToomas Soome #undef fspec_key
929e3d11eeeSToomas Soome #undef fspec_mask
93044961713Sgirish }
93144961713Sgirish 
93244961713Sgirish static void
nxge_fill_tcam_entry_udp_ipv6(p_nxge_t nxgep,flow_spec_t * flow_spec,tcam_entry_t * tcam_ptr)93344961713Sgirish nxge_fill_tcam_entry_udp_ipv6(p_nxge_t nxgep, flow_spec_t *flow_spec,
934*86ef0a63SRichard Lowe     tcam_entry_t *tcam_ptr)
93544961713Sgirish {
936a3c5bd6dSspeer 	p_nxge_class_pt_cfg_t p_class_cfgp;
937e3d11eeeSToomas Soome #define	fspec_key (flow_spec->uh.udpip6spec)
938e3d11eeeSToomas Soome #define	fspec_mask (flow_spec->um.udpip6spec)
93944961713Sgirish 
94044961713Sgirish 	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
94144961713Sgirish 	if (p_class_cfgp->class_cfg[TCAM_CLASS_UDP_IPV6] &
94252ccf843Smisaki 	    NXGE_CLASS_TCAM_USE_SRC_ADDR) {
943e3d11eeeSToomas Soome 		TCAM_IPV6_ADDR(tcam_ptr->ip6_ip_addr_key, fspec_key.ip6src);
944e3d11eeeSToomas Soome 		TCAM_IPV6_ADDR(tcam_ptr->ip6_ip_addr_mask, fspec_mask.ip6src);
94544961713Sgirish 	} else {
946e3d11eeeSToomas Soome 		TCAM_IPV6_ADDR(tcam_ptr->ip6_ip_addr_key, fspec_key.ip6dst);
947e3d11eeeSToomas Soome 		TCAM_IPV6_ADDR(tcam_ptr->ip6_ip_addr_mask, fspec_mask.ip6dst);
94844961713Sgirish 	}
94944961713Sgirish 
95044961713Sgirish 	TCAM_IP_CLASS(tcam_ptr->ip6_class_key,
95152ccf843Smisaki 	    tcam_ptr->ip6_class_mask, TCAM_CLASS_UDP_IPV6);
95244961713Sgirish 	TCAM_IP_PROTO(tcam_ptr->ip6_nxt_hdr_key,
95352ccf843Smisaki 	    tcam_ptr->ip6_nxt_hdr_mask, IPPROTO_UDP);
95444961713Sgirish 	TCAM_IP_PORTS(tcam_ptr->ip6_port_key,
955e3d11eeeSToomas Soome 	    fspec_key.pdst, fspec_key.psrc);
95644961713Sgirish 	TCAM_IP_PORTS(tcam_ptr->ip6_port_mask,
957e3d11eeeSToomas Soome 	    fspec_mask.pdst, fspec_mask.psrc);
958e3d11eeeSToomas Soome 	tcam_ptr->ip6_tos_key = fspec_key.tos;
959e3d11eeeSToomas Soome 	tcam_ptr->ip6_tos_mask = fspec_mask.tos;
960e3d11eeeSToomas Soome #undef fspec_key
961e3d11eeeSToomas Soome #undef fspec_mask
96244961713Sgirish }
96344961713Sgirish 
9640a8e077aSspeer /* ARGSUSED */
96544961713Sgirish static void
nxge_fill_tcam_entry_tcp(p_nxge_t nxgep,flow_spec_t * flow_spec,tcam_entry_t * tcam_ptr)96644961713Sgirish nxge_fill_tcam_entry_tcp(p_nxge_t nxgep, flow_spec_t *flow_spec,
967*86ef0a63SRichard Lowe     tcam_entry_t *tcam_ptr)
96844961713Sgirish {
969e3d11eeeSToomas Soome #define	fspec_key (flow_spec->uh.tcpip4spec)
970e3d11eeeSToomas Soome #define	fspec_mask (flow_spec->um.tcpip4spec)
97144961713Sgirish 
972e3d11eeeSToomas Soome 	TCAM_IPV4_ADDR(tcam_ptr->ip4_dest_key, fspec_key.ip4dst);
973e3d11eeeSToomas Soome 	TCAM_IPV4_ADDR(tcam_ptr->ip4_dest_mask, fspec_mask.ip4dst);
974e3d11eeeSToomas Soome 	TCAM_IPV4_ADDR(tcam_ptr->ip4_src_key, fspec_key.ip4src);
975e3d11eeeSToomas Soome 	TCAM_IPV4_ADDR(tcam_ptr->ip4_src_mask, fspec_mask.ip4src);
97644961713Sgirish 	TCAM_IP_PORTS(tcam_ptr->ip4_port_key,
977e3d11eeeSToomas Soome 	    fspec_key.pdst, fspec_key.psrc);
97844961713Sgirish 	TCAM_IP_PORTS(tcam_ptr->ip4_port_mask,
979e3d11eeeSToomas Soome 	    fspec_mask.pdst, fspec_mask.psrc);
98044961713Sgirish 	TCAM_IP_CLASS(tcam_ptr->ip4_class_key,
98152ccf843Smisaki 	    tcam_ptr->ip4_class_mask, TCAM_CLASS_TCP_IPV4);
98244961713Sgirish 	TCAM_IP_PROTO(tcam_ptr->ip4_proto_key,
98352ccf843Smisaki 	    tcam_ptr->ip4_proto_mask, IPPROTO_TCP);
984e3d11eeeSToomas Soome 	tcam_ptr->ip4_tos_key = fspec_key.tos;
985e3d11eeeSToomas Soome 	tcam_ptr->ip4_tos_mask = fspec_mask.tos;
986e3d11eeeSToomas Soome #undef fspec_key
987e3d11eeeSToomas Soome #undef fspec_mask
98844961713Sgirish }
98944961713Sgirish 
9900a8e077aSspeer /* ARGSUSED */
99144961713Sgirish static void
nxge_fill_tcam_entry_sctp(p_nxge_t nxgep,flow_spec_t * flow_spec,tcam_entry_t * tcam_ptr)99244961713Sgirish nxge_fill_tcam_entry_sctp(p_nxge_t nxgep, flow_spec_t *flow_spec,
993*86ef0a63SRichard Lowe     tcam_entry_t *tcam_ptr)
99444961713Sgirish {
995e3d11eeeSToomas Soome #define	fspec_key (flow_spec->uh.tcpip4spec)
996e3d11eeeSToomas Soome #define	fspec_mask (flow_spec->um.tcpip4spec)
99744961713Sgirish 
998e3d11eeeSToomas Soome 	TCAM_IPV4_ADDR(tcam_ptr->ip4_dest_key, fspec_key.ip4dst);
999e3d11eeeSToomas Soome 	TCAM_IPV4_ADDR(tcam_ptr->ip4_dest_mask, fspec_mask.ip4dst);
1000e3d11eeeSToomas Soome 	TCAM_IPV4_ADDR(tcam_ptr->ip4_src_key, fspec_key.ip4src);
1001e3d11eeeSToomas Soome 	TCAM_IPV4_ADDR(tcam_ptr->ip4_src_mask, fspec_mask.ip4src);
100244961713Sgirish 	TCAM_IP_CLASS(tcam_ptr->ip4_class_key,
100352ccf843Smisaki 	    tcam_ptr->ip4_class_mask, TCAM_CLASS_SCTP_IPV4);
100444961713Sgirish 	TCAM_IP_PROTO(tcam_ptr->ip4_proto_key,
100552ccf843Smisaki 	    tcam_ptr->ip4_proto_mask, IPPROTO_SCTP);
100644961713Sgirish 	TCAM_IP_PORTS(tcam_ptr->ip4_port_key,
1007e3d11eeeSToomas Soome 	    fspec_key.pdst, fspec_key.psrc);
100844961713Sgirish 	TCAM_IP_PORTS(tcam_ptr->ip4_port_mask,
1009e3d11eeeSToomas Soome 	    fspec_mask.pdst, fspec_mask.psrc);
1010e3d11eeeSToomas Soome 	tcam_ptr->ip4_tos_key = fspec_key.tos;
1011e3d11eeeSToomas Soome 	tcam_ptr->ip4_tos_mask = fspec_mask.tos;
1012e3d11eeeSToomas Soome #undef fspec_key
1013e3d11eeeSToomas Soome #undef fspec_mask
101444961713Sgirish }
101544961713Sgirish 
101644961713Sgirish static void
nxge_fill_tcam_entry_tcp_ipv6(p_nxge_t nxgep,flow_spec_t * flow_spec,tcam_entry_t * tcam_ptr)101744961713Sgirish nxge_fill_tcam_entry_tcp_ipv6(p_nxge_t nxgep, flow_spec_t *flow_spec,
1018*86ef0a63SRichard Lowe     tcam_entry_t *tcam_ptr)
101944961713Sgirish {
1020a3c5bd6dSspeer 	p_nxge_class_pt_cfg_t p_class_cfgp;
1021e3d11eeeSToomas Soome #define	fspec_key (flow_spec->uh.tcpip6spec)
1022e3d11eeeSToomas Soome #define	fspec_mask (flow_spec->um.tcpip6spec)
102344961713Sgirish 
102444961713Sgirish 	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
102544961713Sgirish 	if (p_class_cfgp->class_cfg[TCAM_CLASS_UDP_IPV6] &
102652ccf843Smisaki 	    NXGE_CLASS_TCAM_USE_SRC_ADDR) {
1027e3d11eeeSToomas Soome 		TCAM_IPV6_ADDR(tcam_ptr->ip6_ip_addr_key, fspec_key.ip6src);
1028e3d11eeeSToomas Soome 		TCAM_IPV6_ADDR(tcam_ptr->ip6_ip_addr_mask, fspec_mask.ip6src);
102944961713Sgirish 	} else {
1030e3d11eeeSToomas Soome 		TCAM_IPV6_ADDR(tcam_ptr->ip6_ip_addr_key, fspec_key.ip6dst);
1031e3d11eeeSToomas Soome 		TCAM_IPV6_ADDR(tcam_ptr->ip6_ip_addr_mask, fspec_mask.ip6dst);
103244961713Sgirish 	}
103344961713Sgirish 
103444961713Sgirish 	TCAM_IP_CLASS(tcam_ptr->ip6_class_key,
103552ccf843Smisaki 	    tcam_ptr->ip6_class_mask, TCAM_CLASS_TCP_IPV6);
103644961713Sgirish 	TCAM_IP_PROTO(tcam_ptr->ip6_nxt_hdr_key,
103752ccf843Smisaki 	    tcam_ptr->ip6_nxt_hdr_mask, IPPROTO_TCP);
103844961713Sgirish 	TCAM_IP_PORTS(tcam_ptr->ip6_port_key,
1039e3d11eeeSToomas Soome 	    fspec_key.pdst, fspec_key.psrc);
104044961713Sgirish 	TCAM_IP_PORTS(tcam_ptr->ip6_port_mask,
1041e3d11eeeSToomas Soome 	    fspec_mask.pdst, fspec_mask.psrc);
1042e3d11eeeSToomas Soome 	tcam_ptr->ip6_tos_key = fspec_key.tos;
1043e3d11eeeSToomas Soome 	tcam_ptr->ip6_tos_mask = fspec_mask.tos;
1044e3d11eeeSToomas Soome #undef fspec_key
1045e3d11eeeSToomas Soome #undef fspec_mask
104644961713Sgirish }
104744961713Sgirish 
104844961713Sgirish static void
nxge_fill_tcam_entry_sctp_ipv6(p_nxge_t nxgep,flow_spec_t * flow_spec,tcam_entry_t * tcam_ptr)104944961713Sgirish nxge_fill_tcam_entry_sctp_ipv6(p_nxge_t nxgep, flow_spec_t *flow_spec,
1050*86ef0a63SRichard Lowe     tcam_entry_t *tcam_ptr)
105144961713Sgirish {
1052a3c5bd6dSspeer 	p_nxge_class_pt_cfg_t p_class_cfgp;
1053e3d11eeeSToomas Soome #define	fspec_key (flow_spec->uh.tcpip6spec)
1054e3d11eeeSToomas Soome #define	fspec_mask (flow_spec->um.tcpip6spec)
105544961713Sgirish 
105644961713Sgirish 	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
105744961713Sgirish 
105844961713Sgirish 	if (p_class_cfgp->class_cfg[TCAM_CLASS_UDP_IPV6] &
105952ccf843Smisaki 	    NXGE_CLASS_TCAM_USE_SRC_ADDR) {
1060e3d11eeeSToomas Soome 		TCAM_IPV6_ADDR(tcam_ptr->ip6_ip_addr_key, fspec_key.ip6src);
1061e3d11eeeSToomas Soome 		TCAM_IPV6_ADDR(tcam_ptr->ip6_ip_addr_mask, fspec_mask.ip6src);
106244961713Sgirish 	} else {
1063e3d11eeeSToomas Soome 		TCAM_IPV6_ADDR(tcam_ptr->ip6_ip_addr_key, fspec_key.ip6dst);
1064e3d11eeeSToomas Soome 		TCAM_IPV6_ADDR(tcam_ptr->ip6_ip_addr_mask, fspec_mask.ip6dst);
106544961713Sgirish 	}
106644961713Sgirish 
106744961713Sgirish 	TCAM_IP_CLASS(tcam_ptr->ip6_class_key,
106852ccf843Smisaki 	    tcam_ptr->ip6_class_mask, TCAM_CLASS_SCTP_IPV6);
106944961713Sgirish 	TCAM_IP_PROTO(tcam_ptr->ip6_nxt_hdr_key,
107052ccf843Smisaki 	    tcam_ptr->ip6_nxt_hdr_mask, IPPROTO_SCTP);
107144961713Sgirish 	TCAM_IP_PORTS(tcam_ptr->ip6_port_key,
1072e3d11eeeSToomas Soome 	    fspec_key.pdst, fspec_key.psrc);
107344961713Sgirish 	TCAM_IP_PORTS(tcam_ptr->ip6_port_mask,
1074e3d11eeeSToomas Soome 	    fspec_mask.pdst, fspec_mask.psrc);
1075e3d11eeeSToomas Soome 	tcam_ptr->ip6_tos_key = fspec_key.tos;
1076e3d11eeeSToomas Soome 	tcam_ptr->ip6_tos_mask = fspec_mask.tos;
1077e3d11eeeSToomas Soome #undef fspec_key
1078e3d11eeeSToomas Soome #undef fspec_mask
10794df55fdeSJanie Lu }
10804df55fdeSJanie Lu 
10814df55fdeSJanie Lu /* ARGSUSED */
10824df55fdeSJanie Lu static void
nxge_fill_tcam_entry_ah_esp(p_nxge_t nxgep,flow_spec_t * flow_spec,tcam_entry_t * tcam_ptr)10834df55fdeSJanie Lu nxge_fill_tcam_entry_ah_esp(p_nxge_t nxgep, flow_spec_t *flow_spec,
1084*86ef0a63SRichard Lowe     tcam_entry_t *tcam_ptr)
10854df55fdeSJanie Lu {
1086e3d11eeeSToomas Soome #define	fspec_key (flow_spec->uh.ahip4spec)
1087e3d11eeeSToomas Soome #define	fspec_mask (flow_spec->um.ahip4spec)
10884df55fdeSJanie Lu 
1089e3d11eeeSToomas Soome 	TCAM_IPV4_ADDR(tcam_ptr->ip4_dest_key, fspec_key.ip4dst);
1090e3d11eeeSToomas Soome 	TCAM_IPV4_ADDR(tcam_ptr->ip4_dest_mask, fspec_mask.ip4dst);
1091e3d11eeeSToomas Soome 	TCAM_IPV4_ADDR(tcam_ptr->ip4_src_key, fspec_key.ip4src);
1092e3d11eeeSToomas Soome 	TCAM_IPV4_ADDR(tcam_ptr->ip4_src_mask, fspec_mask.ip4src);
10934df55fdeSJanie Lu 
1094e3d11eeeSToomas Soome 	tcam_ptr->ip4_port_key = fspec_key.spi;
1095e3d11eeeSToomas Soome 	tcam_ptr->ip4_port_mask = fspec_mask.spi;
10964df55fdeSJanie Lu 
10974df55fdeSJanie Lu 	TCAM_IP_CLASS(tcam_ptr->ip4_class_key,
10984df55fdeSJanie Lu 	    tcam_ptr->ip4_class_mask,
10994df55fdeSJanie Lu 	    TCAM_CLASS_AH_ESP_IPV4);
11004df55fdeSJanie Lu 
11014df55fdeSJanie Lu 	if (flow_spec->flow_type == FSPEC_AHIP4) {
11024df55fdeSJanie Lu 		TCAM_IP_PROTO(tcam_ptr->ip4_proto_key,
11034df55fdeSJanie Lu 		    tcam_ptr->ip4_proto_mask, IPPROTO_AH);
11044df55fdeSJanie Lu 	} else {
11054df55fdeSJanie Lu 		TCAM_IP_PROTO(tcam_ptr->ip4_proto_key,
11064df55fdeSJanie Lu 		    tcam_ptr->ip4_proto_mask, IPPROTO_ESP);
11074df55fdeSJanie Lu 	}
1108e3d11eeeSToomas Soome 	tcam_ptr->ip4_tos_key = fspec_key.tos;
1109e3d11eeeSToomas Soome 	tcam_ptr->ip4_tos_mask = fspec_mask.tos;
1110e3d11eeeSToomas Soome #undef fspec_key
1111e3d11eeeSToomas Soome #undef fspec_mask
111244961713Sgirish }
111344961713Sgirish 
11144df55fdeSJanie Lu static void
nxge_fill_tcam_entry_ah_esp_ipv6(p_nxge_t nxgep,flow_spec_t * flow_spec,tcam_entry_t * tcam_ptr)11154df55fdeSJanie Lu nxge_fill_tcam_entry_ah_esp_ipv6(p_nxge_t nxgep, flow_spec_t *flow_spec,
1116*86ef0a63SRichard Lowe     tcam_entry_t *tcam_ptr)
11174df55fdeSJanie Lu {
11184df55fdeSJanie Lu 	p_nxge_class_pt_cfg_t p_class_cfgp;
1119e3d11eeeSToomas Soome #define	fspec_key (flow_spec->uh.ahip6spec)
1120e3d11eeeSToomas Soome #define	fspec_mask (flow_spec->um.ahip6spec)
11214df55fdeSJanie Lu 
11224df55fdeSJanie Lu 	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
11234df55fdeSJanie Lu 	if (p_class_cfgp->class_cfg[TCAM_CLASS_AH_ESP_IPV6] &
11244df55fdeSJanie Lu 	    NXGE_CLASS_TCAM_USE_SRC_ADDR) {
1125e3d11eeeSToomas Soome 		TCAM_IPV6_ADDR(tcam_ptr->ip6_ip_addr_key, fspec_key.ip6src);
1126e3d11eeeSToomas Soome 		TCAM_IPV6_ADDR(tcam_ptr->ip6_ip_addr_mask, fspec_mask.ip6src);
11274df55fdeSJanie Lu 	} else {
1128e3d11eeeSToomas Soome 		TCAM_IPV6_ADDR(tcam_ptr->ip6_ip_addr_key, fspec_key.ip6dst);
1129e3d11eeeSToomas Soome 		TCAM_IPV6_ADDR(tcam_ptr->ip6_ip_addr_mask, fspec_mask.ip6dst);
11304df55fdeSJanie Lu 	}
11314df55fdeSJanie Lu 
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