xref: /illumos-gate/usr/src/uts/common/io/nxge/npi/npi_zcp.h (revision 6f45ec7b)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef _NPI_ZCP_H
27 #define	_NPI_ZCP_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #ifdef	__cplusplus
32 extern "C" {
33 #endif
34 
35 #include <npi.h>
36 #include <nxge_zcp_hw.h>
37 
38 typedef	enum zcp_buf_region_e {
39 	BAM_4BUF			= 1,
40 	BAM_8BUF			= 2,
41 	BAM_16BUF			= 3,
42 	BAM_32BUF			= 4
43 } zcp_buf_region_t;
44 
45 typedef enum zcp_config_e {
46 	CFG_ZCP				= 0x01,
47 	CFG_ZCP_ECC_CHK			= 0x02,
48 	CFG_ZCP_PAR_CHK			= 0x04,
49 	CFG_ZCP_BUF_RESP		= 0x08,
50 	CFG_ZCP_BUF_REQ			= 0x10,
51 	CFG_ZCP_ALL			= 0x1F
52 } zcp_config_t;
53 
54 typedef enum zcp_iconfig_e {
55 	ICFG_ZCP_RRFIFO_UNDERRUN	= RRFIFO_UNDERRUN,
56 	ICFG_ZCP_RRFIFO_OVERRUN		= RRFIFO_OVERRUN,
57 	ICFG_ZCP_RSPFIFO_UNCORR_ERR	= RSPFIFO_UNCORR_ERR,
58 	ICFG_ZCP_BUFFER_OVERFLOW	= BUFFER_OVERFLOW,
59 	ICFG_ZCP_STAT_TBL_PERR		= STAT_TBL_PERR,
60 	ICFG_ZCP_DYN_TBL_PERR		= BUF_DYN_TBL_PERR,
61 	ICFG_ZCP_BUF_TBL_PERR		= BUF_TBL_PERR,
62 	ICFG_ZCP_TT_PROGRAM_ERR		= TT_PROGRAM_ERR,
63 	ICFG_ZCP_RSP_TT_INDEX_ERR	= RSP_TT_INDEX_ERR,
64 	ICFG_ZCP_SLV_TT_INDEX_ERR	= SLV_TT_INDEX_ERR,
65 	ICFG_ZCP_TT_INDEX_ERR		= ZCP_TT_INDEX_ERR,
66 	ICFG_ZCP_CFIFO_ECC3		= CFIFO_ECC3,
67 	ICFG_ZCP_CFIFO_ECC2		= CFIFO_ECC2,
68 	ICFG_ZCP_CFIFO_ECC1		= CFIFO_ECC1,
69 	ICFG_ZCP_CFIFO_ECC0		= CFIFO_ECC0,
70 	ICFG_ZCP_ALL			= (RRFIFO_UNDERRUN | RRFIFO_OVERRUN |
71 				RSPFIFO_UNCORR_ERR | STAT_TBL_PERR |
72 				BUF_DYN_TBL_PERR | BUF_TBL_PERR |
73 				TT_PROGRAM_ERR | RSP_TT_INDEX_ERR |
74 				SLV_TT_INDEX_ERR | ZCP_TT_INDEX_ERR |
75 				CFIFO_ECC3 | CFIFO_ECC2 |  CFIFO_ECC1 |
76 				CFIFO_ECC0 | BUFFER_OVERFLOW)
77 } zcp_iconfig_t;
78 
79 typedef enum tte_sflow_attr_mask_e {
80 	TTE_RDC_TBL_OFF			= 0x0001,
81 	TTE_BUF_SIZE			= 0x0002,
82 	TTE_NUM_BUF			= 0x0004,
83 	TTE_ULP_END			= 0x0008,
84 	TTE_ULP_END_EN			= 0x0010,
85 	TTE_UNMAP_ALL_EN		= 0x0020,
86 	TTE_TMODE			= 0x0040,
87 	TTE_SKIP			= 0x0080,
88 	TTE_HBM_RING_BASE_ADDR		= 0x0100,
89 	TTE_HBM_RING_SIZE		= 0x0200,
90 	TTE_HBM_BUSY			= 0x0400,
91 	TTE_HBM_TOQ			= 0x0800,
92 	TTE_SFLOW_ATTR_ALL		= 0x0FFF
93 } tte_sflow_attr_mask_t;
94 
95 typedef	enum tte_dflow_attr_mask_e {
96 	TTE_MAPPED_IN			= 0x0001,
97 	TTE_ANCHOR_SEQ			= 0x0002,
98 	TTE_ANCHOR_OFFSET		= 0x0004,
99 	TTE_ANCHOR_BUFFER		= 0x0008,
100 	TTE_ANCHOR_BUF_FLAG		= 0x0010,
101 	TTE_UNMAP_ON_LEFT		= 0x0020,
102 	TTE_ULP_END_REACHED		= 0x0040,
103 	TTE_ERR_STAT			= 0x0080,
104 	TTE_HBM_WR_PTR			= 0x0100,
105 	TTE_HBM_HOQ			= 0x0200,
106 	TTE_HBM_PREFETCH_ON		= 0x0400,
107 	TTE_DFLOW_ATTR_ALL		= 0x07FF
108 } tte_dflow_attr_mask_t;
109 
110 #define	IS_VALID_BAM_REGION(region)\
111 		((region == BAM_4BUF) || (region == BAM_8BUF) ||\
112 		(region == BAM_16BUF) || (region == BAM_32BUF))
113 
114 #define	ZCP_WAIT_RAM_READY(handle, val) {\
115 	uint32_t cnt = MAX_PIO_RETRIES;\
116 	do {\
117 		NXGE_REG_RD64(handle, ZCP_RAM_ACC_REG, &val);\
118 		cnt--;\
119 	} while ((ram_ctl.bits.ldw.busy != 0) && (cnt > 0));\
120 }
121 
122 #define	ZCP_DMA_THRES_INVALID		0x10
123 #define	ZCP_BAM_REGION_INVALID		0x11
124 #define	ZCP_ROW_INDEX_INVALID		0x12
125 #define	ZCP_SFLOW_ATTR_INVALID		0x13
126 #define	ZCP_DFLOW_ATTR_INVALID		0x14
127 #define	ZCP_FLOW_ID_INVALID		0x15
128 #define	ZCP_BAM_BANK_INVALID		0x16
129 #define	ZCP_BAM_WORD_EN_INVALID		0x17
130 
131 #define	NPI_ZCP_OPCODE_INVALID		((ZCP_BLK_ID << 8) | OPCODE_INVALID)
132 #define	NPI_ZCP_CONFIG_INVALID		((ZCP_BLK_ID << 8) | CONFIG_INVALID)
133 #define	NPI_ZCP_DMA_THRES_INVALID	((ZCP_BLK_ID << 8) |\
134 					ZCP_DMA_THRES_INVALID)
135 #define	NPI_ZCP_BAM_REGION_INVALID	((ZCP_BLK_ID << 8) |\
136 					ZCP_BAM_REGION_INVALID)
137 #define	NPI_ZCP_ROW_INDEX_INVALID	((ZCP_BLK_ID << 8) |\
138 					ZCP_ROW_INDEX_INVALID)
139 #define	NPI_ZCP_SFLOW_ATTR_INVALID	((ZCP_BLK_ID << 8) |\
140 					ZCP_SFLOW_ATTR_INVALID)
141 #define	NPI_ZCP_DFLOW_ATTR_INVALID	((ZCP_BLK_ID << 8) |\
142 					ZCP_DFLOW_ATTR_INVALID)
143 #define	NPI_ZCP_FLOW_ID_INVALID		((ZCP_BLK_ID << 8) |\
144 					ZCP_FLOW_ID_INVALID)
145 #define	NPI_ZCP_MEM_WRITE_FAILED	((ZCP_BLK_ID << 8) | WRITE_FAILED)
146 #define	NPI_ZCP_MEM_READ_FAILED		((ZCP_BLK_ID << 8) | READ_FAILED)
147 #define	NPI_ZCP_BAM_BANK_INVALID	((ZCP_BLK_ID << 8) |\
148 					(ZCP_BAM_BANK_INVALID))
149 #define	NPI_ZCP_BAM_WORD_EN_INVALID	((ZCP_BLK_ID << 8) |\
150 					(ZCP_BAM_WORD_EN_INVALID))
151 #define	NPI_ZCP_PORT_INVALID(portn)	((ZCP_BLK_ID << 8) | PORT_INVALID |\
152 					(portn << 12))
153 
154 /* ZCP HW NPI Prototypes */
155 npi_status_t npi_zcp_config(npi_handle_t, config_op_t,
156 				zcp_config_t);
157 npi_status_t npi_zcp_iconfig(npi_handle_t, config_op_t,
158 				zcp_iconfig_t);
159 npi_status_t npi_zcp_get_istatus(npi_handle_t, zcp_iconfig_t *);
160 npi_status_t npi_zcp_clear_istatus(npi_handle_t);
161 npi_status_t npi_zcp_set_dma_thresh(npi_handle_t, uint16_t);
162 npi_status_t npi_zcp_set_bam_region(npi_handle_t,
163 				zcp_buf_region_t,
164 				zcp_bam_region_reg_t *);
165 npi_status_t npi_zcp_set_sdt_region(npi_handle_t,
166 				zcp_buf_region_t, uint16_t);
167 npi_status_t npi_zcp_tt_static_entry(npi_handle_t, io_op_t,
168 				uint16_t, tte_sflow_attr_mask_t,
169 				tte_sflow_attr_t *);
170 npi_status_t npi_zcp_tt_dynamic_entry(npi_handle_t, io_op_t,
171 				uint16_t, tte_dflow_attr_mask_t,
172 				tte_dflow_attr_t *);
173 npi_status_t npi_zcp_tt_bam_entry(npi_handle_t, io_op_t,
174 				uint16_t, uint8_t,
175 				uint8_t, zcp_ram_unit_t *);
176 npi_status_t npi_zcp_tt_cfifo_entry(npi_handle_t, io_op_t,
177 				uint8_t, uint16_t,
178 				zcp_ram_unit_t *);
179 
180 npi_status_t npi_zcp_rest_cfifo_port(npi_handle_t, uint8_t);
181 npi_status_t npi_zcp_rest_cfifo_all(npi_handle_t);
182 
183 #ifdef	__cplusplus
184 }
185 #endif
186 
187 #endif	/* _NPI_ZCP_H */
188