xref: /illumos-gate/usr/src/uts/common/io/nxge/npi/npi_vir.c (revision 73ff8cc6)
144961713Sgirish /*
244961713Sgirish  * CDDL HEADER START
344961713Sgirish  *
444961713Sgirish  * The contents of this file are subject to the terms of the
544961713Sgirish  * Common Development and Distribution License (the "License").
644961713Sgirish  * You may not use this file except in compliance with the License.
744961713Sgirish  *
844961713Sgirish  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
944961713Sgirish  * or http://www.opensolaris.org/os/licensing.
1044961713Sgirish  * See the License for the specific language governing permissions
1144961713Sgirish  * and limitations under the License.
1244961713Sgirish  *
1344961713Sgirish  * When distributing Covered Code, include this CDDL HEADER in each
1444961713Sgirish  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1544961713Sgirish  * If applicable, add the following below this CDDL HEADER, with the
1644961713Sgirish  * fields enclosed by brackets "[]" replaced with your own identifying
1744961713Sgirish  * information: Portions Copyright [yyyy] [name of copyright owner]
1844961713Sgirish  *
1944961713Sgirish  * CDDL HEADER END
2044961713Sgirish  */
2144961713Sgirish /*
22678453a8Sspeer  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
2344961713Sgirish  * Use is subject to license terms.
2444961713Sgirish  */
2544961713Sgirish 
26a3c5bd6dSspeer #include <npi_vir.h>
2744961713Sgirish 
2844961713Sgirish /* One register only */
2944961713Sgirish uint64_t pio_offset[] = {
3044961713Sgirish 	DEV_FUNC_SR_REG
3144961713Sgirish };
3244961713Sgirish 
3344961713Sgirish const char *pio_name[] = {
3444961713Sgirish 	"DEV_FUNC_SR_REG",
3544961713Sgirish };
3644961713Sgirish 
3744961713Sgirish /* One register only */
3844961713Sgirish uint64_t fzc_pio_offset[] = {
3944961713Sgirish 	MULTI_PART_CTL_REG,
4044961713Sgirish 	LDGITMRES_REG
4144961713Sgirish };
4244961713Sgirish 
4344961713Sgirish const char *fzc_pio_name[] = {
4444961713Sgirish 	"MULTI_PART_CTL_REG",
4544961713Sgirish 	"LDGITMRES_REG"
4644961713Sgirish };
4744961713Sgirish 
4844961713Sgirish /* 64 sets */
4944961713Sgirish uint64_t fzc_pio_dma_bind_offset[] = {
5044961713Sgirish 	DMA_BIND_REG
5144961713Sgirish };
5244961713Sgirish 
5344961713Sgirish const char *fzc_pio_dma_bind_name[] = {
5444961713Sgirish 	"DMA_BIND_REG",
5544961713Sgirish };
5644961713Sgirish 
5744961713Sgirish /* 69 logical devices */
5844961713Sgirish uint64_t fzc_pio_ldgnum_offset[] = {
5944961713Sgirish 	LDG_NUM_REG
6044961713Sgirish };
6144961713Sgirish 
6244961713Sgirish const char *fzc_pio_ldgnum_name[] = {
6344961713Sgirish 	"LDG_NUM_REG",
6444961713Sgirish };
6544961713Sgirish 
6644961713Sgirish /* PIO_LDSV, 64 sets by 8192 bytes */
6744961713Sgirish uint64_t pio_ldsv_offset[] = {
6844961713Sgirish 	LDSV0_REG,
6944961713Sgirish 	LDSV1_REG,
7044961713Sgirish 	LDSV2_REG,
7144961713Sgirish 	LDGIMGN_REG
7244961713Sgirish };
7344961713Sgirish const char *pio_ldsv_name[] = {
7444961713Sgirish 	"LDSV0_REG",
7544961713Sgirish 	"LDSV1_REG",
7644961713Sgirish 	"LDSV2_REG",
7744961713Sgirish 	"LDGIMGN_REG"
7844961713Sgirish };
7944961713Sgirish 
8044961713Sgirish /* PIO_IMASK0: 64 by 8192 */
8144961713Sgirish uint64_t pio_imask0_offset[] = {
8244961713Sgirish 	LD_IM0_REG,
8344961713Sgirish };
8444961713Sgirish 
8544961713Sgirish const char *pio_imask0_name[] = {
8644961713Sgirish 	"LD_IM0_REG",
8744961713Sgirish };
8844961713Sgirish 
8944961713Sgirish /* PIO_IMASK1: 5 by 8192 */
9044961713Sgirish uint64_t pio_imask1_offset[] = {
9144961713Sgirish 	LD_IM1_REG
9244961713Sgirish };
9344961713Sgirish 
9444961713Sgirish const char *pio_imask1_name[] = {
9544961713Sgirish 	"LD_IM1_REG"
9644961713Sgirish };
9744961713Sgirish 
9844961713Sgirish /* SID: 64 by 8 */
9944961713Sgirish uint64_t fzc_pio_sid_offset[] = {
10044961713Sgirish 	SID_REG
10144961713Sgirish };
10244961713Sgirish 
10344961713Sgirish const char *fzc_pio_sid_name[] = {
10444961713Sgirish 	"SID_REG"
10544961713Sgirish };
10644961713Sgirish 
10744961713Sgirish npi_status_t
npi_vir_dump_pio_fzc_regs_one(npi_handle_t handle)10844961713Sgirish npi_vir_dump_pio_fzc_regs_one(npi_handle_t handle)
10944961713Sgirish {
11044961713Sgirish 	uint64_t value;
11144961713Sgirish 	int num_regs, i;
11244961713Sgirish 
11344961713Sgirish 	NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
11452ccf843Smisaki 	    "\nPIO FZC Common Register Dump\n"));
11544961713Sgirish 
11644961713Sgirish 	num_regs = sizeof (pio_offset) / sizeof (uint64_t);
11744961713Sgirish 	for (i = 0; i < num_regs; i++) {
11844961713Sgirish 		value = 0;
11944961713Sgirish 		NXGE_REG_RD64(handle, pio_offset[i], &value);
12044961713Sgirish 		NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, "0x%08llx "
12152ccf843Smisaki 		    "%s\t 0x%08llx \n",
12252ccf843Smisaki 		    pio_offset[i],
12352ccf843Smisaki 		    pio_name[i], value));
12444961713Sgirish 	}
12544961713Sgirish 
12644961713Sgirish 	num_regs = sizeof (fzc_pio_offset) / sizeof (uint64_t);
12744961713Sgirish 	for (i = 0; i < num_regs; i++) {
12844961713Sgirish 		NXGE_REG_RD64(handle, fzc_pio_offset[i], &value);
12944961713Sgirish 		NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, "0x%08llx "
13052ccf843Smisaki 		    "%s\t 0x%08llx \n",
13152ccf843Smisaki 		    fzc_pio_offset[i],
13252ccf843Smisaki 		    fzc_pio_name[i], value));
13344961713Sgirish 	}
13444961713Sgirish 
13544961713Sgirish 	NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
13652ccf843Smisaki 	    "\n PIO FZC Register Dump Done \n"));
13744961713Sgirish 	return (NPI_SUCCESS);
13844961713Sgirish }
13944961713Sgirish 
14044961713Sgirish npi_status_t
npi_vir_dump_ldgnum(npi_handle_t handle)14144961713Sgirish npi_vir_dump_ldgnum(npi_handle_t handle)
14244961713Sgirish {
14344961713Sgirish 	uint64_t value = 0, offset = 0;
14444961713Sgirish 	int num_regs, i, ldv;
14544961713Sgirish 
14644961713Sgirish 	NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
14752ccf843Smisaki 	    "\nFZC PIO LDG Number Register Dump\n"));
14844961713Sgirish 
14944961713Sgirish 	num_regs = sizeof (fzc_pio_ldgnum_offset) / sizeof (uint64_t);
15044961713Sgirish 	for (ldv = 0; ldv < NXGE_INT_MAX_LDS; ldv++) {
15144961713Sgirish 		for (i = 0; i < num_regs; i++) {
15244961713Sgirish 			value = 0;
15344961713Sgirish 			offset = fzc_pio_ldgnum_offset[i] + 8 * ldv;
15444961713Sgirish 			NXGE_REG_RD64(handle, offset, &value);
15544961713Sgirish 			NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
15652ccf843Smisaki 			    "Logical Device %d: 0x%08llx "
15752ccf843Smisaki 			    "%s\t %d\n",
15852ccf843Smisaki 			    ldv, offset,
15952ccf843Smisaki 			    fzc_pio_ldgnum_name[i], value));
16044961713Sgirish 		}
16144961713Sgirish 	}
16244961713Sgirish 
16344961713Sgirish 	NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
16452ccf843Smisaki 	    "\n FZC PIO LDG Register Dump Done \n"));
16544961713Sgirish 
16644961713Sgirish 	return (NPI_SUCCESS);
16744961713Sgirish }
16844961713Sgirish 
16944961713Sgirish npi_status_t
npi_vir_dump_ldsv(npi_handle_t handle)17044961713Sgirish npi_vir_dump_ldsv(npi_handle_t handle)
17144961713Sgirish {
17244961713Sgirish 	uint64_t value, offset;
17344961713Sgirish 	int num_regs, i, ldg;
17444961713Sgirish 
17544961713Sgirish 	NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
17652ccf843Smisaki 	    "\nLD Device State Vector Register Dump\n"));
17744961713Sgirish 
17844961713Sgirish 	num_regs = sizeof (pio_ldsv_offset) / sizeof (uint64_t);
17944961713Sgirish 	for (ldg = 0; ldg < NXGE_INT_MAX_LDGS; ldg++) {
18044961713Sgirish 		for (i = 0; i < num_regs; i++) {
18144961713Sgirish 			value = 0;
18244961713Sgirish 			offset = pio_ldsv_offset[i] + 8192 * ldg;
18344961713Sgirish 			NXGE_REG_RD64(handle, offset, &value);
18444961713Sgirish 			NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
18552ccf843Smisaki 			    "LDG State: group %d: 0x%08llx "
18652ccf843Smisaki 			    "%s\t 0x%08llx \n",
18752ccf843Smisaki 			    ldg, offset,
18852ccf843Smisaki 			    pio_ldsv_name[i], value));
18944961713Sgirish 		}
19044961713Sgirish 	}
19144961713Sgirish 
19244961713Sgirish 	NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
19352ccf843Smisaki 	    "\n FZC PIO LDG Register Dump Done \n"));
19444961713Sgirish 
19544961713Sgirish 	return (NPI_SUCCESS);
19644961713Sgirish }
19744961713Sgirish 
19844961713Sgirish npi_status_t
npi_vir_dump_imask0(npi_handle_t handle)19944961713Sgirish npi_vir_dump_imask0(npi_handle_t handle)
20044961713Sgirish {
20144961713Sgirish 	uint64_t value, offset;
20244961713Sgirish 	int num_regs, i, ldv;
20344961713Sgirish 
20444961713Sgirish 	NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
20552ccf843Smisaki 	    "\nLD Interrupt Mask Register Dump\n"));
20644961713Sgirish 
20744961713Sgirish 	num_regs = sizeof (pio_imask0_offset) / sizeof (uint64_t);
20844961713Sgirish 	for (ldv = 0; ldv < 64; ldv++) {
20944961713Sgirish 		for (i = 0; i < num_regs; i++) {
21044961713Sgirish 			value = 0;
21144961713Sgirish 			offset = pio_imask0_offset[i] + 8192 * ldv;
21244961713Sgirish 			NXGE_REG_RD64(handle, offset,
21352ccf843Smisaki 			    &value);
21444961713Sgirish 			NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
21552ccf843Smisaki 			    "LD Interrupt Mask %d: 0x%08llx "
21652ccf843Smisaki 			    "%s\t 0x%08llx \n",
21752ccf843Smisaki 			    ldv, offset,
21852ccf843Smisaki 			    pio_imask0_name[i], value));
21944961713Sgirish 		}
22044961713Sgirish 	}
22144961713Sgirish 	num_regs = sizeof (pio_imask1_offset) / sizeof (uint64_t);
22244961713Sgirish 	for (ldv = 64; ldv < 69; ldv++) {
22344961713Sgirish 		for (i = 0; i < num_regs; i++) {
22444961713Sgirish 			value = 0;
22544961713Sgirish 			offset = pio_imask1_offset[i] + 8192 * (ldv - 64);
22644961713Sgirish 			NXGE_REG_RD64(handle, offset,
22752ccf843Smisaki 			    &value);
22844961713Sgirish 			NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
22952ccf843Smisaki 			    "LD Interrupt Mask %d: 0x%08llx "
23052ccf843Smisaki 			    "%s\t 0x%08llx \n",
23152ccf843Smisaki 			    ldv, offset,
23252ccf843Smisaki 			    pio_imask1_name[i], value));
23344961713Sgirish 		}
23444961713Sgirish 	}
23544961713Sgirish 
23644961713Sgirish 	NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
23752ccf843Smisaki 	    "\n FZC PIO Logical Device Group Register Dump Done \n"));
23844961713Sgirish 
23944961713Sgirish 	return (NPI_SUCCESS);
24044961713Sgirish }
24144961713Sgirish 
24244961713Sgirish npi_status_t
npi_vir_dump_sid(npi_handle_t handle)24344961713Sgirish npi_vir_dump_sid(npi_handle_t handle)
24444961713Sgirish {
24544961713Sgirish 	uint64_t value, offset;
24644961713Sgirish 	int num_regs, i, ldg;
24744961713Sgirish 
24844961713Sgirish 	NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
24952ccf843Smisaki 	    "\nSystem Interrupt Data Register Dump\n"));
25044961713Sgirish 
25144961713Sgirish 	num_regs = sizeof (fzc_pio_sid_offset) / sizeof (uint64_t);
25244961713Sgirish 	for (ldg = 0; ldg < NXGE_INT_MAX_LDGS; ldg++) {
25344961713Sgirish 		for (i = 0; i < num_regs; i++) {
25444961713Sgirish 			value = 0;
25544961713Sgirish 			offset = fzc_pio_sid_offset[i] + 8 * ldg;
25644961713Sgirish 			NXGE_REG_RD64(handle, offset,
25752ccf843Smisaki 			    &value);
25844961713Sgirish 			NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
25952ccf843Smisaki 			    "SID for group %d: 0x%08llx "
26052ccf843Smisaki 			    "%s\t 0x%08llx \n",
26152ccf843Smisaki 			    ldg, offset,
26252ccf843Smisaki 			    fzc_pio_sid_name[i], value));
26344961713Sgirish 		}
26444961713Sgirish 	}
26544961713Sgirish 
26644961713Sgirish 	NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
26752ccf843Smisaki 	    "\n FZC PIO SID Register Dump Done \n"));
26844961713Sgirish 
26944961713Sgirish 	return (NPI_SUCCESS);
27044961713Sgirish }
27144961713Sgirish 
27244961713Sgirish /*
27344961713Sgirish  * npi_dev_func_sr_init():
27444961713Sgirish  *	This function is called to initialize the device function
27544961713Sgirish  *	shared register (set the software implementation lock
27644961713Sgirish  *	state to FREE).
27744961713Sgirish  * Parameters:
27844961713Sgirish  *	handle		- NPI handle
27944961713Sgirish  * Return:
28044961713Sgirish  *	NPI_SUCCESS	- If initialization is complete successfully.
28144961713Sgirish  *			  (set sr bits to free).
28244961713Sgirish  *	Error:
28344961713Sgirish  *	NPI_FAILURE
28444961713Sgirish  *		VIR_TAS_BUSY
28544961713Sgirish  */
286a3c5bd6dSspeer 
28744961713Sgirish npi_status_t
npi_dev_func_sr_init(npi_handle_t handle)28844961713Sgirish npi_dev_func_sr_init(npi_handle_t handle)
28944961713Sgirish {
29044961713Sgirish 	dev_func_sr_t		sr;
29144961713Sgirish 	int			status = NPI_SUCCESS;
29244961713Sgirish 
29344961713Sgirish 	NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value);
29444961713Sgirish 	if (!sr.bits.ldw.tas) {
29544961713Sgirish 		/*
29644961713Sgirish 		 * After read, this bit is set to 1 by hardware.
29744961713Sgirish 		 * We own it if tas bit read as 0.
29844961713Sgirish 		 * Set the lock state to free if it is in reset state.
29944961713Sgirish 		 */
30044961713Sgirish 		if (!sr.bits.ldw.sr) {
30144961713Sgirish 			/* reset state */
30244961713Sgirish 			sr.bits.ldw.sr |= NPI_DEV_SR_LOCK_ST_FREE;
30344961713Sgirish 			NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value);
30444961713Sgirish 			sr.bits.ldw.tas = 0;
30544961713Sgirish 			NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value);
30644961713Sgirish 		}
30744961713Sgirish 
30856d930aeSspeer 		NPI_DEBUG_MSG((handle.function, NPI_VIR_CTL,
30952ccf843Smisaki 		    " npi_dev_func_sr_init"
31052ccf843Smisaki 		    " sr <0x%x>",
31152ccf843Smisaki 		    sr.bits.ldw.sr));
31244961713Sgirish 	} else {
31344961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
31452ccf843Smisaki 		    " npi_dev_func_sr_init"
31552ccf843Smisaki 		    " tas busy <0x%x>",
31652ccf843Smisaki 		    sr.bits.ldw));
31744961713Sgirish 		status = NPI_VIR_TAS_BUSY(sr.bits.ldw.funcid);
31844961713Sgirish 	}
31944961713Sgirish 
32044961713Sgirish 	return (status);
32144961713Sgirish }
32244961713Sgirish 
32344961713Sgirish /*
32444961713Sgirish  * npi_dev_func_sr_lock_enter():
32544961713Sgirish  *	This function is called to lock the function shared register
32644961713Sgirish  *	by setting the lock state to busy.
32744961713Sgirish  * Parameters:
32844961713Sgirish  *	handle		- NPI handle
32944961713Sgirish  * Return:
33044961713Sgirish  *	NPI_SUCCESS	- If the function id can own the lock.
33144961713Sgirish  *
33244961713Sgirish  *	Error:
33344961713Sgirish  *	NPI_FAILURE
33444961713Sgirish  *		VIR_SR_RESET
33544961713Sgirish  *		VIR_SR_BUSY
33644961713Sgirish  *		VIR_SR_INVALID
33744961713Sgirish  *		VIR_TAS_BUSY
33844961713Sgirish  */
339a3c5bd6dSspeer 
34044961713Sgirish npi_status_t
npi_dev_func_sr_lock_enter(npi_handle_t handle)34144961713Sgirish npi_dev_func_sr_lock_enter(npi_handle_t handle)
34244961713Sgirish {
34344961713Sgirish 	dev_func_sr_t		sr;
34444961713Sgirish 	int			status = NPI_SUCCESS;
34544961713Sgirish 	uint32_t		state;
34644961713Sgirish 
34744961713Sgirish 	NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value);
34844961713Sgirish 	if (!sr.bits.ldw.tas) {
34944961713Sgirish 		/*
35044961713Sgirish 		 * tas bit will be set to 1 by hardware.
35144961713Sgirish 		 * reset tas bit when we unlock the sr.
35244961713Sgirish 		 */
35344961713Sgirish 		state = sr.bits.ldw.sr & NPI_DEV_SR_LOCK_ST_MASK;
35444961713Sgirish 		switch (state) {
35544961713Sgirish 		case NPI_DEV_SR_LOCK_ST_FREE:
35644961713Sgirish 			/*
35744961713Sgirish 			 * set it to busy and our function id.
35844961713Sgirish 			 */
35944961713Sgirish 			sr.bits.ldw.sr |= (NPI_DEV_SR_LOCK_ST_BUSY |
36052ccf843Smisaki 			    (sr.bits.ldw.funcid <<
36152ccf843Smisaki 			    NPI_DEV_SR_LOCK_FID_SHIFT));
36244961713Sgirish 			NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value);
36344961713Sgirish 			break;
36444961713Sgirish 
36544961713Sgirish 		case NPI_DEV_SR_LOCK_ST_RESET:
36644961713Sgirish 			NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
36752ccf843Smisaki 			    " npi_dev_func_sr_lock_enter"
36852ccf843Smisaki 			    " reset state <0x%x>",
36952ccf843Smisaki 			    sr.bits.ldw.sr));
37044961713Sgirish 			status = NPI_VIR_SR_RESET(sr.bits.ldw.funcid);
37144961713Sgirish 			break;
37244961713Sgirish 
37344961713Sgirish 		case NPI_DEV_SR_LOCK_ST_BUSY:
37444961713Sgirish 			NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
37552ccf843Smisaki 			    " npi_dev_func_sr_lock_enter"
37652ccf843Smisaki 			    " busy <0x%x>",
37752ccf843Smisaki 			    sr.bits.ldw.sr));
37844961713Sgirish 			status = NPI_VIR_SR_BUSY(sr.bits.ldw.funcid);
37944961713Sgirish 			break;
38044961713Sgirish 
38144961713Sgirish 		default:
38244961713Sgirish 			NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
38352ccf843Smisaki 			    " npi_dev_func_sr_lock_enter",
38452ccf843Smisaki 			    " invalid state",
38552ccf843Smisaki 			    sr.bits.ldw.sr));
38644961713Sgirish 			status = NPI_VIR_SR_INVALID(sr.bits.ldw.funcid);
38744961713Sgirish 			break;
38844961713Sgirish 		}
38944961713Sgirish 	} else {
39044961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
39152ccf843Smisaki 		    " npi_dev_func_sr_lock_enter",
39252ccf843Smisaki 		    " tas busy", sr.bits.ldw));
39344961713Sgirish 		status = NPI_VIR_TAS_BUSY(sr.bits.ldw.funcid);
39444961713Sgirish 	}
39544961713Sgirish 
39644961713Sgirish 	return (status);
39744961713Sgirish }
39844961713Sgirish 
39944961713Sgirish /*
40044961713Sgirish  * npi_dev_func_sr_lock_free():
40144961713Sgirish  *	This function is called to free the function shared register
40244961713Sgirish  *	by setting the lock state to free.
40344961713Sgirish  * Parameters:
40444961713Sgirish  *	handle		- NPI handle
40544961713Sgirish  * Return:
40644961713Sgirish  *	NPI_SUCCESS	- If the function id can free the lock.
40744961713Sgirish  *
40844961713Sgirish  *	Error:
40944961713Sgirish  *	NPI_FAILURE
41044961713Sgirish  *		VIR_SR_NOTOWNER
41144961713Sgirish  *		VIR_TAS_NOTREAD
41244961713Sgirish  */
413a3c5bd6dSspeer 
41444961713Sgirish npi_status_t
npi_dev_func_sr_lock_free(npi_handle_t handle)41544961713Sgirish npi_dev_func_sr_lock_free(npi_handle_t handle)
41644961713Sgirish {
41744961713Sgirish 	dev_func_sr_t		sr;
41844961713Sgirish 	int			status = NPI_SUCCESS;
41944961713Sgirish 
42044961713Sgirish 	NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value);
42144961713Sgirish 	if (sr.bits.ldw.tas) {
42244961713Sgirish 		if (sr.bits.ldw.funcid == NPI_GET_LOCK_OWNER(sr.bits.ldw.sr)) {
42344961713Sgirish 			sr.bits.ldw.sr &= NPI_DEV_SR_IMPL_ST_MASK;
42444961713Sgirish 			sr.bits.ldw.sr |= NPI_DEV_SR_LOCK_ST_FREE;
42544961713Sgirish 			sr.bits.ldw.tas = 0;
42644961713Sgirish 			NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value);
42744961713Sgirish 		} else {
42844961713Sgirish 			NPI_DEBUG_MSG((handle.function, NPI_VIR_CTL,
42952ccf843Smisaki 			    " npi_dev_func_sr_lock_free"
43052ccf843Smisaki 			    " not owner <0x%x>",
43152ccf843Smisaki 			    sr.bits.ldw.sr));
43244961713Sgirish 			status = NPI_VIR_SR_NOTOWNER(sr.bits.ldw.funcid);
43344961713Sgirish 		}
43444961713Sgirish 	} else {
43544961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
43652ccf843Smisaki 		    " npi_dev_func_sr_lock_free",
43752ccf843Smisaki 		    " invalid tas state <0x%x>",
43852ccf843Smisaki 		    sr.bits.ldw.tas));
43944961713Sgirish 		status = NPI_VIR_TAS_NOTREAD(sr.bits.ldw.funcid);
44044961713Sgirish 	}
44144961713Sgirish 
44244961713Sgirish 	return (status);
44344961713Sgirish }
44444961713Sgirish 
44544961713Sgirish /*
44644961713Sgirish  * npi_dev_func_sr_funcid_get():
44744961713Sgirish  *	This function is called to get the caller's function ID.
44844961713Sgirish  *	(based on address bits [25:26] on read access.
44944961713Sgirish  *	(After read, the TAS bit is always set to 1. Software needs
45044961713Sgirish  *	to write 0 to clear.) This function will write 0 to clear
45144961713Sgirish  *	the TAS bit if we own it.
45244961713Sgirish  * Parameters:
45344961713Sgirish  *	handle		- NPI handle
45444961713Sgirish  *	funcid_p	- pointer to store the function id.
45544961713Sgirish  * Return:
45644961713Sgirish  *	NPI_SUCCESS	- If get function id is complete successfully.
45744961713Sgirish  *
45844961713Sgirish  *	Error:
45944961713Sgirish  */
460a3c5bd6dSspeer 
46144961713Sgirish npi_status_t
npi_dev_func_sr_funcid_get(npi_handle_t handle,uint8_t * funcid_p)46244961713Sgirish npi_dev_func_sr_funcid_get(npi_handle_t handle, uint8_t *funcid_p)
46344961713Sgirish {
46444961713Sgirish 	dev_func_sr_t		sr;
46544961713Sgirish 
46644961713Sgirish 	NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value);
46744961713Sgirish 	*funcid_p = NXGE_VAL(DEV_FUNC_SR_FUNCID, sr.value);
46844961713Sgirish 	if (!sr.bits.ldw.tas) {
46944961713Sgirish 		/*
47044961713Sgirish 		 * After read, this bit is set to 1 by hardware.
47144961713Sgirish 		 * We own it if tas bit read as 0.
47244961713Sgirish 		 */
47344961713Sgirish 		sr.bits.ldw.tas = 0;
47444961713Sgirish 		NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value);
47544961713Sgirish 	}
47644961713Sgirish 
47744961713Sgirish 	return (NPI_SUCCESS);
47844961713Sgirish }
47944961713Sgirish 
48044961713Sgirish /*
48144961713Sgirish  * npi_dev_func_sr_sr_get():
48244961713Sgirish  *	This function is called to get the shared register value.
48344961713Sgirish  *	(After read, the TAS bit is always set to 1. Software needs
48444961713Sgirish  *	to write 0 to clear if we own it.)
48544961713Sgirish  *
48644961713Sgirish  * Parameters:
48744961713Sgirish  *	handle		- NPI handle
48844961713Sgirish  *	sr_p		- pointer to store the shared value of this register.
48944961713Sgirish  *
49044961713Sgirish  * Return:
49144961713Sgirish  *	NPI_SUCCESS		- If shared value get is complete successfully.
49244961713Sgirish  *
49344961713Sgirish  *	Error:
49444961713Sgirish  */
49544961713Sgirish npi_status_t
npi_dev_func_sr_sr_raw_get(npi_handle_t handle,uint16_t * sr_p)49644961713Sgirish npi_dev_func_sr_sr_raw_get(npi_handle_t handle, uint16_t *sr_p)
49744961713Sgirish {
49844961713Sgirish 	dev_func_sr_t		sr;
49944961713Sgirish 
50044961713Sgirish 	NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value);
50144961713Sgirish 	*sr_p = NXGE_VAL(DEV_FUNC_SR_FUNCID, sr.value);
50244961713Sgirish 	if (!sr.bits.ldw.tas) {
50344961713Sgirish 		/*
50444961713Sgirish 		 * After read, this bit is set to 1 by hardware.
50544961713Sgirish 		 * We own it if tas bit read as 0.
50644961713Sgirish 		 */
50744961713Sgirish 		sr.bits.ldw.tas = 0;
50844961713Sgirish 		NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value);
50944961713Sgirish 	}
51044961713Sgirish 
51144961713Sgirish 	return (NPI_SUCCESS);
51244961713Sgirish }
51344961713Sgirish 
51444961713Sgirish /*
51544961713Sgirish  * npi_dev_func_sr_sr_get():
51644961713Sgirish  *	This function is called to get the shared register value.
51744961713Sgirish  *	(After read, the TAS bit is always set to 1. Software needs
51844961713Sgirish  *	to write 0 to clear if we own it.)
51944961713Sgirish  *
52044961713Sgirish  * Parameters:
52144961713Sgirish  *	handle	- NPI handle
52244961713Sgirish  *	sr_p	- pointer to store the shared value of this register.
52344961713Sgirish  *		. this will get only non-lock, non-function id portion
52444961713Sgirish  *              . of the register
52544961713Sgirish  *
52644961713Sgirish  *
52744961713Sgirish  * Return:
52844961713Sgirish  *	NPI_SUCCESS		- If shared value get is complete successfully.
52944961713Sgirish  *
53044961713Sgirish  *	Error:
53144961713Sgirish  */
53244961713Sgirish 
53344961713Sgirish npi_status_t
npi_dev_func_sr_sr_get(npi_handle_t handle,uint16_t * sr_p)53444961713Sgirish npi_dev_func_sr_sr_get(npi_handle_t handle, uint16_t *sr_p)
53544961713Sgirish {
53644961713Sgirish 	dev_func_sr_t		sr;
53744961713Sgirish 	uint16_t sr_impl = 0;
53844961713Sgirish 
53944961713Sgirish 	NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value);
54044961713Sgirish 	sr_impl = NXGE_VAL(DEV_FUNC_SR_FUNCID, sr.value);
54144961713Sgirish 	*sr_p =  (sr_impl << NPI_DEV_SR_IMPL_ST_SHIFT);
54244961713Sgirish 	if (!sr.bits.ldw.tas) {
54344961713Sgirish 		/*
54444961713Sgirish 		 * After read, this bit is set to 1 by hardware.
54544961713Sgirish 		 * We own it if tas bit read as 0.
54644961713Sgirish 		 */
54744961713Sgirish 		sr.bits.ldw.tas = 0;
54844961713Sgirish 		NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value);
54944961713Sgirish 	}
55044961713Sgirish 
55144961713Sgirish 	return (NPI_SUCCESS);
55244961713Sgirish }
55344961713Sgirish 
55444961713Sgirish /*
55544961713Sgirish  * npi_dev_func_sr_sr_get_set_clear():
55644961713Sgirish  *	This function is called to set the shared register value.
55744961713Sgirish  *	(Shared register must be read first. If tas bit is 0, then
55844961713Sgirish  *	it implies that the software can proceed to set). After
55944961713Sgirish  *	setting, tas bit will be cleared.
56044961713Sgirish  * Parameters:
56144961713Sgirish  *	handle		- NPI handle
56244961713Sgirish  *	impl_sr		- shared value to set (only the 8 bit
56344961713Sgirish  *			  implementation specific state info).
56444961713Sgirish  *
56544961713Sgirish  * Return:
56644961713Sgirish  *	NPI_SUCCESS		- If shared value is set successfully.
56744961713Sgirish  *
56844961713Sgirish  *	Error:
56944961713Sgirish  *	NPI_FAILURE
57044961713Sgirish  *		VIR_TAS_BUSY
57144961713Sgirish  */
572a3c5bd6dSspeer 
57344961713Sgirish npi_status_t
npi_dev_func_sr_sr_get_set_clear(npi_handle_t handle,uint16_t impl_sr)57444961713Sgirish npi_dev_func_sr_sr_get_set_clear(npi_handle_t handle, uint16_t impl_sr)
57544961713Sgirish {
57644961713Sgirish 	dev_func_sr_t		sr;
57744961713Sgirish 	int			status;
57844961713Sgirish 
57944961713Sgirish 	status = npi_dev_func_sr_lock_enter(handle);
58044961713Sgirish 	if (status != NPI_SUCCESS) {
58144961713Sgirish 		NPI_DEBUG_MSG((handle.function, NPI_VIR_CTL,
58252ccf843Smisaki 		    " npi_dev_func_sr_src_get_set_clear"
58352ccf843Smisaki 		    " unable to acquire lock:"
58452ccf843Smisaki 		    " status <0x%x>", status));
58544961713Sgirish 		return (status);
58644961713Sgirish 	}
58744961713Sgirish 
58844961713Sgirish 	NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value);
58944961713Sgirish 	sr.bits.ldw.sr |= (impl_sr << NPI_DEV_SR_IMPL_ST_SHIFT);
59044961713Sgirish 	NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value);
59144961713Sgirish 
59244961713Sgirish 	return (npi_dev_func_sr_lock_free(handle));
59344961713Sgirish }
59444961713Sgirish 
59544961713Sgirish /*
59644961713Sgirish  * npi_dev_func_sr_sr_set_only():
59744961713Sgirish  *	This function is called to only set the shared register value.
59844961713Sgirish  * Parameters:
59944961713Sgirish  *	handle		- NPI handle
60044961713Sgirish  *	impl_sr		- shared value to set.
60144961713Sgirish  *
60244961713Sgirish  * Return:
60344961713Sgirish  *	NPI_SUCCESS		- If shared value is set successfully.
60444961713Sgirish  *
60544961713Sgirish  *	Error:
60644961713Sgirish  *	NPI_FAILURE
60744961713Sgirish  *		VIR_TAS_BUSY
60844961713Sgirish  */
609a3c5bd6dSspeer 
61044961713Sgirish npi_status_t
npi_dev_func_sr_sr_set_only(npi_handle_t handle,uint16_t impl_sr)61144961713Sgirish npi_dev_func_sr_sr_set_only(npi_handle_t handle, uint16_t impl_sr)
61244961713Sgirish {
61344961713Sgirish 	int		status = NPI_SUCCESS;
61444961713Sgirish 	dev_func_sr_t	sr;
61544961713Sgirish 
61644961713Sgirish 	NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value);
61744961713Sgirish 	/* must be the owner */
61844961713Sgirish 	if (sr.bits.ldw.funcid == NPI_GET_LOCK_OWNER(sr.bits.ldw.sr)) {
61944961713Sgirish 		sr.bits.ldw.sr |= (impl_sr << NPI_DEV_SR_IMPL_ST_SHIFT);
62044961713Sgirish 		NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value);
62144961713Sgirish 	} else {
62244961713Sgirish 		NPI_DEBUG_MSG((handle.function, NPI_VIR_CTL,
62352ccf843Smisaki 		    " npi_dev_func_sr_sr_set_only"
62452ccf843Smisaki 		    " not owner <0x%x>",
62552ccf843Smisaki 		    sr.bits.ldw.sr));
62644961713Sgirish 		status = NPI_VIR_SR_NOTOWNER(sr.bits.ldw.funcid);
62744961713Sgirish 	}
62844961713Sgirish 
62944961713Sgirish 	return (status);
63044961713Sgirish }
63144961713Sgirish 
63244961713Sgirish /*
63344961713Sgirish  * npi_dev_func_sr_busy():
63444961713Sgirish  *	This function is called to see if we can own the device.
63544961713Sgirish  *	It will not reset the tas bit.
63644961713Sgirish  * Parameters:
63744961713Sgirish  *	handle		- NPI handle
63844961713Sgirish  *	busy_p		- pointer to store busy flag.
63944961713Sgirish  *				(B_TRUE: device is in use, B_FALSE: free).
64044961713Sgirish  * Return:
64144961713Sgirish  *	NPI_SUCCESS		- If tas bit is read successfully.
64244961713Sgirish  *	Error:
64344961713Sgirish  */
644a3c5bd6dSspeer 
64544961713Sgirish npi_status_t
npi_dev_func_sr_busy(npi_handle_t handle,boolean_t * busy_p)64644961713Sgirish npi_dev_func_sr_busy(npi_handle_t handle, boolean_t *busy_p)
64744961713Sgirish {
64844961713Sgirish 	dev_func_sr_t	sr;
64944961713Sgirish 
65044961713Sgirish 	NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value);
65144961713Sgirish 	if (!sr.bits.ldw.tas) {
65244961713Sgirish 		sr.bits.ldw.tas = 0;
65344961713Sgirish 		NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value);
65444961713Sgirish 		*busy_p = B_FALSE;
65544961713Sgirish 	} else {
65644961713Sgirish 		/* Other function already owns it */
65744961713Sgirish 		*busy_p = B_TRUE;
65844961713Sgirish 	}
65944961713Sgirish 
66044961713Sgirish 	return (NPI_SUCCESS);
66144961713Sgirish }
66244961713Sgirish 
66344961713Sgirish /*
66444961713Sgirish  * npi_dev_func_sr_tas_get():
66544961713Sgirish  *	This function is called to get the tas bit
66644961713Sgirish  *	(after read, this bit is always set to 1, software write 0
66744961713Sgirish  *	 to clear it).
66844961713Sgirish  *
66944961713Sgirish  * Parameters:
67044961713Sgirish  *	handle		- NPI handle
67144961713Sgirish  *	tas_p		- pointer to store the tas value
67244961713Sgirish  *
67344961713Sgirish  * Return:
67444961713Sgirish  *	NPI_SUCCESS		- If tas value get is complete successfully.
67544961713Sgirish  *	Error:
67644961713Sgirish  */
677a3c5bd6dSspeer 
67844961713Sgirish npi_status_t
npi_dev_func_sr_tas_get(npi_handle_t handle,uint8_t * tas_p)67944961713Sgirish npi_dev_func_sr_tas_get(npi_handle_t handle, uint8_t *tas_p)
68044961713Sgirish {
68144961713Sgirish 	dev_func_sr_t		sr;
68244961713Sgirish 
68344961713Sgirish 	NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value);
68444961713Sgirish 	*tas_p = sr.bits.ldw.tas;
68544961713Sgirish 	if (!sr.bits.ldw.tas) {
68644961713Sgirish 		sr.bits.ldw.tas = 0;
68744961713Sgirish 		NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value);
68844961713Sgirish 
68944961713Sgirish 	}
69044961713Sgirish 
69144961713Sgirish 	return (NPI_SUCCESS);
69244961713Sgirish }
69344961713Sgirish 
69444961713Sgirish /*
69544961713Sgirish  * npi_fzc_mpc_set():
69644961713Sgirish  *	This function is called to enable the write access
69744961713Sgirish  *	to FZC region to function zero.
69844961713Sgirish  * Parameters:
69944961713Sgirish  *	handle		- NPI handle
70044961713Sgirish  * Return:
70144961713Sgirish  *	NPI_SUCCESS	-
70244961713Sgirish  *	Error:
70344961713Sgirish  */
704a3c5bd6dSspeer 
70544961713Sgirish npi_status_t
npi_fzc_mpc_set(npi_handle_t handle,boolean_t mpc)70644961713Sgirish npi_fzc_mpc_set(npi_handle_t handle, boolean_t mpc)
70744961713Sgirish {
70844961713Sgirish 	multi_part_ctl_t	mp;
70944961713Sgirish 
71044961713Sgirish 	mp.value = 0;
71144961713Sgirish 	if (mpc) {
71244961713Sgirish 		mp.bits.ldw.mpc = 1;
71344961713Sgirish 	}
71444961713Sgirish 	NXGE_REG_WR64(handle, MULTI_PART_CTL_REG, mp.value);
71544961713Sgirish 
71644961713Sgirish 	return (NPI_SUCCESS);
71744961713Sgirish }
71844961713Sgirish 
71944961713Sgirish /*
72044961713Sgirish  * npi_fzc_mpc_get():
72144961713Sgirish  *	This function is called to get the access mode.
72244961713Sgirish  * Parameters:
72344961713Sgirish  *	handle		- NPI handle
72444961713Sgirish  * Return:
72544961713Sgirish  *	NPI_SUCCESS	-
72644961713Sgirish  *
72744961713Sgirish  */
728a3c5bd6dSspeer 
72944961713Sgirish npi_status_t
npi_fzc_mpc_get(npi_handle_t handle,boolean_t * mpc_p)73044961713Sgirish npi_fzc_mpc_get(npi_handle_t handle, boolean_t *mpc_p)
73144961713Sgirish {
73244961713Sgirish 	multi_part_ctl_t	mpc;
73344961713Sgirish 
73444961713Sgirish 	mpc.value = 0;
73544961713Sgirish 	NXGE_REG_RD64(handle, MULTI_PART_CTL_REG, &mpc.value);
73644961713Sgirish 	*mpc_p = mpc.bits.ldw.mpc;
73744961713Sgirish 
73844961713Sgirish 	return (NPI_SUCCESS);
73944961713Sgirish }
74044961713Sgirish 
74144961713Sgirish /*
74244961713Sgirish  * npi_fzc_dma_bind_set():
74344961713Sgirish  *	This function is called to set DMA binding register.
74444961713Sgirish  * Parameters:
74544961713Sgirish  *	handle		- NPI handle
74644961713Sgirish  *	dma_bind	- NPI defined data structure that
74744961713Sgirish  *			  contains the tx/rx channel binding info.
74844961713Sgirish  *			  to set.
74944961713Sgirish  * Return:
75044961713Sgirish  *	NPI_SUCCESS	-
75144961713Sgirish  *	Error:
75244961713Sgirish  *	NPI_FAILURE
75344961713Sgirish  *
75444961713Sgirish  */
755a3c5bd6dSspeer 
75644961713Sgirish npi_status_t
npi_fzc_dma_bind_set(npi_handle_t handle,fzc_dma_bind_t dma_bind)75744961713Sgirish npi_fzc_dma_bind_set(npi_handle_t handle, fzc_dma_bind_t dma_bind)
75844961713Sgirish {
75944961713Sgirish 	dma_bind_t	bind;
76044961713Sgirish 	int		status;
76144961713Sgirish 	uint8_t		fn, region, id, tn, rn;
76244961713Sgirish 
76344961713Sgirish 	fn = dma_bind.function_id;
76444961713Sgirish 	region = dma_bind.sub_vir_region;
76544961713Sgirish 	id = dma_bind.vir_index;
76644961713Sgirish 	tn = dma_bind.tx_channel;
76744961713Sgirish 	rn = dma_bind.rx_channel;
76844961713Sgirish 
76944961713Sgirish 	DMA_BIND_VADDR_VALIDATE(fn, region, id, status);
77044961713Sgirish 	if (status) {
77144961713Sgirish 		return (status);
77244961713Sgirish 	}
77344961713Sgirish 
77444961713Sgirish 	if (dma_bind.tx_bind) {
77544961713Sgirish 		DMA_BIND_TX_VALIDATE(tn, status);
77644961713Sgirish 		if (status) {
77744961713Sgirish 			return (status);
77844961713Sgirish 		}
77944961713Sgirish 	}
78044961713Sgirish 
78144961713Sgirish 	if (dma_bind.rx_bind) {
78244961713Sgirish 		DMA_BIND_RX_VALIDATE(rn, status);
78344961713Sgirish 		if (status) {
78444961713Sgirish 			return (status);
78544961713Sgirish 		}
78644961713Sgirish 	}
78744961713Sgirish 
78844961713Sgirish 	bind.value = 0;
78944961713Sgirish 	if (dma_bind.tx_bind) {
79044961713Sgirish 		bind.bits.ldw.tx_bind = 1;
79144961713Sgirish 		bind.bits.ldw.tx = tn;
79244961713Sgirish 	}
79344961713Sgirish 	if (dma_bind.rx_bind) {
79444961713Sgirish 		bind.bits.ldw.rx_bind = 1;
79544961713Sgirish 		bind.bits.ldw.rx = rn;
79644961713Sgirish 	}
79744961713Sgirish 
79844961713Sgirish 	NXGE_REG_WR64(handle, DMA_BIND_REG +
799678453a8Sspeer 	    DMA_BIND_REG_OFFSET(fn, region, id), bind.value);
800678453a8Sspeer 
801678453a8Sspeer 	return (status);
802678453a8Sspeer }
803678453a8Sspeer 
804678453a8Sspeer npi_status_t
npi_fzc_dma_bind_get(npi_handle_t handle,fzc_dma_bind_t dma_bind,uint64_t * pValue)805678453a8Sspeer npi_fzc_dma_bind_get(
806678453a8Sspeer 	npi_handle_t handle,
807678453a8Sspeer 	fzc_dma_bind_t dma_bind,
808678453a8Sspeer 	uint64_t *pValue)
809678453a8Sspeer {
810678453a8Sspeer 	uint8_t		function, region, slot;
811678453a8Sspeer 	int		offset;
812678453a8Sspeer 	int		status;
813678453a8Sspeer 
814678453a8Sspeer 	function = dma_bind.function_id;
815678453a8Sspeer 	region = dma_bind.sub_vir_region;
816678453a8Sspeer 	slot = dma_bind.vir_index;
817678453a8Sspeer 
818678453a8Sspeer 	DMA_BIND_VADDR_VALIDATE(function, region, slot, status);
819678453a8Sspeer 	if (status) {
820678453a8Sspeer 		return (status);
821678453a8Sspeer 	}
822678453a8Sspeer 
823678453a8Sspeer 	offset = DMA_BIND_REG_OFFSET(function, region, slot);
824678453a8Sspeer 	NXGE_REG_RD64(handle, DMA_BIND_REG + offset, pValue);
82544961713Sgirish 
82644961713Sgirish 	return (status);
82744961713Sgirish }
82844961713Sgirish 
82944961713Sgirish /*
83044961713Sgirish  * npi_fzc_ldg_num_set():
83144961713Sgirish  *	This function is called to set up a logical group number that
83244961713Sgirish  *	a logical device belongs to.
83344961713Sgirish  * Parameters:
83444961713Sgirish  *	handle		- NPI handle
83544961713Sgirish  *	ld		- logical device number (0 - 68)
83644961713Sgirish  *	ldg		- logical device group number (0 - 63)
83744961713Sgirish  * Return:
83844961713Sgirish  *	NPI_SUCCESS	-
83944961713Sgirish  *	Error:
84044961713Sgirish  *	NPI_FAILURE
84144961713Sgirish  *
84244961713Sgirish  */
843a3c5bd6dSspeer 
84444961713Sgirish npi_status_t
npi_fzc_ldg_num_set(npi_handle_t handle,uint8_t ld,uint8_t ldg)84544961713Sgirish npi_fzc_ldg_num_set(npi_handle_t handle, uint8_t ld, uint8_t ldg)
84644961713Sgirish {
84744961713Sgirish 	ldg_num_t	gnum;
84844961713Sgirish 
849a3c5bd6dSspeer 	ASSERT(LD_VALID(ld));
85044961713Sgirish 	if (!LD_VALID(ld)) {
85144961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
85252ccf843Smisaki 		    " npi_fzc_ldg_num_set"
85352ccf843Smisaki 		    "ld <0x%x>", ld));
85444961713Sgirish 		return (NPI_FAILURE | NPI_VIR_LD_INVALID(ld));
85544961713Sgirish 	}
856a3c5bd6dSspeer 
857a3c5bd6dSspeer 	ASSERT(LDG_VALID(ldg));
85844961713Sgirish 	if (!LDG_VALID(ldg)) {
85944961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
86052ccf843Smisaki 		    " npi_fzc_ldg_num_set"
86152ccf843Smisaki 		    " ldg <0x%x>", ldg));
86244961713Sgirish 		return (NPI_FAILURE | NPI_VIR_LDG_INVALID(ld));
86344961713Sgirish 	}
86444961713Sgirish 
86544961713Sgirish 	gnum.value = 0;
86644961713Sgirish 	gnum.bits.ldw.num = ldg;
86744961713Sgirish 
86844961713Sgirish 	NXGE_REG_WR64(handle, LDG_NUM_REG + LD_NUM_OFFSET(ld),
86952ccf843Smisaki 	    gnum.value);
87044961713Sgirish 
87144961713Sgirish 	return (NPI_SUCCESS);
87244961713Sgirish }
87344961713Sgirish 
87444961713Sgirish /*
87544961713Sgirish  * npi_fzc_ldg_num_get():
87644961713Sgirish  *	This function is called to get the logical device group that
87744961713Sgirish  *	a logical device belongs to.
87844961713Sgirish  * Parameters:
87944961713Sgirish  *	handle		- NPI handle
88044961713Sgirish  *	ld		- logical device number (0 - 68)
88144961713Sgirish  *	*ldg_p		- pointer to store its group number.
88244961713Sgirish  * Return:
88344961713Sgirish  *	NPI_SUCCESS	-
88444961713Sgirish  *	Error:
88544961713Sgirish  *	NPI_FAILURE
88644961713Sgirish  */
887a3c5bd6dSspeer 
88844961713Sgirish npi_status_t
npi_fzc_ldg_num_get(npi_handle_t handle,uint8_t ld,uint8_t * ldg_p)88944961713Sgirish npi_fzc_ldg_num_get(npi_handle_t handle, uint8_t ld, uint8_t *ldg_p)
89044961713Sgirish {
89144961713Sgirish 	uint64_t val;
89244961713Sgirish 
893a3c5bd6dSspeer 	ASSERT(LD_VALID(ld));
89444961713Sgirish 	if (!LD_VALID(ld)) {
89544961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
89652ccf843Smisaki 		    " npi_fzc_ldg_num_get"
89752ccf843Smisaki 		    " Invalid Input:",
89852ccf843Smisaki 		    " ld <0x%x>", ld));
89944961713Sgirish 		return (NPI_FAILURE | NPI_VIR_LD_INVALID(ld));
90044961713Sgirish 	}
90144961713Sgirish 
90244961713Sgirish 	NXGE_REG_RD64(handle, LDG_NUM_REG + LD_NUM_OFFSET(ld), &val);
90344961713Sgirish 
90444961713Sgirish 	*ldg_p = (uint8_t)(val & LDG_NUM_NUM_MASK);
90544961713Sgirish 
90644961713Sgirish 	return (NPI_SUCCESS);
90744961713Sgirish }
90844961713Sgirish 
90944961713Sgirish /*
91044961713Sgirish  * npi_ldsv_ldfs_get():
91144961713Sgirish  *	This function is called to get device state vectors.
91244961713Sgirish  * Parameters:
91344961713Sgirish  *	handle		- NPI handle
91444961713Sgirish  *	ldg		- logical device group (0 - 63)
91544961713Sgirish  *	*ldf_p		- pointer to store ldf0 and ldf1 flag bits.
91644961713Sgirish  * Return:
91744961713Sgirish  *	NPI_SUCCESS	-
91844961713Sgirish  *	Error:
91944961713Sgirish  *	NPI_FAILURE
92044961713Sgirish  */
921a3c5bd6dSspeer 
92244961713Sgirish npi_status_t
npi_ldsv_ldfs_get(npi_handle_t handle,uint8_t ldg,uint64_t * vector0_p,uint64_t * vector1_p,uint64_t * vector2_p)92344961713Sgirish npi_ldsv_ldfs_get(npi_handle_t handle, uint8_t ldg, uint64_t *vector0_p,
924a3c5bd6dSspeer 	uint64_t *vector1_p, uint64_t *vector2_p)
92544961713Sgirish {
92644961713Sgirish 	int	status;
92744961713Sgirish 
92844961713Sgirish 	if ((status = npi_ldsv_get(handle, ldg, VECTOR0, vector0_p))) {
92944961713Sgirish 		return (status);
93044961713Sgirish 	}
93144961713Sgirish 	if ((status = npi_ldsv_get(handle, ldg, VECTOR1, vector1_p))) {
93244961713Sgirish 		return (status);
93344961713Sgirish 	}
93444961713Sgirish 	if ((status = npi_ldsv_get(handle, ldg, VECTOR2, vector2_p))) {
93544961713Sgirish 		return (status);
93644961713Sgirish 	}
93744961713Sgirish 
93844961713Sgirish 	return (NPI_SUCCESS);
93944961713Sgirish }
94044961713Sgirish 
94144961713Sgirish /*
94244961713Sgirish  * npi_ldsv_get():
94344961713Sgirish  *	This function is called to get device state vectors.
94444961713Sgirish  * Parameters:
94544961713Sgirish  *	handle		- NPI handle
94644961713Sgirish  *	ldg		- logical device group (0 - 63)
94744961713Sgirish  *	ldf_type	- either LDF0 (0) or LDF1 (1)
94844961713Sgirish  *	vector		- vector type (0, 1 or 2)
94944961713Sgirish  *	*ldf_p		- pointer to store its flag bits.
95044961713Sgirish  * Return:
95144961713Sgirish  *	NPI_SUCCESS	-
95244961713Sgirish  *	Error:
95344961713Sgirish  *	NPI_FAILURE
95444961713Sgirish  */
955a3c5bd6dSspeer 
95644961713Sgirish npi_status_t
npi_ldsv_get(npi_handle_t handle,uint8_t ldg,ldsv_type_t vector,uint64_t * ldf_p)95744961713Sgirish npi_ldsv_get(npi_handle_t handle, uint8_t ldg, ldsv_type_t vector,
958a3c5bd6dSspeer 	uint64_t *ldf_p)
95944961713Sgirish {
96044961713Sgirish 	uint64_t		offset;
96144961713Sgirish 
962a3c5bd6dSspeer 	ASSERT(LDG_VALID(ldg));
96344961713Sgirish 	if (!LDG_VALID(ldg)) {
96444961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
96552ccf843Smisaki 		    " npi_ldsv_get"
96652ccf843Smisaki 		    " Invalid Input "
96752ccf843Smisaki 		    " ldg <0x%x>", ldg));
96844961713Sgirish 		return (NPI_FAILURE | NPI_VIR_LDG_INVALID(ldg));
96944961713Sgirish 	}
97044961713Sgirish 
97144961713Sgirish 	switch (vector) {
97244961713Sgirish 	case VECTOR0:
97344961713Sgirish 		offset = LDSV0_REG + LDSV_OFFSET(ldg);
97444961713Sgirish 		break;
97544961713Sgirish 
97644961713Sgirish 	case VECTOR1:
97744961713Sgirish 		offset = LDSV1_REG + LDSV_OFFSET(ldg);
97844961713Sgirish 		break;
97944961713Sgirish 
98044961713Sgirish 	case VECTOR2:
98144961713Sgirish 		offset = LDSV2_REG + LDSV_OFFSET(ldg);
98244961713Sgirish 		break;
98344961713Sgirish 
98444961713Sgirish 	default:
98544961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
98652ccf843Smisaki 		    " npi_ldsv_get"
98752ccf843Smisaki 		    " Invalid Input: "
98852ccf843Smisaki 		    " ldsv type <0x%x>", vector));
98944961713Sgirish 		return (NPI_FAILURE | NPI_VIR_LDSV_INVALID(vector));
99044961713Sgirish 	}
99144961713Sgirish 
99244961713Sgirish 	NXGE_REG_RD64(handle, offset, ldf_p);
99344961713Sgirish 
99444961713Sgirish 	return (NPI_SUCCESS);
99544961713Sgirish }
99644961713Sgirish 
99744961713Sgirish /*
99844961713Sgirish  * npi_ldsv_ld_get():
99944961713Sgirish  *	This function is called to get the flag bit value of a device.
100044961713Sgirish  * Parameters:
100144961713Sgirish  *	handle		- NPI handle
100244961713Sgirish  *	ldg		- logical device group (0 - 63)
100344961713Sgirish  *	ld		- logical device (0 - 68)
100444961713Sgirish  *	ldf_type	- either LDF0 (0) or LDF1 (1)
100544961713Sgirish  *	vector		- vector type (0, 1 or 2)
100644961713Sgirish  *	*ldf_p		- pointer to store its flag bits.
100744961713Sgirish  * Return:
100844961713Sgirish  *	NPI_SUCCESS	-
100944961713Sgirish  *	Error:
101044961713Sgirish  *	NPI_FAILURE
101144961713Sgirish  */
1012a3c5bd6dSspeer 
101344961713Sgirish npi_status_t
npi_ldsv_ld_get(npi_handle_t handle,uint8_t ldg,uint8_t ld,ldsv_type_t vector,ldf_type_t ldf_type,boolean_t * flag_p)101444961713Sgirish npi_ldsv_ld_get(npi_handle_t handle, uint8_t ldg, uint8_t ld,
1015a3c5bd6dSspeer 	ldsv_type_t vector, ldf_type_t ldf_type, boolean_t *flag_p)
101644961713Sgirish {
101744961713Sgirish 	uint64_t		sv;
101844961713Sgirish 	uint64_t		offset;
101944961713Sgirish 
1020a3c5bd6dSspeer 	ASSERT(LDG_VALID(ldg));
102144961713Sgirish 	if (!LDG_VALID(ldg)) {
102244961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
102352ccf843Smisaki 		    " npi_ldsv_ld_get"
102452ccf843Smisaki 		    " Invalid Input: "
102552ccf843Smisaki 		    " ldg <0x%x>", ldg));
102644961713Sgirish 		return (NPI_FAILURE | NPI_VIR_LDG_INVALID(ldg));
102744961713Sgirish 	}
1028a3c5bd6dSspeer 	ASSERT((LD_VALID(ld)) &&	\
102952ccf843Smisaki 	    ((vector != VECTOR2) || (ld >= NXGE_MAC_LD_START)));
103044961713Sgirish 	if (!LD_VALID(ld)) {
103144961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
103252ccf843Smisaki 		    " npi_ldsv_ld_get Invalid Input: "
103352ccf843Smisaki 		    " ld <9x%x>", ld));
103444961713Sgirish 		return (NPI_FAILURE | NPI_VIR_LD_INVALID(ld));
103544961713Sgirish 	} else if (vector == VECTOR2 && ld < NXGE_MAC_LD_START) {
103644961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
103752ccf843Smisaki 		    " npi_ldsv_ld_get Invalid Input:"
103852ccf843Smisaki 		    " ld-vector2 <0x%x>", ld));
103944961713Sgirish 		return (NPI_FAILURE | NPI_VIR_LD_INVALID(ld));
104044961713Sgirish 	}
104144961713Sgirish 
104244961713Sgirish 	switch (vector) {
104344961713Sgirish 	case VECTOR0:
104444961713Sgirish 		offset = LDSV0_REG + LDSV_OFFSET(ldg);
104544961713Sgirish 		break;
104644961713Sgirish 
104744961713Sgirish 	case VECTOR1:
104844961713Sgirish 		offset = LDSV1_REG + LDSV_OFFSET(ldg);
104944961713Sgirish 		break;
105044961713Sgirish 
105144961713Sgirish 	case VECTOR2:
105244961713Sgirish 		offset = LDSV2_REG + LDSV_OFFSET(ldg);
1053*73ff8cc6SToomas Soome 		break;
105444961713Sgirish 
105544961713Sgirish 	default:
105644961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, "npi_ldsv_get"
105752ccf843Smisaki 		    "ldsv", vector));
105844961713Sgirish 		return (NPI_FAILURE | NPI_VIR_LDSV_INVALID(vector));
105944961713Sgirish 	}
106044961713Sgirish 
106144961713Sgirish 	NXGE_REG_RD64(handle, offset, &sv);
106244961713Sgirish 	if (vector != VECTOR2) {
106344961713Sgirish 		*flag_p = ((sv >> ld) & LDSV_MASK_ALL);
106444961713Sgirish 	} else {
106544961713Sgirish 		if (ldf_type) {
106644961713Sgirish 			*flag_p = (((sv >> LDSV2_LDF1_SHIFT) >>
106752ccf843Smisaki 			    (ld - NXGE_MAC_LD_START)) & LDSV_MASK_ALL);
106844961713Sgirish 		} else {
106944961713Sgirish 			*flag_p = (((sv >> LDSV2_LDF0_SHIFT) >>
107052ccf843Smisaki 			    (ld - NXGE_MAC_LD_START)) & LDSV_MASK_ALL);
107144961713Sgirish 		}
107244961713Sgirish 	}
107344961713Sgirish 
107444961713Sgirish 	return (NPI_SUCCESS);
107544961713Sgirish }
107644961713Sgirish 
107744961713Sgirish /*
107844961713Sgirish  * npi_ldsv_ld_ldf0_get():
107944961713Sgirish  *	This function is called to get the ldf0 bit value of a device.
108044961713Sgirish  * Parameters:
108144961713Sgirish  *	handle		- NPI handle
108244961713Sgirish  *	ldg		- logical device group (0 - 63)
108344961713Sgirish  *	ld		- logical device (0 - 68)
108444961713Sgirish  *	*ldf_p		- pointer to store its flag bits.
108544961713Sgirish  * Return:
108644961713Sgirish  *	NPI_SUCCESS	-
108744961713Sgirish  *	Error:
108844961713Sgirish  *	NPI_FAILURE
108944961713Sgirish  */
1090a3c5bd6dSspeer 
109144961713Sgirish npi_status_t
npi_ldsv_ld_ldf0_get(npi_handle_t handle,uint8_t ldg,uint8_t ld,boolean_t * flag_p)109244961713Sgirish npi_ldsv_ld_ldf0_get(npi_handle_t handle, uint8_t ldg, uint8_t ld,
1093a3c5bd6dSspeer 	boolean_t *flag_p)
109444961713Sgirish {
109544961713Sgirish 	ldsv_type_t vector;
109644961713Sgirish 
109744961713Sgirish 	if (ld >= NXGE_MAC_LD_START) {
109844961713Sgirish 		vector = VECTOR2;
109944961713Sgirish 	}
110044961713Sgirish 
110144961713Sgirish 	return (npi_ldsv_ld_get(handle, ldg, ld, vector, LDF0, flag_p));
110244961713Sgirish }
110344961713Sgirish 
110444961713Sgirish /*
110544961713Sgirish  * npi_ldsv_ld_ldf1_get():
110644961713Sgirish  *	This function is called to get the ldf1 bit value of a device.
110744961713Sgirish  * Parameters:
110844961713Sgirish  *	handle		- NPI handle
110944961713Sgirish  *	ldg		- logical device group (0 - 63)
111044961713Sgirish  *	ld		- logical device (0 - 68)
111144961713Sgirish  *	*ldf_p		- pointer to store its flag bits.
111244961713Sgirish  * Return:
111344961713Sgirish  *	NPI_SUCCESS	-
111444961713Sgirish  *	Error:
111544961713Sgirish  *	NPI_FAILURE
111644961713Sgirish  */
1117a3c5bd6dSspeer 
111844961713Sgirish npi_status_t
npi_ldsv_ld_ldf1_get(npi_handle_t handle,uint8_t ldg,uint8_t ld,boolean_t * flag_p)111944961713Sgirish npi_ldsv_ld_ldf1_get(npi_handle_t handle, uint8_t ldg, uint8_t ld,
112044961713Sgirish 		boolean_t *flag_p)
112144961713Sgirish {
112244961713Sgirish 	ldsv_type_t vector;
112344961713Sgirish 
112444961713Sgirish 	if (ld >= NXGE_MAC_LD_START) {
112544961713Sgirish 		vector = VECTOR2;
112644961713Sgirish 	}
112744961713Sgirish 
112844961713Sgirish 	return (npi_ldsv_ld_get(handle, ldg, ld, vector, LDF1, flag_p));
112944961713Sgirish }
113044961713Sgirish 
113144961713Sgirish /*
113244961713Sgirish  * npi_intr_mask_set():
113344961713Sgirish  *	This function is called to select the mask bits for both ldf0 and ldf1.
113444961713Sgirish  * Parameters:
113544961713Sgirish  *	handle		- NPI handle
113644961713Sgirish  *	ld		- logical device (0 - 68)
113744961713Sgirish  *	ldf_mask	- mask value to set (both ldf0 and ldf1).
113844961713Sgirish  * Return:
113944961713Sgirish  *	NPI_SUCCESS	-
114044961713Sgirish  *	Error:
114144961713Sgirish  *	NPI_FAILURE
114244961713Sgirish  */
1143a3c5bd6dSspeer 
114444961713Sgirish npi_status_t
npi_intr_mask_set(npi_handle_t handle,uint8_t ld,uint8_t ldf_mask)114544961713Sgirish npi_intr_mask_set(npi_handle_t handle, uint8_t ld, uint8_t ldf_mask)
114644961713Sgirish {
114744961713Sgirish 	uint64_t		offset;
114844961713Sgirish 
1149a3c5bd6dSspeer 	ASSERT(LD_VALID(ld));
115044961713Sgirish 	if (!LD_VALID(ld)) {
115144961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
115252ccf843Smisaki 		    " npi_intr_mask_set ld", ld));
115344961713Sgirish 		return (NPI_FAILURE | NPI_VIR_LD_INVALID(ld));
115444961713Sgirish 	}
115544961713Sgirish 
115644961713Sgirish 	ldf_mask &= LD_IM0_MASK;
115744961713Sgirish 	offset = LDSV_OFFSET_MASK(ld);
115844961713Sgirish 
115944961713Sgirish 	NPI_DEBUG_MSG((handle.function, NPI_VIR_CTL,
116052ccf843Smisaki 	    "npi_intr_mask_set: ld %d "
116152ccf843Smisaki 	    " offset 0x%0llx "
116252ccf843Smisaki 	    " mask 0x%x",
116352ccf843Smisaki 	    ld, offset, ldf_mask));
116444961713Sgirish 
116544961713Sgirish 	NXGE_REG_WR64(handle, offset, (uint64_t)ldf_mask);
116644961713Sgirish 
116744961713Sgirish 	return (NPI_SUCCESS);
116844961713Sgirish }
116944961713Sgirish 
117044961713Sgirish /*
117144961713Sgirish  * npi_intr_mask_get():
117244961713Sgirish  *	This function is called to get the mask bits.
117344961713Sgirish  * Parameters:
117444961713Sgirish  *	handle		- NPI handle
117544961713Sgirish  *	ld		- logical device (0 - 68)
117644961713Sgirish  *	ldf_mask	- pointer to store mask bits info.
117744961713Sgirish  * Return:
117844961713Sgirish  *	NPI_SUCCESS	-
117944961713Sgirish  *	Error:
118044961713Sgirish  *	NPI_FAILURE
118144961713Sgirish  */
118244961713Sgirish npi_status_t
npi_intr_mask_get(npi_handle_t handle,uint8_t ld,uint8_t * ldf_mask_p)118344961713Sgirish npi_intr_mask_get(npi_handle_t handle, uint8_t ld, uint8_t *ldf_mask_p)
118444961713Sgirish {
118544961713Sgirish 	uint64_t		offset;
118644961713Sgirish 	uint64_t		val;
118744961713Sgirish 
1188a3c5bd6dSspeer 	ASSERT(LD_VALID(ld));
118944961713Sgirish 	if (!LD_VALID(ld)) {
119044961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
119152ccf843Smisaki 		    " npi_intr_mask_get ld", ld));
119244961713Sgirish 		return (NPI_FAILURE | NPI_VIR_LD_INVALID(ld));
119344961713Sgirish 	}
119444961713Sgirish 
119544961713Sgirish 	offset = LDSV_OFFSET_MASK(ld);
119644961713Sgirish 
119744961713Sgirish 	NXGE_REG_RD64(handle, offset, &val);
119844961713Sgirish 
119944961713Sgirish 	*ldf_mask_p = (uint8_t)(val & LD_IM_MASK);
120044961713Sgirish 
120144961713Sgirish 	return (NPI_SUCCESS);
120244961713Sgirish }
120344961713Sgirish 
120444961713Sgirish /*
120544961713Sgirish  * npi_intr_ldg_mgmt_set():
120644961713Sgirish  *	This function is called to set interrupt timer and arm bit.
120744961713Sgirish  * Parameters:
120844961713Sgirish  *	handle		- NPI handle
120944961713Sgirish  *	ldg		- logical device group (0 - 63)
121044961713Sgirish  *	arm		- B_TRUE (arm) B_FALSE (disable)
121144961713Sgirish  * Return:
121244961713Sgirish  *	NPI_SUCCESS	-
121344961713Sgirish  *	Error:
121444961713Sgirish  *	NPI_FAILURE
121544961713Sgirish  */
1216a3c5bd6dSspeer 
121744961713Sgirish npi_status_t
npi_intr_ldg_mgmt_set(npi_handle_t handle,uint8_t ldg,boolean_t arm,uint8_t timer)121844961713Sgirish npi_intr_ldg_mgmt_set(npi_handle_t handle, uint8_t ldg, boolean_t arm,
121944961713Sgirish 			uint8_t timer)
122044961713Sgirish {
122144961713Sgirish 	ldgimgm_t		mgm;
122244961713Sgirish 	uint64_t		val;
122344961713Sgirish 
1224a3c5bd6dSspeer 	ASSERT((LDG_VALID(ldg)) && (LD_INTTIMER_VALID(timer)));
122544961713Sgirish 	if (!LDG_VALID(ldg)) {
122644961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
122752ccf843Smisaki 		    " npi_intr_ldg_mgmt_set"
122852ccf843Smisaki 		    " Invalid Input: "
122952ccf843Smisaki 		    " ldg <0x%x>", ldg));
123044961713Sgirish 		return (NPI_FAILURE | NPI_VIR_LDG_INVALID(ldg));
123144961713Sgirish 	}
123244961713Sgirish 	if (!LD_INTTIMER_VALID(timer)) {
123344961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
123452ccf843Smisaki 		    " npi_intr_ldg_mgmt_set Invalid Input"
123552ccf843Smisaki 		    " timer <0x%x>", timer));
123644961713Sgirish 		return (NPI_FAILURE | NPI_VIR_INTM_TM_INVALID(ldg));
123744961713Sgirish 	}
123844961713Sgirish 
123944961713Sgirish 	if (arm) {
124044961713Sgirish 		mgm.bits.ldw.arm = 1;
124144961713Sgirish 	} else {
124244961713Sgirish 		NXGE_REG_RD64(handle, LDGIMGN_REG + LDSV_OFFSET(ldg), &val);
124344961713Sgirish 		mgm.value = val & LDGIMGM_ARM_MASK;
124444961713Sgirish 	}
124544961713Sgirish 
124644961713Sgirish 	mgm.bits.ldw.timer = timer;
124744961713Sgirish 	NXGE_REG_WR64(handle, LDGIMGN_REG + LDSV_OFFSET(ldg),
124852ccf843Smisaki 	    mgm.value);
124944961713Sgirish 
125044961713Sgirish 	NPI_DEBUG_MSG((handle.function, NPI_VIR_CTL,
125152ccf843Smisaki 	    " npi_intr_ldg_mgmt_set: ldg %d"
125252ccf843Smisaki 	    " reg offset 0x%x",
125352ccf843Smisaki 	    ldg, LDGIMGN_REG + LDSV_OFFSET(ldg)));
125444961713Sgirish 
125544961713Sgirish 	return (NPI_SUCCESS);
125644961713Sgirish }
125744961713Sgirish 
125844961713Sgirish /*
125944961713Sgirish  * npi_intr_ldg_mgmt_timer_get():
126044961713Sgirish  *	This function is called to get the timer counter
126144961713Sgirish  * Parameters:
126244961713Sgirish  *	handle		- NPI handle
126344961713Sgirish  *	ldg		- logical device group (0 - 63)
126444961713Sgirish  *	timer_p		- pointer to store the timer counter.
126544961713Sgirish  * Return:
126644961713Sgirish  *	NPI_SUCCESS	-
126744961713Sgirish  *	Error:
126844961713Sgirish  *	NPI_FAILURE
126944961713Sgirish  */
1270a3c5bd6dSspeer 
127144961713Sgirish npi_status_t
npi_intr_ldg_mgmt_timer_get(npi_handle_t handle,uint8_t ldg,uint8_t * timer_p)127244961713Sgirish npi_intr_ldg_mgmt_timer_get(npi_handle_t handle, uint8_t ldg, uint8_t *timer_p)
127344961713Sgirish {
127444961713Sgirish 	uint64_t val;
127544961713Sgirish 
1276a3c5bd6dSspeer 	ASSERT(LDG_VALID(ldg));
127744961713Sgirish 	if (!LDG_VALID(ldg)) {
127844961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
127952ccf843Smisaki 		    " npi_intr_ldg_mgmt_timer_get"
128052ccf843Smisaki 		    " Invalid Input: ldg <0x%x>", ldg));
128144961713Sgirish 		return (NPI_FAILURE | NPI_VIR_LDG_INVALID(ldg));
128244961713Sgirish 	}
128344961713Sgirish 
128444961713Sgirish 	NXGE_REG_RD64(handle, LDGIMGN_REG + LDSV_OFFSET(ldg), &val);
128544961713Sgirish 
128644961713Sgirish 	*timer_p = (uint8_t)(val & LDGIMGM_TIMER_MASK);
128744961713Sgirish 
128844961713Sgirish 	NPI_DEBUG_MSG((handle.function, NPI_VIR_CTL,
128952ccf843Smisaki 	    " npi_intr_ldg_mgmt_timer_get: ldg %d"
129052ccf843Smisaki 	    " reg offset 0x%x",
129152ccf843Smisaki 	    ldg, LDGIMGN_REG + LDSV_OFFSET(ldg)));
129244961713Sgirish 
129344961713Sgirish 	return (NPI_SUCCESS);
129444961713Sgirish }
129544961713Sgirish 
129644961713Sgirish /*
129744961713Sgirish  * npi_intr_ldg_mgmt_arm():
129844961713Sgirish  *	This function is called to arm the group.
129944961713Sgirish  * Parameters:
130044961713Sgirish  *	handle		- NPI handle
130144961713Sgirish  *	ldg		- logical device group (0 - 63)
130244961713Sgirish  * Return:
130344961713Sgirish  *	NPI_SUCCESS	-
130444961713Sgirish  *	Error:
130544961713Sgirish  *	NPI_FAILURE
130644961713Sgirish  */
1307a3c5bd6dSspeer 
130844961713Sgirish npi_status_t
npi_intr_ldg_mgmt_arm(npi_handle_t handle,uint8_t ldg)130944961713Sgirish npi_intr_ldg_mgmt_arm(npi_handle_t handle, uint8_t ldg)
131044961713Sgirish {
131144961713Sgirish 	ldgimgm_t		mgm;
131244961713Sgirish 
1313a3c5bd6dSspeer 	ASSERT(LDG_VALID(ldg));
131444961713Sgirish 	if (!LDG_VALID(ldg)) {
131544961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
131652ccf843Smisaki 		    " npi_intr_ldg_mgmt_arm"
131752ccf843Smisaki 		    " Invalid Input: ldg <0x%x>",
131852ccf843Smisaki 		    ldg));
131944961713Sgirish 		return (NPI_FAILURE | NPI_VIR_LDG_INVALID(ldg));
132044961713Sgirish 	}
132144961713Sgirish 
132244961713Sgirish 	NXGE_REG_RD64(handle, (LDGIMGN_REG + LDSV_OFFSET(ldg)), &mgm.value);
132344961713Sgirish 	mgm.bits.ldw.arm = 1;
132444961713Sgirish 
132544961713Sgirish 	NXGE_REG_WR64(handle, LDGIMGN_REG + LDSV_OFFSET(ldg),
132652ccf843Smisaki 	    mgm.value);
132744961713Sgirish 	NPI_DEBUG_MSG((handle.function, NPI_VIR_CTL,
132852ccf843Smisaki 	    " npi_intr_ldg_mgmt_arm: ldg %d"
132952ccf843Smisaki 	    " reg offset 0x%x",
133052ccf843Smisaki 	    ldg, LDGIMGN_REG + LDSV_OFFSET(ldg)));
133144961713Sgirish 
133244961713Sgirish 	return (NPI_SUCCESS);
133344961713Sgirish }
133444961713Sgirish 
133544961713Sgirish /*
133644961713Sgirish  * npi_fzc_ldg_timer_res_set():
133744961713Sgirish  *	This function is called to set the timer resolution.
133844961713Sgirish  * Parameters:
133944961713Sgirish  *	handle		- NPI handle
134044961713Sgirish  *	res		- timer resolution (# of system clocks)
134144961713Sgirish  * Return:
134244961713Sgirish  *	NPI_SUCCESS	-
134344961713Sgirish  *	Error:
134444961713Sgirish  *	NPI_FAILURE
134544961713Sgirish  */
1346a3c5bd6dSspeer 
134744961713Sgirish npi_status_t
npi_fzc_ldg_timer_res_set(npi_handle_t handle,uint32_t res)134844961713Sgirish npi_fzc_ldg_timer_res_set(npi_handle_t handle, uint32_t res)
134944961713Sgirish {
1350a3c5bd6dSspeer 	ASSERT(res <= LDGTITMRES_RES_MASK);
135144961713Sgirish 	if (res > LDGTITMRES_RES_MASK) {
135244961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
135352ccf843Smisaki 		    " npi_fzc_ldg_timer_res_set"
135452ccf843Smisaki 		    " Invalid Input: res <0x%x>",
135552ccf843Smisaki 		    res));
135644961713Sgirish 		return (NPI_FAILURE | NPI_VIR_TM_RES_INVALID);
135744961713Sgirish 	}
135844961713Sgirish 
135944961713Sgirish 	NXGE_REG_WR64(handle, LDGITMRES_REG, (res & LDGTITMRES_RES_MASK));
136044961713Sgirish 
136144961713Sgirish 	return (NPI_SUCCESS);
136244961713Sgirish }
136344961713Sgirish 
136444961713Sgirish /*
136544961713Sgirish  * npi_fzc_ldg_timer_res_get():
136644961713Sgirish  *	This function is called to get the timer resolution.
136744961713Sgirish  * Parameters:
136844961713Sgirish  *	handle		- NPI handle
136944961713Sgirish  *	res_p		- pointer to store the timer resolution.
137044961713Sgirish  * Return:
137144961713Sgirish  *	NPI_SUCCESS	-
137244961713Sgirish  *	Error:
137344961713Sgirish  *	NPI_FAILURE
137444961713Sgirish  */
1375a3c5bd6dSspeer 
137644961713Sgirish npi_status_t
npi_fzc_ldg_timer_res_get(npi_handle_t handle,uint8_t * res_p)137744961713Sgirish npi_fzc_ldg_timer_res_get(npi_handle_t handle, uint8_t *res_p)
137844961713Sgirish {
137944961713Sgirish 	uint64_t val;
138044961713Sgirish 
138144961713Sgirish 	NXGE_REG_RD64(handle, LDGITMRES_REG, &val);
138244961713Sgirish 
138344961713Sgirish 	*res_p = (uint8_t)(val & LDGIMGM_TIMER_MASK);
138444961713Sgirish 
138544961713Sgirish 	return (NPI_SUCCESS);
138644961713Sgirish }
138744961713Sgirish 
138844961713Sgirish /*
138944961713Sgirish  * npi_fzc_sid_set():
139044961713Sgirish  *	This function is called to set the system interrupt data.
139144961713Sgirish  * Parameters:
139244961713Sgirish  *	handle		- NPI handle
139344961713Sgirish  *	ldg		- logical group (0 - 63)
139444961713Sgirish  *	sid		- NPI defined data to set
139544961713Sgirish  * Return:
139644961713Sgirish  *	NPI_SUCCESS	-
139744961713Sgirish  *	Error:
139844961713Sgirish  *	NPI_FAILURE
139944961713Sgirish  */
1400a3c5bd6dSspeer 
140144961713Sgirish npi_status_t
npi_fzc_sid_set(npi_handle_t handle,fzc_sid_t sid)140244961713Sgirish npi_fzc_sid_set(npi_handle_t handle, fzc_sid_t sid)
140344961713Sgirish {
140444961713Sgirish 	sid_t		sd;
140544961713Sgirish 
1406a3c5bd6dSspeer 	ASSERT(LDG_VALID(sid.ldg));
140744961713Sgirish 	if (!LDG_VALID(sid.ldg)) {
140844961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
140952ccf843Smisaki 		    " npi_fzc_sid_set"
141052ccf843Smisaki 		    " Invalid Input: ldg <0x%x>",
141152ccf843Smisaki 		    sid.ldg));
141244961713Sgirish 		return (NPI_FAILURE | NPI_VIR_LDG_INVALID(sid.ldg));
141344961713Sgirish 	}
141444961713Sgirish 	if (!sid.niu) {
1415a3c5bd6dSspeer 		ASSERT(FUNC_VALID(sid.func));
141644961713Sgirish 		if (!FUNC_VALID(sid.func)) {
141744961713Sgirish 			NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
141852ccf843Smisaki 			    " npi_fzc_sid_set"
141952ccf843Smisaki 			    " Invalid Input: func <0x%x>",
142052ccf843Smisaki 			    sid.func));
142144961713Sgirish 			NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
142252ccf843Smisaki 			    "invalid FUNC: npi_fzc_sid_set(%d)", sid.func));
142344961713Sgirish 			return (NPI_FAILURE | NPI_VIR_FUNC_INVALID(sid.func));
142444961713Sgirish 		}
142544961713Sgirish 
1426a3c5bd6dSspeer 		ASSERT(SID_VECTOR_VALID(sid.vector));
142744961713Sgirish 		if (!SID_VECTOR_VALID(sid.vector)) {
142844961713Sgirish 			NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
142952ccf843Smisaki 			    " npi_fzc_sid_set"
143052ccf843Smisaki 			    " Invalid Input: vector <0x%x>",
143152ccf843Smisaki 			    sid.vector));
143244961713Sgirish 			NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
143352ccf843Smisaki 			    " invalid VECTOR: npi_fzc_sid_set(%d)",
143452ccf843Smisaki 			    sid.vector));
143544961713Sgirish 			return (NPI_FAILURE |
143652ccf843Smisaki 			    NPI_VIR_SID_VEC_INVALID(sid.vector));
143744961713Sgirish 		}
143844961713Sgirish 	}
143944961713Sgirish 	sd.value = 0;
144044961713Sgirish 	if (!sid.niu) {
144144961713Sgirish 		sd.bits.ldw.data = ((sid.func << SID_DATA_FUNCNUM_SHIFT) |
144252ccf843Smisaki 		    (sid.vector & SID_DATA_INTNUM_MASK));
144344961713Sgirish 	}
1444a3c5bd6dSspeer 
144556d930aeSspeer 	NPI_DEBUG_MSG((handle.function, NPI_VIR_CTL,
1446a3c5bd6dSspeer 	    " npi_fzc_sid_set: group %d 0x%llx", sid.ldg, sd.value));
144744961713Sgirish 
144844961713Sgirish 	NXGE_REG_WR64(handle,  SID_REG + LDG_SID_OFFSET(sid.ldg), sd.value);
144944961713Sgirish 
145044961713Sgirish 	return (NPI_SUCCESS);
145144961713Sgirish }
145244961713Sgirish 
145344961713Sgirish /*
145444961713Sgirish  * npi_fzc_sid_get():
145544961713Sgirish  *	This function is called to get the system interrupt data.
145644961713Sgirish  * Parameters:
145744961713Sgirish  *	handle		- NPI handle
145844961713Sgirish  *	ldg		- logical group (0 - 63)
145944961713Sgirish  *	sid_p		- NPI defined data to get
146044961713Sgirish  * Return:
146144961713Sgirish  *	NPI_SUCCESS	-
146244961713Sgirish  *	Error:
146344961713Sgirish  *	NPI_FAILURE
146444961713Sgirish  */
1465a3c5bd6dSspeer 
146644961713Sgirish npi_status_t
npi_fzc_sid_get(npi_handle_t handle,p_fzc_sid_t sid_p)146744961713Sgirish npi_fzc_sid_get(npi_handle_t handle, p_fzc_sid_t sid_p)
146844961713Sgirish {
146944961713Sgirish 	sid_t		sd;
147044961713Sgirish 
1471a3c5bd6dSspeer 	ASSERT(LDG_VALID(sid_p->ldg));
147244961713Sgirish 	if (!LDG_VALID(sid_p->ldg)) {
147344961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
147452ccf843Smisaki 		    " npi_fzc_sid_get"
147552ccf843Smisaki 		    " Invalid Input: ldg <0x%x>",
147652ccf843Smisaki 		    sid_p->ldg));
147744961713Sgirish 		return (NPI_FAILURE | NPI_VIR_LDG_INVALID(sid_p->ldg));
147844961713Sgirish 	}
147944961713Sgirish 	NXGE_REG_RD64(handle, (SID_REG + LDG_SID_OFFSET(sid_p->ldg)),
148052ccf843Smisaki 	    &sd.value);
148144961713Sgirish 	if (!sid_p->niu) {
148244961713Sgirish 		sid_p->func = ((sd.bits.ldw.data & SID_DATA_FUNCNUM_MASK) >>
148352ccf843Smisaki 		    SID_DATA_FUNCNUM_SHIFT);
148444961713Sgirish 		sid_p->vector = ((sd.bits.ldw.data & SID_DATA_INTNUM_MASK) >>
148552ccf843Smisaki 		    SID_DATA_INTNUM_SHIFT);
148644961713Sgirish 	} else {
148744961713Sgirish 		sid_p->vector = (sd.value & SID_DATA_MASK);
148844961713Sgirish 	}
148944961713Sgirish 
149044961713Sgirish 	return (NPI_SUCCESS);
149144961713Sgirish }
149244961713Sgirish 
149344961713Sgirish /*
149444961713Sgirish  * npi_fzc_sys_err_mask_set():
149544961713Sgirish  *	This function is called to mask/unmask the device error mask bits.
149644961713Sgirish  *
149744961713Sgirish  * Parameters:
149844961713Sgirish  *	handle		- NPI handle
149944961713Sgirish  *	mask		- set bit mapped mask
150044961713Sgirish  * Return:
150144961713Sgirish  *	NPI_SUCCESS	-
150244961713Sgirish  *	Error:
150344961713Sgirish  *	NPI_FAILURE
150444961713Sgirish  */
1505a3c5bd6dSspeer 
150644961713Sgirish npi_status_t
npi_fzc_sys_err_mask_set(npi_handle_t handle,uint64_t mask)150744961713Sgirish npi_fzc_sys_err_mask_set(npi_handle_t handle, uint64_t mask)
150844961713Sgirish {
150944961713Sgirish 	NXGE_REG_WR64(handle,  SYS_ERR_MASK_REG, mask);
151044961713Sgirish 	return (NPI_SUCCESS);
151144961713Sgirish }
151244961713Sgirish 
151344961713Sgirish /*
151444961713Sgirish  * npi_fzc_sys_err_stat_get():
151544961713Sgirish  *	This function is called to get the system error stats.
151644961713Sgirish  *
151744961713Sgirish  * Parameters:
151844961713Sgirish  *	handle		- NPI handle
151944961713Sgirish  *	err_stat	- sys_err_stat structure to hold stats.
152044961713Sgirish  * Return:
152144961713Sgirish  *	NPI_SUCCESS	-
152244961713Sgirish  *	Error:
152344961713Sgirish  *	NPI_FAILURE
152444961713Sgirish  */
1525a3c5bd6dSspeer 
152644961713Sgirish npi_status_t
npi_fzc_sys_err_stat_get(npi_handle_t handle,p_sys_err_stat_t statp)152744961713Sgirish npi_fzc_sys_err_stat_get(npi_handle_t handle, p_sys_err_stat_t statp)
152844961713Sgirish {
152944961713Sgirish 	NXGE_REG_RD64(handle,  SYS_ERR_STAT_REG, &statp->value);
153044961713Sgirish 	return (NPI_SUCCESS);
153144961713Sgirish }
153244961713Sgirish 
153344961713Sgirish npi_status_t
npi_fzc_rst_ctl_get(npi_handle_t handle,p_rst_ctl_t rstp)153444961713Sgirish npi_fzc_rst_ctl_get(npi_handle_t handle, p_rst_ctl_t rstp)
153544961713Sgirish {
153644961713Sgirish 	NXGE_REG_RD64(handle, RST_CTL_REG, &rstp->value);
153744961713Sgirish 
153844961713Sgirish 	return (NPI_SUCCESS);
153944961713Sgirish }
154044961713Sgirish 
154144961713Sgirish /*
154244961713Sgirish  * npi_fzc_mpc_get():
154344961713Sgirish  *	This function is called to get the access mode.
154444961713Sgirish  * Parameters:
154544961713Sgirish  *	handle		- NPI handle
154644961713Sgirish  * Return:
154744961713Sgirish  *	NPI_SUCCESS	-
154844961713Sgirish  *
154944961713Sgirish  */
1550a3c5bd6dSspeer 
155144961713Sgirish npi_status_t
npi_fzc_rst_ctl_reset_mac(npi_handle_t handle,uint8_t port)155244961713Sgirish npi_fzc_rst_ctl_reset_mac(npi_handle_t handle, uint8_t port)
155344961713Sgirish {
155444961713Sgirish 	rst_ctl_t 		rst;
155544961713Sgirish 
155644961713Sgirish 	rst.value = 0;
155744961713Sgirish 	NXGE_REG_RD64(handle, RST_CTL_REG, &rst.value);
155844961713Sgirish 	rst.value |= (1 << (RST_CTL_MAC_RST0_SHIFT + port));
155944961713Sgirish 	NXGE_REG_WR64(handle, RST_CTL_REG, rst.value);
156044961713Sgirish 
156144961713Sgirish 	return (NPI_SUCCESS);
156244961713Sgirish }
1563