144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 22*678453a8Sspeer * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 2344961713Sgirish * Use is subject to license terms. 2444961713Sgirish */ 2544961713Sgirish 2644961713Sgirish #pragma ident "%Z%%M% %I% %E% SMI" 2744961713Sgirish 28a3c5bd6dSspeer #include <npi_vir.h> 2944961713Sgirish 3044961713Sgirish /* One register only */ 3144961713Sgirish uint64_t pio_offset[] = { 3244961713Sgirish DEV_FUNC_SR_REG 3344961713Sgirish }; 3444961713Sgirish 3544961713Sgirish const char *pio_name[] = { 3644961713Sgirish "DEV_FUNC_SR_REG", 3744961713Sgirish }; 3844961713Sgirish 3944961713Sgirish /* One register only */ 4044961713Sgirish uint64_t fzc_pio_offset[] = { 4144961713Sgirish MULTI_PART_CTL_REG, 4244961713Sgirish LDGITMRES_REG 4344961713Sgirish }; 4444961713Sgirish 4544961713Sgirish const char *fzc_pio_name[] = { 4644961713Sgirish "MULTI_PART_CTL_REG", 4744961713Sgirish "LDGITMRES_REG" 4844961713Sgirish }; 4944961713Sgirish 5044961713Sgirish /* 64 sets */ 5144961713Sgirish uint64_t fzc_pio_dma_bind_offset[] = { 5244961713Sgirish DMA_BIND_REG 5344961713Sgirish }; 5444961713Sgirish 5544961713Sgirish const char *fzc_pio_dma_bind_name[] = { 5644961713Sgirish "DMA_BIND_REG", 5744961713Sgirish }; 5844961713Sgirish 5944961713Sgirish /* 69 logical devices */ 6044961713Sgirish uint64_t fzc_pio_ldgnum_offset[] = { 6144961713Sgirish LDG_NUM_REG 6244961713Sgirish }; 6344961713Sgirish 6444961713Sgirish const char *fzc_pio_ldgnum_name[] = { 6544961713Sgirish "LDG_NUM_REG", 6644961713Sgirish }; 6744961713Sgirish 6844961713Sgirish /* PIO_LDSV, 64 sets by 8192 bytes */ 6944961713Sgirish uint64_t pio_ldsv_offset[] = { 7044961713Sgirish LDSV0_REG, 7144961713Sgirish LDSV1_REG, 7244961713Sgirish LDSV2_REG, 7344961713Sgirish LDGIMGN_REG 7444961713Sgirish }; 7544961713Sgirish const char *pio_ldsv_name[] = { 7644961713Sgirish "LDSV0_REG", 7744961713Sgirish "LDSV1_REG", 7844961713Sgirish "LDSV2_REG", 7944961713Sgirish "LDGIMGN_REG" 8044961713Sgirish }; 8144961713Sgirish 8244961713Sgirish /* PIO_IMASK0: 64 by 8192 */ 8344961713Sgirish uint64_t pio_imask0_offset[] = { 8444961713Sgirish LD_IM0_REG, 8544961713Sgirish }; 8644961713Sgirish 8744961713Sgirish const char *pio_imask0_name[] = { 8844961713Sgirish "LD_IM0_REG", 8944961713Sgirish }; 9044961713Sgirish 9144961713Sgirish /* PIO_IMASK1: 5 by 8192 */ 9244961713Sgirish uint64_t pio_imask1_offset[] = { 9344961713Sgirish LD_IM1_REG 9444961713Sgirish }; 9544961713Sgirish 9644961713Sgirish const char *pio_imask1_name[] = { 9744961713Sgirish "LD_IM1_REG" 9844961713Sgirish }; 9944961713Sgirish 10044961713Sgirish /* SID: 64 by 8 */ 10144961713Sgirish uint64_t fzc_pio_sid_offset[] = { 10244961713Sgirish SID_REG 10344961713Sgirish }; 10444961713Sgirish 10544961713Sgirish const char *fzc_pio_sid_name[] = { 10644961713Sgirish "SID_REG" 10744961713Sgirish }; 10844961713Sgirish 10944961713Sgirish npi_status_t 11044961713Sgirish npi_vir_dump_pio_fzc_regs_one(npi_handle_t handle) 11144961713Sgirish { 11244961713Sgirish uint64_t value; 11344961713Sgirish int num_regs, i; 11444961713Sgirish 11544961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 11644961713Sgirish "\nPIO FZC Common Register Dump\n")); 11744961713Sgirish 11844961713Sgirish num_regs = sizeof (pio_offset) / sizeof (uint64_t); 11944961713Sgirish for (i = 0; i < num_regs; i++) { 12044961713Sgirish value = 0; 12144961713Sgirish NXGE_REG_RD64(handle, pio_offset[i], &value); 12244961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, "0x%08llx " 12344961713Sgirish "%s\t 0x%08llx \n", 12444961713Sgirish pio_offset[i], 12544961713Sgirish pio_name[i], value)); 12644961713Sgirish } 12744961713Sgirish 12844961713Sgirish num_regs = sizeof (fzc_pio_offset) / sizeof (uint64_t); 12944961713Sgirish for (i = 0; i < num_regs; i++) { 13044961713Sgirish NXGE_REG_RD64(handle, fzc_pio_offset[i], &value); 13144961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, "0x%08llx " 13244961713Sgirish "%s\t 0x%08llx \n", 13344961713Sgirish fzc_pio_offset[i], 13444961713Sgirish fzc_pio_name[i], value)); 13544961713Sgirish } 13644961713Sgirish 13744961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 13844961713Sgirish "\n PIO FZC Register Dump Done \n")); 13944961713Sgirish return (NPI_SUCCESS); 14044961713Sgirish } 14144961713Sgirish 14244961713Sgirish npi_status_t 14344961713Sgirish npi_vir_dump_ldgnum(npi_handle_t handle) 14444961713Sgirish { 14544961713Sgirish uint64_t value = 0, offset = 0; 14644961713Sgirish int num_regs, i, ldv; 14744961713Sgirish 14844961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 14944961713Sgirish "\nFZC PIO LDG Number Register Dump\n")); 15044961713Sgirish 15144961713Sgirish num_regs = sizeof (fzc_pio_ldgnum_offset) / sizeof (uint64_t); 15244961713Sgirish for (ldv = 0; ldv < NXGE_INT_MAX_LDS; ldv++) { 15344961713Sgirish for (i = 0; i < num_regs; i++) { 15444961713Sgirish value = 0; 15544961713Sgirish offset = fzc_pio_ldgnum_offset[i] + 8 * ldv; 15644961713Sgirish NXGE_REG_RD64(handle, offset, &value); 15744961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 15844961713Sgirish "Logical Device %d: 0x%08llx " 159*678453a8Sspeer "%s\t %d\n", 16044961713Sgirish ldv, offset, 16144961713Sgirish fzc_pio_ldgnum_name[i], value)); 16244961713Sgirish } 16344961713Sgirish } 16444961713Sgirish 16544961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 16644961713Sgirish "\n FZC PIO LDG Register Dump Done \n")); 16744961713Sgirish 16844961713Sgirish return (NPI_SUCCESS); 16944961713Sgirish } 17044961713Sgirish 17144961713Sgirish npi_status_t 17244961713Sgirish npi_vir_dump_ldsv(npi_handle_t handle) 17344961713Sgirish { 17444961713Sgirish uint64_t value, offset; 17544961713Sgirish int num_regs, i, ldg; 17644961713Sgirish 17744961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 17844961713Sgirish "\nLD Device State Vector Register Dump\n")); 17944961713Sgirish 18044961713Sgirish num_regs = sizeof (pio_ldsv_offset) / sizeof (uint64_t); 18144961713Sgirish for (ldg = 0; ldg < NXGE_INT_MAX_LDGS; ldg++) { 18244961713Sgirish for (i = 0; i < num_regs; i++) { 18344961713Sgirish value = 0; 18444961713Sgirish offset = pio_ldsv_offset[i] + 8192 * ldg; 18544961713Sgirish NXGE_REG_RD64(handle, offset, &value); 18644961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 18744961713Sgirish "LDG State: group %d: 0x%08llx " 18844961713Sgirish "%s\t 0x%08llx \n", 18944961713Sgirish ldg, offset, 19044961713Sgirish pio_ldsv_name[i], value)); 19144961713Sgirish } 19244961713Sgirish } 19344961713Sgirish 19444961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 19544961713Sgirish "\n FZC PIO LDG Register Dump Done \n")); 19644961713Sgirish 19744961713Sgirish return (NPI_SUCCESS); 19844961713Sgirish } 19944961713Sgirish 20044961713Sgirish npi_status_t 20144961713Sgirish npi_vir_dump_imask0(npi_handle_t handle) 20244961713Sgirish { 20344961713Sgirish uint64_t value, offset; 20444961713Sgirish int num_regs, i, ldv; 20544961713Sgirish 20644961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 20744961713Sgirish "\nLD Interrupt Mask Register Dump\n")); 20844961713Sgirish 20944961713Sgirish num_regs = sizeof (pio_imask0_offset) / sizeof (uint64_t); 21044961713Sgirish for (ldv = 0; ldv < 64; ldv++) { 21144961713Sgirish for (i = 0; i < num_regs; i++) { 21244961713Sgirish value = 0; 21344961713Sgirish offset = pio_imask0_offset[i] + 8192 * ldv; 21444961713Sgirish NXGE_REG_RD64(handle, offset, 21544961713Sgirish &value); 21644961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 21744961713Sgirish "LD Interrupt Mask %d: 0x%08llx " 21844961713Sgirish "%s\t 0x%08llx \n", 21944961713Sgirish ldv, offset, 22044961713Sgirish pio_imask0_name[i], value)); 22144961713Sgirish } 22244961713Sgirish } 22344961713Sgirish num_regs = sizeof (pio_imask1_offset) / sizeof (uint64_t); 22444961713Sgirish for (ldv = 64; ldv < 69; ldv++) { 22544961713Sgirish for (i = 0; i < num_regs; i++) { 22644961713Sgirish value = 0; 22744961713Sgirish offset = pio_imask1_offset[i] + 8192 * (ldv - 64); 22844961713Sgirish NXGE_REG_RD64(handle, offset, 22944961713Sgirish &value); 23044961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 23144961713Sgirish "LD Interrupt Mask %d: 0x%08llx " 23244961713Sgirish "%s\t 0x%08llx \n", 23344961713Sgirish ldv, offset, 23444961713Sgirish pio_imask1_name[i], value)); 23544961713Sgirish } 23644961713Sgirish } 23744961713Sgirish 23844961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 23944961713Sgirish "\n FZC PIO Logical Device Group Register Dump Done \n")); 24044961713Sgirish 24144961713Sgirish return (NPI_SUCCESS); 24244961713Sgirish } 24344961713Sgirish 24444961713Sgirish npi_status_t 24544961713Sgirish npi_vir_dump_sid(npi_handle_t handle) 24644961713Sgirish { 24744961713Sgirish uint64_t value, offset; 24844961713Sgirish int num_regs, i, ldg; 24944961713Sgirish 25044961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 25144961713Sgirish "\nSystem Interrupt Data Register Dump\n")); 25244961713Sgirish 25344961713Sgirish num_regs = sizeof (fzc_pio_sid_offset) / sizeof (uint64_t); 25444961713Sgirish for (ldg = 0; ldg < NXGE_INT_MAX_LDGS; ldg++) { 25544961713Sgirish for (i = 0; i < num_regs; i++) { 25644961713Sgirish value = 0; 25744961713Sgirish offset = fzc_pio_sid_offset[i] + 8 * ldg; 25844961713Sgirish NXGE_REG_RD64(handle, offset, 25944961713Sgirish &value); 26044961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 26144961713Sgirish "SID for group %d: 0x%08llx " 26244961713Sgirish "%s\t 0x%08llx \n", 26344961713Sgirish ldg, offset, 26444961713Sgirish fzc_pio_sid_name[i], value)); 26544961713Sgirish } 26644961713Sgirish } 26744961713Sgirish 26844961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 26944961713Sgirish "\n FZC PIO SID Register Dump Done \n")); 27044961713Sgirish 27144961713Sgirish return (NPI_SUCCESS); 27244961713Sgirish } 27344961713Sgirish 27444961713Sgirish /* 27544961713Sgirish * npi_dev_func_sr_init(): 27644961713Sgirish * This function is called to initialize the device function 27744961713Sgirish * shared register (set the software implementation lock 27844961713Sgirish * state to FREE). 27944961713Sgirish * Parameters: 28044961713Sgirish * handle - NPI handle 28144961713Sgirish * Return: 28244961713Sgirish * NPI_SUCCESS - If initialization is complete successfully. 28344961713Sgirish * (set sr bits to free). 28444961713Sgirish * Error: 28544961713Sgirish * NPI_FAILURE 28644961713Sgirish * VIR_TAS_BUSY 28744961713Sgirish */ 288a3c5bd6dSspeer 28944961713Sgirish npi_status_t 29044961713Sgirish npi_dev_func_sr_init(npi_handle_t handle) 29144961713Sgirish { 29244961713Sgirish dev_func_sr_t sr; 29344961713Sgirish int status = NPI_SUCCESS; 29444961713Sgirish 29544961713Sgirish NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value); 29644961713Sgirish if (!sr.bits.ldw.tas) { 29744961713Sgirish /* 29844961713Sgirish * After read, this bit is set to 1 by hardware. 29944961713Sgirish * We own it if tas bit read as 0. 30044961713Sgirish * Set the lock state to free if it is in reset state. 30144961713Sgirish */ 30244961713Sgirish if (!sr.bits.ldw.sr) { 30344961713Sgirish /* reset state */ 30444961713Sgirish sr.bits.ldw.sr |= NPI_DEV_SR_LOCK_ST_FREE; 30544961713Sgirish NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); 30644961713Sgirish sr.bits.ldw.tas = 0; 30744961713Sgirish NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); 30844961713Sgirish } 30944961713Sgirish 31056d930aeSspeer NPI_DEBUG_MSG((handle.function, NPI_VIR_CTL, 31144961713Sgirish " npi_dev_func_sr_init" 31244961713Sgirish " sr <0x%x>", 31344961713Sgirish sr.bits.ldw.sr)); 31444961713Sgirish } else { 31544961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 31644961713Sgirish " npi_dev_func_sr_init" 31744961713Sgirish " tas busy <0x%x>", 31844961713Sgirish sr.bits.ldw)); 31944961713Sgirish status = NPI_VIR_TAS_BUSY(sr.bits.ldw.funcid); 32044961713Sgirish } 32144961713Sgirish 32244961713Sgirish return (status); 32344961713Sgirish } 32444961713Sgirish 32544961713Sgirish /* 32644961713Sgirish * npi_dev_func_sr_lock_enter(): 32744961713Sgirish * This function is called to lock the function shared register 32844961713Sgirish * by setting the lock state to busy. 32944961713Sgirish * Parameters: 33044961713Sgirish * handle - NPI handle 33144961713Sgirish * Return: 33244961713Sgirish * NPI_SUCCESS - If the function id can own the lock. 33344961713Sgirish * 33444961713Sgirish * Error: 33544961713Sgirish * NPI_FAILURE 33644961713Sgirish * VIR_SR_RESET 33744961713Sgirish * VIR_SR_BUSY 33844961713Sgirish * VIR_SR_INVALID 33944961713Sgirish * VIR_TAS_BUSY 34044961713Sgirish */ 341a3c5bd6dSspeer 34244961713Sgirish npi_status_t 34344961713Sgirish npi_dev_func_sr_lock_enter(npi_handle_t handle) 34444961713Sgirish { 34544961713Sgirish dev_func_sr_t sr; 34644961713Sgirish int status = NPI_SUCCESS; 34744961713Sgirish uint32_t state; 34844961713Sgirish 34944961713Sgirish NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value); 35044961713Sgirish if (!sr.bits.ldw.tas) { 35144961713Sgirish /* 35244961713Sgirish * tas bit will be set to 1 by hardware. 35344961713Sgirish * reset tas bit when we unlock the sr. 35444961713Sgirish */ 35544961713Sgirish state = sr.bits.ldw.sr & NPI_DEV_SR_LOCK_ST_MASK; 35644961713Sgirish switch (state) { 35744961713Sgirish case NPI_DEV_SR_LOCK_ST_FREE: 35844961713Sgirish /* 35944961713Sgirish * set it to busy and our function id. 36044961713Sgirish */ 36144961713Sgirish sr.bits.ldw.sr |= (NPI_DEV_SR_LOCK_ST_BUSY | 36244961713Sgirish (sr.bits.ldw.funcid << 36344961713Sgirish NPI_DEV_SR_LOCK_FID_SHIFT)); 36444961713Sgirish NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); 36544961713Sgirish break; 36644961713Sgirish 36744961713Sgirish case NPI_DEV_SR_LOCK_ST_RESET: 36844961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 36944961713Sgirish " npi_dev_func_sr_lock_enter" 37044961713Sgirish " reset state <0x%x>", 37144961713Sgirish sr.bits.ldw.sr)); 37244961713Sgirish status = NPI_VIR_SR_RESET(sr.bits.ldw.funcid); 37344961713Sgirish break; 37444961713Sgirish 37544961713Sgirish case NPI_DEV_SR_LOCK_ST_BUSY: 37644961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 37744961713Sgirish " npi_dev_func_sr_lock_enter" 37844961713Sgirish " busy <0x%x>", 37944961713Sgirish sr.bits.ldw.sr)); 38044961713Sgirish status = NPI_VIR_SR_BUSY(sr.bits.ldw.funcid); 38144961713Sgirish break; 38244961713Sgirish 38344961713Sgirish default: 38444961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 38544961713Sgirish " npi_dev_func_sr_lock_enter", 38644961713Sgirish " invalid state", 38744961713Sgirish sr.bits.ldw.sr)); 38844961713Sgirish status = NPI_VIR_SR_INVALID(sr.bits.ldw.funcid); 38944961713Sgirish break; 39044961713Sgirish } 39144961713Sgirish } else { 39244961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 39344961713Sgirish " npi_dev_func_sr_lock_enter", 39444961713Sgirish " tas busy", sr.bits.ldw)); 39544961713Sgirish status = NPI_VIR_TAS_BUSY(sr.bits.ldw.funcid); 39644961713Sgirish } 39744961713Sgirish 39844961713Sgirish return (status); 39944961713Sgirish } 40044961713Sgirish 40144961713Sgirish /* 40244961713Sgirish * npi_dev_func_sr_lock_free(): 40344961713Sgirish * This function is called to free the function shared register 40444961713Sgirish * by setting the lock state to free. 40544961713Sgirish * Parameters: 40644961713Sgirish * handle - NPI handle 40744961713Sgirish * Return: 40844961713Sgirish * NPI_SUCCESS - If the function id can free the lock. 40944961713Sgirish * 41044961713Sgirish * Error: 41144961713Sgirish * NPI_FAILURE 41244961713Sgirish * VIR_SR_NOTOWNER 41344961713Sgirish * VIR_TAS_NOTREAD 41444961713Sgirish */ 415a3c5bd6dSspeer 41644961713Sgirish npi_status_t 41744961713Sgirish npi_dev_func_sr_lock_free(npi_handle_t handle) 41844961713Sgirish { 41944961713Sgirish dev_func_sr_t sr; 42044961713Sgirish int status = NPI_SUCCESS; 42144961713Sgirish 42244961713Sgirish NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value); 42344961713Sgirish if (sr.bits.ldw.tas) { 42444961713Sgirish if (sr.bits.ldw.funcid == NPI_GET_LOCK_OWNER(sr.bits.ldw.sr)) { 42544961713Sgirish sr.bits.ldw.sr &= NPI_DEV_SR_IMPL_ST_MASK; 42644961713Sgirish sr.bits.ldw.sr |= NPI_DEV_SR_LOCK_ST_FREE; 42744961713Sgirish sr.bits.ldw.tas = 0; 42844961713Sgirish NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); 42944961713Sgirish } else { 43044961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_VIR_CTL, 43144961713Sgirish " npi_dev_func_sr_lock_free" 43244961713Sgirish " not owner <0x%x>", 43344961713Sgirish sr.bits.ldw.sr)); 43444961713Sgirish status = NPI_VIR_SR_NOTOWNER(sr.bits.ldw.funcid); 43544961713Sgirish } 43644961713Sgirish } else { 43744961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 43844961713Sgirish " npi_dev_func_sr_lock_free", 43944961713Sgirish " invalid tas state <0x%x>", 44044961713Sgirish sr.bits.ldw.tas)); 44144961713Sgirish status = NPI_VIR_TAS_NOTREAD(sr.bits.ldw.funcid); 44244961713Sgirish } 44344961713Sgirish 44444961713Sgirish return (status); 44544961713Sgirish } 44644961713Sgirish 44744961713Sgirish /* 44844961713Sgirish * npi_dev_func_sr_funcid_get(): 44944961713Sgirish * This function is called to get the caller's function ID. 45044961713Sgirish * (based on address bits [25:26] on read access. 45144961713Sgirish * (After read, the TAS bit is always set to 1. Software needs 45244961713Sgirish * to write 0 to clear.) This function will write 0 to clear 45344961713Sgirish * the TAS bit if we own it. 45444961713Sgirish * Parameters: 45544961713Sgirish * handle - NPI handle 45644961713Sgirish * funcid_p - pointer to store the function id. 45744961713Sgirish * Return: 45844961713Sgirish * NPI_SUCCESS - If get function id is complete successfully. 45944961713Sgirish * 46044961713Sgirish * Error: 46144961713Sgirish */ 462a3c5bd6dSspeer 46344961713Sgirish npi_status_t 46444961713Sgirish npi_dev_func_sr_funcid_get(npi_handle_t handle, uint8_t *funcid_p) 46544961713Sgirish { 46644961713Sgirish dev_func_sr_t sr; 46744961713Sgirish 46844961713Sgirish NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value); 46944961713Sgirish *funcid_p = NXGE_VAL(DEV_FUNC_SR_FUNCID, sr.value); 47044961713Sgirish if (!sr.bits.ldw.tas) { 47144961713Sgirish /* 47244961713Sgirish * After read, this bit is set to 1 by hardware. 47344961713Sgirish * We own it if tas bit read as 0. 47444961713Sgirish */ 47544961713Sgirish sr.bits.ldw.tas = 0; 47644961713Sgirish NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); 47744961713Sgirish } 47844961713Sgirish 47944961713Sgirish return (NPI_SUCCESS); 48044961713Sgirish } 48144961713Sgirish 48244961713Sgirish /* 48344961713Sgirish * npi_dev_func_sr_sr_get(): 48444961713Sgirish * This function is called to get the shared register value. 48544961713Sgirish * (After read, the TAS bit is always set to 1. Software needs 48644961713Sgirish * to write 0 to clear if we own it.) 48744961713Sgirish * 48844961713Sgirish * Parameters: 48944961713Sgirish * handle - NPI handle 49044961713Sgirish * sr_p - pointer to store the shared value of this register. 49144961713Sgirish * 49244961713Sgirish * Return: 49344961713Sgirish * NPI_SUCCESS - If shared value get is complete successfully. 49444961713Sgirish * 49544961713Sgirish * Error: 49644961713Sgirish */ 49744961713Sgirish npi_status_t 49844961713Sgirish npi_dev_func_sr_sr_raw_get(npi_handle_t handle, uint16_t *sr_p) 49944961713Sgirish { 50044961713Sgirish dev_func_sr_t sr; 50144961713Sgirish 50244961713Sgirish NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value); 50344961713Sgirish *sr_p = NXGE_VAL(DEV_FUNC_SR_FUNCID, sr.value); 50444961713Sgirish if (!sr.bits.ldw.tas) { 50544961713Sgirish /* 50644961713Sgirish * After read, this bit is set to 1 by hardware. 50744961713Sgirish * We own it if tas bit read as 0. 50844961713Sgirish */ 50944961713Sgirish sr.bits.ldw.tas = 0; 51044961713Sgirish NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); 51144961713Sgirish } 51244961713Sgirish 51344961713Sgirish return (NPI_SUCCESS); 51444961713Sgirish } 51544961713Sgirish 51644961713Sgirish /* 51744961713Sgirish * npi_dev_func_sr_sr_get(): 51844961713Sgirish * This function is called to get the shared register value. 51944961713Sgirish * (After read, the TAS bit is always set to 1. Software needs 52044961713Sgirish * to write 0 to clear if we own it.) 52144961713Sgirish * 52244961713Sgirish * Parameters: 52344961713Sgirish * handle - NPI handle 52444961713Sgirish * sr_p - pointer to store the shared value of this register. 52544961713Sgirish * . this will get only non-lock, non-function id portion 52644961713Sgirish * . of the register 52744961713Sgirish * 52844961713Sgirish * 52944961713Sgirish * Return: 53044961713Sgirish * NPI_SUCCESS - If shared value get is complete successfully. 53144961713Sgirish * 53244961713Sgirish * Error: 53344961713Sgirish */ 53444961713Sgirish 53544961713Sgirish npi_status_t 53644961713Sgirish npi_dev_func_sr_sr_get(npi_handle_t handle, uint16_t *sr_p) 53744961713Sgirish { 53844961713Sgirish dev_func_sr_t sr; 53944961713Sgirish uint16_t sr_impl = 0; 54044961713Sgirish 54144961713Sgirish NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value); 54244961713Sgirish sr_impl = NXGE_VAL(DEV_FUNC_SR_FUNCID, sr.value); 54344961713Sgirish *sr_p = (sr_impl << NPI_DEV_SR_IMPL_ST_SHIFT); 54444961713Sgirish if (!sr.bits.ldw.tas) { 54544961713Sgirish /* 54644961713Sgirish * After read, this bit is set to 1 by hardware. 54744961713Sgirish * We own it if tas bit read as 0. 54844961713Sgirish */ 54944961713Sgirish sr.bits.ldw.tas = 0; 55044961713Sgirish NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); 55144961713Sgirish } 55244961713Sgirish 55344961713Sgirish return (NPI_SUCCESS); 55444961713Sgirish } 55544961713Sgirish 55644961713Sgirish /* 55744961713Sgirish * npi_dev_func_sr_sr_get_set_clear(): 55844961713Sgirish * This function is called to set the shared register value. 55944961713Sgirish * (Shared register must be read first. If tas bit is 0, then 56044961713Sgirish * it implies that the software can proceed to set). After 56144961713Sgirish * setting, tas bit will be cleared. 56244961713Sgirish * Parameters: 56344961713Sgirish * handle - NPI handle 56444961713Sgirish * impl_sr - shared value to set (only the 8 bit 56544961713Sgirish * implementation specific state info). 56644961713Sgirish * 56744961713Sgirish * Return: 56844961713Sgirish * NPI_SUCCESS - If shared value is set successfully. 56944961713Sgirish * 57044961713Sgirish * Error: 57144961713Sgirish * NPI_FAILURE 57244961713Sgirish * VIR_TAS_BUSY 57344961713Sgirish */ 574a3c5bd6dSspeer 57544961713Sgirish npi_status_t 57644961713Sgirish npi_dev_func_sr_sr_get_set_clear(npi_handle_t handle, uint16_t impl_sr) 57744961713Sgirish { 57844961713Sgirish dev_func_sr_t sr; 57944961713Sgirish int status; 58044961713Sgirish 58144961713Sgirish status = npi_dev_func_sr_lock_enter(handle); 58244961713Sgirish if (status != NPI_SUCCESS) { 58344961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_VIR_CTL, 58444961713Sgirish " npi_dev_func_sr_src_get_set_clear" 58544961713Sgirish " unable to acquire lock:" 58644961713Sgirish " status <0x%x>", status)); 58744961713Sgirish return (status); 58844961713Sgirish } 58944961713Sgirish 59044961713Sgirish NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value); 59144961713Sgirish sr.bits.ldw.sr |= (impl_sr << NPI_DEV_SR_IMPL_ST_SHIFT); 59244961713Sgirish NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); 59344961713Sgirish 59444961713Sgirish return (npi_dev_func_sr_lock_free(handle)); 59544961713Sgirish } 59644961713Sgirish 59744961713Sgirish /* 59844961713Sgirish * npi_dev_func_sr_sr_set_only(): 59944961713Sgirish * This function is called to only set the shared register value. 60044961713Sgirish * Parameters: 60144961713Sgirish * handle - NPI handle 60244961713Sgirish * impl_sr - shared value to set. 60344961713Sgirish * 60444961713Sgirish * Return: 60544961713Sgirish * NPI_SUCCESS - If shared value is set successfully. 60644961713Sgirish * 60744961713Sgirish * Error: 60844961713Sgirish * NPI_FAILURE 60944961713Sgirish * VIR_TAS_BUSY 61044961713Sgirish */ 611a3c5bd6dSspeer 61244961713Sgirish npi_status_t 61344961713Sgirish npi_dev_func_sr_sr_set_only(npi_handle_t handle, uint16_t impl_sr) 61444961713Sgirish { 61544961713Sgirish int status = NPI_SUCCESS; 61644961713Sgirish dev_func_sr_t sr; 61744961713Sgirish 61844961713Sgirish NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value); 61944961713Sgirish /* must be the owner */ 62044961713Sgirish if (sr.bits.ldw.funcid == NPI_GET_LOCK_OWNER(sr.bits.ldw.sr)) { 62144961713Sgirish sr.bits.ldw.sr |= (impl_sr << NPI_DEV_SR_IMPL_ST_SHIFT); 62244961713Sgirish NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); 62344961713Sgirish } else { 62444961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_VIR_CTL, 62544961713Sgirish " npi_dev_func_sr_sr_set_only" 62644961713Sgirish " not owner <0x%x>", 62744961713Sgirish sr.bits.ldw.sr)); 62844961713Sgirish status = NPI_VIR_SR_NOTOWNER(sr.bits.ldw.funcid); 62944961713Sgirish } 63044961713Sgirish 63144961713Sgirish return (status); 63244961713Sgirish } 63344961713Sgirish 63444961713Sgirish /* 63544961713Sgirish * npi_dev_func_sr_busy(): 63644961713Sgirish * This function is called to see if we can own the device. 63744961713Sgirish * It will not reset the tas bit. 63844961713Sgirish * Parameters: 63944961713Sgirish * handle - NPI handle 64044961713Sgirish * busy_p - pointer to store busy flag. 64144961713Sgirish * (B_TRUE: device is in use, B_FALSE: free). 64244961713Sgirish * Return: 64344961713Sgirish * NPI_SUCCESS - If tas bit is read successfully. 64444961713Sgirish * Error: 64544961713Sgirish */ 646a3c5bd6dSspeer 64744961713Sgirish npi_status_t 64844961713Sgirish npi_dev_func_sr_busy(npi_handle_t handle, boolean_t *busy_p) 64944961713Sgirish { 65044961713Sgirish dev_func_sr_t sr; 65144961713Sgirish 65244961713Sgirish NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value); 65344961713Sgirish if (!sr.bits.ldw.tas) { 65444961713Sgirish sr.bits.ldw.tas = 0; 65544961713Sgirish NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); 65644961713Sgirish *busy_p = B_FALSE; 65744961713Sgirish } else { 65844961713Sgirish /* Other function already owns it */ 65944961713Sgirish *busy_p = B_TRUE; 66044961713Sgirish } 66144961713Sgirish 66244961713Sgirish return (NPI_SUCCESS); 66344961713Sgirish } 66444961713Sgirish 66544961713Sgirish /* 66644961713Sgirish * npi_dev_func_sr_tas_get(): 66744961713Sgirish * This function is called to get the tas bit 66844961713Sgirish * (after read, this bit is always set to 1, software write 0 66944961713Sgirish * to clear it). 67044961713Sgirish * 67144961713Sgirish * Parameters: 67244961713Sgirish * handle - NPI handle 67344961713Sgirish * tas_p - pointer to store the tas value 67444961713Sgirish * 67544961713Sgirish * Return: 67644961713Sgirish * NPI_SUCCESS - If tas value get is complete successfully. 67744961713Sgirish * Error: 67844961713Sgirish */ 679a3c5bd6dSspeer 68044961713Sgirish npi_status_t 68144961713Sgirish npi_dev_func_sr_tas_get(npi_handle_t handle, uint8_t *tas_p) 68244961713Sgirish { 68344961713Sgirish dev_func_sr_t sr; 68444961713Sgirish 68544961713Sgirish NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value); 68644961713Sgirish *tas_p = sr.bits.ldw.tas; 68744961713Sgirish if (!sr.bits.ldw.tas) { 68844961713Sgirish sr.bits.ldw.tas = 0; 68944961713Sgirish NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); 69044961713Sgirish 69144961713Sgirish } 69244961713Sgirish 69344961713Sgirish return (NPI_SUCCESS); 69444961713Sgirish } 69544961713Sgirish 69644961713Sgirish /* 69744961713Sgirish * npi_fzc_mpc_set(): 69844961713Sgirish * This function is called to enable the write access 69944961713Sgirish * to FZC region to function zero. 70044961713Sgirish * Parameters: 70144961713Sgirish * handle - NPI handle 70244961713Sgirish * Return: 70344961713Sgirish * NPI_SUCCESS - 70444961713Sgirish * Error: 70544961713Sgirish */ 706a3c5bd6dSspeer 70744961713Sgirish npi_status_t 70844961713Sgirish npi_fzc_mpc_set(npi_handle_t handle, boolean_t mpc) 70944961713Sgirish { 71044961713Sgirish multi_part_ctl_t mp; 71144961713Sgirish 71244961713Sgirish mp.value = 0; 71344961713Sgirish if (mpc) { 71444961713Sgirish mp.bits.ldw.mpc = 1; 71544961713Sgirish } 71644961713Sgirish NXGE_REG_WR64(handle, MULTI_PART_CTL_REG, mp.value); 71744961713Sgirish 71844961713Sgirish return (NPI_SUCCESS); 71944961713Sgirish } 72044961713Sgirish 72144961713Sgirish /* 72244961713Sgirish * npi_fzc_mpc_get(): 72344961713Sgirish * This function is called to get the access mode. 72444961713Sgirish * Parameters: 72544961713Sgirish * handle - NPI handle 72644961713Sgirish * Return: 72744961713Sgirish * NPI_SUCCESS - 72844961713Sgirish * 72944961713Sgirish */ 730a3c5bd6dSspeer 73144961713Sgirish npi_status_t 73244961713Sgirish npi_fzc_mpc_get(npi_handle_t handle, boolean_t *mpc_p) 73344961713Sgirish { 73444961713Sgirish multi_part_ctl_t mpc; 73544961713Sgirish 73644961713Sgirish mpc.value = 0; 73744961713Sgirish NXGE_REG_RD64(handle, MULTI_PART_CTL_REG, &mpc.value); 73844961713Sgirish *mpc_p = mpc.bits.ldw.mpc; 73944961713Sgirish 74044961713Sgirish return (NPI_SUCCESS); 74144961713Sgirish } 74244961713Sgirish 74344961713Sgirish /* 74444961713Sgirish * npi_fzc_dma_bind_set(): 74544961713Sgirish * This function is called to set DMA binding register. 74644961713Sgirish * Parameters: 74744961713Sgirish * handle - NPI handle 74844961713Sgirish * dma_bind - NPI defined data structure that 74944961713Sgirish * contains the tx/rx channel binding info. 75044961713Sgirish * to set. 75144961713Sgirish * Return: 75244961713Sgirish * NPI_SUCCESS - 75344961713Sgirish * Error: 75444961713Sgirish * NPI_FAILURE 75544961713Sgirish * 75644961713Sgirish */ 757a3c5bd6dSspeer 75844961713Sgirish npi_status_t 75944961713Sgirish npi_fzc_dma_bind_set(npi_handle_t handle, fzc_dma_bind_t dma_bind) 76044961713Sgirish { 76144961713Sgirish dma_bind_t bind; 76244961713Sgirish int status; 76344961713Sgirish uint8_t fn, region, id, tn, rn; 76444961713Sgirish 76544961713Sgirish fn = dma_bind.function_id; 76644961713Sgirish region = dma_bind.sub_vir_region; 76744961713Sgirish id = dma_bind.vir_index; 76844961713Sgirish tn = dma_bind.tx_channel; 76944961713Sgirish rn = dma_bind.rx_channel; 77044961713Sgirish 77144961713Sgirish DMA_BIND_VADDR_VALIDATE(fn, region, id, status); 77244961713Sgirish if (status) { 77344961713Sgirish return (status); 77444961713Sgirish } 77544961713Sgirish 77644961713Sgirish if (dma_bind.tx_bind) { 77744961713Sgirish DMA_BIND_TX_VALIDATE(tn, status); 77844961713Sgirish if (status) { 77944961713Sgirish return (status); 78044961713Sgirish } 78144961713Sgirish } 78244961713Sgirish 78344961713Sgirish if (dma_bind.rx_bind) { 78444961713Sgirish DMA_BIND_RX_VALIDATE(rn, status); 78544961713Sgirish if (status) { 78644961713Sgirish return (status); 78744961713Sgirish } 78844961713Sgirish } 78944961713Sgirish 79044961713Sgirish bind.value = 0; 79144961713Sgirish if (dma_bind.tx_bind) { 79244961713Sgirish bind.bits.ldw.tx_bind = 1; 79344961713Sgirish bind.bits.ldw.tx = tn; 79444961713Sgirish } 79544961713Sgirish if (dma_bind.rx_bind) { 79644961713Sgirish bind.bits.ldw.rx_bind = 1; 79744961713Sgirish bind.bits.ldw.rx = rn; 79844961713Sgirish } 79944961713Sgirish 80044961713Sgirish NXGE_REG_WR64(handle, DMA_BIND_REG + 801*678453a8Sspeer DMA_BIND_REG_OFFSET(fn, region, id), bind.value); 802*678453a8Sspeer 803*678453a8Sspeer return (status); 804*678453a8Sspeer } 805*678453a8Sspeer 806*678453a8Sspeer npi_status_t 807*678453a8Sspeer npi_fzc_dma_bind_get( 808*678453a8Sspeer npi_handle_t handle, 809*678453a8Sspeer fzc_dma_bind_t dma_bind, 810*678453a8Sspeer uint64_t *pValue) 811*678453a8Sspeer { 812*678453a8Sspeer uint8_t function, region, slot; 813*678453a8Sspeer int offset; 814*678453a8Sspeer int status; 815*678453a8Sspeer 816*678453a8Sspeer function = dma_bind.function_id; 817*678453a8Sspeer region = dma_bind.sub_vir_region; 818*678453a8Sspeer slot = dma_bind.vir_index; 819*678453a8Sspeer 820*678453a8Sspeer DMA_BIND_VADDR_VALIDATE(function, region, slot, status); 821*678453a8Sspeer if (status) { 822*678453a8Sspeer return (status); 823*678453a8Sspeer } 824*678453a8Sspeer 825*678453a8Sspeer offset = DMA_BIND_REG_OFFSET(function, region, slot); 826*678453a8Sspeer NXGE_REG_RD64(handle, DMA_BIND_REG + offset, pValue); 82744961713Sgirish 82844961713Sgirish return (status); 82944961713Sgirish } 83044961713Sgirish 83144961713Sgirish /* 83244961713Sgirish * npi_fzc_ldg_num_set(): 83344961713Sgirish * This function is called to set up a logical group number that 83444961713Sgirish * a logical device belongs to. 83544961713Sgirish * Parameters: 83644961713Sgirish * handle - NPI handle 83744961713Sgirish * ld - logical device number (0 - 68) 83844961713Sgirish * ldg - logical device group number (0 - 63) 83944961713Sgirish * Return: 84044961713Sgirish * NPI_SUCCESS - 84144961713Sgirish * Error: 84244961713Sgirish * NPI_FAILURE 84344961713Sgirish * 84444961713Sgirish */ 845a3c5bd6dSspeer 84644961713Sgirish npi_status_t 84744961713Sgirish npi_fzc_ldg_num_set(npi_handle_t handle, uint8_t ld, uint8_t ldg) 84844961713Sgirish { 84944961713Sgirish ldg_num_t gnum; 85044961713Sgirish 851a3c5bd6dSspeer ASSERT(LD_VALID(ld)); 85244961713Sgirish if (!LD_VALID(ld)) { 85344961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 85444961713Sgirish " npi_fzc_ldg_num_set" 85544961713Sgirish "ld <0x%x>", ld)); 85644961713Sgirish return (NPI_FAILURE | NPI_VIR_LD_INVALID(ld)); 85744961713Sgirish } 858a3c5bd6dSspeer 859a3c5bd6dSspeer ASSERT(LDG_VALID(ldg)); 86044961713Sgirish if (!LDG_VALID(ldg)) { 86144961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 86244961713Sgirish " npi_fzc_ldg_num_set" 86344961713Sgirish " ldg <0x%x>", ldg)); 86444961713Sgirish return (NPI_FAILURE | NPI_VIR_LDG_INVALID(ld)); 86544961713Sgirish } 86644961713Sgirish 86744961713Sgirish gnum.value = 0; 86844961713Sgirish gnum.bits.ldw.num = ldg; 86944961713Sgirish 87044961713Sgirish NXGE_REG_WR64(handle, LDG_NUM_REG + LD_NUM_OFFSET(ld), 87144961713Sgirish gnum.value); 87244961713Sgirish 87344961713Sgirish return (NPI_SUCCESS); 87444961713Sgirish } 87544961713Sgirish 87644961713Sgirish /* 87744961713Sgirish * npi_fzc_ldg_num_get(): 87844961713Sgirish * This function is called to get the logical device group that 87944961713Sgirish * a logical device belongs to. 88044961713Sgirish * Parameters: 88144961713Sgirish * handle - NPI handle 88244961713Sgirish * ld - logical device number (0 - 68) 88344961713Sgirish * *ldg_p - pointer to store its group number. 88444961713Sgirish * Return: 88544961713Sgirish * NPI_SUCCESS - 88644961713Sgirish * Error: 88744961713Sgirish * NPI_FAILURE 88844961713Sgirish */ 889a3c5bd6dSspeer 89044961713Sgirish npi_status_t 89144961713Sgirish npi_fzc_ldg_num_get(npi_handle_t handle, uint8_t ld, uint8_t *ldg_p) 89244961713Sgirish { 89344961713Sgirish uint64_t val; 89444961713Sgirish 895a3c5bd6dSspeer ASSERT(LD_VALID(ld)); 89644961713Sgirish if (!LD_VALID(ld)) { 89744961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 89844961713Sgirish " npi_fzc_ldg_num_get" 89944961713Sgirish " Invalid Input:", 90044961713Sgirish " ld <0x%x>", ld)); 90144961713Sgirish return (NPI_FAILURE | NPI_VIR_LD_INVALID(ld)); 90244961713Sgirish } 90344961713Sgirish 90444961713Sgirish NXGE_REG_RD64(handle, LDG_NUM_REG + LD_NUM_OFFSET(ld), &val); 90544961713Sgirish 90644961713Sgirish *ldg_p = (uint8_t)(val & LDG_NUM_NUM_MASK); 90744961713Sgirish 90844961713Sgirish return (NPI_SUCCESS); 90944961713Sgirish } 91044961713Sgirish 91144961713Sgirish /* 91244961713Sgirish * npi_ldsv_ldfs_get(): 91344961713Sgirish * This function is called to get device state vectors. 91444961713Sgirish * Parameters: 91544961713Sgirish * handle - NPI handle 91644961713Sgirish * ldg - logical device group (0 - 63) 91744961713Sgirish * *ldf_p - pointer to store ldf0 and ldf1 flag bits. 91844961713Sgirish * Return: 91944961713Sgirish * NPI_SUCCESS - 92044961713Sgirish * Error: 92144961713Sgirish * NPI_FAILURE 92244961713Sgirish */ 923a3c5bd6dSspeer 92444961713Sgirish npi_status_t 92544961713Sgirish npi_ldsv_ldfs_get(npi_handle_t handle, uint8_t ldg, uint64_t *vector0_p, 926a3c5bd6dSspeer uint64_t *vector1_p, uint64_t *vector2_p) 92744961713Sgirish { 92844961713Sgirish int status; 92944961713Sgirish 93044961713Sgirish if ((status = npi_ldsv_get(handle, ldg, VECTOR0, vector0_p))) { 93144961713Sgirish return (status); 93244961713Sgirish } 93344961713Sgirish if ((status = npi_ldsv_get(handle, ldg, VECTOR1, vector1_p))) { 93444961713Sgirish return (status); 93544961713Sgirish } 93644961713Sgirish if ((status = npi_ldsv_get(handle, ldg, VECTOR2, vector2_p))) { 93744961713Sgirish return (status); 93844961713Sgirish } 93944961713Sgirish 94044961713Sgirish return (NPI_SUCCESS); 94144961713Sgirish } 94244961713Sgirish 94344961713Sgirish /* 94444961713Sgirish * npi_ldsv_get(): 94544961713Sgirish * This function is called to get device state vectors. 94644961713Sgirish * Parameters: 94744961713Sgirish * handle - NPI handle 94844961713Sgirish * ldg - logical device group (0 - 63) 94944961713Sgirish * ldf_type - either LDF0 (0) or LDF1 (1) 95044961713Sgirish * vector - vector type (0, 1 or 2) 95144961713Sgirish * *ldf_p - pointer to store its flag bits. 95244961713Sgirish * Return: 95344961713Sgirish * NPI_SUCCESS - 95444961713Sgirish * Error: 95544961713Sgirish * NPI_FAILURE 95644961713Sgirish */ 957a3c5bd6dSspeer 95844961713Sgirish npi_status_t 95944961713Sgirish npi_ldsv_get(npi_handle_t handle, uint8_t ldg, ldsv_type_t vector, 960a3c5bd6dSspeer uint64_t *ldf_p) 96144961713Sgirish { 96244961713Sgirish uint64_t offset; 96344961713Sgirish 964a3c5bd6dSspeer ASSERT(LDG_VALID(ldg)); 96544961713Sgirish if (!LDG_VALID(ldg)) { 96644961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 96744961713Sgirish " npi_ldsv_get" 96844961713Sgirish " Invalid Input " 96944961713Sgirish " ldg <0x%x>", ldg)); 97044961713Sgirish return (NPI_FAILURE | NPI_VIR_LDG_INVALID(ldg)); 97144961713Sgirish } 97244961713Sgirish 97344961713Sgirish switch (vector) { 97444961713Sgirish case VECTOR0: 97544961713Sgirish offset = LDSV0_REG + LDSV_OFFSET(ldg); 97644961713Sgirish break; 97744961713Sgirish 97844961713Sgirish case VECTOR1: 97944961713Sgirish offset = LDSV1_REG + LDSV_OFFSET(ldg); 98044961713Sgirish break; 98144961713Sgirish 98244961713Sgirish case VECTOR2: 98344961713Sgirish offset = LDSV2_REG + LDSV_OFFSET(ldg); 98444961713Sgirish break; 98544961713Sgirish 98644961713Sgirish default: 98744961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 98844961713Sgirish " npi_ldsv_get" 98944961713Sgirish " Invalid Input: " 99044961713Sgirish " ldsv type <0x%x>", vector)); 99144961713Sgirish return (NPI_FAILURE | NPI_VIR_LDSV_INVALID(vector)); 99244961713Sgirish } 99344961713Sgirish 99444961713Sgirish NXGE_REG_RD64(handle, offset, ldf_p); 99544961713Sgirish 99644961713Sgirish return (NPI_SUCCESS); 99744961713Sgirish } 99844961713Sgirish 99944961713Sgirish /* 100044961713Sgirish * npi_ldsv_ld_get(): 100144961713Sgirish * This function is called to get the flag bit value of a device. 100244961713Sgirish * Parameters: 100344961713Sgirish * handle - NPI handle 100444961713Sgirish * ldg - logical device group (0 - 63) 100544961713Sgirish * ld - logical device (0 - 68) 100644961713Sgirish * ldf_type - either LDF0 (0) or LDF1 (1) 100744961713Sgirish * vector - vector type (0, 1 or 2) 100844961713Sgirish * *ldf_p - pointer to store its flag bits. 100944961713Sgirish * Return: 101044961713Sgirish * NPI_SUCCESS - 101144961713Sgirish * Error: 101244961713Sgirish * NPI_FAILURE 101344961713Sgirish */ 1014a3c5bd6dSspeer 101544961713Sgirish npi_status_t 101644961713Sgirish npi_ldsv_ld_get(npi_handle_t handle, uint8_t ldg, uint8_t ld, 1017a3c5bd6dSspeer ldsv_type_t vector, ldf_type_t ldf_type, boolean_t *flag_p) 101844961713Sgirish { 101944961713Sgirish uint64_t sv; 102044961713Sgirish uint64_t offset; 102144961713Sgirish 1022a3c5bd6dSspeer ASSERT(LDG_VALID(ldg)); 102344961713Sgirish if (!LDG_VALID(ldg)) { 102444961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 102544961713Sgirish " npi_ldsv_ld_get" 102644961713Sgirish " Invalid Input: " 102744961713Sgirish " ldg <0x%x>", ldg)); 102844961713Sgirish return (NPI_FAILURE | NPI_VIR_LDG_INVALID(ldg)); 102944961713Sgirish } 1030a3c5bd6dSspeer ASSERT((LD_VALID(ld)) && \ 1031a3c5bd6dSspeer ((vector != VECTOR2) || (ld >= NXGE_MAC_LD_START))); 103244961713Sgirish if (!LD_VALID(ld)) { 103344961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 103444961713Sgirish " npi_ldsv_ld_get Invalid Input: " 103544961713Sgirish " ld <9x%x>", ld)); 103644961713Sgirish return (NPI_FAILURE | NPI_VIR_LD_INVALID(ld)); 103744961713Sgirish } else if (vector == VECTOR2 && ld < NXGE_MAC_LD_START) { 103844961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 103944961713Sgirish " npi_ldsv_ld_get Invalid Input:" 104044961713Sgirish " ld-vector2 <0x%x>", ld)); 104144961713Sgirish return (NPI_FAILURE | NPI_VIR_LD_INVALID(ld)); 104244961713Sgirish } 104344961713Sgirish 104444961713Sgirish switch (vector) { 104544961713Sgirish case VECTOR0: 104644961713Sgirish offset = LDSV0_REG + LDSV_OFFSET(ldg); 104744961713Sgirish break; 104844961713Sgirish 104944961713Sgirish case VECTOR1: 105044961713Sgirish offset = LDSV1_REG + LDSV_OFFSET(ldg); 105144961713Sgirish break; 105244961713Sgirish 105344961713Sgirish case VECTOR2: 105444961713Sgirish offset = LDSV2_REG + LDSV_OFFSET(ldg); 105544961713Sgirish 105644961713Sgirish default: 105744961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, "npi_ldsv_get" 105844961713Sgirish "ldsv", vector)); 105944961713Sgirish return (NPI_FAILURE | NPI_VIR_LDSV_INVALID(vector)); 106044961713Sgirish } 106144961713Sgirish 106244961713Sgirish NXGE_REG_RD64(handle, offset, &sv); 106344961713Sgirish if (vector != VECTOR2) { 106444961713Sgirish *flag_p = ((sv >> ld) & LDSV_MASK_ALL); 106544961713Sgirish } else { 106644961713Sgirish if (ldf_type) { 106744961713Sgirish *flag_p = (((sv >> LDSV2_LDF1_SHIFT) >> 106844961713Sgirish (ld - NXGE_MAC_LD_START)) & LDSV_MASK_ALL); 106944961713Sgirish } else { 107044961713Sgirish *flag_p = (((sv >> LDSV2_LDF0_SHIFT) >> 107144961713Sgirish (ld - NXGE_MAC_LD_START)) & LDSV_MASK_ALL); 107244961713Sgirish } 107344961713Sgirish } 107444961713Sgirish 107544961713Sgirish return (NPI_SUCCESS); 107644961713Sgirish } 107744961713Sgirish 107844961713Sgirish /* 107944961713Sgirish * npi_ldsv_ld_ldf0_get(): 108044961713Sgirish * This function is called to get the ldf0 bit value of a device. 108144961713Sgirish * Parameters: 108244961713Sgirish * handle - NPI handle 108344961713Sgirish * ldg - logical device group (0 - 63) 108444961713Sgirish * ld - logical device (0 - 68) 108544961713Sgirish * *ldf_p - pointer to store its flag bits. 108644961713Sgirish * Return: 108744961713Sgirish * NPI_SUCCESS - 108844961713Sgirish * Error: 108944961713Sgirish * NPI_FAILURE 109044961713Sgirish */ 1091a3c5bd6dSspeer 109244961713Sgirish npi_status_t 109344961713Sgirish npi_ldsv_ld_ldf0_get(npi_handle_t handle, uint8_t ldg, uint8_t ld, 1094a3c5bd6dSspeer boolean_t *flag_p) 109544961713Sgirish { 109644961713Sgirish ldsv_type_t vector; 109744961713Sgirish 109844961713Sgirish if (ld >= NXGE_MAC_LD_START) { 109944961713Sgirish vector = VECTOR2; 110044961713Sgirish } 110144961713Sgirish 110244961713Sgirish return (npi_ldsv_ld_get(handle, ldg, ld, vector, LDF0, flag_p)); 110344961713Sgirish } 110444961713Sgirish 110544961713Sgirish /* 110644961713Sgirish * npi_ldsv_ld_ldf1_get(): 110744961713Sgirish * This function is called to get the ldf1 bit value of a device. 110844961713Sgirish * Parameters: 110944961713Sgirish * handle - NPI handle 111044961713Sgirish * ldg - logical device group (0 - 63) 111144961713Sgirish * ld - logical device (0 - 68) 111244961713Sgirish * *ldf_p - pointer to store its flag bits. 111344961713Sgirish * Return: 111444961713Sgirish * NPI_SUCCESS - 111544961713Sgirish * Error: 111644961713Sgirish * NPI_FAILURE 111744961713Sgirish */ 1118a3c5bd6dSspeer 111944961713Sgirish npi_status_t 112044961713Sgirish npi_ldsv_ld_ldf1_get(npi_handle_t handle, uint8_t ldg, uint8_t ld, 112144961713Sgirish boolean_t *flag_p) 112244961713Sgirish { 112344961713Sgirish ldsv_type_t vector; 112444961713Sgirish 112544961713Sgirish if (ld >= NXGE_MAC_LD_START) { 112644961713Sgirish vector = VECTOR2; 112744961713Sgirish } 112844961713Sgirish 112944961713Sgirish return (npi_ldsv_ld_get(handle, ldg, ld, vector, LDF1, flag_p)); 113044961713Sgirish } 113144961713Sgirish 113244961713Sgirish /* 113344961713Sgirish * npi_intr_mask_set(): 113444961713Sgirish * This function is called to select the mask bits for both ldf0 and ldf1. 113544961713Sgirish * Parameters: 113644961713Sgirish * handle - NPI handle 113744961713Sgirish * ld - logical device (0 - 68) 113844961713Sgirish * ldf_mask - mask value to set (both ldf0 and ldf1). 113944961713Sgirish * Return: 114044961713Sgirish * NPI_SUCCESS - 114144961713Sgirish * Error: 114244961713Sgirish * NPI_FAILURE 114344961713Sgirish */ 1144a3c5bd6dSspeer 114544961713Sgirish npi_status_t 114644961713Sgirish npi_intr_mask_set(npi_handle_t handle, uint8_t ld, uint8_t ldf_mask) 114744961713Sgirish { 114844961713Sgirish uint64_t offset; 114944961713Sgirish 1150a3c5bd6dSspeer ASSERT(LD_VALID(ld)); 115144961713Sgirish if (!LD_VALID(ld)) { 115244961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 115344961713Sgirish " npi_intr_mask_set ld", ld)); 115444961713Sgirish return (NPI_FAILURE | NPI_VIR_LD_INVALID(ld)); 115544961713Sgirish } 115644961713Sgirish 115744961713Sgirish ldf_mask &= LD_IM0_MASK; 115844961713Sgirish offset = LDSV_OFFSET_MASK(ld); 115944961713Sgirish 116044961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_VIR_CTL, 116144961713Sgirish "npi_intr_mask_set: ld %d " 116244961713Sgirish " offset 0x%0llx " 116344961713Sgirish " mask 0x%x", 116444961713Sgirish ld, offset, ldf_mask)); 116544961713Sgirish 116644961713Sgirish NXGE_REG_WR64(handle, offset, (uint64_t)ldf_mask); 116744961713Sgirish 116844961713Sgirish return (NPI_SUCCESS); 116944961713Sgirish } 117044961713Sgirish 117144961713Sgirish /* 117244961713Sgirish * npi_intr_mask_get(): 117344961713Sgirish * This function is called to get the mask bits. 117444961713Sgirish * Parameters: 117544961713Sgirish * handle - NPI handle 117644961713Sgirish * ld - logical device (0 - 68) 117744961713Sgirish * ldf_mask - pointer to store mask bits info. 117844961713Sgirish * Return: 117944961713Sgirish * NPI_SUCCESS - 118044961713Sgirish * Error: 118144961713Sgirish * NPI_FAILURE 118244961713Sgirish */ 118344961713Sgirish npi_status_t 118444961713Sgirish npi_intr_mask_get(npi_handle_t handle, uint8_t ld, uint8_t *ldf_mask_p) 118544961713Sgirish { 118644961713Sgirish uint64_t offset; 118744961713Sgirish uint64_t val; 118844961713Sgirish 1189a3c5bd6dSspeer ASSERT(LD_VALID(ld)); 119044961713Sgirish if (!LD_VALID(ld)) { 119144961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 119244961713Sgirish " npi_intr_mask_get ld", ld)); 119344961713Sgirish return (NPI_FAILURE | NPI_VIR_LD_INVALID(ld)); 119444961713Sgirish } 119544961713Sgirish 119644961713Sgirish offset = LDSV_OFFSET_MASK(ld); 119744961713Sgirish 119844961713Sgirish NXGE_REG_RD64(handle, offset, &val); 119944961713Sgirish 120044961713Sgirish *ldf_mask_p = (uint8_t)(val & LD_IM_MASK); 120144961713Sgirish 120244961713Sgirish return (NPI_SUCCESS); 120344961713Sgirish } 120444961713Sgirish 120544961713Sgirish /* 120644961713Sgirish * npi_intr_ldg_mgmt_set(): 120744961713Sgirish * This function is called to set interrupt timer and arm bit. 120844961713Sgirish * Parameters: 120944961713Sgirish * handle - NPI handle 121044961713Sgirish * ldg - logical device group (0 - 63) 121144961713Sgirish * arm - B_TRUE (arm) B_FALSE (disable) 121244961713Sgirish * Return: 121344961713Sgirish * NPI_SUCCESS - 121444961713Sgirish * Error: 121544961713Sgirish * NPI_FAILURE 121644961713Sgirish */ 1217a3c5bd6dSspeer 121844961713Sgirish npi_status_t 121944961713Sgirish npi_intr_ldg_mgmt_set(npi_handle_t handle, uint8_t ldg, boolean_t arm, 122044961713Sgirish uint8_t timer) 122144961713Sgirish { 122244961713Sgirish ldgimgm_t mgm; 122344961713Sgirish uint64_t val; 122444961713Sgirish 1225a3c5bd6dSspeer ASSERT((LDG_VALID(ldg)) && (LD_INTTIMER_VALID(timer))); 122644961713Sgirish if (!LDG_VALID(ldg)) { 122744961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 122844961713Sgirish " npi_intr_ldg_mgmt_set" 122944961713Sgirish " Invalid Input: " 123044961713Sgirish " ldg <0x%x>", ldg)); 123144961713Sgirish return (NPI_FAILURE | NPI_VIR_LDG_INVALID(ldg)); 123244961713Sgirish } 123344961713Sgirish if (!LD_INTTIMER_VALID(timer)) { 123444961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 123544961713Sgirish " npi_intr_ldg_mgmt_set Invalid Input" 123644961713Sgirish " timer <0x%x>", timer)); 123744961713Sgirish return (NPI_FAILURE | NPI_VIR_INTM_TM_INVALID(ldg)); 123844961713Sgirish } 123944961713Sgirish 124044961713Sgirish if (arm) { 124144961713Sgirish mgm.bits.ldw.arm = 1; 124244961713Sgirish } else { 124344961713Sgirish NXGE_REG_RD64(handle, LDGIMGN_REG + LDSV_OFFSET(ldg), &val); 124444961713Sgirish mgm.value = val & LDGIMGM_ARM_MASK; 124544961713Sgirish } 124644961713Sgirish 124744961713Sgirish mgm.bits.ldw.timer = timer; 124844961713Sgirish NXGE_REG_WR64(handle, LDGIMGN_REG + LDSV_OFFSET(ldg), 124944961713Sgirish mgm.value); 125044961713Sgirish 125144961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_VIR_CTL, 125244961713Sgirish " npi_intr_ldg_mgmt_set: ldg %d" 125344961713Sgirish " reg offset 0x%x", 125444961713Sgirish ldg, LDGIMGN_REG + LDSV_OFFSET(ldg))); 125544961713Sgirish 125644961713Sgirish return (NPI_SUCCESS); 125744961713Sgirish } 125844961713Sgirish 125944961713Sgirish /* 126044961713Sgirish * npi_intr_ldg_mgmt_timer_get(): 126144961713Sgirish * This function is called to get the timer counter 126244961713Sgirish * Parameters: 126344961713Sgirish * handle - NPI handle 126444961713Sgirish * ldg - logical device group (0 - 63) 126544961713Sgirish * timer_p - pointer to store the timer counter. 126644961713Sgirish * Return: 126744961713Sgirish * NPI_SUCCESS - 126844961713Sgirish * Error: 126944961713Sgirish * NPI_FAILURE 127044961713Sgirish */ 1271a3c5bd6dSspeer 127244961713Sgirish npi_status_t 127344961713Sgirish npi_intr_ldg_mgmt_timer_get(npi_handle_t handle, uint8_t ldg, uint8_t *timer_p) 127444961713Sgirish { 127544961713Sgirish uint64_t val; 127644961713Sgirish 1277a3c5bd6dSspeer ASSERT(LDG_VALID(ldg)); 127844961713Sgirish if (!LDG_VALID(ldg)) { 127944961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 128044961713Sgirish " npi_intr_ldg_mgmt_timer_get" 128144961713Sgirish " Invalid Input: ldg <0x%x>", ldg)); 128244961713Sgirish return (NPI_FAILURE | NPI_VIR_LDG_INVALID(ldg)); 128344961713Sgirish } 128444961713Sgirish 128544961713Sgirish NXGE_REG_RD64(handle, LDGIMGN_REG + LDSV_OFFSET(ldg), &val); 128644961713Sgirish 128744961713Sgirish *timer_p = (uint8_t)(val & LDGIMGM_TIMER_MASK); 128844961713Sgirish 128944961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_VIR_CTL, 129044961713Sgirish " npi_intr_ldg_mgmt_timer_get: ldg %d" 129144961713Sgirish " reg offset 0x%x", 129244961713Sgirish ldg, LDGIMGN_REG + LDSV_OFFSET(ldg))); 129344961713Sgirish 129444961713Sgirish return (NPI_SUCCESS); 129544961713Sgirish } 129644961713Sgirish 129744961713Sgirish /* 129844961713Sgirish * npi_intr_ldg_mgmt_arm(): 129944961713Sgirish * This function is called to arm the group. 130044961713Sgirish * Parameters: 130144961713Sgirish * handle - NPI handle 130244961713Sgirish * ldg - logical device group (0 - 63) 130344961713Sgirish * Return: 130444961713Sgirish * NPI_SUCCESS - 130544961713Sgirish * Error: 130644961713Sgirish * NPI_FAILURE 130744961713Sgirish */ 1308a3c5bd6dSspeer 130944961713Sgirish npi_status_t 131044961713Sgirish npi_intr_ldg_mgmt_arm(npi_handle_t handle, uint8_t ldg) 131144961713Sgirish { 131244961713Sgirish ldgimgm_t mgm; 131344961713Sgirish 1314a3c5bd6dSspeer ASSERT(LDG_VALID(ldg)); 131544961713Sgirish if (!LDG_VALID(ldg)) { 131644961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 131744961713Sgirish " npi_intr_ldg_mgmt_arm" 131844961713Sgirish " Invalid Input: ldg <0x%x>", 131944961713Sgirish ldg)); 132044961713Sgirish return (NPI_FAILURE | NPI_VIR_LDG_INVALID(ldg)); 132144961713Sgirish } 132244961713Sgirish 132344961713Sgirish NXGE_REG_RD64(handle, (LDGIMGN_REG + LDSV_OFFSET(ldg)), &mgm.value); 132444961713Sgirish mgm.bits.ldw.arm = 1; 132544961713Sgirish 132644961713Sgirish NXGE_REG_WR64(handle, LDGIMGN_REG + LDSV_OFFSET(ldg), 132744961713Sgirish mgm.value); 132844961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_VIR_CTL, 132944961713Sgirish " npi_intr_ldg_mgmt_arm: ldg %d" 133044961713Sgirish " reg offset 0x%x", 133144961713Sgirish ldg, LDGIMGN_REG + LDSV_OFFSET(ldg))); 133244961713Sgirish 133344961713Sgirish return (NPI_SUCCESS); 133444961713Sgirish } 133544961713Sgirish 133644961713Sgirish /* 133744961713Sgirish * npi_fzc_ldg_timer_res_set(): 133844961713Sgirish * This function is called to set the timer resolution. 133944961713Sgirish * Parameters: 134044961713Sgirish * handle - NPI handle 134144961713Sgirish * res - timer resolution (# of system clocks) 134244961713Sgirish * Return: 134344961713Sgirish * NPI_SUCCESS - 134444961713Sgirish * Error: 134544961713Sgirish * NPI_FAILURE 134644961713Sgirish */ 1347a3c5bd6dSspeer 134844961713Sgirish npi_status_t 134944961713Sgirish npi_fzc_ldg_timer_res_set(npi_handle_t handle, uint32_t res) 135044961713Sgirish { 1351a3c5bd6dSspeer ASSERT(res <= LDGTITMRES_RES_MASK); 135244961713Sgirish if (res > LDGTITMRES_RES_MASK) { 135344961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 135444961713Sgirish " npi_fzc_ldg_timer_res_set" 135544961713Sgirish " Invalid Input: res <0x%x>", 135644961713Sgirish res)); 135744961713Sgirish return (NPI_FAILURE | NPI_VIR_TM_RES_INVALID); 135844961713Sgirish } 135944961713Sgirish 136044961713Sgirish NXGE_REG_WR64(handle, LDGITMRES_REG, (res & LDGTITMRES_RES_MASK)); 136144961713Sgirish 136244961713Sgirish return (NPI_SUCCESS); 136344961713Sgirish } 136444961713Sgirish 136544961713Sgirish /* 136644961713Sgirish * npi_fzc_ldg_timer_res_get(): 136744961713Sgirish * This function is called to get the timer resolution. 136844961713Sgirish * Parameters: 136944961713Sgirish * handle - NPI handle 137044961713Sgirish * res_p - pointer to store the timer resolution. 137144961713Sgirish * Return: 137244961713Sgirish * NPI_SUCCESS - 137344961713Sgirish * Error: 137444961713Sgirish * NPI_FAILURE 137544961713Sgirish */ 1376a3c5bd6dSspeer 137744961713Sgirish npi_status_t 137844961713Sgirish npi_fzc_ldg_timer_res_get(npi_handle_t handle, uint8_t *res_p) 137944961713Sgirish { 138044961713Sgirish uint64_t val; 138144961713Sgirish 138244961713Sgirish NXGE_REG_RD64(handle, LDGITMRES_REG, &val); 138344961713Sgirish 138444961713Sgirish *res_p = (uint8_t)(val & LDGIMGM_TIMER_MASK); 138544961713Sgirish 138644961713Sgirish return (NPI_SUCCESS); 138744961713Sgirish } 138844961713Sgirish 138944961713Sgirish /* 139044961713Sgirish * npi_fzc_sid_set(): 139144961713Sgirish * This function is called to set the system interrupt data. 139244961713Sgirish * Parameters: 139344961713Sgirish * handle - NPI handle 139444961713Sgirish * ldg - logical group (0 - 63) 139544961713Sgirish * sid - NPI defined data to set 139644961713Sgirish * Return: 139744961713Sgirish * NPI_SUCCESS - 139844961713Sgirish * Error: 139944961713Sgirish * NPI_FAILURE 140044961713Sgirish */ 1401a3c5bd6dSspeer 140244961713Sgirish npi_status_t 140344961713Sgirish npi_fzc_sid_set(npi_handle_t handle, fzc_sid_t sid) 140444961713Sgirish { 140544961713Sgirish sid_t sd; 140644961713Sgirish 1407a3c5bd6dSspeer ASSERT(LDG_VALID(sid.ldg)); 140844961713Sgirish if (!LDG_VALID(sid.ldg)) { 140944961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 141044961713Sgirish " npi_fzc_sid_set" 141144961713Sgirish " Invalid Input: ldg <0x%x>", 141244961713Sgirish sid.ldg)); 141344961713Sgirish return (NPI_FAILURE | NPI_VIR_LDG_INVALID(sid.ldg)); 141444961713Sgirish } 141544961713Sgirish if (!sid.niu) { 1416a3c5bd6dSspeer ASSERT(FUNC_VALID(sid.func)); 141744961713Sgirish if (!FUNC_VALID(sid.func)) { 141844961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 141944961713Sgirish " npi_fzc_sid_set" 142044961713Sgirish " Invalid Input: func <0x%x>", 142144961713Sgirish sid.func)); 142244961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1423a3c5bd6dSspeer "invalid FUNC: npi_fzc_sid_set(%d)", sid.func)); 142444961713Sgirish return (NPI_FAILURE | NPI_VIR_FUNC_INVALID(sid.func)); 142544961713Sgirish } 142644961713Sgirish 1427a3c5bd6dSspeer ASSERT(SID_VECTOR_VALID(sid.vector)); 142844961713Sgirish if (!SID_VECTOR_VALID(sid.vector)) { 142944961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 143044961713Sgirish " npi_fzc_sid_set" 143144961713Sgirish " Invalid Input: vector <0x%x>", 143244961713Sgirish sid.vector)); 143344961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 143444961713Sgirish " invalid VECTOR: npi_fzc_sid_set(%d)", 143544961713Sgirish sid.vector)); 143644961713Sgirish return (NPI_FAILURE | 143744961713Sgirish NPI_VIR_SID_VEC_INVALID(sid.vector)); 143844961713Sgirish } 143944961713Sgirish } 144044961713Sgirish sd.value = 0; 144144961713Sgirish if (!sid.niu) { 144244961713Sgirish sd.bits.ldw.data = ((sid.func << SID_DATA_FUNCNUM_SHIFT) | 144344961713Sgirish (sid.vector & SID_DATA_INTNUM_MASK)); 144444961713Sgirish } 1445a3c5bd6dSspeer 144656d930aeSspeer NPI_DEBUG_MSG((handle.function, NPI_VIR_CTL, 1447a3c5bd6dSspeer " npi_fzc_sid_set: group %d 0x%llx", sid.ldg, sd.value)); 144844961713Sgirish 144944961713Sgirish NXGE_REG_WR64(handle, SID_REG + LDG_SID_OFFSET(sid.ldg), sd.value); 145044961713Sgirish 145144961713Sgirish return (NPI_SUCCESS); 145244961713Sgirish } 145344961713Sgirish 145444961713Sgirish /* 145544961713Sgirish * npi_fzc_sid_get(): 145644961713Sgirish * This function is called to get the system interrupt data. 145744961713Sgirish * Parameters: 145844961713Sgirish * handle - NPI handle 145944961713Sgirish * ldg - logical group (0 - 63) 146044961713Sgirish * sid_p - NPI defined data to get 146144961713Sgirish * Return: 146244961713Sgirish * NPI_SUCCESS - 146344961713Sgirish * Error: 146444961713Sgirish * NPI_FAILURE 146544961713Sgirish */ 1466a3c5bd6dSspeer 146744961713Sgirish npi_status_t 146844961713Sgirish npi_fzc_sid_get(npi_handle_t handle, p_fzc_sid_t sid_p) 146944961713Sgirish { 147044961713Sgirish sid_t sd; 147144961713Sgirish 1472a3c5bd6dSspeer ASSERT(LDG_VALID(sid_p->ldg)); 147344961713Sgirish if (!LDG_VALID(sid_p->ldg)) { 147444961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 147544961713Sgirish " npi_fzc_sid_get" 147644961713Sgirish " Invalid Input: ldg <0x%x>", 147744961713Sgirish sid_p->ldg)); 147844961713Sgirish return (NPI_FAILURE | NPI_VIR_LDG_INVALID(sid_p->ldg)); 147944961713Sgirish } 148044961713Sgirish NXGE_REG_RD64(handle, (SID_REG + LDG_SID_OFFSET(sid_p->ldg)), 148144961713Sgirish &sd.value); 148244961713Sgirish if (!sid_p->niu) { 148344961713Sgirish sid_p->func = ((sd.bits.ldw.data & SID_DATA_FUNCNUM_MASK) >> 148444961713Sgirish SID_DATA_FUNCNUM_SHIFT); 148544961713Sgirish sid_p->vector = ((sd.bits.ldw.data & SID_DATA_INTNUM_MASK) >> 148644961713Sgirish SID_DATA_INTNUM_SHIFT); 148744961713Sgirish } else { 148844961713Sgirish sid_p->vector = (sd.value & SID_DATA_MASK); 148944961713Sgirish } 149044961713Sgirish 149144961713Sgirish return (NPI_SUCCESS); 149244961713Sgirish } 149344961713Sgirish 149444961713Sgirish /* 149544961713Sgirish * npi_fzc_sys_err_mask_set(): 149644961713Sgirish * This function is called to mask/unmask the device error mask bits. 149744961713Sgirish * 149844961713Sgirish * Parameters: 149944961713Sgirish * handle - NPI handle 150044961713Sgirish * mask - set bit mapped mask 150144961713Sgirish * Return: 150244961713Sgirish * NPI_SUCCESS - 150344961713Sgirish * Error: 150444961713Sgirish * NPI_FAILURE 150544961713Sgirish */ 1506a3c5bd6dSspeer 150744961713Sgirish npi_status_t 150844961713Sgirish npi_fzc_sys_err_mask_set(npi_handle_t handle, uint64_t mask) 150944961713Sgirish { 151044961713Sgirish NXGE_REG_WR64(handle, SYS_ERR_MASK_REG, mask); 151144961713Sgirish return (NPI_SUCCESS); 151244961713Sgirish } 151344961713Sgirish 151444961713Sgirish /* 151544961713Sgirish * npi_fzc_sys_err_stat_get(): 151644961713Sgirish * This function is called to get the system error stats. 151744961713Sgirish * 151844961713Sgirish * Parameters: 151944961713Sgirish * handle - NPI handle 152044961713Sgirish * err_stat - sys_err_stat structure to hold stats. 152144961713Sgirish * Return: 152244961713Sgirish * NPI_SUCCESS - 152344961713Sgirish * Error: 152444961713Sgirish * NPI_FAILURE 152544961713Sgirish */ 1526a3c5bd6dSspeer 152744961713Sgirish npi_status_t 152844961713Sgirish npi_fzc_sys_err_stat_get(npi_handle_t handle, p_sys_err_stat_t statp) 152944961713Sgirish { 153044961713Sgirish NXGE_REG_RD64(handle, SYS_ERR_STAT_REG, &statp->value); 153144961713Sgirish return (NPI_SUCCESS); 153244961713Sgirish } 153344961713Sgirish 153444961713Sgirish npi_status_t 153544961713Sgirish npi_fzc_rst_ctl_get(npi_handle_t handle, p_rst_ctl_t rstp) 153644961713Sgirish { 153744961713Sgirish NXGE_REG_RD64(handle, RST_CTL_REG, &rstp->value); 153844961713Sgirish 153944961713Sgirish return (NPI_SUCCESS); 154044961713Sgirish } 154144961713Sgirish 154244961713Sgirish /* 154344961713Sgirish * npi_fzc_mpc_get(): 154444961713Sgirish * This function is called to get the access mode. 154544961713Sgirish * Parameters: 154644961713Sgirish * handle - NPI handle 154744961713Sgirish * Return: 154844961713Sgirish * NPI_SUCCESS - 154944961713Sgirish * 155044961713Sgirish */ 1551a3c5bd6dSspeer 155244961713Sgirish npi_status_t 155344961713Sgirish npi_fzc_rst_ctl_reset_mac(npi_handle_t handle, uint8_t port) 155444961713Sgirish { 155544961713Sgirish rst_ctl_t rst; 155644961713Sgirish 155744961713Sgirish rst.value = 0; 155844961713Sgirish NXGE_REG_RD64(handle, RST_CTL_REG, &rst.value); 155944961713Sgirish rst.value |= (1 << (RST_CTL_MAC_RST0_SHIFT + port)); 156044961713Sgirish NXGE_REG_WR64(handle, RST_CTL_REG, rst.value); 156144961713Sgirish 156244961713Sgirish return (NPI_SUCCESS); 156344961713Sgirish } 1564