xref: /illumos-gate/usr/src/uts/common/io/nxge/npi/npi_txc.h (revision 6f45ec7b)
144961713Sgirish /*
244961713Sgirish  * CDDL HEADER START
344961713Sgirish  *
444961713Sgirish  * The contents of this file are subject to the terms of the
544961713Sgirish  * Common Development and Distribution License (the "License").
644961713Sgirish  * You may not use this file except in compliance with the License.
744961713Sgirish  *
844961713Sgirish  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
944961713Sgirish  * or http://www.opensolaris.org/os/licensing.
1044961713Sgirish  * See the License for the specific language governing permissions
1144961713Sgirish  * and limitations under the License.
1244961713Sgirish  *
1344961713Sgirish  * When distributing Covered Code, include this CDDL HEADER in each
1444961713Sgirish  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1544961713Sgirish  * If applicable, add the following below this CDDL HEADER, with the
1644961713Sgirish  * fields enclosed by brackets "[]" replaced with your own identifying
1744961713Sgirish  * information: Portions Copyright [yyyy] [name of copyright owner]
1844961713Sgirish  *
1944961713Sgirish  * CDDL HEADER END
2044961713Sgirish  */
2144961713Sgirish /*
2244961713Sgirish  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
2344961713Sgirish  * Use is subject to license terms.
2444961713Sgirish  */
2544961713Sgirish 
2644961713Sgirish #ifndef _NPI_TXC_H
2744961713Sgirish #define	_NPI_TXC_H
2844961713Sgirish 
2944961713Sgirish #pragma ident	"%Z%%M%	%I%	%E% SMI"
3044961713Sgirish 
3144961713Sgirish #ifdef	__cplusplus
3244961713Sgirish extern "C" {
3344961713Sgirish #endif
3444961713Sgirish 
3544961713Sgirish #include <npi.h>
3644961713Sgirish #include <nxge_txc_hw.h>
3744961713Sgirish 
3844961713Sgirish /*
3944961713Sgirish  * Transmit Controller (TXC) NPI error codes
4044961713Sgirish  */
4144961713Sgirish #define	TXC_ER_ST			(TXC_BLK_ID << NPI_BLOCK_ID_SHIFT)
4244961713Sgirish #define	TXC_ID_SHIFT(n)			(n << NPI_PORT_CHAN_SHIFT)
4344961713Sgirish 
4444961713Sgirish #define	NPI_TXC_PORT_INVALID(n)		(TXC_ID_SHIFT(n) | IS_PORT |\
4544961713Sgirish 					TXC_ER_ST | PORT_INVALID)
4644961713Sgirish 
4744961713Sgirish #define	NPI_TXC_CHANNEL_INVALID(n)	(TXC_ID_SHIFT(n) | IS_PORT |\
4844961713Sgirish 					TXC_ER_ST | CHANNEL_INVALID)
4944961713Sgirish 
5044961713Sgirish #define	NPI_TXC_OPCODE_INVALID(n)	(TXC_ID_SHIFT(n) | IS_PORT |\
5144961713Sgirish 					TXC_ER_ST | OPCODE_INVALID)
5244961713Sgirish 
5344961713Sgirish /*
5444961713Sgirish  * Register offset (0x1000 bytes for each channel) for TXC registers.
5544961713Sgirish  */
5644961713Sgirish #define	NXGE_TXC_FZC_OFFSET(x, cn)	(x + TXC_FZC_CHANNEL_OFFSET(cn))
5744961713Sgirish 
5844961713Sgirish /*
5944961713Sgirish  * Register offset (0x100 bytes for each port) for TXC Function zero
6044961713Sgirish  * control registers.
6144961713Sgirish  */
6244961713Sgirish #define	NXGE_TXC_FZC_CNTL_OFFSET(x, port) (x + \
6344961713Sgirish 			TXC_FZC_CNTL_PORT_OFFSET(port))
6444961713Sgirish /*
6544961713Sgirish  * PIO macros to read and write the transmit control registers.
6644961713Sgirish  */
6744961713Sgirish #define	TXC_FZC_REG_READ64(handle, reg, cn, val_p)	\
6844961713Sgirish 		NXGE_REG_RD64(handle, \
6944961713Sgirish 		(NXGE_TXC_FZC_OFFSET(reg, cn)), val_p)
7044961713Sgirish 
7144961713Sgirish #define	TXC_FZC_REG_WRITE64(handle, reg, cn, data)	\
7244961713Sgirish 		NXGE_REG_WR64(handle, \
7344961713Sgirish 		(NXGE_TXC_FZC_OFFSET(reg, cn)), data)
7444961713Sgirish 
7544961713Sgirish #define	TXC_FZC_CNTL_REG_READ64(handle, reg, port, val_p)	\
7644961713Sgirish 		NXGE_REG_RD64(handle, \
7744961713Sgirish 		(NXGE_TXC_FZC_CNTL_OFFSET(reg, port)), val_p)
7844961713Sgirish 
7944961713Sgirish #define	TXC_FZC_CNTL_REG_WRITE64(handle, reg, port, data)	\
8044961713Sgirish 		NXGE_REG_WR64(handle, \
8144961713Sgirish 		(NXGE_TXC_FZC_CNTL_OFFSET(reg, port)), data)
8244961713Sgirish 
8344961713Sgirish /*
8444961713Sgirish  * TXC (Transmit Controller) prototypes.
8544961713Sgirish  */
8644961713Sgirish npi_status_t npi_txc_dma_max_burst(npi_handle_t, io_op_t,
8744961713Sgirish 		uint8_t, uint32_t *);
8844961713Sgirish npi_status_t npi_txc_dma_max_burst_set(npi_handle_t, uint8_t,
8944961713Sgirish 		uint32_t);
9044961713Sgirish npi_status_t npi_txc_dma_bytes_transmitted(npi_handle_t,
9144961713Sgirish 		uint8_t, uint32_t *);
9244961713Sgirish npi_status_t npi_txc_control(npi_handle_t, io_op_t,
9344961713Sgirish 		p_txc_control_t);
9444961713Sgirish npi_status_t npi_txc_global_enable(npi_handle_t);
9544961713Sgirish npi_status_t npi_txc_global_disable(npi_handle_t);
9644961713Sgirish npi_status_t npi_txc_control_clear(npi_handle_t, uint8_t);
9744961713Sgirish npi_status_t npi_txc_training_set(npi_handle_t, uint32_t);
9844961713Sgirish npi_status_t npi_txc_training_get(npi_handle_t, uint32_t *);
9944961713Sgirish npi_status_t npi_txc_port_control_get(npi_handle_t, uint8_t,
10044961713Sgirish 		uint32_t *);
10144961713Sgirish npi_status_t npi_txc_port_enable(npi_handle_t, uint8_t);
10244961713Sgirish npi_status_t npi_txc_port_disable(npi_handle_t, uint8_t);
10344961713Sgirish npi_status_t npi_txc_dma_max_burst(npi_handle_t, io_op_t,
10444961713Sgirish 		uint8_t, uint32_t *);
10544961713Sgirish npi_status_t npi_txc_port_dma_enable(npi_handle_t, uint8_t,
10644961713Sgirish 		uint32_t);
10744961713Sgirish npi_status_t npi_txc_port_dma_list_get(npi_handle_t, uint8_t,
10844961713Sgirish 		uint32_t *);
10944961713Sgirish npi_status_t npi_txc_port_dma_channel_enable(npi_handle_t, uint8_t,
11044961713Sgirish 		uint8_t);
11144961713Sgirish npi_status_t npi_txc_port_dma_channel_disable(npi_handle_t, uint8_t,
11244961713Sgirish 		uint8_t);
11344961713Sgirish 
11444961713Sgirish npi_status_t npi_txc_pkt_stuffed_get(npi_handle_t, uint8_t,
11544961713Sgirish 		uint32_t *, uint32_t *);
11644961713Sgirish npi_status_t npi_txc_pkt_xmt_to_mac_get(npi_handle_t, uint8_t,
11744961713Sgirish 		uint32_t *, uint32_t *);
11844961713Sgirish npi_status_t npi_txc_reorder_get(npi_handle_t, uint8_t,
11944961713Sgirish 		uint32_t *);
12044961713Sgirish npi_status_t npi_txc_dump_tdc_fzc_regs(npi_handle_t, uint8_t);
12144961713Sgirish npi_status_t npi_txc_dump_fzc_regs(npi_handle_t);
12244961713Sgirish npi_status_t npi_txc_dump_port_fzc_regs(npi_handle_t, uint8_t);
12344961713Sgirish npi_status_t npi_txc_ro_states_get(npi_handle_t, uint8_t,
12444961713Sgirish 		txc_ro_states_t *);
12544961713Sgirish npi_status_t npi_txc_ro_ecc_state_clr(npi_handle_t, uint8_t);
12644961713Sgirish npi_status_t npi_txc_sf_states_get(npi_handle_t, uint8_t,
12744961713Sgirish 		txc_sf_states_t *);
12844961713Sgirish npi_status_t npi_txc_sf_ecc_state_clr(npi_handle_t, uint8_t);
12944961713Sgirish void npi_txc_global_istatus_get(npi_handle_t, txc_int_stat_t *);
13044961713Sgirish void npi_txc_global_istatus_clear(npi_handle_t, uint64_t);
13144961713Sgirish void npi_txc_global_imask_set(npi_handle_t, uint8_t,
13244961713Sgirish 		uint8_t);
13344961713Sgirish 
13444961713Sgirish #ifdef	__cplusplus
13544961713Sgirish }
13644961713Sgirish #endif
13744961713Sgirish 
13844961713Sgirish #endif	/* _NPI_TXC_H */
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