1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _NPI_TX_RD64_H 27 #define _NPI_TX_RD64_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <npi.h> 36 37 static void TXDMA_REG_READ64(npi_handle_t, uint64_t, int, uint64_t *); 38 #pragma inline(TXDMA_REG_READ64) 39 40 /* 41 * TXDMA_REG_READ64 42 * 43 * Read a 64-bit value from a DMC register. 44 * 45 * Arguments: 46 * handle The NPI handle to use. 47 * offset The offset into the DMA CSR (the register). 48 * channel The channel, which is used as a multiplicand. 49 * value Where to put the 64-bit value to be read. 50 * 51 * Notes: 52 * For reference, here is the old macro: 53 * 54 * #define TXDMA_REG_READ64(handle, reg, channel, val_p) \ 55 * NXGE_REG_RD64(handle, \ 56 * (NXGE_TXDMA_OFFSET(reg, handle.is_vraddr, channel)), val_p) 57 * 58 * If handle.regp is a virtual address (the address of a VR), 59 * we have to subtract the value DMC right off the bat. DMC 60 * is defined as 0x600000, which works in a non-virtual address 61 * space, but not in a VR. In a VR, a DMA CSR's space begins 62 * at zero (0). So, since every call to RXMDA_REG_READ64 uses 63 * a register macro which adds in DMC, we have to subtract it. 64 * 65 * The rest of it is pretty straighforward. In a VR, a channel is 66 * logical, not absolute; and every DMA CSR is 512 bytes big; 67 * furthermore, a subpage of a VR is always ordered with the 68 * transmit CSRs first, followed by the receive CSRs. That is, 69 * a 512 byte space of Tx CSRs, followed by a 512 byte space of 70 * Rx CSRs. Hence this calculation: 71 * 72 * offset += ((channel << 1) << DMA_CSR_SLL); 73 * 74 * Here's an example: 75 * 76 * TXDMA_REG_READ64(handle, TX_CS_REG, channel, &value); 77 * Let's say channel is 3 78 * #define TX_CS_REG (DMC + 0x40028) 79 * offset = 0x640028 80 * offset &= 0xff = 0x28 81 * offset += ((3 << 1) << 9) 82 * 3 << 1 = 6 83 * 6 << 9 = 0xc00 84 * offset += 0xc00 = 0xc28 85 * 86 * Therefore, our register's (virtual) PIO address is 0xc28. 87 * 88 * cf. Table 10-6 on page 181 of the Neptune PRM, v 1.4: 89 * 90 * C00 - dFF CSRs for bound logical transmit DMA channel 3. 91 * 92 * In a non-virtual environment, you simply multiply the absolute 93 * channel number by 512 bytes, and get the correct offset to 94 * the register you're looking for. That is, the RX_DMA_CTL_STAT CSR, 95 * is, as are all of these registers, in a table where each channel 96 * is offset 512 bytes from the previous channel (count 16 step 512). 97 * 98 * offset += (channel << DMA_CSR_SLL); // channel<<9 = channel*512 99 * 100 * Here's an example: 101 * 102 * TXDMA_REG_READ64(handle, TX_CS_REG, channel, &value); 103 * Let's say channel is 3 104 * #define TX_CS_REG (DMC + 0x40028) 105 * offset = 0x640028 106 * offset += (3 << 9) 107 * 3 << 9 = 0x600 108 * offset += 0x600 = 0x640628 109 * 110 * Therefore, our register's PIO address is 0x640628. 111 * 112 * cf. Table 13-15 on page 265 of the Neptune PRM, v 1.4: 113 * TX_CS (DMC + 4002816) (count 24 step 0x200) 114 * 115 * Context: 116 * Any domain 117 * 118 */ 119 extern const char *nxge_tx2str(int); 120 121 void 122 TXDMA_REG_READ64( 123 npi_handle_t handle, 124 uint64_t offset, 125 int channel, 126 uint64_t *value) 127 { 128 #if defined(NPI_REG_TRACE) 129 const char *name = nxge_tx2str((int)offset); 130 #endif 131 if (handle.is_vraddr) { 132 offset &= DMA_CSR_MASK; 133 offset += ((channel << 1) << DMA_CSR_SLL); 134 } else { 135 offset += (channel << DMA_CSR_SLL); 136 } 137 138 #if defined(__i386) 139 *value = ddi_get64(handle.regh, 140 (uint64_t *)(handle.regp + (uint32_t)offset)); 141 #else 142 *value = ddi_get64(handle.regh, (uint64_t *)(handle.regp + offset)); 143 #endif 144 145 #if defined(NPI_REG_TRACE) 146 npi_trace_update(handle, B_FALSE, &npi_rtracebuf, 147 name, (uint32_t)offset, *value); 148 #elif defined(REG_SHOW) 149 /* 150 * Since we don't have a valid RTBUF index to show, send 0xBADBAD. 151 */ 152 rt_show_reg(0xbadbad, B_FALSE, (uint32_t)offset, *value); 153 #endif 154 } 155 156 #ifdef __cplusplus 157 } 158 #endif 159 160 #endif /* _NPI_TX_RD64_H */ 161