144961713Sgirish /*
244961713Sgirish * CDDL HEADER START
344961713Sgirish *
444961713Sgirish * The contents of this file are subject to the terms of the
544961713Sgirish * Common Development and Distribution License (the "License").
644961713Sgirish * You may not use this file except in compliance with the License.
744961713Sgirish *
844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
944961713Sgirish * or http://www.opensolaris.org/os/licensing.
1044961713Sgirish * See the License for the specific language governing permissions
1144961713Sgirish * and limitations under the License.
1244961713Sgirish *
1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each
1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the
1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying
1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner]
1844961713Sgirish *
1944961713Sgirish * CDDL HEADER END
2044961713Sgirish */
2144961713Sgirish /*
224df55fdeSJanie Lu * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
2344961713Sgirish * Use is subject to license terms.
2444961713Sgirish */
2544961713Sgirish
2644961713Sgirish #include <npi_rxdma.h>
27678453a8Sspeer #include <npi_rx_rd64.h>
28678453a8Sspeer #include <npi_rx_wr64.h>
2944961713Sgirish #include <nxge_common.h>
3044961713Sgirish
3144961713Sgirish #define RXDMA_RESET_TRY_COUNT 4
3244961713Sgirish #define RXDMA_RESET_DELAY 5
3344961713Sgirish
3444961713Sgirish #define RXDMA_OP_DISABLE 0
3544961713Sgirish #define RXDMA_OP_ENABLE 1
3644961713Sgirish #define RXDMA_OP_RESET 2
3744961713Sgirish
3844961713Sgirish #define RCR_TIMEOUT_ENABLE 1
3944961713Sgirish #define RCR_TIMEOUT_DISABLE 2
4044961713Sgirish #define RCR_THRESHOLD 4
4144961713Sgirish
42a3c5bd6dSspeer /* assume weight is in byte frames unit */
43a3c5bd6dSspeer #define WEIGHT_FACTOR 3/2
4444961713Sgirish
4544961713Sgirish uint64_t rdc_dmc_offset[] = {
4644961713Sgirish RXDMA_CFIG1_REG, RXDMA_CFIG2_REG, RBR_CFIG_A_REG, RBR_CFIG_B_REG,
4744961713Sgirish RBR_KICK_REG, RBR_STAT_REG, RBR_HDH_REG, RBR_HDL_REG,
4844961713Sgirish RCRCFIG_A_REG, RCRCFIG_B_REG, RCRSTAT_A_REG, RCRSTAT_B_REG,
4944961713Sgirish RCRSTAT_C_REG, RX_DMA_ENT_MSK_REG, RX_DMA_CTL_STAT_REG, RCR_FLSH_REG,
5044961713Sgirish RXMISC_DISCARD_REG
5144961713Sgirish };
5244961713Sgirish
5344961713Sgirish const char *rdc_dmc_name[] = {
5444961713Sgirish "RXDMA_CFIG1", "RXDMA_CFIG2", "RBR_CFIG_A", "RBR_CFIG_B",
5544961713Sgirish "RBR_KICK", "RBR_STAT", "RBR_HDH", "RBR_HDL",
5644961713Sgirish "RCRCFIG_A", "RCRCFIG_B", "RCRSTAT_A", "RCRSTAT_B",
5744961713Sgirish "RCRSTAT_C", "RX_DMA_ENT_MSK", "RX_DMA_CTL_STAT", "RCR_FLSH",
5844961713Sgirish "RXMISC_DISCARD"
5944961713Sgirish };
6044961713Sgirish
6144961713Sgirish uint64_t rdc_fzc_offset [] = {
6244961713Sgirish RX_LOG_PAGE_VLD_REG, RX_LOG_PAGE_MASK1_REG, RX_LOG_PAGE_VAL1_REG,
6344961713Sgirish RX_LOG_PAGE_MASK2_REG, RX_LOG_PAGE_VAL2_REG, RX_LOG_PAGE_RELO1_REG,
6444961713Sgirish RX_LOG_PAGE_RELO2_REG, RX_LOG_PAGE_HDL_REG, RDC_RED_PARA_REG,
6544961713Sgirish RED_DIS_CNT_REG
6644961713Sgirish };
6744961713Sgirish
6844961713Sgirish
6944961713Sgirish const char *rdc_fzc_name [] = {
7044961713Sgirish "RX_LOG_PAGE_VLD", "RX_LOG_PAGE_MASK1", "RX_LOG_PAGE_VAL1",
7144961713Sgirish "RX_LOG_PAGE_MASK2", "RX_LOG_PAGE_VAL2", "RX_LOG_PAGE_RELO1",
7244961713Sgirish "RX_LOG_PAGE_RELO2", "RX_LOG_PAGE_HDL", "RDC_RED_PARA", "RED_DIS_CNT"
7344961713Sgirish };
7444961713Sgirish
7544961713Sgirish
7644961713Sgirish /*
7744961713Sgirish * Dump the MEM_ADD register first so all the data registers
7844961713Sgirish * will have valid data buffer pointers.
7944961713Sgirish */
8044961713Sgirish uint64_t rx_fzc_offset[] = {
8144961713Sgirish RX_DMA_CK_DIV_REG, DEF_PT0_RDC_REG, DEF_PT1_RDC_REG, DEF_PT2_RDC_REG,
8244961713Sgirish DEF_PT3_RDC_REG, RX_ADDR_MD_REG, PT_DRR_WT0_REG, PT_DRR_WT1_REG,
8344961713Sgirish PT_DRR_WT2_REG, PT_DRR_WT3_REG, PT_USE0_REG, PT_USE1_REG,
8444961713Sgirish PT_USE2_REG, PT_USE3_REG, RED_RAN_INIT_REG, RX_ADDR_MD_REG,
8544961713Sgirish RDMC_PRE_PAR_ERR_REG, RDMC_SHA_PAR_ERR_REG,
8644961713Sgirish RDMC_MEM_DATA4_REG, RDMC_MEM_DATA3_REG, RDMC_MEM_DATA2_REG,
8744961713Sgirish RDMC_MEM_DATA1_REG, RDMC_MEM_DATA0_REG,
8844961713Sgirish RDMC_MEM_ADDR_REG,
8944961713Sgirish RX_CTL_DAT_FIFO_STAT_REG, RX_CTL_DAT_FIFO_MASK_REG,
9044961713Sgirish RX_CTL_DAT_FIFO_STAT_DBG_REG,
9144961713Sgirish RDMC_TRAINING_VECTOR_REG,
9244961713Sgirish };
9344961713Sgirish
9444961713Sgirish
9544961713Sgirish const char *rx_fzc_name[] = {
9644961713Sgirish "RX_DMA_CK_DIV", "DEF_PT0_RDC", "DEF_PT1_RDC", "DEF_PT2_RDC",
9744961713Sgirish "DEF_PT3_RDC", "RX_ADDR_MD", "PT_DRR_WT0", "PT_DRR_WT1",
9844961713Sgirish "PT_DRR_WT2", "PT_DRR_WT3", "PT_USE0", "PT_USE1",
9944961713Sgirish "PT_USE2", "PT_USE3", "RED_RAN_INIT", "RX_ADDR_MD",
10044961713Sgirish "RDMC_PRE_PAR_ERR", "RDMC_SHA_PAR_ERR",
10144961713Sgirish "RDMC_MEM_DATA4", "RDMC_MEM_DATA3", "RDMC_MEM_DATA2",
10244961713Sgirish "RDMC_MEM_DATA1", "RDMC_MEM_DATA0",
10344961713Sgirish "RDMC_MEM_ADDR",
10444961713Sgirish "RX_CTL_DAT_FIFO_STAT", "RX_CTL_DAT_FIFO_MASK",
10544961713Sgirish "RDMC_TRAINING_VECTOR_REG",
10644961713Sgirish "RX_CTL_DAT_FIFO_STAT_DBG_REG"
10744961713Sgirish };
10844961713Sgirish
10944961713Sgirish
11044961713Sgirish npi_status_t
11144961713Sgirish npi_rxdma_cfg_rdc_ctl(npi_handle_t handle, uint8_t rdc, uint8_t op);
11244961713Sgirish npi_status_t
11344961713Sgirish npi_rxdma_cfg_rdc_rcr_ctl(npi_handle_t handle, uint8_t rdc, uint8_t op,
11444961713Sgirish uint16_t param);
11544961713Sgirish
11644961713Sgirish
11744961713Sgirish /*
11844961713Sgirish * npi_rxdma_dump_rdc_regs
11944961713Sgirish * Dumps the contents of rdc csrs and fzc registers
12044961713Sgirish *
12144961713Sgirish * Input:
122a3c5bd6dSspeer * handle: opaque handle interpreted by the underlying OS
12344961713Sgirish * rdc: RX DMA number
12444961713Sgirish *
12544961713Sgirish * return:
12644961713Sgirish * NPI_SUCCESS
12744961713Sgirish * NPI_RXDMA_RDC_INVALID
12844961713Sgirish *
12944961713Sgirish */
13044961713Sgirish npi_status_t
npi_rxdma_dump_rdc_regs(npi_handle_t handle,uint8_t rdc)13144961713Sgirish npi_rxdma_dump_rdc_regs(npi_handle_t handle, uint8_t rdc)
13244961713Sgirish {
13344961713Sgirish
13444961713Sgirish uint64_t value, offset;
13544961713Sgirish int num_regs, i;
13644961713Sgirish #ifdef NPI_DEBUG
13744961713Sgirish extern uint64_t npi_debug_level;
13844961713Sgirish uint64_t old_npi_debug_level = npi_debug_level;
13944961713Sgirish #endif
140a3c5bd6dSspeer ASSERT(RXDMA_CHANNEL_VALID(rdc));
14144961713Sgirish if (!RXDMA_CHANNEL_VALID(rdc)) {
14244961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
14352ccf843Smisaki "npi_rxdma_dump_rdc_regs"
14452ccf843Smisaki " Illegal RDC number %d \n",
14552ccf843Smisaki rdc));
14644961713Sgirish return (NPI_RXDMA_RDC_INVALID);
14744961713Sgirish }
14844961713Sgirish #ifdef NPI_DEBUG
14944961713Sgirish npi_debug_level |= DUMP_ALWAYS;
15044961713Sgirish #endif
15144961713Sgirish num_regs = sizeof (rdc_dmc_offset) / sizeof (uint64_t);
15244961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
15352ccf843Smisaki "\nDMC Register Dump for Channel %d\n",
15452ccf843Smisaki rdc));
15544961713Sgirish for (i = 0; i < num_regs; i++) {
15644961713Sgirish RXDMA_REG_READ64(handle, rdc_dmc_offset[i], rdc, &value);
15744961713Sgirish offset = NXGE_RXDMA_OFFSET(rdc_dmc_offset[i], handle.is_vraddr,
15852ccf843Smisaki rdc);
15944961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
16052ccf843Smisaki "%08llx %s\t %08llx \n",
16152ccf843Smisaki offset, rdc_dmc_name[i], value));
16244961713Sgirish }
16344961713Sgirish
16444961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
16552ccf843Smisaki "\n Register Dump for Channel %d done\n",
16652ccf843Smisaki rdc));
16744961713Sgirish #ifdef NPI_DEBUG
16844961713Sgirish npi_debug_level = old_npi_debug_level;
16944961713Sgirish #endif
17044961713Sgirish return (NPI_SUCCESS);
17144961713Sgirish }
17244961713Sgirish
17344961713Sgirish /*
17444961713Sgirish * npi_rxdma_dump_fzc_regs
17544961713Sgirish * Dumps the contents of rdc csrs and fzc registers
17644961713Sgirish *
17744961713Sgirish * Input:
178a3c5bd6dSspeer * handle: opaque handle interpreted by the underlying OS
17944961713Sgirish *
18044961713Sgirish * return:
18144961713Sgirish * NPI_SUCCESS
18244961713Sgirish */
18344961713Sgirish npi_status_t
npi_rxdma_dump_fzc_regs(npi_handle_t handle)18444961713Sgirish npi_rxdma_dump_fzc_regs(npi_handle_t handle)
18544961713Sgirish {
18644961713Sgirish
18744961713Sgirish uint64_t value;
18844961713Sgirish int num_regs, i;
18944961713Sgirish
19044961713Sgirish
19144961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
19252ccf843Smisaki "\nFZC_DMC Common Register Dump\n"));
19344961713Sgirish num_regs = sizeof (rx_fzc_offset) / sizeof (uint64_t);
19444961713Sgirish
19544961713Sgirish for (i = 0; i < num_regs; i++) {
19644961713Sgirish NXGE_REG_RD64(handle, rx_fzc_offset[i], &value);
19744961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
19852ccf843Smisaki "0x%08llx %s\t 0x%08llx \n",
19952ccf843Smisaki rx_fzc_offset[i],
20052ccf843Smisaki rx_fzc_name[i], value));
20144961713Sgirish }
20244961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
20352ccf843Smisaki "\n FZC_DMC Register Dump Done \n"));
20444961713Sgirish
20544961713Sgirish return (NPI_SUCCESS);
20644961713Sgirish }
20744961713Sgirish
20844961713Sgirish
20944961713Sgirish
210a3c5bd6dSspeer /*
211a3c5bd6dSspeer * per rdc config functions
212a3c5bd6dSspeer */
21344961713Sgirish npi_status_t
npi_rxdma_cfg_logical_page_disable(npi_handle_t handle,uint8_t rdc,uint8_t page_num)21444961713Sgirish npi_rxdma_cfg_logical_page_disable(npi_handle_t handle, uint8_t rdc,
21544961713Sgirish uint8_t page_num)
21644961713Sgirish {
21744961713Sgirish log_page_vld_t page_vld;
21844961713Sgirish uint64_t valid_offset;
21944961713Sgirish
220a3c5bd6dSspeer ASSERT(RXDMA_CHANNEL_VALID(rdc));
22144961713Sgirish if (!RXDMA_CHANNEL_VALID(rdc)) {
22244961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
22352ccf843Smisaki "rxdma_cfg_logical_page_disable"
22452ccf843Smisaki " Illegal RDC number %d \n",
22552ccf843Smisaki rdc));
22644961713Sgirish return (NPI_RXDMA_RDC_INVALID);
22744961713Sgirish }
22844961713Sgirish
229a3c5bd6dSspeer ASSERT(RXDMA_PAGE_VALID(page_num));
23044961713Sgirish if (!RXDMA_PAGE_VALID(page_num)) {
23144961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
23252ccf843Smisaki "rxdma_cfg_logical_page_disable"
23352ccf843Smisaki " Illegal page number %d \n",
23452ccf843Smisaki page_num));
23544961713Sgirish return (NPI_RXDMA_PAGE_INVALID);
23644961713Sgirish }
23744961713Sgirish
23844961713Sgirish valid_offset = REG_FZC_RDC_OFFSET(RX_LOG_PAGE_VLD_REG, rdc);
23944961713Sgirish NXGE_REG_RD64(handle, valid_offset, &page_vld.value);
24044961713Sgirish
24144961713Sgirish if (page_num == 0)
24244961713Sgirish page_vld.bits.ldw.page0 = 0;
24344961713Sgirish
24444961713Sgirish if (page_num == 1)
24544961713Sgirish page_vld.bits.ldw.page1 = 0;
24644961713Sgirish
24744961713Sgirish NXGE_REG_WR64(handle, valid_offset, page_vld.value);
24844961713Sgirish return (NPI_SUCCESS);
24944961713Sgirish
25044961713Sgirish }
25144961713Sgirish
25244961713Sgirish npi_status_t
npi_rxdma_cfg_logical_page(npi_handle_t handle,uint8_t rdc,dma_log_page_t * pg_cfg)25344961713Sgirish npi_rxdma_cfg_logical_page(npi_handle_t handle, uint8_t rdc,
25444961713Sgirish dma_log_page_t *pg_cfg)
25544961713Sgirish {
25644961713Sgirish log_page_vld_t page_vld;
25744961713Sgirish log_page_mask_t page_mask;
25844961713Sgirish log_page_value_t page_value;
25944961713Sgirish log_page_relo_t page_reloc;
26044961713Sgirish uint64_t value_offset, reloc_offset, mask_offset;
26144961713Sgirish uint64_t valid_offset;
26244961713Sgirish
263e3d11eeeSToomas Soome value_offset = 0;
264e3d11eeeSToomas Soome reloc_offset = 0;
265e3d11eeeSToomas Soome mask_offset = 0;
266a3c5bd6dSspeer ASSERT(RXDMA_CHANNEL_VALID(rdc));
26744961713Sgirish if (!RXDMA_CHANNEL_VALID(rdc)) {
26844961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
26952ccf843Smisaki " rxdma_cfg_logical_page"
27052ccf843Smisaki " Illegal RDC number %d \n",
27152ccf843Smisaki rdc));
27244961713Sgirish return (NPI_RXDMA_RDC_INVALID);
27344961713Sgirish }
27444961713Sgirish
275a3c5bd6dSspeer ASSERT(RXDMA_PAGE_VALID(pg_cfg->page_num));
27644961713Sgirish if (!RXDMA_PAGE_VALID(pg_cfg->page_num)) {
27744961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
27852ccf843Smisaki " rxdma_cfg_logical_page"
27952ccf843Smisaki " Illegal page number %d \n",
28052ccf843Smisaki pg_cfg->page_num));
28144961713Sgirish return (NPI_RXDMA_PAGE_INVALID);
28244961713Sgirish }
28344961713Sgirish
28444961713Sgirish valid_offset = REG_FZC_RDC_OFFSET(RX_LOG_PAGE_VLD_REG, rdc);
28544961713Sgirish NXGE_REG_RD64(handle, valid_offset, &page_vld.value);
28644961713Sgirish
287a3c5bd6dSspeer if (!pg_cfg->valid) {
28844961713Sgirish if (pg_cfg->page_num == 0)
28944961713Sgirish page_vld.bits.ldw.page0 = 0;
29044961713Sgirish
29144961713Sgirish if (pg_cfg->page_num == 1)
29244961713Sgirish page_vld.bits.ldw.page1 = 0;
29344961713Sgirish NXGE_REG_WR64(handle, valid_offset, page_vld.value);
29444961713Sgirish return (NPI_SUCCESS);
29544961713Sgirish }
29644961713Sgirish
29744961713Sgirish if (pg_cfg->page_num == 0) {
29844961713Sgirish mask_offset = REG_FZC_RDC_OFFSET(RX_LOG_PAGE_MASK1_REG, rdc);
29944961713Sgirish value_offset = REG_FZC_RDC_OFFSET(RX_LOG_PAGE_VAL1_REG, rdc);
30044961713Sgirish reloc_offset = REG_FZC_RDC_OFFSET(RX_LOG_PAGE_RELO1_REG, rdc);
30144961713Sgirish page_vld.bits.ldw.page0 = 1;
30244961713Sgirish }
30344961713Sgirish
30444961713Sgirish if (pg_cfg->page_num == 1) {
30544961713Sgirish mask_offset = REG_FZC_RDC_OFFSET(RX_LOG_PAGE_MASK2_REG, rdc);
30644961713Sgirish value_offset = REG_FZC_RDC_OFFSET(RX_LOG_PAGE_VAL2_REG, rdc);
30744961713Sgirish reloc_offset = REG_FZC_RDC_OFFSET(RX_LOG_PAGE_RELO2_REG, rdc);
30844961713Sgirish page_vld.bits.ldw.page1 = 1;
30944961713Sgirish }
31044961713Sgirish
31144961713Sgirish
31244961713Sgirish page_vld.bits.ldw.func = pg_cfg->func_num;
31344961713Sgirish
31444961713Sgirish page_mask.value = 0;
31544961713Sgirish page_value.value = 0;
31644961713Sgirish page_reloc.value = 0;
31744961713Sgirish
31844961713Sgirish
31944961713Sgirish page_mask.bits.ldw.mask = pg_cfg->mask >> LOG_PAGE_ADDR_SHIFT;
32044961713Sgirish page_value.bits.ldw.value = pg_cfg->value >> LOG_PAGE_ADDR_SHIFT;
32144961713Sgirish page_reloc.bits.ldw.relo = pg_cfg->reloc >> LOG_PAGE_ADDR_SHIFT;
32244961713Sgirish
32344961713Sgirish
32444961713Sgirish NXGE_REG_WR64(handle, mask_offset, page_mask.value);
32544961713Sgirish NXGE_REG_WR64(handle, value_offset, page_value.value);
32644961713Sgirish NXGE_REG_WR64(handle, reloc_offset, page_reloc.value);
32744961713Sgirish
32844961713Sgirish
32944961713Sgirish /* enable the logical page */
33044961713Sgirish NXGE_REG_WR64(handle, valid_offset, page_vld.value);
33144961713Sgirish return (NPI_SUCCESS);
33244961713Sgirish }
33344961713Sgirish
33444961713Sgirish npi_status_t
npi_rxdma_cfg_logical_page_handle(npi_handle_t handle,uint8_t rdc,uint64_t page_handle)33544961713Sgirish npi_rxdma_cfg_logical_page_handle(npi_handle_t handle, uint8_t rdc,
33644961713Sgirish uint64_t page_handle)
33744961713Sgirish {
33844961713Sgirish uint64_t offset;
33944961713Sgirish log_page_hdl_t page_hdl;
34044961713Sgirish
341a3c5bd6dSspeer ASSERT(RXDMA_CHANNEL_VALID(rdc));
34244961713Sgirish if (!RXDMA_CHANNEL_VALID(rdc)) {
34344961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
34444961713Sgirish "rxdma_cfg_logical_page_handle"
34544961713Sgirish " Illegal RDC number %d \n", rdc));
34644961713Sgirish return (NPI_RXDMA_RDC_INVALID);
34744961713Sgirish }
34844961713Sgirish
34944961713Sgirish page_hdl.value = 0;
35044961713Sgirish
35144961713Sgirish page_hdl.bits.ldw.handle = (uint32_t)page_handle;
35244961713Sgirish offset = REG_FZC_RDC_OFFSET(RX_LOG_PAGE_HDL_REG, rdc);
35344961713Sgirish NXGE_REG_WR64(handle, offset, page_hdl.value);
35444961713Sgirish
35544961713Sgirish return (NPI_SUCCESS);
35644961713Sgirish }
35744961713Sgirish
358a3c5bd6dSspeer /*
359a3c5bd6dSspeer * RX DMA functions
360a3c5bd6dSspeer */
36144961713Sgirish npi_status_t
npi_rxdma_cfg_rdc_ctl(npi_handle_t handle,uint8_t rdc,uint8_t op)36244961713Sgirish npi_rxdma_cfg_rdc_ctl(npi_handle_t handle, uint8_t rdc, uint8_t op)
36344961713Sgirish {
36444961713Sgirish
36544961713Sgirish rxdma_cfig1_t cfg;
36644961713Sgirish uint32_t count = RXDMA_RESET_TRY_COUNT;
36744961713Sgirish uint32_t delay_time = RXDMA_RESET_DELAY;
36844961713Sgirish uint32_t error = NPI_RXDMA_ERROR_ENCODE(NPI_RXDMA_RESET_ERR, rdc);
36944961713Sgirish
370a3c5bd6dSspeer ASSERT(RXDMA_CHANNEL_VALID(rdc));
37144961713Sgirish if (!RXDMA_CHANNEL_VALID(rdc)) {
37244961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
37352ccf843Smisaki "npi_rxdma_cfg_rdc_ctl"
37452ccf843Smisaki " Illegal RDC number %d \n", rdc));
37544961713Sgirish return (NPI_RXDMA_RDC_INVALID);
37644961713Sgirish }
37744961713Sgirish
37844961713Sgirish
37944961713Sgirish switch (op) {
38044961713Sgirish case RXDMA_OP_ENABLE:
38144961713Sgirish RXDMA_REG_READ64(handle, RXDMA_CFIG1_REG, rdc,
38252ccf843Smisaki &cfg.value);
38344961713Sgirish cfg.bits.ldw.en = 1;
38444961713Sgirish RXDMA_REG_WRITE64(handle, RXDMA_CFIG1_REG,
38552ccf843Smisaki rdc, cfg.value);
38644961713Sgirish
38744961713Sgirish NXGE_DELAY(delay_time);
38844961713Sgirish RXDMA_REG_READ64(handle, RXDMA_CFIG1_REG, rdc,
38952ccf843Smisaki &cfg.value);
39044961713Sgirish while ((count--) && (cfg.bits.ldw.qst == 0)) {
39144961713Sgirish NXGE_DELAY(delay_time);
39244961713Sgirish RXDMA_REG_READ64(handle, RXDMA_CFIG1_REG, rdc,
39352ccf843Smisaki &cfg.value);
39444961713Sgirish }
39544961713Sgirish
39644961713Sgirish if (cfg.bits.ldw.qst == 0) {
39744961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
39844961713Sgirish " npi_rxdma_cfg_rdc_ctl"
39944961713Sgirish " RXDMA_OP_ENABLE Failed for RDC %d \n",
40044961713Sgirish rdc));
40144961713Sgirish return (error);
40244961713Sgirish }
40344961713Sgirish
40444961713Sgirish break;
40544961713Sgirish case RXDMA_OP_DISABLE:
40644961713Sgirish RXDMA_REG_READ64(handle, RXDMA_CFIG1_REG, rdc,
40752ccf843Smisaki &cfg.value);
40844961713Sgirish cfg.bits.ldw.en = 0;
40944961713Sgirish RXDMA_REG_WRITE64(handle, RXDMA_CFIG1_REG,
41052ccf843Smisaki rdc, cfg.value);
41144961713Sgirish
41244961713Sgirish NXGE_DELAY(delay_time);
41344961713Sgirish RXDMA_REG_READ64(handle, RXDMA_CFIG1_REG, rdc,
41452ccf843Smisaki &cfg.value);
41544961713Sgirish while ((count--) && (cfg.bits.ldw.qst == 0)) {
41644961713Sgirish NXGE_DELAY(delay_time);
41744961713Sgirish RXDMA_REG_READ64(handle, RXDMA_CFIG1_REG, rdc,
41852ccf843Smisaki &cfg.value);
41944961713Sgirish }
42044961713Sgirish if (cfg.bits.ldw.qst == 0) {
42144961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
42244961713Sgirish " npi_rxdma_cfg_rdc_ctl"
42344961713Sgirish " RXDMA_OP_DISABLE Failed for RDC %d \n",
42444961713Sgirish rdc));
42544961713Sgirish return (error);
42644961713Sgirish }
42744961713Sgirish
42844961713Sgirish break;
42944961713Sgirish case RXDMA_OP_RESET:
43044961713Sgirish cfg.value = 0;
43144961713Sgirish cfg.bits.ldw.rst = 1;
43244961713Sgirish RXDMA_REG_WRITE64(handle,
43352ccf843Smisaki RXDMA_CFIG1_REG,
43452ccf843Smisaki rdc, cfg.value);
43544961713Sgirish NXGE_DELAY(delay_time);
43644961713Sgirish RXDMA_REG_READ64(handle, RXDMA_CFIG1_REG, rdc,
43752ccf843Smisaki &cfg.value);
43844961713Sgirish while ((count--) && (cfg.bits.ldw.rst)) {
43944961713Sgirish NXGE_DELAY(delay_time);
44044961713Sgirish RXDMA_REG_READ64(handle, RXDMA_CFIG1_REG, rdc,
44152ccf843Smisaki &cfg.value);
44244961713Sgirish }
44344961713Sgirish if (count == 0) {
44444961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
44552ccf843Smisaki " npi_rxdma_cfg_rdc_ctl"
44652ccf843Smisaki " Reset Failed for RDC %d \n",
44752ccf843Smisaki rdc));
44844961713Sgirish return (error);
44944961713Sgirish }
45044961713Sgirish break;
45144961713Sgirish default:
45244961713Sgirish return (NPI_RXDMA_SW_PARAM_ERROR);
45344961713Sgirish }
45444961713Sgirish
45544961713Sgirish return (NPI_SUCCESS);
45644961713Sgirish }
45744961713Sgirish
45844961713Sgirish npi_status_t
npi_rxdma_cfg_rdc_enable(npi_handle_t handle,uint8_t rdc)45944961713Sgirish npi_rxdma_cfg_rdc_enable(npi_handle_t handle, uint8_t rdc)
46044961713Sgirish {
46144961713Sgirish return (npi_rxdma_cfg_rdc_ctl(handle, rdc, RXDMA_OP_ENABLE));
46244961713Sgirish }
46344961713Sgirish
46444961713Sgirish npi_status_t
npi_rxdma_cfg_rdc_disable(npi_handle_t handle,uint8_t rdc)46544961713Sgirish npi_rxdma_cfg_rdc_disable(npi_handle_t handle, uint8_t rdc)
46644961713Sgirish {
46744961713Sgirish return (npi_rxdma_cfg_rdc_ctl(handle, rdc, RXDMA_OP_DISABLE));
46844961713Sgirish }
46944961713Sgirish
47044961713Sgirish npi_status_t
npi_rxdma_cfg_rdc_reset(npi_handle_t handle,uint8_t rdc)47144961713Sgirish npi_rxdma_cfg_rdc_reset(npi_handle_t handle, uint8_t rdc)
47244961713Sgirish {
47344961713Sgirish return (npi_rxdma_cfg_rdc_ctl(handle, rdc, RXDMA_OP_RESET));
47444961713Sgirish }
47544961713Sgirish
47644961713Sgirish /*
477*9b622488SToomas Soome * npi_rxdma_cfg_default_port_rdc()
47844961713Sgirish * Set the default rdc for the port
47944961713Sgirish *
48044961713Sgirish * Inputs:
48144961713Sgirish * handle: register handle interpreted by the underlying OS
48244961713Sgirish * portnm: Physical Port Number
48344961713Sgirish * rdc: RX DMA Channel number
48444961713Sgirish *
48544961713Sgirish * Return:
48644961713Sgirish * NPI_SUCCESS
48744961713Sgirish * NPI_RXDMA_RDC_INVALID
48844961713Sgirish * NPI_RXDMA_PORT_INVALID
48944961713Sgirish *
49044961713Sgirish */
npi_rxdma_cfg_default_port_rdc(npi_handle_t handle,uint8_t portnm,uint8_t rdc)49144961713Sgirish npi_status_t npi_rxdma_cfg_default_port_rdc(npi_handle_t handle,
49244961713Sgirish uint8_t portnm, uint8_t rdc)
49344961713Sgirish {
49444961713Sgirish
49544961713Sgirish uint64_t offset;
49644961713Sgirish def_pt_rdc_t cfg;
49744961713Sgirish
498a3c5bd6dSspeer ASSERT(RXDMA_CHANNEL_VALID(rdc));
49944961713Sgirish if (!RXDMA_CHANNEL_VALID(rdc)) {
50044961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
50152ccf843Smisaki "rxdma_cfg_default_port_rdc"
50252ccf843Smisaki " Illegal RDC number %d \n",
50352ccf843Smisaki rdc));
50444961713Sgirish return (NPI_RXDMA_RDC_INVALID);
50544961713Sgirish }
50644961713Sgirish
507a3c5bd6dSspeer ASSERT(RXDMA_PORT_VALID(portnm));
50844961713Sgirish if (!RXDMA_PORT_VALID(portnm)) {
50944961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
51052ccf843Smisaki "rxdma_cfg_default_port_rdc"
51152ccf843Smisaki " Illegal Port number %d \n",
51252ccf843Smisaki portnm));
51344961713Sgirish return (NPI_RXDMA_PORT_INVALID);
51444961713Sgirish }
51544961713Sgirish
51644961713Sgirish offset = DEF_PT_RDC_REG(portnm);
51744961713Sgirish cfg.value = 0;
51844961713Sgirish cfg.bits.ldw.rdc = rdc;
51944961713Sgirish NXGE_REG_WR64(handle, offset, cfg.value);
52044961713Sgirish return (NPI_SUCCESS);
52144961713Sgirish }
52244961713Sgirish
52344961713Sgirish npi_status_t
npi_rxdma_cfg_rdc_rcr_ctl(npi_handle_t handle,uint8_t rdc,uint8_t op,uint16_t param)52444961713Sgirish npi_rxdma_cfg_rdc_rcr_ctl(npi_handle_t handle, uint8_t rdc,
52544961713Sgirish uint8_t op, uint16_t param)
52644961713Sgirish {
52744961713Sgirish rcrcfig_b_t rcr_cfgb;
52844961713Sgirish
529a3c5bd6dSspeer ASSERT(RXDMA_CHANNEL_VALID(rdc));
53044961713Sgirish if (!RXDMA_CHANNEL_VALID(rdc)) {
53144961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
53252ccf843Smisaki "rxdma_cfg_rdc_rcr_ctl"
53352ccf843Smisaki " Illegal RDC number %d \n",
53452ccf843Smisaki rdc));
53544961713Sgirish return (NPI_RXDMA_RDC_INVALID);
53644961713Sgirish }
53744961713Sgirish
53844961713Sgirish
53944961713Sgirish RXDMA_REG_READ64(handle, RCRCFIG_B_REG, rdc, &rcr_cfgb.value);
54044961713Sgirish
54144961713Sgirish switch (op) {
54244961713Sgirish case RCR_TIMEOUT_ENABLE:
54344961713Sgirish rcr_cfgb.bits.ldw.timeout = (uint8_t)param;
54444961713Sgirish rcr_cfgb.bits.ldw.entout = 1;
54544961713Sgirish break;
54644961713Sgirish
54744961713Sgirish case RCR_THRESHOLD:
54844961713Sgirish rcr_cfgb.bits.ldw.pthres = param;
54944961713Sgirish break;
55044961713Sgirish
55144961713Sgirish case RCR_TIMEOUT_DISABLE:
55244961713Sgirish rcr_cfgb.bits.ldw.entout = 0;
55344961713Sgirish break;
55444961713Sgirish
55544961713Sgirish default:
55644961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
55752ccf843Smisaki "rxdma_cfg_rdc_rcr_ctl"
55852ccf843Smisaki " Illegal opcode %x \n",
55952ccf843Smisaki op));
56044961713Sgirish return (NPI_RXDMA_OPCODE_INVALID(rdc));
56144961713Sgirish }
56244961713Sgirish
56344961713Sgirish RXDMA_REG_WRITE64(handle, RCRCFIG_B_REG, rdc, rcr_cfgb.value);
56444961713Sgirish return (NPI_SUCCESS);
56544961713Sgirish }
56644961713Sgirish
56744961713Sgirish npi_status_t
npi_rxdma_cfg_rdc_rcr_timeout_disable(npi_handle_t handle,uint8_t rdc)56844961713Sgirish npi_rxdma_cfg_rdc_rcr_timeout_disable(npi_handle_t handle, uint8_t rdc)
56944961713Sgirish {
57044961713Sgirish return (npi_rxdma_cfg_rdc_rcr_ctl(handle, rdc,
57144961713Sgirish RCR_TIMEOUT_DISABLE, 0));
57244961713Sgirish }
57344961713Sgirish
57444961713Sgirish npi_status_t
npi_rxdma_cfg_rdc_rcr_threshold(npi_handle_t handle,uint8_t rdc,uint16_t rcr_threshold)57544961713Sgirish npi_rxdma_cfg_rdc_rcr_threshold(npi_handle_t handle, uint8_t rdc,
57644961713Sgirish uint16_t rcr_threshold)
57744961713Sgirish {
57844961713Sgirish return (npi_rxdma_cfg_rdc_rcr_ctl(handle, rdc,
57944961713Sgirish RCR_THRESHOLD, rcr_threshold));
58044961713Sgirish
58144961713Sgirish }
58244961713Sgirish
58344961713Sgirish npi_status_t
npi_rxdma_cfg_rdc_rcr_timeout(npi_handle_t handle,uint8_t rdc,uint8_t rcr_timeout)58444961713Sgirish npi_rxdma_cfg_rdc_rcr_timeout(npi_handle_t handle, uint8_t rdc,
58544961713Sgirish uint8_t rcr_timeout)
58644961713Sgirish {
58744961713Sgirish return (npi_rxdma_cfg_rdc_rcr_ctl(handle, rdc,
58844961713Sgirish RCR_TIMEOUT_ENABLE, rcr_timeout));
58944961713Sgirish
59044961713Sgirish }
59144961713Sgirish
59244961713Sgirish /*
59344961713Sgirish * npi_rxdma_cfg_rdc_ring()
59444961713Sgirish * Configure The RDC channel Rcv Buffer Ring
59544961713Sgirish */
59644961713Sgirish npi_status_t
npi_rxdma_cfg_rdc_ring(npi_handle_t handle,uint8_t rdc,rdc_desc_cfg_t * rdc_desc_cfg,boolean_t new_off)59744961713Sgirish npi_rxdma_cfg_rdc_ring(npi_handle_t handle, uint8_t rdc,
5984df55fdeSJanie Lu rdc_desc_cfg_t *rdc_desc_cfg, boolean_t new_off)
59944961713Sgirish {
60044961713Sgirish rbr_cfig_a_t cfga;
60144961713Sgirish rbr_cfig_b_t cfgb;
60244961713Sgirish rxdma_cfig1_t cfg1;
60344961713Sgirish rxdma_cfig2_t cfg2;
60444961713Sgirish rcrcfig_a_t rcr_cfga;
60544961713Sgirish rcrcfig_b_t rcr_cfgb;
60644961713Sgirish
607a3c5bd6dSspeer ASSERT(RXDMA_CHANNEL_VALID(rdc));
60844961713Sgirish if (!RXDMA_CHANNEL_VALID(rdc)) {
60944961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
61052ccf843Smisaki "rxdma_cfg_rdc_ring"
61152ccf843Smisaki " Illegal RDC number %d \n",
61252ccf843Smisaki rdc));
61344961713Sgirish return (NPI_RXDMA_RDC_INVALID);
61444961713Sgirish }
61544961713Sgirish
61644961713Sgirish
61744961713Sgirish cfga.value = 0;
61844961713Sgirish cfgb.value = 0;
61944961713Sgirish cfg1.value = 0;
62044961713Sgirish cfg2.value = 0;
62144961713Sgirish
62244961713Sgirish if (rdc_desc_cfg->mbox_enable == 1) {
62344961713Sgirish cfg1.bits.ldw.mbaddr_h =
62444961713Sgirish (rdc_desc_cfg->mbox_addr >> 32) & 0xfff;
62544961713Sgirish cfg2.bits.ldw.mbaddr =
62644961713Sgirish ((rdc_desc_cfg->mbox_addr &
62752ccf843Smisaki RXDMA_CFIG2_MBADDR_L_MASK) >>
62852ccf843Smisaki RXDMA_CFIG2_MBADDR_L_SHIFT);
62944961713Sgirish
63044961713Sgirish
63144961713Sgirish /*
63244961713Sgirish * Only after all the configurations are set, then
63344961713Sgirish * enable the RDC or else configuration fatal error
63444961713Sgirish * will be returned (especially if the Hypervisor
63544961713Sgirish * set up the logical pages with non-zero values.
63644961713Sgirish * This NPI function only sets up the configuration.
63744961713Sgirish */
63844961713Sgirish }
63944961713Sgirish
64044961713Sgirish
64144961713Sgirish if (rdc_desc_cfg->full_hdr == 1)
64244961713Sgirish cfg2.bits.ldw.full_hdr = 1;
64344961713Sgirish
6444df55fdeSJanie Lu if (new_off) {
6454df55fdeSJanie Lu if (RXDMA_RF_BUFF_OFFSET_VALID(rdc_desc_cfg->offset)) {
6464df55fdeSJanie Lu switch (rdc_desc_cfg->offset) {
6474df55fdeSJanie Lu case SW_OFFSET_NO_OFFSET:
6484df55fdeSJanie Lu case SW_OFFSET_64:
6494df55fdeSJanie Lu case SW_OFFSET_128:
6504df55fdeSJanie Lu case SW_OFFSET_192:
6514df55fdeSJanie Lu cfg2.bits.ldw.offset = rdc_desc_cfg->offset;
6524df55fdeSJanie Lu cfg2.bits.ldw.offset256 = 0;
6534df55fdeSJanie Lu break;
6544df55fdeSJanie Lu case SW_OFFSET_256:
6554df55fdeSJanie Lu case SW_OFFSET_320:
6564df55fdeSJanie Lu case SW_OFFSET_384:
6574df55fdeSJanie Lu case SW_OFFSET_448:
6584df55fdeSJanie Lu cfg2.bits.ldw.offset =
6594df55fdeSJanie Lu rdc_desc_cfg->offset & 0x3;
6604df55fdeSJanie Lu cfg2.bits.ldw.offset256 = 1;
6614df55fdeSJanie Lu break;
6624df55fdeSJanie Lu default:
6634df55fdeSJanie Lu cfg2.bits.ldw.offset = SW_OFFSET_NO_OFFSET;
6644df55fdeSJanie Lu cfg2.bits.ldw.offset256 = 0;
6654df55fdeSJanie Lu }
6664df55fdeSJanie Lu } else {
6674df55fdeSJanie Lu cfg2.bits.ldw.offset = SW_OFFSET_NO_OFFSET;
6684df55fdeSJanie Lu cfg2.bits.ldw.offset256 = 0;
6694df55fdeSJanie Lu }
67044961713Sgirish } else {
6714df55fdeSJanie Lu if (RXDMA_BUFF_OFFSET_VALID(rdc_desc_cfg->offset)) {
6724df55fdeSJanie Lu cfg2.bits.ldw.offset = rdc_desc_cfg->offset;
6734df55fdeSJanie Lu } else {
6744df55fdeSJanie Lu cfg2.bits.ldw.offset = SW_OFFSET_NO_OFFSET;
6754df55fdeSJanie Lu }
67644961713Sgirish }
67744961713Sgirish
67844961713Sgirish /* rbr config */
67944961713Sgirish
68044961713Sgirish cfga.value = (rdc_desc_cfg->rbr_addr & (RBR_CFIG_A_STDADDR_MASK |
68152ccf843Smisaki RBR_CFIG_A_STDADDR_BASE_MASK));
68244961713Sgirish
68344961713Sgirish if ((rdc_desc_cfg->rbr_len < RBR_DEFAULT_MIN_LEN) ||
68452ccf843Smisaki (rdc_desc_cfg->rbr_len > RBR_DEFAULT_MAX_LEN)) {
68544961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
68652ccf843Smisaki "npi_rxdma_cfg_rdc_ring"
68752ccf843Smisaki " Illegal RBR Queue Length %d \n",
68852ccf843Smisaki rdc_desc_cfg->rbr_len));
689678453a8Sspeer return (NPI_RXDMA_ERROR_ENCODE(NPI_RXDMA_RBRSIZE_INVALID, rdc));
69044961713Sgirish }
69144961713Sgirish
69244961713Sgirish
69344961713Sgirish cfga.bits.hdw.len = rdc_desc_cfg->rbr_len;
69444961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_RDC_CTL,
69552ccf843Smisaki "npi_rxdma_cfg_rdc_ring"
69652ccf843Smisaki " CFGA 0x%llx hdw.len %d (RBR LEN %d)\n",
69752ccf843Smisaki cfga.value, cfga.bits.hdw.len,
69852ccf843Smisaki rdc_desc_cfg->rbr_len));
69944961713Sgirish
70044961713Sgirish if (rdc_desc_cfg->page_size == SIZE_4KB)
70144961713Sgirish cfgb.bits.ldw.bksize = RBR_BKSIZE_4K;
70244961713Sgirish else if (rdc_desc_cfg->page_size == SIZE_8KB)
70344961713Sgirish cfgb.bits.ldw.bksize = RBR_BKSIZE_8K;
70444961713Sgirish else if (rdc_desc_cfg->page_size == SIZE_16KB)
70544961713Sgirish cfgb.bits.ldw.bksize = RBR_BKSIZE_16K;
70644961713Sgirish else if (rdc_desc_cfg->page_size == SIZE_32KB)
70744961713Sgirish cfgb.bits.ldw.bksize = RBR_BKSIZE_32K;
70844961713Sgirish else {
70944961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
71052ccf843Smisaki "rxdma_cfg_rdc_ring"
71152ccf843Smisaki " blksize: Illegal buffer size %d \n",
71252ccf843Smisaki rdc_desc_cfg->page_size));
713678453a8Sspeer return (NPI_RXDMA_BUFSIZE_INVALID);
71444961713Sgirish }
71544961713Sgirish
71644961713Sgirish if (rdc_desc_cfg->valid0) {
71744961713Sgirish
71844961713Sgirish if (rdc_desc_cfg->size0 == SIZE_256B)
71944961713Sgirish cfgb.bits.ldw.bufsz0 = RBR_BUFSZ0_256B;
72044961713Sgirish else if (rdc_desc_cfg->size0 == SIZE_512B)
72144961713Sgirish cfgb.bits.ldw.bufsz0 = RBR_BUFSZ0_512B;
72244961713Sgirish else if (rdc_desc_cfg->size0 == SIZE_1KB)
72344961713Sgirish cfgb.bits.ldw.bufsz0 = RBR_BUFSZ0_1K;
72444961713Sgirish else if (rdc_desc_cfg->size0 == SIZE_2KB)
72544961713Sgirish cfgb.bits.ldw.bufsz0 = RBR_BUFSZ0_2K;
72644961713Sgirish else {
72744961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
72852ccf843Smisaki " rxdma_cfg_rdc_ring"
72952ccf843Smisaki " blksize0: Illegal buffer size %x \n",
73052ccf843Smisaki rdc_desc_cfg->size0));
731678453a8Sspeer return (NPI_RXDMA_BUFSIZE_INVALID);
73244961713Sgirish }
73344961713Sgirish cfgb.bits.ldw.vld0 = 1;
73444961713Sgirish } else {
73544961713Sgirish cfgb.bits.ldw.vld0 = 0;
73644961713Sgirish }
73744961713Sgirish
73844961713Sgirish
73944961713Sgirish if (rdc_desc_cfg->valid1) {
74044961713Sgirish if (rdc_desc_cfg->size1 == SIZE_1KB)
74144961713Sgirish cfgb.bits.ldw.bufsz1 = RBR_BUFSZ1_1K;
74244961713Sgirish else if (rdc_desc_cfg->size1 == SIZE_2KB)
74344961713Sgirish cfgb.bits.ldw.bufsz1 = RBR_BUFSZ1_2K;
74444961713Sgirish else if (rdc_desc_cfg->size1 == SIZE_4KB)
74544961713Sgirish cfgb.bits.ldw.bufsz1 = RBR_BUFSZ1_4K;
74644961713Sgirish else if (rdc_desc_cfg->size1 == SIZE_8KB)
74744961713Sgirish cfgb.bits.ldw.bufsz1 = RBR_BUFSZ1_8K;
74844961713Sgirish else {
74944961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
75052ccf843Smisaki " rxdma_cfg_rdc_ring"
75152ccf843Smisaki " blksize1: Illegal buffer size %x \n",
75252ccf843Smisaki rdc_desc_cfg->size1));
753678453a8Sspeer return (NPI_RXDMA_BUFSIZE_INVALID);
75444961713Sgirish }
75544961713Sgirish cfgb.bits.ldw.vld1 = 1;
75644961713Sgirish } else {
75744961713Sgirish cfgb.bits.ldw.vld1 = 0;
75844961713Sgirish }
75944961713Sgirish
76044961713Sgirish
76144961713Sgirish if (rdc_desc_cfg->valid2) {
76244961713Sgirish if (rdc_desc_cfg->size2 == SIZE_2KB)
76344961713Sgirish cfgb.bits.ldw.bufsz2 = RBR_BUFSZ2_2K;
76444961713Sgirish else if (rdc_desc_cfg->size2 == SIZE_4KB)
76544961713Sgirish cfgb.bits.ldw.bufsz2 = RBR_BUFSZ2_4K;
76644961713Sgirish else if (rdc_desc_cfg->size2 == SIZE_8KB)
76744961713Sgirish cfgb.bits.ldw.bufsz2 = RBR_BUFSZ2_8K;
76844961713Sgirish else if (rdc_desc_cfg->size2 == SIZE_16KB)
76944961713Sgirish cfgb.bits.ldw.bufsz2 = RBR_BUFSZ2_16K;
77044961713Sgirish else {
77144961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
77252ccf843Smisaki " rxdma_cfg_rdc_ring"
77352ccf843Smisaki " blksize2: Illegal buffer size %x \n",
77452ccf843Smisaki rdc_desc_cfg->size2));
775678453a8Sspeer return (NPI_RXDMA_BUFSIZE_INVALID);
77644961713Sgirish }
77744961713Sgirish cfgb.bits.ldw.vld2 = 1;
77844961713Sgirish } else {
77944961713Sgirish cfgb.bits.ldw.vld2 = 0;
78044961713Sgirish }
78144961713Sgirish
78244961713Sgirish
78344961713Sgirish rcr_cfga.value = (rdc_desc_cfg->rcr_addr &
78452ccf843Smisaki (RCRCFIG_A_STADDR_MASK |
78552ccf843Smisaki RCRCFIG_A_STADDR_BASE_MASK));
78644961713Sgirish
78744961713Sgirish
78844961713Sgirish if ((rdc_desc_cfg->rcr_len < RCR_DEFAULT_MIN_LEN) ||
78952ccf843Smisaki (rdc_desc_cfg->rcr_len > NXGE_RCR_MAX)) {
79044961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
79152ccf843Smisaki " rxdma_cfg_rdc_ring"
79252ccf843Smisaki " Illegal RCR Queue Length %d \n",
79352ccf843Smisaki rdc_desc_cfg->rcr_len));
794678453a8Sspeer return (NPI_RXDMA_ERROR_ENCODE(NPI_RXDMA_RCRSIZE_INVALID, rdc));
79544961713Sgirish }
79644961713Sgirish
79744961713Sgirish rcr_cfga.bits.hdw.len = rdc_desc_cfg->rcr_len;
79844961713Sgirish
79944961713Sgirish
80044961713Sgirish rcr_cfgb.value = 0;
80144961713Sgirish if (rdc_desc_cfg->rcr_timeout_enable == 1) {
80244961713Sgirish /* check if the rcr timeout value is valid */
80344961713Sgirish
80444961713Sgirish if (RXDMA_RCR_TO_VALID(rdc_desc_cfg->rcr_timeout)) {
80544961713Sgirish rcr_cfgb.bits.ldw.timeout = rdc_desc_cfg->rcr_timeout;
80644961713Sgirish rcr_cfgb.bits.ldw.entout = 1;
80744961713Sgirish } else {
80844961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
80952ccf843Smisaki " rxdma_cfg_rdc_ring"
81052ccf843Smisaki " Illegal RCR Timeout value %d \n",
81152ccf843Smisaki rdc_desc_cfg->rcr_timeout));
81244961713Sgirish rcr_cfgb.bits.ldw.entout = 0;
81344961713Sgirish }
81444961713Sgirish } else {
81544961713Sgirish rcr_cfgb.bits.ldw.entout = 0;
81644961713Sgirish }
81744961713Sgirish
81844961713Sgirish /* check if the rcr threshold value is valid */
81944961713Sgirish if (RXDMA_RCR_THRESH_VALID(rdc_desc_cfg->rcr_threshold)) {
82044961713Sgirish rcr_cfgb.bits.ldw.pthres = rdc_desc_cfg->rcr_threshold;
82144961713Sgirish } else {
82244961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
82352ccf843Smisaki " rxdma_cfg_rdc_ring"
82452ccf843Smisaki " Illegal RCR Threshold value %d \n",
82552ccf843Smisaki rdc_desc_cfg->rcr_threshold));
82644961713Sgirish rcr_cfgb.bits.ldw.pthres = 1;
82744961713Sgirish }
82844961713Sgirish
82944961713Sgirish /* now do the actual HW configuration */
83044961713Sgirish RXDMA_REG_WRITE64(handle, RXDMA_CFIG1_REG, rdc, cfg1.value);
83144961713Sgirish RXDMA_REG_WRITE64(handle, RXDMA_CFIG2_REG, rdc, cfg2.value);
83244961713Sgirish
83344961713Sgirish
83444961713Sgirish RXDMA_REG_WRITE64(handle, RBR_CFIG_A_REG, rdc, cfga.value);
83544961713Sgirish RXDMA_REG_WRITE64(handle, RBR_CFIG_B_REG, rdc, cfgb.value);
83644961713Sgirish
83744961713Sgirish RXDMA_REG_WRITE64(handle, RCRCFIG_A_REG, rdc, rcr_cfga.value);
83844961713Sgirish RXDMA_REG_WRITE64(handle, RCRCFIG_B_REG, rdc, rcr_cfgb.value);
83944961713Sgirish
84044961713Sgirish return (NPI_SUCCESS);
84144961713Sgirish
84244961713Sgirish }
84344961713Sgirish
84444961713Sgirish /*
84544961713Sgirish * npi_rxdma_red_discard_stat_get
84644961713Sgirish * Gets the current discrad count due RED
84744961713Sgirish * The counter overflow bit is cleared, if it has been set.
84844961713Sgirish *
84944961713Sgirish * Inputs:
850a3c5bd6dSspeer * handle: opaque handle interpreted by the underlying OS
85144961713Sgirish * rdc: RX DMA Channel number
852a3c5bd6dSspeer * cnt: Ptr to structure to write current RDC discard stat
85344961713Sgirish *
85444961713Sgirish * Return:
85544961713Sgirish * NPI_SUCCESS
85644961713Sgirish * NPI_RXDMA_RDC_INVALID
85744961713Sgirish *
85844961713Sgirish */
85944961713Sgirish npi_status_t
npi_rxdma_red_discard_stat_get(npi_handle_t handle,uint8_t rdc,rx_disc_cnt_t * cnt)86044961713Sgirish npi_rxdma_red_discard_stat_get(npi_handle_t handle, uint8_t rdc,
86144961713Sgirish rx_disc_cnt_t *cnt)
86244961713Sgirish {
86344961713Sgirish uint64_t offset;
86444961713Sgirish
865a3c5bd6dSspeer ASSERT(RXDMA_CHANNEL_VALID(rdc));
86644961713Sgirish if (!RXDMA_CHANNEL_VALID(rdc)) {
86744961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
86852ccf843Smisaki " npi_rxdma_red_discard_stat_get"
86952ccf843Smisaki " Illegal RDC Number %d \n",
87052ccf843Smisaki rdc));
87144961713Sgirish return (NPI_RXDMA_RDC_INVALID);
87244961713Sgirish }
87344961713Sgirish
87444961713Sgirish offset = RDC_RED_RDC_DISC_REG(rdc);
87544961713Sgirish NXGE_REG_RD64(handle, offset, &cnt->value);
87644961713Sgirish if (cnt->bits.ldw.oflow) {
87744961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_ERR_CTL,
87852ccf843Smisaki " npi_rxdma_red_discard_stat_get"
87952ccf843Smisaki " Counter overflow for channel %d ",
88052ccf843Smisaki " ..... clearing \n",
88152ccf843Smisaki rdc));
88244961713Sgirish cnt->bits.ldw.oflow = 0;
88344961713Sgirish NXGE_REG_WR64(handle, offset, cnt->value);
88444961713Sgirish cnt->bits.ldw.oflow = 1;
88544961713Sgirish }
88644961713Sgirish
88744961713Sgirish return (NPI_SUCCESS);
88844961713Sgirish }
88944961713Sgirish
89044961713Sgirish /*
89144961713Sgirish * npi_rxdma_red_discard_oflow_clear
89244961713Sgirish * Clear RED discard counter overflow bit
89344961713Sgirish *
89444961713Sgirish * Inputs:
895a3c5bd6dSspeer * handle: opaque handle interpreted by the underlying OS
89644961713Sgirish * rdc: RX DMA Channel number
89744961713Sgirish *
89844961713Sgirish * Return:
89944961713Sgirish * NPI_SUCCESS
90044961713Sgirish * NPI_RXDMA_RDC_INVALID
90144961713Sgirish *
90244961713Sgirish */
90344961713Sgirish npi_status_t
npi_rxdma_red_discard_oflow_clear(npi_handle_t handle,uint8_t rdc)90444961713Sgirish npi_rxdma_red_discard_oflow_clear(npi_handle_t handle, uint8_t rdc)
90544961713Sgirish
90644961713Sgirish {
90744961713Sgirish uint64_t offset;
90844961713Sgirish rx_disc_cnt_t cnt;
90944961713Sgirish
910a3c5bd6dSspeer ASSERT(RXDMA_CHANNEL_VALID(rdc));
91144961713Sgirish if (!RXDMA_CHANNEL_VALID(rdc)) {
91244961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
91344961713Sgirish " npi_rxdma_red_discard_oflow_clear"
91444961713Sgirish " Illegal RDC Number %d \n",
91544961713Sgirish rdc));
91644961713Sgirish return (NPI_RXDMA_RDC_INVALID);
91744961713Sgirish }
91844961713Sgirish
91944961713Sgirish offset = RDC_RED_RDC_DISC_REG(rdc);
92044961713Sgirish NXGE_REG_RD64(handle, offset, &cnt.value);
92144961713Sgirish if (cnt.bits.ldw.oflow) {
92244961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_RDC_CTL,
92344961713Sgirish " npi_rxdma_red_discard_oflow_clear"
92444961713Sgirish " Counter overflow for channel %d ",
92544961713Sgirish " ..... clearing \n",
92644961713Sgirish rdc));
92744961713Sgirish cnt.bits.ldw.oflow = 0;
92844961713Sgirish NXGE_REG_WR64(handle, offset, cnt.value);
92944961713Sgirish }
93044961713Sgirish return (NPI_SUCCESS);
93144961713Sgirish }
93244961713Sgirish
93344961713Sgirish /*
93444961713Sgirish * npi_rxdma_misc_discard_stat_get
93544961713Sgirish * Gets the current discrad count for the rdc due to
93644961713Sgirish * buffer pool empty
93744961713Sgirish * The counter overflow bit is cleared, if it has been set.
93844961713Sgirish *
93944961713Sgirish * Inputs:
940a3c5bd6dSspeer * handle: opaque handle interpreted by the underlying OS
94144961713Sgirish * rdc: RX DMA Channel number
942a3c5bd6dSspeer * cnt: Ptr to structure to write current RDC discard stat
94344961713Sgirish *
94444961713Sgirish * Return:
94544961713Sgirish * NPI_SUCCESS
94644961713Sgirish * NPI_RXDMA_RDC_INVALID
94744961713Sgirish *
94844961713Sgirish */
94944961713Sgirish npi_status_t
npi_rxdma_misc_discard_stat_get(npi_handle_t handle,uint8_t rdc,rx_disc_cnt_t * cnt)95044961713Sgirish npi_rxdma_misc_discard_stat_get(npi_handle_t handle, uint8_t rdc,
95144961713Sgirish rx_disc_cnt_t *cnt)
95244961713Sgirish {
953a3c5bd6dSspeer ASSERT(RXDMA_CHANNEL_VALID(rdc));
95444961713Sgirish if (!RXDMA_CHANNEL_VALID(rdc)) {
95544961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
95652ccf843Smisaki " npi_rxdma_misc_discard_stat_get"
95752ccf843Smisaki " Illegal RDC Number %d \n",
95852ccf843Smisaki rdc));
95944961713Sgirish return (NPI_RXDMA_RDC_INVALID);
96044961713Sgirish }
96144961713Sgirish
96244961713Sgirish RXDMA_REG_READ64(handle, RXMISC_DISCARD_REG, rdc, &cnt->value);
96344961713Sgirish if (cnt->bits.ldw.oflow) {
96444961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_RDC_CTL,
96552ccf843Smisaki " npi_rxdma_misc_discard_stat_get"
96652ccf843Smisaki " Counter overflow for channel %d ",
96752ccf843Smisaki " ..... clearing \n",
96852ccf843Smisaki rdc));
96944961713Sgirish cnt->bits.ldw.oflow = 0;
97044961713Sgirish RXDMA_REG_WRITE64(handle, RXMISC_DISCARD_REG, rdc, cnt->value);
97144961713Sgirish cnt->bits.ldw.oflow = 1;
97244961713Sgirish }
97344961713Sgirish
97444961713Sgirish return (NPI_SUCCESS);
97544961713Sgirish }
97644961713Sgirish
97744961713Sgirish /*
97844961713Sgirish * npi_rxdma_red_discard_oflow_clear
97944961713Sgirish * Clear RED discard counter overflow bit
98044961713Sgirish * clear the overflow bit for buffer pool empty discrad counter
98144961713Sgirish * for the rdc
98244961713Sgirish *
98344961713Sgirish * Inputs:
984a3c5bd6dSspeer * handle: opaque handle interpreted by the underlying OS
98544961713Sgirish * rdc: RX DMA Channel number
98644961713Sgirish *
98744961713Sgirish * Return:
98844961713Sgirish * NPI_SUCCESS
98944961713Sgirish * NPI_RXDMA_RDC_INVALID
99044961713Sgirish *
99144961713Sgirish */
99244961713Sgirish npi_status_t
npi_rxdma_misc_discard_oflow_clear(npi_handle_t handle,uint8_t rdc)99344961713Sgirish npi_rxdma_misc_discard_oflow_clear(npi_handle_t handle, uint8_t rdc)
99444961713Sgirish {
99544961713Sgirish rx_disc_cnt_t cnt;
99644961713Sgirish
997a3c5bd6dSspeer ASSERT(RXDMA_CHANNEL_VALID(rdc));
99844961713Sgirish if (!RXDMA_CHANNEL_VALID(rdc)) {
99944961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
100052ccf843Smisaki " npi_rxdma_misc_discard_oflow_clear"
100152ccf843Smisaki " Illegal RDC Number %d \n",
100252ccf843Smisaki rdc));
100344961713Sgirish return (NPI_RXDMA_RDC_INVALID);
100444961713Sgirish }
100544961713Sgirish
100644961713Sgirish RXDMA_REG_READ64(handle, RXMISC_DISCARD_REG, rdc, &cnt.value);
100744961713Sgirish if (cnt.bits.ldw.oflow) {
100844961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_RDC_CTL,
100952ccf843Smisaki " npi_rxdma_misc_discard_oflow_clear"
101052ccf843Smisaki " Counter overflow for channel %d ",
101152ccf843Smisaki " ..... clearing \n",
101252ccf843Smisaki rdc));
101344961713Sgirish cnt.bits.ldw.oflow = 0;
101444961713Sgirish RXDMA_REG_WRITE64(handle, RXMISC_DISCARD_REG, rdc, cnt.value);
101544961713Sgirish }
101644961713Sgirish
101744961713Sgirish return (NPI_SUCCESS);
101844961713Sgirish }
101944961713Sgirish
102044961713Sgirish /*
102144961713Sgirish * npi_rxdma_ring_perr_stat_get
102244961713Sgirish * Gets the current RDC Memory parity error
102344961713Sgirish * The counter overflow bit is cleared, if it has been set.
102444961713Sgirish *
102544961713Sgirish * Inputs:
1026a3c5bd6dSspeer * handle: opaque handle interpreted by the underlying OS
102744961713Sgirish * pre_log: Structure to write current RDC Prefetch memory
102844961713Sgirish * Parity Error stat
102944961713Sgirish * sha_log: Structure to write current RDC Shadow memory
103044961713Sgirish * Parity Error stat
103144961713Sgirish *
103244961713Sgirish * Return:
103344961713Sgirish * NPI_SUCCESS
103444961713Sgirish *
103544961713Sgirish */
103644961713Sgirish npi_status_t
npi_rxdma_ring_perr_stat_get(npi_handle_t handle,rdmc_par_err_log_t * pre_log,rdmc_par_err_log_t * sha_log)103744961713Sgirish npi_rxdma_ring_perr_stat_get(npi_handle_t handle,
103844961713Sgirish rdmc_par_err_log_t *pre_log,
103944961713Sgirish rdmc_par_err_log_t *sha_log)
104044961713Sgirish {
104144961713Sgirish uint64_t pre_offset, sha_offset;
104244961713Sgirish rdmc_par_err_log_t clr;
104344961713Sgirish int clr_bits = 0;
104444961713Sgirish
104544961713Sgirish pre_offset = RDMC_PRE_PAR_ERR_REG;
104644961713Sgirish sha_offset = RDMC_SHA_PAR_ERR_REG;
104744961713Sgirish NXGE_REG_RD64(handle, pre_offset, &pre_log->value);
104844961713Sgirish NXGE_REG_RD64(handle, sha_offset, &sha_log->value);
104944961713Sgirish
105044961713Sgirish clr.value = pre_log->value;
105144961713Sgirish if (pre_log->bits.ldw.err) {
105244961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_RDC_CTL,
105352ccf843Smisaki " npi_rxdma_ring_perr_stat_get"
105452ccf843Smisaki " PRE ERR Bit set ..... clearing \n"));
105544961713Sgirish clr.bits.ldw.err = 0;
105644961713Sgirish clr_bits++;
105744961713Sgirish }
105844961713Sgirish
105944961713Sgirish if (pre_log->bits.ldw.merr) {
106044961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_RDC_CTL,
106152ccf843Smisaki " npi_rxdma_ring_perr_stat_get"
106252ccf843Smisaki " PRE MERR Bit set ..... clearing \n"));
106344961713Sgirish clr.bits.ldw.merr = 0;
106444961713Sgirish clr_bits++;
106544961713Sgirish }
106644961713Sgirish
106744961713Sgirish if (clr_bits) {
106844961713Sgirish NXGE_REG_WR64(handle, pre_offset, clr.value);
106944961713Sgirish }
107044961713Sgirish
107144961713Sgirish clr_bits = 0;
107244961713Sgirish clr.value = sha_log->value;
107344961713Sgirish if (sha_log->bits.ldw.err) {
107444961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_RDC_CTL,
107552ccf843Smisaki " npi_rxdma_ring_perr_stat_get"
107652ccf843Smisaki " SHA ERR Bit set ..... clearing \n"));
107744961713Sgirish clr.bits.ldw.err = 0;
107844961713Sgirish clr_bits++;
107944961713Sgirish }
108044961713Sgirish
108144961713Sgirish if (sha_log->bits.ldw.merr) {
108244961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_RDC_CTL,
108352ccf843Smisaki " npi_rxdma_ring_perr_stat_get"
108452ccf843Smisaki " SHA MERR Bit set ..... clearing \n"));
108544961713Sgirish clr.bits.ldw.merr = 0;
108644961713Sgirish clr_bits++;
108744961713Sgirish }
108844961713Sgirish
108944961713Sgirish if (clr_bits) {
109044961713Sgirish NXGE_REG_WR64(handle, sha_offset, clr.value);
109144961713Sgirish }
109244961713Sgirish
109344961713Sgirish return (NPI_SUCCESS);
109444961713Sgirish }
109544961713Sgirish
109644961713Sgirish /*
109744961713Sgirish * npi_rxdma_ring_perr_stat_clear
109844961713Sgirish * Clear RDC Memory Parity Error counter overflow bits
109944961713Sgirish *
110044961713Sgirish * Inputs:
1101a3c5bd6dSspeer * handle: opaque handle interpreted by the underlying OS
110244961713Sgirish * Return:
110344961713Sgirish * NPI_SUCCESS
110444961713Sgirish *
110544961713Sgirish */
110644961713Sgirish npi_status_t
npi_rxdma_ring_perr_stat_clear(npi_handle_t handle)110744961713Sgirish npi_rxdma_ring_perr_stat_clear(npi_handle_t handle)
110844961713Sgirish {
110944961713Sgirish uint64_t pre_offset, sha_offset;
111044961713Sgirish rdmc_par_err_log_t clr;
111144961713Sgirish int clr_bits = 0;
111244961713Sgirish pre_offset = RDMC_PRE_PAR_ERR_REG;
111344961713Sgirish sha_offset = RDMC_SHA_PAR_ERR_REG;
111444961713Sgirish
111544961713Sgirish NXGE_REG_RD64(handle, pre_offset, &clr.value);
111644961713Sgirish
111744961713Sgirish if (clr.bits.ldw.err) {
111844961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_RDC_CTL,
111952ccf843Smisaki " npi_rxdma_ring_perr_stat_get"
112052ccf843Smisaki " PRE ERR Bit set ..... clearing \n"));
112144961713Sgirish clr.bits.ldw.err = 0;
112244961713Sgirish clr_bits++;
112344961713Sgirish }
112444961713Sgirish
112544961713Sgirish if (clr.bits.ldw.merr) {
112644961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_RDC_CTL,
112752ccf843Smisaki " npi_rxdma_ring_perr_stat_get"
112852ccf843Smisaki " PRE MERR Bit set ..... clearing \n"));
112944961713Sgirish clr.bits.ldw.merr = 0;
113044961713Sgirish clr_bits++;
113144961713Sgirish }
113244961713Sgirish
113344961713Sgirish if (clr_bits) {
113444961713Sgirish NXGE_REG_WR64(handle, pre_offset, clr.value);
113544961713Sgirish }
113644961713Sgirish
113744961713Sgirish clr_bits = 0;
113844961713Sgirish NXGE_REG_RD64(handle, sha_offset, &clr.value);
113944961713Sgirish if (clr.bits.ldw.err) {
114044961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_RDC_CTL,
114152ccf843Smisaki " npi_rxdma_ring_perr_stat_get"
114252ccf843Smisaki " SHA ERR Bit set ..... clearing \n"));
114344961713Sgirish clr.bits.ldw.err = 0;
114444961713Sgirish clr_bits++;
114544961713Sgirish }
114644961713Sgirish
114744961713Sgirish if (clr.bits.ldw.merr) {
114844961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_RDC_CTL,
114952ccf843Smisaki " npi_rxdma_ring_perr_stat_get"
115052ccf843Smisaki " SHA MERR Bit set ..... clearing \n"));
115144961713Sgirish clr.bits.ldw.merr = 0;
115244961713Sgirish clr_bits++;
115344961713Sgirish }
115444961713Sgirish
115544961713Sgirish if (clr_bits) {
115644961713Sgirish NXGE_REG_WR64(handle, sha_offset, clr.value);
115744961713Sgirish }
115844961713Sgirish
115944961713Sgirish return (NPI_SUCCESS);
116044961713Sgirish }
116144961713Sgirish
1162a3c5bd6dSspeer /*
1163a3c5bd6dSspeer * Access the RDMC Memory: used for debugging
1164a3c5bd6dSspeer */
116544961713Sgirish npi_status_t
npi_rxdma_rdmc_memory_io(npi_handle_t handle,rdmc_mem_access_t * data,uint8_t op)116644961713Sgirish npi_rxdma_rdmc_memory_io(npi_handle_t handle,
116744961713Sgirish rdmc_mem_access_t *data, uint8_t op)
116844961713Sgirish {
116944961713Sgirish uint64_t d0_offset, d1_offset, d2_offset, d3_offset, d4_offset;
117044961713Sgirish uint64_t addr_offset;
117144961713Sgirish rdmc_mem_addr_t addr;
117244961713Sgirish rdmc_mem_data_t d0, d1, d2, d3, d4;
117344961713Sgirish d0.value = 0;
117444961713Sgirish d1.value = 0;
117544961713Sgirish d2.value = 0;
117644961713Sgirish d3.value = 0;
117744961713Sgirish d4.value = 0;
117844961713Sgirish addr.value = 0;
117944961713Sgirish
118044961713Sgirish
118144961713Sgirish if ((data->location != RDMC_MEM_ADDR_PREFETCH) &&
118252ccf843Smisaki (data->location != RDMC_MEM_ADDR_SHADOW)) {
118344961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
118452ccf843Smisaki " npi_rxdma_rdmc_memory_io"
118552ccf843Smisaki " Illegal memory Type %x \n",
118652ccf843Smisaki data->location));
118744961713Sgirish return (NPI_RXDMA_OPCODE_INVALID(0));
118844961713Sgirish }
118944961713Sgirish
119044961713Sgirish addr_offset = RDMC_MEM_ADDR_REG;
119144961713Sgirish addr.bits.ldw.addr = data->addr;
119244961713Sgirish addr.bits.ldw.pre_shad = data->location;
119344961713Sgirish
119444961713Sgirish d0_offset = RDMC_MEM_DATA0_REG;
119544961713Sgirish d1_offset = RDMC_MEM_DATA1_REG;
119644961713Sgirish d2_offset = RDMC_MEM_DATA2_REG;
119744961713Sgirish d3_offset = RDMC_MEM_DATA3_REG;
119844961713Sgirish d4_offset = RDMC_MEM_DATA4_REG;
119944961713Sgirish
120044961713Sgirish
120144961713Sgirish if (op == RDMC_MEM_WRITE) {
120244961713Sgirish d0.bits.ldw.data = data->data[0];
120344961713Sgirish d1.bits.ldw.data = data->data[1];
120444961713Sgirish d2.bits.ldw.data = data->data[2];
120544961713Sgirish d3.bits.ldw.data = data->data[3];
120644961713Sgirish d4.bits.ldw.data = data->data[4];
120744961713Sgirish NXGE_REG_WR64(handle, addr_offset, addr.value);
120844961713Sgirish NXGE_REG_WR64(handle, d0_offset, d0.value);
120944961713Sgirish NXGE_REG_WR64(handle, d1_offset, d1.value);
121044961713Sgirish NXGE_REG_WR64(handle, d2_offset, d2.value);
121144961713Sgirish NXGE_REG_WR64(handle, d3_offset, d3.value);
121244961713Sgirish NXGE_REG_WR64(handle, d4_offset, d4.value);
121344961713Sgirish }
121444961713Sgirish
121544961713Sgirish if (op == RDMC_MEM_READ) {
121644961713Sgirish NXGE_REG_WR64(handle, addr_offset, addr.value);
121744961713Sgirish NXGE_REG_RD64(handle, d4_offset, &d4.value);
121844961713Sgirish NXGE_REG_RD64(handle, d3_offset, &d3.value);
121944961713Sgirish NXGE_REG_RD64(handle, d2_offset, &d2.value);
122044961713Sgirish NXGE_REG_RD64(handle, d1_offset, &d1.value);
122144961713Sgirish NXGE_REG_RD64(handle, d0_offset, &d0.value);
122244961713Sgirish
122344961713Sgirish data->data[0] = d0.bits.ldw.data;
122444961713Sgirish data->data[1] = d1.bits.ldw.data;
122544961713Sgirish data->data[2] = d2.bits.ldw.data;
122644961713Sgirish data->data[3] = d3.bits.ldw.data;
122744961713Sgirish data->data[4] = d4.bits.ldw.data;
122844961713Sgirish } else {
122944961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
123052ccf843Smisaki " npi_rxdma_rdmc_memory_io"
123152ccf843Smisaki " Illegal opcode %x \n",
123252ccf843Smisaki op));
123344961713Sgirish return (NPI_RXDMA_OPCODE_INVALID(0));
123444961713Sgirish
123544961713Sgirish }
123644961713Sgirish
123744961713Sgirish return (NPI_SUCCESS);
123844961713Sgirish }
123944961713Sgirish
1240a3c5bd6dSspeer /*
1241a3c5bd6dSspeer * system wide conf functions
1242a3c5bd6dSspeer */
124344961713Sgirish npi_status_t
npi_rxdma_cfg_clock_div_set(npi_handle_t handle,uint16_t count)124444961713Sgirish npi_rxdma_cfg_clock_div_set(npi_handle_t handle, uint16_t count)
124544961713Sgirish {
124644961713Sgirish uint64_t offset;
124744961713Sgirish rx_dma_ck_div_t clk_div;
124844961713Sgirish
124944961713Sgirish offset = RX_DMA_CK_DIV_REG;
125044961713Sgirish
125144961713Sgirish clk_div.value = 0;
125244961713Sgirish clk_div.bits.ldw.cnt = count;
125344961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_RDC_CTL,
125452ccf843Smisaki " npi_rxdma_cfg_clock_div_set: add 0x%llx "
125552ccf843Smisaki "handle 0x%llx value 0x%llx",
125652ccf843Smisaki handle.regp, handle.regh, clk_div.value));
125744961713Sgirish
125844961713Sgirish NXGE_REG_WR64(handle, offset, clk_div.value);
125944961713Sgirish
126044961713Sgirish return (NPI_SUCCESS);
126144961713Sgirish }
126244961713Sgirish
126344961713Sgirish npi_status_t
npi_rxdma_cfg_red_rand_init(npi_handle_t handle,uint16_t init_value)126444961713Sgirish npi_rxdma_cfg_red_rand_init(npi_handle_t handle, uint16_t init_value)
126544961713Sgirish {
126644961713Sgirish uint64_t offset;
126744961713Sgirish red_ran_init_t rand_reg;
126844961713Sgirish
126944961713Sgirish offset = RED_RAN_INIT_REG;
127044961713Sgirish
127144961713Sgirish rand_reg.value = 0;
127244961713Sgirish rand_reg.bits.ldw.init = init_value;
127344961713Sgirish rand_reg.bits.ldw.enable = 1;
127444961713Sgirish NXGE_REG_WR64(handle, offset, rand_reg.value);
127544961713Sgirish
127644961713Sgirish return (NPI_SUCCESS);
127744961713Sgirish
127844961713Sgirish }
127944961713Sgirish
128044961713Sgirish npi_status_t
npi_rxdma_cfg_red_rand_disable(npi_handle_t handle)128144961713Sgirish npi_rxdma_cfg_red_rand_disable(npi_handle_t handle)
128244961713Sgirish {
128344961713Sgirish uint64_t offset;
128444961713Sgirish red_ran_init_t rand_reg;
128544961713Sgirish
128644961713Sgirish offset = RED_RAN_INIT_REG;
128744961713Sgirish
128844961713Sgirish NXGE_REG_RD64(handle, offset, &rand_reg.value);
128944961713Sgirish rand_reg.bits.ldw.enable = 0;
129044961713Sgirish NXGE_REG_WR64(handle, offset, rand_reg.value);
129144961713Sgirish
129244961713Sgirish return (NPI_SUCCESS);
129344961713Sgirish
129444961713Sgirish }
129544961713Sgirish
129644961713Sgirish npi_status_t
npi_rxdma_cfg_32bitmode_enable(npi_handle_t handle)129744961713Sgirish npi_rxdma_cfg_32bitmode_enable(npi_handle_t handle)
129844961713Sgirish {
129944961713Sgirish uint64_t offset;
130044961713Sgirish rx_addr_md_t md_reg;
130144961713Sgirish offset = RX_ADDR_MD_REG;
130244961713Sgirish md_reg.value = 0;
130344961713Sgirish md_reg.bits.ldw.mode32 = 1;
130444961713Sgirish
130544961713Sgirish NXGE_REG_WR64(handle, offset, md_reg.value);
130644961713Sgirish return (NPI_SUCCESS);
130744961713Sgirish
130844961713Sgirish }
130944961713Sgirish
131044961713Sgirish npi_status_t
npi_rxdma_cfg_32bitmode_disable(npi_handle_t handle)131144961713Sgirish npi_rxdma_cfg_32bitmode_disable(npi_handle_t handle)
131244961713Sgirish {
131344961713Sgirish uint64_t offset;
131444961713Sgirish rx_addr_md_t md_reg;
131544961713Sgirish offset = RX_ADDR_MD_REG;
131644961713Sgirish md_reg.value = 0;
131744961713Sgirish
131844961713Sgirish NXGE_REG_WR64(handle, offset, md_reg.value);
131944961713Sgirish return (NPI_SUCCESS);
132044961713Sgirish
132144961713Sgirish }
132244961713Sgirish
132344961713Sgirish npi_status_t
npi_rxdma_cfg_ram_access_enable(npi_handle_t handle)132444961713Sgirish npi_rxdma_cfg_ram_access_enable(npi_handle_t handle)
132544961713Sgirish {
132644961713Sgirish uint64_t offset;
132744961713Sgirish rx_addr_md_t md_reg;
132844961713Sgirish offset = RX_ADDR_MD_REG;
132944961713Sgirish NXGE_REG_RD64(handle, offset, &md_reg.value);
133044961713Sgirish md_reg.bits.ldw.ram_acc = 1;
133144961713Sgirish NXGE_REG_WR64(handle, offset, md_reg.value);
133244961713Sgirish return (NPI_SUCCESS);
133344961713Sgirish
133444961713Sgirish }
133544961713Sgirish
133644961713Sgirish npi_status_t
npi_rxdma_cfg_ram_access_disable(npi_handle_t handle)133744961713Sgirish npi_rxdma_cfg_ram_access_disable(npi_handle_t handle)
133844961713Sgirish {
133944961713Sgirish uint64_t offset;
134044961713Sgirish rx_addr_md_t md_reg;
134144961713Sgirish offset = RX_ADDR_MD_REG;
134244961713Sgirish NXGE_REG_RD64(handle, offset, &md_reg.value);
134344961713Sgirish md_reg.bits.ldw.ram_acc = 0;
134444961713Sgirish NXGE_REG_WR64(handle, offset, md_reg.value);
134544961713Sgirish return (NPI_SUCCESS);
134644961713Sgirish
134744961713Sgirish }
134844961713Sgirish
1349a3c5bd6dSspeer npi_status_t
npi_rxdma_cfg_port_ddr_weight(npi_handle_t handle,uint8_t portnm,uint32_t weight)1350a3c5bd6dSspeer npi_rxdma_cfg_port_ddr_weight(npi_handle_t handle,
135144961713Sgirish uint8_t portnm, uint32_t weight)
135244961713Sgirish {
135344961713Sgirish
135444961713Sgirish pt_drr_wt_t wt_reg;
135544961713Sgirish uint64_t offset;
1356a3c5bd6dSspeer
1357a3c5bd6dSspeer ASSERT(RXDMA_PORT_VALID(portnm));
135844961713Sgirish if (!RXDMA_PORT_VALID(portnm)) {
135944961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
136052ccf843Smisaki " rxdma_cfg_port_ddr_weight"
136152ccf843Smisaki " Illegal Port Number %d \n",
136252ccf843Smisaki portnm));
136344961713Sgirish return (NPI_RXDMA_PORT_INVALID);
136444961713Sgirish }
136544961713Sgirish
136644961713Sgirish offset = PT_DRR_WT_REG(portnm);
136744961713Sgirish wt_reg.value = 0;
136844961713Sgirish wt_reg.bits.ldw.wt = weight;
136944961713Sgirish NXGE_REG_WR64(handle, offset, wt_reg.value);
137044961713Sgirish return (NPI_SUCCESS);
137144961713Sgirish }
137244961713Sgirish
1373a3c5bd6dSspeer npi_status_t
npi_rxdma_port_usage_get(npi_handle_t handle,uint8_t portnm,uint32_t * blocks)1374a3c5bd6dSspeer npi_rxdma_port_usage_get(npi_handle_t handle,
137544961713Sgirish uint8_t portnm, uint32_t *blocks)
137644961713Sgirish {
137744961713Sgirish
137844961713Sgirish pt_use_t use_reg;
137944961713Sgirish uint64_t offset;
138044961713Sgirish
1381a3c5bd6dSspeer ASSERT(RXDMA_PORT_VALID(portnm));
138244961713Sgirish if (!RXDMA_PORT_VALID(portnm)) {
138344961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
138452ccf843Smisaki " rxdma_port_usage_get"
138552ccf843Smisaki " Illegal Port Number %d \n",
138652ccf843Smisaki portnm));
138744961713Sgirish return (NPI_RXDMA_PORT_INVALID);
138844961713Sgirish }
138944961713Sgirish
139044961713Sgirish offset = PT_USE_REG(portnm);
139144961713Sgirish NXGE_REG_RD64(handle, offset, &use_reg.value);
139244961713Sgirish *blocks = use_reg.bits.ldw.cnt;
139344961713Sgirish return (NPI_SUCCESS);
139444961713Sgirish
139544961713Sgirish }
139644961713Sgirish
1397a3c5bd6dSspeer npi_status_t
npi_rxdma_cfg_wred_param(npi_handle_t handle,uint8_t rdc,rdc_red_para_t * wred_params)1398a3c5bd6dSspeer npi_rxdma_cfg_wred_param(npi_handle_t handle, uint8_t rdc,
139944961713Sgirish rdc_red_para_t *wred_params)
140044961713Sgirish {
140144961713Sgirish rdc_red_para_t wred_reg;
140244961713Sgirish uint64_t offset;
140344961713Sgirish
1404a3c5bd6dSspeer ASSERT(RXDMA_CHANNEL_VALID(rdc));
140544961713Sgirish if (!RXDMA_CHANNEL_VALID(rdc)) {
140644961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
140752ccf843Smisaki " rxdma_cfg_wred_param"
140852ccf843Smisaki " Illegal RDC Number %d \n",
140952ccf843Smisaki rdc));
141044961713Sgirish return (NPI_RXDMA_RDC_INVALID);
141144961713Sgirish }
141244961713Sgirish
141344961713Sgirish /*
141444961713Sgirish * need to update RDC_RED_PARA_REG as well as bit defs in
141544961713Sgirish * the hw header file
141644961713Sgirish */
141744961713Sgirish offset = RDC_RED_RDC_PARA_REG(rdc);
141844961713Sgirish
141944961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_RDC_CTL,
142052ccf843Smisaki " npi_rxdma_cfg_wred_param: "
142152ccf843Smisaki "set RED_PARA: passed value 0x%llx "
142252ccf843Smisaki "win 0x%x thre 0x%x sync 0x%x thre_sync 0x%x",
142352ccf843Smisaki wred_params->value,
142452ccf843Smisaki wred_params->bits.ldw.win,
142552ccf843Smisaki wred_params->bits.ldw.thre,
142652ccf843Smisaki wred_params->bits.ldw.win_syn,
142752ccf843Smisaki wred_params->bits.ldw.thre_sync));
142844961713Sgirish
142944961713Sgirish wred_reg.value = 0;
143044961713Sgirish wred_reg.bits.ldw.win = wred_params->bits.ldw.win;
143144961713Sgirish wred_reg.bits.ldw.thre = wred_params->bits.ldw.thre;
143244961713Sgirish wred_reg.bits.ldw.win_syn = wred_params->bits.ldw.win_syn;
143344961713Sgirish wred_reg.bits.ldw.thre_sync = wred_params->bits.ldw.thre_sync;
143444961713Sgirish NXGE_REG_WR64(handle, offset, wred_reg.value);
143544961713Sgirish
143644961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_RDC_CTL,
143752ccf843Smisaki "set RED_PARA: value 0x%llx "
143852ccf843Smisaki "win 0x%x thre 0x%x sync 0x%x thre_sync 0x%x",
143952ccf843Smisaki wred_reg.value,
144052ccf843Smisaki wred_reg.bits.ldw.win,
144152ccf843Smisaki wred_reg.bits.ldw.thre,
144252ccf843Smisaki wred_reg.bits.ldw.win_syn,
144352ccf843Smisaki wred_reg.bits.ldw.thre_sync));
144444961713Sgirish
144544961713Sgirish return (NPI_SUCCESS);
144644961713Sgirish }
144744961713Sgirish
144844961713Sgirish /*
1449678453a8Sspeer * npi_rxdma_rdc_table_config()
145044961713Sgirish * Configure/populate the RDC table
145144961713Sgirish *
145244961713Sgirish * Inputs:
1453678453a8Sspeer * handle: register handle interpreted by the underlying OS
1454678453a8Sspeer * table: RDC Group Number
1455678453a8Sspeer * map: A bitmap of the RDCs to populate with.
1456678453a8Sspeer * count: A count of the RDCs expressed in <map>.
1457678453a8Sspeer *
1458678453a8Sspeer * Notes:
1459678453a8Sspeer * This function assumes that we are not using the TCAM, but are
1460678453a8Sspeer * hashing all fields of the incoming ethernet packet!
146144961713Sgirish *
146244961713Sgirish * Return:
1463678453a8Sspeer * NPI_SUCCESS
1464678453a8Sspeer * NPI_RXDMA_TABLE_INVALID
146544961713Sgirish *
146644961713Sgirish */
146744961713Sgirish npi_status_t
npi_rxdma_rdc_table_config(npi_handle_t handle,uint8_t table,dc_map_t rdc_map,int count)1468678453a8Sspeer npi_rxdma_rdc_table_config(
1469678453a8Sspeer npi_handle_t handle,
1470678453a8Sspeer uint8_t table,
1471678453a8Sspeer dc_map_t rdc_map,
1472678453a8Sspeer int count)
147344961713Sgirish {
1474678453a8Sspeer int8_t set[NXGE_MAX_RDCS];
1475678453a8Sspeer int i, cursor;
1476678453a8Sspeer
1477678453a8Sspeer rdc_tbl_t rdc_tbl;
147844961713Sgirish uint64_t offset;
147944961713Sgirish
1480a3c5bd6dSspeer ASSERT(RXDMA_TABLE_VALID(table));
148144961713Sgirish if (!RXDMA_TABLE_VALID(table)) {
148244961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
148352ccf843Smisaki " npi_rxdma_cfg_rdc_table"
148452ccf843Smisaki " Illegal RDC Table Number %d \n",
148552ccf843Smisaki table));
148644961713Sgirish return (NPI_RXDMA_TABLE_INVALID);
148744961713Sgirish }
148844961713Sgirish
1489678453a8Sspeer if (count == 0) /* This shouldn't happen */
1490678453a8Sspeer return (NPI_SUCCESS);
1491678453a8Sspeer
1492678453a8Sspeer for (i = 0, cursor = 0; i < NXGE_MAX_RDCS; i++) {
1493678453a8Sspeer if ((1 << i) & rdc_map) {
1494678453a8Sspeer set[cursor++] = (int8_t)i;
1495678453a8Sspeer if (cursor == count)
1496678453a8Sspeer break;
1497678453a8Sspeer }
1498678453a8Sspeer }
1499678453a8Sspeer
1500678453a8Sspeer rdc_tbl.value = 0;
150144961713Sgirish offset = REG_RDC_TABLE_OFFSET(table);
1502678453a8Sspeer
1503678453a8Sspeer /* Now write ( NXGE_MAX_RDCS / count ) sets of RDC numbers. */
1504678453a8Sspeer for (i = 0, cursor = 0; i < NXGE_MAX_RDCS; i++) {
1505678453a8Sspeer rdc_tbl.bits.ldw.rdc = set[cursor++];
1506678453a8Sspeer NXGE_REG_WR64(handle, offset, rdc_tbl.value);
1507678453a8Sspeer offset += sizeof (rdc_tbl.value);
1508678453a8Sspeer if (cursor == count)
1509678453a8Sspeer cursor = 0;
151044961713Sgirish }
151144961713Sgirish
1512678453a8Sspeer /*
1513678453a8Sspeer * Here is what the resulting table looks like with:
1514678453a8Sspeer *
1515678453a8Sspeer * 0 1 2 3 4 5 6 7 8 9 a b c d e f
1516678453a8Sspeer * +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
1517678453a8Sspeer * |v |w |x |y |z |v |w |x |y |z |v |w |x |y |z |v | 5 RDCs
1518678453a8Sspeer * +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
1519678453a8Sspeer * |w |x |y |z |w |x |y |z |w |x |y |z |w |x |y |z | 4 RDCs
1520678453a8Sspeer * +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
1521678453a8Sspeer * |x |y |z |x |y |z |x |y |z |x |y |z |x |y |z |x | 3 RDCs
1522678453a8Sspeer * +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
1523678453a8Sspeer * |x |y |x |y |x |y |x |y |x |y |x |y |x |y |x |y | 2 RDCs
1524678453a8Sspeer * +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
1525678453a8Sspeer * |x |x |x |x |x |x |x |x |x |x |x |x |x |x |x |x | 1 RDC
1526678453a8Sspeer * +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
1527678453a8Sspeer */
152844961713Sgirish
1529678453a8Sspeer return (NPI_SUCCESS);
153044961713Sgirish }
153144961713Sgirish
153244961713Sgirish npi_status_t
npi_rxdma_cfg_rdc_table_default_rdc(npi_handle_t handle,uint8_t table,uint8_t rdc)153344961713Sgirish npi_rxdma_cfg_rdc_table_default_rdc(npi_handle_t handle,
153444961713Sgirish uint8_t table, uint8_t rdc)
153544961713Sgirish {
153644961713Sgirish uint64_t offset;
153744961713Sgirish rdc_tbl_t tbl_reg;
153844961713Sgirish tbl_reg.value = 0;
153944961713Sgirish
1540a3c5bd6dSspeer ASSERT(RXDMA_TABLE_VALID(table));
154144961713Sgirish if (!RXDMA_TABLE_VALID(table)) {
154244961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
154352ccf843Smisaki " npi_rxdma_cfg_rdc_table"
154452ccf843Smisaki " Illegal RDC table Number %d \n",
154552ccf843Smisaki rdc));
154644961713Sgirish return (NPI_RXDMA_TABLE_INVALID);
154744961713Sgirish }
154844961713Sgirish
154944961713Sgirish offset = REG_RDC_TABLE_OFFSET(table);
155044961713Sgirish tbl_reg.bits.ldw.rdc = rdc;
155144961713Sgirish NXGE_REG_WR64(handle, offset, tbl_reg.value);
155244961713Sgirish return (NPI_SUCCESS);
155344961713Sgirish
155444961713Sgirish }
155544961713Sgirish
155644961713Sgirish npi_status_t
npi_rxdma_dump_rdc_table(npi_handle_t handle,uint8_t table)155744961713Sgirish npi_rxdma_dump_rdc_table(npi_handle_t handle,
155844961713Sgirish uint8_t table)
155944961713Sgirish {
156044961713Sgirish uint64_t offset;
156144961713Sgirish int tbl_offset;
156244961713Sgirish uint64_t value;
156344961713Sgirish
1564a3c5bd6dSspeer ASSERT(RXDMA_TABLE_VALID(table));
156544961713Sgirish if (!RXDMA_TABLE_VALID(table)) {
156644961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
156752ccf843Smisaki " npi_rxdma_dump_rdc_table"
156852ccf843Smisaki " Illegal RDC Rable Number %d \n",
156952ccf843Smisaki table));
157044961713Sgirish return (NPI_RXDMA_TABLE_INVALID);
157144961713Sgirish }
157244961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
157352ccf843Smisaki "\n Register Dump for RDC Table %d \n",
157452ccf843Smisaki table));
157544961713Sgirish offset = REG_RDC_TABLE_OFFSET(table);
157644961713Sgirish for (tbl_offset = 0; tbl_offset < NXGE_MAX_RDCS; tbl_offset++) {
157744961713Sgirish NXGE_REG_RD64(handle, offset, &value);
157844961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
157952ccf843Smisaki " 0x%08llx 0x%08llx \n",
158052ccf843Smisaki offset, value));
158144961713Sgirish offset += 8;
158244961713Sgirish }
158344961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
158452ccf843Smisaki "\n Register Dump for RDC Table %d done\n",
158552ccf843Smisaki table));
158644961713Sgirish return (NPI_SUCCESS);
158744961713Sgirish
158844961713Sgirish }
158944961713Sgirish
159044961713Sgirish npi_status_t
npi_rxdma_rdc_rbr_stat_get(npi_handle_t handle,uint8_t rdc,rbr_stat_t * rbr_stat)159144961713Sgirish npi_rxdma_rdc_rbr_stat_get(npi_handle_t handle, uint8_t rdc,
159244961713Sgirish rbr_stat_t *rbr_stat)
159344961713Sgirish {
159444961713Sgirish
1595a3c5bd6dSspeer ASSERT(RXDMA_CHANNEL_VALID(rdc));
159644961713Sgirish if (!RXDMA_CHANNEL_VALID(rdc)) {
159744961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
159852ccf843Smisaki " rxdma_rdc_rbr_stat_get"
159952ccf843Smisaki " Illegal RDC Number %d \n",
160052ccf843Smisaki rdc));
160144961713Sgirish return (NPI_RXDMA_RDC_INVALID);
160244961713Sgirish }
160344961713Sgirish
160444961713Sgirish RXDMA_REG_READ64(handle, RBR_STAT_REG, rdc, &rbr_stat->value);
160544961713Sgirish return (NPI_SUCCESS);
160644961713Sgirish }
160744961713Sgirish
160844961713Sgirish /*
160944961713Sgirish * npi_rxdma_rdc_rbr_head_get
161044961713Sgirish * Gets the current rbr head pointer.
161144961713Sgirish *
161244961713Sgirish * Inputs:
1613a3c5bd6dSspeer * handle: opaque handle interpreted by the underlying OS
161444961713Sgirish * rdc: RX DMA Channel number
161544961713Sgirish * hdptr ptr to write the rbr head value
161644961713Sgirish *
161744961713Sgirish * Return:
1618a3c5bd6dSspeer * NPI_SUCCESS
1619a3c5bd6dSspeer * NPI_RXDMA_RDC_INVALID
162044961713Sgirish */
1621a3c5bd6dSspeer npi_status_t
npi_rxdma_rdc_rbr_head_get(npi_handle_t handle,uint8_t rdc,addr44_t * hdptr)1622a3c5bd6dSspeer npi_rxdma_rdc_rbr_head_get(npi_handle_t handle,
162344961713Sgirish uint8_t rdc, addr44_t *hdptr)
162444961713Sgirish {
162544961713Sgirish rbr_hdh_t hh_ptr;
162644961713Sgirish rbr_hdl_t hl_ptr;
162744961713Sgirish
1628a3c5bd6dSspeer ASSERT(RXDMA_CHANNEL_VALID(rdc));
162944961713Sgirish if (!RXDMA_CHANNEL_VALID(rdc)) {
163044961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
163152ccf843Smisaki " rxdma_rdc_rbr_head_get"
163252ccf843Smisaki " Illegal RDC Number %d \n",
163352ccf843Smisaki rdc));
163444961713Sgirish return (NPI_RXDMA_RDC_INVALID);
163544961713Sgirish }
163644961713Sgirish hh_ptr.value = 0;
163744961713Sgirish hl_ptr.value = 0;
163844961713Sgirish RXDMA_REG_READ64(handle, RBR_HDH_REG, rdc, &hh_ptr.value);
163944961713Sgirish RXDMA_REG_READ64(handle, RBR_HDL_REG, rdc, &hl_ptr.value);
164044961713Sgirish hdptr->bits.ldw = hl_ptr.bits.ldw.head_l << 2;
164144961713Sgirish hdptr->bits.hdw = hh_ptr.bits.ldw.head_h;
164244961713Sgirish return (NPI_SUCCESS);
164344961713Sgirish
164444961713Sgirish }
164544961713Sgirish
164644961713Sgirish npi_status_t
npi_rxdma_rdc_rcr_qlen_get(npi_handle_t handle,uint8_t rdc,uint16_t * rcr_qlen)164744961713Sgirish npi_rxdma_rdc_rcr_qlen_get(npi_handle_t handle, uint8_t rdc,
164844961713Sgirish uint16_t *rcr_qlen)
164944961713Sgirish {
165044961713Sgirish
165144961713Sgirish rcrstat_a_t stats;
1652a3c5bd6dSspeer
1653a3c5bd6dSspeer ASSERT(RXDMA_CHANNEL_VALID(rdc));
165444961713Sgirish if (!RXDMA_CHANNEL_VALID(rdc)) {
165544961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
165652ccf843Smisaki " rxdma_rdc_rcr_qlen_get"
165752ccf843Smisaki " Illegal RDC Number %d \n",
165852ccf843Smisaki rdc));
165944961713Sgirish return (NPI_RXDMA_RDC_INVALID);
166044961713Sgirish }
166144961713Sgirish
166244961713Sgirish RXDMA_REG_READ64(handle, RCRSTAT_A_REG, rdc, &stats.value);
166344961713Sgirish *rcr_qlen = stats.bits.ldw.qlen;
166444961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_RDC_CTL,
166552ccf843Smisaki " rxdma_rdc_rcr_qlen_get"
166652ccf843Smisaki " RDC %d qlen %x qlen %x\n",
166752ccf843Smisaki rdc, *rcr_qlen, stats.bits.ldw.qlen));
166844961713Sgirish return (NPI_SUCCESS);
166944961713Sgirish }
167044961713Sgirish
167144961713Sgirish npi_status_t
npi_rxdma_rdc_rcr_tail_get(npi_handle_t handle,uint8_t rdc,addr44_t * tail_addr)167244961713Sgirish npi_rxdma_rdc_rcr_tail_get(npi_handle_t handle,
167344961713Sgirish uint8_t rdc, addr44_t *tail_addr)
167444961713Sgirish {
167544961713Sgirish
167644961713Sgirish rcrstat_b_t th_ptr;
167744961713Sgirish rcrstat_c_t tl_ptr;
167844961713Sgirish
1679a3c5bd6dSspeer ASSERT(RXDMA_CHANNEL_VALID(rdc));
168044961713Sgirish if (!RXDMA_CHANNEL_VALID(rdc)) {
168144961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
168252ccf843Smisaki " rxdma_rdc_rcr_tail_get"
168352ccf843Smisaki " Illegal RDC Number %d \n",
168452ccf843Smisaki rdc));
168544961713Sgirish return (NPI_RXDMA_RDC_INVALID);
168644961713Sgirish }
168744961713Sgirish th_ptr.value = 0;
168844961713Sgirish tl_ptr.value = 0;
168944961713Sgirish RXDMA_REG_READ64(handle, RCRSTAT_B_REG, rdc, &th_ptr.value);
169044961713Sgirish RXDMA_REG_READ64(handle, RCRSTAT_C_REG, rdc, &tl_ptr.value);
169144961713Sgirish tail_addr->bits.ldw = tl_ptr.bits.ldw.tlptr_l << 3;
169244961713Sgirish tail_addr->bits.hdw = th_ptr.bits.ldw.tlptr_h;
169344961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_RDC_CTL,
169452ccf843Smisaki " rxdma_rdc_rcr_tail_get"
169552ccf843Smisaki " RDC %d rcr_tail %llx tl %x\n",
169652ccf843Smisaki rdc, tl_ptr.value,
169752ccf843Smisaki tl_ptr.bits.ldw.tlptr_l));
169844961713Sgirish
169944961713Sgirish return (NPI_SUCCESS);
170044961713Sgirish
170144961713Sgirish
170244961713Sgirish }
170344961713Sgirish
170444961713Sgirish /*
170544961713Sgirish * npi_rxdma_rxctl_fifo_error_intr_set
170644961713Sgirish * Configure The RX ctrl fifo error interrupt generation
170744961713Sgirish *
170844961713Sgirish * Inputs:
1709a3c5bd6dSspeer * handle: opaque handle interpreted by the underlying OS
171044961713Sgirish * mask: rx_ctl_dat_fifo_mask_t specifying the errors
171144961713Sgirish * valid fields in rx_ctl_dat_fifo_mask_t structure are:
171244961713Sgirish * zcp_eop_err, ipp_eop_err, id_mismatch. If a field is set
171344961713Sgirish * to 1, we will enable interrupt generation for the
171444961713Sgirish * corresponding error condition. In the hardware, the bit(s)
171544961713Sgirish * have to be cleared to enable interrupt.
171644961713Sgirish *
171744961713Sgirish * Return:
171844961713Sgirish * NPI_SUCCESS
171944961713Sgirish *
172044961713Sgirish */
172144961713Sgirish npi_status_t
npi_rxdma_rxctl_fifo_error_intr_set(npi_handle_t handle,rx_ctl_dat_fifo_mask_t * mask)172244961713Sgirish npi_rxdma_rxctl_fifo_error_intr_set(npi_handle_t handle,
172344961713Sgirish rx_ctl_dat_fifo_mask_t *mask)
172444961713Sgirish {
172544961713Sgirish uint64_t offset;
172644961713Sgirish rx_ctl_dat_fifo_mask_t intr_mask;
172744961713Sgirish offset = RX_CTL_DAT_FIFO_MASK_REG;
172844961713Sgirish NXGE_REG_RD64(handle, offset, &intr_mask.value);
172944961713Sgirish
173044961713Sgirish if (mask->bits.ldw.ipp_eop_err) {
173144961713Sgirish intr_mask.bits.ldw.ipp_eop_err = 0;
173244961713Sgirish }
173344961713Sgirish
173444961713Sgirish if (mask->bits.ldw.zcp_eop_err) {
173544961713Sgirish intr_mask.bits.ldw.zcp_eop_err = 0;
173644961713Sgirish }
173744961713Sgirish
173844961713Sgirish if (mask->bits.ldw.id_mismatch) {
173944961713Sgirish intr_mask.bits.ldw.id_mismatch = 0;
174044961713Sgirish }
174144961713Sgirish
174244961713Sgirish NXGE_REG_WR64(handle, offset, intr_mask.value);
174344961713Sgirish return (NPI_SUCCESS);
174444961713Sgirish }
174544961713Sgirish
174644961713Sgirish /*
174744961713Sgirish * npi_rxdma_rxctl_fifo_error_stat_get
174844961713Sgirish * Read The RX ctrl fifo error Status
174944961713Sgirish *
175044961713Sgirish * Inputs:
1751a3c5bd6dSspeer * handle: opaque handle interpreted by the underlying OS
175244961713Sgirish * stat: rx_ctl_dat_fifo_stat_t to read the errors to
175344961713Sgirish * valid fields in rx_ctl_dat_fifo_stat_t structure are:
175444961713Sgirish * zcp_eop_err, ipp_eop_err, id_mismatch.
175544961713Sgirish * Return:
175644961713Sgirish * NPI_SUCCESS
175744961713Sgirish *
175844961713Sgirish */
175944961713Sgirish npi_status_t
npi_rxdma_rxctl_fifo_error_intr_get(npi_handle_t handle,rx_ctl_dat_fifo_stat_t * stat)176044961713Sgirish npi_rxdma_rxctl_fifo_error_intr_get(npi_handle_t handle,
176144961713Sgirish rx_ctl_dat_fifo_stat_t *stat)
176244961713Sgirish {
176344961713Sgirish uint64_t offset = RX_CTL_DAT_FIFO_STAT_REG;
176444961713Sgirish NXGE_REG_RD64(handle, offset, &stat->value);
176544961713Sgirish return (NPI_SUCCESS);
176644961713Sgirish }
176744961713Sgirish
176844961713Sgirish npi_status_t
npi_rxdma_rdc_rcr_pktread_update(npi_handle_t handle,uint8_t channel,uint16_t pkts_read)176944961713Sgirish npi_rxdma_rdc_rcr_pktread_update(npi_handle_t handle, uint8_t channel,
177044961713Sgirish uint16_t pkts_read)
177144961713Sgirish {
177244961713Sgirish
177344961713Sgirish rx_dma_ctl_stat_t cs;
177444961713Sgirish uint16_t min_read = 0;
1775a3c5bd6dSspeer
1776a3c5bd6dSspeer ASSERT(RXDMA_CHANNEL_VALID(channel));
177744961713Sgirish if (!RXDMA_CHANNEL_VALID(channel)) {
177844961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
177944961713Sgirish " npi_rxdma_rdc_rcr_pktread_update ",
178044961713Sgirish " channel %d", channel));
178144961713Sgirish return (NPI_FAILURE | NPI_RXDMA_CHANNEL_INVALID(channel));
178244961713Sgirish }
178344961713Sgirish
178444961713Sgirish if ((pkts_read < min_read) && (pkts_read > 512)) {
178544961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
178644961713Sgirish " npi_rxdma_rdc_rcr_pktread_update ",
178744961713Sgirish " pkts %d out of bound", pkts_read));
178844961713Sgirish return (NPI_RXDMA_OPCODE_INVALID(pkts_read));
178944961713Sgirish }
179044961713Sgirish
179144961713Sgirish RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel,
179252ccf843Smisaki &cs.value);
179344961713Sgirish cs.bits.ldw.pktread = pkts_read;
179444961713Sgirish RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG,
179552ccf843Smisaki channel, cs.value);
179644961713Sgirish
179744961713Sgirish return (NPI_SUCCESS);
179844961713Sgirish }
179944961713Sgirish
180044961713Sgirish npi_status_t
npi_rxdma_rdc_rcr_bufread_update(npi_handle_t handle,uint8_t channel,uint16_t bufs_read)180144961713Sgirish npi_rxdma_rdc_rcr_bufread_update(npi_handle_t handle, uint8_t channel,
180244961713Sgirish uint16_t bufs_read)
180344961713Sgirish {
180444961713Sgirish
180544961713Sgirish rx_dma_ctl_stat_t cs;
180644961713Sgirish uint16_t min_read = 0;
1807a3c5bd6dSspeer
1808a3c5bd6dSspeer ASSERT(RXDMA_CHANNEL_VALID(channel));
180944961713Sgirish if (!RXDMA_CHANNEL_VALID(channel)) {
181044961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
181144961713Sgirish " npi_rxdma_rdc_rcr_bufread_update ",
181244961713Sgirish " channel %d", channel));
181344961713Sgirish return (NPI_FAILURE | NPI_RXDMA_CHANNEL_INVALID(channel));
181444961713Sgirish }
181544961713Sgirish
181644961713Sgirish if ((bufs_read < min_read) && (bufs_read > 512)) {
181744961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
181844961713Sgirish " npi_rxdma_rdc_rcr_bufread_update ",
181944961713Sgirish " bufs read %d out of bound", bufs_read));
182044961713Sgirish return (NPI_RXDMA_OPCODE_INVALID(bufs_read));
182144961713Sgirish }
182244961713Sgirish
182344961713Sgirish RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel,
182452ccf843Smisaki &cs.value);
182544961713Sgirish cs.bits.ldw.ptrread = bufs_read;
182644961713Sgirish RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG,
182752ccf843Smisaki channel, cs.value);
182844961713Sgirish
182944961713Sgirish return (NPI_SUCCESS);
183044961713Sgirish }
183144961713Sgirish
183244961713Sgirish npi_status_t
npi_rxdma_rdc_rcr_read_update(npi_handle_t handle,uint8_t channel,uint16_t pkts_read,uint16_t bufs_read)183344961713Sgirish npi_rxdma_rdc_rcr_read_update(npi_handle_t handle, uint8_t channel,
183444961713Sgirish uint16_t pkts_read, uint16_t bufs_read)
183544961713Sgirish {
183644961713Sgirish
183744961713Sgirish rx_dma_ctl_stat_t cs;
183844961713Sgirish
1839a3c5bd6dSspeer ASSERT(RXDMA_CHANNEL_VALID(channel));
184044961713Sgirish if (!RXDMA_CHANNEL_VALID(channel)) {
184144961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
184244961713Sgirish " npi_rxdma_rdc_rcr_read_update ",
184344961713Sgirish " channel %d", channel));
184444961713Sgirish return (NPI_FAILURE | NPI_RXDMA_CHANNEL_INVALID(channel));
184544961713Sgirish }
184644961713Sgirish
184744961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_RDC_CTL,
184844961713Sgirish " npi_rxdma_rdc_rcr_read_update "
184944961713Sgirish " bufs read %d pkt read %d",
185052ccf843Smisaki bufs_read, pkts_read));
185144961713Sgirish
185244961713Sgirish RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel,
185352ccf843Smisaki &cs.value);
185444961713Sgirish
185544961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_RDC_CTL,
185652ccf843Smisaki " npi_rxdma_rdc_rcr_read_update: "
185752ccf843Smisaki " value: 0x%llx bufs read %d pkt read %d",
185852ccf843Smisaki cs.value,
185952ccf843Smisaki cs.bits.ldw.ptrread, cs.bits.ldw.pktread));
186044961713Sgirish
186144961713Sgirish cs.bits.ldw.pktread = pkts_read;
186244961713Sgirish cs.bits.ldw.ptrread = bufs_read;
186344961713Sgirish
186444961713Sgirish RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG,
186552ccf843Smisaki channel, cs.value);
186644961713Sgirish
186744961713Sgirish RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel,
186852ccf843Smisaki &cs.value);
186944961713Sgirish
187044961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_RDC_CTL,
187144961713Sgirish " npi_rxdma_rdc_rcr_read_update: read back after update "
187244961713Sgirish " value: 0x%llx bufs read %d pkt read %d",
187352ccf843Smisaki cs.value,
187452ccf843Smisaki cs.bits.ldw.ptrread, cs.bits.ldw.pktread));
187544961713Sgirish
187644961713Sgirish return (NPI_SUCCESS);
187744961713Sgirish }
187844961713Sgirish
187944961713Sgirish /*
188044961713Sgirish * npi_rxdma_channel_mex_set():
188144961713Sgirish * This function is called to arm the DMA channel with
188244961713Sgirish * mailbox updating capability. Software needs to rearm
188344961713Sgirish * for each update by writing to the control and status register.
188444961713Sgirish *
188544961713Sgirish * Parameters:
188644961713Sgirish * handle - NPI handle (virtualization flag must be defined).
188744961713Sgirish * channel - logical RXDMA channel from 0 to 23.
188844961713Sgirish * (If virtualization flag is not set, then
188944961713Sgirish * logical channel is the same as the hardware
189044961713Sgirish * channel number).
189144961713Sgirish *
189244961713Sgirish * Return:
189344961713Sgirish * NPI_SUCCESS - If enable channel with mailbox update
1894a3c5bd6dSspeer * is completed successfully.
189544961713Sgirish *
189644961713Sgirish * Error:
1897a3c5bd6dSspeer * NPI error status code
189844961713Sgirish */
189944961713Sgirish npi_status_t
npi_rxdma_channel_mex_set(npi_handle_t handle,uint8_t channel)190044961713Sgirish npi_rxdma_channel_mex_set(npi_handle_t handle, uint8_t channel)
190144961713Sgirish {
190244961713Sgirish return (npi_rxdma_channel_control(handle, RXDMA_MEX_SET, channel));
190344961713Sgirish }
190444961713Sgirish
190544961713Sgirish /*
190644961713Sgirish * npi_rxdma_channel_rcrto_clear():
190744961713Sgirish * This function is called to reset RCRTO bit to 0.
190844961713Sgirish *
190944961713Sgirish * Parameters:
191044961713Sgirish * handle - NPI handle (virtualization flag must be defined).
191144961713Sgirish * channel - logical RXDMA channel from 0 to 23.
191244961713Sgirish * (If virtualization flag is not set, then
191344961713Sgirish * logical channel is the same as the hardware
191444961713Sgirish * channel number).
191544961713Sgirish * Return:
191644961713Sgirish * NPI_SUCCESS
191744961713Sgirish *
191844961713Sgirish * Error:
1919a3c5bd6dSspeer * NPI error status code
192044961713Sgirish */
192144961713Sgirish npi_status_t
npi_rxdma_channel_rcrto_clear(npi_handle_t handle,uint8_t channel)192244961713Sgirish npi_rxdma_channel_rcrto_clear(npi_handle_t handle, uint8_t channel)
192344961713Sgirish {
192444961713Sgirish return (npi_rxdma_channel_control(handle, RXDMA_RCRTO_CLEAR, channel));
192544961713Sgirish }
192644961713Sgirish
192744961713Sgirish /*
192844961713Sgirish * npi_rxdma_channel_pt_drop_pkt_clear():
192944961713Sgirish * This function is called to clear the port drop packet bit (debug).
193044961713Sgirish *
193144961713Sgirish * Parameters:
193244961713Sgirish * handle - NPI handle (virtualization flag must be defined).
193344961713Sgirish * channel - logical RXDMA channel from 0 to 23.
193444961713Sgirish * (If virtualization flag is not set, then
193544961713Sgirish * logical channel is the same as the hardware
193644961713Sgirish * channel number).
193744961713Sgirish * Return:
193844961713Sgirish * NPI_SUCCESS
193944961713Sgirish *
194044961713Sgirish * Error:
1941a3c5bd6dSspeer * NPI error status code
194244961713Sgirish */
194344961713Sgirish npi_status_t
npi_rxdma_channel_pt_drop_pkt_clear(npi_handle_t handle,uint8_t channel)194444961713Sgirish npi_rxdma_channel_pt_drop_pkt_clear(npi_handle_t handle, uint8_t channel)
194544961713Sgirish {
194644961713Sgirish return (npi_rxdma_channel_control(handle, RXDMA_PT_DROP_PKT_CLEAR,
194752ccf843Smisaki channel));
194844961713Sgirish }
194944961713Sgirish
195044961713Sgirish /*
195144961713Sgirish * npi_rxdma_channel_wred_drop_clear():
195244961713Sgirish * This function is called to wred drop bit (debug only).
195344961713Sgirish *
195444961713Sgirish * Parameters:
195544961713Sgirish * handle - NPI handle (virtualization flag must be defined).
195644961713Sgirish * channel - logical RXDMA channel from 0 to 23.
195744961713Sgirish * (If virtualization flag is not set, then
195844961713Sgirish * logical channel is the same as the hardware
195944961713Sgirish * channel number).
196044961713Sgirish * Return:
196144961713Sgirish * NPI_SUCCESS
196244961713Sgirish *
196344961713Sgirish * Error:
1964a3c5bd6dSspeer * NPI error status code
196544961713Sgirish */
196644961713Sgirish npi_status_t
npi_rxdma_channel_wred_dop_clear(npi_handle_t handle,uint8_t channel)196744961713Sgirish npi_rxdma_channel_wred_dop_clear(npi_handle_t handle, uint8_t channel)
196844961713Sgirish {
196944961713Sgirish return (npi_rxdma_channel_control(handle, RXDMA_WRED_DROP_CLEAR,
197052ccf843Smisaki channel));
197144961713Sgirish }
197244961713Sgirish
197344961713Sgirish /*
197444961713Sgirish * npi_rxdma_channel_rcr_shfull_clear():
197544961713Sgirish * This function is called to clear RCR shadow full bit.
197644961713Sgirish *
197744961713Sgirish * Parameters:
197844961713Sgirish * handle - NPI handle (virtualization flag must be defined).
197944961713Sgirish * channel - logical RXDMA channel from 0 to 23.
198044961713Sgirish * (If virtualization flag is not set, then
198144961713Sgirish * logical channel is the same as the hardware
198244961713Sgirish * channel number).
198344961713Sgirish * Return:
198444961713Sgirish * NPI_SUCCESS
198544961713Sgirish *
198644961713Sgirish * Error:
1987a3c5bd6dSspeer * NPI error status code
198844961713Sgirish */
198944961713Sgirish npi_status_t
npi_rxdma_channel_rcr_shfull_clear(npi_handle_t handle,uint8_t channel)199044961713Sgirish npi_rxdma_channel_rcr_shfull_clear(npi_handle_t handle, uint8_t channel)
199144961713Sgirish {
199244961713Sgirish return (npi_rxdma_channel_control(handle, RXDMA_RCR_SFULL_CLEAR,
199352ccf843Smisaki channel));
199444961713Sgirish }
199544961713Sgirish
199644961713Sgirish /*
199744961713Sgirish * npi_rxdma_channel_rcrfull_clear():
199844961713Sgirish * This function is called to clear RCR full bit.
199944961713Sgirish *
200044961713Sgirish * Parameters:
200144961713Sgirish * handle - NPI handle (virtualization flag must be defined).
200244961713Sgirish * channel - logical RXDMA channel from 0 to 23.
200344961713Sgirish * (If virtualization flag is not set, then
200444961713Sgirish * logical channel is the same as the hardware
200544961713Sgirish * channel number).
200644961713Sgirish * Return:
200744961713Sgirish * NPI_SUCCESS
200844961713Sgirish *
200944961713Sgirish * Error:
2010a3c5bd6dSspeer * NPI error status code
201144961713Sgirish */
201244961713Sgirish npi_status_t
npi_rxdma_channel_rcr_full_clear(npi_handle_t handle,uint8_t channel)201344961713Sgirish npi_rxdma_channel_rcr_full_clear(npi_handle_t handle, uint8_t channel)
201444961713Sgirish {
201544961713Sgirish return (npi_rxdma_channel_control(handle, RXDMA_RCR_FULL_CLEAR,
201652ccf843Smisaki channel));
201744961713Sgirish }
201844961713Sgirish
201944961713Sgirish npi_status_t
npi_rxdma_channel_rbr_empty_clear(npi_handle_t handle,uint8_t channel)202044961713Sgirish npi_rxdma_channel_rbr_empty_clear(npi_handle_t handle, uint8_t channel)
202144961713Sgirish {
202244961713Sgirish return (npi_rxdma_channel_control(handle,
202352ccf843Smisaki RXDMA_RBR_EMPTY_CLEAR, channel));
202444961713Sgirish }
202544961713Sgirish
202644961713Sgirish npi_status_t
npi_rxdma_channel_cs_clear_all(npi_handle_t handle,uint8_t channel)202744961713Sgirish npi_rxdma_channel_cs_clear_all(npi_handle_t handle, uint8_t channel)
202844961713Sgirish {
202944961713Sgirish return (npi_rxdma_channel_control(handle, RXDMA_CS_CLEAR_ALL, channel));
203044961713Sgirish }
203144961713Sgirish
203244961713Sgirish /*
203344961713Sgirish * npi_rxdma_channel_control():
203444961713Sgirish * This function is called to control a receive DMA channel
203544961713Sgirish * for arming the channel with mailbox updates, resetting
203644961713Sgirish * various event status bits (control and status register).
203744961713Sgirish *
203844961713Sgirish * Parameters:
203944961713Sgirish * handle - NPI handle (virtualization flag must be defined).
204044961713Sgirish * control - NPI defined control type supported:
204144961713Sgirish * - RXDMA_MEX_SET
204244961713Sgirish * - RXDMA_RCRTO_CLEAR
204344961713Sgirish * - RXDMA_PT_DROP_PKT_CLEAR
204444961713Sgirish * - RXDMA_WRED_DROP_CLEAR
204544961713Sgirish * - RXDMA_RCR_SFULL_CLEAR
204644961713Sgirish * - RXDMA_RCR_FULL_CLEAR
204744961713Sgirish * - RXDMA_RBR_PRE_EMPTY_CLEAR
204844961713Sgirish * - RXDMA_RBR_EMPTY_CLEAR
204944961713Sgirish * channel - logical RXDMA channel from 0 to 23.
205044961713Sgirish * (If virtualization flag is not set, then
205144961713Sgirish * logical channel is the same as the hardware.
205244961713Sgirish * Return:
205344961713Sgirish * NPI_SUCCESS
205444961713Sgirish *
205544961713Sgirish * Error:
2056a3c5bd6dSspeer * NPI error status code
205744961713Sgirish */
205844961713Sgirish npi_status_t
npi_rxdma_channel_control(npi_handle_t handle,rxdma_cs_cntl_t control,uint8_t channel)205944961713Sgirish npi_rxdma_channel_control(npi_handle_t handle, rxdma_cs_cntl_t control,
206044961713Sgirish uint8_t channel)
206144961713Sgirish {
206244961713Sgirish
206344961713Sgirish rx_dma_ctl_stat_t cs;
206444961713Sgirish
2065a3c5bd6dSspeer ASSERT(RXDMA_CHANNEL_VALID(channel));
206644961713Sgirish if (!RXDMA_CHANNEL_VALID(channel)) {
206744961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
206844961713Sgirish " npi_rxdma_channel_control",
206944961713Sgirish " channel", channel));
207044961713Sgirish return (NPI_FAILURE | NPI_RXDMA_CHANNEL_INVALID(channel));
207144961713Sgirish }
207244961713Sgirish
207344961713Sgirish switch (control) {
207444961713Sgirish case RXDMA_MEX_SET:
207544961713Sgirish RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel,
207652ccf843Smisaki &cs.value);
207744961713Sgirish cs.bits.hdw.mex = 1;
207844961713Sgirish RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG,
207952ccf843Smisaki channel, cs.value);
208044961713Sgirish break;
208144961713Sgirish
208244961713Sgirish case RXDMA_RCRTO_CLEAR:
208344961713Sgirish RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel,
208452ccf843Smisaki &cs.value);
208544961713Sgirish cs.bits.hdw.rcrto = 0;
208644961713Sgirish RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel,
208752ccf843Smisaki cs.value);
208844961713Sgirish break;
208944961713Sgirish
209044961713Sgirish case RXDMA_PT_DROP_PKT_CLEAR:
209144961713Sgirish RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel,
209252ccf843Smisaki &cs.value);
209344961713Sgirish cs.bits.hdw.port_drop_pkt = 0;
209444961713Sgirish RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel,
209552ccf843Smisaki cs.value);
209644961713Sgirish break;
209744961713Sgirish
209844961713Sgirish case RXDMA_WRED_DROP_CLEAR:
209944961713Sgirish RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel,
210052ccf843Smisaki &cs.value);
210144961713Sgirish cs.bits.hdw.wred_drop = 0;
210244961713Sgirish RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel,
210352ccf843Smisaki cs.value);
210444961713Sgirish break;
210544961713Sgirish
210644961713Sgirish case RXDMA_RCR_SFULL_CLEAR:
210744961713Sgirish RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel,
210852ccf843Smisaki &cs.value);
210944961713Sgirish cs.bits.hdw.rcr_shadow_full = 0;
211044961713Sgirish RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel,
211152ccf843Smisaki cs.value);
211244961713Sgirish break;
211344961713Sgirish
211444961713Sgirish case RXDMA_RCR_FULL_CLEAR:
211544961713Sgirish RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel,
211652ccf843Smisaki &cs.value);
211744961713Sgirish cs.bits.hdw.rcrfull = 0;
211844961713Sgirish RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel,
211952ccf843Smisaki cs.value);
212044961713Sgirish break;
212144961713Sgirish
212244961713Sgirish case RXDMA_RBR_PRE_EMPTY_CLEAR:
212344961713Sgirish RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel,
212452ccf843Smisaki &cs.value);
212544961713Sgirish cs.bits.hdw.rbr_pre_empty = 0;
212644961713Sgirish RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel,
212752ccf843Smisaki cs.value);
212844961713Sgirish break;
212944961713Sgirish
213044961713Sgirish case RXDMA_RBR_EMPTY_CLEAR:
213144961713Sgirish RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel,
213252ccf843Smisaki &cs.value);
213344961713Sgirish cs.bits.hdw.rbr_empty = 1;
213444961713Sgirish RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel,
213552ccf843Smisaki cs.value);
213644961713Sgirish break;
213744961713Sgirish
213844961713Sgirish case RXDMA_CS_CLEAR_ALL:
213944961713Sgirish cs.value = 0;
214044961713Sgirish RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel,
214152ccf843Smisaki cs.value);
214244961713Sgirish break;
214344961713Sgirish
214444961713Sgirish default:
214544961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
214652ccf843Smisaki "npi_rxdma_channel_control",
214752ccf843Smisaki "control", control));
214844961713Sgirish return (NPI_FAILURE | NPI_RXDMA_OPCODE_INVALID(channel));
214944961713Sgirish }
215044961713Sgirish
215144961713Sgirish return (NPI_SUCCESS);
215244961713Sgirish }
215344961713Sgirish
215444961713Sgirish /*
215544961713Sgirish * npi_rxdma_control_status():
215644961713Sgirish * This function is called to operate on the control
215744961713Sgirish * and status register.
215844961713Sgirish *
215944961713Sgirish * Parameters:
216044961713Sgirish * handle - NPI handle
216144961713Sgirish * op_mode - OP_GET: get hardware control and status
216244961713Sgirish * OP_SET: set hardware control and status
216344961713Sgirish * OP_UPDATE: update hardware control and status.
216444961713Sgirish * OP_CLEAR: clear control and status register to 0s.
216544961713Sgirish * channel - hardware RXDMA channel from 0 to 23.
216644961713Sgirish * cs_p - pointer to hardware defined control and status
216744961713Sgirish * structure.
216844961713Sgirish * Return:
216944961713Sgirish * NPI_SUCCESS
217044961713Sgirish *
217144961713Sgirish * Error:
2172a3c5bd6dSspeer * NPI error status code
217344961713Sgirish */
217444961713Sgirish npi_status_t
npi_rxdma_control_status(npi_handle_t handle,io_op_t op_mode,uint8_t channel,p_rx_dma_ctl_stat_t cs_p)217544961713Sgirish npi_rxdma_control_status(npi_handle_t handle, io_op_t op_mode,
217644961713Sgirish uint8_t channel, p_rx_dma_ctl_stat_t cs_p)
217744961713Sgirish {
217844961713Sgirish int status = NPI_SUCCESS;
217944961713Sgirish rx_dma_ctl_stat_t cs;
218044961713Sgirish
2181a3c5bd6dSspeer ASSERT(RXDMA_CHANNEL_VALID(channel));
218244961713Sgirish if (!RXDMA_CHANNEL_VALID(channel)) {
218344961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
218444961713Sgirish "npi_rxdma_control_status",
218544961713Sgirish "channel", channel));
218644961713Sgirish return (NPI_FAILURE | NPI_RXDMA_CHANNEL_INVALID(channel));
218744961713Sgirish }
218844961713Sgirish
218944961713Sgirish switch (op_mode) {
219044961713Sgirish case OP_GET:
219144961713Sgirish RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel,
219252ccf843Smisaki &cs_p->value);
219344961713Sgirish break;
219444961713Sgirish
219544961713Sgirish case OP_SET:
219644961713Sgirish RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel,
219752ccf843Smisaki cs_p->value);
219844961713Sgirish break;
219944961713Sgirish
220044961713Sgirish case OP_UPDATE:
220144961713Sgirish RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel,
220252ccf843Smisaki &cs.value);
220344961713Sgirish RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel,
220452ccf843Smisaki cs_p->value | cs.value);
220544961713Sgirish break;
220644961713Sgirish
220744961713Sgirish default:
220844961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
220944961713Sgirish "npi_rxdma_control_status",
221044961713Sgirish "control", op_mode));
221144961713Sgirish return (NPI_FAILURE | NPI_RXDMA_OPCODE_INVALID(channel));
221244961713Sgirish }
221344961713Sgirish
221444961713Sgirish return (status);
221544961713Sgirish }
221644961713Sgirish
221744961713Sgirish /*
221844961713Sgirish * npi_rxdma_event_mask():
221944961713Sgirish * This function is called to operate on the event mask
222044961713Sgirish * register which is used for generating interrupts.
222144961713Sgirish *
222244961713Sgirish * Parameters:
222344961713Sgirish * handle - NPI handle
222444961713Sgirish * op_mode - OP_GET: get hardware event mask
222544961713Sgirish * OP_SET: set hardware interrupt event masks
222644961713Sgirish * OP_CLEAR: clear control and status register to 0s.
222744961713Sgirish * channel - hardware RXDMA channel from 0 to 23.
222844961713Sgirish * mask_p - pointer to hardware defined event mask
222944961713Sgirish * structure.
223044961713Sgirish * Return:
223144961713Sgirish * NPI_SUCCESS - If set is complete successfully.
223244961713Sgirish *
223344961713Sgirish * Error:
2234a3c5bd6dSspeer * NPI error status code
223544961713Sgirish */
223644961713Sgirish npi_status_t
npi_rxdma_event_mask(npi_handle_t handle,io_op_t op_mode,uint8_t channel,p_rx_dma_ent_msk_t mask_p)223744961713Sgirish npi_rxdma_event_mask(npi_handle_t handle, io_op_t op_mode,
223844961713Sgirish uint8_t channel, p_rx_dma_ent_msk_t mask_p)
223944961713Sgirish {
224044961713Sgirish int status = NPI_SUCCESS;
224144961713Sgirish rx_dma_ent_msk_t mask;
224244961713Sgirish
2243a3c5bd6dSspeer ASSERT(RXDMA_CHANNEL_VALID(channel));
224444961713Sgirish if (!RXDMA_CHANNEL_VALID(channel)) {
224544961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
224644961713Sgirish "npi_rxdma_event_mask",
224744961713Sgirish "channel", channel));
224844961713Sgirish return (NPI_FAILURE | NPI_RXDMA_CHANNEL_INVALID(channel));
224944961713Sgirish }
225044961713Sgirish
225144961713Sgirish switch (op_mode) {
225244961713Sgirish case OP_GET:
225344961713Sgirish RXDMA_REG_READ64(handle, RX_DMA_ENT_MSK_REG, channel,
225452ccf843Smisaki &mask_p->value);
225544961713Sgirish break;
225644961713Sgirish
225744961713Sgirish case OP_SET:
225844961713Sgirish RXDMA_REG_WRITE64(handle, RX_DMA_ENT_MSK_REG, channel,
225952ccf843Smisaki mask_p->value);
226044961713Sgirish break;
226144961713Sgirish
226244961713Sgirish case OP_UPDATE:
226344961713Sgirish RXDMA_REG_READ64(handle, RX_DMA_ENT_MSK_REG, channel,
226452ccf843Smisaki &mask.value);
226544961713Sgirish RXDMA_REG_WRITE64(handle, RX_DMA_ENT_MSK_REG, channel,
226652ccf843Smisaki mask_p->value | mask.value);
226744961713Sgirish break;
226844961713Sgirish
226944961713Sgirish default:
227044961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
227144961713Sgirish "npi_rxdma_event_mask",
227244961713Sgirish "eventmask", op_mode));
227344961713Sgirish return (NPI_FAILURE | NPI_RXDMA_OPCODE_INVALID(channel));
227444961713Sgirish }
227544961713Sgirish
227644961713Sgirish return (status);
227744961713Sgirish }
227844961713Sgirish
227944961713Sgirish /*
228044961713Sgirish * npi_rxdma_event_mask_config():
228144961713Sgirish * This function is called to operate on the event mask
228244961713Sgirish * register which is used for generating interrupts
228344961713Sgirish * and status register.
228444961713Sgirish *
228544961713Sgirish * Parameters:
228644961713Sgirish * handle - NPI handle
228744961713Sgirish * op_mode - OP_GET: get hardware event mask
228844961713Sgirish * OP_SET: set hardware interrupt event masks
228944961713Sgirish * OP_CLEAR: clear control and status register to 0s.
229044961713Sgirish * channel - hardware RXDMA channel from 0 to 23.
2291a3c5bd6dSspeer * mask_cfgp - pointer to NPI defined event mask
229244961713Sgirish * enum data type.
229344961713Sgirish * Return:
229444961713Sgirish * NPI_SUCCESS - If set is complete successfully.
229544961713Sgirish *
229644961713Sgirish * Error:
2297a3c5bd6dSspeer * NPI error status code
229844961713Sgirish */
229944961713Sgirish npi_status_t
npi_rxdma_event_mask_config(npi_handle_t handle,io_op_t op_mode,uint8_t channel,rxdma_ent_msk_cfg_t * mask_cfgp)230044961713Sgirish npi_rxdma_event_mask_config(npi_handle_t handle, io_op_t op_mode,
230144961713Sgirish uint8_t channel, rxdma_ent_msk_cfg_t *mask_cfgp)
230244961713Sgirish {
230344961713Sgirish int status = NPI_SUCCESS;
2304678453a8Sspeer uint64_t configuration = *mask_cfgp;
230544961713Sgirish uint64_t value;
230644961713Sgirish
2307a3c5bd6dSspeer ASSERT(RXDMA_CHANNEL_VALID(channel));
230844961713Sgirish if (!RXDMA_CHANNEL_VALID(channel)) {
230944961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
231044961713Sgirish "npi_rxdma_event_mask_config",
231144961713Sgirish "channel", channel));
231244961713Sgirish return (NPI_FAILURE | NPI_RXDMA_CHANNEL_INVALID(channel));
231344961713Sgirish }
231444961713Sgirish
231544961713Sgirish switch (op_mode) {
231644961713Sgirish case OP_GET:
231744961713Sgirish RXDMA_REG_READ64(handle, RX_DMA_ENT_MSK_REG, channel,
2318678453a8Sspeer (uint64_t *)mask_cfgp);
231944961713Sgirish break;
232044961713Sgirish
232144961713Sgirish case OP_SET:
232244961713Sgirish RXDMA_REG_WRITE64(handle, RX_DMA_ENT_MSK_REG, channel,
2323678453a8Sspeer configuration);
232444961713Sgirish break;
232544961713Sgirish
232644961713Sgirish case OP_UPDATE:
232744961713Sgirish RXDMA_REG_READ64(handle, RX_DMA_ENT_MSK_REG, channel, &value);
232844961713Sgirish RXDMA_REG_WRITE64(handle, RX_DMA_ENT_MSK_REG, channel,
2329678453a8Sspeer configuration | value);
233044961713Sgirish break;
233144961713Sgirish
233244961713Sgirish case OP_CLEAR:
233344961713Sgirish RXDMA_REG_WRITE64(handle, RX_DMA_ENT_MSK_REG, channel,
2334678453a8Sspeer CFG_RXDMA_MASK_ALL);
233544961713Sgirish break;
233644961713Sgirish default:
233744961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
233844961713Sgirish "npi_rxdma_event_mask_config",
233944961713Sgirish "eventmask", op_mode));
234044961713Sgirish return (NPI_FAILURE | NPI_RXDMA_OPCODE_INVALID(channel));
234144961713Sgirish }
234244961713Sgirish
234344961713Sgirish return (status);
234444961713Sgirish }
2345