1*678453a8Sspeer /*
2*678453a8Sspeer  * CDDL HEADER START
3*678453a8Sspeer  *
4*678453a8Sspeer  * The contents of this file are subject to the terms of the
5*678453a8Sspeer  * Common Development and Distribution License (the "License").
6*678453a8Sspeer  * You may not use this file except in compliance with the License.
7*678453a8Sspeer  *
8*678453a8Sspeer  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*678453a8Sspeer  * or http://www.opensolaris.org/os/licensing.
10*678453a8Sspeer  * See the License for the specific language governing permissions
11*678453a8Sspeer  * and limitations under the License.
12*678453a8Sspeer  *
13*678453a8Sspeer  * When distributing Covered Code, include this CDDL HEADER in each
14*678453a8Sspeer  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*678453a8Sspeer  * If applicable, add the following below this CDDL HEADER, with the
16*678453a8Sspeer  * fields enclosed by brackets "[]" replaced with your own identifying
17*678453a8Sspeer  * information: Portions Copyright [yyyy] [name of copyright owner]
18*678453a8Sspeer  *
19*678453a8Sspeer  * CDDL HEADER END
20*678453a8Sspeer  */
21*678453a8Sspeer /*
22*678453a8Sspeer  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23*678453a8Sspeer  * Use is subject to license terms.
24*678453a8Sspeer  */
25*678453a8Sspeer 
26*678453a8Sspeer #ifndef _NPI_RX_WR64_H
27*678453a8Sspeer #define	_NPI_RX_WR64_H
28*678453a8Sspeer 
29*678453a8Sspeer #pragma ident	"%Z%%M%	%I%	%E% SMI"
30*678453a8Sspeer 
31*678453a8Sspeer #ifdef	__cplusplus
32*678453a8Sspeer extern "C" {
33*678453a8Sspeer #endif
34*678453a8Sspeer 
35*678453a8Sspeer #include <npi.h>
36*678453a8Sspeer 
37*678453a8Sspeer /*
38*678453a8Sspeer  * RXDMA_REG_WRITE64
39*678453a8Sspeer  *
40*678453a8Sspeer  *	Write a 64-bit value to a DMC register.
41*678453a8Sspeer  *
42*678453a8Sspeer  * This is the old, rather convoluted,  macro.
43*678453a8Sspeer  *
44*678453a8Sspeer  * #define RXDMA_REG_WRITE64(handle, reg, channel, data) {	\
45*678453a8Sspeer  *	NXGE_REG_WR64(handle, (NXGE_RXDMA_OFFSET(reg, handle.is_vraddr,\
46*678453a8Sspeer  *	channel)), (data))				       \
47*678453a8Sspeer  *
48*678453a8Sspeer  * There are 3 versions of NXGE_REG_WR64:
49*678453a8Sspeer  * -------------------------------------------------------------
50*678453a8Sspeer  * #if defined(REG_TRACE)
51*678453a8Sspeer  * #define	NXGE_REG_WR64(handle, offset, val) {	\
52*678453a8Sspeer  * 	NXGE_NPI_PIO_WRITE64(handle, (offset), (val));			\
53*678453a8Sspeer  * 	npi_rtrace_update(handle, B_TRUE, &npi_rtracebuf, (uint32_t)offset, \
54*678453a8Sspeer  * 				(uint64_t)(val));			\
55*678453a8Sspeer  * }
56*678453a8Sspeer  * #elif defined(REG_SHOW)
57*678453a8Sspeer  * #define	NXGE_REG_WR64(handle, offset, val) {\
58*678453a8Sspeer  * 	NXGE_NPI_PIO_WRITE64(handle, offset, (val));\
59*678453a8Sspeer  * 	rt_show_reg(0xbadbad, B_TRUE, (uint32_t)offset, (uint64_t)(val));\
60*678453a8Sspeer  * }
61*678453a8Sspeer  * #else
62*678453a8Sspeer  * #define	NXGE_REG_WR64(handle, offset, val) {\
63*678453a8Sspeer  * 	NXGE_NPI_PIO_WRITE64(handle, (offset), (val));\
64*678453a8Sspeer  * }
65*678453a8Sspeer  * #endif
66*678453a8Sspeer  *
67*678453a8Sspeer  * There are 2 versions of NXGE_NPI_PIO_WRITE64:
68*678453a8Sspeer  * -------------------------------------------------------------
69*678453a8Sspeer  * #if defined(__i386)
70*678453a8Sspeer  * #define	NXGE_NPI_PIO_WRITE64(npi_handle, offset, data)	\
71*678453a8Sspeer  * 	(ddi_put64(NPI_REGH(npi_handle),		\
72*678453a8Sspeer  * 	(uint64_t *)(NPI_REGP(npi_handle) + (uint32_t)offset), data))
73*678453a8Sspeer  * #else
74*678453a8Sspeer  * #define	NXGE_NPI_PIO_WRITE64(npi_handle, offset, data)	\
75*678453a8Sspeer  * 	(ddi_put64(NPI_REGH(npi_handle),		\
76*678453a8Sspeer  * 	(uint64_t *)(NPI_REGP(npi_handle) + offset), data))
77*678453a8Sspeer  * #endif
78*678453a8Sspeer  *
79*678453a8Sspeer  * -------------------------------------------------------------
80*678453a8Sspeer  * #define	NPI_REGH(npi_handle)		(npi_handle.regh)
81*678453a8Sspeer  * #define	NPI_REGP(npi_handle)		(npi_handle.regp)
82*678453a8Sspeer  *
83*678453a8Sspeer  * Now let's tackle NXGE_RXDMA_OFFSET
84*678453a8Sspeer  * -------------------------------------------------------------
85*678453a8Sspeer  * #define	NXGE_RXDMA_OFFSET(x, v, channel) (x + \
86*678453a8Sspeer  * 		(!v ? DMC_OFFSET(channel) : \
87*678453a8Sspeer  *			RDMC_PIOVADDR_OFFSET(channel)))
88*678453a8Sspeer  *
89*678453a8Sspeer  * -------------------------------------------------------------
90*678453a8Sspeer  * #define	DMC_OFFSET(channel)	(DMA_CSR_SIZE * channel)
91*678453a8Sspeer  *
92*678453a8Sspeer  * #define	TDMC_PIOVADDR_OFFSET(channel)	(2 * DMA_CSR_SIZE * channel)
93*678453a8Sspeer  * -------------------------------------------------------------
94*678453a8Sspeer  * #define	RDMC_PIOVADDR_OFFSET(channel) \
95*678453a8Sspeer  *			(TDMC_OFFSET(channel) + DMA_CSR_SIZE)
96*678453a8Sspeer  * -------------------------------------------------------------
97*678453a8Sspeer  * #define	DMA_CSR_SIZE		512
98*678453a8Sspeer  *
99*678453a8Sspeer  * #define TDMC_OFFSET(channel)	(TX_RNG_CFIG + DMA_CSR_SIZE * channel)
100*678453a8Sspeer  * #define TX_RNG_CFIG		(DMC + 0x40000)
101*678453a8Sspeer  * -------------------------------------------------------------
102*678453a8Sspeer  * This definition is clearly wrong!  I think this was intended:
103*678453a8Sspeer  *
104*678453a8Sspeer  * #define	RDMC_PIOVADDR_OFFSET(channel) \
105*678453a8Sspeer  *			(TDMC_PIOVADDR__OFFSET(channel) + DMA_CSR_SIZE)
106*678453a8Sspeer  * -------------------------------------------------------------
107*678453a8Sspeer  *
108*678453a8Sspeer  * Finally, we have the full macro:
109*678453a8Sspeer  * -------------------------------------------------------------
110*678453a8Sspeer  * #define RXDMA_REG_WRITE64(handle, reg, channel, data) {	\
111*678453a8Sspeer  *	NXGE_REG_WR64(handle, (NXGE_RXDMA_OFFSET(reg, handle.is_vraddr,\
112*678453a8Sspeer  *	channel)), (data))				       \
113*678453a8Sspeer  *
114*678453a8Sspeer  * ddi_put64(handle.regh, (uint64_t*)(handle.regp + ((0x600000 + 0x00000) +
115*678453a8Sspeer  *	(!handle.is_vraddr ?
116*678453a8Sspeer  *		(512 * channel) :
117*678453a8Sspeer  *		(0x600000 + 0x40000 + 512 * channel + 512))), data);
118*678453a8Sspeer  */
119*678453a8Sspeer 
120*678453a8Sspeer static void RXDMA_REG_WRITE64(npi_handle_t, uint64_t, int, uint64_t);
121*678453a8Sspeer #pragma inline(RXDMA_REG_WRITE64)
122*678453a8Sspeer 
123*678453a8Sspeer /*
124*678453a8Sspeer  * RXDMA_REG_WRITE64
125*678453a8Sspeer  *
126*678453a8Sspeer  *	Write a 64-bit value to a DMC register.
127*678453a8Sspeer  *
128*678453a8Sspeer  * Arguments:
129*678453a8Sspeer  * 	handle	The NPI handle to use.
130*678453a8Sspeer  * 	offset	The offset into the DMA CSR (the register).
131*678453a8Sspeer  * 	channel	The channel, which is used as a multiplicand.
132*678453a8Sspeer  * 	value	The 64-bit value to write.
133*678453a8Sspeer  *
134*678453a8Sspeer  * Notes:
135*678453a8Sspeer  *	If handle.regp is a virtual address (the address of a VR),
136*678453a8Sspeer  *	we have to subtract the value DMC right off the bat.  DMC
137*678453a8Sspeer  *	is defined as 0x600000, which works in a non-virtual address
138*678453a8Sspeer  *	space, but not in a VR.  In a VR, a DMA CSR's space begins
139*678453a8Sspeer  *	at zero (0).  So, since every call to RXMDA_REG_READ64 uses
140*678453a8Sspeer  *	a register macro which adds in DMC, we have to subtract it.
141*678453a8Sspeer  *
142*678453a8Sspeer  *	The rest of it is pretty straighforward.  In a VR, a channel is
143*678453a8Sspeer  *	logical, not absolute; and every DMA CSR is 512 bytes big;
144*678453a8Sspeer  *	furthermore, a subpage of a VR is always ordered with the
145*678453a8Sspeer  *	transmit CSRs first, followed by the receive CSRs.  That is,
146*678453a8Sspeer  *	a 512 byte space of Tx CSRs, followed by a 512 byte space of
147*678453a8Sspeer  *	Rx CSRs.  Hence this calculation:
148*678453a8Sspeer  *
149*678453a8Sspeer  *	offset += ((channel << 1) + 1) << DMA_CSR_SLL;
150*678453a8Sspeer  *
151*678453a8Sspeer  *	Here's an example:
152*678453a8Sspeer  *
153*678453a8Sspeer  *	RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel, value);
154*678453a8Sspeer  *	Let's say channel is 3
155*678453a8Sspeer  *	#define	RX_DMA_CTL_STAT_REG	(DMC + 0x00070)
156*678453a8Sspeer  *	offset = 0x600070
157*678453a8Sspeer  *	offset &= 0xff = 0x70
158*678453a8Sspeer  *	offset += ((3 << 1) + 1) << 9
159*678453a8Sspeer  *	3 << 1 = 6
160*678453a8Sspeer  *	6 + 1 = 7
161*678453a8Sspeer  *	7 << 9 = 0xe00
162*678453a8Sspeer  *	offset += 0xe00 = 0xe70
163*678453a8Sspeer  *
164*678453a8Sspeer  *	Therefore, our register's (virtual) PIO address is 0xe70.
165*678453a8Sspeer  *
166*678453a8Sspeer  *	cf. Table 10-6 on page 181 of the Neptune PRM, v 1.4:
167*678453a8Sspeer  *
168*678453a8Sspeer  *	E00 - FFF CSRs for bound logical receive DMA channel 3.
169*678453a8Sspeer  *
170*678453a8Sspeer  *	In a non-virtual environment, you simply multiply the absolute
171*678453a8Sspeer  *	channel number by 512 bytes, and get the correct offset to
172*678453a8Sspeer  *	the register you're looking for.  That is, the RX_DMA_CTL_STAT CSR,
173*678453a8Sspeer  *	is, as are all of these registers, in a table where each channel
174*678453a8Sspeer  *	is offset 512 bytes from the previous channel (count 16 step 512).
175*678453a8Sspeer  *
176*678453a8Sspeer  *	offset += (channel << DMA_CSR_SLL);	// channel<<9 = channel*512
177*678453a8Sspeer  *
178*678453a8Sspeer  *	Here's an example:
179*678453a8Sspeer  *
180*678453a8Sspeer  *	RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel, value);
181*678453a8Sspeer  *	Let's say channel is 3
182*678453a8Sspeer  *	#define	RX_DMA_CTL_STAT_REG	(DMC + 0x00070)
183*678453a8Sspeer  *	offset = 0x600070
184*678453a8Sspeer  *	offset += (3 << 9)
185*678453a8Sspeer  *	3 << 9 = 0x600
186*678453a8Sspeer  *	offset += 0x600 = 0x600670
187*678453a8Sspeer  *
188*678453a8Sspeer  *	Therefore, our register's PIO address is 0x600670.
189*678453a8Sspeer  *
190*678453a8Sspeer  *	cf. Table 12-42 on page 234 of the Neptune PRM, v 1.4:
191*678453a8Sspeer  *	RX_DMA_CTL_STAT (DMC + [0x]00070) (count 16 step [0x]200)
192*678453a8Sspeer  *
193*678453a8Sspeer  * Context:
194*678453a8Sspeer  *	Any domain
195*678453a8Sspeer  *
196*678453a8Sspeer  */
197*678453a8Sspeer extern const char *nxge_rx2str(int);
198*678453a8Sspeer 
199*678453a8Sspeer void
RXDMA_REG_WRITE64(npi_handle_t handle,uint64_t offset,int channel,uint64_t value)200*678453a8Sspeer RXDMA_REG_WRITE64(
201*678453a8Sspeer 	npi_handle_t handle,
202*678453a8Sspeer 	uint64_t offset,
203*678453a8Sspeer 	int channel,
204*678453a8Sspeer 	uint64_t value)
205*678453a8Sspeer {
206*678453a8Sspeer #if defined(NPI_REG_TRACE)
207*678453a8Sspeer 	const char *name = nxge_rx2str((int)offset);
208*678453a8Sspeer #endif
209*678453a8Sspeer 	if (handle.is_vraddr) {
210*678453a8Sspeer 		offset &= DMA_CSR_MASK;
211*678453a8Sspeer 		offset += (((channel << 1) + 1) << DMA_CSR_SLL);
212*678453a8Sspeer 	} else {
213*678453a8Sspeer 		offset += (channel << DMA_CSR_SLL);
214*678453a8Sspeer 	}
215*678453a8Sspeer 
216*678453a8Sspeer #if defined(__i386)
217*678453a8Sspeer 	ddi_put64(handle.regh,
218*678453a8Sspeer 	    (uint64_t *)(handle.regp + (uint32_t)offset), value);
219*678453a8Sspeer #else
220*678453a8Sspeer 	ddi_put64(handle.regh,
221*678453a8Sspeer 	    (uint64_t *)(handle.regp + offset), value);
222*678453a8Sspeer #endif
223*678453a8Sspeer 
224*678453a8Sspeer #if defined(NPI_REG_TRACE)
225*678453a8Sspeer 	npi_trace_update(handle, B_TRUE, &npi_rtracebuf,
226*678453a8Sspeer 	    name, (uint32_t)offset, value);
227*678453a8Sspeer #elif defined(REG_SHOW)
228*678453a8Sspeer 	/*
229*678453a8Sspeer 	 * Since we don't have a valid RTBUF index to show, send 0xBADBAD.
230*678453a8Sspeer 	 */
231*678453a8Sspeer 	rt_show_reg(0xbadbad, B_TRUE, (uint32_t)offset, value);
232*678453a8Sspeer #endif
233*678453a8Sspeer }
234*678453a8Sspeer 
235*678453a8Sspeer #ifdef	__cplusplus
236*678453a8Sspeer }
237*678453a8Sspeer #endif
238*678453a8Sspeer 
239*678453a8Sspeer #endif	/* _NPI_RX_WR64_H */
240