1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _NPI_MAC_H 27 #define _NPI_MAC_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <npi.h> 36 #include <nxge_mac_hw.h> 37 #include <nxge_mii.h> 38 39 typedef struct _npi_mac_addr { 40 uint16_t w0; 41 uint16_t w1; 42 uint16_t w2; 43 } npi_mac_addr_t; 44 45 typedef enum npi_mac_attr { 46 MAC_PORT_MODE = 0, 47 MAC_PORT_FRAME_SIZE, 48 MAC_PORT_ADDR, 49 MAC_PORT_ADDR_FILTER, 50 MAC_PORT_ADDR_FILTER_MASK, 51 XMAC_PORT_IPG, 52 XMAC_10G_PORT_IPG, 53 BMAC_PORT_MAX_BURST_SIZE, 54 BMAC_PORT_PA_SIZE, 55 BMAC_PORT_CTRL_TYPE 56 } npi_mac_attr_t; 57 58 /* MAC Mode options */ 59 60 typedef enum npi_mac_mode_e { 61 MAC_MII_MODE = 0, 62 MAC_GMII_MODE, 63 MAC_XGMII_MODE 64 } npi_mac_mode_t; 65 66 typedef enum npi_mac_reset_e { 67 TX_MAC_RESET = 1, 68 RX_MAC_RESET, 69 XTX_MAC_REG_RESET, 70 XRX_MAC_REG_RESET, 71 XTX_MAC_LOGIC_RESET, 72 XRX_MAC_LOGIC_RESET, 73 XTX_MAC_RESET_ALL, 74 XRX_MAC_RESET_ALL, 75 BMAC_RESET_ALL, 76 XMAC_RESET_ALL 77 } npi_mac_reset_t; 78 79 typedef enum xmac_tx_iconfig_e { 80 ICFG_XMAC_TX_FRAME_XMIT = XMAC_TX_FRAME_XMIT, 81 ICFG_XMAC_TX_UNDERRUN = XMAC_TX_UNDERRUN, 82 ICFG_XMAC_TX_MAX_PACKET_ERR = XMAC_TX_MAX_PACKET_ERR, 83 ICFG_XMAC_TX_OVERFLOW = XMAC_TX_OVERFLOW, 84 ICFG_XMAC_TX_FIFO_XFR_ERR = XMAC_TX_FIFO_XFR_ERR, 85 ICFG_XMAC_TX_BYTE_CNT_EXP = XMAC_TX_BYTE_CNT_EXP, 86 ICFG_XMAC_TX_FRAME_CNT_EXP = XMAC_TX_FRAME_CNT_EXP, 87 ICFG_XMAC_TX_ALL = (XMAC_TX_FRAME_XMIT | XMAC_TX_UNDERRUN | 88 XMAC_TX_MAX_PACKET_ERR | XMAC_TX_OVERFLOW | 89 XMAC_TX_FIFO_XFR_ERR | XMAC_TX_BYTE_CNT_EXP | 90 XMAC_TX_FRAME_CNT_EXP) 91 } xmac_tx_iconfig_t; 92 93 typedef enum xmac_rx_iconfig_e { 94 ICFG_XMAC_RX_FRAME_RCVD = XMAC_RX_FRAME_RCVD, 95 ICFG_XMAC_RX_OVERFLOW = XMAC_RX_OVERFLOW, 96 ICFG_XMAC_RX_UNDERFLOW = XMAC_RX_UNDERFLOW, 97 ICFG_XMAC_RX_CRC_ERR_CNT_EXP = XMAC_RX_CRC_ERR_CNT_EXP, 98 ICFG_XMAC_RX_LEN_ERR_CNT_EXP = XMAC_RX_LEN_ERR_CNT_EXP, 99 ICFG_XMAC_RX_VIOL_ERR_CNT_EXP = XMAC_RX_VIOL_ERR_CNT_EXP, 100 ICFG_XMAC_RX_OCT_CNT_EXP = XMAC_RX_OCT_CNT_EXP, 101 ICFG_XMAC_RX_HST_CNT1_EXP = XMAC_RX_HST_CNT1_EXP, 102 ICFG_XMAC_RX_HST_CNT2_EXP = XMAC_RX_HST_CNT2_EXP, 103 ICFG_XMAC_RX_HST_CNT3_EXP = XMAC_RX_HST_CNT3_EXP, 104 ICFG_XMAC_RX_HST_CNT4_EXP = XMAC_RX_HST_CNT4_EXP, 105 ICFG_XMAC_RX_HST_CNT5_EXP = XMAC_RX_HST_CNT5_EXP, 106 ICFG_XMAC_RX_HST_CNT6_EXP = XMAC_RX_HST_CNT6_EXP, 107 ICFG_XMAC_RX_BCAST_CNT_EXP = XMAC_RX_BCAST_CNT_EXP, 108 ICFG_XMAC_RX_MCAST_CNT_EXP = XMAC_RX_MCAST_CNT_EXP, 109 ICFG_XMAC_RX_FRAG_CNT_EXP = XMAC_RX_FRAG_CNT_EXP, 110 ICFG_XMAC_RX_ALIGNERR_CNT_EXP = XMAC_RX_ALIGNERR_CNT_EXP, 111 ICFG_XMAC_RX_LINK_FLT_CNT_EXP = XMAC_RX_LINK_FLT_CNT_EXP, 112 ICFG_XMAC_RX_HST_CNT7_EXP = XMAC_RX_HST_CNT7_EXP, 113 ICFG_XMAC_RX_REMOTE_FLT_DET = XMAC_RX_REMOTE_FLT_DET, 114 ICFG_XMAC_RX_LOCAL_FLT_DET = XMAC_RX_LOCAL_FLT_DET, 115 ICFG_XMAC_RX_ALL = (XMAC_RX_FRAME_RCVD | XMAC_RX_OVERFLOW | 116 XMAC_RX_UNDERFLOW | XMAC_RX_CRC_ERR_CNT_EXP | 117 XMAC_RX_LEN_ERR_CNT_EXP | 118 XMAC_RX_VIOL_ERR_CNT_EXP | 119 XMAC_RX_OCT_CNT_EXP | XMAC_RX_HST_CNT1_EXP | 120 XMAC_RX_HST_CNT2_EXP | XMAC_RX_HST_CNT3_EXP | 121 XMAC_RX_HST_CNT4_EXP | XMAC_RX_HST_CNT5_EXP | 122 XMAC_RX_HST_CNT6_EXP | XMAC_RX_BCAST_CNT_EXP | 123 XMAC_RX_MCAST_CNT_EXP | XMAC_RX_FRAG_CNT_EXP | 124 XMAC_RX_ALIGNERR_CNT_EXP | 125 XMAC_RX_LINK_FLT_CNT_EXP | 126 XMAC_RX_HST_CNT7_EXP | 127 XMAC_RX_REMOTE_FLT_DET | XMAC_RX_LOCAL_FLT_DET) 128 } xmac_rx_iconfig_t; 129 130 typedef enum xmac_ctl_iconfig_e { 131 ICFG_XMAC_CTRL_PAUSE_RCVD = XMAC_CTRL_PAUSE_RCVD, 132 ICFG_XMAC_CTRL_PAUSE_STATE = XMAC_CTRL_PAUSE_STATE, 133 ICFG_XMAC_CTRL_NOPAUSE_STATE = XMAC_CTRL_NOPAUSE_STATE, 134 ICFG_XMAC_CTRL_ALL = (XMAC_CTRL_PAUSE_RCVD | XMAC_CTRL_PAUSE_STATE | 135 XMAC_CTRL_NOPAUSE_STATE) 136 } xmac_ctl_iconfig_t; 137 138 139 typedef enum bmac_tx_iconfig_e { 140 ICFG_BMAC_TX_FRAME_SENT = MAC_TX_FRAME_XMIT, 141 ICFG_BMAC_TX_UNDERFLOW = MAC_TX_UNDERRUN, 142 ICFG_BMAC_TX_MAXPKTSZ_ERR = MAC_TX_MAX_PACKET_ERR, 143 ICFG_BMAC_TX_BYTE_CNT_EXP = MAC_TX_BYTE_CNT_EXP, 144 ICFG_BMAC_TX_FRAME_CNT_EXP = MAC_TX_FRAME_CNT_EXP, 145 ICFG_BMAC_TX_ALL = (MAC_TX_FRAME_XMIT | MAC_TX_UNDERRUN | 146 MAC_TX_MAX_PACKET_ERR | MAC_TX_BYTE_CNT_EXP | 147 MAC_TX_FRAME_CNT_EXP) 148 } bmac_tx_iconfig_t; 149 150 typedef enum bmac_rx_iconfig_e { 151 ICFG_BMAC_RX_FRAME_RCVD = MAC_RX_FRAME_RECV, 152 ICFG_BMAC_RX_OVERFLOW = MAC_RX_OVERFLOW, 153 ICFG_BMAC_RX_FRAME_CNT_EXP = MAC_RX_FRAME_COUNT, 154 ICFG_BMAC_RX_CRC_ERR_CNT_EXP = MAC_RX_ALIGN_ERR, 155 ICFG_BMAC_RX_LEN_ERR_CNT_EXP = MAC_RX_CRC_ERR, 156 ICFG_BMAC_RX_VIOL_ERR_CNT_EXP = MAC_RX_LEN_ERR, 157 ICFG_BMAC_RX_BYTE_CNT_EXP = MAC_RX_VIOL_ERR, 158 ICFG_BMAC_RX_ALIGNERR_CNT_EXP = MAC_RX_BYTE_CNT_EXP, 159 ICFG_BMAC_RX_ALL = (MAC_RX_FRAME_RECV | MAC_RX_OVERFLOW | 160 MAC_RX_FRAME_COUNT | MAC_RX_ALIGN_ERR | 161 MAC_RX_CRC_ERR | MAC_RX_LEN_ERR | 162 MAC_RX_VIOL_ERR | MAC_RX_BYTE_CNT_EXP) 163 } bmac_rx_iconfig_t; 164 165 typedef enum bmac_ctl_iconfig_e { 166 ICFG_BMAC_CTL_RCVPAUSE = MAC_CTRL_PAUSE_RECEIVED, 167 ICFG_BMAC_CTL_INPAUSE_ST = MAC_CTRL_PAUSE_STATE, 168 ICFG_BMAC_CTL_INNOTPAUSE_ST = MAC_CTRL_NOPAUSE_STATE, 169 ICFG_BMAC_CTL_ALL = (MAC_CTRL_PAUSE_RECEIVED | MAC_CTRL_PAUSE_STATE | 170 MAC_CTRL_NOPAUSE_STATE) 171 } bmac_ctl_iconfig_t; 172 173 typedef enum xmac_tx_config_e { 174 CFG_XMAC_TX = 0x00000001, 175 CFG_XMAC_TX_STRETCH_MODE = 0x00000002, 176 CFG_XMAC_VAR_IPG = 0x00000004, 177 CFG_XMAC_TX_CRC = 0x00000008, 178 CFG_XMAC_TX_ALL = 0x0000000F 179 } xmac_tx_config_t; 180 181 typedef enum xmac_rx_config_e { 182 CFG_XMAC_RX = 0x00000001, 183 CFG_XMAC_RX_PROMISCUOUS = 0x00000002, 184 CFG_XMAC_RX_PROMISCUOUSGROUP = 0x00000004, 185 CFG_XMAC_RX_ERRCHK = 0x00000008, 186 CFG_XMAC_RX_CRC_CHK = 0x00000010, 187 CFG_XMAC_RX_RESV_MULTICAST = 0x00000020, 188 CFG_XMAC_RX_CODE_VIO_CHK = 0x00000040, 189 CFG_XMAC_RX_HASH_FILTER = 0x00000080, 190 CFG_XMAC_RX_ADDR_FILTER = 0x00000100, 191 CFG_XMAC_RX_STRIP_CRC = 0x00000200, 192 CFG_XMAC_RX_PAUSE = 0x00000400, 193 CFG_XMAC_RX_PASS_FC_FRAME = 0x00000800, 194 CFG_XMAC_RX_MAC2IPP_PKT_CNT = 0x00001000, 195 CFG_XMAC_RX_ALL = 0x00001FFF 196 } xmac_rx_config_t; 197 198 typedef enum xmac_xif_config_e { 199 CFG_XMAC_XIF_LED_FORCE = 0x00000001, 200 CFG_XMAC_XIF_LED_POLARITY = 0x00000002, 201 CFG_XMAC_XIF_SEL_POR_CLK_SRC = 0x00000004, 202 CFG_XMAC_XIF_TX_OUTPUT = 0x00000008, 203 CFG_XMAC_XIF_LOOPBACK = 0x00000010, 204 CFG_XMAC_XIF_LFS = 0x00000020, 205 CFG_XMAC_XIF_XPCS_BYPASS = 0x00000040, 206 CFG_XMAC_XIF_1G_PCS_BYPASS = 0x00000080, 207 CFG_XMAC_XIF_SEL_CLK_25MHZ = 0x00000100, 208 CFG_XMAC_XIF_ALL = 0x000001FF 209 } xmac_xif_config_t; 210 211 typedef enum bmac_tx_config_e { 212 CFG_BMAC_TX = 0x00000001, 213 CFG_BMAC_TX_CRC = 0x00000002, 214 CFG_BMAC_TX_ALL = 0x00000003 215 } bmac_tx_config_t; 216 217 typedef enum bmac_rx_config_e { 218 CFG_BMAC_RX = 0x00000001, 219 CFG_BMAC_RX_STRIP_PAD = 0x00000002, 220 CFG_BMAC_RX_STRIP_CRC = 0x00000004, 221 CFG_BMAC_RX_PROMISCUOUS = 0x00000008, 222 CFG_BMAC_RX_PROMISCUOUSGROUP = 0x00000010, 223 CFG_BMAC_RX_HASH_FILTER = 0x00000020, 224 CFG_BMAC_RX_ADDR_FILTER = 0x00000040, 225 CFG_BMAC_RX_DISCARD_ON_ERR = 0x00000080, 226 CFG_BMAC_RX_ALL = 0x000000FF 227 } bmac_rx_config_t; 228 229 typedef enum bmac_xif_config_e { 230 CFG_BMAC_XIF_TX_OUTPUT = 0x00000001, 231 CFG_BMAC_XIF_LOOPBACK = 0x00000002, 232 CFG_BMAC_XIF_GMII_MODE = 0x00000008, 233 CFG_BMAC_XIF_LINKLED = 0x00000020, 234 CFG_BMAC_XIF_LED_POLARITY = 0x00000040, 235 CFG_BMAC_XIF_SEL_CLK_25MHZ = 0x00000080, 236 CFG_BMAC_XIF_ALL = 0x000000FF 237 } bmac_xif_config_t; 238 239 240 typedef enum xmac_ipg_e { 241 XGMII_IPG_12_15 = 0, 242 XGMII_IPG_16_19, 243 XGMII_IPG_20_23, 244 MII_GMII_IPG_12, 245 MII_GMII_IPG_13, 246 MII_GMII_IPG_14, 247 MII_GMII_IPG_15, 248 MII_GMII_IPG_16 249 } xmac_ipg_t; 250 251 typedef enum xpcs_reg_e { 252 XPCS_REG_CONTROL1, 253 XPCS_REG_STATUS1, 254 XPCS_REG_DEVICE_ID, 255 XPCS_REG_SPEED_ABILITY, 256 XPCS_REG_DEVICE_IN_PKG, 257 XPCS_REG_CONTROL2, 258 XPCS_REG_STATUS2, 259 XPCS_REG_PKG_ID, 260 XPCS_REG_STATUS, 261 XPCS_REG_TEST_CONTROL, 262 XPCS_REG_CONFIG_VENDOR1, 263 XPCS_REG_DIAG_VENDOR2, 264 XPCS_REG_MASK1, 265 XPCS_REG_PACKET_COUNTER, 266 XPCS_REG_TX_STATEMACHINE, 267 XPCS_REG_DESCWERR_COUNTER, 268 XPCS_REG_SYMBOL_ERR_L0_1_COUNTER, 269 XPCS_REG_SYMBOL_ERR_L2_3_COUNTER, 270 XPCS_REG_TRAINING_VECTOR 271 } xpcs_reg_t; 272 273 #define IS_XMAC_PORT_NUM_VALID(portn)\ 274 ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) 275 276 #define IS_BMAC_PORT_NUM_VALID(portn)\ 277 ((portn == BMAC_PORT_0) || (portn == BMAC_PORT_1)) 278 279 #define XMAC_REG_WR(handle, portn, reg, val)\ 280 NXGE_REG_WR64(handle, XMAC_REG_ADDR((portn), (reg)), (val)) 281 282 #define XMAC_REG_RD(handle, portn, reg, val_p)\ 283 NXGE_REG_RD64(handle, XMAC_REG_ADDR((portn), (reg)), (val_p)) 284 285 #define BMAC_REG_WR(handle, portn, reg, val)\ 286 NXGE_REG_WR64(handle, BMAC_REG_ADDR((portn), (reg)), (val)) 287 288 #define BMAC_REG_RD(handle, portn, reg, val_p)\ 289 NXGE_REG_RD64(handle, BMAC_REG_ADDR((portn), (reg)), (val_p)) 290 291 #define PCS_REG_WR(handle, portn, reg, val)\ 292 NXGE_REG_WR64(handle, PCS_REG_ADDR((portn), (reg)), (val)) 293 294 #define PCS_REG_RD(handle, portn, reg, val_p)\ 295 NXGE_REG_RD64(handle, PCS_REG_ADDR((portn), (reg)), (val_p)) 296 297 #define XPCS_REG_WR(handle, portn, reg, val)\ 298 NXGE_REG_WR64(handle, XPCS_ADDR((portn), (reg)), (val)) 299 300 #define XPCS_REG_RD(handle, portn, reg, val_p)\ 301 NXGE_REG_RD64(handle, XPCS_ADDR((portn), (reg)), (val_p)) 302 303 #define MIF_REG_WR(handle, reg, val)\ 304 NXGE_REG_WR64(handle, MIF_ADDR((reg)), (val)) 305 306 #define MIF_REG_RD(handle, reg, val_p)\ 307 NXGE_REG_RD64(handle, MIF_ADDR((reg)), (val_p)) 308 309 310 /* 311 * When MIF_REG_RD is called inside a poll loop and if the poll takes 312 * very long time to complete, then each poll will print a rt_show_reg 313 * result on the screen and the rtrace "register show" result may 314 * become too messy to read. The solution is to call MIF_REG_RD_NO_SHOW 315 * instead of MIF_REG_RD in a polling loop. When COSIM or REG_SHOW is 316 * not defined, this macro is the same as MIF_REG_RD. When both COSIM 317 * and REG_SHOW are defined, this macro calls NXGE_REG_RD64_NO_SHOW 318 * which does not call rt_show_reg. 319 */ 320 #if defined(COSIM) && defined(REG_SHOW) 321 #define MIF_REG_RD_NO_SHOW(handle, reg, val_p)\ 322 NXGE_REG_RD64_NO_SHOW(handle, MIF_ADDR((reg)), (val_p)) 323 #else 324 /* If not COSIM or REG_SHOW, still show */ 325 #define MIF_REG_RD_NO_SHOW(handle, reg, val_p)\ 326 NXGE_REG_RD64(handle, MIF_ADDR((reg)), (val_p)) 327 #endif 328 329 #define ESR_REG_WR(handle, reg, val)\ 330 NXGE_REG_WR64(handle, ESR_ADDR((reg)), (val)) 331 332 #define ESR_REG_RD(handle, reg, val_p)\ 333 NXGE_REG_RD64(handle, ESR_ADDR((reg)), (val_p)) 334 335 /* Macros to read/modify MAC attributes */ 336 337 #define SET_MAC_ATTR1(handle, p, portn, attr, val, stat) {\ 338 p.type = attr;\ 339 p.idata[0] = (uint32_t)val;\ 340 stat = npi_mac_port_attr(handle, OP_SET, portn, (npi_attr_t *)&p);\ 341 } 342 343 #define SET_MAC_ATTR2(handle, p, portn, attr, val0, val1, stat) {\ 344 p.type = attr;\ 345 p.idata[0] = (uint32_t)val0;\ 346 p.idata[1] = (uint32_t)val1;\ 347 stat = npi_mac_port_attr(handle, OP_SET, portn, (npi_attr_t *)&p);\ 348 } 349 350 #define SET_MAC_ATTR3(handle, p, portn, attr, val0, val1, val2, stat) {\ 351 p.type = attr;\ 352 p.idata[0] = (uint32_t)val0;\ 353 p.idata[1] = (uint32_t)val1;\ 354 p.idata[2] = (uint32_t)val2;\ 355 stat = npi_mac_port_attr(handle, OP_SET, portn, (npi_attr_t *)&p);\ 356 } 357 358 #define SET_MAC_ATTR4(handle, p, portn, attr, val0, val1, val2, val3, stat) {\ 359 p.type = attr;\ 360 p.idata[0] = (uint32_t)val0;\ 361 p.idata[1] = (uint32_t)val1;\ 362 p.idata[2] = (uint32_t)val2;\ 363 p.idata[3] = (uint32_t)val3;\ 364 stat = npi_mac_port_attr(handle, OP_SET, portn, (npi_attr_t *)&p);\ 365 } 366 367 #define GET_MAC_ATTR1(handle, p, portn, attr, val, stat) {\ 368 p.type = attr;\ 369 if ((stat = npi_mac_port_attr(handle, OP_GET, portn, \ 370 (npi_attr_t *)&p)) == NPI_SUCCESS) {\ 371 val = p.odata[0];\ 372 }\ 373 } 374 375 #define GET_MAC_ATTR2(handle, p, portn, attr, val0, val1, stat) {\ 376 p.type = attr;\ 377 if ((stat = npi_mac_port_attr(handle, OP_GET, portn, \ 378 (npi_attr_t *)&p)) == NPI_SUCCESS) {\ 379 val0 = p.odata[0];\ 380 val1 = p.odata[1];\ 381 }\ 382 } 383 384 #define GET_MAC_ATTR3(handle, p, portn, attr, val0, val1, \ 385 val2, stat) {\ 386 p.type = attr;\ 387 if ((stat = npi_mac_port_attr(handle, OP_GET, portn, \ 388 (npi_attr_t *)&p)) == NPI_SUCCESS) {\ 389 val0 = p.odata[0];\ 390 val1 = p.odata[1];\ 391 val2 = p.odata[2];\ 392 }\ 393 } 394 395 #define GET_MAC_ATTR4(handle, p, portn, attr, val0, val1, \ 396 val2, val3, stat) {\ 397 p.type = attr;\ 398 if ((stat = npi_mac_port_attr(handle, OP_GET, portn, \ 399 (npi_attr_t *)&p)) == NPI_SUCCESS) {\ 400 val0 = p.odata[0];\ 401 val1 = p.odata[1];\ 402 val2 = p.odata[2];\ 403 val3 = p.odata[3];\ 404 }\ 405 } 406 407 /* MAC specific errors */ 408 409 #define MAC_PORT_ATTR_INVALID 0x50 410 #define MAC_RESET_MODE_INVALID 0x51 411 #define MAC_HASHTAB_ENTRY_INVALID 0x52 412 #define MAC_HOSTINFO_ENTRY_INVALID 0x53 413 #define MAC_ALT_ADDR_ENTRY_INVALID 0x54 414 415 /* MAC error return macros */ 416 417 #define NPI_MAC_PORT_INVALID(portn) ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 418 PORT_INVALID | IS_PORT | (portn << 12)) 419 #define NPI_MAC_OPCODE_INVALID(portn) ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 420 OPCODE_INVALID |\ 421 IS_PORT | (portn << 12)) 422 #define NPI_MAC_HASHTAB_ENTRY_INVALID(portn)\ 423 ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 424 MAC_HASHTAB_ENTRY_INVALID |\ 425 IS_PORT | (portn << 12)) 426 #define NPI_MAC_HOSTINFO_ENTRY_INVALID(portn)\ 427 ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 428 MAC_HOSTINFO_ENTRY_INVALID |\ 429 IS_PORT | (portn << 12)) 430 #define NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)\ 431 ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 432 MAC_ALT_ADDR_ENTRY_INVALID |\ 433 IS_PORT | (portn << 12)) 434 #define NPI_MAC_PORT_ATTR_INVALID(portn)\ 435 ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 436 MAC_PORT_ATTR_INVALID |\ 437 IS_PORT | (portn << 12)) 438 #define NPI_MAC_RESET_MODE_INVALID(portn)\ 439 ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 440 MAC_RESET_MODE_INVALID |\ 441 IS_PORT | (portn << 12)) 442 #define NPI_MAC_PCS_REG_INVALID(portn) ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 443 REGISTER_INVALID |\ 444 IS_PORT | (portn << 12)) 445 #define NPI_TXMAC_RESET_FAILED(portn) ((TXMAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 446 RESET_FAILED | IS_PORT | (portn << 12)) 447 #define NPI_RXMAC_RESET_FAILED(portn) ((RXMAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 448 RESET_FAILED | IS_PORT | (portn << 12)) 449 #define NPI_MAC_CONFIG_INVALID(portn) ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 450 CONFIG_INVALID |\ 451 IS_PORT | (portn << 12)) 452 #define NPI_MAC_REG_INVALID(portn) ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 453 REGISTER_INVALID |\ 454 IS_PORT | (portn << 12)) 455 #define NPI_MAC_MII_READ_FAILED(portn) ((MIF_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 456 READ_FAILED | IS_PORT | (portn << 12)) 457 #define NPI_MAC_MII_WRITE_FAILED(portn) ((MIF_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 458 WRITE_FAILED | IS_PORT | (portn << 12)) 459 460 /* library functions prototypes */ 461 462 /* general mac functions */ 463 npi_status_t npi_mac_hashtab_entry(npi_handle_t, io_op_t, 464 uint8_t, uint8_t, uint16_t *); 465 npi_status_t npi_mac_hostinfo_entry(npi_handle_t, io_op_t, 466 uint8_t, uint8_t, 467 hostinfo_t *); 468 npi_status_t npi_mac_altaddr_enable(npi_handle_t, uint8_t, 469 uint8_t); 470 npi_status_t npi_mac_altaddr_disble(npi_handle_t, uint8_t, 471 uint8_t); 472 npi_status_t npi_mac_altaddr_entry(npi_handle_t, io_op_t, 473 uint8_t, uint8_t, 474 npi_mac_addr_t *); 475 npi_status_t npi_mac_port_attr(npi_handle_t, io_op_t, uint8_t, 476 npi_attr_t *); 477 npi_status_t npi_mac_get_link_status(npi_handle_t, uint8_t, 478 boolean_t *); 479 npi_status_t npi_mac_get_10g_link_status(npi_handle_t, uint8_t, 480 boolean_t *); 481 npi_status_t npi_mac_mif_mii_read(npi_handle_t, uint8_t, 482 uint8_t, uint16_t *); 483 npi_status_t npi_mac_mif_mii_write(npi_handle_t, uint8_t, 484 uint8_t, uint16_t); 485 npi_status_t npi_mac_mif_link_intr_enable(npi_handle_t, uint8_t, 486 uint8_t, uint16_t); 487 npi_status_t npi_mac_mif_mdio_read(npi_handle_t, uint8_t, 488 uint8_t, uint16_t, 489 uint16_t *); 490 npi_status_t npi_mac_mif_mdio_write(npi_handle_t, uint8_t, 491 uint8_t, uint16_t, 492 uint16_t); 493 npi_status_t npi_mac_mif_mdio_link_intr_enable(npi_handle_t, 494 uint8_t, uint8_t, 495 uint16_t, uint16_t); 496 npi_status_t npi_mac_mif_link_intr_disable(npi_handle_t, uint8_t); 497 npi_status_t npi_mac_pcs_mii_read(npi_handle_t, uint8_t, 498 uint8_t, uint16_t *); 499 npi_status_t npi_mac_pcs_mii_write(npi_handle_t, uint8_t, 500 uint8_t, uint16_t); 501 npi_status_t npi_mac_pcs_link_intr_enable(npi_handle_t, uint8_t); 502 npi_status_t npi_mac_pcs_link_intr_disable(npi_handle_t, uint8_t); 503 npi_status_t npi_mac_pcs_reset(npi_handle_t, uint8_t); 504 505 /* xmac functions */ 506 npi_status_t npi_xmac_reset(npi_handle_t, uint8_t, 507 npi_mac_reset_t); 508 npi_status_t npi_xmac_xif_config(npi_handle_t, config_op_t, 509 uint8_t, xmac_xif_config_t); 510 npi_status_t npi_xmac_tx_config(npi_handle_t, config_op_t, 511 uint8_t, xmac_tx_config_t); 512 npi_status_t npi_xmac_rx_config(npi_handle_t, config_op_t, 513 uint8_t, xmac_rx_config_t); 514 npi_status_t npi_xmac_tx_iconfig(npi_handle_t, config_op_t, 515 uint8_t, xmac_tx_iconfig_t); 516 npi_status_t npi_xmac_rx_iconfig(npi_handle_t, config_op_t, 517 uint8_t, xmac_rx_iconfig_t); 518 npi_status_t npi_xmac_ctl_iconfig(npi_handle_t, config_op_t, 519 uint8_t, xmac_ctl_iconfig_t); 520 npi_status_t npi_xmac_tx_get_istatus(npi_handle_t, uint8_t, 521 xmac_tx_iconfig_t *); 522 npi_status_t npi_xmac_rx_get_istatus(npi_handle_t, uint8_t, 523 xmac_rx_iconfig_t *); 524 npi_status_t npi_xmac_ctl_get_istatus(npi_handle_t, uint8_t, 525 xmac_ctl_iconfig_t *); 526 npi_status_t npi_xmac_xpcs_reset(npi_handle_t, uint8_t); 527 npi_status_t npi_xmac_xpcs_enable(npi_handle_t, uint8_t); 528 npi_status_t npi_xmac_xpcs_disable(npi_handle_t, uint8_t); 529 npi_status_t npi_xmac_xpcs_read(npi_handle_t, uint8_t, 530 uint8_t, uint32_t *); 531 npi_status_t npi_xmac_xpcs_write(npi_handle_t, uint8_t, 532 uint8_t, uint32_t); 533 npi_status_t npi_xmac_xpcs_link_intr_enable(npi_handle_t, uint8_t); 534 npi_status_t npi_xmac_xpcs_link_intr_disable(npi_handle_t, 535 uint8_t); 536 npi_status_t npi_xmac_xif_led(npi_handle_t, uint8_t, 537 boolean_t); 538 npi_status_t npi_xmac_zap_tx_counters(npi_handle_t, uint8_t); 539 npi_status_t npi_xmac_zap_rx_counters(npi_handle_t, uint8_t); 540 541 /* bmac functions */ 542 npi_status_t npi_bmac_reset(npi_handle_t, uint8_t, 543 npi_mac_reset_t mode); 544 npi_status_t npi_bmac_tx_config(npi_handle_t, config_op_t, 545 uint8_t, bmac_tx_config_t); 546 npi_status_t npi_bmac_rx_config(npi_handle_t, config_op_t, 547 uint8_t, bmac_rx_config_t); 548 npi_status_t npi_bmac_rx_iconfig(npi_handle_t, config_op_t, 549 uint8_t, bmac_rx_iconfig_t); 550 npi_status_t npi_bmac_xif_config(npi_handle_t, config_op_t, 551 uint8_t, bmac_xif_config_t); 552 npi_status_t npi_bmac_tx_iconfig(npi_handle_t, config_op_t, 553 uint8_t, bmac_tx_iconfig_t); 554 npi_status_t npi_bmac_ctl_iconfig(npi_handle_t, config_op_t, 555 uint8_t, bmac_ctl_iconfig_t); 556 npi_status_t npi_bmac_tx_get_istatus(npi_handle_t, uint8_t, 557 bmac_tx_iconfig_t *); 558 npi_status_t npi_bmac_rx_get_istatus(npi_handle_t, uint8_t, 559 bmac_rx_iconfig_t *); 560 npi_status_t npi_bmac_ctl_get_istatus(npi_handle_t, uint8_t, 561 bmac_ctl_iconfig_t *); 562 npi_status_t npi_bmac_send_pause(npi_handle_t, uint8_t, 563 uint16_t); 564 npi_status_t npi_mac_dump_regs(npi_handle_t, uint8_t); 565 566 /* MIF common functions */ 567 void npi_mac_mif_set_indirect_mode(npi_handle_t, boolean_t); 568 569 #ifdef __cplusplus 570 } 571 #endif 572 573 #endif /* _NPI_MAC_H */ 574