xref: /illumos-gate/usr/src/uts/common/io/nxge/npi/npi_mac.h (revision 678453a8)
144961713Sgirish /*
244961713Sgirish  * CDDL HEADER START
344961713Sgirish  *
444961713Sgirish  * The contents of this file are subject to the terms of the
544961713Sgirish  * Common Development and Distribution License (the "License").
644961713Sgirish  * You may not use this file except in compliance with the License.
744961713Sgirish  *
844961713Sgirish  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
944961713Sgirish  * or http://www.opensolaris.org/os/licensing.
1044961713Sgirish  * See the License for the specific language governing permissions
1144961713Sgirish  * and limitations under the License.
1244961713Sgirish  *
1344961713Sgirish  * When distributing Covered Code, include this CDDL HEADER in each
1444961713Sgirish  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1544961713Sgirish  * If applicable, add the following below this CDDL HEADER, with the
1644961713Sgirish  * fields enclosed by brackets "[]" replaced with your own identifying
1744961713Sgirish  * information: Portions Copyright [yyyy] [name of copyright owner]
1844961713Sgirish  *
1944961713Sgirish  * CDDL HEADER END
2044961713Sgirish  */
2144961713Sgirish /*
22*678453a8Sspeer  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
2344961713Sgirish  * Use is subject to license terms.
2444961713Sgirish  */
2544961713Sgirish 
2644961713Sgirish #ifndef _NPI_MAC_H
2744961713Sgirish #define	_NPI_MAC_H
2844961713Sgirish 
2944961713Sgirish #pragma ident	"%Z%%M%	%I%	%E% SMI"
3044961713Sgirish 
3144961713Sgirish #ifdef	__cplusplus
3244961713Sgirish extern "C" {
3344961713Sgirish #endif
3444961713Sgirish 
3544961713Sgirish #include <npi.h>
3644961713Sgirish #include <nxge_mac_hw.h>
3744961713Sgirish #include <nxge_mii.h>
3844961713Sgirish 
3944961713Sgirish typedef struct _npi_mac_addr {
4044961713Sgirish 	uint16_t	w0;
4144961713Sgirish 	uint16_t	w1;
4244961713Sgirish 	uint16_t	w2;
4344961713Sgirish } npi_mac_addr_t;
4444961713Sgirish 
4544961713Sgirish typedef enum npi_mac_attr {
4644961713Sgirish 	MAC_PORT_MODE = 0,
4744961713Sgirish 	MAC_PORT_FRAME_SIZE,
4844961713Sgirish 	MAC_PORT_ADDR,
4944961713Sgirish 	MAC_PORT_ADDR_FILTER,
5044961713Sgirish 	MAC_PORT_ADDR_FILTER_MASK,
5144961713Sgirish 	XMAC_PORT_IPG,
5244961713Sgirish 	XMAC_10G_PORT_IPG,
5344961713Sgirish 	BMAC_PORT_MAX_BURST_SIZE,
5444961713Sgirish 	BMAC_PORT_PA_SIZE,
5544961713Sgirish 	BMAC_PORT_CTRL_TYPE
5644961713Sgirish } npi_mac_attr_t;
5744961713Sgirish 
5844961713Sgirish /* MAC Mode options */
5944961713Sgirish 
6044961713Sgirish typedef enum npi_mac_mode_e {
6144961713Sgirish 	MAC_MII_MODE = 0,
6244961713Sgirish 	MAC_GMII_MODE,
6344961713Sgirish 	MAC_XGMII_MODE
6444961713Sgirish } npi_mac_mode_t;
6544961713Sgirish 
6644961713Sgirish typedef enum npi_mac_reset_e {
6744961713Sgirish 	TX_MAC_RESET = 1,
6844961713Sgirish 	RX_MAC_RESET,
6944961713Sgirish 	XTX_MAC_REG_RESET,
7044961713Sgirish 	XRX_MAC_REG_RESET,
7144961713Sgirish 	XTX_MAC_LOGIC_RESET,
7244961713Sgirish 	XRX_MAC_LOGIC_RESET,
7344961713Sgirish 	XTX_MAC_RESET_ALL,
7444961713Sgirish 	XRX_MAC_RESET_ALL,
7544961713Sgirish 	BMAC_RESET_ALL,
7644961713Sgirish 	XMAC_RESET_ALL
7744961713Sgirish } npi_mac_reset_t;
7844961713Sgirish 
7944961713Sgirish typedef enum xmac_tx_iconfig_e {
8044961713Sgirish 	ICFG_XMAC_TX_FRAME_XMIT 	= XMAC_TX_FRAME_XMIT,
8144961713Sgirish 	ICFG_XMAC_TX_UNDERRUN		= XMAC_TX_UNDERRUN,
8244961713Sgirish 	ICFG_XMAC_TX_MAX_PACKET_ERR	= XMAC_TX_MAX_PACKET_ERR,
8344961713Sgirish 	ICFG_XMAC_TX_OVERFLOW		= XMAC_TX_OVERFLOW,
8444961713Sgirish 	ICFG_XMAC_TX_FIFO_XFR_ERR	= XMAC_TX_FIFO_XFR_ERR,
8544961713Sgirish 	ICFG_XMAC_TX_BYTE_CNT_EXP	= XMAC_TX_BYTE_CNT_EXP,
8644961713Sgirish 	ICFG_XMAC_TX_FRAME_CNT_EXP	= XMAC_TX_FRAME_CNT_EXP,
8744961713Sgirish 	ICFG_XMAC_TX_ALL = (XMAC_TX_FRAME_XMIT | XMAC_TX_UNDERRUN |
8844961713Sgirish 				XMAC_TX_MAX_PACKET_ERR | XMAC_TX_OVERFLOW |
8944961713Sgirish 				XMAC_TX_FIFO_XFR_ERR |  XMAC_TX_BYTE_CNT_EXP |
9044961713Sgirish 				XMAC_TX_FRAME_CNT_EXP)
9144961713Sgirish } xmac_tx_iconfig_t;
9244961713Sgirish 
9344961713Sgirish typedef enum xmac_rx_iconfig_e {
9444961713Sgirish 	ICFG_XMAC_RX_FRAME_RCVD		= XMAC_RX_FRAME_RCVD,
9544961713Sgirish 	ICFG_XMAC_RX_OVERFLOW		= XMAC_RX_OVERFLOW,
9644961713Sgirish 	ICFG_XMAC_RX_UNDERFLOW		= XMAC_RX_UNDERFLOW,
9744961713Sgirish 	ICFG_XMAC_RX_CRC_ERR_CNT_EXP	= XMAC_RX_CRC_ERR_CNT_EXP,
9844961713Sgirish 	ICFG_XMAC_RX_LEN_ERR_CNT_EXP	= XMAC_RX_LEN_ERR_CNT_EXP,
9944961713Sgirish 	ICFG_XMAC_RX_VIOL_ERR_CNT_EXP	= XMAC_RX_VIOL_ERR_CNT_EXP,
10044961713Sgirish 	ICFG_XMAC_RX_OCT_CNT_EXP	= XMAC_RX_OCT_CNT_EXP,
10144961713Sgirish 	ICFG_XMAC_RX_HST_CNT1_EXP	= XMAC_RX_HST_CNT1_EXP,
10244961713Sgirish 	ICFG_XMAC_RX_HST_CNT2_EXP	= XMAC_RX_HST_CNT2_EXP,
10344961713Sgirish 	ICFG_XMAC_RX_HST_CNT3_EXP	= XMAC_RX_HST_CNT3_EXP,
10444961713Sgirish 	ICFG_XMAC_RX_HST_CNT4_EXP	= XMAC_RX_HST_CNT4_EXP,
10544961713Sgirish 	ICFG_XMAC_RX_HST_CNT5_EXP	= XMAC_RX_HST_CNT5_EXP,
10644961713Sgirish 	ICFG_XMAC_RX_HST_CNT6_EXP	= XMAC_RX_HST_CNT6_EXP,
10744961713Sgirish 	ICFG_XMAC_RX_BCAST_CNT_EXP	= XMAC_RX_BCAST_CNT_EXP,
10844961713Sgirish 	ICFG_XMAC_RX_MCAST_CNT_EXP	= XMAC_RX_MCAST_CNT_EXP,
10944961713Sgirish 	ICFG_XMAC_RX_FRAG_CNT_EXP	= XMAC_RX_FRAG_CNT_EXP,
11044961713Sgirish 	ICFG_XMAC_RX_ALIGNERR_CNT_EXP	= XMAC_RX_ALIGNERR_CNT_EXP,
11144961713Sgirish 	ICFG_XMAC_RX_LINK_FLT_CNT_EXP	= XMAC_RX_LINK_FLT_CNT_EXP,
11244961713Sgirish 	ICFG_XMAC_RX_HST_CNT7_EXP	= XMAC_RX_HST_CNT7_EXP,
11344961713Sgirish 	ICFG_XMAC_RX_REMOTE_FLT_DET	= XMAC_RX_REMOTE_FLT_DET,
11444961713Sgirish 	ICFG_XMAC_RX_LOCAL_FLT_DET	= XMAC_RX_LOCAL_FLT_DET,
11544961713Sgirish 	ICFG_XMAC_RX_ALL = (XMAC_RX_FRAME_RCVD | XMAC_RX_OVERFLOW |
11644961713Sgirish 				XMAC_RX_UNDERFLOW | XMAC_RX_CRC_ERR_CNT_EXP |
11744961713Sgirish 				XMAC_RX_LEN_ERR_CNT_EXP |
11844961713Sgirish 				XMAC_RX_VIOL_ERR_CNT_EXP |
11944961713Sgirish 				XMAC_RX_OCT_CNT_EXP | XMAC_RX_HST_CNT1_EXP |
12044961713Sgirish 				XMAC_RX_HST_CNT2_EXP | XMAC_RX_HST_CNT3_EXP |
12144961713Sgirish 				XMAC_RX_HST_CNT4_EXP | XMAC_RX_HST_CNT5_EXP |
12244961713Sgirish 				XMAC_RX_HST_CNT6_EXP | XMAC_RX_BCAST_CNT_EXP |
12344961713Sgirish 				XMAC_RX_MCAST_CNT_EXP | XMAC_RX_FRAG_CNT_EXP |
12444961713Sgirish 				XMAC_RX_ALIGNERR_CNT_EXP |
12544961713Sgirish 				XMAC_RX_LINK_FLT_CNT_EXP |
12644961713Sgirish 				XMAC_RX_HST_CNT7_EXP |
12744961713Sgirish 				XMAC_RX_REMOTE_FLT_DET | XMAC_RX_LOCAL_FLT_DET)
12844961713Sgirish } xmac_rx_iconfig_t;
12944961713Sgirish 
13044961713Sgirish typedef enum xmac_ctl_iconfig_e {
13144961713Sgirish 	ICFG_XMAC_CTRL_PAUSE_RCVD	= XMAC_CTRL_PAUSE_RCVD,
13244961713Sgirish 	ICFG_XMAC_CTRL_PAUSE_STATE	= XMAC_CTRL_PAUSE_STATE,
13344961713Sgirish 	ICFG_XMAC_CTRL_NOPAUSE_STATE	= XMAC_CTRL_NOPAUSE_STATE,
13444961713Sgirish 	ICFG_XMAC_CTRL_ALL = (XMAC_CTRL_PAUSE_RCVD | XMAC_CTRL_PAUSE_STATE |
13544961713Sgirish 				XMAC_CTRL_NOPAUSE_STATE)
13644961713Sgirish } xmac_ctl_iconfig_t;
13744961713Sgirish 
13844961713Sgirish 
13944961713Sgirish typedef enum bmac_tx_iconfig_e {
14044961713Sgirish 	ICFG_BMAC_TX_FRAME_SENT 	= MAC_TX_FRAME_XMIT,
14144961713Sgirish 	ICFG_BMAC_TX_UNDERFLOW		= MAC_TX_UNDERRUN,
14244961713Sgirish 	ICFG_BMAC_TX_MAXPKTSZ_ERR	= MAC_TX_MAX_PACKET_ERR,
14344961713Sgirish 	ICFG_BMAC_TX_BYTE_CNT_EXP	= MAC_TX_BYTE_CNT_EXP,
14444961713Sgirish 	ICFG_BMAC_TX_FRAME_CNT_EXP	= MAC_TX_FRAME_CNT_EXP,
14544961713Sgirish 	ICFG_BMAC_TX_ALL = (MAC_TX_FRAME_XMIT | MAC_TX_UNDERRUN |
14644961713Sgirish 				MAC_TX_MAX_PACKET_ERR | MAC_TX_BYTE_CNT_EXP |
14744961713Sgirish 				MAC_TX_FRAME_CNT_EXP)
14844961713Sgirish } bmac_tx_iconfig_t;
14944961713Sgirish 
15044961713Sgirish typedef enum bmac_rx_iconfig_e {
15144961713Sgirish 	ICFG_BMAC_RX_FRAME_RCVD		= MAC_RX_FRAME_RECV,
15244961713Sgirish 	ICFG_BMAC_RX_OVERFLOW		= MAC_RX_OVERFLOW,
15344961713Sgirish 	ICFG_BMAC_RX_FRAME_CNT_EXP	= MAC_RX_FRAME_COUNT,
15444961713Sgirish 	ICFG_BMAC_RX_CRC_ERR_CNT_EXP	= MAC_RX_ALIGN_ERR,
15544961713Sgirish 	ICFG_BMAC_RX_LEN_ERR_CNT_EXP	= MAC_RX_CRC_ERR,
15644961713Sgirish 	ICFG_BMAC_RX_VIOL_ERR_CNT_EXP	= MAC_RX_LEN_ERR,
15744961713Sgirish 	ICFG_BMAC_RX_BYTE_CNT_EXP	= MAC_RX_VIOL_ERR,
15844961713Sgirish 	ICFG_BMAC_RX_ALIGNERR_CNT_EXP	= MAC_RX_BYTE_CNT_EXP,
15944961713Sgirish 	ICFG_BMAC_RX_ALL = (MAC_RX_FRAME_RECV | MAC_RX_OVERFLOW |
16044961713Sgirish 				MAC_RX_FRAME_COUNT | MAC_RX_ALIGN_ERR |
16144961713Sgirish 				MAC_RX_CRC_ERR | MAC_RX_LEN_ERR |
16244961713Sgirish 				MAC_RX_VIOL_ERR | MAC_RX_BYTE_CNT_EXP)
16344961713Sgirish } bmac_rx_iconfig_t;
16444961713Sgirish 
16544961713Sgirish typedef enum bmac_ctl_iconfig_e {
16644961713Sgirish 	ICFG_BMAC_CTL_RCVPAUSE		= MAC_CTRL_PAUSE_RECEIVED,
16744961713Sgirish 	ICFG_BMAC_CTL_INPAUSE_ST	= MAC_CTRL_PAUSE_STATE,
16844961713Sgirish 	ICFG_BMAC_CTL_INNOTPAUSE_ST	= MAC_CTRL_NOPAUSE_STATE,
16944961713Sgirish 	ICFG_BMAC_CTL_ALL = (MAC_CTRL_PAUSE_RECEIVED | MAC_CTRL_PAUSE_STATE |
17044961713Sgirish 				MAC_CTRL_NOPAUSE_STATE)
17144961713Sgirish } bmac_ctl_iconfig_t;
17244961713Sgirish 
17344961713Sgirish typedef	enum xmac_tx_config_e {
17444961713Sgirish 	CFG_XMAC_TX			= 0x00000001,
17544961713Sgirish 	CFG_XMAC_TX_STRETCH_MODE	= 0x00000002,
17644961713Sgirish 	CFG_XMAC_VAR_IPG		= 0x00000004,
17744961713Sgirish 	CFG_XMAC_TX_CRC			= 0x00000008,
17844961713Sgirish 	CFG_XMAC_TX_ALL			= 0x0000000F
17944961713Sgirish } xmac_tx_config_t;
18044961713Sgirish 
18144961713Sgirish typedef enum xmac_rx_config_e {
18244961713Sgirish 	CFG_XMAC_RX			= 0x00000001,
18344961713Sgirish 	CFG_XMAC_RX_PROMISCUOUS		= 0x00000002,
18444961713Sgirish 	CFG_XMAC_RX_PROMISCUOUSGROUP	= 0x00000004,
18544961713Sgirish 	CFG_XMAC_RX_ERRCHK		= 0x00000008,
18644961713Sgirish 	CFG_XMAC_RX_CRC_CHK		= 0x00000010,
18744961713Sgirish 	CFG_XMAC_RX_RESV_MULTICAST	= 0x00000020,
18844961713Sgirish 	CFG_XMAC_RX_CODE_VIO_CHK	= 0x00000040,
18944961713Sgirish 	CFG_XMAC_RX_HASH_FILTER		= 0x00000080,
19044961713Sgirish 	CFG_XMAC_RX_ADDR_FILTER		= 0x00000100,
19144961713Sgirish 	CFG_XMAC_RX_STRIP_CRC		= 0x00000200,
19244961713Sgirish 	CFG_XMAC_RX_PAUSE		= 0x00000400,
19344961713Sgirish 	CFG_XMAC_RX_PASS_FC_FRAME	= 0x00000800,
19444961713Sgirish 	CFG_XMAC_RX_MAC2IPP_PKT_CNT	= 0x00001000,
19544961713Sgirish 	CFG_XMAC_RX_ALL			= 0x00001FFF
19644961713Sgirish } xmac_rx_config_t;
19744961713Sgirish 
19844961713Sgirish typedef	enum xmac_xif_config_e {
19944961713Sgirish 	CFG_XMAC_XIF_LED_FORCE		= 0x00000001,
20044961713Sgirish 	CFG_XMAC_XIF_LED_POLARITY	= 0x00000002,
20144961713Sgirish 	CFG_XMAC_XIF_SEL_POR_CLK_SRC	= 0x00000004,
20244961713Sgirish 	CFG_XMAC_XIF_TX_OUTPUT		= 0x00000008,
20344961713Sgirish 	CFG_XMAC_XIF_LOOPBACK		= 0x00000010,
20444961713Sgirish 	CFG_XMAC_XIF_LFS		= 0x00000020,
20544961713Sgirish 	CFG_XMAC_XIF_XPCS_BYPASS	= 0x00000040,
20644961713Sgirish 	CFG_XMAC_XIF_1G_PCS_BYPASS	= 0x00000080,
20744961713Sgirish 	CFG_XMAC_XIF_SEL_CLK_25MHZ	= 0x00000100,
20844961713Sgirish 	CFG_XMAC_XIF_ALL		= 0x000001FF
20944961713Sgirish } xmac_xif_config_t;
21044961713Sgirish 
21144961713Sgirish typedef	enum bmac_tx_config_e {
21244961713Sgirish 	CFG_BMAC_TX			= 0x00000001,
21344961713Sgirish 	CFG_BMAC_TX_CRC			= 0x00000002,
21444961713Sgirish 	CFG_BMAC_TX_ALL			= 0x00000003
21544961713Sgirish } bmac_tx_config_t;
21644961713Sgirish 
21744961713Sgirish typedef enum bmac_rx_config_e {
21844961713Sgirish 	CFG_BMAC_RX			= 0x00000001,
21944961713Sgirish 	CFG_BMAC_RX_STRIP_PAD		= 0x00000002,
22044961713Sgirish 	CFG_BMAC_RX_STRIP_CRC		= 0x00000004,
22144961713Sgirish 	CFG_BMAC_RX_PROMISCUOUS		= 0x00000008,
22244961713Sgirish 	CFG_BMAC_RX_PROMISCUOUSGROUP	= 0x00000010,
22344961713Sgirish 	CFG_BMAC_RX_HASH_FILTER		= 0x00000020,
22444961713Sgirish 	CFG_BMAC_RX_ADDR_FILTER		= 0x00000040,
22544961713Sgirish 	CFG_BMAC_RX_DISCARD_ON_ERR	= 0x00000080,
22644961713Sgirish 	CFG_BMAC_RX_ALL			= 0x000000FF
22744961713Sgirish } bmac_rx_config_t;
22844961713Sgirish 
22944961713Sgirish typedef	enum bmac_xif_config_e {
23044961713Sgirish 	CFG_BMAC_XIF_TX_OUTPUT		= 0x00000001,
23144961713Sgirish 	CFG_BMAC_XIF_LOOPBACK		= 0x00000002,
23244961713Sgirish 	CFG_BMAC_XIF_GMII_MODE		= 0x00000008,
23344961713Sgirish 	CFG_BMAC_XIF_LINKLED		= 0x00000020,
23444961713Sgirish 	CFG_BMAC_XIF_LED_POLARITY	= 0x00000040,
23544961713Sgirish 	CFG_BMAC_XIF_SEL_CLK_25MHZ	= 0x00000080,
23644961713Sgirish 	CFG_BMAC_XIF_ALL		= 0x000000FF
23744961713Sgirish } bmac_xif_config_t;
23844961713Sgirish 
23944961713Sgirish 
24044961713Sgirish typedef enum xmac_ipg_e {
24144961713Sgirish 	XGMII_IPG_12_15 = 0,
24244961713Sgirish 	XGMII_IPG_16_19,
24344961713Sgirish 	XGMII_IPG_20_23,
24444961713Sgirish 	MII_GMII_IPG_12,
24544961713Sgirish 	MII_GMII_IPG_13,
24644961713Sgirish 	MII_GMII_IPG_14,
24744961713Sgirish 	MII_GMII_IPG_15,
24844961713Sgirish 	MII_GMII_IPG_16
24944961713Sgirish } xmac_ipg_t;
25044961713Sgirish 
25144961713Sgirish typedef	enum xpcs_reg_e {
25244961713Sgirish 	XPCS_REG_CONTROL1,
25344961713Sgirish 	XPCS_REG_STATUS1,
25444961713Sgirish 	XPCS_REG_DEVICE_ID,
25544961713Sgirish 	XPCS_REG_SPEED_ABILITY,
25644961713Sgirish 	XPCS_REG_DEVICE_IN_PKG,
25744961713Sgirish 	XPCS_REG_CONTROL2,
25844961713Sgirish 	XPCS_REG_STATUS2,
25944961713Sgirish 	XPCS_REG_PKG_ID,
26044961713Sgirish 	XPCS_REG_STATUS,
26144961713Sgirish 	XPCS_REG_TEST_CONTROL,
26244961713Sgirish 	XPCS_REG_CONFIG_VENDOR1,
26344961713Sgirish 	XPCS_REG_DIAG_VENDOR2,
26444961713Sgirish 	XPCS_REG_MASK1,
26544961713Sgirish 	XPCS_REG_PACKET_COUNTER,
26644961713Sgirish 	XPCS_REG_TX_STATEMACHINE,
26744961713Sgirish 	XPCS_REG_DESCWERR_COUNTER,
26844961713Sgirish 	XPCS_REG_SYMBOL_ERR_L0_1_COUNTER,
26944961713Sgirish 	XPCS_REG_SYMBOL_ERR_L2_3_COUNTER,
27044961713Sgirish 	XPCS_REG_TRAINING_VECTOR
27144961713Sgirish } xpcs_reg_t;
27244961713Sgirish 
27344961713Sgirish #define	IS_XMAC_PORT_NUM_VALID(portn)\
27444961713Sgirish 	((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1))
27544961713Sgirish 
27644961713Sgirish #define	IS_BMAC_PORT_NUM_VALID(portn)\
27744961713Sgirish 	((portn == BMAC_PORT_0) || (portn == BMAC_PORT_1))
27844961713Sgirish 
27944961713Sgirish #define	XMAC_REG_WR(handle, portn, reg, val)\
28044961713Sgirish 	NXGE_REG_WR64(handle, XMAC_REG_ADDR((portn), (reg)), (val))
28144961713Sgirish 
28244961713Sgirish #define	XMAC_REG_RD(handle, portn, reg, val_p)\
28344961713Sgirish 	NXGE_REG_RD64(handle, XMAC_REG_ADDR((portn), (reg)), (val_p))
28444961713Sgirish 
28544961713Sgirish #define	BMAC_REG_WR(handle, portn, reg, val)\
28644961713Sgirish 	NXGE_REG_WR64(handle, BMAC_REG_ADDR((portn), (reg)), (val))
28744961713Sgirish 
28844961713Sgirish #define	BMAC_REG_RD(handle, portn, reg, val_p)\
28944961713Sgirish 	NXGE_REG_RD64(handle, BMAC_REG_ADDR((portn), (reg)), (val_p))
29044961713Sgirish 
29144961713Sgirish #define	PCS_REG_WR(handle, portn, reg, val)\
29244961713Sgirish 	NXGE_REG_WR64(handle, PCS_REG_ADDR((portn), (reg)), (val))
29344961713Sgirish 
29444961713Sgirish #define	PCS_REG_RD(handle, portn, reg, val_p)\
29544961713Sgirish 	NXGE_REG_RD64(handle, PCS_REG_ADDR((portn), (reg)), (val_p))
29644961713Sgirish 
29744961713Sgirish #define	XPCS_REG_WR(handle, portn, reg, val)\
29844961713Sgirish 	NXGE_REG_WR64(handle, XPCS_ADDR((portn), (reg)), (val))
29944961713Sgirish 
30044961713Sgirish #define	XPCS_REG_RD(handle, portn, reg, val_p)\
30144961713Sgirish 	NXGE_REG_RD64(handle, XPCS_ADDR((portn), (reg)), (val_p))
30244961713Sgirish 
30344961713Sgirish #define	MIF_REG_WR(handle, reg, val)\
30444961713Sgirish 	NXGE_REG_WR64(handle, MIF_ADDR((reg)), (val))
30544961713Sgirish 
30644961713Sgirish #define	MIF_REG_RD(handle, reg, val_p)\
30744961713Sgirish 	NXGE_REG_RD64(handle, MIF_ADDR((reg)), (val_p))
30844961713Sgirish 
30944961713Sgirish 
31044961713Sgirish /*
31144961713Sgirish  * When MIF_REG_RD is called inside a poll loop and if the poll takes
31244961713Sgirish  * very long time to complete, then each poll will print a rt_show_reg
31344961713Sgirish  * result on the screen and the rtrace "register show" result may
31444961713Sgirish  * become too messy to read.  The solution is to call MIF_REG_RD_NO_SHOW
31544961713Sgirish  * instead of MIF_REG_RD in a polling loop. When COSIM or REG_SHOW is
31644961713Sgirish  * not defined, this macro is the same as MIF_REG_RD.  When both COSIM
31744961713Sgirish  * and REG_SHOW are defined, this macro calls NXGE_REG_RD64_NO_SHOW
31844961713Sgirish  * which does not call rt_show_reg.
31944961713Sgirish  */
32044961713Sgirish #if defined(COSIM) && defined(REG_SHOW)
32144961713Sgirish #define	MIF_REG_RD_NO_SHOW(handle, reg, val_p)\
32244961713Sgirish 	NXGE_REG_RD64_NO_SHOW(handle, MIF_ADDR((reg)), (val_p))
32344961713Sgirish #else
32444961713Sgirish 	/*	If not COSIM or REG_SHOW, still show */
32544961713Sgirish #define	MIF_REG_RD_NO_SHOW(handle, reg, val_p)\
32644961713Sgirish 	NXGE_REG_RD64(handle, MIF_ADDR((reg)), (val_p))
32744961713Sgirish #endif
32844961713Sgirish 
32944961713Sgirish #define	ESR_REG_WR(handle, reg, val)\
33044961713Sgirish 	NXGE_REG_WR64(handle, ESR_ADDR((reg)), (val))
33144961713Sgirish 
33244961713Sgirish #define	ESR_REG_RD(handle, reg, val_p)\
33344961713Sgirish 	NXGE_REG_RD64(handle, ESR_ADDR((reg)), (val_p))
33444961713Sgirish 
33544961713Sgirish /* Macros to read/modify MAC attributes */
33644961713Sgirish 
33744961713Sgirish #define	SET_MAC_ATTR1(handle, p, portn, attr, val, stat) {\
33844961713Sgirish 	p.type = attr;\
33944961713Sgirish 	p.idata[0] = (uint32_t)val;\
34044961713Sgirish 	stat = npi_mac_port_attr(handle, OP_SET, portn, (npi_attr_t *)&p);\
34144961713Sgirish }
34244961713Sgirish 
34344961713Sgirish #define	SET_MAC_ATTR2(handle, p, portn, attr, val0, val1, stat) {\
34444961713Sgirish 	p.type = attr;\
34544961713Sgirish 	p.idata[0] = (uint32_t)val0;\
34644961713Sgirish 	p.idata[1] = (uint32_t)val1;\
34744961713Sgirish 	stat = npi_mac_port_attr(handle, OP_SET, portn, (npi_attr_t *)&p);\
34844961713Sgirish }
34944961713Sgirish 
35044961713Sgirish #define	SET_MAC_ATTR3(handle, p, portn, attr, val0, val1, val2, stat) {\
35144961713Sgirish 	p.type = attr;\
35244961713Sgirish 	p.idata[0] = (uint32_t)val0;\
35344961713Sgirish 	p.idata[1] = (uint32_t)val1;\
35444961713Sgirish 	p.idata[2] = (uint32_t)val2;\
35544961713Sgirish 	stat = npi_mac_port_attr(handle, OP_SET, portn, (npi_attr_t *)&p);\
35644961713Sgirish }
35744961713Sgirish 
35844961713Sgirish #define	SET_MAC_ATTR4(handle, p, portn, attr, val0, val1, val2, val3, stat) {\
35944961713Sgirish 	p.type = attr;\
36044961713Sgirish 	p.idata[0] = (uint32_t)val0;\
36144961713Sgirish 	p.idata[1] = (uint32_t)val1;\
36244961713Sgirish 	p.idata[2] = (uint32_t)val2;\
36344961713Sgirish 	p.idata[3] = (uint32_t)val3;\
36444961713Sgirish 	stat = npi_mac_port_attr(handle, OP_SET, portn, (npi_attr_t *)&p);\
36544961713Sgirish }
36644961713Sgirish 
36744961713Sgirish #define	GET_MAC_ATTR1(handle, p, portn, attr, val, stat) {\
36844961713Sgirish 	p.type = attr;\
36944961713Sgirish 	if ((stat = npi_mac_port_attr(handle, OP_GET, portn, \
37044961713Sgirish 					(npi_attr_t *)&p)) == NPI_SUCCESS) {\
37144961713Sgirish 		val = p.odata[0];\
37244961713Sgirish 	}\
37344961713Sgirish }
37444961713Sgirish 
37544961713Sgirish #define	GET_MAC_ATTR2(handle, p, portn, attr, val0, val1, stat) {\
37644961713Sgirish 	p.type = attr;\
37744961713Sgirish 	if ((stat = npi_mac_port_attr(handle, OP_GET, portn, \
37844961713Sgirish 					(npi_attr_t *)&p)) == NPI_SUCCESS) {\
37944961713Sgirish 		val0 = p.odata[0];\
38044961713Sgirish 		val1 = p.odata[1];\
38144961713Sgirish 	}\
38244961713Sgirish }
38344961713Sgirish 
38444961713Sgirish #define	GET_MAC_ATTR3(handle, p, portn, attr, val0, val1, \
38544961713Sgirish 			val2, stat) {\
38644961713Sgirish 	p.type = attr;\
38744961713Sgirish 	if ((stat = npi_mac_port_attr(handle, OP_GET, portn, \
38844961713Sgirish 					(npi_attr_t *)&p)) == NPI_SUCCESS) {\
38944961713Sgirish 		val0 = p.odata[0];\
39044961713Sgirish 		val1 = p.odata[1];\
39144961713Sgirish 		val2 = p.odata[2];\
39244961713Sgirish 	}\
39344961713Sgirish }
39444961713Sgirish 
39544961713Sgirish #define	GET_MAC_ATTR4(handle, p, portn, attr, val0, val1, \
39644961713Sgirish 			val2, val3, stat) {\
39744961713Sgirish 	p.type = attr;\
39844961713Sgirish 	if ((stat = npi_mac_port_attr(handle, OP_GET, portn, \
39944961713Sgirish 					(npi_attr_t *)&p)) == NPI_SUCCESS) {\
40044961713Sgirish 		val0 = p.odata[0];\
40144961713Sgirish 		val1 = p.odata[1];\
40244961713Sgirish 		val2 = p.odata[2];\
40344961713Sgirish 		val3 = p.odata[3];\
40444961713Sgirish 	}\
40544961713Sgirish }
40644961713Sgirish 
40744961713Sgirish /* MAC specific errors */
40844961713Sgirish 
40944961713Sgirish #define	MAC_PORT_ATTR_INVALID		0x50
41044961713Sgirish #define	MAC_RESET_MODE_INVALID		0x51
41144961713Sgirish #define	MAC_HASHTAB_ENTRY_INVALID	0x52
41244961713Sgirish #define	MAC_HOSTINFO_ENTRY_INVALID	0x53
41344961713Sgirish #define	MAC_ALT_ADDR_ENTRY_INVALID	0x54
41444961713Sgirish 
41544961713Sgirish /* MAC error return macros */
41644961713Sgirish 
41744961713Sgirish #define	NPI_MAC_PORT_INVALID(portn)	((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
41844961713Sgirish 					PORT_INVALID | IS_PORT | (portn << 12))
41944961713Sgirish #define	NPI_MAC_OPCODE_INVALID(portn)	((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
42044961713Sgirish 					OPCODE_INVALID |\
42144961713Sgirish 					IS_PORT | (portn << 12))
42244961713Sgirish #define	NPI_MAC_HASHTAB_ENTRY_INVALID(portn)\
42344961713Sgirish 					((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
42444961713Sgirish 					MAC_HASHTAB_ENTRY_INVALID |\
42544961713Sgirish 					IS_PORT | (portn << 12))
42644961713Sgirish #define	NPI_MAC_HOSTINFO_ENTRY_INVALID(portn)\
42744961713Sgirish 					((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
42844961713Sgirish 					MAC_HOSTINFO_ENTRY_INVALID |\
42944961713Sgirish 					IS_PORT | (portn << 12))
43044961713Sgirish #define	NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)\
43144961713Sgirish 					((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
43244961713Sgirish 					MAC_ALT_ADDR_ENTRY_INVALID |\
43344961713Sgirish 					IS_PORT | (portn << 12))
43444961713Sgirish #define	NPI_MAC_PORT_ATTR_INVALID(portn)\
43544961713Sgirish 					((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
43644961713Sgirish 					MAC_PORT_ATTR_INVALID |\
43744961713Sgirish 					IS_PORT | (portn << 12))
43844961713Sgirish #define	NPI_MAC_RESET_MODE_INVALID(portn)\
43944961713Sgirish 					((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
44044961713Sgirish 					MAC_RESET_MODE_INVALID |\
44144961713Sgirish 					IS_PORT | (portn << 12))
44244961713Sgirish #define	NPI_MAC_PCS_REG_INVALID(portn)	((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
44344961713Sgirish 					REGISTER_INVALID |\
44444961713Sgirish 					IS_PORT | (portn << 12))
44544961713Sgirish #define	NPI_TXMAC_RESET_FAILED(portn)	((TXMAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
44644961713Sgirish 					RESET_FAILED | IS_PORT | (portn << 12))
44744961713Sgirish #define	NPI_RXMAC_RESET_FAILED(portn)	((RXMAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
44844961713Sgirish 					RESET_FAILED | IS_PORT | (portn << 12))
44944961713Sgirish #define	NPI_MAC_CONFIG_INVALID(portn)	((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
45044961713Sgirish 					CONFIG_INVALID |\
45144961713Sgirish 					IS_PORT | (portn << 12))
45244961713Sgirish #define	NPI_MAC_REG_INVALID(portn)	((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
45344961713Sgirish 					REGISTER_INVALID |\
45444961713Sgirish 					IS_PORT | (portn << 12))
45544961713Sgirish #define	NPI_MAC_MII_READ_FAILED(portn)	((MIF_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
45644961713Sgirish 					READ_FAILED | IS_PORT | (portn << 12))
45744961713Sgirish #define	NPI_MAC_MII_WRITE_FAILED(portn)	((MIF_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
45844961713Sgirish 					WRITE_FAILED | IS_PORT | (portn << 12))
45944961713Sgirish 
46044961713Sgirish /* library functions prototypes */
46144961713Sgirish 
46244961713Sgirish /* general mac functions */
46344961713Sgirish npi_status_t npi_mac_hashtab_entry(npi_handle_t, io_op_t,
46444961713Sgirish 				uint8_t, uint8_t, uint16_t *);
46544961713Sgirish npi_status_t npi_mac_hostinfo_entry(npi_handle_t, io_op_t,
46644961713Sgirish 				uint8_t, uint8_t,
46744961713Sgirish 				hostinfo_t *);
46844961713Sgirish npi_status_t npi_mac_altaddr_enable(npi_handle_t, uint8_t,
46944961713Sgirish 				uint8_t);
470*678453a8Sspeer npi_status_t npi_mac_altaddr_disable(npi_handle_t, uint8_t,
47144961713Sgirish 				uint8_t);
47244961713Sgirish npi_status_t npi_mac_altaddr_entry(npi_handle_t, io_op_t,
47344961713Sgirish 				uint8_t, uint8_t,
47444961713Sgirish 				npi_mac_addr_t *);
47544961713Sgirish npi_status_t npi_mac_port_attr(npi_handle_t, io_op_t, uint8_t,
47644961713Sgirish 				npi_attr_t *);
47744961713Sgirish npi_status_t npi_mac_get_link_status(npi_handle_t, uint8_t,
47844961713Sgirish 				boolean_t *);
47944961713Sgirish npi_status_t npi_mac_get_10g_link_status(npi_handle_t, uint8_t,
48044961713Sgirish 				boolean_t *);
48144961713Sgirish npi_status_t npi_mac_mif_mii_read(npi_handle_t, uint8_t,
48244961713Sgirish 				uint8_t, uint16_t *);
48344961713Sgirish npi_status_t npi_mac_mif_mii_write(npi_handle_t, uint8_t,
48444961713Sgirish 				uint8_t, uint16_t);
48544961713Sgirish npi_status_t npi_mac_mif_link_intr_enable(npi_handle_t, uint8_t,
48644961713Sgirish 				uint8_t, uint16_t);
48744961713Sgirish npi_status_t npi_mac_mif_mdio_read(npi_handle_t, uint8_t,
48844961713Sgirish 				uint8_t, uint16_t,
48944961713Sgirish 				uint16_t *);
49044961713Sgirish npi_status_t npi_mac_mif_mdio_write(npi_handle_t, uint8_t,
49144961713Sgirish 				uint8_t, uint16_t,
49244961713Sgirish 				uint16_t);
49344961713Sgirish npi_status_t npi_mac_mif_mdio_link_intr_enable(npi_handle_t,
49444961713Sgirish 				uint8_t, uint8_t,
49544961713Sgirish 				uint16_t, uint16_t);
49644961713Sgirish npi_status_t npi_mac_mif_link_intr_disable(npi_handle_t, uint8_t);
49744961713Sgirish npi_status_t npi_mac_pcs_mii_read(npi_handle_t, uint8_t,
49844961713Sgirish 				uint8_t, uint16_t *);
49944961713Sgirish npi_status_t npi_mac_pcs_mii_write(npi_handle_t, uint8_t,
50044961713Sgirish 				uint8_t, uint16_t);
50144961713Sgirish npi_status_t npi_mac_pcs_link_intr_enable(npi_handle_t, uint8_t);
50244961713Sgirish npi_status_t npi_mac_pcs_link_intr_disable(npi_handle_t, uint8_t);
50344961713Sgirish npi_status_t npi_mac_pcs_reset(npi_handle_t, uint8_t);
50444961713Sgirish 
50544961713Sgirish /* xmac functions */
50644961713Sgirish npi_status_t npi_xmac_reset(npi_handle_t, uint8_t,
50744961713Sgirish 				npi_mac_reset_t);
50844961713Sgirish npi_status_t npi_xmac_xif_config(npi_handle_t, config_op_t,
50944961713Sgirish 				uint8_t, xmac_xif_config_t);
51044961713Sgirish npi_status_t npi_xmac_tx_config(npi_handle_t, config_op_t,
51144961713Sgirish 				uint8_t, xmac_tx_config_t);
51244961713Sgirish npi_status_t npi_xmac_rx_config(npi_handle_t, config_op_t,
51344961713Sgirish 				uint8_t, xmac_rx_config_t);
51444961713Sgirish npi_status_t npi_xmac_tx_iconfig(npi_handle_t, config_op_t,
51544961713Sgirish 				uint8_t, xmac_tx_iconfig_t);
51644961713Sgirish npi_status_t npi_xmac_rx_iconfig(npi_handle_t, config_op_t,
51744961713Sgirish 				uint8_t, xmac_rx_iconfig_t);
51844961713Sgirish npi_status_t npi_xmac_ctl_iconfig(npi_handle_t, config_op_t,
51944961713Sgirish 				uint8_t, xmac_ctl_iconfig_t);
52044961713Sgirish npi_status_t npi_xmac_tx_get_istatus(npi_handle_t, uint8_t,
52144961713Sgirish 				xmac_tx_iconfig_t *);
52244961713Sgirish npi_status_t npi_xmac_rx_get_istatus(npi_handle_t, uint8_t,
52344961713Sgirish 				xmac_rx_iconfig_t *);
52444961713Sgirish npi_status_t npi_xmac_ctl_get_istatus(npi_handle_t, uint8_t,
52544961713Sgirish 				xmac_ctl_iconfig_t *);
52644961713Sgirish npi_status_t npi_xmac_xpcs_reset(npi_handle_t, uint8_t);
52744961713Sgirish npi_status_t npi_xmac_xpcs_enable(npi_handle_t, uint8_t);
52844961713Sgirish npi_status_t npi_xmac_xpcs_disable(npi_handle_t, uint8_t);
52944961713Sgirish npi_status_t npi_xmac_xpcs_read(npi_handle_t, uint8_t,
53044961713Sgirish 				uint8_t, uint32_t *);
53144961713Sgirish npi_status_t npi_xmac_xpcs_write(npi_handle_t, uint8_t,
53244961713Sgirish 				uint8_t, uint32_t);
53344961713Sgirish npi_status_t npi_xmac_xpcs_link_intr_enable(npi_handle_t, uint8_t);
53444961713Sgirish npi_status_t npi_xmac_xpcs_link_intr_disable(npi_handle_t,
53544961713Sgirish 				uint8_t);
53644961713Sgirish npi_status_t npi_xmac_xif_led(npi_handle_t, uint8_t,
53744961713Sgirish 				boolean_t);
53844961713Sgirish npi_status_t npi_xmac_zap_tx_counters(npi_handle_t, uint8_t);
53944961713Sgirish npi_status_t npi_xmac_zap_rx_counters(npi_handle_t, uint8_t);
54044961713Sgirish 
54144961713Sgirish /* bmac functions */
54244961713Sgirish npi_status_t npi_bmac_reset(npi_handle_t, uint8_t,
54344961713Sgirish 				npi_mac_reset_t mode);
54444961713Sgirish npi_status_t npi_bmac_tx_config(npi_handle_t, config_op_t,
54544961713Sgirish 				uint8_t, bmac_tx_config_t);
54644961713Sgirish npi_status_t npi_bmac_rx_config(npi_handle_t, config_op_t,
54744961713Sgirish 				uint8_t, bmac_rx_config_t);
54844961713Sgirish npi_status_t npi_bmac_rx_iconfig(npi_handle_t, config_op_t,
54944961713Sgirish 				uint8_t, bmac_rx_iconfig_t);
55044961713Sgirish npi_status_t npi_bmac_xif_config(npi_handle_t, config_op_t,
55144961713Sgirish 				uint8_t, bmac_xif_config_t);
55244961713Sgirish npi_status_t npi_bmac_tx_iconfig(npi_handle_t, config_op_t,
55344961713Sgirish 				uint8_t, bmac_tx_iconfig_t);
55444961713Sgirish npi_status_t npi_bmac_ctl_iconfig(npi_handle_t, config_op_t,
55544961713Sgirish 				uint8_t, bmac_ctl_iconfig_t);
55644961713Sgirish npi_status_t npi_bmac_tx_get_istatus(npi_handle_t, uint8_t,
55744961713Sgirish 				bmac_tx_iconfig_t *);
55844961713Sgirish npi_status_t npi_bmac_rx_get_istatus(npi_handle_t, uint8_t,
55944961713Sgirish 				bmac_rx_iconfig_t *);
56044961713Sgirish npi_status_t npi_bmac_ctl_get_istatus(npi_handle_t, uint8_t,
56144961713Sgirish 				bmac_ctl_iconfig_t *);
56244961713Sgirish npi_status_t npi_bmac_send_pause(npi_handle_t, uint8_t,
56344961713Sgirish 				uint16_t);
56444961713Sgirish npi_status_t npi_mac_dump_regs(npi_handle_t, uint8_t);
56544961713Sgirish 
56644961713Sgirish /* MIF common functions */
56744961713Sgirish void npi_mac_mif_set_indirect_mode(npi_handle_t, boolean_t);
568d81011f0Ssbehera void npi_mac_mif_set_atca_mode(npi_handle_t, boolean_t);
56944961713Sgirish 
57044961713Sgirish #ifdef	__cplusplus
57144961713Sgirish }
57244961713Sgirish #endif
57344961713Sgirish 
57444961713Sgirish #endif	/* _NPI_MAC_H */
575