144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 22*678453a8Sspeer * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 2344961713Sgirish * Use is subject to license terms. 2444961713Sgirish */ 2544961713Sgirish 2644961713Sgirish #ifndef _NPI_MAC_H 2744961713Sgirish #define _NPI_MAC_H 2844961713Sgirish 2944961713Sgirish #ifdef __cplusplus 3044961713Sgirish extern "C" { 3144961713Sgirish #endif 3244961713Sgirish 3344961713Sgirish #include <npi.h> 3444961713Sgirish #include <nxge_mac_hw.h> 3544961713Sgirish #include <nxge_mii.h> 3644961713Sgirish 3744961713Sgirish typedef struct _npi_mac_addr { 3844961713Sgirish uint16_t w0; 3944961713Sgirish uint16_t w1; 4044961713Sgirish uint16_t w2; 4144961713Sgirish } npi_mac_addr_t; 4244961713Sgirish 4344961713Sgirish typedef enum npi_mac_attr { 4444961713Sgirish MAC_PORT_MODE = 0, 4544961713Sgirish MAC_PORT_FRAME_SIZE, 4644961713Sgirish MAC_PORT_ADDR, 4744961713Sgirish MAC_PORT_ADDR_FILTER, 4844961713Sgirish MAC_PORT_ADDR_FILTER_MASK, 4944961713Sgirish XMAC_PORT_IPG, 5044961713Sgirish XMAC_10G_PORT_IPG, 5144961713Sgirish BMAC_PORT_MAX_BURST_SIZE, 5244961713Sgirish BMAC_PORT_PA_SIZE, 5344961713Sgirish BMAC_PORT_CTRL_TYPE 5444961713Sgirish } npi_mac_attr_t; 5544961713Sgirish 5644961713Sgirish /* MAC Mode options */ 5744961713Sgirish 5844961713Sgirish typedef enum npi_mac_mode_e { 5944961713Sgirish MAC_MII_MODE = 0, 6044961713Sgirish MAC_GMII_MODE, 6144961713Sgirish MAC_XGMII_MODE 6244961713Sgirish } npi_mac_mode_t; 6344961713Sgirish 6444961713Sgirish typedef enum npi_mac_reset_e { 6544961713Sgirish TX_MAC_RESET = 1, 6644961713Sgirish RX_MAC_RESET, 6744961713Sgirish XTX_MAC_REG_RESET, 6844961713Sgirish XRX_MAC_REG_RESET, 6944961713Sgirish XTX_MAC_LOGIC_RESET, 7044961713Sgirish XRX_MAC_LOGIC_RESET, 7144961713Sgirish XTX_MAC_RESET_ALL, 7244961713Sgirish XRX_MAC_RESET_ALL, 7344961713Sgirish BMAC_RESET_ALL, 7444961713Sgirish XMAC_RESET_ALL 7544961713Sgirish } npi_mac_reset_t; 7644961713Sgirish 7744961713Sgirish typedef enum xmac_tx_iconfig_e { 7844961713Sgirish ICFG_XMAC_TX_FRAME_XMIT = XMAC_TX_FRAME_XMIT, 7944961713Sgirish ICFG_XMAC_TX_UNDERRUN = XMAC_TX_UNDERRUN, 8044961713Sgirish ICFG_XMAC_TX_MAX_PACKET_ERR = XMAC_TX_MAX_PACKET_ERR, 8144961713Sgirish ICFG_XMAC_TX_OVERFLOW = XMAC_TX_OVERFLOW, 8244961713Sgirish ICFG_XMAC_TX_FIFO_XFR_ERR = XMAC_TX_FIFO_XFR_ERR, 8344961713Sgirish ICFG_XMAC_TX_BYTE_CNT_EXP = XMAC_TX_BYTE_CNT_EXP, 8444961713Sgirish ICFG_XMAC_TX_FRAME_CNT_EXP = XMAC_TX_FRAME_CNT_EXP, 8544961713Sgirish ICFG_XMAC_TX_ALL = (XMAC_TX_FRAME_XMIT | XMAC_TX_UNDERRUN | 8644961713Sgirish XMAC_TX_MAX_PACKET_ERR | XMAC_TX_OVERFLOW | 8744961713Sgirish XMAC_TX_FIFO_XFR_ERR | XMAC_TX_BYTE_CNT_EXP | 8844961713Sgirish XMAC_TX_FRAME_CNT_EXP) 8944961713Sgirish } xmac_tx_iconfig_t; 9044961713Sgirish 9144961713Sgirish typedef enum xmac_rx_iconfig_e { 9244961713Sgirish ICFG_XMAC_RX_FRAME_RCVD = XMAC_RX_FRAME_RCVD, 9344961713Sgirish ICFG_XMAC_RX_OVERFLOW = XMAC_RX_OVERFLOW, 9444961713Sgirish ICFG_XMAC_RX_UNDERFLOW = XMAC_RX_UNDERFLOW, 9544961713Sgirish ICFG_XMAC_RX_CRC_ERR_CNT_EXP = XMAC_RX_CRC_ERR_CNT_EXP, 9644961713Sgirish ICFG_XMAC_RX_LEN_ERR_CNT_EXP = XMAC_RX_LEN_ERR_CNT_EXP, 9744961713Sgirish ICFG_XMAC_RX_VIOL_ERR_CNT_EXP = XMAC_RX_VIOL_ERR_CNT_EXP, 9844961713Sgirish ICFG_XMAC_RX_OCT_CNT_EXP = XMAC_RX_OCT_CNT_EXP, 9944961713Sgirish ICFG_XMAC_RX_HST_CNT1_EXP = XMAC_RX_HST_CNT1_EXP, 10044961713Sgirish ICFG_XMAC_RX_HST_CNT2_EXP = XMAC_RX_HST_CNT2_EXP, 10144961713Sgirish ICFG_XMAC_RX_HST_CNT3_EXP = XMAC_RX_HST_CNT3_EXP, 10244961713Sgirish ICFG_XMAC_RX_HST_CNT4_EXP = XMAC_RX_HST_CNT4_EXP, 10344961713Sgirish ICFG_XMAC_RX_HST_CNT5_EXP = XMAC_RX_HST_CNT5_EXP, 10444961713Sgirish ICFG_XMAC_RX_HST_CNT6_EXP = XMAC_RX_HST_CNT6_EXP, 10544961713Sgirish ICFG_XMAC_RX_BCAST_CNT_EXP = XMAC_RX_BCAST_CNT_EXP, 10644961713Sgirish ICFG_XMAC_RX_MCAST_CNT_EXP = XMAC_RX_MCAST_CNT_EXP, 10744961713Sgirish ICFG_XMAC_RX_FRAG_CNT_EXP = XMAC_RX_FRAG_CNT_EXP, 10844961713Sgirish ICFG_XMAC_RX_ALIGNERR_CNT_EXP = XMAC_RX_ALIGNERR_CNT_EXP, 10944961713Sgirish ICFG_XMAC_RX_LINK_FLT_CNT_EXP = XMAC_RX_LINK_FLT_CNT_EXP, 11044961713Sgirish ICFG_XMAC_RX_HST_CNT7_EXP = XMAC_RX_HST_CNT7_EXP, 11144961713Sgirish ICFG_XMAC_RX_REMOTE_FLT_DET = XMAC_RX_REMOTE_FLT_DET, 11244961713Sgirish ICFG_XMAC_RX_LOCAL_FLT_DET = XMAC_RX_LOCAL_FLT_DET, 11344961713Sgirish ICFG_XMAC_RX_ALL = (XMAC_RX_FRAME_RCVD | XMAC_RX_OVERFLOW | 11444961713Sgirish XMAC_RX_UNDERFLOW | XMAC_RX_CRC_ERR_CNT_EXP | 11544961713Sgirish XMAC_RX_LEN_ERR_CNT_EXP | 11644961713Sgirish XMAC_RX_VIOL_ERR_CNT_EXP | 11744961713Sgirish XMAC_RX_OCT_CNT_EXP | XMAC_RX_HST_CNT1_EXP | 11844961713Sgirish XMAC_RX_HST_CNT2_EXP | XMAC_RX_HST_CNT3_EXP | 11944961713Sgirish XMAC_RX_HST_CNT4_EXP | XMAC_RX_HST_CNT5_EXP | 12044961713Sgirish XMAC_RX_HST_CNT6_EXP | XMAC_RX_BCAST_CNT_EXP | 12144961713Sgirish XMAC_RX_MCAST_CNT_EXP | XMAC_RX_FRAG_CNT_EXP | 12244961713Sgirish XMAC_RX_ALIGNERR_CNT_EXP | 12344961713Sgirish XMAC_RX_LINK_FLT_CNT_EXP | 12444961713Sgirish XMAC_RX_HST_CNT7_EXP | 12544961713Sgirish XMAC_RX_REMOTE_FLT_DET | XMAC_RX_LOCAL_FLT_DET) 12644961713Sgirish } xmac_rx_iconfig_t; 12744961713Sgirish 12844961713Sgirish typedef enum xmac_ctl_iconfig_e { 12944961713Sgirish ICFG_XMAC_CTRL_PAUSE_RCVD = XMAC_CTRL_PAUSE_RCVD, 13044961713Sgirish ICFG_XMAC_CTRL_PAUSE_STATE = XMAC_CTRL_PAUSE_STATE, 13144961713Sgirish ICFG_XMAC_CTRL_NOPAUSE_STATE = XMAC_CTRL_NOPAUSE_STATE, 13244961713Sgirish ICFG_XMAC_CTRL_ALL = (XMAC_CTRL_PAUSE_RCVD | XMAC_CTRL_PAUSE_STATE | 13344961713Sgirish XMAC_CTRL_NOPAUSE_STATE) 13444961713Sgirish } xmac_ctl_iconfig_t; 13544961713Sgirish 13644961713Sgirish 13744961713Sgirish typedef enum bmac_tx_iconfig_e { 13844961713Sgirish ICFG_BMAC_TX_FRAME_SENT = MAC_TX_FRAME_XMIT, 13944961713Sgirish ICFG_BMAC_TX_UNDERFLOW = MAC_TX_UNDERRUN, 14044961713Sgirish ICFG_BMAC_TX_MAXPKTSZ_ERR = MAC_TX_MAX_PACKET_ERR, 14144961713Sgirish ICFG_BMAC_TX_BYTE_CNT_EXP = MAC_TX_BYTE_CNT_EXP, 14244961713Sgirish ICFG_BMAC_TX_FRAME_CNT_EXP = MAC_TX_FRAME_CNT_EXP, 14344961713Sgirish ICFG_BMAC_TX_ALL = (MAC_TX_FRAME_XMIT | MAC_TX_UNDERRUN | 14444961713Sgirish MAC_TX_MAX_PACKET_ERR | MAC_TX_BYTE_CNT_EXP | 14544961713Sgirish MAC_TX_FRAME_CNT_EXP) 14644961713Sgirish } bmac_tx_iconfig_t; 14744961713Sgirish 14844961713Sgirish typedef enum bmac_rx_iconfig_e { 14944961713Sgirish ICFG_BMAC_RX_FRAME_RCVD = MAC_RX_FRAME_RECV, 15044961713Sgirish ICFG_BMAC_RX_OVERFLOW = MAC_RX_OVERFLOW, 15144961713Sgirish ICFG_BMAC_RX_FRAME_CNT_EXP = MAC_RX_FRAME_COUNT, 15244961713Sgirish ICFG_BMAC_RX_CRC_ERR_CNT_EXP = MAC_RX_ALIGN_ERR, 15344961713Sgirish ICFG_BMAC_RX_LEN_ERR_CNT_EXP = MAC_RX_CRC_ERR, 15444961713Sgirish ICFG_BMAC_RX_VIOL_ERR_CNT_EXP = MAC_RX_LEN_ERR, 15544961713Sgirish ICFG_BMAC_RX_BYTE_CNT_EXP = MAC_RX_VIOL_ERR, 15644961713Sgirish ICFG_BMAC_RX_ALIGNERR_CNT_EXP = MAC_RX_BYTE_CNT_EXP, 15744961713Sgirish ICFG_BMAC_RX_ALL = (MAC_RX_FRAME_RECV | MAC_RX_OVERFLOW | 15844961713Sgirish MAC_RX_FRAME_COUNT | MAC_RX_ALIGN_ERR | 15944961713Sgirish MAC_RX_CRC_ERR | MAC_RX_LEN_ERR | 16044961713Sgirish MAC_RX_VIOL_ERR | MAC_RX_BYTE_CNT_EXP) 16144961713Sgirish } bmac_rx_iconfig_t; 16244961713Sgirish 16344961713Sgirish typedef enum bmac_ctl_iconfig_e { 16444961713Sgirish ICFG_BMAC_CTL_RCVPAUSE = MAC_CTRL_PAUSE_RECEIVED, 16544961713Sgirish ICFG_BMAC_CTL_INPAUSE_ST = MAC_CTRL_PAUSE_STATE, 16644961713Sgirish ICFG_BMAC_CTL_INNOTPAUSE_ST = MAC_CTRL_NOPAUSE_STATE, 16744961713Sgirish ICFG_BMAC_CTL_ALL = (MAC_CTRL_PAUSE_RECEIVED | MAC_CTRL_PAUSE_STATE | 16844961713Sgirish MAC_CTRL_NOPAUSE_STATE) 16944961713Sgirish } bmac_ctl_iconfig_t; 17044961713Sgirish 17144961713Sgirish typedef enum xmac_tx_config_e { 17244961713Sgirish CFG_XMAC_TX = 0x00000001, 17344961713Sgirish CFG_XMAC_TX_STRETCH_MODE = 0x00000002, 17444961713Sgirish CFG_XMAC_VAR_IPG = 0x00000004, 17544961713Sgirish CFG_XMAC_TX_CRC = 0x00000008, 17644961713Sgirish CFG_XMAC_TX_ALL = 0x0000000F 17744961713Sgirish } xmac_tx_config_t; 17844961713Sgirish 17944961713Sgirish typedef enum xmac_rx_config_e { 18044961713Sgirish CFG_XMAC_RX = 0x00000001, 18144961713Sgirish CFG_XMAC_RX_PROMISCUOUS = 0x00000002, 18244961713Sgirish CFG_XMAC_RX_PROMISCUOUSGROUP = 0x00000004, 18344961713Sgirish CFG_XMAC_RX_ERRCHK = 0x00000008, 18444961713Sgirish CFG_XMAC_RX_CRC_CHK = 0x00000010, 18544961713Sgirish CFG_XMAC_RX_RESV_MULTICAST = 0x00000020, 18644961713Sgirish CFG_XMAC_RX_CODE_VIO_CHK = 0x00000040, 18744961713Sgirish CFG_XMAC_RX_HASH_FILTER = 0x00000080, 18844961713Sgirish CFG_XMAC_RX_ADDR_FILTER = 0x00000100, 18944961713Sgirish CFG_XMAC_RX_STRIP_CRC = 0x00000200, 19044961713Sgirish CFG_XMAC_RX_PAUSE = 0x00000400, 19144961713Sgirish CFG_XMAC_RX_PASS_FC_FRAME = 0x00000800, 19244961713Sgirish CFG_XMAC_RX_MAC2IPP_PKT_CNT = 0x00001000, 19344961713Sgirish CFG_XMAC_RX_ALL = 0x00001FFF 19444961713Sgirish } xmac_rx_config_t; 19544961713Sgirish 19644961713Sgirish typedef enum xmac_xif_config_e { 19744961713Sgirish CFG_XMAC_XIF_LED_FORCE = 0x00000001, 19844961713Sgirish CFG_XMAC_XIF_LED_POLARITY = 0x00000002, 19944961713Sgirish CFG_XMAC_XIF_SEL_POR_CLK_SRC = 0x00000004, 20044961713Sgirish CFG_XMAC_XIF_TX_OUTPUT = 0x00000008, 20144961713Sgirish CFG_XMAC_XIF_LOOPBACK = 0x00000010, 20244961713Sgirish CFG_XMAC_XIF_LFS = 0x00000020, 20344961713Sgirish CFG_XMAC_XIF_XPCS_BYPASS = 0x00000040, 20444961713Sgirish CFG_XMAC_XIF_1G_PCS_BYPASS = 0x00000080, 20544961713Sgirish CFG_XMAC_XIF_SEL_CLK_25MHZ = 0x00000100, 20644961713Sgirish CFG_XMAC_XIF_ALL = 0x000001FF 20744961713Sgirish } xmac_xif_config_t; 20844961713Sgirish 20944961713Sgirish typedef enum bmac_tx_config_e { 21044961713Sgirish CFG_BMAC_TX = 0x00000001, 21144961713Sgirish CFG_BMAC_TX_CRC = 0x00000002, 21244961713Sgirish CFG_BMAC_TX_ALL = 0x00000003 21344961713Sgirish } bmac_tx_config_t; 21444961713Sgirish 21544961713Sgirish typedef enum bmac_rx_config_e { 21644961713Sgirish CFG_BMAC_RX = 0x00000001, 21744961713Sgirish CFG_BMAC_RX_STRIP_PAD = 0x00000002, 21844961713Sgirish CFG_BMAC_RX_STRIP_CRC = 0x00000004, 21944961713Sgirish CFG_BMAC_RX_PROMISCUOUS = 0x00000008, 22044961713Sgirish CFG_BMAC_RX_PROMISCUOUSGROUP = 0x00000010, 22144961713Sgirish CFG_BMAC_RX_HASH_FILTER = 0x00000020, 22244961713Sgirish CFG_BMAC_RX_ADDR_FILTER = 0x00000040, 22344961713Sgirish CFG_BMAC_RX_DISCARD_ON_ERR = 0x00000080, 22444961713Sgirish CFG_BMAC_RX_ALL = 0x000000FF 22544961713Sgirish } bmac_rx_config_t; 22644961713Sgirish 22744961713Sgirish typedef enum bmac_xif_config_e { 22844961713Sgirish CFG_BMAC_XIF_TX_OUTPUT = 0x00000001, 22944961713Sgirish CFG_BMAC_XIF_LOOPBACK = 0x00000002, 23044961713Sgirish CFG_BMAC_XIF_GMII_MODE = 0x00000008, 23144961713Sgirish CFG_BMAC_XIF_LINKLED = 0x00000020, 23244961713Sgirish CFG_BMAC_XIF_LED_POLARITY = 0x00000040, 23344961713Sgirish CFG_BMAC_XIF_SEL_CLK_25MHZ = 0x00000080, 23444961713Sgirish CFG_BMAC_XIF_ALL = 0x000000FF 23544961713Sgirish } bmac_xif_config_t; 23644961713Sgirish 23744961713Sgirish 23844961713Sgirish typedef enum xmac_ipg_e { 23944961713Sgirish XGMII_IPG_12_15 = 0, 24044961713Sgirish XGMII_IPG_16_19, 24144961713Sgirish XGMII_IPG_20_23, 24244961713Sgirish MII_GMII_IPG_12, 24344961713Sgirish MII_GMII_IPG_13, 24444961713Sgirish MII_GMII_IPG_14, 24544961713Sgirish MII_GMII_IPG_15, 24644961713Sgirish MII_GMII_IPG_16 24744961713Sgirish } xmac_ipg_t; 24844961713Sgirish 24944961713Sgirish typedef enum xpcs_reg_e { 25044961713Sgirish XPCS_REG_CONTROL1, 25144961713Sgirish XPCS_REG_STATUS1, 25244961713Sgirish XPCS_REG_DEVICE_ID, 25344961713Sgirish XPCS_REG_SPEED_ABILITY, 25444961713Sgirish XPCS_REG_DEVICE_IN_PKG, 25544961713Sgirish XPCS_REG_CONTROL2, 25644961713Sgirish XPCS_REG_STATUS2, 25744961713Sgirish XPCS_REG_PKG_ID, 25844961713Sgirish XPCS_REG_STATUS, 25944961713Sgirish XPCS_REG_TEST_CONTROL, 26044961713Sgirish XPCS_REG_CONFIG_VENDOR1, 26144961713Sgirish XPCS_REG_DIAG_VENDOR2, 26244961713Sgirish XPCS_REG_MASK1, 26344961713Sgirish XPCS_REG_PACKET_COUNTER, 26444961713Sgirish XPCS_REG_TX_STATEMACHINE, 26544961713Sgirish XPCS_REG_DESCWERR_COUNTER, 26644961713Sgirish XPCS_REG_SYMBOL_ERR_L0_1_COUNTER, 26744961713Sgirish XPCS_REG_SYMBOL_ERR_L2_3_COUNTER, 26844961713Sgirish XPCS_REG_TRAINING_VECTOR 26944961713Sgirish } xpcs_reg_t; 27044961713Sgirish 27144961713Sgirish #define IS_XMAC_PORT_NUM_VALID(portn)\ 27244961713Sgirish ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) 27344961713Sgirish 27444961713Sgirish #define IS_BMAC_PORT_NUM_VALID(portn)\ 27544961713Sgirish ((portn == BMAC_PORT_0) || (portn == BMAC_PORT_1)) 27644961713Sgirish 27744961713Sgirish #define XMAC_REG_WR(handle, portn, reg, val)\ 27844961713Sgirish NXGE_REG_WR64(handle, XMAC_REG_ADDR((portn), (reg)), (val)) 27944961713Sgirish 28044961713Sgirish #define XMAC_REG_RD(handle, portn, reg, val_p)\ 28144961713Sgirish NXGE_REG_RD64(handle, XMAC_REG_ADDR((portn), (reg)), (val_p)) 28244961713Sgirish 28344961713Sgirish #define BMAC_REG_WR(handle, portn, reg, val)\ 28444961713Sgirish NXGE_REG_WR64(handle, BMAC_REG_ADDR((portn), (reg)), (val)) 28544961713Sgirish 28644961713Sgirish #define BMAC_REG_RD(handle, portn, reg, val_p)\ 28744961713Sgirish NXGE_REG_RD64(handle, BMAC_REG_ADDR((portn), (reg)), (val_p)) 28844961713Sgirish 28944961713Sgirish #define PCS_REG_WR(handle, portn, reg, val)\ 29044961713Sgirish NXGE_REG_WR64(handle, PCS_REG_ADDR((portn), (reg)), (val)) 29144961713Sgirish 29244961713Sgirish #define PCS_REG_RD(handle, portn, reg, val_p)\ 29344961713Sgirish NXGE_REG_RD64(handle, PCS_REG_ADDR((portn), (reg)), (val_p)) 29444961713Sgirish 29544961713Sgirish #define XPCS_REG_WR(handle, portn, reg, val)\ 29644961713Sgirish NXGE_REG_WR64(handle, XPCS_ADDR((portn), (reg)), (val)) 29744961713Sgirish 29844961713Sgirish #define XPCS_REG_RD(handle, portn, reg, val_p)\ 29944961713Sgirish NXGE_REG_RD64(handle, XPCS_ADDR((portn), (reg)), (val_p)) 30044961713Sgirish 30144961713Sgirish #define MIF_REG_WR(handle, reg, val)\ 30244961713Sgirish NXGE_REG_WR64(handle, MIF_ADDR((reg)), (val)) 30344961713Sgirish 30444961713Sgirish #define MIF_REG_RD(handle, reg, val_p)\ 30544961713Sgirish NXGE_REG_RD64(handle, MIF_ADDR((reg)), (val_p)) 30644961713Sgirish 30744961713Sgirish 30844961713Sgirish /* 30944961713Sgirish * When MIF_REG_RD is called inside a poll loop and if the poll takes 31044961713Sgirish * very long time to complete, then each poll will print a rt_show_reg 31144961713Sgirish * result on the screen and the rtrace "register show" result may 31244961713Sgirish * become too messy to read. The solution is to call MIF_REG_RD_NO_SHOW 31344961713Sgirish * instead of MIF_REG_RD in a polling loop. When COSIM or REG_SHOW is 31444961713Sgirish * not defined, this macro is the same as MIF_REG_RD. When both COSIM 31544961713Sgirish * and REG_SHOW are defined, this macro calls NXGE_REG_RD64_NO_SHOW 31644961713Sgirish * which does not call rt_show_reg. 31744961713Sgirish */ 31844961713Sgirish #if defined(COSIM) && defined(REG_SHOW) 31944961713Sgirish #define MIF_REG_RD_NO_SHOW(handle, reg, val_p)\ 32044961713Sgirish NXGE_REG_RD64_NO_SHOW(handle, MIF_ADDR((reg)), (val_p)) 32144961713Sgirish #else 32244961713Sgirish /* If not COSIM or REG_SHOW, still show */ 32344961713Sgirish #define MIF_REG_RD_NO_SHOW(handle, reg, val_p)\ 32444961713Sgirish NXGE_REG_RD64(handle, MIF_ADDR((reg)), (val_p)) 32544961713Sgirish #endif 32644961713Sgirish 32744961713Sgirish #define ESR_REG_WR(handle, reg, val)\ 32844961713Sgirish NXGE_REG_WR64(handle, ESR_ADDR((reg)), (val)) 32944961713Sgirish 33044961713Sgirish #define ESR_REG_RD(handle, reg, val_p)\ 33144961713Sgirish NXGE_REG_RD64(handle, ESR_ADDR((reg)), (val_p)) 33244961713Sgirish 33344961713Sgirish /* Macros to read/modify MAC attributes */ 33444961713Sgirish 33544961713Sgirish #define SET_MAC_ATTR1(handle, p, portn, attr, val, stat) {\ 33644961713Sgirish p.type = attr;\ 33744961713Sgirish p.idata[0] = (uint32_t)val;\ 33844961713Sgirish stat = npi_mac_port_attr(handle, OP_SET, portn, (npi_attr_t *)&p);\ 33944961713Sgirish } 34044961713Sgirish 34144961713Sgirish #define SET_MAC_ATTR2(handle, p, portn, attr, val0, val1, stat) {\ 34244961713Sgirish p.type = attr;\ 34344961713Sgirish p.idata[0] = (uint32_t)val0;\ 34444961713Sgirish p.idata[1] = (uint32_t)val1;\ 34544961713Sgirish stat = npi_mac_port_attr(handle, OP_SET, portn, (npi_attr_t *)&p);\ 34644961713Sgirish } 34744961713Sgirish 34844961713Sgirish #define SET_MAC_ATTR3(handle, p, portn, attr, val0, val1, val2, stat) {\ 34944961713Sgirish p.type = attr;\ 35044961713Sgirish p.idata[0] = (uint32_t)val0;\ 35144961713Sgirish p.idata[1] = (uint32_t)val1;\ 35244961713Sgirish p.idata[2] = (uint32_t)val2;\ 35344961713Sgirish stat = npi_mac_port_attr(handle, OP_SET, portn, (npi_attr_t *)&p);\ 35444961713Sgirish } 35544961713Sgirish 35644961713Sgirish #define SET_MAC_ATTR4(handle, p, portn, attr, val0, val1, val2, val3, stat) {\ 35744961713Sgirish p.type = attr;\ 35844961713Sgirish p.idata[0] = (uint32_t)val0;\ 35944961713Sgirish p.idata[1] = (uint32_t)val1;\ 36044961713Sgirish p.idata[2] = (uint32_t)val2;\ 36144961713Sgirish p.idata[3] = (uint32_t)val3;\ 36244961713Sgirish stat = npi_mac_port_attr(handle, OP_SET, portn, (npi_attr_t *)&p);\ 36344961713Sgirish } 36444961713Sgirish 36544961713Sgirish #define GET_MAC_ATTR1(handle, p, portn, attr, val, stat) {\ 36644961713Sgirish p.type = attr;\ 36744961713Sgirish if ((stat = npi_mac_port_attr(handle, OP_GET, portn, \ 36844961713Sgirish (npi_attr_t *)&p)) == NPI_SUCCESS) {\ 36944961713Sgirish val = p.odata[0];\ 37044961713Sgirish }\ 37144961713Sgirish } 37244961713Sgirish 37344961713Sgirish #define GET_MAC_ATTR2(handle, p, portn, attr, val0, val1, stat) {\ 37444961713Sgirish p.type = attr;\ 37544961713Sgirish if ((stat = npi_mac_port_attr(handle, OP_GET, portn, \ 37644961713Sgirish (npi_attr_t *)&p)) == NPI_SUCCESS) {\ 37744961713Sgirish val0 = p.odata[0];\ 37844961713Sgirish val1 = p.odata[1];\ 37944961713Sgirish }\ 38044961713Sgirish } 38144961713Sgirish 38244961713Sgirish #define GET_MAC_ATTR3(handle, p, portn, attr, val0, val1, \ 38344961713Sgirish val2, stat) {\ 38444961713Sgirish p.type = attr;\ 38544961713Sgirish if ((stat = npi_mac_port_attr(handle, OP_GET, portn, \ 38644961713Sgirish (npi_attr_t *)&p)) == NPI_SUCCESS) {\ 38744961713Sgirish val0 = p.odata[0];\ 38844961713Sgirish val1 = p.odata[1];\ 38944961713Sgirish val2 = p.odata[2];\ 39044961713Sgirish }\ 39144961713Sgirish } 39244961713Sgirish 39344961713Sgirish #define GET_MAC_ATTR4(handle, p, portn, attr, val0, val1, \ 39444961713Sgirish val2, val3, stat) {\ 39544961713Sgirish p.type = attr;\ 39644961713Sgirish if ((stat = npi_mac_port_attr(handle, OP_GET, portn, \ 39744961713Sgirish (npi_attr_t *)&p)) == NPI_SUCCESS) {\ 39844961713Sgirish val0 = p.odata[0];\ 39944961713Sgirish val1 = p.odata[1];\ 40044961713Sgirish val2 = p.odata[2];\ 40144961713Sgirish val3 = p.odata[3];\ 40244961713Sgirish }\ 40344961713Sgirish } 40444961713Sgirish 40544961713Sgirish /* MAC specific errors */ 40644961713Sgirish 40744961713Sgirish #define MAC_PORT_ATTR_INVALID 0x50 40844961713Sgirish #define MAC_RESET_MODE_INVALID 0x51 40944961713Sgirish #define MAC_HASHTAB_ENTRY_INVALID 0x52 41044961713Sgirish #define MAC_HOSTINFO_ENTRY_INVALID 0x53 41144961713Sgirish #define MAC_ALT_ADDR_ENTRY_INVALID 0x54 41244961713Sgirish 41344961713Sgirish /* MAC error return macros */ 41444961713Sgirish 41544961713Sgirish #define NPI_MAC_PORT_INVALID(portn) ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 41644961713Sgirish PORT_INVALID | IS_PORT | (portn << 12)) 41744961713Sgirish #define NPI_MAC_OPCODE_INVALID(portn) ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 41844961713Sgirish OPCODE_INVALID |\ 41944961713Sgirish IS_PORT | (portn << 12)) 42044961713Sgirish #define NPI_MAC_HASHTAB_ENTRY_INVALID(portn)\ 42144961713Sgirish ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 42244961713Sgirish MAC_HASHTAB_ENTRY_INVALID |\ 42344961713Sgirish IS_PORT | (portn << 12)) 42444961713Sgirish #define NPI_MAC_HOSTINFO_ENTRY_INVALID(portn)\ 42544961713Sgirish ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 42644961713Sgirish MAC_HOSTINFO_ENTRY_INVALID |\ 42744961713Sgirish IS_PORT | (portn << 12)) 42844961713Sgirish #define NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)\ 42944961713Sgirish ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 43044961713Sgirish MAC_ALT_ADDR_ENTRY_INVALID |\ 43144961713Sgirish IS_PORT | (portn << 12)) 43244961713Sgirish #define NPI_MAC_PORT_ATTR_INVALID(portn)\ 43344961713Sgirish ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 43444961713Sgirish MAC_PORT_ATTR_INVALID |\ 43544961713Sgirish IS_PORT | (portn << 12)) 43644961713Sgirish #define NPI_MAC_RESET_MODE_INVALID(portn)\ 43744961713Sgirish ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 43844961713Sgirish MAC_RESET_MODE_INVALID |\ 43944961713Sgirish IS_PORT | (portn << 12)) 44044961713Sgirish #define NPI_MAC_PCS_REG_INVALID(portn) ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 44144961713Sgirish REGISTER_INVALID |\ 44244961713Sgirish IS_PORT | (portn << 12)) 44344961713Sgirish #define NPI_TXMAC_RESET_FAILED(portn) ((TXMAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 44444961713Sgirish RESET_FAILED | IS_PORT | (portn << 12)) 44544961713Sgirish #define NPI_RXMAC_RESET_FAILED(portn) ((RXMAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 44644961713Sgirish RESET_FAILED | IS_PORT | (portn << 12)) 44744961713Sgirish #define NPI_MAC_CONFIG_INVALID(portn) ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 44844961713Sgirish CONFIG_INVALID |\ 44944961713Sgirish IS_PORT | (portn << 12)) 45044961713Sgirish #define NPI_MAC_REG_INVALID(portn) ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 45144961713Sgirish REGISTER_INVALID |\ 45244961713Sgirish IS_PORT | (portn << 12)) 45344961713Sgirish #define NPI_MAC_MII_READ_FAILED(portn) ((MIF_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 45444961713Sgirish READ_FAILED | IS_PORT | (portn << 12)) 45544961713Sgirish #define NPI_MAC_MII_WRITE_FAILED(portn) ((MIF_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 45644961713Sgirish WRITE_FAILED | IS_PORT | (portn << 12)) 45744961713Sgirish 45844961713Sgirish /* library functions prototypes */ 45944961713Sgirish 46044961713Sgirish /* general mac functions */ 46144961713Sgirish npi_status_t npi_mac_hashtab_entry(npi_handle_t, io_op_t, 46244961713Sgirish uint8_t, uint8_t, uint16_t *); 46344961713Sgirish npi_status_t npi_mac_hostinfo_entry(npi_handle_t, io_op_t, 46444961713Sgirish uint8_t, uint8_t, 46544961713Sgirish hostinfo_t *); 46644961713Sgirish npi_status_t npi_mac_altaddr_enable(npi_handle_t, uint8_t, 46744961713Sgirish uint8_t); 468*678453a8Sspeer npi_status_t npi_mac_altaddr_disable(npi_handle_t, uint8_t, 46944961713Sgirish uint8_t); 47044961713Sgirish npi_status_t npi_mac_altaddr_entry(npi_handle_t, io_op_t, 47144961713Sgirish uint8_t, uint8_t, 47244961713Sgirish npi_mac_addr_t *); 47344961713Sgirish npi_status_t npi_mac_port_attr(npi_handle_t, io_op_t, uint8_t, 47444961713Sgirish npi_attr_t *); 47544961713Sgirish npi_status_t npi_mac_get_link_status(npi_handle_t, uint8_t, 47644961713Sgirish boolean_t *); 47744961713Sgirish npi_status_t npi_mac_get_10g_link_status(npi_handle_t, uint8_t, 47844961713Sgirish boolean_t *); 47944961713Sgirish npi_status_t npi_mac_mif_mii_read(npi_handle_t, uint8_t, 48044961713Sgirish uint8_t, uint16_t *); 48144961713Sgirish npi_status_t npi_mac_mif_mii_write(npi_handle_t, uint8_t, 48244961713Sgirish uint8_t, uint16_t); 48344961713Sgirish npi_status_t npi_mac_mif_link_intr_enable(npi_handle_t, uint8_t, 48444961713Sgirish uint8_t, uint16_t); 48544961713Sgirish npi_status_t npi_mac_mif_mdio_read(npi_handle_t, uint8_t, 48644961713Sgirish uint8_t, uint16_t, 48744961713Sgirish uint16_t *); 48844961713Sgirish npi_status_t npi_mac_mif_mdio_write(npi_handle_t, uint8_t, 48944961713Sgirish uint8_t, uint16_t, 49044961713Sgirish uint16_t); 49144961713Sgirish npi_status_t npi_mac_mif_mdio_link_intr_enable(npi_handle_t, 49244961713Sgirish uint8_t, uint8_t, 49344961713Sgirish uint16_t, uint16_t); 49444961713Sgirish npi_status_t npi_mac_mif_link_intr_disable(npi_handle_t, uint8_t); 49544961713Sgirish npi_status_t npi_mac_pcs_mii_read(npi_handle_t, uint8_t, 49644961713Sgirish uint8_t, uint16_t *); 49744961713Sgirish npi_status_t npi_mac_pcs_mii_write(npi_handle_t, uint8_t, 49844961713Sgirish uint8_t, uint16_t); 49944961713Sgirish npi_status_t npi_mac_pcs_link_intr_enable(npi_handle_t, uint8_t); 50044961713Sgirish npi_status_t npi_mac_pcs_link_intr_disable(npi_handle_t, uint8_t); 50144961713Sgirish npi_status_t npi_mac_pcs_reset(npi_handle_t, uint8_t); 50244961713Sgirish 50344961713Sgirish /* xmac functions */ 50444961713Sgirish npi_status_t npi_xmac_reset(npi_handle_t, uint8_t, 50544961713Sgirish npi_mac_reset_t); 50644961713Sgirish npi_status_t npi_xmac_xif_config(npi_handle_t, config_op_t, 50744961713Sgirish uint8_t, xmac_xif_config_t); 50844961713Sgirish npi_status_t npi_xmac_tx_config(npi_handle_t, config_op_t, 50944961713Sgirish uint8_t, xmac_tx_config_t); 51044961713Sgirish npi_status_t npi_xmac_rx_config(npi_handle_t, config_op_t, 51144961713Sgirish uint8_t, xmac_rx_config_t); 51244961713Sgirish npi_status_t npi_xmac_tx_iconfig(npi_handle_t, config_op_t, 51344961713Sgirish uint8_t, xmac_tx_iconfig_t); 51444961713Sgirish npi_status_t npi_xmac_rx_iconfig(npi_handle_t, config_op_t, 51544961713Sgirish uint8_t, xmac_rx_iconfig_t); 51644961713Sgirish npi_status_t npi_xmac_ctl_iconfig(npi_handle_t, config_op_t, 51744961713Sgirish uint8_t, xmac_ctl_iconfig_t); 51844961713Sgirish npi_status_t npi_xmac_tx_get_istatus(npi_handle_t, uint8_t, 51944961713Sgirish xmac_tx_iconfig_t *); 52044961713Sgirish npi_status_t npi_xmac_rx_get_istatus(npi_handle_t, uint8_t, 52144961713Sgirish xmac_rx_iconfig_t *); 52244961713Sgirish npi_status_t npi_xmac_ctl_get_istatus(npi_handle_t, uint8_t, 52344961713Sgirish xmac_ctl_iconfig_t *); 52444961713Sgirish npi_status_t npi_xmac_xpcs_reset(npi_handle_t, uint8_t); 52544961713Sgirish npi_status_t npi_xmac_xpcs_enable(npi_handle_t, uint8_t); 52644961713Sgirish npi_status_t npi_xmac_xpcs_disable(npi_handle_t, uint8_t); 52744961713Sgirish npi_status_t npi_xmac_xpcs_read(npi_handle_t, uint8_t, 52844961713Sgirish uint8_t, uint32_t *); 52944961713Sgirish npi_status_t npi_xmac_xpcs_write(npi_handle_t, uint8_t, 53044961713Sgirish uint8_t, uint32_t); 53144961713Sgirish npi_status_t npi_xmac_xpcs_link_intr_enable(npi_handle_t, uint8_t); 53244961713Sgirish npi_status_t npi_xmac_xpcs_link_intr_disable(npi_handle_t, 53344961713Sgirish uint8_t); 53444961713Sgirish npi_status_t npi_xmac_xif_led(npi_handle_t, uint8_t, 53544961713Sgirish boolean_t); 53644961713Sgirish npi_status_t npi_xmac_zap_tx_counters(npi_handle_t, uint8_t); 53744961713Sgirish npi_status_t npi_xmac_zap_rx_counters(npi_handle_t, uint8_t); 53844961713Sgirish 53944961713Sgirish /* bmac functions */ 54044961713Sgirish npi_status_t npi_bmac_reset(npi_handle_t, uint8_t, 54144961713Sgirish npi_mac_reset_t mode); 54244961713Sgirish npi_status_t npi_bmac_tx_config(npi_handle_t, config_op_t, 54344961713Sgirish uint8_t, bmac_tx_config_t); 54444961713Sgirish npi_status_t npi_bmac_rx_config(npi_handle_t, config_op_t, 54544961713Sgirish uint8_t, bmac_rx_config_t); 54644961713Sgirish npi_status_t npi_bmac_rx_iconfig(npi_handle_t, config_op_t, 54744961713Sgirish uint8_t, bmac_rx_iconfig_t); 54844961713Sgirish npi_status_t npi_bmac_xif_config(npi_handle_t, config_op_t, 54944961713Sgirish uint8_t, bmac_xif_config_t); 55044961713Sgirish npi_status_t npi_bmac_tx_iconfig(npi_handle_t, config_op_t, 55144961713Sgirish uint8_t, bmac_tx_iconfig_t); 55244961713Sgirish npi_status_t npi_bmac_ctl_iconfig(npi_handle_t, config_op_t, 55344961713Sgirish uint8_t, bmac_ctl_iconfig_t); 55444961713Sgirish npi_status_t npi_bmac_tx_get_istatus(npi_handle_t, uint8_t, 55544961713Sgirish bmac_tx_iconfig_t *); 55644961713Sgirish npi_status_t npi_bmac_rx_get_istatus(npi_handle_t, uint8_t, 55744961713Sgirish bmac_rx_iconfig_t *); 55844961713Sgirish npi_status_t npi_bmac_ctl_get_istatus(npi_handle_t, uint8_t, 55944961713Sgirish bmac_ctl_iconfig_t *); 56044961713Sgirish npi_status_t npi_bmac_send_pause(npi_handle_t, uint8_t, 56144961713Sgirish uint16_t); 56244961713Sgirish npi_status_t npi_mac_dump_regs(npi_handle_t, uint8_t); 56344961713Sgirish 56444961713Sgirish /* MIF common functions */ 56544961713Sgirish void npi_mac_mif_set_indirect_mode(npi_handle_t, boolean_t); 566d81011f0Ssbehera void npi_mac_mif_set_atca_mode(npi_handle_t, boolean_t); 56744961713Sgirish 56844961713Sgirish #ifdef __cplusplus 56944961713Sgirish } 57044961713Sgirish #endif 57144961713Sgirish 57244961713Sgirish #endif /* _NPI_MAC_H */ 573