1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <npi_mac.h> 29 30 #define MIF_DELAY 500 31 32 #define MAX_FRAME_SZ1 0x5EE 33 #define MAX_FRAME_SZ2 0x5F6 34 #define MAX_FRAME_SZ3 0x7D6 35 #define MAX_FRAME_SZ4 0x232E 36 #define MAX_FRAME_SZ5 0x2406 37 38 #define XMAC_WAIT_REG(handle, portn, reg, val) {\ 39 uint32_t cnt = MAX_PIO_RETRIES;\ 40 do {\ 41 NXGE_DELAY(MAC_RESET_WAIT);\ 42 XMAC_REG_RD(handle, portn, reg, &val);\ 43 cnt--;\ 44 } while (((val & 0x3) != 0) && (cnt > 0));\ 45 } 46 47 #define BMAC_WAIT_REG(handle, portn, reg, val) {\ 48 uint32_t cnt = MAX_PIO_RETRIES;\ 49 do {\ 50 NXGE_DELAY(MAC_RESET_WAIT);\ 51 BMAC_REG_RD(handle, portn, reg, &val);\ 52 cnt--;\ 53 } while (((val & 0x3) != 0) && (cnt > 0));\ 54 } 55 56 #define MIF_WAIT_REG(handle, m_frame, t_delay, interval, max_delay) { \ 57 do { \ 58 NXGE_DELAY(interval); \ 59 MIF_REG_RD(handle, MIF_OUTPUT_FRAME_REG, &m_frame.value); \ 60 t_delay++; \ 61 } while ((m_frame.bits.w0.ta_lsb == 0) && t_delay < max_delay); \ 62 } 63 64 uint64_t xmac_offset[] = { 65 XTXMAC_SW_RST_REG, 66 XRXMAC_SW_RST_REG, 67 XTXMAC_STATUS_REG, 68 XRXMAC_STATUS_REG, 69 XMAC_CTRL_STAT_REG, 70 XTXMAC_STAT_MSK_REG, 71 XRXMAC_STAT_MSK_REG, 72 XMAC_C_S_MSK_REG, 73 XMAC_CONFIG_REG, 74 XMAC_IPG_REG, 75 XMAC_MIN_REG, 76 XMAC_MAX_REG, 77 XMAC_ADDR0_REG, 78 XMAC_ADDR1_REG, 79 XMAC_ADDR2_REG, 80 XRXMAC_BT_CNT_REG, 81 XRXMAC_BC_FRM_CNT_REG, 82 XRXMAC_MC_FRM_CNT_REG, 83 XRXMAC_FRAG_CNT_REG, 84 XRXMAC_HIST_CNT1_REG, 85 XRXMAC_HIST_CNT2_REG, 86 XRXMAC_HIST_CNT3_REG, 87 XRXMAC_HIST_CNT4_REG, 88 XRXMAC_HIST_CNT5_REG, 89 XRXMAC_HIST_CNT6_REG, 90 XRXMAC_MPSZER_CNT_REG, 91 XRXMAC_CRC_ER_CNT_REG, 92 XRXMAC_CD_VIO_CNT_REG, 93 XRXMAC_AL_ER_CNT_REG, 94 XTXMAC_FRM_CNT_REG, 95 XTXMAC_BYTE_CNT_REG, 96 XMAC_LINK_FLT_CNT_REG, 97 XRXMAC_HIST_CNT7_REG, 98 XMAC_SM_REG, 99 XMAC_INTERN1_REG, 100 XMAC_ADDR_CMPEN_REG, 101 XMAC_ADDR3_REG, 102 XMAC_ADDR4_REG, 103 XMAC_ADDR5_REG, 104 XMAC_ADDR6_REG, 105 XMAC_ADDR7_REG, 106 XMAC_ADDR8_REG, 107 XMAC_ADDR9_REG, 108 XMAC_ADDR10_REG, 109 XMAC_ADDR11_REG, 110 XMAC_ADDR12_REG, 111 XMAC_ADDR13_REG, 112 XMAC_ADDR14_REG, 113 XMAC_ADDR15_REG, 114 XMAC_ADDR16_REG, 115 XMAC_ADDR17_REG, 116 XMAC_ADDR18_REG, 117 XMAC_ADDR19_REG, 118 XMAC_ADDR20_REG, 119 XMAC_ADDR21_REG, 120 XMAC_ADDR22_REG, 121 XMAC_ADDR23_REG, 122 XMAC_ADDR24_REG, 123 XMAC_ADDR25_REG, 124 XMAC_ADDR26_REG, 125 XMAC_ADDR27_REG, 126 XMAC_ADDR28_REG, 127 XMAC_ADDR29_REG, 128 XMAC_ADDR30_REG, 129 XMAC_ADDR31_REG, 130 XMAC_ADDR32_REG, 131 XMAC_ADDR33_REG, 132 XMAC_ADDR34_REG, 133 XMAC_ADDR35_REG, 134 XMAC_ADDR36_REG, 135 XMAC_ADDR37_REG, 136 XMAC_ADDR38_REG, 137 XMAC_ADDR39_REG, 138 XMAC_ADDR40_REG, 139 XMAC_ADDR41_REG, 140 XMAC_ADDR42_REG, 141 XMAC_ADDR43_REG, 142 XMAC_ADDR44_REG, 143 XMAC_ADDR45_REG, 144 XMAC_ADDR46_REG, 145 XMAC_ADDR47_REG, 146 XMAC_ADDR48_REG, 147 XMAC_ADDR49_REG, 148 XMAC_ADDR50_REG, 149 XMAC_ADDR_FILT0_REG, 150 XMAC_ADDR_FILT1_REG, 151 XMAC_ADDR_FILT2_REG, 152 XMAC_ADDR_FILT12_MASK_REG, 153 XMAC_ADDR_FILT0_MASK_REG, 154 XMAC_HASH_TBL0_REG, 155 XMAC_HASH_TBL1_REG, 156 XMAC_HASH_TBL2_REG, 157 XMAC_HASH_TBL3_REG, 158 XMAC_HASH_TBL4_REG, 159 XMAC_HASH_TBL5_REG, 160 XMAC_HASH_TBL6_REG, 161 XMAC_HASH_TBL7_REG, 162 XMAC_HASH_TBL8_REG, 163 XMAC_HASH_TBL9_REG, 164 XMAC_HASH_TBL10_REG, 165 XMAC_HASH_TBL11_REG, 166 XMAC_HASH_TBL12_REG, 167 XMAC_HASH_TBL13_REG, 168 XMAC_HASH_TBL14_REG, 169 XMAC_HASH_TBL15_REG, 170 XMAC_HOST_INF0_REG, 171 XMAC_HOST_INF1_REG, 172 XMAC_HOST_INF2_REG, 173 XMAC_HOST_INF3_REG, 174 XMAC_HOST_INF4_REG, 175 XMAC_HOST_INF5_REG, 176 XMAC_HOST_INF6_REG, 177 XMAC_HOST_INF7_REG, 178 XMAC_HOST_INF8_REG, 179 XMAC_HOST_INF9_REG, 180 XMAC_HOST_INF10_REG, 181 XMAC_HOST_INF11_REG, 182 XMAC_HOST_INF12_REG, 183 XMAC_HOST_INF13_REG, 184 XMAC_HOST_INF14_REG, 185 XMAC_HOST_INF15_REG, 186 XMAC_HOST_INF16_REG, 187 XMAC_HOST_INF17_REG, 188 XMAC_HOST_INF18_REG, 189 XMAC_HOST_INF19_REG, 190 XMAC_PA_DATA0_REG, 191 XMAC_PA_DATA1_REG, 192 XMAC_DEBUG_SEL_REG, 193 XMAC_TRAINING_VECT_REG, 194 }; 195 196 const char *xmac_name[] = { 197 "XTXMAC_SW_RST_REG", 198 "XRXMAC_SW_RST_REG", 199 "XTXMAC_STATUS_REG", 200 "XRXMAC_STATUS_REG", 201 "XMAC_CTRL_STAT_REG", 202 "XTXMAC_STAT_MSK_REG", 203 "XRXMAC_STAT_MSK_REG", 204 "XMAC_C_S_MSK_REG", 205 "XMAC_CONFIG_REG", 206 "XMAC_IPG_REG", 207 "XMAC_MIN_REG", 208 "XMAC_MAX_REG", 209 "XMAC_ADDR0_REG", 210 "XMAC_ADDR1_REG", 211 "XMAC_ADDR2_REG", 212 "XRXMAC_BT_CNT_REG", 213 "XRXMAC_BC_FRM_CNT_REG", 214 "XRXMAC_MC_FRM_CNT_REG", 215 "XRXMAC_FRAG_CNT_REG", 216 "XRXMAC_HIST_CNT1_REG", 217 "XRXMAC_HIST_CNT2_REG", 218 "XRXMAC_HIST_CNT3_REG", 219 "XRXMAC_HIST_CNT4_REG", 220 "XRXMAC_HIST_CNT5_REG", 221 "XRXMAC_HIST_CNT6_REG", 222 "XRXMAC_MPSZER_CNT_REG", 223 "XRXMAC_CRC_ER_CNT_REG", 224 "XRXMAC_CD_VIO_CNT_REG", 225 "XRXMAC_AL_ER_CNT_REG", 226 "XTXMAC_FRM_CNT_REG", 227 "XTXMAC_BYTE_CNT_REG", 228 "XMAC_LINK_FLT_CNT_REG", 229 "XRXMAC_HIST_CNT7_REG", 230 "XMAC_SM_REG", 231 "XMAC_INTERN1_REG", 232 "XMAC_ADDR_CMPEN_REG", 233 "XMAC_ADDR3_REG", 234 "XMAC_ADDR4_REG", 235 "XMAC_ADDR5_REG", 236 "XMAC_ADDR6_REG", 237 "XMAC_ADDR7_REG", 238 "XMAC_ADDR8_REG", 239 "XMAC_ADDR9_REG", 240 "XMAC_ADDR10_REG", 241 "XMAC_ADDR11_REG", 242 "XMAC_ADDR12_REG", 243 "XMAC_ADDR13_REG", 244 "XMAC_ADDR14_REG", 245 "XMAC_ADDR15_REG", 246 "XMAC_ADDR16_REG", 247 "XMAC_ADDR17_REG", 248 "XMAC_ADDR18_REG", 249 "XMAC_ADDR19_REG", 250 "XMAC_ADDR20_REG", 251 "XMAC_ADDR21_REG", 252 "XMAC_ADDR22_REG", 253 "XMAC_ADDR23_REG", 254 "XMAC_ADDR24_REG", 255 "XMAC_ADDR25_REG", 256 "XMAC_ADDR26_REG", 257 "XMAC_ADDR27_REG", 258 "XMAC_ADDR28_REG", 259 "XMAC_ADDR29_REG", 260 "XMAC_ADDR30_REG", 261 "XMAC_ADDR31_REG", 262 "XMAC_ADDR32_REG", 263 "XMAC_ADDR33_REG", 264 "XMAC_ADDR34_REG", 265 "XMAC_ADDR35_REG", 266 "XMAC_ADDR36_REG", 267 "XMAC_ADDR37_REG", 268 "XMAC_ADDR38_REG", 269 "XMAC_ADDR39_REG", 270 "XMAC_ADDR40_REG", 271 "XMAC_ADDR41_REG", 272 "XMAC_ADDR42_REG", 273 "XMAC_ADDR43_REG", 274 "XMAC_ADDR44_REG", 275 "XMAC_ADDR45_REG", 276 "XMAC_ADDR46_REG", 277 "XMAC_ADDR47_REG", 278 "XMAC_ADDR48_REG", 279 "XMAC_ADDR49_REG", 280 "XMAC_ADDR50_RE", 281 "XMAC_ADDR_FILT0_REG", 282 "XMAC_ADDR_FILT1_REG", 283 "XMAC_ADDR_FILT2_REG", 284 "XMAC_ADDR_FILT12_MASK_REG", 285 "XMAC_ADDR_FILT0_MASK_REG", 286 "XMAC_HASH_TBL0_REG", 287 "XMAC_HASH_TBL1_REG", 288 "XMAC_HASH_TBL2_REG", 289 "XMAC_HASH_TBL3_REG", 290 "XMAC_HASH_TBL4_REG", 291 "XMAC_HASH_TBL5_REG", 292 "XMAC_HASH_TBL6_REG", 293 "XMAC_HASH_TBL7_REG", 294 "XMAC_HASH_TBL8_REG", 295 "XMAC_HASH_TBL9_REG", 296 "XMAC_HASH_TBL10_REG", 297 "XMAC_HASH_TBL11_REG", 298 "XMAC_HASH_TBL12_REG", 299 "XMAC_HASH_TBL13_REG", 300 "XMAC_HASH_TBL14_REG", 301 "XMAC_HASH_TBL15_REG", 302 "XMAC_HOST_INF0_REG", 303 "XMAC_HOST_INF1_REG", 304 "XMAC_HOST_INF2_REG", 305 "XMAC_HOST_INF3_REG", 306 "XMAC_HOST_INF4_REG", 307 "XMAC_HOST_INF5_REG", 308 "XMAC_HOST_INF6_REG", 309 "XMAC_HOST_INF7_REG", 310 "XMAC_HOST_INF8_REG", 311 "XMAC_HOST_INF9_REG", 312 "XMAC_HOST_INF10_REG", 313 "XMAC_HOST_INF11_REG", 314 "XMAC_HOST_INF12_REG", 315 "XMAC_HOST_INF13_REG", 316 "XMAC_HOST_INF14_REG", 317 "XMAC_HOST_INF15_REG", 318 "XMAC_HOST_INF16_REG", 319 "XMAC_HOST_INF17_REG", 320 "XMAC_HOST_INF18_REG", 321 "XMAC_HOST_INF19_REG", 322 "XMAC_PA_DATA0_REG", 323 "XMAC_PA_DATA1_REG", 324 "XMAC_DEBUG_SEL_REG", 325 "XMAC_TRAINING_VECT_REG", 326 }; 327 328 uint64_t bmac_offset[] = { 329 BTXMAC_SW_RST_REG, 330 BRXMAC_SW_RST_REG, 331 MAC_SEND_PAUSE_REG, 332 BTXMAC_STATUS_REG, 333 BRXMAC_STATUS_REG, 334 BMAC_CTRL_STAT_REG, 335 BTXMAC_STAT_MSK_REG, 336 BRXMAC_STAT_MSK_REG, 337 BMAC_C_S_MSK_REG, 338 TXMAC_CONFIG_REG, 339 RXMAC_CONFIG_REG, 340 MAC_CTRL_CONFIG_REG, 341 MAC_XIF_CONFIG_REG, 342 BMAC_MIN_REG, 343 BMAC_MAX_REG, 344 MAC_PA_SIZE_REG, 345 MAC_CTRL_TYPE_REG, 346 BMAC_ADDR0_REG, 347 BMAC_ADDR1_REG, 348 BMAC_ADDR2_REG, 349 BMAC_ADDR3_REG, 350 BMAC_ADDR4_REG, 351 BMAC_ADDR5_REG, 352 BMAC_ADDR6_REG, 353 BMAC_ADDR7_REG, 354 BMAC_ADDR8_REG, 355 BMAC_ADDR9_REG, 356 BMAC_ADDR10_REG, 357 BMAC_ADDR11_REG, 358 BMAC_ADDR12_REG, 359 BMAC_ADDR13_REG, 360 BMAC_ADDR14_REG, 361 BMAC_ADDR15_REG, 362 BMAC_ADDR16_REG, 363 BMAC_ADDR17_REG, 364 BMAC_ADDR18_REG, 365 BMAC_ADDR19_REG, 366 BMAC_ADDR20_REG, 367 BMAC_ADDR21_REG, 368 BMAC_ADDR22_REG, 369 BMAC_ADDR23_REG, 370 MAC_FC_ADDR0_REG, 371 MAC_FC_ADDR1_REG, 372 MAC_FC_ADDR2_REG, 373 MAC_ADDR_FILT0_REG, 374 MAC_ADDR_FILT1_REG, 375 MAC_ADDR_FILT2_REG, 376 MAC_ADDR_FILT12_MASK_REG, 377 MAC_ADDR_FILT00_MASK_REG, 378 MAC_HASH_TBL0_REG, 379 MAC_HASH_TBL1_REG, 380 MAC_HASH_TBL2_REG, 381 MAC_HASH_TBL3_REG, 382 MAC_HASH_TBL4_REG, 383 MAC_HASH_TBL5_REG, 384 MAC_HASH_TBL6_REG, 385 MAC_HASH_TBL7_REG, 386 MAC_HASH_TBL8_REG, 387 MAC_HASH_TBL9_REG, 388 MAC_HASH_TBL10_REG, 389 MAC_HASH_TBL11_REG, 390 MAC_HASH_TBL12_REG, 391 MAC_HASH_TBL13_REG, 392 MAC_HASH_TBL14_REG, 393 MAC_HASH_TBL15_REG, 394 RXMAC_FRM_CNT_REG, 395 MAC_LEN_ER_CNT_REG, 396 BMAC_AL_ER_CNT_REG, 397 BMAC_CRC_ER_CNT_REG, 398 BMAC_CD_VIO_CNT_REG, 399 BMAC_SM_REG, 400 BMAC_ALTAD_CMPEN_REG, 401 BMAC_HOST_INF0_REG, 402 BMAC_HOST_INF1_REG, 403 BMAC_HOST_INF2_REG, 404 BMAC_HOST_INF3_REG, 405 BMAC_HOST_INF4_REG, 406 BMAC_HOST_INF5_REG, 407 BMAC_HOST_INF6_REG, 408 BMAC_HOST_INF7_REG, 409 BMAC_HOST_INF8_REG, 410 BTXMAC_BYTE_CNT_REG, 411 BTXMAC_FRM_CNT_REG, 412 BRXMAC_BYTE_CNT_REG, 413 }; 414 415 const char *bmac_name[] = { 416 "BTXMAC_SW_RST_REG", 417 "BRXMAC_SW_RST_REG", 418 "MAC_SEND_PAUSE_REG", 419 "BTXMAC_STATUS_REG", 420 "BRXMAC_STATUS_REG", 421 "BMAC_CTRL_STAT_REG", 422 "BTXMAC_STAT_MSK_REG", 423 "BRXMAC_STAT_MSK_REG", 424 "BMAC_C_S_MSK_REG", 425 "TXMAC_CONFIG_REG", 426 "RXMAC_CONFIG_REG", 427 "MAC_CTRL_CONFIG_REG", 428 "MAC_XIF_CONFIG_REG", 429 "BMAC_MIN_REG", 430 "BMAC_MAX_REG", 431 "MAC_PA_SIZE_REG", 432 "MAC_CTRL_TYPE_REG", 433 "BMAC_ADDR0_REG", 434 "BMAC_ADDR1_REG", 435 "BMAC_ADDR2_REG", 436 "BMAC_ADDR3_REG", 437 "BMAC_ADDR4_REG", 438 "BMAC_ADDR5_REG", 439 "BMAC_ADDR6_REG", 440 "BMAC_ADDR7_REG", 441 "BMAC_ADDR8_REG", 442 "BMAC_ADDR9_REG", 443 "BMAC_ADDR10_REG", 444 "BMAC_ADDR11_REG", 445 "BMAC_ADDR12_REG", 446 "BMAC_ADDR13_REG", 447 "BMAC_ADDR14_REG", 448 "BMAC_ADDR15_REG", 449 "BMAC_ADDR16_REG", 450 "BMAC_ADDR17_REG", 451 "BMAC_ADDR18_REG", 452 "BMAC_ADDR19_REG", 453 "BMAC_ADDR20_REG", 454 "BMAC_ADDR21_REG", 455 "BMAC_ADDR22_REG", 456 "BMAC_ADDR23_REG", 457 "MAC_FC_ADDR0_REG", 458 "MAC_FC_ADDR1_REG", 459 "MAC_FC_ADDR2_REG", 460 "MAC_ADDR_FILT0_REG", 461 "MAC_ADDR_FILT1_REG", 462 "MAC_ADDR_FILT2_REG", 463 "MAC_ADDR_FILT12_MASK_REG", 464 "MAC_ADDR_FILT00_MASK_REG", 465 "MAC_HASH_TBL0_REG", 466 "MAC_HASH_TBL1_REG", 467 "MAC_HASH_TBL2_REG", 468 "MAC_HASH_TBL3_REG", 469 "MAC_HASH_TBL4_REG", 470 "MAC_HASH_TBL5_REG", 471 "MAC_HASH_TBL6_REG", 472 "MAC_HASH_TBL7_REG", 473 "MAC_HASH_TBL8_REG", 474 "MAC_HASH_TBL9_REG", 475 "MAC_HASH_TBL10_REG", 476 "MAC_HASH_TBL11_REG", 477 "MAC_HASH_TBL12_REG", 478 "MAC_HASH_TBL13_REG", 479 "MAC_HASH_TBL14_REG", 480 "MAC_HASH_TBL15_REG", 481 "RXMAC_FRM_CNT_REG", 482 "MAC_LEN_ER_CNT_REG", 483 "BMAC_AL_ER_CNT_REG", 484 "BMAC_CRC_ER_CNT_REG", 485 "BMAC_CD_VIO_CNT_REG", 486 "BMAC_SM_REG", 487 "BMAC_ALTAD_CMPEN_REG", 488 "BMAC_HOST_INF0_REG", 489 "BMAC_HOST_INF1_REG", 490 "BMAC_HOST_INF2_REG", 491 "BMAC_HOST_INF3_REG", 492 "BMAC_HOST_INF4_REG", 493 "BMAC_HOST_INF5_REG", 494 "BMAC_HOST_INF6_REG", 495 "BMAC_HOST_INF7_REG", 496 "BMAC_HOST_INF8_REG", 497 "BTXMAC_BYTE_CNT_REG", 498 "BTXMAC_FRM_CNT_REG", 499 "BRXMAC_BYTE_CNT_REG", 500 }; 501 502 npi_status_t 503 npi_mac_dump_regs(npi_handle_t handle, uint8_t port) 504 { 505 506 uint64_t value; 507 int num_regs, i; 508 509 ASSERT(IS_PORT_NUM_VALID(port)); 510 511 switch (port) { 512 case 0: 513 case 1: 514 num_regs = sizeof (xmac_offset) / sizeof (uint64_t); 515 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 516 "\nXMAC Register Dump for port %d\n", 517 port)); 518 for (i = 0; i < num_regs; i++) { 519 #if defined(__i386) 520 XMAC_REG_RD(handle, port, (uint32_t)xmac_offset[i], 521 &value); 522 #else 523 XMAC_REG_RD(handle, port, xmac_offset[i], &value); 524 #endif 525 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 526 "%08llx %s\t %08llx \n", 527 (XMAC_REG_ADDR((port), (xmac_offset[i]))), 528 xmac_name[i], value)); 529 } 530 531 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 532 "\n XMAC Register Dump for port %d done\n", 533 port)); 534 break; 535 536 case 2: 537 case 3: 538 num_regs = sizeof (bmac_offset) / sizeof (uint64_t); 539 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 540 "\nBMAC Register Dump for port %d\n", 541 port)); 542 for (i = 0; i < num_regs; i++) { 543 #if defined(__i386) 544 BMAC_REG_RD(handle, port, (uint32_t)bmac_offset[i], 545 &value); 546 #else 547 BMAC_REG_RD(handle, port, bmac_offset[i], &value); 548 #endif 549 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 550 "%08llx %s\t %08llx \n", 551 (BMAC_REG_ADDR((port), (bmac_offset[i]))), 552 bmac_name[i], value)); 553 } 554 555 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 556 "\n BMAC Register Dump for port %d done\n", 557 port)); 558 break; 559 } 560 561 return (NPI_SUCCESS); 562 } 563 564 npi_status_t 565 npi_mac_pcs_link_intr_enable(npi_handle_t handle, uint8_t portn) 566 { 567 pcs_cfg_t pcs_cfg; 568 569 ASSERT(IS_PORT_NUM_VALID(portn)); 570 571 PCS_REG_RD(handle, portn, PCS_CONFIG_REG, &pcs_cfg.value); 572 pcs_cfg.bits.w0.mask = 0; 573 PCS_REG_WR(handle, portn, PCS_CONFIG_REG, pcs_cfg.value); 574 575 return (NPI_SUCCESS); 576 } 577 578 npi_status_t 579 npi_mac_pcs_link_intr_disable(npi_handle_t handle, uint8_t portn) 580 { 581 pcs_cfg_t pcs_cfg; 582 583 ASSERT(IS_PORT_NUM_VALID(portn)); 584 585 PCS_REG_RD(handle, portn, PCS_CONFIG_REG, &pcs_cfg.val.lsw); 586 pcs_cfg.bits.w0.mask = 1; 587 PCS_REG_WR(handle, portn, PCS_CONFIG_REG, pcs_cfg.val.lsw); 588 589 return (NPI_SUCCESS); 590 } 591 592 npi_status_t 593 npi_xmac_xpcs_link_intr_enable(npi_handle_t handle, uint8_t portn) 594 { 595 xpcs_stat1_t xpcs_mask1; 596 597 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 598 599 XPCS_REG_RD(handle, portn, XPCS_MASK_1_REG, &xpcs_mask1.val.lsw); 600 xpcs_mask1.bits.w0.csr_rx_link_stat = 1; 601 XPCS_REG_WR(handle, portn, XPCS_MASK_1_REG, xpcs_mask1.val.lsw); 602 603 return (NPI_SUCCESS); 604 } 605 606 npi_status_t 607 npi_xmac_xpcs_link_intr_disable(npi_handle_t handle, uint8_t portn) 608 { 609 xpcs_stat1_t xpcs_mask1; 610 611 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 612 613 XPCS_REG_RD(handle, portn, XPCS_MASK_1_REG, &xpcs_mask1.val.lsw); 614 xpcs_mask1.bits.w0.csr_rx_link_stat = 0; 615 XPCS_REG_WR(handle, portn, XPCS_MASK_1_REG, xpcs_mask1.val.lsw); 616 617 return (NPI_SUCCESS); 618 } 619 620 npi_status_t 621 npi_mac_mif_link_intr_disable(npi_handle_t handle, uint8_t portn) 622 { 623 mif_cfg_t mif_cfg; 624 625 ASSERT(IS_PORT_NUM_VALID(portn)); 626 627 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.val.lsw); 628 629 mif_cfg.bits.w0.phy_addr = portn; 630 mif_cfg.bits.w0.poll_en = 0; 631 632 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.val.lsw); 633 634 NXGE_DELAY(20); 635 636 return (NPI_SUCCESS); 637 } 638 639 npi_status_t 640 npi_mac_hashtab_entry(npi_handle_t handle, io_op_t op, uint8_t portn, 641 uint8_t entryn, uint16_t *data) 642 { 643 uint64_t val; 644 645 ASSERT((op == OP_GET) || (op == OP_SET)); 646 ASSERT(IS_PORT_NUM_VALID(portn)); 647 648 ASSERT(entryn < MAC_MAX_HASH_ENTRY); 649 if (entryn >= MAC_MAX_HASH_ENTRY) { 650 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 651 " npi_mac_hashtab_entry" 652 " Invalid Input: entryn <0x%x>", 653 entryn)); 654 return (NPI_FAILURE | NPI_MAC_HASHTAB_ENTRY_INVALID(portn)); 655 } 656 657 if (op == OP_SET) { 658 val = *data; 659 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 660 XMAC_REG_WR(handle, portn, 661 XMAC_HASH_TBLN_REG_ADDR(entryn), val); 662 } else { 663 BMAC_REG_WR(handle, portn, 664 BMAC_HASH_TBLN_REG_ADDR(entryn), val); 665 } 666 } else { 667 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 668 XMAC_REG_RD(handle, portn, 669 XMAC_HASH_TBLN_REG_ADDR(entryn), &val); 670 } else { 671 BMAC_REG_RD(handle, portn, 672 BMAC_HASH_TBLN_REG_ADDR(entryn), &val); 673 } 674 *data = val & 0xFFFF; 675 } 676 677 return (NPI_SUCCESS); 678 } 679 680 npi_status_t 681 npi_mac_hostinfo_entry(npi_handle_t handle, io_op_t op, uint8_t portn, 682 uint8_t entryn, hostinfo_t *hostinfo) 683 { 684 ASSERT((op == OP_GET) || (op == OP_SET)); 685 ASSERT(IS_PORT_NUM_VALID(portn)); 686 687 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 688 ASSERT(entryn < XMAC_MAX_HOST_INFO_ENTRY); 689 if (entryn >= XMAC_MAX_HOST_INFO_ENTRY) { 690 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 691 " npi_mac_hostinfo_entry" 692 " Invalid Input: entryn <0x%x>", 693 entryn)); 694 return (NPI_FAILURE | 695 NPI_MAC_HOSTINFO_ENTRY_INVALID(portn)); 696 } 697 } else { 698 ASSERT(entryn < BMAC_MAX_HOST_INFO_ENTRY); 699 if (entryn >= BMAC_MAX_HOST_INFO_ENTRY) { 700 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 701 " npi_mac_hostinfo_entry" 702 " Invalid Input: entryn <0x%x>", 703 entryn)); 704 return (NPI_FAILURE | 705 NPI_MAC_HOSTINFO_ENTRY_INVALID(portn)); 706 } 707 } 708 709 if (op == OP_SET) { 710 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 711 XMAC_REG_WR(handle, portn, 712 XMAC_HOST_INFN_REG_ADDR(entryn), 713 hostinfo->value); 714 } else { 715 BMAC_REG_WR(handle, portn, 716 BMAC_HOST_INFN_REG_ADDR(entryn), 717 hostinfo->value); 718 } 719 } else { 720 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 721 XMAC_REG_RD(handle, portn, 722 XMAC_HOST_INFN_REG_ADDR(entryn), 723 &hostinfo->value); 724 } else { 725 BMAC_REG_RD(handle, portn, 726 BMAC_HOST_INFN_REG_ADDR(entryn), 727 &hostinfo->value); 728 } 729 } 730 731 return (NPI_SUCCESS); 732 } 733 734 npi_status_t 735 npi_mac_altaddr_enable(npi_handle_t handle, uint8_t portn, uint8_t addrn) 736 { 737 uint64_t val; 738 739 ASSERT(IS_PORT_NUM_VALID(portn)); 740 741 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 742 ASSERT(addrn <= XMAC_MAX_ALT_ADDR_ENTRY); 743 if (addrn > XMAC_MAX_ALT_ADDR_ENTRY) { 744 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 745 " npi_mac_altaddr_enable" 746 " Invalid Input: addrn <0x%x>", 747 addrn)); 748 return (NPI_FAILURE | 749 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 750 } 751 XMAC_REG_RD(handle, portn, XMAC_ADDR_CMPEN_REG, &val); 752 val |= (1 << addrn); 753 XMAC_REG_WR(handle, portn, XMAC_ADDR_CMPEN_REG, val); 754 } else { 755 ASSERT(addrn <= BMAC_MAX_ALT_ADDR_ENTRY); 756 if (addrn > BMAC_MAX_ALT_ADDR_ENTRY) { 757 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 758 " npi_mac_altaddr_enable" 759 " Invalid Input: addrn <0x%x>", 760 addrn)); 761 return (NPI_FAILURE | 762 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 763 } 764 BMAC_REG_RD(handle, portn, BMAC_ALTAD_CMPEN_REG, &val); 765 val |= (1 << addrn); 766 BMAC_REG_WR(handle, portn, BMAC_ALTAD_CMPEN_REG, val); 767 } 768 769 return (NPI_SUCCESS); 770 } 771 772 /* 773 * While all bits of XMAC_ADDR_CMPEN_REG are for alternate MAC addresses, 774 * bit0 of BMAC_ALTAD_CMPEN_REG is for unique MAC address. 775 */ 776 npi_status_t 777 npi_mac_altaddr_disable(npi_handle_t handle, uint8_t portn, uint8_t addrn) 778 { 779 uint64_t val; 780 781 ASSERT(IS_PORT_NUM_VALID(portn)); 782 783 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 784 ASSERT(addrn <= XMAC_MAX_ALT_ADDR_ENTRY); 785 if (addrn > XMAC_MAX_ALT_ADDR_ENTRY) { 786 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 787 " npi_mac_altaddr_disable" 788 " Invalid Input: addrn <0x%x>", 789 addrn)); 790 return (NPI_FAILURE | 791 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 792 } 793 XMAC_REG_RD(handle, portn, XMAC_ADDR_CMPEN_REG, &val); 794 val &= ~(1 << addrn); 795 XMAC_REG_WR(handle, portn, XMAC_ADDR_CMPEN_REG, val); 796 } else { 797 ASSERT(addrn <= BMAC_MAX_ALT_ADDR_ENTRY); 798 if (addrn > BMAC_MAX_ALT_ADDR_ENTRY) { 799 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 800 " npi_mac_altaddr_disable" 801 " Invalid Input: addrn <0x%x>", 802 addrn)); 803 return (NPI_FAILURE | 804 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 805 } 806 BMAC_REG_RD(handle, portn, BMAC_ALTAD_CMPEN_REG, &val); 807 val &= ~(1 << addrn); 808 BMAC_REG_WR(handle, portn, BMAC_ALTAD_CMPEN_REG, val); 809 } 810 811 return (NPI_SUCCESS); 812 } 813 814 npi_status_t 815 npi_mac_altaddr_entry(npi_handle_t handle, io_op_t op, uint8_t portn, 816 uint8_t entryn, npi_mac_addr_t *data) 817 { 818 uint64_t val0, val1, val2; 819 820 ASSERT(IS_PORT_NUM_VALID(portn)); 821 ASSERT((op == OP_GET) || (op == OP_SET)); 822 823 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 824 ASSERT(entryn <= XMAC_MAX_ALT_ADDR_ENTRY); 825 if (entryn > XMAC_MAX_ALT_ADDR_ENTRY) { 826 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 827 " npi_mac_altaddr_entry" 828 " Invalid Input: entryn <0x%x>", 829 entryn)); 830 return (NPI_FAILURE | 831 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 832 } 833 if (op == OP_SET) { 834 val0 = data->w0; 835 val1 = data->w1; 836 val2 = data->w2; 837 XMAC_REG_WR(handle, portn, 838 XMAC_ALT_ADDR0N_REG_ADDR(entryn), val0); 839 XMAC_REG_WR(handle, portn, 840 XMAC_ALT_ADDR1N_REG_ADDR(entryn), val1); 841 XMAC_REG_WR(handle, portn, 842 XMAC_ALT_ADDR2N_REG_ADDR(entryn), val2); 843 } else { 844 XMAC_REG_RD(handle, portn, 845 XMAC_ALT_ADDR0N_REG_ADDR(entryn), &val0); 846 XMAC_REG_RD(handle, portn, 847 XMAC_ALT_ADDR1N_REG_ADDR(entryn), &val1); 848 XMAC_REG_RD(handle, portn, 849 XMAC_ALT_ADDR2N_REG_ADDR(entryn), &val2); 850 data->w0 = val0 & 0xFFFF; 851 data->w1 = val1 & 0xFFFF; 852 data->w2 = val2 & 0xFFFF; 853 } 854 } else { 855 ASSERT(entryn <= BMAC_MAX_ALT_ADDR_ENTRY); 856 if (entryn > BMAC_MAX_ALT_ADDR_ENTRY) { 857 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 858 " npi_mac_altaddr_entry" 859 " Invalid Input: entryn <0x%x>", 860 entryn)); 861 return (NPI_FAILURE | 862 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 863 } 864 if (op == OP_SET) { 865 val0 = data->w0; 866 val1 = data->w1; 867 val2 = data->w2; 868 BMAC_REG_WR(handle, portn, 869 BMAC_ALT_ADDR0N_REG_ADDR(entryn), val0); 870 BMAC_REG_WR(handle, portn, 871 BMAC_ALT_ADDR1N_REG_ADDR(entryn), val1); 872 BMAC_REG_WR(handle, portn, 873 BMAC_ALT_ADDR2N_REG_ADDR(entryn), val2); 874 } else { 875 BMAC_REG_RD(handle, portn, 876 BMAC_ALT_ADDR0N_REG_ADDR(entryn), &val0); 877 BMAC_REG_RD(handle, portn, 878 BMAC_ALT_ADDR1N_REG_ADDR(entryn), &val1); 879 BMAC_REG_RD(handle, portn, 880 BMAC_ALT_ADDR2N_REG_ADDR(entryn), &val2); 881 data->w0 = val0 & 0xFFFF; 882 data->w1 = val1 & 0xFFFF; 883 data->w2 = val2 & 0xFFFF; 884 } 885 } 886 887 return (NPI_SUCCESS); 888 } 889 890 npi_status_t 891 npi_mac_port_attr(npi_handle_t handle, io_op_t op, uint8_t portn, 892 npi_attr_t *attrp) 893 { 894 uint64_t val = 0; 895 uint32_t attr; 896 897 ASSERT(IS_PORT_NUM_VALID(portn)); 898 ASSERT((op == OP_GET) || (op == OP_SET)); 899 900 switch (attrp->type) { 901 case MAC_PORT_MODE: 902 switch (portn) { 903 case XMAC_PORT_0: 904 case XMAC_PORT_1: 905 if (op == OP_SET) { 906 attr = attrp->idata[0]; 907 ASSERT((attr == MAC_MII_MODE) || \ 908 (attr == MAC_GMII_MODE) || \ 909 (attr == MAC_XGMII_MODE)); 910 if ((attr != MAC_MII_MODE) && 911 (attr != MAC_GMII_MODE) && 912 (attr != MAC_XGMII_MODE)) { 913 NPI_ERROR_MSG((handle.function, 914 NPI_ERR_CTL, 915 " npi_mac_port_attr" 916 " Invalid Input:" 917 " MAC_PORT_MODE <0x%x>", 918 attr)); 919 return (NPI_FAILURE | 920 NPI_MAC_PORT_ATTR_INVALID(portn)); 921 } 922 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, 923 &val); 924 val &= ~XMAC_XIF_MII_MODE_MASK; 925 switch (attr) { 926 case MAC_MII_MODE: 927 val |= (XMAC_XIF_MII_MODE << 928 XMAC_XIF_MII_MODE_SHIFT); 929 break; 930 case MAC_GMII_MODE: 931 val |= (XMAC_XIF_GMII_MODE << 932 XMAC_XIF_MII_MODE_SHIFT); 933 break; 934 case MAC_XGMII_MODE: 935 val |= (XMAC_XIF_XGMII_MODE << 936 XMAC_XIF_MII_MODE_SHIFT); 937 break; 938 default: 939 return (NPI_FAILURE | 940 NPI_MAC_PORT_ATTR_INVALID(portn)); 941 } 942 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, 943 val); 944 } else { 945 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, 946 &val); 947 val &= XMAC_XIF_MII_MODE_MASK; 948 attr = val >> XMAC_XIF_MII_MODE_SHIFT; 949 attrp->odata[0] = attr; 950 } 951 break; 952 case BMAC_PORT_0: 953 case BMAC_PORT_1: 954 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 955 " npi_mac_port_attr" 956 " Invalid Input:" 957 " MAC_PORT_MODE <0x%x>", 958 attrp->type)); 959 return (NPI_FAILURE | 960 NPI_MAC_PORT_ATTR_INVALID(portn)); 961 default: 962 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 963 } 964 break; 965 966 case MAC_PORT_FRAME_SIZE: { 967 uint32_t min_fsize; 968 uint32_t max_fsize; 969 970 switch (portn) { 971 case XMAC_PORT_0: 972 case XMAC_PORT_1: 973 if (op == OP_SET) { 974 min_fsize = attrp->idata[0]; 975 max_fsize = attrp->idata[1]; 976 ASSERT((min_fsize & \ 977 ~XMAC_MIN_TX_FRM_SZ_MASK) == 0); 978 if ((min_fsize & ~XMAC_MIN_TX_FRM_SZ_MASK) 979 != 0) { 980 NPI_ERROR_MSG((handle.function, 981 NPI_ERR_CTL, 982 " npi_mac_port_attr" 983 " MAC_PORT_FRAME_SIZE:" 984 " Invalid Input:" 985 " xmac_min_fsize <0x%x>", 986 min_fsize)); 987 return (NPI_FAILURE | 988 NPI_MAC_PORT_ATTR_INVALID(portn)); 989 } 990 ASSERT((max_fsize & \ 991 ~XMAC_MAX_FRM_SZ_MASK) == 0); 992 if ((max_fsize & ~XMAC_MAX_FRM_SZ_MASK) 993 != 0) { 994 NPI_ERROR_MSG((handle.function, 995 NPI_ERR_CTL, 996 " npi_mac_port_attr" 997 " MAC_PORT_FRAME_SIZE:" 998 " Invalid Input:" 999 " xmac_max_fsize <0x%x>", 1000 max_fsize)); 1001 return (NPI_FAILURE | 1002 NPI_MAC_PORT_ATTR_INVALID(portn)); 1003 } 1004 XMAC_REG_RD(handle, portn, XMAC_MIN_REG, &val); 1005 val &= ~(XMAC_MIN_TX_FRM_SZ_MASK | 1006 XMAC_MIN_RX_FRM_SZ_MASK); 1007 val |= (min_fsize << XMAC_MIN_TX_FRM_SZ_SHIFT); 1008 val |= (min_fsize << XMAC_MIN_RX_FRM_SZ_SHIFT); 1009 XMAC_REG_WR(handle, portn, XMAC_MIN_REG, val); 1010 XMAC_REG_WR(handle, portn, XMAC_MAX_REG, 1011 max_fsize); 1012 } else { 1013 XMAC_REG_RD(handle, portn, XMAC_MIN_REG, &val); 1014 min_fsize = (val & XMAC_MIN_TX_FRM_SZ_MASK) 1015 >> XMAC_MIN_TX_FRM_SZ_SHIFT; 1016 XMAC_REG_RD(handle, portn, XMAC_MAX_REG, &val); 1017 attrp->odata[0] = min_fsize; 1018 attrp->odata[1] = max_fsize; 1019 } 1020 break; 1021 case BMAC_PORT_0: 1022 case BMAC_PORT_1: 1023 if (op == OP_SET) { 1024 min_fsize = attrp->idata[0]; 1025 max_fsize = attrp->idata[1]; 1026 ASSERT((min_fsize & ~BMAC_MIN_FRAME_MASK) == 0); 1027 if ((min_fsize & ~BMAC_MIN_FRAME_MASK) 1028 != 0) { 1029 NPI_ERROR_MSG((handle.function, 1030 NPI_ERR_CTL, 1031 " npi_mac_port_attr" 1032 " MAC_FRAME_SIZE:" 1033 " Invalid Input:" 1034 " bmac_min_fsize <0x%x>", 1035 min_fsize)); 1036 return (NPI_FAILURE | 1037 NPI_MAC_PORT_ATTR_INVALID(portn)); 1038 } 1039 ASSERT((max_fsize & ~BMAC_MAX_FRAME_MASK) == 0); 1040 if ((max_fsize & ~BMAC_MAX_FRAME_MASK) 1041 != 0) { 1042 NPI_ERROR_MSG((handle.function, 1043 NPI_ERR_CTL, 1044 " npi_mac_port_attr" 1045 " MAC_FRAME_SIZE:" 1046 " Invalid Input:" 1047 " bmac_max_fsize <0x%x>", 1048 max_fsize)); 1049 return (NPI_FAILURE | 1050 NPI_MAC_PORT_ATTR_INVALID(portn)); 1051 } 1052 BMAC_REG_RD(handle, portn, BMAC_MAX_REG, &val); 1053 val &= ~BMAC_MAX_FRAME_MASK; 1054 if (max_fsize <= MAX_FRAME_SZ1) 1055 val |= MAX_FRAME_SZ1; 1056 else if ((max_fsize > MAX_FRAME_SZ1) && 1057 (max_fsize <= MAX_FRAME_SZ2)) 1058 val |= MAX_FRAME_SZ2; 1059 else if ((max_fsize > MAX_FRAME_SZ2) && 1060 (max_fsize <= MAX_FRAME_SZ3)) 1061 val |= MAX_FRAME_SZ3; 1062 else if ((max_fsize > MAX_FRAME_SZ3) && 1063 (max_fsize <= MAX_FRAME_SZ4)) 1064 val |= MAX_FRAME_SZ4; 1065 else if ((max_fsize > MAX_FRAME_SZ4) && 1066 (max_fsize <= MAX_FRAME_SZ5)) 1067 val |= MAX_FRAME_SZ5; 1068 BMAC_REG_WR(handle, portn, BMAC_MAX_REG, val); 1069 BMAC_REG_WR(handle, portn, BMAC_MIN_REG, 1070 min_fsize); 1071 } else { 1072 BMAC_REG_RD(handle, portn, BMAC_MIN_REG, &val); 1073 min_fsize = val & BMAC_MIN_FRAME_MASK; 1074 BMAC_REG_RD(handle, portn, BMAC_MAX_REG, &val); 1075 max_fsize = val & BMAC_MAX_FRAME_MASK; 1076 attrp->odata[0] = min_fsize; 1077 attrp->odata[1] = max_fsize; 1078 } 1079 break; 1080 default: 1081 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1082 } 1083 } break; 1084 1085 case BMAC_PORT_MAX_BURST_SIZE: { 1086 uint32_t burst_size; 1087 switch (portn) { 1088 case XMAC_PORT_0: 1089 case XMAC_PORT_1: 1090 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1091 " npi_mac_port_attr" 1092 " BMAC_PORT_MAX_BURST_SIZE:" 1093 " Invalid Input: portn <%d>", 1094 portn)); 1095 return (NPI_FAILURE | NPI_MAC_PORT_ATTR_INVALID(portn)); 1096 case BMAC_PORT_0: 1097 case BMAC_PORT_1: 1098 /* NOTE: Not used in Full duplex mode */ 1099 if (op == OP_SET) { 1100 burst_size = attrp->idata[0]; 1101 ASSERT((burst_size & ~0x7FFF) == 0); 1102 if ((burst_size & ~0x7FFF) != 0) { 1103 NPI_ERROR_MSG((handle.function, 1104 NPI_ERR_CTL, 1105 " npi_mac_port_attr" 1106 " BMAC_MAX_BURST_SIZE:" 1107 " Invalid Input:" 1108 " burst_size <0x%x>", 1109 burst_size)); 1110 return (NPI_FAILURE | 1111 NPI_MAC_PORT_ATTR_INVALID(portn)); 1112 } 1113 BMAC_REG_RD(handle, portn, BMAC_MAX_REG, &val); 1114 val &= ~BMAC_MAX_BURST_MASK; 1115 val |= (burst_size << BMAC_MAX_BURST_SHIFT); 1116 BMAC_REG_WR(handle, portn, BMAC_MAX_REG, val); 1117 } else { 1118 BMAC_REG_RD(handle, portn, BMAC_MAX_REG, &val); 1119 burst_size = (val & BMAC_MAX_BURST_MASK) 1120 >> BMAC_MAX_BURST_SHIFT; 1121 attrp->odata[0] = burst_size; 1122 } 1123 break; 1124 default: 1125 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1126 } 1127 } break; 1128 1129 case BMAC_PORT_PA_SIZE: { 1130 uint32_t pa_size; 1131 switch (portn) { 1132 case XMAC_PORT_0: 1133 case XMAC_PORT_1: 1134 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1135 " npi_mac_port_attr" 1136 " BMAC_PORT_PA_SIZE:" 1137 " Invalid Input: portn <%d>", 1138 portn)); 1139 return (NPI_FAILURE | NPI_MAC_PORT_ATTR_INVALID(portn)); 1140 case BMAC_PORT_0: 1141 case BMAC_PORT_1: 1142 if (op == OP_SET) { 1143 pa_size = attrp->idata[0]; 1144 ASSERT((pa_size & ~0x3FF) == 0); 1145 if ((pa_size & ~0x3FF) != 0) { 1146 NPI_ERROR_MSG((handle.function, 1147 NPI_ERR_CTL, 1148 " npi_mac_port_attr" 1149 " BMAC_PORT_PA_SIZE:" 1150 " Invalid Input: pa_size <0x%x>", 1151 pa_size)); 1152 1153 return (NPI_FAILURE | 1154 NPI_MAC_PORT_ATTR_INVALID(portn)); 1155 } 1156 BMAC_REG_RD(handle, portn, MAC_PA_SIZE_REG, 1157 &val); 1158 val &= ~BMAC_PA_SIZE_MASK; 1159 val |= (pa_size << 0); 1160 BMAC_REG_WR(handle, portn, MAC_PA_SIZE_REG, 1161 val); 1162 } else { 1163 BMAC_REG_RD(handle, portn, MAC_PA_SIZE_REG, 1164 &val); 1165 pa_size = (val & BMAC_PA_SIZE_MASK) >> 0; 1166 attrp->odata[0] = pa_size; 1167 } 1168 break; 1169 default: 1170 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1171 } 1172 } break; 1173 1174 case BMAC_PORT_CTRL_TYPE: { 1175 uint32_t ctrl_type; 1176 switch (portn) { 1177 case XMAC_PORT_0: 1178 case XMAC_PORT_1: 1179 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1180 " npi_mac_port_attr" 1181 " BMAC_PORT_CTRL_TYPE:" 1182 " Invalid Input: portn <%d>", 1183 portn)); 1184 return (NPI_FAILURE | NPI_MAC_PORT_ATTR_INVALID(portn)); 1185 case BMAC_PORT_0: 1186 case BMAC_PORT_1: 1187 if (op == OP_SET) { 1188 ctrl_type = attrp->idata[0]; 1189 ASSERT((ctrl_type & ~0xFFFF) == 0); 1190 if ((ctrl_type & ~0xFFFF) != 0) { 1191 NPI_ERROR_MSG((handle.function, 1192 NPI_ERR_CTL, 1193 " npi_mac_port_attr" 1194 " BMAC_PORT_CTRL_TYPE:" 1195 " Invalid Input:" 1196 " ctrl_type <0x%x>", 1197 ctrl_type)); 1198 return (NPI_FAILURE | 1199 NPI_MAC_PORT_ATTR_INVALID(portn)); 1200 } 1201 BMAC_REG_WR(handle, portn, MAC_CTRL_TYPE_REG, 1202 val); 1203 } else { 1204 BMAC_REG_RD(handle, portn, MAC_CTRL_TYPE_REG, 1205 &val); 1206 ctrl_type = (val & 0xFFFF); 1207 attrp->odata[0] = ctrl_type; 1208 } 1209 break; 1210 default: 1211 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1212 } 1213 } break; 1214 1215 case XMAC_10G_PORT_IPG: 1216 { 1217 uint32_t ipg0; 1218 1219 switch (portn) { 1220 case XMAC_PORT_0: 1221 case XMAC_PORT_1: 1222 if (op == OP_SET) { 1223 ipg0 = attrp->idata[0]; 1224 ASSERT((ipg0 == XGMII_IPG_12_15) || \ 1225 (ipg0 == XGMII_IPG_16_19) || \ 1226 (ipg0 == XGMII_IPG_20_23)); 1227 if ((ipg0 != XGMII_IPG_12_15) && 1228 (ipg0 != XGMII_IPG_16_19) && 1229 (ipg0 != XGMII_IPG_20_23)) { 1230 NPI_ERROR_MSG((handle.function, 1231 NPI_ERR_CTL, 1232 " npi_mac_port_attr" 1233 " MAC_10G_PORT_IPG:" 1234 " Invalid Input:" 1235 " xgmii_ipg <0x%x>", 1236 ipg0)); 1237 return (NPI_FAILURE | 1238 NPI_MAC_PORT_ATTR_INVALID(portn)); 1239 } 1240 1241 XMAC_REG_RD(handle, portn, XMAC_IPG_REG, &val); 1242 val &= ~(XMAC_IPG_VALUE_MASK | 1243 XMAC_IPG_VALUE1_MASK); 1244 1245 switch (ipg0) { 1246 case XGMII_IPG_12_15: 1247 val |= (IPG_12_15_BYTE << 1248 XMAC_IPG_VALUE_SHIFT); 1249 break; 1250 case XGMII_IPG_16_19: 1251 val |= (IPG_16_19_BYTE << 1252 XMAC_IPG_VALUE_SHIFT); 1253 break; 1254 case XGMII_IPG_20_23: 1255 val |= (IPG_20_23_BYTE << 1256 XMAC_IPG_VALUE_SHIFT); 1257 break; 1258 default: 1259 return (NPI_FAILURE | 1260 NPI_MAC_PORT_ATTR_INVALID(portn)); 1261 } 1262 XMAC_REG_WR(handle, portn, XMAC_IPG_REG, val); 1263 } else { 1264 XMAC_REG_RD(handle, portn, XMAC_IPG_REG, &val); 1265 ipg0 = (val & XMAC_IPG_VALUE_MASK) >> 1266 XMAC_IPG_VALUE_SHIFT; 1267 switch (ipg0) { 1268 case IPG_12_15_BYTE: 1269 attrp->odata[0] = XGMII_IPG_12_15; 1270 break; 1271 case IPG_16_19_BYTE: 1272 attrp->odata[0] = XGMII_IPG_16_19; 1273 break; 1274 case IPG_20_23_BYTE: 1275 attrp->odata[0] = XGMII_IPG_20_23; 1276 break; 1277 default: 1278 return (NPI_FAILURE | 1279 NPI_MAC_PORT_ATTR_INVALID(portn)); 1280 } 1281 } 1282 break; 1283 case BMAC_PORT_0: 1284 case BMAC_PORT_1: 1285 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1286 " npi_mac_port_attr" "MAC_PORT_IPG:" 1287 " Invalid Input: portn <%d>", 1288 portn)); 1289 default: 1290 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1291 } 1292 break; 1293 } 1294 1295 case XMAC_PORT_IPG: 1296 { 1297 uint32_t ipg1; 1298 switch (portn) { 1299 case XMAC_PORT_0: 1300 case XMAC_PORT_1: 1301 if (op == OP_SET) { 1302 ipg1 = attrp->idata[0]; 1303 ASSERT((ipg1 == MII_GMII_IPG_12) || \ 1304 (ipg1 == MII_GMII_IPG_13) || \ 1305 (ipg1 == MII_GMII_IPG_14) || \ 1306 (ipg1 == MII_GMII_IPG_15) || \ 1307 (ipg1 == MII_GMII_IPG_16)); 1308 if ((ipg1 != MII_GMII_IPG_12) && 1309 (ipg1 != MII_GMII_IPG_13) && 1310 (ipg1 != MII_GMII_IPG_14) && 1311 (ipg1 != MII_GMII_IPG_15) && 1312 (ipg1 != MII_GMII_IPG_16)) { 1313 NPI_ERROR_MSG((handle.function, 1314 NPI_ERR_CTL, 1315 " npi_mac_port_attr" 1316 " XMAC_PORT_IPG:" 1317 " Invalid Input:" 1318 " mii_gmii_ipg <0x%x>", 1319 ipg1)); 1320 return (NPI_FAILURE | 1321 NPI_MAC_PORT_ATTR_INVALID(portn)); 1322 } 1323 1324 XMAC_REG_RD(handle, portn, XMAC_IPG_REG, &val); 1325 val &= ~(XMAC_IPG_VALUE_MASK | 1326 XMAC_IPG_VALUE1_MASK); 1327 1328 switch (ipg1) { 1329 case MII_GMII_IPG_12: 1330 val |= (IPG1_12_BYTES << 1331 XMAC_IPG_VALUE1_SHIFT); 1332 break; 1333 case MII_GMII_IPG_13: 1334 val |= (IPG1_13_BYTES << 1335 XMAC_IPG_VALUE1_SHIFT); 1336 break; 1337 case MII_GMII_IPG_14: 1338 val |= (IPG1_14_BYTES << 1339 XMAC_IPG_VALUE1_SHIFT); 1340 break; 1341 case MII_GMII_IPG_15: 1342 val |= (IPG1_15_BYTES << 1343 XMAC_IPG_VALUE1_SHIFT); 1344 break; 1345 case MII_GMII_IPG_16: 1346 val |= (IPG1_16_BYTES << 1347 XMAC_IPG_VALUE1_SHIFT); 1348 break; 1349 default: 1350 return (NPI_FAILURE | 1351 NPI_MAC_PORT_ATTR_INVALID(portn)); 1352 } 1353 XMAC_REG_WR(handle, portn, XMAC_IPG_REG, val); 1354 } else { 1355 XMAC_REG_RD(handle, portn, XMAC_IPG_REG, &val); 1356 ipg1 = (val & XMAC_IPG_VALUE1_MASK) >> 1357 XMAC_IPG_VALUE1_SHIFT; 1358 switch (ipg1) { 1359 case IPG1_12_BYTES: 1360 attrp->odata[1] = MII_GMII_IPG_12; 1361 break; 1362 case IPG1_13_BYTES: 1363 attrp->odata[1] = MII_GMII_IPG_13; 1364 break; 1365 case IPG1_14_BYTES: 1366 attrp->odata[1] = MII_GMII_IPG_14; 1367 break; 1368 case IPG1_15_BYTES: 1369 attrp->odata[1] = MII_GMII_IPG_15; 1370 break; 1371 case IPG1_16_BYTES: 1372 attrp->odata[1] = MII_GMII_IPG_16; 1373 break; 1374 default: 1375 return (NPI_FAILURE | 1376 NPI_MAC_PORT_ATTR_INVALID(portn)); 1377 } 1378 } 1379 break; 1380 case BMAC_PORT_0: 1381 case BMAC_PORT_1: 1382 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1383 " npi_mac_port_attr" 1384 " MAC_PORT_IPG:" 1385 " Invalid Input: portn <%d>", 1386 portn)); 1387 default: 1388 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1389 } 1390 break; 1391 } 1392 1393 case MAC_PORT_ADDR: { 1394 uint32_t addr0; 1395 uint32_t addr1; 1396 uint32_t addr2; 1397 1398 switch (portn) { 1399 case XMAC_PORT_0: 1400 case XMAC_PORT_1: 1401 if (op == OP_SET) { 1402 addr0 = attrp->idata[0]; 1403 addr1 = attrp->idata[1]; 1404 addr2 = attrp->idata[2]; 1405 ASSERT((addr0 & ~0xFFFF) == 0); 1406 if ((addr0 & ~0xFFFF) != 0) { 1407 NPI_ERROR_MSG((handle.function, 1408 NPI_ERR_CTL, 1409 " npi_mac_port_attr" 1410 " MAC_PORT_ADDR:" 1411 " Invalid Input:" 1412 " addr0 <0x%x>", addr0)); 1413 1414 return (NPI_FAILURE | 1415 NPI_MAC_PORT_ATTR_INVALID(portn)); 1416 } 1417 ASSERT((addr1 & ~0xFFFF) == 0); 1418 if ((addr1 & ~0xFFFF) != 0) { 1419 NPI_ERROR_MSG((handle.function, 1420 NPI_ERR_CTL, 1421 " npi_mac_port_attr" 1422 " MAC_PORT_ADDR:" 1423 " Invalid Input:" 1424 " addr1 <0x%x>", addr1)); 1425 return (NPI_FAILURE | 1426 NPI_MAC_PORT_ATTR_INVALID(portn)); 1427 } 1428 ASSERT((addr2 & ~0xFFFF) == 0); 1429 if ((addr2 & ~0xFFFF) != 0) { 1430 NPI_ERROR_MSG((handle.function, 1431 NPI_ERR_CTL, 1432 " npi_mac_port_attr" 1433 " MAC_PORT_ADDR:" 1434 " Invalid Input:" 1435 " addr2 <0x%x.", 1436 addr2)); 1437 1438 return (NPI_FAILURE | 1439 NPI_MAC_PORT_ATTR_INVALID(portn)); 1440 } 1441 XMAC_REG_WR(handle, portn, XMAC_ADDR0_REG, 1442 addr0); 1443 XMAC_REG_WR(handle, portn, XMAC_ADDR1_REG, 1444 addr1); 1445 XMAC_REG_WR(handle, portn, XMAC_ADDR2_REG, 1446 addr2); 1447 } else { 1448 XMAC_REG_RD(handle, portn, XMAC_ADDR0_REG, 1449 &addr0); 1450 XMAC_REG_RD(handle, portn, XMAC_ADDR1_REG, 1451 &addr1); 1452 XMAC_REG_RD(handle, portn, XMAC_ADDR2_REG, 1453 &addr2); 1454 attrp->odata[0] = addr0 & MAC_ADDR_REG_MASK; 1455 attrp->odata[1] = addr1 & MAC_ADDR_REG_MASK; 1456 attrp->odata[2] = addr2 & MAC_ADDR_REG_MASK; 1457 } 1458 break; 1459 case BMAC_PORT_0: 1460 case BMAC_PORT_1: 1461 if (op == OP_SET) { 1462 addr0 = attrp->idata[0]; 1463 addr1 = attrp->idata[1]; 1464 addr2 = attrp->idata[2]; 1465 ASSERT((addr0 & ~0xFFFF) == 0); 1466 if ((addr0 & ~0xFFFF) != 0) { 1467 NPI_ERROR_MSG((handle.function, 1468 NPI_ERR_CTL, 1469 " npi_mac_port_attr" 1470 " MAC_PORT_ADDR:" 1471 " Invalid Input:" 1472 " addr0 <0x%x>", 1473 addr0)); 1474 return (NPI_FAILURE | 1475 NPI_MAC_PORT_ATTR_INVALID(portn)); 1476 } 1477 ASSERT((addr1 & ~0xFFFF) == 0); 1478 if ((addr1 & ~0xFFFF) != 0) { 1479 NPI_ERROR_MSG((handle.function, 1480 NPI_ERR_CTL, 1481 " npi_mac_port_attr" 1482 " MAC_PORT_ADDR:" 1483 " Invalid Input:" 1484 " addr1 <0x%x>", 1485 addr1)); 1486 return (NPI_FAILURE | 1487 NPI_MAC_PORT_ATTR_INVALID(portn)); 1488 } 1489 ASSERT((addr2 & ~0xFFFF) == 0); 1490 if ((addr2 & ~0xFFFF) != 0) { 1491 NPI_ERROR_MSG((handle.function, 1492 NPI_ERR_CTL, 1493 " npi_mac_port_attr" 1494 " MAC_PORT_ADDR:" 1495 " Invalid Input:" 1496 " addr2 <0x%x>", 1497 addr2)); 1498 return (NPI_FAILURE | 1499 NPI_MAC_PORT_ATTR_INVALID(portn)); 1500 } 1501 BMAC_REG_WR(handle, portn, BMAC_ADDR0_REG, 1502 addr0); 1503 BMAC_REG_WR(handle, portn, BMAC_ADDR1_REG, 1504 addr1); 1505 BMAC_REG_WR(handle, portn, BMAC_ADDR2_REG, 1506 addr2); 1507 } else { 1508 BMAC_REG_RD(handle, portn, BMAC_ADDR0_REG, 1509 &addr0); 1510 BMAC_REG_RD(handle, portn, BMAC_ADDR1_REG, 1511 &addr1); 1512 BMAC_REG_RD(handle, portn, BMAC_ADDR2_REG, 1513 &addr2); 1514 attrp->odata[0] = addr0 & MAC_ADDR_REG_MASK; 1515 attrp->odata[1] = addr1 & MAC_ADDR_REG_MASK; 1516 attrp->odata[2] = addr2 & MAC_ADDR_REG_MASK; 1517 } 1518 break; 1519 default: 1520 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1521 } 1522 } break; 1523 1524 case MAC_PORT_ADDR_FILTER: { 1525 uint32_t addr0; 1526 uint32_t addr1; 1527 uint32_t addr2; 1528 1529 switch (portn) { 1530 case XMAC_PORT_0: 1531 case XMAC_PORT_1: 1532 if (op == OP_SET) { 1533 addr0 = attrp->idata[0]; 1534 addr1 = attrp->idata[1]; 1535 addr2 = attrp->idata[2]; 1536 ASSERT((addr0 & ~0xFFFF) == 0); 1537 if ((addr0 & ~0xFFFF) != 0) { 1538 NPI_ERROR_MSG((handle.function, 1539 NPI_ERR_CTL, 1540 " npi_mac_port_attr" 1541 " MAC_PORT_ADDR_FILTER:" 1542 " Invalid Input:" 1543 " addr0 <0x%x>", 1544 addr0)); 1545 return (NPI_FAILURE | 1546 NPI_MAC_PORT_ATTR_INVALID(portn)); 1547 } 1548 ASSERT((addr1 & ~0xFFFF) == 0); 1549 if ((addr1 & ~0xFFFF) != 0) { 1550 NPI_ERROR_MSG((handle.function, 1551 NPI_ERR_CTL, 1552 " npi_mac_port_attr" 1553 " MAC_PORT_ADDR_FILTER:" 1554 " Invalid Input:" 1555 " addr1 <0x%x>", 1556 addr1)); 1557 return (NPI_FAILURE | 1558 NPI_MAC_PORT_ATTR_INVALID(portn)); 1559 } 1560 ASSERT((addr2 & ~0xFFFF) == 0); 1561 if ((addr2 & ~0xFFFF) != 0) { 1562 NPI_ERROR_MSG((handle.function, 1563 NPI_ERR_CTL, 1564 " npi_mac_port_attr" 1565 " MAC_PORT_ADDR_FILTER:" 1566 " Invalid Input:" 1567 " addr2 <0x%x>", 1568 addr2)); 1569 return (NPI_FAILURE | 1570 NPI_MAC_PORT_ATTR_INVALID(portn)); 1571 } 1572 XMAC_REG_WR(handle, portn, 1573 XMAC_ADDR_FILT0_REG, addr0); 1574 XMAC_REG_WR(handle, portn, 1575 XMAC_ADDR_FILT1_REG, addr1); 1576 XMAC_REG_WR(handle, portn, 1577 XMAC_ADDR_FILT2_REG, addr2); 1578 } else { 1579 XMAC_REG_RD(handle, portn, 1580 XMAC_ADDR_FILT0_REG, &addr0); 1581 XMAC_REG_RD(handle, portn, 1582 XMAC_ADDR_FILT1_REG, &addr1); 1583 XMAC_REG_RD(handle, portn, 1584 XMAC_ADDR_FILT2_REG, &addr2); 1585 attrp->odata[0] = addr0 & MAC_ADDR_REG_MASK; 1586 attrp->odata[1] = addr1 & MAC_ADDR_REG_MASK; 1587 attrp->odata[2] = addr2 & MAC_ADDR_REG_MASK; 1588 } 1589 break; 1590 case BMAC_PORT_0: 1591 case BMAC_PORT_1: 1592 if (op == OP_SET) { 1593 addr0 = attrp->idata[0]; 1594 addr1 = attrp->idata[1]; 1595 addr2 = attrp->idata[2]; 1596 ASSERT((addr0 & ~0xFFFF) == 0); 1597 if ((addr0 & ~0xFFFF) != 0) { 1598 NPI_ERROR_MSG((handle.function, 1599 NPI_ERR_CTL, 1600 " npi_mac_port_attr" 1601 " MAC_PORT_ADDR_FILTER:" 1602 " addr0", 1603 addr0)); 1604 return (NPI_FAILURE | 1605 NPI_MAC_PORT_ATTR_INVALID(portn)); 1606 } 1607 ASSERT((addr1 & ~0xFFFF) == 0); 1608 if ((addr1 & ~0xFFFF) != 0) { 1609 NPI_ERROR_MSG((handle.function, 1610 NPI_ERR_CTL, 1611 " npi_mac_port_attr" 1612 " MAC_PORT_ADDR_FILTER:" 1613 " Invalid Input:" 1614 " addr1 <0x%x>", 1615 addr1)); 1616 return (NPI_FAILURE | 1617 NPI_MAC_PORT_ATTR_INVALID(portn)); 1618 } 1619 ASSERT((addr2 & ~0xFFFF) == 0); 1620 if ((addr2 & ~0xFFFF) != 0) { 1621 NPI_ERROR_MSG((handle.function, 1622 NPI_ERR_CTL, 1623 " npi_mac_port_attr" 1624 " MAC_PORT_ADDR_FILTER:" 1625 " Invalid Input:" 1626 " addr2 <0x%x>", 1627 addr2)); 1628 return (NPI_FAILURE | 1629 NPI_MAC_PORT_ATTR_INVALID(portn)); 1630 } 1631 BMAC_REG_WR(handle, portn, MAC_ADDR_FILT0_REG, 1632 addr0); 1633 BMAC_REG_WR(handle, portn, MAC_ADDR_FILT1_REG, 1634 addr1); 1635 BMAC_REG_WR(handle, portn, MAC_ADDR_FILT2_REG, 1636 addr2); 1637 } else { 1638 BMAC_REG_RD(handle, portn, MAC_ADDR_FILT0_REG, 1639 &addr0); 1640 BMAC_REG_RD(handle, portn, MAC_ADDR_FILT1_REG, 1641 &addr1); 1642 BMAC_REG_RD(handle, portn, MAC_ADDR_FILT2_REG, 1643 &addr2); 1644 attrp->odata[0] = addr0 & MAC_ADDR_REG_MASK; 1645 attrp->odata[1] = addr1 & MAC_ADDR_REG_MASK; 1646 attrp->odata[2] = addr2 & MAC_ADDR_REG_MASK; 1647 } 1648 break; 1649 default: 1650 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1651 } 1652 } break; 1653 1654 case MAC_PORT_ADDR_FILTER_MASK: { 1655 uint32_t mask_1_2; 1656 uint32_t mask_0; 1657 1658 switch (portn) { 1659 case XMAC_PORT_0: 1660 case XMAC_PORT_1: 1661 if (op == OP_SET) { 1662 mask_0 = attrp->idata[0]; 1663 mask_1_2 = attrp->idata[1]; 1664 ASSERT((mask_0 & ~0xFFFF) == 0); 1665 if ((mask_0 & ~0xFFFF) != 0) { 1666 NPI_ERROR_MSG((handle.function, 1667 NPI_ERR_CTL, 1668 " npi_mac_port_attr" 1669 " MAC_ADDR_FILTER_MASK:" 1670 " Invalid Input:" 1671 " mask_0 <0x%x>", 1672 mask_0)); 1673 return (NPI_FAILURE | 1674 NPI_MAC_PORT_ATTR_INVALID(portn)); 1675 } 1676 ASSERT((mask_1_2 & ~0xFF) == 0); 1677 if ((mask_1_2 & ~0xFF) != 0) { 1678 NPI_ERROR_MSG((handle.function, 1679 NPI_ERR_CTL, 1680 " npi_mac_port_attr" 1681 " MAC_ADDR_FILTER_MASK:" 1682 " Invalid Input:" 1683 " mask_1_2 <0x%x>", 1684 mask_1_2)); 1685 return (NPI_FAILURE | 1686 NPI_MAC_PORT_ATTR_INVALID(portn)); 1687 } 1688 XMAC_REG_WR(handle, portn, 1689 XMAC_ADDR_FILT0_MASK_REG, mask_0); 1690 XMAC_REG_WR(handle, portn, 1691 XMAC_ADDR_FILT12_MASK_REG, mask_1_2); 1692 } else { 1693 XMAC_REG_RD(handle, portn, 1694 XMAC_ADDR_FILT0_MASK_REG, &mask_0); 1695 XMAC_REG_RD(handle, portn, 1696 XMAC_ADDR_FILT12_MASK_REG, &mask_1_2); 1697 attrp->odata[0] = mask_0 & 0xFFFF; 1698 attrp->odata[1] = mask_1_2 & 0xFF; 1699 } 1700 break; 1701 case BMAC_PORT_0: 1702 case BMAC_PORT_1: 1703 if (op == OP_SET) { 1704 mask_0 = attrp->idata[0]; 1705 mask_1_2 = attrp->idata[1]; 1706 BMAC_REG_WR(handle, portn, 1707 MAC_ADDR_FILT00_MASK_REG, mask_0); 1708 BMAC_REG_WR(handle, portn, 1709 MAC_ADDR_FILT12_MASK_REG, mask_1_2); 1710 } else { 1711 BMAC_REG_RD(handle, portn, 1712 MAC_ADDR_FILT00_MASK_REG, &mask_0); 1713 BMAC_REG_RD(handle, portn, 1714 MAC_ADDR_FILT12_MASK_REG, &mask_1_2); 1715 attrp->odata[0] = mask_0; 1716 attrp->odata[1] = mask_1_2; 1717 } 1718 break; 1719 default: 1720 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1721 } 1722 } break; 1723 1724 default: 1725 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1726 " npi_mac_port_attr" 1727 " Invalid Input:" 1728 " attr <0x%x>", attrp->type)); 1729 return (NPI_FAILURE | NPI_MAC_PORT_ATTR_INVALID(portn)); 1730 } 1731 1732 return (NPI_SUCCESS); 1733 } 1734 1735 npi_status_t 1736 npi_xmac_reset(npi_handle_t handle, uint8_t portn, npi_mac_reset_t mode) 1737 { 1738 uint64_t val; 1739 boolean_t txmac = B_FALSE; 1740 1741 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 1742 1743 switch (mode) { 1744 case XTX_MAC_REG_RESET: 1745 XMAC_REG_WR(handle, portn, XTXMAC_SW_RST_REG, XTXMAC_REG_RST); 1746 XMAC_WAIT_REG(handle, portn, XTXMAC_SW_RST_REG, val); 1747 txmac = B_TRUE; 1748 break; 1749 case XRX_MAC_REG_RESET: 1750 XMAC_REG_WR(handle, portn, XRXMAC_SW_RST_REG, XRXMAC_REG_RST); 1751 XMAC_WAIT_REG(handle, portn, XRXMAC_SW_RST_REG, val); 1752 break; 1753 case XTX_MAC_LOGIC_RESET: 1754 XMAC_REG_WR(handle, portn, XTXMAC_SW_RST_REG, XTXMAC_SOFT_RST); 1755 XMAC_WAIT_REG(handle, portn, XTXMAC_SW_RST_REG, val); 1756 txmac = B_TRUE; 1757 break; 1758 case XRX_MAC_LOGIC_RESET: 1759 XMAC_REG_WR(handle, portn, XRXMAC_SW_RST_REG, XRXMAC_SOFT_RST); 1760 XMAC_WAIT_REG(handle, portn, XRXMAC_SW_RST_REG, val); 1761 break; 1762 case XTX_MAC_RESET_ALL: 1763 XMAC_REG_WR(handle, portn, XTXMAC_SW_RST_REG, 1764 XTXMAC_SOFT_RST | XTXMAC_REG_RST); 1765 XMAC_WAIT_REG(handle, portn, XTXMAC_SW_RST_REG, val); 1766 txmac = B_TRUE; 1767 break; 1768 case XRX_MAC_RESET_ALL: 1769 XMAC_REG_WR(handle, portn, XRXMAC_SW_RST_REG, 1770 XRXMAC_SOFT_RST | XRXMAC_REG_RST); 1771 XMAC_WAIT_REG(handle, portn, XRXMAC_SW_RST_REG, val); 1772 break; 1773 default: 1774 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1775 " npi_mac_reset" 1776 " Invalid Input: mode <0x%x>", 1777 mode)); 1778 return (NPI_FAILURE | NPI_MAC_RESET_MODE_INVALID(portn)); 1779 } 1780 1781 if (val != 0) { 1782 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1783 " npi_xmac_reset" 1784 " HW ERROR: MAC_RESET failed <0x%x>", 1785 val)); 1786 1787 if (txmac) 1788 return (NPI_FAILURE | NPI_TXMAC_RESET_FAILED(portn)); 1789 else 1790 return (NPI_FAILURE | NPI_RXMAC_RESET_FAILED(portn)); 1791 } 1792 1793 return (NPI_SUCCESS); 1794 } 1795 1796 npi_status_t 1797 npi_xmac_xif_config(npi_handle_t handle, config_op_t op, uint8_t portn, 1798 xmac_xif_config_t config) 1799 { 1800 uint64_t val = 0; 1801 1802 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 1803 1804 switch (op) { 1805 case ENABLE: 1806 case DISABLE: 1807 ASSERT((config != 0) && ((config & ~CFG_XMAC_XIF_ALL) == 0)); 1808 if ((config == 0) || (config & ~CFG_XMAC_XIF_ALL) != 0) { 1809 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1810 " npi_xmac_xif_config" 1811 " Invalid Input:" 1812 " config <0x%x>", config)); 1813 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 1814 } 1815 if (op == ENABLE) { 1816 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1817 if (config & CFG_XMAC_XIF_LED_FORCE) 1818 val |= XMAC_XIF_FORCE_LED_ON; 1819 if (config & CFG_XMAC_XIF_LED_POLARITY) 1820 val |= XMAC_XIF_LED_POLARITY; 1821 if (config & CFG_XMAC_XIF_SEL_POR_CLK_SRC) 1822 val |= XMAC_XIF_SEL_POR_CLK_SRC; 1823 if (config & CFG_XMAC_XIF_TX_OUTPUT) 1824 val |= XMAC_XIF_TX_OUTPUT_EN; 1825 1826 if (config & CFG_XMAC_XIF_LOOPBACK) { 1827 val &= ~XMAC_XIF_SEL_POR_CLK_SRC; 1828 val |= XMAC_XIF_LOOPBACK; 1829 } 1830 1831 if (config & CFG_XMAC_XIF_LFS) 1832 val &= ~XMAC_XIF_LFS_DISABLE; 1833 if (config & CFG_XMAC_XIF_XPCS_BYPASS) 1834 val |= XMAC_XIF_XPCS_BYPASS; 1835 if (config & CFG_XMAC_XIF_1G_PCS_BYPASS) 1836 val |= XMAC_XIF_1G_PCS_BYPASS; 1837 if (config & CFG_XMAC_XIF_SEL_CLK_25MHZ) 1838 val |= XMAC_XIF_SEL_CLK_25MHZ; 1839 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1840 1841 } else { 1842 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1843 if (config & CFG_XMAC_XIF_LED_FORCE) 1844 val &= ~XMAC_XIF_FORCE_LED_ON; 1845 if (config & CFG_XMAC_XIF_LED_POLARITY) 1846 val &= ~XMAC_XIF_LED_POLARITY; 1847 if (config & CFG_XMAC_XIF_SEL_POR_CLK_SRC) 1848 val &= ~XMAC_XIF_SEL_POR_CLK_SRC; 1849 if (config & CFG_XMAC_XIF_TX_OUTPUT) 1850 val &= ~XMAC_XIF_TX_OUTPUT_EN; 1851 if (config & CFG_XMAC_XIF_LOOPBACK) 1852 val &= ~XMAC_XIF_LOOPBACK; 1853 if (config & CFG_XMAC_XIF_LFS) 1854 val |= XMAC_XIF_LFS_DISABLE; 1855 if (config & CFG_XMAC_XIF_XPCS_BYPASS) 1856 val &= ~XMAC_XIF_XPCS_BYPASS; 1857 if (config & CFG_XMAC_XIF_1G_PCS_BYPASS) 1858 val &= ~XMAC_XIF_1G_PCS_BYPASS; 1859 if (config & CFG_XMAC_XIF_SEL_CLK_25MHZ) 1860 val &= ~XMAC_XIF_SEL_CLK_25MHZ; 1861 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1862 } 1863 break; 1864 case INIT: 1865 ASSERT((config & ~CFG_XMAC_XIF_ALL) == 0); 1866 if ((config & ~CFG_XMAC_XIF_ALL) != 0) { 1867 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1868 " npi_xmac_xif_config" 1869 " Invalid Input: config <0x%x>", 1870 config)); 1871 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 1872 } 1873 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1874 1875 if (config & CFG_XMAC_XIF_LED_FORCE) 1876 val |= XMAC_XIF_FORCE_LED_ON; 1877 else 1878 val &= ~XMAC_XIF_FORCE_LED_ON; 1879 if (config & CFG_XMAC_XIF_LED_POLARITY) 1880 val |= XMAC_XIF_LED_POLARITY; 1881 else 1882 val &= ~XMAC_XIF_LED_POLARITY; 1883 if (config & CFG_XMAC_XIF_SEL_POR_CLK_SRC) 1884 val |= XMAC_XIF_SEL_POR_CLK_SRC; 1885 else 1886 val &= ~XMAC_XIF_SEL_POR_CLK_SRC; 1887 if (config & CFG_XMAC_XIF_TX_OUTPUT) 1888 val |= XMAC_XIF_TX_OUTPUT_EN; 1889 else 1890 val &= ~XMAC_XIF_TX_OUTPUT_EN; 1891 1892 if (config & CFG_XMAC_XIF_LOOPBACK) { 1893 val &= ~XMAC_XIF_SEL_POR_CLK_SRC; 1894 val |= XMAC_XIF_LOOPBACK; 1895 #ifdef AXIS_DEBUG_LB 1896 val |= XMAC_RX_MAC2IPP_PKT_CNT_EN; 1897 #endif 1898 } else { 1899 val &= ~XMAC_XIF_LOOPBACK; 1900 } 1901 1902 if (config & CFG_XMAC_XIF_LFS) 1903 val &= ~XMAC_XIF_LFS_DISABLE; 1904 else 1905 val |= XMAC_XIF_LFS_DISABLE; 1906 if (config & CFG_XMAC_XIF_XPCS_BYPASS) 1907 val |= XMAC_XIF_XPCS_BYPASS; 1908 else 1909 val &= ~XMAC_XIF_XPCS_BYPASS; 1910 if (config & CFG_XMAC_XIF_1G_PCS_BYPASS) 1911 val |= XMAC_XIF_1G_PCS_BYPASS; 1912 else 1913 val &= ~XMAC_XIF_1G_PCS_BYPASS; 1914 if (config & CFG_XMAC_XIF_SEL_CLK_25MHZ) 1915 val |= XMAC_XIF_SEL_CLK_25MHZ; 1916 else 1917 val &= ~XMAC_XIF_SEL_CLK_25MHZ; 1918 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1919 1920 break; 1921 default: 1922 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1923 " npi_xmac_xif_config" 1924 " Invalid Input: op <0x%x>", op)); 1925 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 1926 } 1927 1928 return (NPI_SUCCESS); 1929 } 1930 1931 npi_status_t 1932 npi_xmac_tx_config(npi_handle_t handle, config_op_t op, uint8_t portn, 1933 xmac_tx_config_t config) 1934 { 1935 uint64_t val = 0; 1936 1937 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 1938 1939 switch (op) { 1940 case ENABLE: 1941 case DISABLE: 1942 ASSERT((config != 0) && ((config & ~CFG_XMAC_TX_ALL) == 0)); 1943 if ((config == 0) || (config & ~CFG_XMAC_TX_ALL) != 0) { 1944 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1945 " npi_xmac_tx_config" 1946 " Invalid Input: config <0x%x>", 1947 config)); 1948 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 1949 } 1950 if (op == ENABLE) { 1951 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1952 if (config & CFG_XMAC_TX) 1953 val |= XMAC_TX_CFG_TX_ENABLE; 1954 if (config & CFG_XMAC_TX_STRETCH_MODE) 1955 val |= XMAC_TX_CFG_STRETCH_MD; 1956 if (config & CFG_XMAC_VAR_IPG) 1957 val |= XMAC_TX_CFG_VAR_MIN_IPG_EN; 1958 if (config & CFG_XMAC_TX_CRC) 1959 val &= ~XMAC_TX_CFG_ALWAYS_NO_CRC; 1960 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1961 } else { 1962 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1963 if (config & CFG_XMAC_TX) 1964 val &= ~XMAC_TX_CFG_TX_ENABLE; 1965 if (config & CFG_XMAC_TX_STRETCH_MODE) 1966 val &= ~XMAC_TX_CFG_STRETCH_MD; 1967 if (config & CFG_XMAC_VAR_IPG) 1968 val &= ~XMAC_TX_CFG_VAR_MIN_IPG_EN; 1969 if (config & CFG_XMAC_TX_CRC) 1970 val |= XMAC_TX_CFG_ALWAYS_NO_CRC; 1971 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1972 } 1973 break; 1974 case INIT: 1975 ASSERT((config & ~CFG_XMAC_TX_ALL) == 0); 1976 if ((config & ~CFG_XMAC_TX_ALL) != 0) { 1977 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1978 " npi_xmac_tx_config" 1979 " Invalid Input: config <0x%x>", 1980 config)); 1981 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 1982 } 1983 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1984 if (config & CFG_XMAC_TX) 1985 val |= XMAC_TX_CFG_TX_ENABLE; 1986 else 1987 val &= ~XMAC_TX_CFG_TX_ENABLE; 1988 if (config & CFG_XMAC_TX_STRETCH_MODE) 1989 val |= XMAC_TX_CFG_STRETCH_MD; 1990 else 1991 val &= ~XMAC_TX_CFG_STRETCH_MD; 1992 if (config & CFG_XMAC_VAR_IPG) 1993 val |= XMAC_TX_CFG_VAR_MIN_IPG_EN; 1994 else 1995 val &= ~XMAC_TX_CFG_VAR_MIN_IPG_EN; 1996 if (config & CFG_XMAC_TX_CRC) 1997 val &= ~XMAC_TX_CFG_ALWAYS_NO_CRC; 1998 else 1999 val |= XMAC_TX_CFG_ALWAYS_NO_CRC; 2000 2001 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 2002 break; 2003 default: 2004 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2005 " npi_xmac_tx_config" 2006 " Invalid Input: op <0x%x>", 2007 op)); 2008 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2009 } 2010 2011 return (NPI_SUCCESS); 2012 } 2013 2014 npi_status_t 2015 npi_xmac_rx_config(npi_handle_t handle, config_op_t op, uint8_t portn, 2016 xmac_rx_config_t config) 2017 { 2018 uint64_t val = 0; 2019 2020 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2021 2022 switch (op) { 2023 case ENABLE: 2024 case DISABLE: 2025 ASSERT((config != 0) && ((config & ~CFG_XMAC_RX_ALL) == 0)); 2026 if ((config == 0) || (config & ~CFG_XMAC_RX_ALL) != 0) { 2027 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2028 " npi_xmac_rx_config" 2029 " Invalid Input: config <0x%x>", 2030 config)); 2031 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2032 } 2033 if (op == ENABLE) { 2034 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 2035 if (config & CFG_XMAC_RX) 2036 val |= XMAC_RX_CFG_RX_ENABLE; 2037 if (config & CFG_XMAC_RX_PROMISCUOUS) 2038 val |= XMAC_RX_CFG_PROMISC; 2039 if (config & CFG_XMAC_RX_PROMISCUOUSGROUP) 2040 val |= XMAC_RX_CFG_PROMISC_GROUP; 2041 if (config & CFG_XMAC_RX_ERRCHK) 2042 val &= ~XMAC_RX_CFG_ERR_CHK_DISABLE; 2043 if (config & CFG_XMAC_RX_CRC_CHK) 2044 val &= ~XMAC_RX_CFG_CRC_CHK_DISABLE; 2045 if (config & CFG_XMAC_RX_RESV_MULTICAST) 2046 val |= XMAC_RX_CFG_RESERVED_MCAST; 2047 if (config & CFG_XMAC_RX_CODE_VIO_CHK) 2048 val &= ~XMAC_RX_CFG_CD_VIO_CHK; 2049 if (config & CFG_XMAC_RX_HASH_FILTER) 2050 val |= XMAC_RX_CFG_HASH_FILTER_EN; 2051 if (config & CFG_XMAC_RX_ADDR_FILTER) 2052 val |= XMAC_RX_CFG_ADDR_FILTER_EN; 2053 if (config & CFG_XMAC_RX_STRIP_CRC) 2054 val |= XMAC_RX_CFG_STRIP_CRC; 2055 if (config & CFG_XMAC_RX_PAUSE) 2056 val |= XMAC_RX_CFG_RX_PAUSE_EN; 2057 if (config & CFG_XMAC_RX_PASS_FC_FRAME) 2058 val |= XMAC_RX_CFG_PASS_FLOW_CTRL; 2059 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 2060 } else { 2061 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 2062 if (config & CFG_XMAC_RX) 2063 val &= ~XMAC_RX_CFG_RX_ENABLE; 2064 if (config & CFG_XMAC_RX_PROMISCUOUS) 2065 val &= ~XMAC_RX_CFG_PROMISC; 2066 if (config & CFG_XMAC_RX_PROMISCUOUSGROUP) 2067 val &= ~XMAC_RX_CFG_PROMISC_GROUP; 2068 if (config & CFG_XMAC_RX_ERRCHK) 2069 val |= XMAC_RX_CFG_ERR_CHK_DISABLE; 2070 if (config & CFG_XMAC_RX_CRC_CHK) 2071 val |= XMAC_RX_CFG_CRC_CHK_DISABLE; 2072 if (config & CFG_XMAC_RX_RESV_MULTICAST) 2073 val &= ~XMAC_RX_CFG_RESERVED_MCAST; 2074 if (config & CFG_XMAC_RX_CODE_VIO_CHK) 2075 val |= XMAC_RX_CFG_CD_VIO_CHK; 2076 if (config & CFG_XMAC_RX_HASH_FILTER) 2077 val &= ~XMAC_RX_CFG_HASH_FILTER_EN; 2078 if (config & CFG_XMAC_RX_ADDR_FILTER) 2079 val &= ~XMAC_RX_CFG_ADDR_FILTER_EN; 2080 if (config & CFG_XMAC_RX_STRIP_CRC) 2081 val &= ~XMAC_RX_CFG_STRIP_CRC; 2082 if (config & CFG_XMAC_RX_PAUSE) 2083 val &= ~XMAC_RX_CFG_RX_PAUSE_EN; 2084 if (config & CFG_XMAC_RX_PASS_FC_FRAME) 2085 val &= ~XMAC_RX_CFG_PASS_FLOW_CTRL; 2086 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 2087 } 2088 break; 2089 case INIT: 2090 ASSERT((config & ~CFG_XMAC_RX_ALL) == 0); 2091 if ((config & ~CFG_XMAC_RX_ALL) != 0) { 2092 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2093 " npi_xmac_rx_config" 2094 " Invalid Input: config <0x%x>", 2095 config)); 2096 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2097 } 2098 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 2099 if (config & CFG_XMAC_RX) 2100 val |= XMAC_RX_CFG_RX_ENABLE; 2101 else 2102 val &= ~XMAC_RX_CFG_RX_ENABLE; 2103 if (config & CFG_XMAC_RX_PROMISCUOUS) 2104 val |= XMAC_RX_CFG_PROMISC; 2105 else 2106 val &= ~XMAC_RX_CFG_PROMISC; 2107 if (config & CFG_XMAC_RX_PROMISCUOUSGROUP) 2108 val |= XMAC_RX_CFG_PROMISC_GROUP; 2109 else 2110 val &= ~XMAC_RX_CFG_PROMISC_GROUP; 2111 if (config & CFG_XMAC_RX_ERRCHK) 2112 val &= ~XMAC_RX_CFG_ERR_CHK_DISABLE; 2113 else 2114 val |= XMAC_RX_CFG_ERR_CHK_DISABLE; 2115 if (config & CFG_XMAC_RX_CRC_CHK) 2116 val &= ~XMAC_RX_CFG_CRC_CHK_DISABLE; 2117 else 2118 val |= XMAC_RX_CFG_CRC_CHK_DISABLE; 2119 if (config & CFG_XMAC_RX_RESV_MULTICAST) 2120 val |= XMAC_RX_CFG_RESERVED_MCAST; 2121 else 2122 val &= ~XMAC_RX_CFG_RESERVED_MCAST; 2123 if (config & CFG_XMAC_RX_CODE_VIO_CHK) 2124 val &= ~XMAC_RX_CFG_CD_VIO_CHK; 2125 else 2126 val |= XMAC_RX_CFG_CD_VIO_CHK; 2127 if (config & CFG_XMAC_RX_HASH_FILTER) 2128 val |= XMAC_RX_CFG_HASH_FILTER_EN; 2129 else 2130 val &= ~XMAC_RX_CFG_HASH_FILTER_EN; 2131 if (config & CFG_XMAC_RX_ADDR_FILTER) 2132 val |= XMAC_RX_CFG_ADDR_FILTER_EN; 2133 else 2134 val &= ~XMAC_RX_CFG_ADDR_FILTER_EN; 2135 if (config & CFG_XMAC_RX_PAUSE) 2136 val |= XMAC_RX_CFG_RX_PAUSE_EN; 2137 else 2138 val &= ~XMAC_RX_CFG_RX_PAUSE_EN; 2139 if (config & CFG_XMAC_RX_STRIP_CRC) 2140 val |= XMAC_RX_CFG_STRIP_CRC; 2141 else 2142 val &= ~XMAC_RX_CFG_STRIP_CRC; 2143 if (config & CFG_XMAC_RX_PASS_FC_FRAME) 2144 val |= XMAC_RX_CFG_PASS_FLOW_CTRL; 2145 else 2146 val &= ~XMAC_RX_CFG_PASS_FLOW_CTRL; 2147 2148 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 2149 break; 2150 default: 2151 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2152 " npi_xmac_rx_config" 2153 " Invalid Input: op <0x%x>", op)); 2154 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2155 } 2156 2157 return (NPI_SUCCESS); 2158 } 2159 2160 npi_status_t 2161 npi_xmac_tx_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2162 xmac_tx_iconfig_t iconfig) 2163 { 2164 uint64_t val = 0; 2165 2166 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2167 2168 switch (op) { 2169 case ENABLE: 2170 case DISABLE: 2171 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_XMAC_TX_ALL) == 0)); 2172 if ((iconfig == 0) || (iconfig & ~ICFG_XMAC_TX_ALL) != 0) { 2173 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2174 " npi_xmac_tx_iconfig" 2175 " Invalid Input: iconfig <0x%x>", 2176 iconfig)); 2177 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2178 } 2179 XMAC_REG_RD(handle, portn, XTXMAC_STAT_MSK_REG, &val); 2180 if (op == ENABLE) 2181 val &= ~iconfig; 2182 else 2183 val |= iconfig; 2184 XMAC_REG_WR(handle, portn, XTXMAC_STAT_MSK_REG, val); 2185 2186 break; 2187 case INIT: 2188 ASSERT((iconfig & ~ICFG_XMAC_TX_ALL) == 0); 2189 if ((iconfig & ~ICFG_XMAC_TX_ALL) != 0) { 2190 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2191 " npi_xmac_tx_iconfig" 2192 " Invalid Input: iconfig <0x%x>", 2193 iconfig)); 2194 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2195 } 2196 XMAC_REG_WR(handle, portn, XTXMAC_STAT_MSK_REG, ~iconfig); 2197 2198 break; 2199 default: 2200 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2201 " npi_xmac_tx_iconfig" 2202 " Invalid Input: iconfig <0x%x>", 2203 iconfig)); 2204 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2205 } 2206 2207 return (NPI_SUCCESS); 2208 } 2209 2210 npi_status_t 2211 npi_xmac_rx_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2212 xmac_rx_iconfig_t iconfig) 2213 { 2214 uint64_t val = 0; 2215 2216 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2217 2218 switch (op) { 2219 case ENABLE: 2220 case DISABLE: 2221 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_XMAC_RX_ALL) == 0)); 2222 if ((iconfig == 0) || (iconfig & ~ICFG_XMAC_RX_ALL) != 0) { 2223 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2224 " npi_xmac_rx_iconfig" 2225 " Invalid Input: iconfig <0x%x>", 2226 iconfig)); 2227 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2228 } 2229 XMAC_REG_RD(handle, portn, XRXMAC_STAT_MSK_REG, &val); 2230 if (op == ENABLE) 2231 val &= ~iconfig; 2232 else 2233 val |= iconfig; 2234 XMAC_REG_WR(handle, portn, XRXMAC_STAT_MSK_REG, val); 2235 2236 break; 2237 case INIT: 2238 ASSERT((iconfig & ~ICFG_XMAC_RX_ALL) == 0); 2239 if ((iconfig & ~ICFG_XMAC_RX_ALL) != 0) { 2240 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2241 " npi_xmac_rx_iconfig" 2242 " Invalid Input: iconfig <0x%x>", 2243 iconfig)); 2244 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2245 } 2246 XMAC_REG_WR(handle, portn, XRXMAC_STAT_MSK_REG, ~iconfig); 2247 2248 break; 2249 default: 2250 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2251 " npi_xmac_rx_iconfig" 2252 " Invalid Input: iconfig <0x%x>", 2253 iconfig)); 2254 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2255 } 2256 2257 return (NPI_SUCCESS); 2258 } 2259 2260 npi_status_t 2261 npi_xmac_ctl_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2262 xmac_ctl_iconfig_t iconfig) 2263 { 2264 uint64_t val = 0; 2265 2266 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2267 2268 switch (op) { 2269 case ENABLE: 2270 case DISABLE: 2271 ASSERT((iconfig != 0) && \ 2272 ((iconfig & ~ICFG_XMAC_CTRL_ALL) == 0)); 2273 if ((iconfig == 0) || (iconfig & ~ICFG_XMAC_CTRL_ALL) != 0) { 2274 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2275 " npi_xmac_ctl_iconfig" 2276 " Invalid Input: iconfig <0x%x>", 2277 iconfig)); 2278 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2279 } 2280 XMAC_REG_RD(handle, portn, XMAC_C_S_MSK_REG, &val); 2281 if (op == ENABLE) 2282 val &= ~iconfig; 2283 else 2284 val |= iconfig; 2285 XMAC_REG_WR(handle, portn, XMAC_C_S_MSK_REG, val); 2286 2287 break; 2288 case INIT: 2289 ASSERT((iconfig & ~ICFG_XMAC_CTRL_ALL) == 0); 2290 if ((iconfig & ~ICFG_XMAC_CTRL_ALL) != 0) { 2291 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2292 " npi_xmac_ctl_iconfig" 2293 " Invalid Input: iconfig <0x%x>", 2294 iconfig)); 2295 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2296 } 2297 XMAC_REG_WR(handle, portn, XMAC_C_S_MSK_REG, ~iconfig); 2298 2299 break; 2300 default: 2301 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2302 " npi_xmac_ctl_iconfig" 2303 " Invalid Input: iconfig <0x%x>", 2304 iconfig)); 2305 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2306 } 2307 2308 return (NPI_SUCCESS); 2309 } 2310 2311 npi_status_t 2312 npi_xmac_tx_get_istatus(npi_handle_t handle, uint8_t portn, 2313 xmac_tx_iconfig_t *istatus) 2314 { 2315 uint64_t val; 2316 2317 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2318 2319 XMAC_REG_RD(handle, portn, XTXMAC_STATUS_REG, &val); 2320 *istatus = (uint32_t)val; 2321 2322 return (NPI_SUCCESS); 2323 } 2324 2325 npi_status_t 2326 npi_xmac_rx_get_istatus(npi_handle_t handle, uint8_t portn, 2327 xmac_rx_iconfig_t *istatus) 2328 { 2329 uint64_t val; 2330 2331 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2332 2333 XMAC_REG_RD(handle, portn, XRXMAC_STATUS_REG, &val); 2334 *istatus = (uint32_t)val; 2335 2336 return (NPI_SUCCESS); 2337 } 2338 2339 npi_status_t 2340 npi_xmac_ctl_get_istatus(npi_handle_t handle, uint8_t portn, 2341 xmac_ctl_iconfig_t *istatus) 2342 { 2343 uint64_t val; 2344 2345 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2346 2347 XMAC_REG_RD(handle, portn, XMAC_CTRL_STAT_REG, &val); 2348 *istatus = (uint32_t)val; 2349 2350 return (NPI_SUCCESS); 2351 } 2352 2353 npi_status_t 2354 npi_xmac_xpcs_reset(npi_handle_t handle, uint8_t portn) 2355 { 2356 uint64_t val; 2357 2358 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2359 2360 XPCS_REG_RD(handle, portn, XPCS_CTRL_1_REG, &val); 2361 val |= XPCS_CTRL1_RST; 2362 XPCS_REG_WR(handle, portn, XPCS_CTRL_1_REG, val); 2363 2364 return (NPI_SUCCESS); 2365 } 2366 2367 npi_status_t 2368 npi_xmac_xpcs_enable(npi_handle_t handle, uint8_t portn) 2369 { 2370 uint64_t val; 2371 2372 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2373 2374 XPCS_REG_RD(handle, portn, XPCS_CFG_VENDOR_1_REG, &val); 2375 val |= XPCS_CFG_XPCS_ENABLE; 2376 XPCS_REG_WR(handle, portn, XPCS_CFG_VENDOR_1_REG, val); 2377 2378 return (NPI_SUCCESS); 2379 } 2380 2381 npi_status_t 2382 npi_xmac_xpcs_disable(npi_handle_t handle, uint8_t portn) 2383 { 2384 uint64_t val; 2385 2386 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2387 2388 XPCS_REG_RD(handle, portn, XPCS_CFG_VENDOR_1_REG, &val); 2389 val &= ~XPCS_CFG_XPCS_ENABLE; 2390 XPCS_REG_WR(handle, portn, XPCS_CFG_VENDOR_1_REG, val); 2391 2392 return (NPI_SUCCESS); 2393 } 2394 2395 npi_status_t 2396 npi_xmac_xpcs_read(npi_handle_t handle, uint8_t portn, uint8_t xpcs_reg, 2397 uint32_t *value) 2398 { 2399 uint32_t reg; 2400 uint64_t val; 2401 2402 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2403 2404 switch (xpcs_reg) { 2405 case XPCS_REG_CONTROL1: 2406 reg = XPCS_CTRL_1_REG; 2407 break; 2408 case XPCS_REG_STATUS1: 2409 reg = XPCS_STATUS_1_REG; 2410 break; 2411 case XPCS_REG_DEVICE_ID: 2412 reg = XPCS_DEV_ID_REG; 2413 break; 2414 case XPCS_REG_SPEED_ABILITY: 2415 reg = XPCS_SPEED_ABILITY_REG; 2416 break; 2417 case XPCS_REG_DEVICE_IN_PKG: 2418 reg = XPCS_DEV_IN_PKG_REG; 2419 break; 2420 case XPCS_REG_CONTROL2: 2421 reg = XPCS_CTRL_2_REG; 2422 break; 2423 case XPCS_REG_STATUS2: 2424 reg = XPCS_STATUS_2_REG; 2425 break; 2426 case XPCS_REG_PKG_ID: 2427 reg = XPCS_PKG_ID_REG; 2428 break; 2429 case XPCS_REG_STATUS: 2430 reg = XPCS_STATUS_REG; 2431 break; 2432 case XPCS_REG_TEST_CONTROL: 2433 reg = XPCS_TEST_CTRL_REG; 2434 break; 2435 case XPCS_REG_CONFIG_VENDOR1: 2436 reg = XPCS_CFG_VENDOR_1_REG; 2437 break; 2438 case XPCS_REG_DIAG_VENDOR2: 2439 reg = XPCS_DIAG_VENDOR_2_REG; 2440 break; 2441 case XPCS_REG_MASK1: 2442 reg = XPCS_MASK_1_REG; 2443 break; 2444 case XPCS_REG_PACKET_COUNTER: 2445 reg = XPCS_PKT_CNTR_REG; 2446 break; 2447 case XPCS_REG_TX_STATEMACHINE: 2448 reg = XPCS_TX_STATE_MC_REG; 2449 break; 2450 case XPCS_REG_DESCWERR_COUNTER: 2451 reg = XPCS_DESKEW_ERR_CNTR_REG; 2452 break; 2453 case XPCS_REG_SYMBOL_ERR_L0_1_COUNTER: 2454 reg = XPCS_SYM_ERR_CNTR_L0_L1_REG; 2455 break; 2456 case XPCS_REG_SYMBOL_ERR_L2_3_COUNTER: 2457 reg = XPCS_SYM_ERR_CNTR_L2_L3_REG; 2458 break; 2459 case XPCS_REG_TRAINING_VECTOR: 2460 reg = XPCS_TRAINING_VECTOR_REG; 2461 break; 2462 default: 2463 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2464 " npi_xmac_xpcs_read" 2465 " Invalid Input: xpcs_reg <0x%x>", 2466 xpcs_reg)); 2467 return (NPI_FAILURE | NPI_MAC_REG_INVALID(portn)); 2468 } 2469 XPCS_REG_RD(handle, portn, reg, &val); 2470 *value = val & 0xFFFFFFFF; 2471 2472 return (NPI_SUCCESS); 2473 } 2474 2475 npi_status_t 2476 npi_xmac_xpcs_write(npi_handle_t handle, uint8_t portn, uint8_t xpcs_reg, 2477 uint32_t value) 2478 { 2479 uint32_t reg; 2480 uint64_t val; 2481 2482 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2483 2484 switch (xpcs_reg) { 2485 case XPCS_REG_CONTROL1: 2486 reg = XPCS_CTRL_1_REG; 2487 break; 2488 case XPCS_REG_TEST_CONTROL: 2489 reg = XPCS_TEST_CTRL_REG; 2490 break; 2491 case XPCS_REG_CONFIG_VENDOR1: 2492 reg = XPCS_CFG_VENDOR_1_REG; 2493 break; 2494 case XPCS_REG_DIAG_VENDOR2: 2495 reg = XPCS_DIAG_VENDOR_2_REG; 2496 break; 2497 case XPCS_REG_MASK1: 2498 reg = XPCS_MASK_1_REG; 2499 break; 2500 case XPCS_REG_PACKET_COUNTER: 2501 reg = XPCS_PKT_CNTR_REG; 2502 break; 2503 case XPCS_REG_DESCWERR_COUNTER: 2504 reg = XPCS_DESKEW_ERR_CNTR_REG; 2505 break; 2506 case XPCS_REG_TRAINING_VECTOR: 2507 reg = XPCS_TRAINING_VECTOR_REG; 2508 break; 2509 default: 2510 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2511 " npi_xmac_xpcs_write" 2512 " Invalid Input: xpcs_reg <0x%x>", 2513 xpcs_reg)); 2514 return (NPI_FAILURE | NPI_MAC_PCS_REG_INVALID(portn)); 2515 } 2516 val = value; 2517 2518 XPCS_REG_WR(handle, portn, reg, val); 2519 2520 return (NPI_SUCCESS); 2521 } 2522 2523 npi_status_t 2524 npi_bmac_reset(npi_handle_t handle, uint8_t portn, npi_mac_reset_t mode) 2525 { 2526 uint64_t val = 0; 2527 boolean_t txmac = B_FALSE; 2528 2529 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2530 2531 switch (mode) { 2532 case TX_MAC_RESET: 2533 BMAC_REG_WR(handle, portn, BTXMAC_SW_RST_REG, 0x1); 2534 BMAC_WAIT_REG(handle, portn, BTXMAC_SW_RST_REG, val); 2535 txmac = B_TRUE; 2536 break; 2537 case RX_MAC_RESET: 2538 BMAC_REG_WR(handle, portn, BRXMAC_SW_RST_REG, 0x1); 2539 BMAC_WAIT_REG(handle, portn, BRXMAC_SW_RST_REG, val); 2540 break; 2541 default: 2542 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2543 " npi_bmac_reset" 2544 " Invalid Input: mode <0x%x>", 2545 mode)); 2546 return (NPI_FAILURE | NPI_MAC_RESET_MODE_INVALID(portn)); 2547 } 2548 2549 if (val != 0) { 2550 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2551 " npi_bmac_reset" 2552 " BMAC_RESET HW Error: ret <0x%x>", 2553 val)); 2554 if (txmac) 2555 return (NPI_FAILURE | NPI_TXMAC_RESET_FAILED(portn)); 2556 else 2557 return (NPI_FAILURE | NPI_RXMAC_RESET_FAILED(portn)); 2558 } 2559 2560 return (NPI_SUCCESS); 2561 } 2562 2563 npi_status_t 2564 npi_mac_pcs_reset(npi_handle_t handle, uint8_t portn) 2565 { 2566 /* what to do here ? */ 2567 uint64_t val = 0; 2568 2569 ASSERT(IS_PORT_NUM_VALID(portn)); 2570 2571 PCS_REG_RD(handle, portn, PCS_MII_CTRL_REG, &val); 2572 val |= PCS_MII_RESET; 2573 PCS_REG_WR(handle, portn, PCS_MII_CTRL_REG, val); 2574 2575 return (NPI_SUCCESS); 2576 } 2577 2578 npi_status_t 2579 npi_mac_get_link_status(npi_handle_t handle, uint8_t portn, 2580 boolean_t *link_up) 2581 { 2582 uint64_t val; 2583 2584 ASSERT(IS_PORT_NUM_VALID(portn)); 2585 2586 PCS_REG_RD(handle, portn, PCS_MII_STATUS_REG, &val); 2587 2588 if (val & PCS_MII_STATUS_LINK_STATUS) { 2589 *link_up = B_TRUE; 2590 } else { 2591 *link_up = B_FALSE; 2592 } 2593 2594 return (NPI_SUCCESS); 2595 } 2596 2597 npi_status_t 2598 npi_bmac_tx_config(npi_handle_t handle, config_op_t op, uint8_t portn, 2599 bmac_tx_config_t config) 2600 { 2601 uint64_t val = 0; 2602 2603 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2604 2605 switch (op) { 2606 case ENABLE: 2607 case DISABLE: 2608 ASSERT((config != 0) && ((config & ~CFG_BMAC_TX_ALL) == 0)); 2609 if ((config == 0) || (config & ~CFG_BMAC_TX_ALL) != 0) { 2610 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2611 " npi_bmac_tx_config" 2612 " Invalid Input: config <0x%x>", 2613 config)); 2614 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2615 } 2616 if (op == ENABLE) { 2617 BMAC_REG_RD(handle, portn, TXMAC_CONFIG_REG, &val); 2618 if (config & CFG_BMAC_TX) 2619 val |= MAC_TX_CFG_TXMAC_ENABLE; 2620 if (config & CFG_BMAC_TX_CRC) 2621 val &= ~MAC_TX_CFG_NO_FCS; 2622 BMAC_REG_WR(handle, portn, TXMAC_CONFIG_REG, val); 2623 } else { 2624 BMAC_REG_RD(handle, portn, TXMAC_CONFIG_REG, &val); 2625 if (config & CFG_BMAC_TX) 2626 val &= ~MAC_TX_CFG_TXMAC_ENABLE; 2627 if (config & CFG_BMAC_TX_CRC) 2628 val |= MAC_TX_CFG_NO_FCS; 2629 BMAC_REG_WR(handle, portn, TXMAC_CONFIG_REG, val); 2630 } 2631 break; 2632 case INIT: 2633 ASSERT((config & ~CFG_BMAC_TX_ALL) == 0); 2634 if ((config & ~CFG_BMAC_TX_ALL) != 0) { 2635 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2636 " npi_bmac_tx_config" 2637 " Invalid Input: config <0x%x>", 2638 config)); 2639 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2640 } 2641 BMAC_REG_RD(handle, portn, TXMAC_CONFIG_REG, &val); 2642 if (config & CFG_BMAC_TX) 2643 val |= MAC_TX_CFG_TXMAC_ENABLE; 2644 else 2645 val &= ~MAC_TX_CFG_TXMAC_ENABLE; 2646 if (config & CFG_BMAC_TX_CRC) 2647 val &= ~MAC_TX_CFG_NO_FCS; 2648 else 2649 val |= MAC_TX_CFG_NO_FCS; 2650 BMAC_REG_WR(handle, portn, TXMAC_CONFIG_REG, val); 2651 break; 2652 default: 2653 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2654 " npi_bmac_tx_config" 2655 " Invalid Input: op <0x%x>", 2656 op)); 2657 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2658 } 2659 2660 return (NPI_SUCCESS); 2661 } 2662 2663 npi_status_t 2664 npi_bmac_rx_config(npi_handle_t handle, config_op_t op, uint8_t portn, 2665 bmac_rx_config_t config) 2666 { 2667 uint64_t val = 0; 2668 2669 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2670 2671 switch (op) { 2672 case ENABLE: 2673 case DISABLE: 2674 ASSERT((config != 0) && ((config & ~CFG_BMAC_RX_ALL) == 0)); 2675 if ((config == 0) || (config & ~CFG_BMAC_RX_ALL) != 0) { 2676 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2677 " npi_bmac_rx_config" 2678 " Invalid Input: config <0x%x>", 2679 config)); 2680 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2681 } 2682 if (op == ENABLE) { 2683 BMAC_REG_RD(handle, portn, RXMAC_CONFIG_REG, &val); 2684 if (config & CFG_BMAC_RX) 2685 val |= MAC_RX_CFG_RXMAC_ENABLE; 2686 if (config & CFG_BMAC_RX_STRIP_PAD) 2687 val |= MAC_RX_CFG_STRIP_PAD; 2688 if (config & CFG_BMAC_RX_STRIP_CRC) 2689 val |= MAC_RX_CFG_STRIP_FCS; 2690 if (config & CFG_BMAC_RX_PROMISCUOUS) 2691 val |= MAC_RX_CFG_PROMISC; 2692 if (config & CFG_BMAC_RX_PROMISCUOUSGROUP) 2693 val |= MAC_RX_CFG_PROMISC_GROUP; 2694 if (config & CFG_BMAC_RX_HASH_FILTER) 2695 val |= MAC_RX_CFG_HASH_FILTER_EN; 2696 if (config & CFG_BMAC_RX_ADDR_FILTER) 2697 val |= MAC_RX_CFG_ADDR_FILTER_EN; 2698 if (config & CFG_BMAC_RX_DISCARD_ON_ERR) 2699 val &= ~MAC_RX_CFG_DISABLE_DISCARD; 2700 BMAC_REG_WR(handle, portn, RXMAC_CONFIG_REG, val); 2701 } else { 2702 BMAC_REG_RD(handle, portn, RXMAC_CONFIG_REG, &val); 2703 if (config & CFG_BMAC_RX) 2704 val &= ~MAC_RX_CFG_RXMAC_ENABLE; 2705 if (config & CFG_BMAC_RX_STRIP_PAD) 2706 val &= ~MAC_RX_CFG_STRIP_PAD; 2707 if (config & CFG_BMAC_RX_STRIP_CRC) 2708 val &= ~MAC_RX_CFG_STRIP_FCS; 2709 if (config & CFG_BMAC_RX_PROMISCUOUS) 2710 val &= ~MAC_RX_CFG_PROMISC; 2711 if (config & CFG_BMAC_RX_PROMISCUOUSGROUP) 2712 val &= ~MAC_RX_CFG_PROMISC_GROUP; 2713 if (config & CFG_BMAC_RX_HASH_FILTER) 2714 val &= ~MAC_RX_CFG_HASH_FILTER_EN; 2715 if (config & CFG_BMAC_RX_ADDR_FILTER) 2716 val &= ~MAC_RX_CFG_ADDR_FILTER_EN; 2717 if (config & CFG_BMAC_RX_DISCARD_ON_ERR) 2718 val |= MAC_RX_CFG_DISABLE_DISCARD; 2719 BMAC_REG_WR(handle, portn, RXMAC_CONFIG_REG, val); 2720 } 2721 break; 2722 case INIT: 2723 ASSERT((config & ~CFG_BMAC_RX_ALL) == 0); 2724 if ((config & ~CFG_BMAC_RX_ALL) != 0) { 2725 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2726 " npi_bmac_rx_config" 2727 " Invalid Input: config <0x%x>", 2728 config)); 2729 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2730 } 2731 BMAC_REG_RD(handle, portn, RXMAC_CONFIG_REG, &val); 2732 if (config & CFG_BMAC_RX) 2733 val |= MAC_RX_CFG_RXMAC_ENABLE; 2734 else 2735 val &= ~MAC_RX_CFG_RXMAC_ENABLE; 2736 if (config & CFG_BMAC_RX_STRIP_PAD) 2737 val |= MAC_RX_CFG_STRIP_PAD; 2738 else 2739 val &= ~MAC_RX_CFG_STRIP_PAD; 2740 if (config & CFG_BMAC_RX_STRIP_CRC) 2741 val |= MAC_RX_CFG_STRIP_FCS; 2742 else 2743 val &= ~MAC_RX_CFG_STRIP_FCS; 2744 if (config & CFG_BMAC_RX_PROMISCUOUS) 2745 val |= MAC_RX_CFG_PROMISC; 2746 else 2747 val &= ~MAC_RX_CFG_PROMISC; 2748 if (config & CFG_BMAC_RX_PROMISCUOUSGROUP) 2749 val |= MAC_RX_CFG_PROMISC_GROUP; 2750 else 2751 val &= ~MAC_RX_CFG_PROMISC_GROUP; 2752 if (config & CFG_BMAC_RX_HASH_FILTER) 2753 val |= MAC_RX_CFG_HASH_FILTER_EN; 2754 else 2755 val &= ~MAC_RX_CFG_HASH_FILTER_EN; 2756 if (config & CFG_BMAC_RX_ADDR_FILTER) 2757 val |= MAC_RX_CFG_ADDR_FILTER_EN; 2758 else 2759 val &= ~MAC_RX_CFG_ADDR_FILTER_EN; 2760 if (config & CFG_BMAC_RX_DISCARD_ON_ERR) 2761 val &= ~MAC_RX_CFG_DISABLE_DISCARD; 2762 else 2763 val |= MAC_RX_CFG_DISABLE_DISCARD; 2764 2765 BMAC_REG_WR(handle, portn, RXMAC_CONFIG_REG, val); 2766 break; 2767 default: 2768 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2769 " npi_bmac_rx_config" 2770 " Invalid Input: op <0x%x>", op)); 2771 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2772 } 2773 2774 return (NPI_SUCCESS); 2775 } 2776 2777 npi_status_t 2778 npi_bmac_rx_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2779 bmac_rx_iconfig_t iconfig) 2780 { 2781 uint64_t val = 0; 2782 2783 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2784 2785 switch (op) { 2786 case ENABLE: 2787 case DISABLE: 2788 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_BMAC_RX_ALL) == 0)); 2789 if ((iconfig == 0) || (iconfig & ~ICFG_BMAC_RX_ALL) != 0) { 2790 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2791 " npi_bmac_rx_iconfig" 2792 " Invalid Input: iconfig <0x%x>", 2793 iconfig)); 2794 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2795 } 2796 BMAC_REG_RD(handle, portn, BRXMAC_STAT_MSK_REG, &val); 2797 if (op == ENABLE) 2798 val &= ~iconfig; 2799 else 2800 val |= iconfig; 2801 BMAC_REG_WR(handle, portn, BRXMAC_STAT_MSK_REG, val); 2802 2803 break; 2804 case INIT: 2805 ASSERT((iconfig & ~ICFG_BMAC_RX_ALL) == 0); 2806 if ((iconfig & ~ICFG_BMAC_RX_ALL) != 0) { 2807 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2808 " npi_bmac_rx_iconfig" 2809 " Invalid Input: iconfig <0x%x>", 2810 iconfig)); 2811 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2812 } 2813 BMAC_REG_WR(handle, portn, BRXMAC_STAT_MSK_REG, ~iconfig); 2814 2815 break; 2816 default: 2817 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2818 " npi_bmac_rx_iconfig" 2819 " Invalid Input: iconfig <0x%x>", 2820 iconfig)); 2821 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2822 } 2823 2824 return (NPI_SUCCESS); 2825 } 2826 2827 npi_status_t 2828 npi_bmac_xif_config(npi_handle_t handle, config_op_t op, uint8_t portn, 2829 bmac_xif_config_t config) 2830 { 2831 uint64_t val = 0; 2832 2833 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2834 2835 switch (op) { 2836 case ENABLE: 2837 case DISABLE: 2838 ASSERT((config != 0) && ((config & ~CFG_BMAC_XIF_ALL) == 0)); 2839 if ((config == 0) || (config & ~CFG_BMAC_XIF_ALL) != 0) { 2840 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2841 " npi_bmac_xif_config" 2842 " Invalid Input: config <0x%x>", 2843 config)); 2844 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2845 } 2846 if (op == ENABLE) { 2847 BMAC_REG_RD(handle, portn, MAC_XIF_CONFIG_REG, &val); 2848 if (config & CFG_BMAC_XIF_TX_OUTPUT) 2849 val |= MAC_XIF_TX_OUTPUT_EN; 2850 if (config & CFG_BMAC_XIF_LOOPBACK) 2851 val |= MAC_XIF_MII_INT_LOOPBACK; 2852 if (config & CFG_BMAC_XIF_GMII_MODE) 2853 val |= MAC_XIF_GMII_MODE; 2854 if (config & CFG_BMAC_XIF_LINKLED) 2855 val |= MAC_XIF_LINK_LED; 2856 if (config & CFG_BMAC_XIF_LED_POLARITY) 2857 val |= MAC_XIF_LED_POLARITY; 2858 if (config & CFG_BMAC_XIF_SEL_CLK_25MHZ) 2859 val |= MAC_XIF_SEL_CLK_25MHZ; 2860 BMAC_REG_WR(handle, portn, MAC_XIF_CONFIG_REG, val); 2861 } else { 2862 BMAC_REG_RD(handle, portn, MAC_XIF_CONFIG_REG, &val); 2863 if (config & CFG_BMAC_XIF_TX_OUTPUT) 2864 val &= ~MAC_XIF_TX_OUTPUT_EN; 2865 if (config & CFG_BMAC_XIF_LOOPBACK) 2866 val &= ~MAC_XIF_MII_INT_LOOPBACK; 2867 if (config & CFG_BMAC_XIF_GMII_MODE) 2868 val &= ~MAC_XIF_GMII_MODE; 2869 if (config & CFG_BMAC_XIF_LINKLED) 2870 val &= ~MAC_XIF_LINK_LED; 2871 if (config & CFG_BMAC_XIF_LED_POLARITY) 2872 val &= ~MAC_XIF_LED_POLARITY; 2873 if (config & CFG_BMAC_XIF_SEL_CLK_25MHZ) 2874 val &= ~MAC_XIF_SEL_CLK_25MHZ; 2875 BMAC_REG_WR(handle, portn, MAC_XIF_CONFIG_REG, val); 2876 } 2877 break; 2878 case INIT: 2879 ASSERT((config & ~CFG_BMAC_XIF_ALL) == 0); 2880 if ((config & ~CFG_BMAC_XIF_ALL) != 0) { 2881 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2882 " npi_bmac_xif_config" 2883 " Invalid Input: config <0x%x>", 2884 config)); 2885 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2886 } 2887 BMAC_REG_RD(handle, portn, MAC_XIF_CONFIG_REG, &val); 2888 if (config & CFG_BMAC_XIF_TX_OUTPUT) 2889 val |= MAC_XIF_TX_OUTPUT_EN; 2890 else 2891 val &= ~MAC_XIF_TX_OUTPUT_EN; 2892 if (config & CFG_BMAC_XIF_LOOPBACK) 2893 val |= MAC_XIF_MII_INT_LOOPBACK; 2894 else 2895 val &= ~MAC_XIF_MII_INT_LOOPBACK; 2896 if (config & CFG_BMAC_XIF_GMII_MODE) 2897 val |= MAC_XIF_GMII_MODE; 2898 else 2899 val &= ~MAC_XIF_GMII_MODE; 2900 if (config & CFG_BMAC_XIF_LINKLED) 2901 val |= MAC_XIF_LINK_LED; 2902 else 2903 val &= ~MAC_XIF_LINK_LED; 2904 if (config & CFG_BMAC_XIF_LED_POLARITY) 2905 val |= MAC_XIF_LED_POLARITY; 2906 else 2907 val &= ~MAC_XIF_LED_POLARITY; 2908 if (config & CFG_BMAC_XIF_SEL_CLK_25MHZ) 2909 val |= MAC_XIF_SEL_CLK_25MHZ; 2910 else 2911 val &= ~MAC_XIF_SEL_CLK_25MHZ; 2912 BMAC_REG_WR(handle, portn, MAC_XIF_CONFIG_REG, val); 2913 break; 2914 default: 2915 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2916 " npi_bmac_xif_config" 2917 " Invalid Input: op <0x%x>", 2918 op)); 2919 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2920 } 2921 2922 return (NPI_SUCCESS); 2923 } 2924 2925 npi_status_t 2926 npi_bmac_tx_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2927 bmac_tx_iconfig_t iconfig) 2928 { 2929 uint64_t val = 0; 2930 2931 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2932 2933 switch (op) { 2934 case ENABLE: 2935 case DISABLE: 2936 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_XMAC_TX_ALL) == 0)); 2937 if ((iconfig == 0) || (iconfig & ~ICFG_XMAC_TX_ALL) != 0) { 2938 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2939 " npi_bmac_tx_iconfig" 2940 " Invalid Input: iconfig <0x%x>", 2941 iconfig)); 2942 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2943 } 2944 BMAC_REG_RD(handle, portn, BTXMAC_STAT_MSK_REG, &val); 2945 if (op == ENABLE) 2946 val &= ~iconfig; 2947 else 2948 val |= iconfig; 2949 BMAC_REG_WR(handle, portn, BTXMAC_STAT_MSK_REG, val); 2950 2951 break; 2952 case INIT: 2953 ASSERT((iconfig & ~ICFG_XMAC_TX_ALL) == 0); 2954 if ((iconfig & ~ICFG_XMAC_TX_ALL) != 0) { 2955 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2956 " npi_bmac_tx_iconfig" 2957 " Invalid Input: iconfig <0x%x>", 2958 iconfig)); 2959 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2960 } 2961 BMAC_REG_WR(handle, portn, BTXMAC_STAT_MSK_REG, ~iconfig); 2962 2963 break; 2964 default: 2965 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2966 " npi_bmac_tx_iconfig" 2967 " Invalid Input: iconfig <0x%x>", 2968 iconfig)); 2969 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2970 } 2971 2972 return (NPI_SUCCESS); 2973 } 2974 2975 npi_status_t 2976 npi_bmac_ctl_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2977 bmac_ctl_iconfig_t iconfig) 2978 { 2979 uint64_t val = 0; 2980 2981 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2982 2983 switch (op) { 2984 case ENABLE: 2985 case DISABLE: 2986 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_BMAC_CTL_ALL) == 0)); 2987 if ((iconfig == 0) || (iconfig & ~ICFG_BMAC_CTL_ALL) != 0) { 2988 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2989 " npi_bmac_ctl_iconfig" 2990 " Invalid Input: iconfig <0x%x>", 2991 iconfig)); 2992 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2993 } 2994 BMAC_REG_RD(handle, portn, BMAC_C_S_MSK_REG, &val); 2995 if (op == ENABLE) 2996 val &= ~iconfig; 2997 else 2998 val |= iconfig; 2999 BMAC_REG_WR(handle, portn, BMAC_C_S_MSK_REG, val); 3000 3001 break; 3002 case INIT: 3003 ASSERT((iconfig & ~ICFG_BMAC_RX_ALL) == 0); 3004 if ((iconfig & ~ICFG_BMAC_RX_ALL) != 0) { 3005 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3006 " npi_bmac_ctl_iconfig" 3007 " Invalid Input: iconfig <0x%x>", 3008 iconfig)); 3009 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 3010 } 3011 BMAC_REG_WR(handle, portn, BMAC_C_S_MSK_REG, ~iconfig); 3012 3013 break; 3014 default: 3015 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3016 " npi_bmac_ctl_iconfig" 3017 " Invalid Input: iconfig <0x%x>", 3018 iconfig)); 3019 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 3020 } 3021 3022 return (NPI_SUCCESS); 3023 } 3024 3025 npi_status_t 3026 npi_bmac_tx_get_istatus(npi_handle_t handle, uint8_t portn, 3027 bmac_tx_iconfig_t *istatus) 3028 { 3029 uint64_t val = 0; 3030 3031 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 3032 3033 BMAC_REG_RD(handle, portn, BTXMAC_STATUS_REG, &val); 3034 *istatus = (uint32_t)val; 3035 3036 return (NPI_SUCCESS); 3037 } 3038 3039 npi_status_t 3040 npi_bmac_rx_get_istatus(npi_handle_t handle, uint8_t portn, 3041 bmac_rx_iconfig_t *istatus) 3042 { 3043 uint64_t val = 0; 3044 3045 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 3046 3047 BMAC_REG_RD(handle, portn, BRXMAC_STATUS_REG, &val); 3048 *istatus = (uint32_t)val; 3049 3050 return (NPI_SUCCESS); 3051 } 3052 3053 npi_status_t 3054 npi_bmac_ctl_get_istatus(npi_handle_t handle, uint8_t portn, 3055 bmac_ctl_iconfig_t *istatus) 3056 { 3057 uint64_t val = 0; 3058 3059 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 3060 3061 BMAC_REG_RD(handle, portn, BMAC_CTRL_STAT_REG, &val); 3062 *istatus = (uint32_t)val; 3063 3064 return (NPI_SUCCESS); 3065 } 3066 3067 npi_status_t 3068 npi_mac_mif_mdio_read(npi_handle_t handle, uint8_t portn, uint8_t device, 3069 uint16_t xcvr_reg, uint16_t *value) 3070 { 3071 mif_frame_t frame; 3072 uint_t delay; 3073 3074 frame.value = 0; 3075 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ 3076 frame.bits.w0.op = FRAME45_OP_ADDR; /* Select address */ 3077 frame.bits.w0.phyad = portn; /* Port number */ 3078 frame.bits.w0.regad = device; /* Device number */ 3079 frame.bits.w0.ta_msb = 1; 3080 frame.bits.w0.ta_lsb = 0; 3081 frame.bits.w0.data = xcvr_reg; /* register address */ 3082 3083 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3084 "mdio read port %d addr val=0x%x\n", portn, frame.value)); 3085 3086 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3087 3088 delay = 0; 3089 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); 3090 3091 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3092 "mdio read port %d addr poll=0x%x\n", portn, frame.value)); 3093 3094 if (delay == MIF_DELAY) { 3095 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3096 "mdio read no response1\n")); 3097 } 3098 3099 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ 3100 frame.bits.w0.op = FRAME45_OP_READ; /* Read */ 3101 frame.bits.w0.phyad = portn; /* Port Number */ 3102 frame.bits.w0.regad = device; /* Device Number */ 3103 frame.bits.w0.ta_msb = 1; 3104 frame.bits.w0.ta_lsb = 0; 3105 3106 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3107 "mdio read port %d data frame=0x%x\n", portn, frame.value)); 3108 3109 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3110 3111 delay = 0; 3112 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); 3113 3114 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3115 "mdio read port %d data poll=0x%x\n", portn, frame.value)); 3116 3117 *value = frame.bits.w0.data; 3118 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3119 "mdio read port=%d val=0x%x\n", portn, *value)); 3120 3121 if (delay == MIF_DELAY) { 3122 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3123 "mdio read no response2\n")); 3124 } 3125 3126 return (NPI_SUCCESS); 3127 } 3128 3129 npi_status_t 3130 npi_mac_mif_mii_read(npi_handle_t handle, uint8_t portn, uint8_t xcvr_reg, 3131 uint16_t *value) 3132 { 3133 mif_frame_t frame; 3134 uint_t delay; 3135 3136 frame.bits.w0.st = 0x1; /* Clause 22 */ 3137 frame.bits.w0.op = 0x2; 3138 frame.bits.w0.phyad = portn; 3139 frame.bits.w0.regad = xcvr_reg; 3140 frame.bits.w0.ta_msb = 1; 3141 frame.bits.w0.ta_lsb = 0; 3142 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3143 3144 delay = 0; 3145 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MAX_PIO_RETRIES); 3146 3147 if (delay == MAX_PIO_RETRIES) 3148 return (NPI_FAILURE | NPI_MAC_MII_READ_FAILED(portn)); 3149 3150 *value = frame.bits.w0.data; 3151 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3152 "mif mii read port %d reg=0x%x frame=0x%x\n", portn, 3153 xcvr_reg, frame.bits.w0.data)); 3154 3155 return (NPI_SUCCESS); 3156 } 3157 3158 npi_status_t 3159 npi_mac_mif_mdio_write(npi_handle_t handle, uint8_t portn, uint8_t device, 3160 uint16_t xcvr_reg, uint16_t value) 3161 { 3162 mif_frame_t frame; 3163 uint_t delay; 3164 3165 frame.value = 0; 3166 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ 3167 frame.bits.w0.op = FRAME45_OP_ADDR; /* Select Address */ 3168 frame.bits.w0.phyad = portn; /* Port Number */ 3169 frame.bits.w0.regad = device; /* Device Number */ 3170 frame.bits.w0.ta_msb = 1; 3171 frame.bits.w0.ta_lsb = 0; 3172 frame.bits.w0.data = xcvr_reg; /* register address */ 3173 3174 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3175 3176 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3177 "mdio write port %d addr val=0x%x\n", portn, frame.value)); 3178 3179 delay = 0; 3180 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); 3181 3182 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3183 "mdio write port %d addr poll=0x%x\n", portn, frame.value)); 3184 3185 if (delay == MIF_DELAY) { 3186 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3187 "mdio write no response1\n")); 3188 } 3189 3190 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ 3191 frame.bits.w0.op = FRAME45_OP_WRITE; /* Write */ 3192 frame.bits.w0.phyad = portn; /* Port number */ 3193 frame.bits.w0.regad = device; /* Device number */ 3194 frame.bits.w0.ta_msb = 1; 3195 frame.bits.w0.ta_lsb = 0; 3196 frame.bits.w0.data = value; 3197 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3198 3199 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3200 "mdio write port %d data val=0x%x\n", portn, frame.value)); 3201 3202 delay = 0; 3203 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); 3204 3205 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3206 "mdio write port %d data poll=0x%x\n", portn, frame.value)); 3207 3208 if (delay == MIF_DELAY) { 3209 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3210 "mdio write no response2\n")); 3211 } 3212 3213 return (NPI_SUCCESS); 3214 } 3215 3216 npi_status_t 3217 npi_mac_mif_mii_write(npi_handle_t handle, uint8_t portn, uint8_t xcvr_reg, 3218 uint16_t value) 3219 { 3220 mif_frame_t frame; 3221 uint_t delay; 3222 3223 frame.bits.w0.st = 0x1; /* Clause 22 */ 3224 frame.bits.w0.op = 0x1; 3225 frame.bits.w0.phyad = portn; 3226 frame.bits.w0.regad = xcvr_reg; 3227 frame.bits.w0.ta_msb = 1; 3228 frame.bits.w0.ta_lsb = 0; 3229 frame.bits.w0.data = value; 3230 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3231 3232 delay = 0; 3233 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MAX_PIO_RETRIES); 3234 3235 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3236 "mif mii write port %d reg=0x%x frame=0x%x\n", portn, 3237 xcvr_reg, frame.value)); 3238 3239 if (delay == MAX_PIO_RETRIES) 3240 return (NPI_FAILURE | NPI_MAC_MII_WRITE_FAILED(portn)); 3241 3242 return (NPI_SUCCESS); 3243 } 3244 3245 npi_status_t 3246 npi_mac_pcs_mii_read(npi_handle_t handle, uint8_t portn, uint8_t xcvr_reg, 3247 uint16_t *value) 3248 { 3249 pcs_anar_t pcs_anar; 3250 pcs_anar_t pcs_anlpar; 3251 pcs_stat_t pcs_stat; 3252 pcs_stat_mc_t pcs_stat_mc; 3253 mii_anar_t anar; 3254 mii_anar_t anlpar; 3255 mii_aner_t aner; 3256 mii_esr_t esr; 3257 mii_gsr_t gsr; 3258 uint64_t val = 0; 3259 3260 ASSERT(IS_PORT_NUM_VALID(portn)); 3261 3262 switch (xcvr_reg) { 3263 case MII_BMCR: 3264 PCS_REG_RD(handle, portn, PCS_MII_CTRL_REG, &val); 3265 *value = (uint16_t)val; 3266 break; 3267 case MII_BMSR: 3268 PCS_REG_RD(handle, portn, PCS_MII_STATUS_REG, &val); 3269 pcs_stat.value = val; 3270 PCS_REG_RD(handle, portn, PCS_STATE_MACHINE_REG, &val); 3271 pcs_stat_mc.value = val; 3272 if ((pcs_stat_mc.bits.w0.link_cfg_stat == 0xB) && 3273 (pcs_stat_mc.bits.w0.word_sync != 0)) { 3274 pcs_stat.bits.w0.link_stat = 1; 3275 } else if (pcs_stat_mc.bits.w0.link_cfg_stat != 0xB) { 3276 pcs_stat.bits.w0.link_stat = 0; 3277 } 3278 *value = (uint16_t)pcs_stat.value; 3279 break; 3280 case MII_ESR: 3281 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3282 pcs_anar.value = (uint16_t)val; 3283 esr.value = 0; 3284 esr.bits.link_1000fdx = pcs_anar.bits.w0.full_duplex; 3285 esr.bits.link_1000hdx = pcs_anar.bits.w0.half_duplex; 3286 *value = esr.value; 3287 break; 3288 case MII_ANAR: 3289 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3290 pcs_anar.value = (uint16_t)val; 3291 anar.value = 0; 3292 anar.bits.cap_pause = pcs_anar.bits.w0.pause; 3293 anar.bits.cap_asmpause = pcs_anar.bits.w0.asm_pause; 3294 *value = anar.value; 3295 break; 3296 case MII_ANLPAR: 3297 PCS_REG_RD(handle, portn, PCS_MII_LPA_REG, &val); 3298 pcs_anlpar.value = (uint16_t)val; 3299 anlpar.bits.cap_pause = pcs_anlpar.bits.w0.pause; 3300 anlpar.bits.cap_asmpause = pcs_anlpar.bits.w0.asm_pause; 3301 *value = anlpar.value; 3302 break; 3303 case MII_ANER: 3304 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3305 pcs_anar.value = (uint16_t)val; 3306 aner.value = 0; 3307 aner.bits.lp_an_able = pcs_anar.bits.w0.full_duplex | 3308 pcs_anar.bits.w0.half_duplex; 3309 *value = aner.value; 3310 break; 3311 case MII_GSR: 3312 PCS_REG_RD(handle, portn, PCS_MII_LPA_REG, &val); 3313 pcs_anar.value = (uint16_t)val; 3314 gsr.value = 0; 3315 gsr.bits.link_1000fdx = pcs_anar.bits.w0.full_duplex; 3316 gsr.bits.link_1000hdx = pcs_anar.bits.w0.half_duplex; 3317 *value = gsr.value; 3318 break; 3319 default: 3320 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3321 " npi_mac_pcs_mii_read" 3322 " Invalid Input: xcvr_reg <0x%x>", 3323 xcvr_reg)); 3324 return (NPI_FAILURE | NPI_MAC_REG_INVALID(portn)); 3325 } 3326 3327 return (NPI_SUCCESS); 3328 } 3329 3330 npi_status_t 3331 npi_mac_pcs_mii_write(npi_handle_t handle, uint8_t portn, uint8_t xcvr_reg, 3332 uint16_t value) 3333 { 3334 pcs_anar_t pcs_anar; 3335 mii_anar_t anar; 3336 mii_gcr_t gcr; 3337 uint64_t val; 3338 3339 ASSERT(IS_PORT_NUM_VALID(portn)); 3340 3341 switch (xcvr_reg) { 3342 case MII_BMCR: 3343 val = (uint16_t)value; 3344 PCS_REG_WR(handle, portn, PCS_MII_CTRL_REG, val); 3345 break; 3346 case MII_ANAR: 3347 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3348 pcs_anar.value = (uint16_t)val; 3349 anar.value = value; 3350 pcs_anar.bits.w0.asm_pause = anar.bits.cap_asmpause; 3351 pcs_anar.bits.w0.pause = anar.bits.cap_pause; 3352 val = pcs_anar.value; 3353 PCS_REG_WR(handle, portn, PCS_MII_ADVERT_REG, val); 3354 break; 3355 case MII_GCR: 3356 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3357 pcs_anar.value = (uint16_t)val; 3358 gcr.value = value; 3359 pcs_anar.bits.w0.full_duplex = gcr.bits.link_1000fdx; 3360 pcs_anar.bits.w0.half_duplex = gcr.bits.link_1000hdx; 3361 val = pcs_anar.value; 3362 PCS_REG_WR(handle, portn, PCS_MII_ADVERT_REG, val); 3363 break; 3364 default: 3365 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3366 " npi_mac_pcs_mii_write" 3367 " Invalid Input: xcvr_reg <0x%x>", 3368 xcvr_reg)); 3369 return (NPI_FAILURE | NPI_MAC_REG_INVALID(portn)); 3370 } 3371 3372 return (NPI_SUCCESS); 3373 } 3374 3375 npi_status_t 3376 npi_mac_mif_link_intr_enable(npi_handle_t handle, uint8_t portn, 3377 uint8_t xcvr_reg, uint16_t mask) 3378 { 3379 mif_cfg_t mif_cfg; 3380 3381 ASSERT(IS_PORT_NUM_VALID(portn)); 3382 3383 ASSERT(xcvr_reg <= NXGE_MAX_MII_REGS); 3384 if (xcvr_reg > NXGE_MAX_MII_REGS) { 3385 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3386 " npi_mac_mif_link_intr_enable" 3387 " Invalid Input: xcvr_reg <0x%x>", 3388 xcvr_reg)); 3389 return (NPI_FAILURE | NPI_MAC_REG_INVALID(portn)); 3390 } 3391 3392 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.value); 3393 3394 mif_cfg.bits.w0.phy_addr = portn; /* Port number */ 3395 mif_cfg.bits.w0.reg_addr = xcvr_reg; /* Register address */ 3396 mif_cfg.bits.w0.indirect_md = 0; /* Clause 22 */ 3397 mif_cfg.bits.w0.poll_en = 1; 3398 3399 MIF_REG_WR(handle, MIF_MASK_REG, ~mask); 3400 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.value); 3401 3402 NXGE_DELAY(20); 3403 3404 return (NPI_SUCCESS); 3405 } 3406 3407 npi_status_t 3408 npi_mac_mif_mdio_link_intr_enable(npi_handle_t handle, uint8_t portn, 3409 uint8_t device, uint16_t xcvr_reg, uint16_t mask) 3410 { 3411 mif_cfg_t mif_cfg; 3412 mif_frame_t frame; 3413 uint_t delay; 3414 3415 ASSERT(IS_PORT_NUM_VALID(portn)); 3416 3417 frame.bits.w0.st = 0; /* Clause 45 */ 3418 frame.bits.w0.op = 0; /* Select address */ 3419 frame.bits.w0.phyad = portn; /* Port number */ 3420 frame.bits.w0.regad = device; /* Device number */ 3421 frame.bits.w0.ta_msb = 1; 3422 frame.bits.w0.ta_lsb = 0; 3423 frame.bits.w0.data = xcvr_reg; /* register address */ 3424 3425 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3426 3427 delay = 0; 3428 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MAX_PIO_RETRIES); 3429 if (delay == MAX_PIO_RETRIES) 3430 return (NPI_FAILURE); 3431 3432 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.value); 3433 3434 mif_cfg.bits.w0.phy_addr = portn; /* Port number */ 3435 mif_cfg.bits.w0.reg_addr = device; /* Register address */ 3436 mif_cfg.bits.w0.indirect_md = 1; /* Clause 45 */ 3437 mif_cfg.bits.w0.poll_en = 1; 3438 3439 MIF_REG_WR(handle, MIF_MASK_REG, ~mask); 3440 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.value); 3441 3442 NXGE_DELAY(20); 3443 3444 return (NPI_SUCCESS); 3445 } 3446 3447 void 3448 npi_mac_mif_set_indirect_mode(npi_handle_t handle, boolean_t on_off) 3449 { 3450 mif_cfg_t mif_cfg; 3451 3452 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.value); 3453 mif_cfg.bits.w0.indirect_md = on_off; 3454 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.value); 3455 } 3456 3457 void 3458 npi_mac_mif_set_atca_mode(npi_handle_t handle, boolean_t on_off) 3459 { 3460 mif_cfg_t mif_cfg; 3461 3462 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.value); 3463 mif_cfg.bits.w0.atca_ge = on_off; 3464 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.value); 3465 } 3466 3467 npi_status_t 3468 npi_bmac_send_pause(npi_handle_t handle, uint8_t portn, uint16_t pause_time) 3469 { 3470 uint64_t val; 3471 3472 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 3473 3474 val = MAC_SEND_PAUSE_SEND | pause_time; 3475 BMAC_REG_WR(handle, portn, MAC_SEND_PAUSE_REG, val); 3476 3477 return (NPI_SUCCESS); 3478 } 3479 3480 npi_status_t 3481 npi_xmac_xif_led(npi_handle_t handle, uint8_t portn, boolean_t on_off) 3482 { 3483 uint64_t val = 0; 3484 3485 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 3486 3487 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 3488 3489 if (on_off) { 3490 val |= XMAC_XIF_LED_POLARITY; 3491 val &= ~XMAC_XIF_FORCE_LED_ON; 3492 } else { 3493 val &= ~XMAC_XIF_LED_POLARITY; 3494 val |= XMAC_XIF_FORCE_LED_ON; 3495 } 3496 3497 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 3498 3499 return (NPI_SUCCESS); 3500 } 3501 3502 npi_status_t 3503 npi_xmac_zap_tx_counters(npi_handle_t handle, uint8_t portn) 3504 { 3505 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 3506 3507 XMAC_REG_WR(handle, portn, XTXMAC_FRM_CNT_REG, 0); 3508 XMAC_REG_WR(handle, portn, XTXMAC_BYTE_CNT_REG, 0); 3509 3510 return (NPI_SUCCESS); 3511 } 3512 3513 npi_status_t 3514 npi_xmac_zap_rx_counters(npi_handle_t handle, uint8_t portn) 3515 { 3516 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 3517 3518 XMAC_REG_WR(handle, portn, XRXMAC_BT_CNT_REG, 0); 3519 XMAC_REG_WR(handle, portn, XRXMAC_BC_FRM_CNT_REG, 0); 3520 XMAC_REG_WR(handle, portn, XRXMAC_MC_FRM_CNT_REG, 0); 3521 XMAC_REG_WR(handle, portn, XRXMAC_FRAG_CNT_REG, 0); 3522 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT1_REG, 0); 3523 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT2_REG, 0); 3524 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT3_REG, 0); 3525 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT4_REG, 0); 3526 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT5_REG, 0); 3527 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT6_REG, 0); 3528 XMAC_REG_WR(handle, portn, XRXMAC_MPSZER_CNT_REG, 0); 3529 XMAC_REG_WR(handle, portn, XRXMAC_CRC_ER_CNT_REG, 0); 3530 XMAC_REG_WR(handle, portn, XRXMAC_CD_VIO_CNT_REG, 0); 3531 XMAC_REG_WR(handle, portn, XRXMAC_AL_ER_CNT_REG, 0); 3532 XMAC_REG_WR(handle, portn, XMAC_LINK_FLT_CNT_REG, 0); 3533 3534 return (NPI_SUCCESS); 3535 } 3536