1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <npi_mac.h> 29 30 #define MIF_DELAY 500 31 32 #define MAX_FRAME_SZ1 0x5EE 33 #define MAX_FRAME_SZ2 0x5F6 34 #define MAX_FRAME_SZ3 0x7D6 35 #define MAX_FRAME_SZ4 0x232E 36 #define MAX_FRAME_SZ5 0x2406 37 38 #define XMAC_WAIT_REG(handle, portn, reg, val) {\ 39 uint32_t cnt = MAX_PIO_RETRIES;\ 40 do {\ 41 NXGE_DELAY(MAC_RESET_WAIT);\ 42 XMAC_REG_RD(handle, portn, reg, &val);\ 43 cnt--;\ 44 } while (((val & 0x3) != 0) && (cnt > 0));\ 45 } 46 47 #define BMAC_WAIT_REG(handle, portn, reg, val) {\ 48 uint32_t cnt = MAX_PIO_RETRIES;\ 49 do {\ 50 NXGE_DELAY(MAC_RESET_WAIT);\ 51 BMAC_REG_RD(handle, portn, reg, &val);\ 52 cnt--;\ 53 } while (((val & 0x3) != 0) && (cnt > 0));\ 54 } 55 56 #define MIF_WAIT_REG(handle, m_frame, t_delay, interval, max_delay) { \ 57 do { \ 58 NXGE_DELAY(interval); \ 59 MIF_REG_RD(handle, MIF_OUTPUT_FRAME_REG, &m_frame.value); \ 60 t_delay++; \ 61 } while ((m_frame.bits.w0.ta_lsb == 0) && t_delay < max_delay); \ 62 } 63 64 uint64_t xmac_offset[] = { 65 XTXMAC_SW_RST_REG, 66 XRXMAC_SW_RST_REG, 67 XTXMAC_STATUS_REG, 68 XRXMAC_STATUS_REG, 69 XMAC_CTRL_STAT_REG, 70 XTXMAC_STAT_MSK_REG, 71 XRXMAC_STAT_MSK_REG, 72 XMAC_C_S_MSK_REG, 73 XMAC_CONFIG_REG, 74 XMAC_IPG_REG, 75 XMAC_MIN_REG, 76 XMAC_MAX_REG, 77 XMAC_ADDR0_REG, 78 XMAC_ADDR1_REG, 79 XMAC_ADDR2_REG, 80 XRXMAC_BT_CNT_REG, 81 XRXMAC_BC_FRM_CNT_REG, 82 XRXMAC_MC_FRM_CNT_REG, 83 XRXMAC_FRAG_CNT_REG, 84 XRXMAC_HIST_CNT1_REG, 85 XRXMAC_HIST_CNT2_REG, 86 XRXMAC_HIST_CNT3_REG, 87 XRXMAC_HIST_CNT4_REG, 88 XRXMAC_HIST_CNT5_REG, 89 XRXMAC_HIST_CNT6_REG, 90 XRXMAC_MPSZER_CNT_REG, 91 XRXMAC_CRC_ER_CNT_REG, 92 XRXMAC_CD_VIO_CNT_REG, 93 XRXMAC_AL_ER_CNT_REG, 94 XTXMAC_FRM_CNT_REG, 95 XTXMAC_BYTE_CNT_REG, 96 XMAC_LINK_FLT_CNT_REG, 97 XRXMAC_HIST_CNT7_REG, 98 XMAC_SM_REG, 99 XMAC_INTERN1_REG, 100 XMAC_ADDR_CMPEN_REG, 101 XMAC_ADDR3_REG, 102 XMAC_ADDR4_REG, 103 XMAC_ADDR5_REG, 104 XMAC_ADDR6_REG, 105 XMAC_ADDR7_REG, 106 XMAC_ADDR8_REG, 107 XMAC_ADDR9_REG, 108 XMAC_ADDR10_REG, 109 XMAC_ADDR11_REG, 110 XMAC_ADDR12_REG, 111 XMAC_ADDR13_REG, 112 XMAC_ADDR14_REG, 113 XMAC_ADDR15_REG, 114 XMAC_ADDR16_REG, 115 XMAC_ADDR17_REG, 116 XMAC_ADDR18_REG, 117 XMAC_ADDR19_REG, 118 XMAC_ADDR20_REG, 119 XMAC_ADDR21_REG, 120 XMAC_ADDR22_REG, 121 XMAC_ADDR23_REG, 122 XMAC_ADDR24_REG, 123 XMAC_ADDR25_REG, 124 XMAC_ADDR26_REG, 125 XMAC_ADDR27_REG, 126 XMAC_ADDR28_REG, 127 XMAC_ADDR29_REG, 128 XMAC_ADDR30_REG, 129 XMAC_ADDR31_REG, 130 XMAC_ADDR32_REG, 131 XMAC_ADDR33_REG, 132 XMAC_ADDR34_REG, 133 XMAC_ADDR35_REG, 134 XMAC_ADDR36_REG, 135 XMAC_ADDR37_REG, 136 XMAC_ADDR38_REG, 137 XMAC_ADDR39_REG, 138 XMAC_ADDR40_REG, 139 XMAC_ADDR41_REG, 140 XMAC_ADDR42_REG, 141 XMAC_ADDR43_REG, 142 XMAC_ADDR44_REG, 143 XMAC_ADDR45_REG, 144 XMAC_ADDR46_REG, 145 XMAC_ADDR47_REG, 146 XMAC_ADDR48_REG, 147 XMAC_ADDR49_REG, 148 XMAC_ADDR50_REG, 149 XMAC_ADDR_FILT0_REG, 150 XMAC_ADDR_FILT1_REG, 151 XMAC_ADDR_FILT2_REG, 152 XMAC_ADDR_FILT12_MASK_REG, 153 XMAC_ADDR_FILT0_MASK_REG, 154 XMAC_HASH_TBL0_REG, 155 XMAC_HASH_TBL1_REG, 156 XMAC_HASH_TBL2_REG, 157 XMAC_HASH_TBL3_REG, 158 XMAC_HASH_TBL4_REG, 159 XMAC_HASH_TBL5_REG, 160 XMAC_HASH_TBL6_REG, 161 XMAC_HASH_TBL7_REG, 162 XMAC_HASH_TBL8_REG, 163 XMAC_HASH_TBL9_REG, 164 XMAC_HASH_TBL10_REG, 165 XMAC_HASH_TBL11_REG, 166 XMAC_HASH_TBL12_REG, 167 XMAC_HASH_TBL13_REG, 168 XMAC_HASH_TBL14_REG, 169 XMAC_HASH_TBL15_REG, 170 XMAC_HOST_INF0_REG, 171 XMAC_HOST_INF1_REG, 172 XMAC_HOST_INF2_REG, 173 XMAC_HOST_INF3_REG, 174 XMAC_HOST_INF4_REG, 175 XMAC_HOST_INF5_REG, 176 XMAC_HOST_INF6_REG, 177 XMAC_HOST_INF7_REG, 178 XMAC_HOST_INF8_REG, 179 XMAC_HOST_INF9_REG, 180 XMAC_HOST_INF10_REG, 181 XMAC_HOST_INF11_REG, 182 XMAC_HOST_INF12_REG, 183 XMAC_HOST_INF13_REG, 184 XMAC_HOST_INF14_REG, 185 XMAC_HOST_INF15_REG, 186 XMAC_HOST_INF16_REG, 187 XMAC_HOST_INF17_REG, 188 XMAC_HOST_INF18_REG, 189 XMAC_HOST_INF19_REG, 190 XMAC_PA_DATA0_REG, 191 XMAC_PA_DATA1_REG, 192 XMAC_DEBUG_SEL_REG, 193 XMAC_TRAINING_VECT_REG, 194 }; 195 196 const char *xmac_name[] = { 197 "XTXMAC_SW_RST_REG", 198 "XRXMAC_SW_RST_REG", 199 "XTXMAC_STATUS_REG", 200 "XRXMAC_STATUS_REG", 201 "XMAC_CTRL_STAT_REG", 202 "XTXMAC_STAT_MSK_REG", 203 "XRXMAC_STAT_MSK_REG", 204 "XMAC_C_S_MSK_REG", 205 "XMAC_CONFIG_REG", 206 "XMAC_IPG_REG", 207 "XMAC_MIN_REG", 208 "XMAC_MAX_REG", 209 "XMAC_ADDR0_REG", 210 "XMAC_ADDR1_REG", 211 "XMAC_ADDR2_REG", 212 "XRXMAC_BT_CNT_REG", 213 "XRXMAC_BC_FRM_CNT_REG", 214 "XRXMAC_MC_FRM_CNT_REG", 215 "XRXMAC_FRAG_CNT_REG", 216 "XRXMAC_HIST_CNT1_REG", 217 "XRXMAC_HIST_CNT2_REG", 218 "XRXMAC_HIST_CNT3_REG", 219 "XRXMAC_HIST_CNT4_REG", 220 "XRXMAC_HIST_CNT5_REG", 221 "XRXMAC_HIST_CNT6_REG", 222 "XRXMAC_MPSZER_CNT_REG", 223 "XRXMAC_CRC_ER_CNT_REG", 224 "XRXMAC_CD_VIO_CNT_REG", 225 "XRXMAC_AL_ER_CNT_REG", 226 "XTXMAC_FRM_CNT_REG", 227 "XTXMAC_BYTE_CNT_REG", 228 "XMAC_LINK_FLT_CNT_REG", 229 "XRXMAC_HIST_CNT7_REG", 230 "XMAC_SM_REG", 231 "XMAC_INTERN1_REG", 232 "XMAC_ADDR_CMPEN_REG", 233 "XMAC_ADDR3_REG", 234 "XMAC_ADDR4_REG", 235 "XMAC_ADDR5_REG", 236 "XMAC_ADDR6_REG", 237 "XMAC_ADDR7_REG", 238 "XMAC_ADDR8_REG", 239 "XMAC_ADDR9_REG", 240 "XMAC_ADDR10_REG", 241 "XMAC_ADDR11_REG", 242 "XMAC_ADDR12_REG", 243 "XMAC_ADDR13_REG", 244 "XMAC_ADDR14_REG", 245 "XMAC_ADDR15_REG", 246 "XMAC_ADDR16_REG", 247 "XMAC_ADDR17_REG", 248 "XMAC_ADDR18_REG", 249 "XMAC_ADDR19_REG", 250 "XMAC_ADDR20_REG", 251 "XMAC_ADDR21_REG", 252 "XMAC_ADDR22_REG", 253 "XMAC_ADDR23_REG", 254 "XMAC_ADDR24_REG", 255 "XMAC_ADDR25_REG", 256 "XMAC_ADDR26_REG", 257 "XMAC_ADDR27_REG", 258 "XMAC_ADDR28_REG", 259 "XMAC_ADDR29_REG", 260 "XMAC_ADDR30_REG", 261 "XMAC_ADDR31_REG", 262 "XMAC_ADDR32_REG", 263 "XMAC_ADDR33_REG", 264 "XMAC_ADDR34_REG", 265 "XMAC_ADDR35_REG", 266 "XMAC_ADDR36_REG", 267 "XMAC_ADDR37_REG", 268 "XMAC_ADDR38_REG", 269 "XMAC_ADDR39_REG", 270 "XMAC_ADDR40_REG", 271 "XMAC_ADDR41_REG", 272 "XMAC_ADDR42_REG", 273 "XMAC_ADDR43_REG", 274 "XMAC_ADDR44_REG", 275 "XMAC_ADDR45_REG", 276 "XMAC_ADDR46_REG", 277 "XMAC_ADDR47_REG", 278 "XMAC_ADDR48_REG", 279 "XMAC_ADDR49_REG", 280 "XMAC_ADDR50_RE", 281 "XMAC_ADDR_FILT0_REG", 282 "XMAC_ADDR_FILT1_REG", 283 "XMAC_ADDR_FILT2_REG", 284 "XMAC_ADDR_FILT12_MASK_REG", 285 "XMAC_ADDR_FILT0_MASK_REG", 286 "XMAC_HASH_TBL0_REG", 287 "XMAC_HASH_TBL1_REG", 288 "XMAC_HASH_TBL2_REG", 289 "XMAC_HASH_TBL3_REG", 290 "XMAC_HASH_TBL4_REG", 291 "XMAC_HASH_TBL5_REG", 292 "XMAC_HASH_TBL6_REG", 293 "XMAC_HASH_TBL7_REG", 294 "XMAC_HASH_TBL8_REG", 295 "XMAC_HASH_TBL9_REG", 296 "XMAC_HASH_TBL10_REG", 297 "XMAC_HASH_TBL11_REG", 298 "XMAC_HASH_TBL12_REG", 299 "XMAC_HASH_TBL13_REG", 300 "XMAC_HASH_TBL14_REG", 301 "XMAC_HASH_TBL15_REG", 302 "XMAC_HOST_INF0_REG", 303 "XMAC_HOST_INF1_REG", 304 "XMAC_HOST_INF2_REG", 305 "XMAC_HOST_INF3_REG", 306 "XMAC_HOST_INF4_REG", 307 "XMAC_HOST_INF5_REG", 308 "XMAC_HOST_INF6_REG", 309 "XMAC_HOST_INF7_REG", 310 "XMAC_HOST_INF8_REG", 311 "XMAC_HOST_INF9_REG", 312 "XMAC_HOST_INF10_REG", 313 "XMAC_HOST_INF11_REG", 314 "XMAC_HOST_INF12_REG", 315 "XMAC_HOST_INF13_REG", 316 "XMAC_HOST_INF14_REG", 317 "XMAC_HOST_INF15_REG", 318 "XMAC_HOST_INF16_REG", 319 "XMAC_HOST_INF17_REG", 320 "XMAC_HOST_INF18_REG", 321 "XMAC_HOST_INF19_REG", 322 "XMAC_PA_DATA0_REG", 323 "XMAC_PA_DATA1_REG", 324 "XMAC_DEBUG_SEL_REG", 325 "XMAC_TRAINING_VECT_REG", 326 }; 327 328 uint64_t bmac_offset[] = { 329 BTXMAC_SW_RST_REG, 330 BRXMAC_SW_RST_REG, 331 MAC_SEND_PAUSE_REG, 332 BTXMAC_STATUS_REG, 333 BRXMAC_STATUS_REG, 334 BMAC_CTRL_STAT_REG, 335 BTXMAC_STAT_MSK_REG, 336 BRXMAC_STAT_MSK_REG, 337 BMAC_C_S_MSK_REG, 338 TXMAC_CONFIG_REG, 339 RXMAC_CONFIG_REG, 340 MAC_CTRL_CONFIG_REG, 341 MAC_XIF_CONFIG_REG, 342 BMAC_MIN_REG, 343 BMAC_MAX_REG, 344 MAC_PA_SIZE_REG, 345 MAC_CTRL_TYPE_REG, 346 BMAC_ADDR0_REG, 347 BMAC_ADDR1_REG, 348 BMAC_ADDR2_REG, 349 BMAC_ADDR3_REG, 350 BMAC_ADDR4_REG, 351 BMAC_ADDR5_REG, 352 BMAC_ADDR6_REG, 353 BMAC_ADDR7_REG, 354 BMAC_ADDR8_REG, 355 BMAC_ADDR9_REG, 356 BMAC_ADDR10_REG, 357 BMAC_ADDR11_REG, 358 BMAC_ADDR12_REG, 359 BMAC_ADDR13_REG, 360 BMAC_ADDR14_REG, 361 BMAC_ADDR15_REG, 362 BMAC_ADDR16_REG, 363 BMAC_ADDR17_REG, 364 BMAC_ADDR18_REG, 365 BMAC_ADDR19_REG, 366 BMAC_ADDR20_REG, 367 BMAC_ADDR21_REG, 368 BMAC_ADDR22_REG, 369 BMAC_ADDR23_REG, 370 MAC_FC_ADDR0_REG, 371 MAC_FC_ADDR1_REG, 372 MAC_FC_ADDR2_REG, 373 MAC_ADDR_FILT0_REG, 374 MAC_ADDR_FILT1_REG, 375 MAC_ADDR_FILT2_REG, 376 MAC_ADDR_FILT12_MASK_REG, 377 MAC_ADDR_FILT00_MASK_REG, 378 MAC_HASH_TBL0_REG, 379 MAC_HASH_TBL1_REG, 380 MAC_HASH_TBL2_REG, 381 MAC_HASH_TBL3_REG, 382 MAC_HASH_TBL4_REG, 383 MAC_HASH_TBL5_REG, 384 MAC_HASH_TBL6_REG, 385 MAC_HASH_TBL7_REG, 386 MAC_HASH_TBL8_REG, 387 MAC_HASH_TBL9_REG, 388 MAC_HASH_TBL10_REG, 389 MAC_HASH_TBL11_REG, 390 MAC_HASH_TBL12_REG, 391 MAC_HASH_TBL13_REG, 392 MAC_HASH_TBL14_REG, 393 MAC_HASH_TBL15_REG, 394 RXMAC_FRM_CNT_REG, 395 MAC_LEN_ER_CNT_REG, 396 BMAC_AL_ER_CNT_REG, 397 BMAC_CRC_ER_CNT_REG, 398 BMAC_CD_VIO_CNT_REG, 399 BMAC_SM_REG, 400 BMAC_ALTAD_CMPEN_REG, 401 BMAC_HOST_INF0_REG, 402 BMAC_HOST_INF1_REG, 403 BMAC_HOST_INF2_REG, 404 BMAC_HOST_INF3_REG, 405 BMAC_HOST_INF4_REG, 406 BMAC_HOST_INF5_REG, 407 BMAC_HOST_INF6_REG, 408 BMAC_HOST_INF7_REG, 409 BMAC_HOST_INF8_REG, 410 BTXMAC_BYTE_CNT_REG, 411 BTXMAC_FRM_CNT_REG, 412 BRXMAC_BYTE_CNT_REG, 413 }; 414 415 const char *bmac_name[] = { 416 "BTXMAC_SW_RST_REG", 417 "BRXMAC_SW_RST_REG", 418 "MAC_SEND_PAUSE_REG", 419 "BTXMAC_STATUS_REG", 420 "BRXMAC_STATUS_REG", 421 "BMAC_CTRL_STAT_REG", 422 "BTXMAC_STAT_MSK_REG", 423 "BRXMAC_STAT_MSK_REG", 424 "BMAC_C_S_MSK_REG", 425 "TXMAC_CONFIG_REG", 426 "RXMAC_CONFIG_REG", 427 "MAC_CTRL_CONFIG_REG", 428 "MAC_XIF_CONFIG_REG", 429 "BMAC_MIN_REG", 430 "BMAC_MAX_REG", 431 "MAC_PA_SIZE_REG", 432 "MAC_CTRL_TYPE_REG", 433 "BMAC_ADDR0_REG", 434 "BMAC_ADDR1_REG", 435 "BMAC_ADDR2_REG", 436 "BMAC_ADDR3_REG", 437 "BMAC_ADDR4_REG", 438 "BMAC_ADDR5_REG", 439 "BMAC_ADDR6_REG", 440 "BMAC_ADDR7_REG", 441 "BMAC_ADDR8_REG", 442 "BMAC_ADDR9_REG", 443 "BMAC_ADDR10_REG", 444 "BMAC_ADDR11_REG", 445 "BMAC_ADDR12_REG", 446 "BMAC_ADDR13_REG", 447 "BMAC_ADDR14_REG", 448 "BMAC_ADDR15_REG", 449 "BMAC_ADDR16_REG", 450 "BMAC_ADDR17_REG", 451 "BMAC_ADDR18_REG", 452 "BMAC_ADDR19_REG", 453 "BMAC_ADDR20_REG", 454 "BMAC_ADDR21_REG", 455 "BMAC_ADDR22_REG", 456 "BMAC_ADDR23_REG", 457 "MAC_FC_ADDR0_REG", 458 "MAC_FC_ADDR1_REG", 459 "MAC_FC_ADDR2_REG", 460 "MAC_ADDR_FILT0_REG", 461 "MAC_ADDR_FILT1_REG", 462 "MAC_ADDR_FILT2_REG", 463 "MAC_ADDR_FILT12_MASK_REG", 464 "MAC_ADDR_FILT00_MASK_REG", 465 "MAC_HASH_TBL0_REG", 466 "MAC_HASH_TBL1_REG", 467 "MAC_HASH_TBL2_REG", 468 "MAC_HASH_TBL3_REG", 469 "MAC_HASH_TBL4_REG", 470 "MAC_HASH_TBL5_REG", 471 "MAC_HASH_TBL6_REG", 472 "MAC_HASH_TBL7_REG", 473 "MAC_HASH_TBL8_REG", 474 "MAC_HASH_TBL9_REG", 475 "MAC_HASH_TBL10_REG", 476 "MAC_HASH_TBL11_REG", 477 "MAC_HASH_TBL12_REG", 478 "MAC_HASH_TBL13_REG", 479 "MAC_HASH_TBL14_REG", 480 "MAC_HASH_TBL15_REG", 481 "RXMAC_FRM_CNT_REG", 482 "MAC_LEN_ER_CNT_REG", 483 "BMAC_AL_ER_CNT_REG", 484 "BMAC_CRC_ER_CNT_REG", 485 "BMAC_CD_VIO_CNT_REG", 486 "BMAC_SM_REG", 487 "BMAC_ALTAD_CMPEN_REG", 488 "BMAC_HOST_INF0_REG", 489 "BMAC_HOST_INF1_REG", 490 "BMAC_HOST_INF2_REG", 491 "BMAC_HOST_INF3_REG", 492 "BMAC_HOST_INF4_REG", 493 "BMAC_HOST_INF5_REG", 494 "BMAC_HOST_INF6_REG", 495 "BMAC_HOST_INF7_REG", 496 "BMAC_HOST_INF8_REG", 497 "BTXMAC_BYTE_CNT_REG", 498 "BTXMAC_FRM_CNT_REG", 499 "BRXMAC_BYTE_CNT_REG", 500 }; 501 502 npi_status_t 503 npi_mac_dump_regs(npi_handle_t handle, uint8_t port) 504 { 505 506 uint64_t value; 507 int num_regs, i; 508 509 ASSERT(IS_PORT_NUM_VALID(port)); 510 511 switch (port) { 512 case 0: 513 case 1: 514 num_regs = sizeof (xmac_offset) / sizeof (uint64_t); 515 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 516 "\nXMAC Register Dump for port %d\n", 517 port)); 518 for (i = 0; i < num_regs; i++) { 519 XMAC_REG_RD(handle, port, xmac_offset[i], &value); 520 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 521 "%08llx %s\t %08llx \n", 522 (XMAC_REG_ADDR((port), (xmac_offset[i]))), 523 xmac_name[i], value)); 524 } 525 526 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 527 "\n XMAC Register Dump for port %d done\n", 528 port)); 529 break; 530 531 case 2: 532 case 3: 533 num_regs = sizeof (bmac_offset) / sizeof (uint64_t); 534 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 535 "\nBMAC Register Dump for port %d\n", 536 port)); 537 for (i = 0; i < num_regs; i++) { 538 BMAC_REG_RD(handle, port, bmac_offset[i], &value); 539 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 540 "%08llx %s\t %08llx \n", 541 (BMAC_REG_ADDR((port), (bmac_offset[i]))), 542 bmac_name[i], value)); 543 } 544 545 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 546 "\n BMAC Register Dump for port %d done\n", 547 port)); 548 break; 549 } 550 551 return (NPI_SUCCESS); 552 } 553 554 npi_status_t 555 npi_mac_pcs_link_intr_enable(npi_handle_t handle, uint8_t portn) 556 { 557 pcs_cfg_t pcs_cfg; 558 559 ASSERT(IS_PORT_NUM_VALID(portn)); 560 561 PCS_REG_RD(handle, portn, PCS_CONFIG_REG, &pcs_cfg.value); 562 pcs_cfg.bits.w0.mask = 0; 563 PCS_REG_WR(handle, portn, PCS_CONFIG_REG, pcs_cfg.value); 564 565 return (NPI_SUCCESS); 566 } 567 568 npi_status_t 569 npi_mac_pcs_link_intr_disable(npi_handle_t handle, uint8_t portn) 570 { 571 pcs_cfg_t pcs_cfg; 572 573 ASSERT(IS_PORT_NUM_VALID(portn)); 574 575 PCS_REG_RD(handle, portn, PCS_CONFIG_REG, &pcs_cfg.val.lsw); 576 pcs_cfg.bits.w0.mask = 1; 577 PCS_REG_WR(handle, portn, PCS_CONFIG_REG, pcs_cfg.val.lsw); 578 579 return (NPI_SUCCESS); 580 } 581 582 npi_status_t 583 npi_xmac_xpcs_link_intr_enable(npi_handle_t handle, uint8_t portn) 584 { 585 xpcs_stat1_t xpcs_mask1; 586 587 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 588 589 XPCS_REG_RD(handle, portn, XPCS_MASK_1_REG, &xpcs_mask1.val.lsw); 590 xpcs_mask1.bits.w0.csr_rx_link_stat = 1; 591 XPCS_REG_WR(handle, portn, XPCS_MASK_1_REG, xpcs_mask1.val.lsw); 592 593 return (NPI_SUCCESS); 594 } 595 596 npi_status_t 597 npi_xmac_xpcs_link_intr_disable(npi_handle_t handle, uint8_t portn) 598 { 599 xpcs_stat1_t xpcs_mask1; 600 601 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 602 603 XPCS_REG_RD(handle, portn, XPCS_MASK_1_REG, &xpcs_mask1.val.lsw); 604 xpcs_mask1.bits.w0.csr_rx_link_stat = 0; 605 XPCS_REG_WR(handle, portn, XPCS_MASK_1_REG, xpcs_mask1.val.lsw); 606 607 return (NPI_SUCCESS); 608 } 609 610 npi_status_t 611 npi_mac_mif_link_intr_disable(npi_handle_t handle, uint8_t portn) 612 { 613 mif_cfg_t mif_cfg; 614 615 ASSERT(IS_PORT_NUM_VALID(portn)); 616 617 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.val.lsw); 618 619 mif_cfg.bits.w0.phy_addr = portn; 620 mif_cfg.bits.w0.poll_en = 0; 621 622 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.val.lsw); 623 624 NXGE_DELAY(20); 625 626 return (NPI_SUCCESS); 627 } 628 629 npi_status_t 630 npi_mac_hashtab_entry(npi_handle_t handle, io_op_t op, uint8_t portn, 631 uint8_t entryn, uint16_t *data) 632 { 633 uint64_t val; 634 635 ASSERT((op == OP_GET) || (op == OP_SET)); 636 ASSERT(IS_PORT_NUM_VALID(portn)); 637 638 ASSERT(entryn < MAC_MAX_HASH_ENTRY); 639 if (entryn >= MAC_MAX_HASH_ENTRY) { 640 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 641 " npi_mac_hashtab_entry" 642 " Invalid Input: entryn <0x%x>", 643 entryn)); 644 return (NPI_FAILURE | NPI_MAC_HASHTAB_ENTRY_INVALID(portn)); 645 } 646 647 if (op == OP_SET) { 648 val = *data; 649 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 650 XMAC_REG_WR(handle, portn, 651 XMAC_HASH_TBLN_REG_ADDR(entryn), val); 652 } else { 653 BMAC_REG_WR(handle, portn, 654 BMAC_HASH_TBLN_REG_ADDR(entryn), val); 655 } 656 } else { 657 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 658 XMAC_REG_RD(handle, portn, 659 XMAC_HASH_TBLN_REG_ADDR(entryn), &val); 660 } else { 661 BMAC_REG_RD(handle, portn, 662 BMAC_HASH_TBLN_REG_ADDR(entryn), &val); 663 } 664 *data = val & 0xFFFF; 665 } 666 667 return (NPI_SUCCESS); 668 } 669 670 npi_status_t 671 npi_mac_hostinfo_entry(npi_handle_t handle, io_op_t op, uint8_t portn, 672 uint8_t entryn, hostinfo_t *hostinfo) 673 { 674 ASSERT((op == OP_GET) || (op == OP_SET)); 675 ASSERT(IS_PORT_NUM_VALID(portn)); 676 677 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 678 ASSERT(entryn < XMAC_MAX_HOST_INFO_ENTRY); 679 if (entryn >= XMAC_MAX_HOST_INFO_ENTRY) { 680 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 681 " npi_mac_hostinfo_entry" 682 " Invalid Input: entryn <0x%x>", 683 entryn)); 684 return (NPI_FAILURE | 685 NPI_MAC_HOSTINFO_ENTRY_INVALID(portn)); 686 } 687 } else { 688 ASSERT(entryn < BMAC_MAX_HOST_INFO_ENTRY); 689 if (entryn >= BMAC_MAX_HOST_INFO_ENTRY) { 690 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 691 " npi_mac_hostinfo_entry" 692 " Invalid Input: entryn <0x%x>", 693 entryn)); 694 return (NPI_FAILURE | 695 NPI_MAC_HOSTINFO_ENTRY_INVALID(portn)); 696 } 697 } 698 699 if (op == OP_SET) { 700 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 701 XMAC_REG_WR(handle, portn, 702 XMAC_HOST_INFN_REG_ADDR(entryn), 703 hostinfo->value); 704 } else { 705 BMAC_REG_WR(handle, portn, 706 BMAC_HOST_INFN_REG_ADDR(entryn), 707 hostinfo->value); 708 } 709 } else { 710 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 711 XMAC_REG_RD(handle, portn, 712 XMAC_HOST_INFN_REG_ADDR(entryn), 713 &hostinfo->value); 714 } else { 715 BMAC_REG_RD(handle, portn, 716 BMAC_HOST_INFN_REG_ADDR(entryn), 717 &hostinfo->value); 718 } 719 } 720 721 return (NPI_SUCCESS); 722 } 723 724 npi_status_t 725 npi_mac_altaddr_enable(npi_handle_t handle, uint8_t portn, uint8_t addrn) 726 { 727 uint64_t val; 728 729 ASSERT(IS_PORT_NUM_VALID(portn)); 730 731 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 732 ASSERT(addrn <= XMAC_MAX_ALT_ADDR_ENTRY); 733 if (addrn > XMAC_MAX_ALT_ADDR_ENTRY) { 734 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 735 " npi_mac_altaddr_enable" 736 " Invalid Input: addrn <0x%x>", 737 addrn)); 738 return (NPI_FAILURE | 739 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 740 } 741 XMAC_REG_RD(handle, portn, XMAC_ADDR_CMPEN_REG, &val); 742 val |= (1 << addrn); 743 XMAC_REG_WR(handle, portn, XMAC_ADDR_CMPEN_REG, val); 744 } else { 745 ASSERT(addrn <= BMAC_MAX_ALT_ADDR_ENTRY); 746 if (addrn > BMAC_MAX_ALT_ADDR_ENTRY) { 747 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 748 " npi_mac_altaddr_enable" 749 " Invalid Input: addrn <0x%x>", 750 addrn)); 751 return (NPI_FAILURE | 752 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 753 } 754 BMAC_REG_RD(handle, portn, BMAC_ALTAD_CMPEN_REG, &val); 755 val |= (1 << addrn); 756 BMAC_REG_WR(handle, portn, BMAC_ALTAD_CMPEN_REG, val); 757 } 758 759 return (NPI_SUCCESS); 760 } 761 762 /* 763 * While all bits of XMAC_ADDR_CMPEN_REG are for alternate MAC addresses, 764 * bit0 of BMAC_ALTAD_CMPEN_REG is for unique MAC address. 765 */ 766 npi_status_t 767 npi_mac_altaddr_disable(npi_handle_t handle, uint8_t portn, uint8_t addrn) 768 { 769 uint64_t val; 770 771 ASSERT(IS_PORT_NUM_VALID(portn)); 772 773 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 774 ASSERT(addrn <= XMAC_MAX_ALT_ADDR_ENTRY); 775 if (addrn > XMAC_MAX_ALT_ADDR_ENTRY) { 776 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 777 " npi_mac_altaddr_disable" 778 " Invalid Input: addrn <0x%x>", 779 addrn)); 780 return (NPI_FAILURE | 781 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 782 } 783 XMAC_REG_RD(handle, portn, XMAC_ADDR_CMPEN_REG, &val); 784 val &= ~(1 << addrn); 785 XMAC_REG_WR(handle, portn, XMAC_ADDR_CMPEN_REG, val); 786 } else { 787 ASSERT(addrn <= BMAC_MAX_ALT_ADDR_ENTRY); 788 if (addrn > BMAC_MAX_ALT_ADDR_ENTRY) { 789 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 790 " npi_mac_altaddr_disable" 791 " Invalid Input: addrn <0x%x>", 792 addrn)); 793 return (NPI_FAILURE | 794 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 795 } 796 BMAC_REG_RD(handle, portn, BMAC_ALTAD_CMPEN_REG, &val); 797 val &= ~(1 << addrn); 798 BMAC_REG_WR(handle, portn, BMAC_ALTAD_CMPEN_REG, val); 799 } 800 801 return (NPI_SUCCESS); 802 } 803 804 npi_status_t 805 npi_mac_altaddr_entry(npi_handle_t handle, io_op_t op, uint8_t portn, 806 uint8_t entryn, npi_mac_addr_t *data) 807 { 808 uint64_t val0, val1, val2; 809 810 ASSERT(IS_PORT_NUM_VALID(portn)); 811 ASSERT((op == OP_GET) || (op == OP_SET)); 812 813 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 814 ASSERT(entryn <= XMAC_MAX_ALT_ADDR_ENTRY); 815 if (entryn > XMAC_MAX_ALT_ADDR_ENTRY) { 816 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 817 " npi_mac_altaddr_entry" 818 " Invalid Input: entryn <0x%x>", 819 entryn)); 820 return (NPI_FAILURE | 821 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 822 } 823 if (op == OP_SET) { 824 val0 = data->w0; 825 val1 = data->w1; 826 val2 = data->w2; 827 XMAC_REG_WR(handle, portn, 828 XMAC_ALT_ADDR0N_REG_ADDR(entryn), val0); 829 XMAC_REG_WR(handle, portn, 830 XMAC_ALT_ADDR1N_REG_ADDR(entryn), val1); 831 XMAC_REG_WR(handle, portn, 832 XMAC_ALT_ADDR2N_REG_ADDR(entryn), val2); 833 } else { 834 XMAC_REG_RD(handle, portn, 835 XMAC_ALT_ADDR0N_REG_ADDR(entryn), &val0); 836 XMAC_REG_RD(handle, portn, 837 XMAC_ALT_ADDR1N_REG_ADDR(entryn), &val1); 838 XMAC_REG_RD(handle, portn, 839 XMAC_ALT_ADDR2N_REG_ADDR(entryn), &val2); 840 data->w0 = val0 & 0xFFFF; 841 data->w1 = val1 & 0xFFFF; 842 data->w2 = val2 & 0xFFFF; 843 } 844 } else { 845 ASSERT(entryn <= BMAC_MAX_ALT_ADDR_ENTRY); 846 if (entryn > BMAC_MAX_ALT_ADDR_ENTRY) { 847 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 848 " npi_mac_altaddr_entry" 849 " Invalid Input: entryn <0x%x>", 850 entryn)); 851 return (NPI_FAILURE | 852 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 853 } 854 if (op == OP_SET) { 855 val0 = data->w0; 856 val1 = data->w1; 857 val2 = data->w2; 858 BMAC_REG_WR(handle, portn, 859 BMAC_ALT_ADDR0N_REG_ADDR(entryn), val0); 860 BMAC_REG_WR(handle, portn, 861 BMAC_ALT_ADDR1N_REG_ADDR(entryn), val1); 862 BMAC_REG_WR(handle, portn, 863 BMAC_ALT_ADDR2N_REG_ADDR(entryn), val2); 864 } else { 865 BMAC_REG_RD(handle, portn, 866 BMAC_ALT_ADDR0N_REG_ADDR(entryn), &val0); 867 BMAC_REG_RD(handle, portn, 868 BMAC_ALT_ADDR1N_REG_ADDR(entryn), &val1); 869 BMAC_REG_RD(handle, portn, 870 BMAC_ALT_ADDR2N_REG_ADDR(entryn), &val2); 871 data->w0 = val0 & 0xFFFF; 872 data->w1 = val1 & 0xFFFF; 873 data->w2 = val2 & 0xFFFF; 874 } 875 } 876 877 return (NPI_SUCCESS); 878 } 879 880 npi_status_t 881 npi_mac_port_attr(npi_handle_t handle, io_op_t op, uint8_t portn, 882 npi_attr_t *attrp) 883 { 884 uint64_t val = 0; 885 uint32_t attr; 886 887 ASSERT(IS_PORT_NUM_VALID(portn)); 888 ASSERT((op == OP_GET) || (op == OP_SET)); 889 890 switch (attrp->type) { 891 case MAC_PORT_MODE: 892 switch (portn) { 893 case XMAC_PORT_0: 894 case XMAC_PORT_1: 895 if (op == OP_SET) { 896 attr = attrp->idata[0]; 897 ASSERT((attr == MAC_MII_MODE) || \ 898 (attr == MAC_GMII_MODE) || \ 899 (attr == MAC_XGMII_MODE)); 900 if ((attr != MAC_MII_MODE) && 901 (attr != MAC_GMII_MODE) && 902 (attr != MAC_XGMII_MODE)) { 903 NPI_ERROR_MSG((handle.function, 904 NPI_ERR_CTL, 905 " npi_mac_port_attr" 906 " Invalid Input:" 907 " MAC_PORT_MODE <0x%x>", 908 attr)); 909 return (NPI_FAILURE | 910 NPI_MAC_PORT_ATTR_INVALID(portn)); 911 } 912 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, 913 &val); 914 val &= ~XMAC_XIF_MII_MODE_MASK; 915 switch (attr) { 916 case MAC_MII_MODE: 917 val |= (XMAC_XIF_MII_MODE << 918 XMAC_XIF_MII_MODE_SHIFT); 919 break; 920 case MAC_GMII_MODE: 921 val |= (XMAC_XIF_GMII_MODE << 922 XMAC_XIF_MII_MODE_SHIFT); 923 break; 924 case MAC_XGMII_MODE: 925 val |= (XMAC_XIF_XGMII_MODE << 926 XMAC_XIF_MII_MODE_SHIFT); 927 break; 928 default: 929 return (NPI_FAILURE | 930 NPI_MAC_PORT_ATTR_INVALID(portn)); 931 } 932 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, 933 val); 934 } else { 935 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, 936 &val); 937 val &= XMAC_XIF_MII_MODE_MASK; 938 attr = val >> XMAC_XIF_MII_MODE_SHIFT; 939 attrp->odata[0] = attr; 940 } 941 break; 942 case BMAC_PORT_0: 943 case BMAC_PORT_1: 944 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 945 " npi_mac_port_attr" 946 " Invalid Input:" 947 " MAC_PORT_MODE <0x%x>", 948 attrp->type)); 949 return (NPI_FAILURE | 950 NPI_MAC_PORT_ATTR_INVALID(portn)); 951 default: 952 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 953 } 954 break; 955 956 case MAC_PORT_FRAME_SIZE: { 957 uint32_t min_fsize; 958 uint32_t max_fsize; 959 960 switch (portn) { 961 case XMAC_PORT_0: 962 case XMAC_PORT_1: 963 if (op == OP_SET) { 964 min_fsize = attrp->idata[0]; 965 max_fsize = attrp->idata[1]; 966 ASSERT((min_fsize & \ 967 ~XMAC_MIN_TX_FRM_SZ_MASK) == 0); 968 if ((min_fsize & ~XMAC_MIN_TX_FRM_SZ_MASK) 969 != 0) { 970 NPI_ERROR_MSG((handle.function, 971 NPI_ERR_CTL, 972 " npi_mac_port_attr" 973 " MAC_PORT_FRAME_SIZE:" 974 " Invalid Input:" 975 " xmac_min_fsize <0x%x>", 976 min_fsize)); 977 return (NPI_FAILURE | 978 NPI_MAC_PORT_ATTR_INVALID(portn)); 979 } 980 ASSERT((max_fsize & \ 981 ~XMAC_MAX_FRM_SZ_MASK) == 0); 982 if ((max_fsize & ~XMAC_MAX_FRM_SZ_MASK) 983 != 0) { 984 NPI_ERROR_MSG((handle.function, 985 NPI_ERR_CTL, 986 " npi_mac_port_attr" 987 " MAC_PORT_FRAME_SIZE:" 988 " Invalid Input:" 989 " xmac_max_fsize <0x%x>", 990 max_fsize)); 991 return (NPI_FAILURE | 992 NPI_MAC_PORT_ATTR_INVALID(portn)); 993 } 994 XMAC_REG_RD(handle, portn, XMAC_MIN_REG, &val); 995 val &= ~(XMAC_MIN_TX_FRM_SZ_MASK | 996 XMAC_MIN_RX_FRM_SZ_MASK); 997 val |= (min_fsize << XMAC_MIN_TX_FRM_SZ_SHIFT); 998 val |= (min_fsize << XMAC_MIN_RX_FRM_SZ_SHIFT); 999 XMAC_REG_WR(handle, portn, XMAC_MIN_REG, val); 1000 XMAC_REG_WR(handle, portn, XMAC_MAX_REG, 1001 max_fsize); 1002 } else { 1003 XMAC_REG_RD(handle, portn, XMAC_MIN_REG, &val); 1004 min_fsize = (val & XMAC_MIN_TX_FRM_SZ_MASK) 1005 >> XMAC_MIN_TX_FRM_SZ_SHIFT; 1006 XMAC_REG_RD(handle, portn, XMAC_MAX_REG, &val); 1007 attrp->odata[0] = min_fsize; 1008 attrp->odata[1] = max_fsize; 1009 } 1010 break; 1011 case BMAC_PORT_0: 1012 case BMAC_PORT_1: 1013 if (op == OP_SET) { 1014 min_fsize = attrp->idata[0]; 1015 max_fsize = attrp->idata[1]; 1016 ASSERT((min_fsize & ~BMAC_MIN_FRAME_MASK) == 0); 1017 if ((min_fsize & ~BMAC_MIN_FRAME_MASK) 1018 != 0) { 1019 NPI_ERROR_MSG((handle.function, 1020 NPI_ERR_CTL, 1021 " npi_mac_port_attr" 1022 " MAC_FRAME_SIZE:" 1023 " Invalid Input:" 1024 " bmac_min_fsize <0x%x>", 1025 min_fsize)); 1026 return (NPI_FAILURE | 1027 NPI_MAC_PORT_ATTR_INVALID(portn)); 1028 } 1029 ASSERT((max_fsize & ~BMAC_MAX_FRAME_MASK) == 0); 1030 if ((max_fsize & ~BMAC_MAX_FRAME_MASK) 1031 != 0) { 1032 NPI_ERROR_MSG((handle.function, 1033 NPI_ERR_CTL, 1034 " npi_mac_port_attr" 1035 " MAC_FRAME_SIZE:" 1036 " Invalid Input:" 1037 " bmac_max_fsize <0x%x>", 1038 max_fsize)); 1039 return (NPI_FAILURE | 1040 NPI_MAC_PORT_ATTR_INVALID(portn)); 1041 } 1042 BMAC_REG_RD(handle, portn, BMAC_MAX_REG, &val); 1043 val &= ~BMAC_MAX_FRAME_MASK; 1044 if (max_fsize <= MAX_FRAME_SZ1) 1045 val |= MAX_FRAME_SZ1; 1046 else if ((max_fsize > MAX_FRAME_SZ1) && 1047 (max_fsize <= MAX_FRAME_SZ2)) 1048 val |= MAX_FRAME_SZ2; 1049 else if ((max_fsize > MAX_FRAME_SZ2) && 1050 (max_fsize <= MAX_FRAME_SZ3)) 1051 val |= MAX_FRAME_SZ3; 1052 else if ((max_fsize > MAX_FRAME_SZ3) && 1053 (max_fsize <= MAX_FRAME_SZ4)) 1054 val |= MAX_FRAME_SZ4; 1055 else if ((max_fsize > MAX_FRAME_SZ4) && 1056 (max_fsize <= MAX_FRAME_SZ5)) 1057 val |= MAX_FRAME_SZ5; 1058 BMAC_REG_WR(handle, portn, BMAC_MAX_REG, val); 1059 BMAC_REG_WR(handle, portn, BMAC_MIN_REG, 1060 min_fsize); 1061 } else { 1062 BMAC_REG_RD(handle, portn, BMAC_MIN_REG, &val); 1063 min_fsize = val & BMAC_MIN_FRAME_MASK; 1064 BMAC_REG_RD(handle, portn, BMAC_MAX_REG, &val); 1065 max_fsize = val & BMAC_MAX_FRAME_MASK; 1066 attrp->odata[0] = min_fsize; 1067 attrp->odata[1] = max_fsize; 1068 } 1069 break; 1070 default: 1071 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1072 } 1073 } break; 1074 1075 case BMAC_PORT_MAX_BURST_SIZE: { 1076 uint32_t burst_size; 1077 switch (portn) { 1078 case XMAC_PORT_0: 1079 case XMAC_PORT_1: 1080 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1081 " npi_mac_port_attr" 1082 " BMAC_PORT_MAX_BURST_SIZE:" 1083 " Invalid Input: portn <%d>", 1084 portn)); 1085 return (NPI_FAILURE | NPI_MAC_PORT_ATTR_INVALID(portn)); 1086 case BMAC_PORT_0: 1087 case BMAC_PORT_1: 1088 /* NOTE: Not used in Full duplex mode */ 1089 if (op == OP_SET) { 1090 burst_size = attrp->idata[0]; 1091 ASSERT((burst_size & ~0x7FFF) == 0); 1092 if ((burst_size & ~0x7FFF) != 0) { 1093 NPI_ERROR_MSG((handle.function, 1094 NPI_ERR_CTL, 1095 " npi_mac_port_attr" 1096 " BMAC_MAX_BURST_SIZE:" 1097 " Invalid Input:" 1098 " burst_size <0x%x>", 1099 burst_size)); 1100 return (NPI_FAILURE | 1101 NPI_MAC_PORT_ATTR_INVALID(portn)); 1102 } 1103 BMAC_REG_RD(handle, portn, BMAC_MAX_REG, &val); 1104 val &= ~BMAC_MAX_BURST_MASK; 1105 val |= (burst_size << BMAC_MAX_BURST_SHIFT); 1106 BMAC_REG_WR(handle, portn, BMAC_MAX_REG, val); 1107 } else { 1108 BMAC_REG_RD(handle, portn, BMAC_MAX_REG, &val); 1109 burst_size = (val & BMAC_MAX_BURST_MASK) 1110 >> BMAC_MAX_BURST_SHIFT; 1111 attrp->odata[0] = burst_size; 1112 } 1113 break; 1114 default: 1115 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1116 } 1117 } break; 1118 1119 case BMAC_PORT_PA_SIZE: { 1120 uint32_t pa_size; 1121 switch (portn) { 1122 case XMAC_PORT_0: 1123 case XMAC_PORT_1: 1124 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1125 " npi_mac_port_attr" 1126 " BMAC_PORT_PA_SIZE:" 1127 " Invalid Input: portn <%d>", 1128 portn)); 1129 return (NPI_FAILURE | NPI_MAC_PORT_ATTR_INVALID(portn)); 1130 case BMAC_PORT_0: 1131 case BMAC_PORT_1: 1132 if (op == OP_SET) { 1133 pa_size = attrp->idata[0]; 1134 ASSERT((pa_size & ~0x3FF) == 0); 1135 if ((pa_size & ~0x3FF) != 0) { 1136 NPI_ERROR_MSG((handle.function, 1137 NPI_ERR_CTL, 1138 " npi_mac_port_attr" 1139 " BMAC_PORT_PA_SIZE:" 1140 " Invalid Input: pa_size <0x%x>", 1141 pa_size)); 1142 1143 return (NPI_FAILURE | 1144 NPI_MAC_PORT_ATTR_INVALID(portn)); 1145 } 1146 BMAC_REG_RD(handle, portn, MAC_PA_SIZE_REG, 1147 &val); 1148 val &= ~BMAC_PA_SIZE_MASK; 1149 val |= (pa_size << 0); 1150 BMAC_REG_WR(handle, portn, MAC_PA_SIZE_REG, 1151 val); 1152 } else { 1153 BMAC_REG_RD(handle, portn, MAC_PA_SIZE_REG, 1154 &val); 1155 pa_size = (val & BMAC_PA_SIZE_MASK) >> 0; 1156 attrp->odata[0] = pa_size; 1157 } 1158 break; 1159 default: 1160 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1161 } 1162 } break; 1163 1164 case BMAC_PORT_CTRL_TYPE: { 1165 uint32_t ctrl_type; 1166 switch (portn) { 1167 case XMAC_PORT_0: 1168 case XMAC_PORT_1: 1169 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1170 " npi_mac_port_attr" 1171 " BMAC_PORT_CTRL_TYPE:" 1172 " Invalid Input: portn <%d>", 1173 portn)); 1174 return (NPI_FAILURE | NPI_MAC_PORT_ATTR_INVALID(portn)); 1175 case BMAC_PORT_0: 1176 case BMAC_PORT_1: 1177 if (op == OP_SET) { 1178 ctrl_type = attrp->idata[0]; 1179 ASSERT((ctrl_type & ~0xFFFF) == 0); 1180 if ((ctrl_type & ~0xFFFF) != 0) { 1181 NPI_ERROR_MSG((handle.function, 1182 NPI_ERR_CTL, 1183 " npi_mac_port_attr" 1184 " BMAC_PORT_CTRL_TYPE:" 1185 " Invalid Input:" 1186 " ctrl_type <0x%x>", 1187 ctrl_type)); 1188 return (NPI_FAILURE | 1189 NPI_MAC_PORT_ATTR_INVALID(portn)); 1190 } 1191 BMAC_REG_WR(handle, portn, MAC_CTRL_TYPE_REG, 1192 val); 1193 } else { 1194 BMAC_REG_RD(handle, portn, MAC_CTRL_TYPE_REG, 1195 &val); 1196 ctrl_type = (val & 0xFFFF); 1197 attrp->odata[0] = ctrl_type; 1198 } 1199 break; 1200 default: 1201 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1202 } 1203 } break; 1204 1205 case XMAC_10G_PORT_IPG: 1206 { 1207 uint32_t ipg0; 1208 1209 switch (portn) { 1210 case XMAC_PORT_0: 1211 case XMAC_PORT_1: 1212 if (op == OP_SET) { 1213 ipg0 = attrp->idata[0]; 1214 ASSERT((ipg0 == XGMII_IPG_12_15) || \ 1215 (ipg0 == XGMII_IPG_16_19) || \ 1216 (ipg0 == XGMII_IPG_20_23)); 1217 if ((ipg0 != XGMII_IPG_12_15) && 1218 (ipg0 != XGMII_IPG_16_19) && 1219 (ipg0 != XGMII_IPG_20_23)) { 1220 NPI_ERROR_MSG((handle.function, 1221 NPI_ERR_CTL, 1222 " npi_mac_port_attr" 1223 " MAC_10G_PORT_IPG:" 1224 " Invalid Input:" 1225 " xgmii_ipg <0x%x>", 1226 ipg0)); 1227 return (NPI_FAILURE | 1228 NPI_MAC_PORT_ATTR_INVALID(portn)); 1229 } 1230 1231 XMAC_REG_RD(handle, portn, XMAC_IPG_REG, &val); 1232 val &= ~(XMAC_IPG_VALUE_MASK | 1233 XMAC_IPG_VALUE1_MASK); 1234 1235 switch (ipg0) { 1236 case XGMII_IPG_12_15: 1237 val |= (IPG_12_15_BYTE << 1238 XMAC_IPG_VALUE_SHIFT); 1239 break; 1240 case XGMII_IPG_16_19: 1241 val |= (IPG_16_19_BYTE << 1242 XMAC_IPG_VALUE_SHIFT); 1243 break; 1244 case XGMII_IPG_20_23: 1245 val |= (IPG_20_23_BYTE << 1246 XMAC_IPG_VALUE_SHIFT); 1247 break; 1248 default: 1249 return (NPI_FAILURE | 1250 NPI_MAC_PORT_ATTR_INVALID(portn)); 1251 } 1252 XMAC_REG_WR(handle, portn, XMAC_IPG_REG, val); 1253 } else { 1254 XMAC_REG_RD(handle, portn, XMAC_IPG_REG, &val); 1255 ipg0 = (val & XMAC_IPG_VALUE_MASK) >> 1256 XMAC_IPG_VALUE_SHIFT; 1257 switch (ipg0) { 1258 case IPG_12_15_BYTE: 1259 attrp->odata[0] = XGMII_IPG_12_15; 1260 break; 1261 case IPG_16_19_BYTE: 1262 attrp->odata[0] = XGMII_IPG_16_19; 1263 break; 1264 case IPG_20_23_BYTE: 1265 attrp->odata[0] = XGMII_IPG_20_23; 1266 break; 1267 default: 1268 return (NPI_FAILURE | 1269 NPI_MAC_PORT_ATTR_INVALID(portn)); 1270 } 1271 } 1272 break; 1273 case BMAC_PORT_0: 1274 case BMAC_PORT_1: 1275 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1276 " npi_mac_port_attr" "MAC_PORT_IPG:" 1277 " Invalid Input: portn <%d>", 1278 portn)); 1279 default: 1280 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1281 } 1282 break; 1283 } 1284 1285 case XMAC_PORT_IPG: 1286 { 1287 uint32_t ipg1; 1288 switch (portn) { 1289 case XMAC_PORT_0: 1290 case XMAC_PORT_1: 1291 if (op == OP_SET) { 1292 ipg1 = attrp->idata[0]; 1293 ASSERT((ipg1 == MII_GMII_IPG_12) || \ 1294 (ipg1 == MII_GMII_IPG_13) || \ 1295 (ipg1 == MII_GMII_IPG_14) || \ 1296 (ipg1 == MII_GMII_IPG_15) || \ 1297 (ipg1 == MII_GMII_IPG_16)); 1298 if ((ipg1 != MII_GMII_IPG_12) && 1299 (ipg1 != MII_GMII_IPG_13) && 1300 (ipg1 != MII_GMII_IPG_14) && 1301 (ipg1 != MII_GMII_IPG_15) && 1302 (ipg1 != MII_GMII_IPG_16)) { 1303 NPI_ERROR_MSG((handle.function, 1304 NPI_ERR_CTL, 1305 " npi_mac_port_attr" 1306 " XMAC_PORT_IPG:" 1307 " Invalid Input:" 1308 " mii_gmii_ipg <0x%x>", 1309 ipg1)); 1310 return (NPI_FAILURE | 1311 NPI_MAC_PORT_ATTR_INVALID(portn)); 1312 } 1313 1314 XMAC_REG_RD(handle, portn, XMAC_IPG_REG, &val); 1315 val &= ~(XMAC_IPG_VALUE_MASK | 1316 XMAC_IPG_VALUE1_MASK); 1317 1318 switch (ipg1) { 1319 case MII_GMII_IPG_12: 1320 val |= (IPG1_12_BYTES << 1321 XMAC_IPG_VALUE1_SHIFT); 1322 break; 1323 case MII_GMII_IPG_13: 1324 val |= (IPG1_13_BYTES << 1325 XMAC_IPG_VALUE1_SHIFT); 1326 break; 1327 case MII_GMII_IPG_14: 1328 val |= (IPG1_14_BYTES << 1329 XMAC_IPG_VALUE1_SHIFT); 1330 break; 1331 case MII_GMII_IPG_15: 1332 val |= (IPG1_15_BYTES << 1333 XMAC_IPG_VALUE1_SHIFT); 1334 break; 1335 case MII_GMII_IPG_16: 1336 val |= (IPG1_16_BYTES << 1337 XMAC_IPG_VALUE1_SHIFT); 1338 break; 1339 default: 1340 return (NPI_FAILURE | 1341 NPI_MAC_PORT_ATTR_INVALID(portn)); 1342 } 1343 XMAC_REG_WR(handle, portn, XMAC_IPG_REG, val); 1344 } else { 1345 XMAC_REG_RD(handle, portn, XMAC_IPG_REG, &val); 1346 ipg1 = (val & XMAC_IPG_VALUE1_MASK) >> 1347 XMAC_IPG_VALUE1_SHIFT; 1348 switch (ipg1) { 1349 case IPG1_12_BYTES: 1350 attrp->odata[1] = MII_GMII_IPG_12; 1351 break; 1352 case IPG1_13_BYTES: 1353 attrp->odata[1] = MII_GMII_IPG_13; 1354 break; 1355 case IPG1_14_BYTES: 1356 attrp->odata[1] = MII_GMII_IPG_14; 1357 break; 1358 case IPG1_15_BYTES: 1359 attrp->odata[1] = MII_GMII_IPG_15; 1360 break; 1361 case IPG1_16_BYTES: 1362 attrp->odata[1] = MII_GMII_IPG_16; 1363 break; 1364 default: 1365 return (NPI_FAILURE | 1366 NPI_MAC_PORT_ATTR_INVALID(portn)); 1367 } 1368 } 1369 break; 1370 case BMAC_PORT_0: 1371 case BMAC_PORT_1: 1372 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1373 " npi_mac_port_attr" 1374 " MAC_PORT_IPG:" 1375 " Invalid Input: portn <%d>", 1376 portn)); 1377 default: 1378 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1379 } 1380 break; 1381 } 1382 1383 case MAC_PORT_ADDR: { 1384 uint32_t addr0; 1385 uint32_t addr1; 1386 uint32_t addr2; 1387 1388 switch (portn) { 1389 case XMAC_PORT_0: 1390 case XMAC_PORT_1: 1391 if (op == OP_SET) { 1392 addr0 = attrp->idata[0]; 1393 addr1 = attrp->idata[1]; 1394 addr2 = attrp->idata[2]; 1395 ASSERT((addr0 & ~0xFFFF) == 0); 1396 if ((addr0 & ~0xFFFF) != 0) { 1397 NPI_ERROR_MSG((handle.function, 1398 NPI_ERR_CTL, 1399 " npi_mac_port_attr" 1400 " MAC_PORT_ADDR:" 1401 " Invalid Input:" 1402 " addr0 <0x%x>", addr0)); 1403 1404 return (NPI_FAILURE | 1405 NPI_MAC_PORT_ATTR_INVALID(portn)); 1406 } 1407 ASSERT((addr1 & ~0xFFFF) == 0); 1408 if ((addr1 & ~0xFFFF) != 0) { 1409 NPI_ERROR_MSG((handle.function, 1410 NPI_ERR_CTL, 1411 " npi_mac_port_attr" 1412 " MAC_PORT_ADDR:" 1413 " Invalid Input:" 1414 " addr1 <0x%x>", addr1)); 1415 return (NPI_FAILURE | 1416 NPI_MAC_PORT_ATTR_INVALID(portn)); 1417 } 1418 ASSERT((addr2 & ~0xFFFF) == 0); 1419 if ((addr2 & ~0xFFFF) != 0) { 1420 NPI_ERROR_MSG((handle.function, 1421 NPI_ERR_CTL, 1422 " npi_mac_port_attr" 1423 " MAC_PORT_ADDR:" 1424 " Invalid Input:" 1425 " addr2 <0x%x.", 1426 addr2)); 1427 1428 return (NPI_FAILURE | 1429 NPI_MAC_PORT_ATTR_INVALID(portn)); 1430 } 1431 XMAC_REG_WR(handle, portn, XMAC_ADDR0_REG, 1432 addr0); 1433 XMAC_REG_WR(handle, portn, XMAC_ADDR1_REG, 1434 addr1); 1435 XMAC_REG_WR(handle, portn, XMAC_ADDR2_REG, 1436 addr2); 1437 } else { 1438 XMAC_REG_RD(handle, portn, XMAC_ADDR0_REG, 1439 &addr0); 1440 XMAC_REG_RD(handle, portn, XMAC_ADDR1_REG, 1441 &addr1); 1442 XMAC_REG_RD(handle, portn, XMAC_ADDR2_REG, 1443 &addr2); 1444 attrp->odata[0] = addr0 & MAC_ADDR_REG_MASK; 1445 attrp->odata[1] = addr1 & MAC_ADDR_REG_MASK; 1446 attrp->odata[2] = addr2 & MAC_ADDR_REG_MASK; 1447 } 1448 break; 1449 case BMAC_PORT_0: 1450 case BMAC_PORT_1: 1451 if (op == OP_SET) { 1452 addr0 = attrp->idata[0]; 1453 addr1 = attrp->idata[1]; 1454 addr2 = attrp->idata[2]; 1455 ASSERT((addr0 & ~0xFFFF) == 0); 1456 if ((addr0 & ~0xFFFF) != 0) { 1457 NPI_ERROR_MSG((handle.function, 1458 NPI_ERR_CTL, 1459 " npi_mac_port_attr" 1460 " MAC_PORT_ADDR:" 1461 " Invalid Input:" 1462 " addr0 <0x%x>", 1463 addr0)); 1464 return (NPI_FAILURE | 1465 NPI_MAC_PORT_ATTR_INVALID(portn)); 1466 } 1467 ASSERT((addr1 & ~0xFFFF) == 0); 1468 if ((addr1 & ~0xFFFF) != 0) { 1469 NPI_ERROR_MSG((handle.function, 1470 NPI_ERR_CTL, 1471 " npi_mac_port_attr" 1472 " MAC_PORT_ADDR:" 1473 " Invalid Input:" 1474 " addr1 <0x%x>", 1475 addr1)); 1476 return (NPI_FAILURE | 1477 NPI_MAC_PORT_ATTR_INVALID(portn)); 1478 } 1479 ASSERT((addr2 & ~0xFFFF) == 0); 1480 if ((addr2 & ~0xFFFF) != 0) { 1481 NPI_ERROR_MSG((handle.function, 1482 NPI_ERR_CTL, 1483 " npi_mac_port_attr" 1484 " MAC_PORT_ADDR:" 1485 " Invalid Input:" 1486 " addr2 <0x%x>", 1487 addr2)); 1488 return (NPI_FAILURE | 1489 NPI_MAC_PORT_ATTR_INVALID(portn)); 1490 } 1491 BMAC_REG_WR(handle, portn, BMAC_ADDR0_REG, 1492 addr0); 1493 BMAC_REG_WR(handle, portn, BMAC_ADDR1_REG, 1494 addr1); 1495 BMAC_REG_WR(handle, portn, BMAC_ADDR2_REG, 1496 addr2); 1497 } else { 1498 BMAC_REG_RD(handle, portn, BMAC_ADDR0_REG, 1499 &addr0); 1500 BMAC_REG_RD(handle, portn, BMAC_ADDR1_REG, 1501 &addr1); 1502 BMAC_REG_RD(handle, portn, BMAC_ADDR2_REG, 1503 &addr2); 1504 attrp->odata[0] = addr0 & MAC_ADDR_REG_MASK; 1505 attrp->odata[1] = addr1 & MAC_ADDR_REG_MASK; 1506 attrp->odata[2] = addr2 & MAC_ADDR_REG_MASK; 1507 } 1508 break; 1509 default: 1510 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1511 } 1512 } break; 1513 1514 case MAC_PORT_ADDR_FILTER: { 1515 uint32_t addr0; 1516 uint32_t addr1; 1517 uint32_t addr2; 1518 1519 switch (portn) { 1520 case XMAC_PORT_0: 1521 case XMAC_PORT_1: 1522 if (op == OP_SET) { 1523 addr0 = attrp->idata[0]; 1524 addr1 = attrp->idata[1]; 1525 addr2 = attrp->idata[2]; 1526 ASSERT((addr0 & ~0xFFFF) == 0); 1527 if ((addr0 & ~0xFFFF) != 0) { 1528 NPI_ERROR_MSG((handle.function, 1529 NPI_ERR_CTL, 1530 " npi_mac_port_attr" 1531 " MAC_PORT_ADDR_FILTER:" 1532 " Invalid Input:" 1533 " addr0 <0x%x>", 1534 addr0)); 1535 return (NPI_FAILURE | 1536 NPI_MAC_PORT_ATTR_INVALID(portn)); 1537 } 1538 ASSERT((addr1 & ~0xFFFF) == 0); 1539 if ((addr1 & ~0xFFFF) != 0) { 1540 NPI_ERROR_MSG((handle.function, 1541 NPI_ERR_CTL, 1542 " npi_mac_port_attr" 1543 " MAC_PORT_ADDR_FILTER:" 1544 " Invalid Input:" 1545 " addr1 <0x%x>", 1546 addr1)); 1547 return (NPI_FAILURE | 1548 NPI_MAC_PORT_ATTR_INVALID(portn)); 1549 } 1550 ASSERT((addr2 & ~0xFFFF) == 0); 1551 if ((addr2 & ~0xFFFF) != 0) { 1552 NPI_ERROR_MSG((handle.function, 1553 NPI_ERR_CTL, 1554 " npi_mac_port_attr" 1555 " MAC_PORT_ADDR_FILTER:" 1556 " Invalid Input:" 1557 " addr2 <0x%x>", 1558 addr2)); 1559 return (NPI_FAILURE | 1560 NPI_MAC_PORT_ATTR_INVALID(portn)); 1561 } 1562 XMAC_REG_WR(handle, portn, 1563 XMAC_ADDR_FILT0_REG, addr0); 1564 XMAC_REG_WR(handle, portn, 1565 XMAC_ADDR_FILT1_REG, addr1); 1566 XMAC_REG_WR(handle, portn, 1567 XMAC_ADDR_FILT2_REG, addr2); 1568 } else { 1569 XMAC_REG_RD(handle, portn, 1570 XMAC_ADDR_FILT0_REG, &addr0); 1571 XMAC_REG_RD(handle, portn, 1572 XMAC_ADDR_FILT1_REG, &addr1); 1573 XMAC_REG_RD(handle, portn, 1574 XMAC_ADDR_FILT2_REG, &addr2); 1575 attrp->odata[0] = addr0 & MAC_ADDR_REG_MASK; 1576 attrp->odata[1] = addr1 & MAC_ADDR_REG_MASK; 1577 attrp->odata[2] = addr2 & MAC_ADDR_REG_MASK; 1578 } 1579 break; 1580 case BMAC_PORT_0: 1581 case BMAC_PORT_1: 1582 if (op == OP_SET) { 1583 addr0 = attrp->idata[0]; 1584 addr1 = attrp->idata[1]; 1585 addr2 = attrp->idata[2]; 1586 ASSERT((addr0 & ~0xFFFF) == 0); 1587 if ((addr0 & ~0xFFFF) != 0) { 1588 NPI_ERROR_MSG((handle.function, 1589 NPI_ERR_CTL, 1590 " npi_mac_port_attr" 1591 " MAC_PORT_ADDR_FILTER:" 1592 " addr0", 1593 addr0)); 1594 return (NPI_FAILURE | 1595 NPI_MAC_PORT_ATTR_INVALID(portn)); 1596 } 1597 ASSERT((addr1 & ~0xFFFF) == 0); 1598 if ((addr1 & ~0xFFFF) != 0) { 1599 NPI_ERROR_MSG((handle.function, 1600 NPI_ERR_CTL, 1601 " npi_mac_port_attr" 1602 " MAC_PORT_ADDR_FILTER:" 1603 " Invalid Input:" 1604 " addr1 <0x%x>", 1605 addr1)); 1606 return (NPI_FAILURE | 1607 NPI_MAC_PORT_ATTR_INVALID(portn)); 1608 } 1609 ASSERT((addr2 & ~0xFFFF) == 0); 1610 if ((addr2 & ~0xFFFF) != 0) { 1611 NPI_ERROR_MSG((handle.function, 1612 NPI_ERR_CTL, 1613 " npi_mac_port_attr" 1614 " MAC_PORT_ADDR_FILTER:" 1615 " Invalid Input:" 1616 " addr2 <0x%x>", 1617 addr2)); 1618 return (NPI_FAILURE | 1619 NPI_MAC_PORT_ATTR_INVALID(portn)); 1620 } 1621 BMAC_REG_WR(handle, portn, MAC_ADDR_FILT0_REG, 1622 addr0); 1623 BMAC_REG_WR(handle, portn, MAC_ADDR_FILT1_REG, 1624 addr1); 1625 BMAC_REG_WR(handle, portn, MAC_ADDR_FILT2_REG, 1626 addr2); 1627 } else { 1628 BMAC_REG_RD(handle, portn, MAC_ADDR_FILT0_REG, 1629 &addr0); 1630 BMAC_REG_RD(handle, portn, MAC_ADDR_FILT1_REG, 1631 &addr1); 1632 BMAC_REG_RD(handle, portn, MAC_ADDR_FILT2_REG, 1633 &addr2); 1634 attrp->odata[0] = addr0 & MAC_ADDR_REG_MASK; 1635 attrp->odata[1] = addr1 & MAC_ADDR_REG_MASK; 1636 attrp->odata[2] = addr2 & MAC_ADDR_REG_MASK; 1637 } 1638 break; 1639 default: 1640 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1641 } 1642 } break; 1643 1644 case MAC_PORT_ADDR_FILTER_MASK: { 1645 uint32_t mask_1_2; 1646 uint32_t mask_0; 1647 1648 switch (portn) { 1649 case XMAC_PORT_0: 1650 case XMAC_PORT_1: 1651 if (op == OP_SET) { 1652 mask_0 = attrp->idata[0]; 1653 mask_1_2 = attrp->idata[1]; 1654 ASSERT((mask_0 & ~0xFFFF) == 0); 1655 if ((mask_0 & ~0xFFFF) != 0) { 1656 NPI_ERROR_MSG((handle.function, 1657 NPI_ERR_CTL, 1658 " npi_mac_port_attr" 1659 " MAC_ADDR_FILTER_MASK:" 1660 " Invalid Input:" 1661 " mask_0 <0x%x>", 1662 mask_0)); 1663 return (NPI_FAILURE | 1664 NPI_MAC_PORT_ATTR_INVALID(portn)); 1665 } 1666 ASSERT((mask_1_2 & ~0xFF) == 0); 1667 if ((mask_1_2 & ~0xFF) != 0) { 1668 NPI_ERROR_MSG((handle.function, 1669 NPI_ERR_CTL, 1670 " npi_mac_port_attr" 1671 " MAC_ADDR_FILTER_MASK:" 1672 " Invalid Input:" 1673 " mask_1_2 <0x%x>", 1674 mask_1_2)); 1675 return (NPI_FAILURE | 1676 NPI_MAC_PORT_ATTR_INVALID(portn)); 1677 } 1678 XMAC_REG_WR(handle, portn, 1679 XMAC_ADDR_FILT0_MASK_REG, mask_0); 1680 XMAC_REG_WR(handle, portn, 1681 XMAC_ADDR_FILT12_MASK_REG, mask_1_2); 1682 } else { 1683 XMAC_REG_RD(handle, portn, 1684 XMAC_ADDR_FILT0_MASK_REG, &mask_0); 1685 XMAC_REG_RD(handle, portn, 1686 XMAC_ADDR_FILT12_MASK_REG, &mask_1_2); 1687 attrp->odata[0] = mask_0 & 0xFFFF; 1688 attrp->odata[1] = mask_1_2 & 0xFF; 1689 } 1690 break; 1691 case BMAC_PORT_0: 1692 case BMAC_PORT_1: 1693 if (op == OP_SET) { 1694 mask_0 = attrp->idata[0]; 1695 mask_1_2 = attrp->idata[1]; 1696 BMAC_REG_WR(handle, portn, 1697 MAC_ADDR_FILT00_MASK_REG, mask_0); 1698 BMAC_REG_WR(handle, portn, 1699 MAC_ADDR_FILT12_MASK_REG, mask_1_2); 1700 } else { 1701 BMAC_REG_RD(handle, portn, 1702 MAC_ADDR_FILT00_MASK_REG, &mask_0); 1703 BMAC_REG_RD(handle, portn, 1704 MAC_ADDR_FILT12_MASK_REG, &mask_1_2); 1705 attrp->odata[0] = mask_0; 1706 attrp->odata[1] = mask_1_2; 1707 } 1708 break; 1709 default: 1710 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1711 } 1712 } break; 1713 1714 default: 1715 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1716 " npi_mac_port_attr" 1717 " Invalid Input:" 1718 " attr <0x%x>", attrp->type)); 1719 return (NPI_FAILURE | NPI_MAC_PORT_ATTR_INVALID(portn)); 1720 } 1721 1722 return (NPI_SUCCESS); 1723 } 1724 1725 npi_status_t 1726 npi_xmac_reset(npi_handle_t handle, uint8_t portn, npi_mac_reset_t mode) 1727 { 1728 uint64_t val; 1729 boolean_t txmac = B_FALSE; 1730 1731 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 1732 1733 switch (mode) { 1734 case XTX_MAC_REG_RESET: 1735 XMAC_REG_WR(handle, portn, XTXMAC_SW_RST_REG, XTXMAC_REG_RST); 1736 XMAC_WAIT_REG(handle, portn, XTXMAC_SW_RST_REG, val); 1737 txmac = B_TRUE; 1738 break; 1739 case XRX_MAC_REG_RESET: 1740 XMAC_REG_WR(handle, portn, XRXMAC_SW_RST_REG, XRXMAC_REG_RST); 1741 XMAC_WAIT_REG(handle, portn, XRXMAC_SW_RST_REG, val); 1742 break; 1743 case XTX_MAC_LOGIC_RESET: 1744 XMAC_REG_WR(handle, portn, XTXMAC_SW_RST_REG, XTXMAC_SOFT_RST); 1745 XMAC_WAIT_REG(handle, portn, XTXMAC_SW_RST_REG, val); 1746 txmac = B_TRUE; 1747 break; 1748 case XRX_MAC_LOGIC_RESET: 1749 XMAC_REG_WR(handle, portn, XRXMAC_SW_RST_REG, XRXMAC_SOFT_RST); 1750 XMAC_WAIT_REG(handle, portn, XRXMAC_SW_RST_REG, val); 1751 break; 1752 case XTX_MAC_RESET_ALL: 1753 XMAC_REG_WR(handle, portn, XTXMAC_SW_RST_REG, 1754 XTXMAC_SOFT_RST | XTXMAC_REG_RST); 1755 XMAC_WAIT_REG(handle, portn, XTXMAC_SW_RST_REG, val); 1756 txmac = B_TRUE; 1757 break; 1758 case XRX_MAC_RESET_ALL: 1759 XMAC_REG_WR(handle, portn, XRXMAC_SW_RST_REG, 1760 XRXMAC_SOFT_RST | XRXMAC_REG_RST); 1761 XMAC_WAIT_REG(handle, portn, XRXMAC_SW_RST_REG, val); 1762 break; 1763 default: 1764 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1765 " npi_mac_reset" 1766 " Invalid Input: mode <0x%x>", 1767 mode)); 1768 return (NPI_FAILURE | NPI_MAC_RESET_MODE_INVALID(portn)); 1769 } 1770 1771 if (val != 0) { 1772 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1773 " npi_xmac_reset" 1774 " HW ERROR: MAC_RESET failed <0x%x>", 1775 val)); 1776 1777 if (txmac) 1778 return (NPI_FAILURE | NPI_TXMAC_RESET_FAILED(portn)); 1779 else 1780 return (NPI_FAILURE | NPI_RXMAC_RESET_FAILED(portn)); 1781 } 1782 1783 return (NPI_SUCCESS); 1784 } 1785 1786 npi_status_t 1787 npi_xmac_xif_config(npi_handle_t handle, config_op_t op, uint8_t portn, 1788 xmac_xif_config_t config) 1789 { 1790 uint64_t val = 0; 1791 1792 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 1793 1794 switch (op) { 1795 case ENABLE: 1796 case DISABLE: 1797 ASSERT((config != 0) && ((config & ~CFG_XMAC_XIF_ALL) == 0)); 1798 if ((config == 0) || (config & ~CFG_XMAC_XIF_ALL) != 0) { 1799 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1800 " npi_xmac_xif_config" 1801 " Invalid Input:" 1802 " config <0x%x>", config)); 1803 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 1804 } 1805 if (op == ENABLE) { 1806 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1807 if (config & CFG_XMAC_XIF_LED_FORCE) 1808 val |= XMAC_XIF_FORCE_LED_ON; 1809 if (config & CFG_XMAC_XIF_LED_POLARITY) 1810 val |= XMAC_XIF_LED_POLARITY; 1811 if (config & CFG_XMAC_XIF_SEL_POR_CLK_SRC) 1812 val |= XMAC_XIF_SEL_POR_CLK_SRC; 1813 if (config & CFG_XMAC_XIF_TX_OUTPUT) 1814 val |= XMAC_XIF_TX_OUTPUT_EN; 1815 1816 if (config & CFG_XMAC_XIF_LOOPBACK) { 1817 val &= ~XMAC_XIF_SEL_POR_CLK_SRC; 1818 val |= XMAC_XIF_LOOPBACK; 1819 } 1820 1821 if (config & CFG_XMAC_XIF_LFS) 1822 val &= ~XMAC_XIF_LFS_DISABLE; 1823 if (config & CFG_XMAC_XIF_XPCS_BYPASS) 1824 val |= XMAC_XIF_XPCS_BYPASS; 1825 if (config & CFG_XMAC_XIF_1G_PCS_BYPASS) 1826 val |= XMAC_XIF_1G_PCS_BYPASS; 1827 if (config & CFG_XMAC_XIF_SEL_CLK_25MHZ) 1828 val |= XMAC_XIF_SEL_CLK_25MHZ; 1829 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1830 1831 } else { 1832 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1833 if (config & CFG_XMAC_XIF_LED_FORCE) 1834 val &= ~XMAC_XIF_FORCE_LED_ON; 1835 if (config & CFG_XMAC_XIF_LED_POLARITY) 1836 val &= ~XMAC_XIF_LED_POLARITY; 1837 if (config & CFG_XMAC_XIF_SEL_POR_CLK_SRC) 1838 val &= ~XMAC_XIF_SEL_POR_CLK_SRC; 1839 if (config & CFG_XMAC_XIF_TX_OUTPUT) 1840 val &= ~XMAC_XIF_TX_OUTPUT_EN; 1841 if (config & CFG_XMAC_XIF_LOOPBACK) 1842 val &= ~XMAC_XIF_LOOPBACK; 1843 if (config & CFG_XMAC_XIF_LFS) 1844 val |= XMAC_XIF_LFS_DISABLE; 1845 if (config & CFG_XMAC_XIF_XPCS_BYPASS) 1846 val &= ~XMAC_XIF_XPCS_BYPASS; 1847 if (config & CFG_XMAC_XIF_1G_PCS_BYPASS) 1848 val &= ~XMAC_XIF_1G_PCS_BYPASS; 1849 if (config & CFG_XMAC_XIF_SEL_CLK_25MHZ) 1850 val &= ~XMAC_XIF_SEL_CLK_25MHZ; 1851 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1852 } 1853 break; 1854 case INIT: 1855 ASSERT((config & ~CFG_XMAC_XIF_ALL) == 0); 1856 if ((config & ~CFG_XMAC_XIF_ALL) != 0) { 1857 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1858 " npi_xmac_xif_config" 1859 " Invalid Input: config <0x%x>", 1860 config)); 1861 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 1862 } 1863 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1864 1865 if (config & CFG_XMAC_XIF_LED_FORCE) 1866 val |= XMAC_XIF_FORCE_LED_ON; 1867 else 1868 val &= ~XMAC_XIF_FORCE_LED_ON; 1869 if (config & CFG_XMAC_XIF_LED_POLARITY) 1870 val |= XMAC_XIF_LED_POLARITY; 1871 else 1872 val &= ~XMAC_XIF_LED_POLARITY; 1873 if (config & CFG_XMAC_XIF_SEL_POR_CLK_SRC) 1874 val |= XMAC_XIF_SEL_POR_CLK_SRC; 1875 else 1876 val &= ~XMAC_XIF_SEL_POR_CLK_SRC; 1877 if (config & CFG_XMAC_XIF_TX_OUTPUT) 1878 val |= XMAC_XIF_TX_OUTPUT_EN; 1879 else 1880 val &= ~XMAC_XIF_TX_OUTPUT_EN; 1881 1882 if (config & CFG_XMAC_XIF_LOOPBACK) { 1883 val &= ~XMAC_XIF_SEL_POR_CLK_SRC; 1884 val |= XMAC_XIF_LOOPBACK; 1885 #ifdef AXIS_DEBUG_LB 1886 val |= XMAC_RX_MAC2IPP_PKT_CNT_EN; 1887 #endif 1888 } else { 1889 val &= ~XMAC_XIF_LOOPBACK; 1890 } 1891 1892 if (config & CFG_XMAC_XIF_LFS) 1893 val &= ~XMAC_XIF_LFS_DISABLE; 1894 else 1895 val |= XMAC_XIF_LFS_DISABLE; 1896 if (config & CFG_XMAC_XIF_XPCS_BYPASS) 1897 val |= XMAC_XIF_XPCS_BYPASS; 1898 else 1899 val &= ~XMAC_XIF_XPCS_BYPASS; 1900 if (config & CFG_XMAC_XIF_1G_PCS_BYPASS) 1901 val |= XMAC_XIF_1G_PCS_BYPASS; 1902 else 1903 val &= ~XMAC_XIF_1G_PCS_BYPASS; 1904 if (config & CFG_XMAC_XIF_SEL_CLK_25MHZ) 1905 val |= XMAC_XIF_SEL_CLK_25MHZ; 1906 else 1907 val &= ~XMAC_XIF_SEL_CLK_25MHZ; 1908 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1909 1910 break; 1911 default: 1912 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1913 " npi_xmac_xif_config" 1914 " Invalid Input: op <0x%x>", op)); 1915 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 1916 } 1917 1918 return (NPI_SUCCESS); 1919 } 1920 1921 npi_status_t 1922 npi_xmac_tx_config(npi_handle_t handle, config_op_t op, uint8_t portn, 1923 xmac_tx_config_t config) 1924 { 1925 uint64_t val = 0; 1926 1927 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 1928 1929 switch (op) { 1930 case ENABLE: 1931 case DISABLE: 1932 ASSERT((config != 0) && ((config & ~CFG_XMAC_TX_ALL) == 0)); 1933 if ((config == 0) || (config & ~CFG_XMAC_TX_ALL) != 0) { 1934 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1935 " npi_xmac_tx_config" 1936 " Invalid Input: config <0x%x>", 1937 config)); 1938 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 1939 } 1940 if (op == ENABLE) { 1941 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1942 if (config & CFG_XMAC_TX) 1943 val |= XMAC_TX_CFG_TX_ENABLE; 1944 if (config & CFG_XMAC_TX_STRETCH_MODE) 1945 val |= XMAC_TX_CFG_STRETCH_MD; 1946 if (config & CFG_XMAC_VAR_IPG) 1947 val |= XMAC_TX_CFG_VAR_MIN_IPG_EN; 1948 if (config & CFG_XMAC_TX_CRC) 1949 val &= ~XMAC_TX_CFG_ALWAYS_NO_CRC; 1950 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1951 } else { 1952 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1953 if (config & CFG_XMAC_TX) 1954 val &= ~XMAC_TX_CFG_TX_ENABLE; 1955 if (config & CFG_XMAC_TX_STRETCH_MODE) 1956 val &= ~XMAC_TX_CFG_STRETCH_MD; 1957 if (config & CFG_XMAC_VAR_IPG) 1958 val &= ~XMAC_TX_CFG_VAR_MIN_IPG_EN; 1959 if (config & CFG_XMAC_TX_CRC) 1960 val |= XMAC_TX_CFG_ALWAYS_NO_CRC; 1961 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1962 } 1963 break; 1964 case INIT: 1965 ASSERT((config & ~CFG_XMAC_TX_ALL) == 0); 1966 if ((config & ~CFG_XMAC_TX_ALL) != 0) { 1967 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1968 " npi_xmac_tx_config" 1969 " Invalid Input: config <0x%x>", 1970 config)); 1971 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 1972 } 1973 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1974 if (config & CFG_XMAC_TX) 1975 val |= XMAC_TX_CFG_TX_ENABLE; 1976 else 1977 val &= ~XMAC_TX_CFG_TX_ENABLE; 1978 if (config & CFG_XMAC_TX_STRETCH_MODE) 1979 val |= XMAC_TX_CFG_STRETCH_MD; 1980 else 1981 val &= ~XMAC_TX_CFG_STRETCH_MD; 1982 if (config & CFG_XMAC_VAR_IPG) 1983 val |= XMAC_TX_CFG_VAR_MIN_IPG_EN; 1984 else 1985 val &= ~XMAC_TX_CFG_VAR_MIN_IPG_EN; 1986 if (config & CFG_XMAC_TX_CRC) 1987 val &= ~XMAC_TX_CFG_ALWAYS_NO_CRC; 1988 else 1989 val |= XMAC_TX_CFG_ALWAYS_NO_CRC; 1990 1991 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1992 break; 1993 default: 1994 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1995 " npi_xmac_tx_config" 1996 " Invalid Input: op <0x%x>", 1997 op)); 1998 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 1999 } 2000 2001 return (NPI_SUCCESS); 2002 } 2003 2004 npi_status_t 2005 npi_xmac_rx_config(npi_handle_t handle, config_op_t op, uint8_t portn, 2006 xmac_rx_config_t config) 2007 { 2008 uint64_t val = 0; 2009 2010 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2011 2012 switch (op) { 2013 case ENABLE: 2014 case DISABLE: 2015 ASSERT((config != 0) && ((config & ~CFG_XMAC_RX_ALL) == 0)); 2016 if ((config == 0) || (config & ~CFG_XMAC_RX_ALL) != 0) { 2017 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2018 " npi_xmac_rx_config" 2019 " Invalid Input: config <0x%x>", 2020 config)); 2021 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2022 } 2023 if (op == ENABLE) { 2024 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 2025 if (config & CFG_XMAC_RX) 2026 val |= XMAC_RX_CFG_RX_ENABLE; 2027 if (config & CFG_XMAC_RX_PROMISCUOUS) 2028 val |= XMAC_RX_CFG_PROMISC; 2029 if (config & CFG_XMAC_RX_PROMISCUOUSGROUP) 2030 val |= XMAC_RX_CFG_PROMISC_GROUP; 2031 if (config & CFG_XMAC_RX_ERRCHK) 2032 val &= ~XMAC_RX_CFG_ERR_CHK_DISABLE; 2033 if (config & CFG_XMAC_RX_CRC_CHK) 2034 val &= ~XMAC_RX_CFG_CRC_CHK_DISABLE; 2035 if (config & CFG_XMAC_RX_RESV_MULTICAST) 2036 val |= XMAC_RX_CFG_RESERVED_MCAST; 2037 if (config & CFG_XMAC_RX_CODE_VIO_CHK) 2038 val &= ~XMAC_RX_CFG_CD_VIO_CHK; 2039 if (config & CFG_XMAC_RX_HASH_FILTER) 2040 val |= XMAC_RX_CFG_HASH_FILTER_EN; 2041 if (config & CFG_XMAC_RX_ADDR_FILTER) 2042 val |= XMAC_RX_CFG_ADDR_FILTER_EN; 2043 if (config & CFG_XMAC_RX_STRIP_CRC) 2044 val |= XMAC_RX_CFG_STRIP_CRC; 2045 if (config & CFG_XMAC_RX_PAUSE) 2046 val |= XMAC_RX_CFG_RX_PAUSE_EN; 2047 if (config & CFG_XMAC_RX_PASS_FC_FRAME) 2048 val |= XMAC_RX_CFG_PASS_FLOW_CTRL; 2049 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 2050 } else { 2051 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 2052 if (config & CFG_XMAC_RX) 2053 val &= ~XMAC_RX_CFG_RX_ENABLE; 2054 if (config & CFG_XMAC_RX_PROMISCUOUS) 2055 val &= ~XMAC_RX_CFG_PROMISC; 2056 if (config & CFG_XMAC_RX_PROMISCUOUSGROUP) 2057 val &= ~XMAC_RX_CFG_PROMISC_GROUP; 2058 if (config & CFG_XMAC_RX_ERRCHK) 2059 val |= XMAC_RX_CFG_ERR_CHK_DISABLE; 2060 if (config & CFG_XMAC_RX_CRC_CHK) 2061 val |= XMAC_RX_CFG_CRC_CHK_DISABLE; 2062 if (config & CFG_XMAC_RX_RESV_MULTICAST) 2063 val &= ~XMAC_RX_CFG_RESERVED_MCAST; 2064 if (config & CFG_XMAC_RX_CODE_VIO_CHK) 2065 val |= XMAC_RX_CFG_CD_VIO_CHK; 2066 if (config & CFG_XMAC_RX_HASH_FILTER) 2067 val &= ~XMAC_RX_CFG_HASH_FILTER_EN; 2068 if (config & CFG_XMAC_RX_ADDR_FILTER) 2069 val &= ~XMAC_RX_CFG_ADDR_FILTER_EN; 2070 if (config & CFG_XMAC_RX_STRIP_CRC) 2071 val &= ~XMAC_RX_CFG_STRIP_CRC; 2072 if (config & CFG_XMAC_RX_PAUSE) 2073 val &= ~XMAC_RX_CFG_RX_PAUSE_EN; 2074 if (config & CFG_XMAC_RX_PASS_FC_FRAME) 2075 val &= ~XMAC_RX_CFG_PASS_FLOW_CTRL; 2076 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 2077 } 2078 break; 2079 case INIT: 2080 ASSERT((config & ~CFG_XMAC_RX_ALL) == 0); 2081 if ((config & ~CFG_XMAC_RX_ALL) != 0) { 2082 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2083 " npi_xmac_rx_config" 2084 " Invalid Input: config <0x%x>", 2085 config)); 2086 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2087 } 2088 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 2089 if (config & CFG_XMAC_RX) 2090 val |= XMAC_RX_CFG_RX_ENABLE; 2091 else 2092 val &= ~XMAC_RX_CFG_RX_ENABLE; 2093 if (config & CFG_XMAC_RX_PROMISCUOUS) 2094 val |= XMAC_RX_CFG_PROMISC; 2095 else 2096 val &= ~XMAC_RX_CFG_PROMISC; 2097 if (config & CFG_XMAC_RX_PROMISCUOUSGROUP) 2098 val |= XMAC_RX_CFG_PROMISC_GROUP; 2099 else 2100 val &= ~XMAC_RX_CFG_PROMISC_GROUP; 2101 if (config & CFG_XMAC_RX_ERRCHK) 2102 val &= ~XMAC_RX_CFG_ERR_CHK_DISABLE; 2103 else 2104 val |= XMAC_RX_CFG_ERR_CHK_DISABLE; 2105 if (config & CFG_XMAC_RX_CRC_CHK) 2106 val &= ~XMAC_RX_CFG_CRC_CHK_DISABLE; 2107 else 2108 val |= XMAC_RX_CFG_CRC_CHK_DISABLE; 2109 if (config & CFG_XMAC_RX_RESV_MULTICAST) 2110 val |= XMAC_RX_CFG_RESERVED_MCAST; 2111 else 2112 val &= ~XMAC_RX_CFG_RESERVED_MCAST; 2113 if (config & CFG_XMAC_RX_CODE_VIO_CHK) 2114 val &= ~XMAC_RX_CFG_CD_VIO_CHK; 2115 else 2116 val |= XMAC_RX_CFG_CD_VIO_CHK; 2117 if (config & CFG_XMAC_RX_HASH_FILTER) 2118 val |= XMAC_RX_CFG_HASH_FILTER_EN; 2119 else 2120 val &= ~XMAC_RX_CFG_HASH_FILTER_EN; 2121 if (config & CFG_XMAC_RX_ADDR_FILTER) 2122 val |= XMAC_RX_CFG_ADDR_FILTER_EN; 2123 else 2124 val &= ~XMAC_RX_CFG_ADDR_FILTER_EN; 2125 if (config & CFG_XMAC_RX_PAUSE) 2126 val |= XMAC_RX_CFG_RX_PAUSE_EN; 2127 else 2128 val &= ~XMAC_RX_CFG_RX_PAUSE_EN; 2129 if (config & CFG_XMAC_RX_STRIP_CRC) 2130 val |= XMAC_RX_CFG_STRIP_CRC; 2131 else 2132 val &= ~XMAC_RX_CFG_STRIP_CRC; 2133 if (config & CFG_XMAC_RX_PASS_FC_FRAME) 2134 val |= XMAC_RX_CFG_PASS_FLOW_CTRL; 2135 else 2136 val &= ~XMAC_RX_CFG_PASS_FLOW_CTRL; 2137 2138 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 2139 break; 2140 default: 2141 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2142 " npi_xmac_rx_config" 2143 " Invalid Input: op <0x%x>", op)); 2144 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2145 } 2146 2147 return (NPI_SUCCESS); 2148 } 2149 2150 npi_status_t 2151 npi_xmac_tx_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2152 xmac_tx_iconfig_t iconfig) 2153 { 2154 uint64_t val = 0; 2155 2156 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2157 2158 switch (op) { 2159 case ENABLE: 2160 case DISABLE: 2161 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_XMAC_TX_ALL) == 0)); 2162 if ((iconfig == 0) || (iconfig & ~ICFG_XMAC_TX_ALL) != 0) { 2163 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2164 " npi_xmac_tx_iconfig" 2165 " Invalid Input: iconfig <0x%x>", 2166 iconfig)); 2167 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2168 } 2169 XMAC_REG_RD(handle, portn, XTXMAC_STAT_MSK_REG, &val); 2170 if (op == ENABLE) 2171 val &= ~iconfig; 2172 else 2173 val |= iconfig; 2174 XMAC_REG_WR(handle, portn, XTXMAC_STAT_MSK_REG, val); 2175 2176 break; 2177 case INIT: 2178 ASSERT((iconfig & ~ICFG_XMAC_TX_ALL) == 0); 2179 if ((iconfig & ~ICFG_XMAC_TX_ALL) != 0) { 2180 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2181 " npi_xmac_tx_iconfig" 2182 " Invalid Input: iconfig <0x%x>", 2183 iconfig)); 2184 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2185 } 2186 XMAC_REG_WR(handle, portn, XTXMAC_STAT_MSK_REG, ~iconfig); 2187 2188 break; 2189 default: 2190 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2191 " npi_xmac_tx_iconfig" 2192 " Invalid Input: iconfig <0x%x>", 2193 iconfig)); 2194 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2195 } 2196 2197 return (NPI_SUCCESS); 2198 } 2199 2200 npi_status_t 2201 npi_xmac_rx_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2202 xmac_rx_iconfig_t iconfig) 2203 { 2204 uint64_t val = 0; 2205 2206 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2207 2208 switch (op) { 2209 case ENABLE: 2210 case DISABLE: 2211 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_XMAC_RX_ALL) == 0)); 2212 if ((iconfig == 0) || (iconfig & ~ICFG_XMAC_RX_ALL) != 0) { 2213 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2214 " npi_xmac_rx_iconfig" 2215 " Invalid Input: iconfig <0x%x>", 2216 iconfig)); 2217 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2218 } 2219 XMAC_REG_RD(handle, portn, XRXMAC_STAT_MSK_REG, &val); 2220 if (op == ENABLE) 2221 val &= ~iconfig; 2222 else 2223 val |= iconfig; 2224 XMAC_REG_WR(handle, portn, XRXMAC_STAT_MSK_REG, val); 2225 2226 break; 2227 case INIT: 2228 ASSERT((iconfig & ~ICFG_XMAC_RX_ALL) == 0); 2229 if ((iconfig & ~ICFG_XMAC_RX_ALL) != 0) { 2230 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2231 " npi_xmac_rx_iconfig" 2232 " Invalid Input: iconfig <0x%x>", 2233 iconfig)); 2234 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2235 } 2236 XMAC_REG_WR(handle, portn, XRXMAC_STAT_MSK_REG, ~iconfig); 2237 2238 break; 2239 default: 2240 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2241 " npi_xmac_rx_iconfig" 2242 " Invalid Input: iconfig <0x%x>", 2243 iconfig)); 2244 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2245 } 2246 2247 return (NPI_SUCCESS); 2248 } 2249 2250 npi_status_t 2251 npi_xmac_ctl_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2252 xmac_ctl_iconfig_t iconfig) 2253 { 2254 uint64_t val = 0; 2255 2256 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2257 2258 switch (op) { 2259 case ENABLE: 2260 case DISABLE: 2261 ASSERT((iconfig != 0) && \ 2262 ((iconfig & ~ICFG_XMAC_CTRL_ALL) == 0)); 2263 if ((iconfig == 0) || (iconfig & ~ICFG_XMAC_CTRL_ALL) != 0) { 2264 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2265 " npi_xmac_ctl_iconfig" 2266 " Invalid Input: iconfig <0x%x>", 2267 iconfig)); 2268 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2269 } 2270 XMAC_REG_RD(handle, portn, XMAC_C_S_MSK_REG, &val); 2271 if (op == ENABLE) 2272 val &= ~iconfig; 2273 else 2274 val |= iconfig; 2275 XMAC_REG_WR(handle, portn, XMAC_C_S_MSK_REG, val); 2276 2277 break; 2278 case INIT: 2279 ASSERT((iconfig & ~ICFG_XMAC_CTRL_ALL) == 0); 2280 if ((iconfig & ~ICFG_XMAC_CTRL_ALL) != 0) { 2281 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2282 " npi_xmac_ctl_iconfig" 2283 " Invalid Input: iconfig <0x%x>", 2284 iconfig)); 2285 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2286 } 2287 XMAC_REG_WR(handle, portn, XMAC_C_S_MSK_REG, ~iconfig); 2288 2289 break; 2290 default: 2291 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2292 " npi_xmac_ctl_iconfig" 2293 " Invalid Input: iconfig <0x%x>", 2294 iconfig)); 2295 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2296 } 2297 2298 return (NPI_SUCCESS); 2299 } 2300 2301 npi_status_t 2302 npi_xmac_tx_get_istatus(npi_handle_t handle, uint8_t portn, 2303 xmac_tx_iconfig_t *istatus) 2304 { 2305 uint64_t val; 2306 2307 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2308 2309 XMAC_REG_RD(handle, portn, XTXMAC_STATUS_REG, &val); 2310 *istatus = (uint32_t)val; 2311 2312 return (NPI_SUCCESS); 2313 } 2314 2315 npi_status_t 2316 npi_xmac_rx_get_istatus(npi_handle_t handle, uint8_t portn, 2317 xmac_rx_iconfig_t *istatus) 2318 { 2319 uint64_t val; 2320 2321 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2322 2323 XMAC_REG_RD(handle, portn, XRXMAC_STATUS_REG, &val); 2324 *istatus = (uint32_t)val; 2325 2326 return (NPI_SUCCESS); 2327 } 2328 2329 npi_status_t 2330 npi_xmac_ctl_get_istatus(npi_handle_t handle, uint8_t portn, 2331 xmac_ctl_iconfig_t *istatus) 2332 { 2333 uint64_t val; 2334 2335 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2336 2337 XMAC_REG_RD(handle, portn, XMAC_CTRL_STAT_REG, &val); 2338 *istatus = (uint32_t)val; 2339 2340 return (NPI_SUCCESS); 2341 } 2342 2343 npi_status_t 2344 npi_xmac_xpcs_reset(npi_handle_t handle, uint8_t portn) 2345 { 2346 uint64_t val; 2347 2348 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2349 2350 XPCS_REG_RD(handle, portn, XPCS_CTRL_1_REG, &val); 2351 val |= XPCS_CTRL1_RST; 2352 XPCS_REG_WR(handle, portn, XPCS_CTRL_1_REG, val); 2353 2354 return (NPI_SUCCESS); 2355 } 2356 2357 npi_status_t 2358 npi_xmac_xpcs_enable(npi_handle_t handle, uint8_t portn) 2359 { 2360 uint64_t val; 2361 2362 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2363 2364 XPCS_REG_RD(handle, portn, XPCS_CFG_VENDOR_1_REG, &val); 2365 val |= XPCS_CFG_XPCS_ENABLE; 2366 XPCS_REG_WR(handle, portn, XPCS_CFG_VENDOR_1_REG, val); 2367 2368 return (NPI_SUCCESS); 2369 } 2370 2371 npi_status_t 2372 npi_xmac_xpcs_disable(npi_handle_t handle, uint8_t portn) 2373 { 2374 uint64_t val; 2375 2376 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2377 2378 XPCS_REG_RD(handle, portn, XPCS_CFG_VENDOR_1_REG, &val); 2379 val &= ~XPCS_CFG_XPCS_ENABLE; 2380 XPCS_REG_WR(handle, portn, XPCS_CFG_VENDOR_1_REG, val); 2381 2382 return (NPI_SUCCESS); 2383 } 2384 2385 npi_status_t 2386 npi_xmac_xpcs_read(npi_handle_t handle, uint8_t portn, uint8_t xpcs_reg, 2387 uint32_t *value) 2388 { 2389 uint32_t reg; 2390 uint64_t val; 2391 2392 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2393 2394 switch (xpcs_reg) { 2395 case XPCS_REG_CONTROL1: 2396 reg = XPCS_CTRL_1_REG; 2397 break; 2398 case XPCS_REG_STATUS1: 2399 reg = XPCS_STATUS_1_REG; 2400 break; 2401 case XPCS_REG_DEVICE_ID: 2402 reg = XPCS_DEV_ID_REG; 2403 break; 2404 case XPCS_REG_SPEED_ABILITY: 2405 reg = XPCS_SPEED_ABILITY_REG; 2406 break; 2407 case XPCS_REG_DEVICE_IN_PKG: 2408 reg = XPCS_DEV_IN_PKG_REG; 2409 break; 2410 case XPCS_REG_CONTROL2: 2411 reg = XPCS_CTRL_2_REG; 2412 break; 2413 case XPCS_REG_STATUS2: 2414 reg = XPCS_STATUS_2_REG; 2415 break; 2416 case XPCS_REG_PKG_ID: 2417 reg = XPCS_PKG_ID_REG; 2418 break; 2419 case XPCS_REG_STATUS: 2420 reg = XPCS_STATUS_REG; 2421 break; 2422 case XPCS_REG_TEST_CONTROL: 2423 reg = XPCS_TEST_CTRL_REG; 2424 break; 2425 case XPCS_REG_CONFIG_VENDOR1: 2426 reg = XPCS_CFG_VENDOR_1_REG; 2427 break; 2428 case XPCS_REG_DIAG_VENDOR2: 2429 reg = XPCS_DIAG_VENDOR_2_REG; 2430 break; 2431 case XPCS_REG_MASK1: 2432 reg = XPCS_MASK_1_REG; 2433 break; 2434 case XPCS_REG_PACKET_COUNTER: 2435 reg = XPCS_PKT_CNTR_REG; 2436 break; 2437 case XPCS_REG_TX_STATEMACHINE: 2438 reg = XPCS_TX_STATE_MC_REG; 2439 break; 2440 case XPCS_REG_DESCWERR_COUNTER: 2441 reg = XPCS_DESKEW_ERR_CNTR_REG; 2442 break; 2443 case XPCS_REG_SYMBOL_ERR_L0_1_COUNTER: 2444 reg = XPCS_SYM_ERR_CNTR_L0_L1_REG; 2445 break; 2446 case XPCS_REG_SYMBOL_ERR_L2_3_COUNTER: 2447 reg = XPCS_SYM_ERR_CNTR_L2_L3_REG; 2448 break; 2449 case XPCS_REG_TRAINING_VECTOR: 2450 reg = XPCS_TRAINING_VECTOR_REG; 2451 break; 2452 default: 2453 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2454 " npi_xmac_xpcs_read" 2455 " Invalid Input: xpcs_reg <0x%x>", 2456 xpcs_reg)); 2457 return (NPI_FAILURE | NPI_MAC_REG_INVALID(portn)); 2458 } 2459 XPCS_REG_RD(handle, portn, reg, &val); 2460 *value = val & 0xFFFFFFFF; 2461 2462 return (NPI_SUCCESS); 2463 } 2464 2465 npi_status_t 2466 npi_xmac_xpcs_write(npi_handle_t handle, uint8_t portn, uint8_t xpcs_reg, 2467 uint32_t value) 2468 { 2469 uint32_t reg; 2470 uint64_t val; 2471 2472 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2473 2474 switch (xpcs_reg) { 2475 case XPCS_REG_CONTROL1: 2476 reg = XPCS_CTRL_1_REG; 2477 break; 2478 case XPCS_REG_TEST_CONTROL: 2479 reg = XPCS_TEST_CTRL_REG; 2480 break; 2481 case XPCS_REG_CONFIG_VENDOR1: 2482 reg = XPCS_CFG_VENDOR_1_REG; 2483 break; 2484 case XPCS_REG_DIAG_VENDOR2: 2485 reg = XPCS_DIAG_VENDOR_2_REG; 2486 break; 2487 case XPCS_REG_MASK1: 2488 reg = XPCS_MASK_1_REG; 2489 break; 2490 case XPCS_REG_PACKET_COUNTER: 2491 reg = XPCS_PKT_CNTR_REG; 2492 break; 2493 case XPCS_REG_DESCWERR_COUNTER: 2494 reg = XPCS_DESKEW_ERR_CNTR_REG; 2495 break; 2496 case XPCS_REG_TRAINING_VECTOR: 2497 reg = XPCS_TRAINING_VECTOR_REG; 2498 break; 2499 default: 2500 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2501 " npi_xmac_xpcs_write" 2502 " Invalid Input: xpcs_reg <0x%x>", 2503 xpcs_reg)); 2504 return (NPI_FAILURE | NPI_MAC_PCS_REG_INVALID(portn)); 2505 } 2506 val = value; 2507 2508 XPCS_REG_WR(handle, portn, reg, val); 2509 2510 return (NPI_SUCCESS); 2511 } 2512 2513 npi_status_t 2514 npi_bmac_reset(npi_handle_t handle, uint8_t portn, npi_mac_reset_t mode) 2515 { 2516 uint64_t val = 0; 2517 boolean_t txmac = B_FALSE; 2518 2519 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2520 2521 switch (mode) { 2522 case TX_MAC_RESET: 2523 BMAC_REG_WR(handle, portn, BTXMAC_SW_RST_REG, 0x1); 2524 BMAC_WAIT_REG(handle, portn, BTXMAC_SW_RST_REG, val); 2525 txmac = B_TRUE; 2526 break; 2527 case RX_MAC_RESET: 2528 BMAC_REG_WR(handle, portn, BRXMAC_SW_RST_REG, 0x1); 2529 BMAC_WAIT_REG(handle, portn, BRXMAC_SW_RST_REG, val); 2530 break; 2531 default: 2532 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2533 " npi_bmac_reset" 2534 " Invalid Input: mode <0x%x>", 2535 mode)); 2536 return (NPI_FAILURE | NPI_MAC_RESET_MODE_INVALID(portn)); 2537 } 2538 2539 if (val != 0) { 2540 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2541 " npi_bmac_reset" 2542 " BMAC_RESET HW Error: ret <0x%x>", 2543 val)); 2544 if (txmac) 2545 return (NPI_FAILURE | NPI_TXMAC_RESET_FAILED(portn)); 2546 else 2547 return (NPI_FAILURE | NPI_RXMAC_RESET_FAILED(portn)); 2548 } 2549 2550 return (NPI_SUCCESS); 2551 } 2552 2553 npi_status_t 2554 npi_mac_pcs_reset(npi_handle_t handle, uint8_t portn) 2555 { 2556 /* what to do here ? */ 2557 uint64_t val = 0; 2558 2559 ASSERT(IS_PORT_NUM_VALID(portn)); 2560 2561 PCS_REG_RD(handle, portn, PCS_MII_CTRL_REG, &val); 2562 val |= PCS_MII_RESET; 2563 PCS_REG_WR(handle, portn, PCS_MII_CTRL_REG, val); 2564 2565 return (NPI_SUCCESS); 2566 } 2567 2568 npi_status_t 2569 npi_mac_get_link_status(npi_handle_t handle, uint8_t portn, 2570 boolean_t *link_up) 2571 { 2572 uint64_t val; 2573 2574 ASSERT(IS_PORT_NUM_VALID(portn)); 2575 2576 PCS_REG_RD(handle, portn, PCS_MII_STATUS_REG, &val); 2577 2578 if (val & PCS_MII_STATUS_LINK_STATUS) { 2579 *link_up = B_TRUE; 2580 } else { 2581 *link_up = B_FALSE; 2582 } 2583 2584 return (NPI_SUCCESS); 2585 } 2586 2587 npi_status_t 2588 npi_bmac_tx_config(npi_handle_t handle, config_op_t op, uint8_t portn, 2589 bmac_tx_config_t config) 2590 { 2591 uint64_t val = 0; 2592 2593 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2594 2595 switch (op) { 2596 case ENABLE: 2597 case DISABLE: 2598 ASSERT((config != 0) && ((config & ~CFG_BMAC_TX_ALL) == 0)); 2599 if ((config == 0) || (config & ~CFG_BMAC_TX_ALL) != 0) { 2600 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2601 " npi_bmac_tx_config" 2602 " Invalid Input: config <0x%x>", 2603 config)); 2604 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2605 } 2606 if (op == ENABLE) { 2607 BMAC_REG_RD(handle, portn, TXMAC_CONFIG_REG, &val); 2608 if (config & CFG_BMAC_TX) 2609 val |= MAC_TX_CFG_TXMAC_ENABLE; 2610 if (config & CFG_BMAC_TX_CRC) 2611 val &= ~MAC_TX_CFG_NO_FCS; 2612 BMAC_REG_WR(handle, portn, TXMAC_CONFIG_REG, val); 2613 } else { 2614 BMAC_REG_RD(handle, portn, TXMAC_CONFIG_REG, &val); 2615 if (config & CFG_BMAC_TX) 2616 val &= ~MAC_TX_CFG_TXMAC_ENABLE; 2617 if (config & CFG_BMAC_TX_CRC) 2618 val |= MAC_TX_CFG_NO_FCS; 2619 BMAC_REG_WR(handle, portn, TXMAC_CONFIG_REG, val); 2620 } 2621 break; 2622 case INIT: 2623 ASSERT((config & ~CFG_BMAC_TX_ALL) == 0); 2624 if ((config & ~CFG_BMAC_TX_ALL) != 0) { 2625 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2626 " npi_bmac_tx_config" 2627 " Invalid Input: config <0x%x>", 2628 config)); 2629 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2630 } 2631 BMAC_REG_RD(handle, portn, TXMAC_CONFIG_REG, &val); 2632 if (config & CFG_BMAC_TX) 2633 val |= MAC_TX_CFG_TXMAC_ENABLE; 2634 else 2635 val &= ~MAC_TX_CFG_TXMAC_ENABLE; 2636 if (config & CFG_BMAC_TX_CRC) 2637 val &= ~MAC_TX_CFG_NO_FCS; 2638 else 2639 val |= MAC_TX_CFG_NO_FCS; 2640 BMAC_REG_WR(handle, portn, TXMAC_CONFIG_REG, val); 2641 break; 2642 default: 2643 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2644 " npi_bmac_tx_config" 2645 " Invalid Input: op <0x%x>", 2646 op)); 2647 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2648 } 2649 2650 return (NPI_SUCCESS); 2651 } 2652 2653 npi_status_t 2654 npi_bmac_rx_config(npi_handle_t handle, config_op_t op, uint8_t portn, 2655 bmac_rx_config_t config) 2656 { 2657 uint64_t val = 0; 2658 2659 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2660 2661 switch (op) { 2662 case ENABLE: 2663 case DISABLE: 2664 ASSERT((config != 0) && ((config & ~CFG_BMAC_RX_ALL) == 0)); 2665 if ((config == 0) || (config & ~CFG_BMAC_RX_ALL) != 0) { 2666 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2667 " npi_bmac_rx_config" 2668 " Invalid Input: config <0x%x>", 2669 config)); 2670 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2671 } 2672 if (op == ENABLE) { 2673 BMAC_REG_RD(handle, portn, RXMAC_CONFIG_REG, &val); 2674 if (config & CFG_BMAC_RX) 2675 val |= MAC_RX_CFG_RXMAC_ENABLE; 2676 if (config & CFG_BMAC_RX_STRIP_PAD) 2677 val |= MAC_RX_CFG_STRIP_PAD; 2678 if (config & CFG_BMAC_RX_STRIP_CRC) 2679 val |= MAC_RX_CFG_STRIP_FCS; 2680 if (config & CFG_BMAC_RX_PROMISCUOUS) 2681 val |= MAC_RX_CFG_PROMISC; 2682 if (config & CFG_BMAC_RX_PROMISCUOUSGROUP) 2683 val |= MAC_RX_CFG_PROMISC_GROUP; 2684 if (config & CFG_BMAC_RX_HASH_FILTER) 2685 val |= MAC_RX_CFG_HASH_FILTER_EN; 2686 if (config & CFG_BMAC_RX_ADDR_FILTER) 2687 val |= MAC_RX_CFG_ADDR_FILTER_EN; 2688 if (config & CFG_BMAC_RX_DISCARD_ON_ERR) 2689 val &= ~MAC_RX_CFG_DISABLE_DISCARD; 2690 BMAC_REG_WR(handle, portn, RXMAC_CONFIG_REG, val); 2691 } else { 2692 BMAC_REG_RD(handle, portn, RXMAC_CONFIG_REG, &val); 2693 if (config & CFG_BMAC_RX) 2694 val &= ~MAC_RX_CFG_RXMAC_ENABLE; 2695 if (config & CFG_BMAC_RX_STRIP_PAD) 2696 val &= ~MAC_RX_CFG_STRIP_PAD; 2697 if (config & CFG_BMAC_RX_STRIP_CRC) 2698 val &= ~MAC_RX_CFG_STRIP_FCS; 2699 if (config & CFG_BMAC_RX_PROMISCUOUS) 2700 val &= ~MAC_RX_CFG_PROMISC; 2701 if (config & CFG_BMAC_RX_PROMISCUOUSGROUP) 2702 val &= ~MAC_RX_CFG_PROMISC_GROUP; 2703 if (config & CFG_BMAC_RX_HASH_FILTER) 2704 val &= ~MAC_RX_CFG_HASH_FILTER_EN; 2705 if (config & CFG_BMAC_RX_ADDR_FILTER) 2706 val &= ~MAC_RX_CFG_ADDR_FILTER_EN; 2707 if (config & CFG_BMAC_RX_DISCARD_ON_ERR) 2708 val |= MAC_RX_CFG_DISABLE_DISCARD; 2709 BMAC_REG_WR(handle, portn, RXMAC_CONFIG_REG, val); 2710 } 2711 break; 2712 case INIT: 2713 ASSERT((config & ~CFG_BMAC_RX_ALL) == 0); 2714 if ((config & ~CFG_BMAC_RX_ALL) != 0) { 2715 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2716 " npi_bmac_rx_config" 2717 " Invalid Input: config <0x%x>", 2718 config)); 2719 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2720 } 2721 BMAC_REG_RD(handle, portn, RXMAC_CONFIG_REG, &val); 2722 if (config & CFG_BMAC_RX) 2723 val |= MAC_RX_CFG_RXMAC_ENABLE; 2724 else 2725 val &= ~MAC_RX_CFG_RXMAC_ENABLE; 2726 if (config & CFG_BMAC_RX_STRIP_PAD) 2727 val |= MAC_RX_CFG_STRIP_PAD; 2728 else 2729 val &= ~MAC_RX_CFG_STRIP_PAD; 2730 if (config & CFG_BMAC_RX_STRIP_CRC) 2731 val |= MAC_RX_CFG_STRIP_FCS; 2732 else 2733 val &= ~MAC_RX_CFG_STRIP_FCS; 2734 if (config & CFG_BMAC_RX_PROMISCUOUS) 2735 val |= MAC_RX_CFG_PROMISC; 2736 else 2737 val &= ~MAC_RX_CFG_PROMISC; 2738 if (config & CFG_BMAC_RX_PROMISCUOUSGROUP) 2739 val |= MAC_RX_CFG_PROMISC_GROUP; 2740 else 2741 val &= ~MAC_RX_CFG_PROMISC_GROUP; 2742 if (config & CFG_BMAC_RX_HASH_FILTER) 2743 val |= MAC_RX_CFG_HASH_FILTER_EN; 2744 else 2745 val &= ~MAC_RX_CFG_HASH_FILTER_EN; 2746 if (config & CFG_BMAC_RX_ADDR_FILTER) 2747 val |= MAC_RX_CFG_ADDR_FILTER_EN; 2748 else 2749 val &= ~MAC_RX_CFG_ADDR_FILTER_EN; 2750 if (config & CFG_BMAC_RX_DISCARD_ON_ERR) 2751 val &= ~MAC_RX_CFG_DISABLE_DISCARD; 2752 else 2753 val |= MAC_RX_CFG_DISABLE_DISCARD; 2754 2755 BMAC_REG_WR(handle, portn, RXMAC_CONFIG_REG, val); 2756 break; 2757 default: 2758 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2759 " npi_bmac_rx_config" 2760 " Invalid Input: op <0x%x>", op)); 2761 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2762 } 2763 2764 return (NPI_SUCCESS); 2765 } 2766 2767 npi_status_t 2768 npi_bmac_rx_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2769 bmac_rx_iconfig_t iconfig) 2770 { 2771 uint64_t val = 0; 2772 2773 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2774 2775 switch (op) { 2776 case ENABLE: 2777 case DISABLE: 2778 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_BMAC_RX_ALL) == 0)); 2779 if ((iconfig == 0) || (iconfig & ~ICFG_BMAC_RX_ALL) != 0) { 2780 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2781 " npi_bmac_rx_iconfig" 2782 " Invalid Input: iconfig <0x%x>", 2783 iconfig)); 2784 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2785 } 2786 BMAC_REG_RD(handle, portn, BRXMAC_STAT_MSK_REG, &val); 2787 if (op == ENABLE) 2788 val &= ~iconfig; 2789 else 2790 val |= iconfig; 2791 BMAC_REG_WR(handle, portn, BRXMAC_STAT_MSK_REG, val); 2792 2793 break; 2794 case INIT: 2795 ASSERT((iconfig & ~ICFG_BMAC_RX_ALL) == 0); 2796 if ((iconfig & ~ICFG_BMAC_RX_ALL) != 0) { 2797 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2798 " npi_bmac_rx_iconfig" 2799 " Invalid Input: iconfig <0x%x>", 2800 iconfig)); 2801 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2802 } 2803 BMAC_REG_WR(handle, portn, BRXMAC_STAT_MSK_REG, ~iconfig); 2804 2805 break; 2806 default: 2807 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2808 " npi_bmac_rx_iconfig" 2809 " Invalid Input: iconfig <0x%x>", 2810 iconfig)); 2811 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2812 } 2813 2814 return (NPI_SUCCESS); 2815 } 2816 2817 npi_status_t 2818 npi_bmac_xif_config(npi_handle_t handle, config_op_t op, uint8_t portn, 2819 bmac_xif_config_t config) 2820 { 2821 uint64_t val = 0; 2822 2823 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2824 2825 switch (op) { 2826 case ENABLE: 2827 case DISABLE: 2828 ASSERT((config != 0) && ((config & ~CFG_BMAC_XIF_ALL) == 0)); 2829 if ((config == 0) || (config & ~CFG_BMAC_XIF_ALL) != 0) { 2830 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2831 " npi_bmac_xif_config" 2832 " Invalid Input: config <0x%x>", 2833 config)); 2834 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2835 } 2836 if (op == ENABLE) { 2837 BMAC_REG_RD(handle, portn, MAC_XIF_CONFIG_REG, &val); 2838 if (config & CFG_BMAC_XIF_TX_OUTPUT) 2839 val |= MAC_XIF_TX_OUTPUT_EN; 2840 if (config & CFG_BMAC_XIF_LOOPBACK) 2841 val |= MAC_XIF_MII_INT_LOOPBACK; 2842 if (config & CFG_BMAC_XIF_GMII_MODE) 2843 val |= MAC_XIF_GMII_MODE; 2844 if (config & CFG_BMAC_XIF_LINKLED) 2845 val |= MAC_XIF_LINK_LED; 2846 if (config & CFG_BMAC_XIF_LED_POLARITY) 2847 val |= MAC_XIF_LED_POLARITY; 2848 if (config & CFG_BMAC_XIF_SEL_CLK_25MHZ) 2849 val |= MAC_XIF_SEL_CLK_25MHZ; 2850 BMAC_REG_WR(handle, portn, MAC_XIF_CONFIG_REG, val); 2851 } else { 2852 BMAC_REG_RD(handle, portn, MAC_XIF_CONFIG_REG, &val); 2853 if (config & CFG_BMAC_XIF_TX_OUTPUT) 2854 val &= ~MAC_XIF_TX_OUTPUT_EN; 2855 if (config & CFG_BMAC_XIF_LOOPBACK) 2856 val &= ~MAC_XIF_MII_INT_LOOPBACK; 2857 if (config & CFG_BMAC_XIF_GMII_MODE) 2858 val &= ~MAC_XIF_GMII_MODE; 2859 if (config & CFG_BMAC_XIF_LINKLED) 2860 val &= ~MAC_XIF_LINK_LED; 2861 if (config & CFG_BMAC_XIF_LED_POLARITY) 2862 val &= ~MAC_XIF_LED_POLARITY; 2863 if (config & CFG_BMAC_XIF_SEL_CLK_25MHZ) 2864 val &= ~MAC_XIF_SEL_CLK_25MHZ; 2865 BMAC_REG_WR(handle, portn, MAC_XIF_CONFIG_REG, val); 2866 } 2867 break; 2868 case INIT: 2869 ASSERT((config & ~CFG_BMAC_XIF_ALL) == 0); 2870 if ((config & ~CFG_BMAC_XIF_ALL) != 0) { 2871 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2872 " npi_bmac_xif_config" 2873 " Invalid Input: config <0x%x>", 2874 config)); 2875 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2876 } 2877 BMAC_REG_RD(handle, portn, MAC_XIF_CONFIG_REG, &val); 2878 if (config & CFG_BMAC_XIF_TX_OUTPUT) 2879 val |= MAC_XIF_TX_OUTPUT_EN; 2880 else 2881 val &= ~MAC_XIF_TX_OUTPUT_EN; 2882 if (config & CFG_BMAC_XIF_LOOPBACK) 2883 val |= MAC_XIF_MII_INT_LOOPBACK; 2884 else 2885 val &= ~MAC_XIF_MII_INT_LOOPBACK; 2886 if (config & CFG_BMAC_XIF_GMII_MODE) 2887 val |= MAC_XIF_GMII_MODE; 2888 else 2889 val &= ~MAC_XIF_GMII_MODE; 2890 if (config & CFG_BMAC_XIF_LINKLED) 2891 val |= MAC_XIF_LINK_LED; 2892 else 2893 val &= ~MAC_XIF_LINK_LED; 2894 if (config & CFG_BMAC_XIF_LED_POLARITY) 2895 val |= MAC_XIF_LED_POLARITY; 2896 else 2897 val &= ~MAC_XIF_LED_POLARITY; 2898 if (config & CFG_BMAC_XIF_SEL_CLK_25MHZ) 2899 val |= MAC_XIF_SEL_CLK_25MHZ; 2900 else 2901 val &= ~MAC_XIF_SEL_CLK_25MHZ; 2902 BMAC_REG_WR(handle, portn, MAC_XIF_CONFIG_REG, val); 2903 break; 2904 default: 2905 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2906 " npi_bmac_xif_config" 2907 " Invalid Input: op <0x%x>", 2908 op)); 2909 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2910 } 2911 2912 return (NPI_SUCCESS); 2913 } 2914 2915 npi_status_t 2916 npi_bmac_tx_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2917 bmac_tx_iconfig_t iconfig) 2918 { 2919 uint64_t val = 0; 2920 2921 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2922 2923 switch (op) { 2924 case ENABLE: 2925 case DISABLE: 2926 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_XMAC_TX_ALL) == 0)); 2927 if ((iconfig == 0) || (iconfig & ~ICFG_XMAC_TX_ALL) != 0) { 2928 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2929 " npi_bmac_tx_iconfig" 2930 " Invalid Input: iconfig <0x%x>", 2931 iconfig)); 2932 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2933 } 2934 BMAC_REG_RD(handle, portn, BTXMAC_STAT_MSK_REG, &val); 2935 if (op == ENABLE) 2936 val &= ~iconfig; 2937 else 2938 val |= iconfig; 2939 BMAC_REG_WR(handle, portn, BTXMAC_STAT_MSK_REG, val); 2940 2941 break; 2942 case INIT: 2943 ASSERT((iconfig & ~ICFG_XMAC_TX_ALL) == 0); 2944 if ((iconfig & ~ICFG_XMAC_TX_ALL) != 0) { 2945 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2946 " npi_bmac_tx_iconfig" 2947 " Invalid Input: iconfig <0x%x>", 2948 iconfig)); 2949 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2950 } 2951 BMAC_REG_WR(handle, portn, BTXMAC_STAT_MSK_REG, ~iconfig); 2952 2953 break; 2954 default: 2955 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2956 " npi_bmac_tx_iconfig" 2957 " Invalid Input: iconfig <0x%x>", 2958 iconfig)); 2959 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2960 } 2961 2962 return (NPI_SUCCESS); 2963 } 2964 2965 npi_status_t 2966 npi_bmac_ctl_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2967 bmac_ctl_iconfig_t iconfig) 2968 { 2969 uint64_t val = 0; 2970 2971 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2972 2973 switch (op) { 2974 case ENABLE: 2975 case DISABLE: 2976 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_BMAC_CTL_ALL) == 0)); 2977 if ((iconfig == 0) || (iconfig & ~ICFG_BMAC_CTL_ALL) != 0) { 2978 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2979 " npi_bmac_ctl_iconfig" 2980 " Invalid Input: iconfig <0x%x>", 2981 iconfig)); 2982 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2983 } 2984 BMAC_REG_RD(handle, portn, BMAC_C_S_MSK_REG, &val); 2985 if (op == ENABLE) 2986 val &= ~iconfig; 2987 else 2988 val |= iconfig; 2989 BMAC_REG_WR(handle, portn, BMAC_C_S_MSK_REG, val); 2990 2991 break; 2992 case INIT: 2993 ASSERT((iconfig & ~ICFG_BMAC_RX_ALL) == 0); 2994 if ((iconfig & ~ICFG_BMAC_RX_ALL) != 0) { 2995 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2996 " npi_bmac_ctl_iconfig" 2997 " Invalid Input: iconfig <0x%x>", 2998 iconfig)); 2999 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 3000 } 3001 BMAC_REG_WR(handle, portn, BMAC_C_S_MSK_REG, ~iconfig); 3002 3003 break; 3004 default: 3005 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3006 " npi_bmac_ctl_iconfig" 3007 " Invalid Input: iconfig <0x%x>", 3008 iconfig)); 3009 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 3010 } 3011 3012 return (NPI_SUCCESS); 3013 } 3014 3015 npi_status_t 3016 npi_bmac_tx_get_istatus(npi_handle_t handle, uint8_t portn, 3017 bmac_tx_iconfig_t *istatus) 3018 { 3019 uint64_t val = 0; 3020 3021 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 3022 3023 BMAC_REG_RD(handle, portn, BTXMAC_STATUS_REG, &val); 3024 *istatus = (uint32_t)val; 3025 3026 return (NPI_SUCCESS); 3027 } 3028 3029 npi_status_t 3030 npi_bmac_rx_get_istatus(npi_handle_t handle, uint8_t portn, 3031 bmac_rx_iconfig_t *istatus) 3032 { 3033 uint64_t val = 0; 3034 3035 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 3036 3037 BMAC_REG_RD(handle, portn, BRXMAC_STATUS_REG, &val); 3038 *istatus = (uint32_t)val; 3039 3040 return (NPI_SUCCESS); 3041 } 3042 3043 npi_status_t 3044 npi_bmac_ctl_get_istatus(npi_handle_t handle, uint8_t portn, 3045 bmac_ctl_iconfig_t *istatus) 3046 { 3047 uint64_t val = 0; 3048 3049 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 3050 3051 BMAC_REG_RD(handle, portn, BMAC_CTRL_STAT_REG, &val); 3052 *istatus = (uint32_t)val; 3053 3054 return (NPI_SUCCESS); 3055 } 3056 3057 npi_status_t 3058 npi_mac_mif_mdio_read(npi_handle_t handle, uint8_t portn, uint8_t device, 3059 uint16_t xcvr_reg, uint16_t *value) 3060 { 3061 mif_frame_t frame; 3062 uint_t delay; 3063 3064 frame.value = 0; 3065 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ 3066 frame.bits.w0.op = FRAME45_OP_ADDR; /* Select address */ 3067 frame.bits.w0.phyad = portn; /* Port number */ 3068 frame.bits.w0.regad = device; /* Device number */ 3069 frame.bits.w0.ta_msb = 1; 3070 frame.bits.w0.ta_lsb = 0; 3071 frame.bits.w0.data = xcvr_reg; /* register address */ 3072 3073 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3074 "mdio read port %d addr val=0x%x\n", portn, frame.value)); 3075 3076 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3077 3078 delay = 0; 3079 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); 3080 3081 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3082 "mdio read port %d addr poll=0x%x\n", portn, frame.value)); 3083 3084 if (delay == MIF_DELAY) { 3085 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3086 "mdio read no response1\n")); 3087 } 3088 3089 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ 3090 frame.bits.w0.op = FRAME45_OP_READ; /* Read */ 3091 frame.bits.w0.phyad = portn; /* Port Number */ 3092 frame.bits.w0.regad = device; /* Device Number */ 3093 frame.bits.w0.ta_msb = 1; 3094 frame.bits.w0.ta_lsb = 0; 3095 3096 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3097 "mdio read port %d data frame=0x%x\n", portn, frame.value)); 3098 3099 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3100 3101 delay = 0; 3102 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); 3103 3104 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3105 "mdio read port %d data poll=0x%x\n", portn, frame.value)); 3106 3107 *value = frame.bits.w0.data; 3108 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3109 "mdio read port=%d val=0x%x\n", portn, *value)); 3110 3111 if (delay == MIF_DELAY) { 3112 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3113 "mdio read no response2\n")); 3114 } 3115 3116 return (NPI_SUCCESS); 3117 } 3118 3119 npi_status_t 3120 npi_mac_mif_mii_read(npi_handle_t handle, uint8_t portn, uint8_t xcvr_reg, 3121 uint16_t *value) 3122 { 3123 mif_frame_t frame; 3124 uint_t delay; 3125 3126 frame.bits.w0.st = 0x1; /* Clause 22 */ 3127 frame.bits.w0.op = 0x2; 3128 frame.bits.w0.phyad = portn; 3129 frame.bits.w0.regad = xcvr_reg; 3130 frame.bits.w0.ta_msb = 1; 3131 frame.bits.w0.ta_lsb = 0; 3132 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3133 3134 delay = 0; 3135 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MAX_PIO_RETRIES); 3136 3137 if (delay == MAX_PIO_RETRIES) 3138 return (NPI_FAILURE | NPI_MAC_MII_READ_FAILED(portn)); 3139 3140 *value = frame.bits.w0.data; 3141 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3142 "mif mii read port %d reg=0x%x frame=0x%x\n", portn, 3143 xcvr_reg, frame.bits.w0.data)); 3144 3145 return (NPI_SUCCESS); 3146 } 3147 3148 npi_status_t 3149 npi_mac_mif_mdio_write(npi_handle_t handle, uint8_t portn, uint8_t device, 3150 uint16_t xcvr_reg, uint16_t value) 3151 { 3152 mif_frame_t frame; 3153 uint_t delay; 3154 3155 frame.value = 0; 3156 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ 3157 frame.bits.w0.op = FRAME45_OP_ADDR; /* Select Address */ 3158 frame.bits.w0.phyad = portn; /* Port Number */ 3159 frame.bits.w0.regad = device; /* Device Number */ 3160 frame.bits.w0.ta_msb = 1; 3161 frame.bits.w0.ta_lsb = 0; 3162 frame.bits.w0.data = xcvr_reg; /* register address */ 3163 3164 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3165 3166 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3167 "mdio write port %d addr val=0x%x\n", portn, frame.value)); 3168 3169 delay = 0; 3170 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); 3171 3172 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3173 "mdio write port %d addr poll=0x%x\n", portn, frame.value)); 3174 3175 if (delay == MIF_DELAY) { 3176 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3177 "mdio write no response1\n")); 3178 } 3179 3180 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ 3181 frame.bits.w0.op = FRAME45_OP_WRITE; /* Write */ 3182 frame.bits.w0.phyad = portn; /* Port number */ 3183 frame.bits.w0.regad = device; /* Device number */ 3184 frame.bits.w0.ta_msb = 1; 3185 frame.bits.w0.ta_lsb = 0; 3186 frame.bits.w0.data = value; 3187 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3188 3189 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3190 "mdio write port %d data val=0x%x\n", portn, frame.value)); 3191 3192 delay = 0; 3193 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); 3194 3195 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3196 "mdio write port %d data poll=0x%x\n", portn, frame.value)); 3197 3198 if (delay == MIF_DELAY) { 3199 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3200 "mdio write no response2\n")); 3201 } 3202 3203 return (NPI_SUCCESS); 3204 } 3205 3206 npi_status_t 3207 npi_mac_mif_mii_write(npi_handle_t handle, uint8_t portn, uint8_t xcvr_reg, 3208 uint16_t value) 3209 { 3210 mif_frame_t frame; 3211 uint_t delay; 3212 3213 frame.bits.w0.st = 0x1; /* Clause 22 */ 3214 frame.bits.w0.op = 0x1; 3215 frame.bits.w0.phyad = portn; 3216 frame.bits.w0.regad = xcvr_reg; 3217 frame.bits.w0.ta_msb = 1; 3218 frame.bits.w0.ta_lsb = 0; 3219 frame.bits.w0.data = value; 3220 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3221 3222 delay = 0; 3223 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MAX_PIO_RETRIES); 3224 3225 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3226 "mif mii write port %d reg=0x%x frame=0x%x\n", portn, 3227 xcvr_reg, frame.value)); 3228 3229 if (delay == MAX_PIO_RETRIES) 3230 return (NPI_FAILURE | NPI_MAC_MII_WRITE_FAILED(portn)); 3231 3232 return (NPI_SUCCESS); 3233 } 3234 3235 npi_status_t 3236 npi_mac_pcs_mii_read(npi_handle_t handle, uint8_t portn, uint8_t xcvr_reg, 3237 uint16_t *value) 3238 { 3239 pcs_anar_t pcs_anar; 3240 pcs_anar_t pcs_anlpar; 3241 pcs_stat_t pcs_stat; 3242 pcs_stat_mc_t pcs_stat_mc; 3243 mii_anar_t anar; 3244 mii_anar_t anlpar; 3245 mii_aner_t aner; 3246 mii_esr_t esr; 3247 mii_gsr_t gsr; 3248 uint64_t val = 0; 3249 3250 ASSERT(IS_PORT_NUM_VALID(portn)); 3251 3252 switch (xcvr_reg) { 3253 case MII_BMCR: 3254 PCS_REG_RD(handle, portn, PCS_MII_CTRL_REG, &val); 3255 *value = (uint16_t)val; 3256 break; 3257 case MII_BMSR: 3258 PCS_REG_RD(handle, portn, PCS_MII_STATUS_REG, &val); 3259 pcs_stat.value = val; 3260 PCS_REG_RD(handle, portn, PCS_STATE_MACHINE_REG, &val); 3261 pcs_stat_mc.value = val; 3262 if ((pcs_stat_mc.bits.w0.link_cfg_stat == 0xB) && 3263 (pcs_stat_mc.bits.w0.word_sync != 0)) { 3264 pcs_stat.bits.w0.link_stat = 1; 3265 } else if (pcs_stat_mc.bits.w0.link_cfg_stat != 0xB) { 3266 pcs_stat.bits.w0.link_stat = 0; 3267 } 3268 *value = (uint16_t)pcs_stat.value; 3269 break; 3270 case MII_ESR: 3271 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3272 pcs_anar.value = (uint16_t)val; 3273 esr.value = 0; 3274 esr.bits.link_1000fdx = pcs_anar.bits.w0.full_duplex; 3275 esr.bits.link_1000hdx = pcs_anar.bits.w0.half_duplex; 3276 *value = esr.value; 3277 break; 3278 case MII_ANAR: 3279 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3280 pcs_anar.value = (uint16_t)val; 3281 anar.value = 0; 3282 anar.bits.cap_pause = pcs_anar.bits.w0.pause; 3283 anar.bits.cap_asmpause = pcs_anar.bits.w0.asm_pause; 3284 *value = anar.value; 3285 break; 3286 case MII_ANLPAR: 3287 PCS_REG_RD(handle, portn, PCS_MII_LPA_REG, &val); 3288 pcs_anlpar.value = (uint16_t)val; 3289 anlpar.bits.cap_pause = pcs_anlpar.bits.w0.pause; 3290 anlpar.bits.cap_asmpause = pcs_anlpar.bits.w0.asm_pause; 3291 *value = anlpar.value; 3292 break; 3293 case MII_ANER: 3294 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3295 pcs_anar.value = (uint16_t)val; 3296 aner.value = 0; 3297 aner.bits.lp_an_able = pcs_anar.bits.w0.full_duplex | 3298 pcs_anar.bits.w0.half_duplex; 3299 *value = aner.value; 3300 break; 3301 case MII_GSR: 3302 PCS_REG_RD(handle, portn, PCS_MII_LPA_REG, &val); 3303 pcs_anar.value = (uint16_t)val; 3304 gsr.value = 0; 3305 gsr.bits.link_1000fdx = pcs_anar.bits.w0.full_duplex; 3306 gsr.bits.link_1000hdx = pcs_anar.bits.w0.half_duplex; 3307 *value = gsr.value; 3308 break; 3309 default: 3310 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3311 " npi_mac_pcs_mii_read" 3312 " Invalid Input: xcvr_reg <0x%x>", 3313 xcvr_reg)); 3314 return (NPI_FAILURE | NPI_MAC_REG_INVALID(portn)); 3315 } 3316 3317 return (NPI_SUCCESS); 3318 } 3319 3320 npi_status_t 3321 npi_mac_pcs_mii_write(npi_handle_t handle, uint8_t portn, uint8_t xcvr_reg, 3322 uint16_t value) 3323 { 3324 pcs_anar_t pcs_anar; 3325 mii_anar_t anar; 3326 mii_gcr_t gcr; 3327 uint64_t val; 3328 3329 ASSERT(IS_PORT_NUM_VALID(portn)); 3330 3331 switch (xcvr_reg) { 3332 case MII_BMCR: 3333 val = (uint16_t)value; 3334 PCS_REG_WR(handle, portn, PCS_MII_CTRL_REG, val); 3335 break; 3336 case MII_ANAR: 3337 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3338 pcs_anar.value = (uint16_t)val; 3339 anar.value = value; 3340 pcs_anar.bits.w0.asm_pause = anar.bits.cap_asmpause; 3341 pcs_anar.bits.w0.pause = anar.bits.cap_pause; 3342 val = pcs_anar.value; 3343 PCS_REG_WR(handle, portn, PCS_MII_ADVERT_REG, val); 3344 break; 3345 case MII_GCR: 3346 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3347 pcs_anar.value = (uint16_t)val; 3348 gcr.value = value; 3349 pcs_anar.bits.w0.full_duplex = gcr.bits.link_1000fdx; 3350 pcs_anar.bits.w0.half_duplex = gcr.bits.link_1000hdx; 3351 val = pcs_anar.value; 3352 PCS_REG_WR(handle, portn, PCS_MII_ADVERT_REG, val); 3353 break; 3354 default: 3355 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3356 " npi_mac_pcs_mii_write" 3357 " Invalid Input: xcvr_reg <0x%x>", 3358 xcvr_reg)); 3359 return (NPI_FAILURE | NPI_MAC_REG_INVALID(portn)); 3360 } 3361 3362 return (NPI_SUCCESS); 3363 } 3364 3365 npi_status_t 3366 npi_mac_mif_link_intr_enable(npi_handle_t handle, uint8_t portn, 3367 uint8_t xcvr_reg, uint16_t mask) 3368 { 3369 mif_cfg_t mif_cfg; 3370 3371 ASSERT(IS_PORT_NUM_VALID(portn)); 3372 3373 ASSERT(xcvr_reg <= NXGE_MAX_MII_REGS); 3374 if (xcvr_reg > NXGE_MAX_MII_REGS) { 3375 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3376 " npi_mac_mif_link_intr_enable" 3377 " Invalid Input: xcvr_reg <0x%x>", 3378 xcvr_reg)); 3379 return (NPI_FAILURE | NPI_MAC_REG_INVALID(portn)); 3380 } 3381 3382 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.value); 3383 3384 mif_cfg.bits.w0.phy_addr = portn; /* Port number */ 3385 mif_cfg.bits.w0.reg_addr = xcvr_reg; /* Register address */ 3386 mif_cfg.bits.w0.indirect_md = 0; /* Clause 22 */ 3387 mif_cfg.bits.w0.poll_en = 1; 3388 3389 MIF_REG_WR(handle, MIF_MASK_REG, ~mask); 3390 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.value); 3391 3392 NXGE_DELAY(20); 3393 3394 return (NPI_SUCCESS); 3395 } 3396 3397 npi_status_t 3398 npi_mac_mif_mdio_link_intr_enable(npi_handle_t handle, uint8_t portn, 3399 uint8_t device, uint16_t xcvr_reg, uint16_t mask) 3400 { 3401 mif_cfg_t mif_cfg; 3402 mif_frame_t frame; 3403 uint_t delay; 3404 3405 ASSERT(IS_PORT_NUM_VALID(portn)); 3406 3407 frame.bits.w0.st = 0; /* Clause 45 */ 3408 frame.bits.w0.op = 0; /* Select address */ 3409 frame.bits.w0.phyad = portn; /* Port number */ 3410 frame.bits.w0.regad = device; /* Device number */ 3411 frame.bits.w0.ta_msb = 1; 3412 frame.bits.w0.ta_lsb = 0; 3413 frame.bits.w0.data = xcvr_reg; /* register address */ 3414 3415 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3416 3417 delay = 0; 3418 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MAX_PIO_RETRIES); 3419 if (delay == MAX_PIO_RETRIES) 3420 return (NPI_FAILURE); 3421 3422 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.value); 3423 3424 mif_cfg.bits.w0.phy_addr = portn; /* Port number */ 3425 mif_cfg.bits.w0.reg_addr = device; /* Register address */ 3426 mif_cfg.bits.w0.indirect_md = 1; /* Clause 45 */ 3427 mif_cfg.bits.w0.poll_en = 1; 3428 3429 MIF_REG_WR(handle, MIF_MASK_REG, ~mask); 3430 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.value); 3431 3432 NXGE_DELAY(20); 3433 3434 return (NPI_SUCCESS); 3435 } 3436 3437 void 3438 npi_mac_mif_set_indirect_mode(npi_handle_t handle, boolean_t on_off) 3439 { 3440 mif_cfg_t mif_cfg; 3441 3442 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.value); 3443 mif_cfg.bits.w0.indirect_md = on_off; 3444 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.value); 3445 } 3446 3447 npi_status_t 3448 npi_bmac_send_pause(npi_handle_t handle, uint8_t portn, uint16_t pause_time) 3449 { 3450 uint64_t val; 3451 3452 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 3453 3454 val = MAC_SEND_PAUSE_SEND | pause_time; 3455 BMAC_REG_WR(handle, portn, MAC_SEND_PAUSE_REG, val); 3456 3457 return (NPI_SUCCESS); 3458 } 3459 3460 npi_status_t 3461 npi_xmac_xif_led(npi_handle_t handle, uint8_t portn, boolean_t on_off) 3462 { 3463 uint64_t val = 0; 3464 3465 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 3466 3467 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 3468 3469 if (on_off) { 3470 val |= XMAC_XIF_LED_POLARITY; 3471 val &= ~XMAC_XIF_FORCE_LED_ON; 3472 } else { 3473 val &= ~XMAC_XIF_LED_POLARITY; 3474 val |= XMAC_XIF_FORCE_LED_ON; 3475 } 3476 3477 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 3478 3479 return (NPI_SUCCESS); 3480 } 3481 3482 npi_status_t 3483 npi_xmac_zap_tx_counters(npi_handle_t handle, uint8_t portn) 3484 { 3485 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 3486 3487 XMAC_REG_WR(handle, portn, XTXMAC_FRM_CNT_REG, 0); 3488 XMAC_REG_WR(handle, portn, XTXMAC_BYTE_CNT_REG, 0); 3489 3490 return (NPI_SUCCESS); 3491 } 3492 3493 npi_status_t 3494 npi_xmac_zap_rx_counters(npi_handle_t handle, uint8_t portn) 3495 { 3496 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 3497 3498 XMAC_REG_WR(handle, portn, XRXMAC_BT_CNT_REG, 0); 3499 XMAC_REG_WR(handle, portn, XRXMAC_BC_FRM_CNT_REG, 0); 3500 XMAC_REG_WR(handle, portn, XRXMAC_MC_FRM_CNT_REG, 0); 3501 XMAC_REG_WR(handle, portn, XRXMAC_FRAG_CNT_REG, 0); 3502 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT1_REG, 0); 3503 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT2_REG, 0); 3504 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT3_REG, 0); 3505 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT4_REG, 0); 3506 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT5_REG, 0); 3507 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT6_REG, 0); 3508 XMAC_REG_WR(handle, portn, XRXMAC_MPSZER_CNT_REG, 0); 3509 XMAC_REG_WR(handle, portn, XRXMAC_CRC_ER_CNT_REG, 0); 3510 XMAC_REG_WR(handle, portn, XRXMAC_CD_VIO_CNT_REG, 0); 3511 XMAC_REG_WR(handle, portn, XRXMAC_AL_ER_CNT_REG, 0); 3512 XMAC_REG_WR(handle, portn, XMAC_LINK_FLT_CNT_REG, 0); 3513 3514 return (NPI_SUCCESS); 3515 } 3516