1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <npi_mac.h> 29 30 #define MIF_DELAY 500 31 32 #define MAX_FRAME_SZ1 0x5EE 33 #define MAX_FRAME_SZ2 0x5F6 34 #define MAX_FRAME_SZ3 0x7D6 35 #define MAX_FRAME_SZ4 0x232E 36 #define MAX_FRAME_SZ5 0x2406 37 38 #define XMAC_WAIT_REG(handle, portn, reg, val) {\ 39 uint32_t cnt = MAX_PIO_RETRIES;\ 40 do {\ 41 NXGE_DELAY(MAC_RESET_WAIT);\ 42 XMAC_REG_RD(handle, portn, reg, &val);\ 43 cnt--;\ 44 } while (((val & 0x3) != 0) && (cnt > 0));\ 45 } 46 47 #define BMAC_WAIT_REG(handle, portn, reg, val) {\ 48 uint32_t cnt = MAX_PIO_RETRIES;\ 49 do {\ 50 NXGE_DELAY(MAC_RESET_WAIT);\ 51 BMAC_REG_RD(handle, portn, reg, &val);\ 52 cnt--;\ 53 } while (((val & 0x3) != 0) && (cnt > 0));\ 54 } 55 56 #define MIF_WAIT_REG(handle, m_frame, t_delay, interval, max_delay) { \ 57 do { \ 58 NXGE_DELAY(interval); \ 59 MIF_REG_RD(handle, MIF_OUTPUT_FRAME_REG, &m_frame.value); \ 60 t_delay++; \ 61 } while ((m_frame.bits.w0.ta_lsb == 0) && t_delay < max_delay); \ 62 } 63 64 uint64_t xmac_offset[] = { 65 XTXMAC_SW_RST_REG, 66 XRXMAC_SW_RST_REG, 67 XTXMAC_STATUS_REG, 68 XRXMAC_STATUS_REG, 69 XMAC_CTRL_STAT_REG, 70 XTXMAC_STAT_MSK_REG, 71 XRXMAC_STAT_MSK_REG, 72 XMAC_C_S_MSK_REG, 73 XMAC_CONFIG_REG, 74 XMAC_IPG_REG, 75 XMAC_MIN_REG, 76 XMAC_MAX_REG, 77 XMAC_ADDR0_REG, 78 XMAC_ADDR1_REG, 79 XMAC_ADDR2_REG, 80 XRXMAC_BT_CNT_REG, 81 XRXMAC_BC_FRM_CNT_REG, 82 XRXMAC_MC_FRM_CNT_REG, 83 XRXMAC_FRAG_CNT_REG, 84 XRXMAC_HIST_CNT1_REG, 85 XRXMAC_HIST_CNT2_REG, 86 XRXMAC_HIST_CNT3_REG, 87 XRXMAC_HIST_CNT4_REG, 88 XRXMAC_HIST_CNT5_REG, 89 XRXMAC_HIST_CNT6_REG, 90 XRXMAC_MPSZER_CNT_REG, 91 XRXMAC_CRC_ER_CNT_REG, 92 XRXMAC_CD_VIO_CNT_REG, 93 XRXMAC_AL_ER_CNT_REG, 94 XTXMAC_FRM_CNT_REG, 95 XTXMAC_BYTE_CNT_REG, 96 XMAC_LINK_FLT_CNT_REG, 97 XRXMAC_HIST_CNT7_REG, 98 XMAC_SM_REG, 99 XMAC_INTERN1_REG, 100 XMAC_INTERN2_REG, 101 XMAC_ADDR_CMPEN_REG, 102 XMAC_ADDR3_REG, 103 XMAC_ADDR4_REG, 104 XMAC_ADDR5_REG, 105 XMAC_ADDR6_REG, 106 XMAC_ADDR7_REG, 107 XMAC_ADDR8_REG, 108 XMAC_ADDR9_REG, 109 XMAC_ADDR10_REG, 110 XMAC_ADDR11_REG, 111 XMAC_ADDR12_REG, 112 XMAC_ADDR13_REG, 113 XMAC_ADDR14_REG, 114 XMAC_ADDR15_REG, 115 XMAC_ADDR16_REG, 116 XMAC_ADDR17_REG, 117 XMAC_ADDR18_REG, 118 XMAC_ADDR19_REG, 119 XMAC_ADDR20_REG, 120 XMAC_ADDR21_REG, 121 XMAC_ADDR22_REG, 122 XMAC_ADDR23_REG, 123 XMAC_ADDR24_REG, 124 XMAC_ADDR25_REG, 125 XMAC_ADDR26_REG, 126 XMAC_ADDR27_REG, 127 XMAC_ADDR28_REG, 128 XMAC_ADDR29_REG, 129 XMAC_ADDR30_REG, 130 XMAC_ADDR31_REG, 131 XMAC_ADDR32_REG, 132 XMAC_ADDR33_REG, 133 XMAC_ADDR34_REG, 134 XMAC_ADDR35_REG, 135 XMAC_ADDR36_REG, 136 XMAC_ADDR37_REG, 137 XMAC_ADDR38_REG, 138 XMAC_ADDR39_REG, 139 XMAC_ADDR40_REG, 140 XMAC_ADDR41_REG, 141 XMAC_ADDR42_REG, 142 XMAC_ADDR43_REG, 143 XMAC_ADDR44_REG, 144 XMAC_ADDR45_REG, 145 XMAC_ADDR46_REG, 146 XMAC_ADDR47_REG, 147 XMAC_ADDR48_REG, 148 XMAC_ADDR49_REG, 149 XMAC_ADDR50_REG, 150 XMAC_ADDR_FILT0_REG, 151 XMAC_ADDR_FILT1_REG, 152 XMAC_ADDR_FILT2_REG, 153 XMAC_ADDR_FILT12_MASK_REG, 154 XMAC_ADDR_FILT0_MASK_REG, 155 XMAC_HASH_TBL0_REG, 156 XMAC_HASH_TBL1_REG, 157 XMAC_HASH_TBL2_REG, 158 XMAC_HASH_TBL3_REG, 159 XMAC_HASH_TBL4_REG, 160 XMAC_HASH_TBL5_REG, 161 XMAC_HASH_TBL6_REG, 162 XMAC_HASH_TBL7_REG, 163 XMAC_HASH_TBL8_REG, 164 XMAC_HASH_TBL9_REG, 165 XMAC_HASH_TBL10_REG, 166 XMAC_HASH_TBL11_REG, 167 XMAC_HASH_TBL12_REG, 168 XMAC_HASH_TBL13_REG, 169 XMAC_HASH_TBL14_REG, 170 XMAC_HASH_TBL15_REG, 171 XMAC_HOST_INF0_REG, 172 XMAC_HOST_INF1_REG, 173 XMAC_HOST_INF2_REG, 174 XMAC_HOST_INF3_REG, 175 XMAC_HOST_INF4_REG, 176 XMAC_HOST_INF5_REG, 177 XMAC_HOST_INF6_REG, 178 XMAC_HOST_INF7_REG, 179 XMAC_HOST_INF8_REG, 180 XMAC_HOST_INF9_REG, 181 XMAC_HOST_INF10_REG, 182 XMAC_HOST_INF11_REG, 183 XMAC_HOST_INF12_REG, 184 XMAC_HOST_INF13_REG, 185 XMAC_HOST_INF14_REG, 186 XMAC_HOST_INF15_REG, 187 XMAC_HOST_INF16_REG, 188 XMAC_HOST_INF17_REG, 189 XMAC_HOST_INF18_REG, 190 XMAC_HOST_INF19_REG, 191 XMAC_PA_DATA0_REG, 192 XMAC_PA_DATA1_REG, 193 XMAC_DEBUG_SEL_REG, 194 XMAC_TRAINING_VECT_REG, 195 }; 196 197 const char *xmac_name[] = { 198 "XTXMAC_SW_RST_REG", 199 "XRXMAC_SW_RST_REG", 200 "XTXMAC_STATUS_REG", 201 "XRXMAC_STATUS_REG", 202 "XMAC_CTRL_STAT_REG", 203 "XTXMAC_STAT_MSK_REG", 204 "XRXMAC_STAT_MSK_REG", 205 "XMAC_C_S_MSK_REG", 206 "XMAC_CONFIG_REG", 207 "XMAC_IPG_REG", 208 "XMAC_MIN_REG", 209 "XMAC_MAX_REG", 210 "XMAC_ADDR0_REG", 211 "XMAC_ADDR1_REG", 212 "XMAC_ADDR2_REG", 213 "XRXMAC_BT_CNT_REG", 214 "XRXMAC_BC_FRM_CNT_REG", 215 "XRXMAC_MC_FRM_CNT_REG", 216 "XRXMAC_FRAG_CNT_REG", 217 "XRXMAC_HIST_CNT1_REG", 218 "XRXMAC_HIST_CNT2_REG", 219 "XRXMAC_HIST_CNT3_REG", 220 "XRXMAC_HIST_CNT4_REG", 221 "XRXMAC_HIST_CNT5_REG", 222 "XRXMAC_HIST_CNT6_REG", 223 "XRXMAC_MPSZER_CNT_REG", 224 "XRXMAC_CRC_ER_CNT_REG", 225 "XRXMAC_CD_VIO_CNT_REG", 226 "XRXMAC_AL_ER_CNT_REG", 227 "XTXMAC_FRM_CNT_REG", 228 "XTXMAC_BYTE_CNT_REG", 229 "XMAC_LINK_FLT_CNT_REG", 230 "XRXMAC_HIST_CNT7_REG", 231 "XMAC_SM_REG", 232 "XMAC_INTERN1_REG", 233 "XMAC_INTERN2_REG", 234 "XMAC_ADDR_CMPEN_REG", 235 "XMAC_ADDR3_REG", 236 "XMAC_ADDR4_REG", 237 "XMAC_ADDR5_REG", 238 "XMAC_ADDR6_REG", 239 "XMAC_ADDR7_REG", 240 "XMAC_ADDR8_REG", 241 "XMAC_ADDR9_REG", 242 "XMAC_ADDR10_REG", 243 "XMAC_ADDR11_REG", 244 "XMAC_ADDR12_REG", 245 "XMAC_ADDR13_REG", 246 "XMAC_ADDR14_REG", 247 "XMAC_ADDR15_REG", 248 "XMAC_ADDR16_REG", 249 "XMAC_ADDR17_REG", 250 "XMAC_ADDR18_REG", 251 "XMAC_ADDR19_REG", 252 "XMAC_ADDR20_REG", 253 "XMAC_ADDR21_REG", 254 "XMAC_ADDR22_REG", 255 "XMAC_ADDR23_REG", 256 "XMAC_ADDR24_REG", 257 "XMAC_ADDR25_REG", 258 "XMAC_ADDR26_REG", 259 "XMAC_ADDR27_REG", 260 "XMAC_ADDR28_REG", 261 "XMAC_ADDR29_REG", 262 "XMAC_ADDR30_REG", 263 "XMAC_ADDR31_REG", 264 "XMAC_ADDR32_REG", 265 "XMAC_ADDR33_REG", 266 "XMAC_ADDR34_REG", 267 "XMAC_ADDR35_REG", 268 "XMAC_ADDR36_REG", 269 "XMAC_ADDR37_REG", 270 "XMAC_ADDR38_REG", 271 "XMAC_ADDR39_REG", 272 "XMAC_ADDR40_REG", 273 "XMAC_ADDR41_REG", 274 "XMAC_ADDR42_REG", 275 "XMAC_ADDR43_REG", 276 "XMAC_ADDR44_REG", 277 "XMAC_ADDR45_REG", 278 "XMAC_ADDR46_REG", 279 "XMAC_ADDR47_REG", 280 "XMAC_ADDR48_REG", 281 "XMAC_ADDR49_REG", 282 "XMAC_ADDR50_RE", 283 "XMAC_ADDR_FILT0_REG", 284 "XMAC_ADDR_FILT1_REG", 285 "XMAC_ADDR_FILT2_REG", 286 "XMAC_ADDR_FILT12_MASK_REG", 287 "XMAC_ADDR_FILT0_MASK_REG", 288 "XMAC_HASH_TBL0_REG", 289 "XMAC_HASH_TBL1_REG", 290 "XMAC_HASH_TBL2_REG", 291 "XMAC_HASH_TBL3_REG", 292 "XMAC_HASH_TBL4_REG", 293 "XMAC_HASH_TBL5_REG", 294 "XMAC_HASH_TBL6_REG", 295 "XMAC_HASH_TBL7_REG", 296 "XMAC_HASH_TBL8_REG", 297 "XMAC_HASH_TBL9_REG", 298 "XMAC_HASH_TBL10_REG", 299 "XMAC_HASH_TBL11_REG", 300 "XMAC_HASH_TBL12_REG", 301 "XMAC_HASH_TBL13_REG", 302 "XMAC_HASH_TBL14_REG", 303 "XMAC_HASH_TBL15_REG", 304 "XMAC_HOST_INF0_REG", 305 "XMAC_HOST_INF1_REG", 306 "XMAC_HOST_INF2_REG", 307 "XMAC_HOST_INF3_REG", 308 "XMAC_HOST_INF4_REG", 309 "XMAC_HOST_INF5_REG", 310 "XMAC_HOST_INF6_REG", 311 "XMAC_HOST_INF7_REG", 312 "XMAC_HOST_INF8_REG", 313 "XMAC_HOST_INF9_REG", 314 "XMAC_HOST_INF10_REG", 315 "XMAC_HOST_INF11_REG", 316 "XMAC_HOST_INF12_REG", 317 "XMAC_HOST_INF13_REG", 318 "XMAC_HOST_INF14_REG", 319 "XMAC_HOST_INF15_REG", 320 "XMAC_HOST_INF16_REG", 321 "XMAC_HOST_INF17_REG", 322 "XMAC_HOST_INF18_REG", 323 "XMAC_HOST_INF19_REG", 324 "XMAC_PA_DATA0_REG", 325 "XMAC_PA_DATA1_REG", 326 "XMAC_DEBUG_SEL_REG", 327 "XMAC_TRAINING_VECT_REG", 328 }; 329 330 uint64_t bmac_offset[] = { 331 BTXMAC_SW_RST_REG, 332 BRXMAC_SW_RST_REG, 333 MAC_SEND_PAUSE_REG, 334 BTXMAC_STATUS_REG, 335 BRXMAC_STATUS_REG, 336 BMAC_CTRL_STAT_REG, 337 BTXMAC_STAT_MSK_REG, 338 BRXMAC_STAT_MSK_REG, 339 BMAC_C_S_MSK_REG, 340 TXMAC_CONFIG_REG, 341 RXMAC_CONFIG_REG, 342 MAC_CTRL_CONFIG_REG, 343 MAC_XIF_CONFIG_REG, 344 BMAC_MIN_REG, 345 BMAC_MAX_REG, 346 MAC_PA_SIZE_REG, 347 MAC_CTRL_TYPE_REG, 348 BMAC_ADDR0_REG, 349 BMAC_ADDR1_REG, 350 BMAC_ADDR2_REG, 351 BMAC_ADDR3_REG, 352 BMAC_ADDR4_REG, 353 BMAC_ADDR5_REG, 354 BMAC_ADDR6_REG, 355 BMAC_ADDR7_REG, 356 BMAC_ADDR8_REG, 357 BMAC_ADDR9_REG, 358 BMAC_ADDR10_REG, 359 BMAC_ADDR11_REG, 360 BMAC_ADDR12_REG, 361 BMAC_ADDR13_REG, 362 BMAC_ADDR14_REG, 363 BMAC_ADDR15_REG, 364 BMAC_ADDR16_REG, 365 BMAC_ADDR17_REG, 366 BMAC_ADDR18_REG, 367 BMAC_ADDR19_REG, 368 BMAC_ADDR20_REG, 369 BMAC_ADDR21_REG, 370 BMAC_ADDR22_REG, 371 BMAC_ADDR23_REG, 372 MAC_FC_ADDR0_REG, 373 MAC_FC_ADDR1_REG, 374 MAC_FC_ADDR2_REG, 375 MAC_ADDR_FILT0_REG, 376 MAC_ADDR_FILT1_REG, 377 MAC_ADDR_FILT2_REG, 378 MAC_ADDR_FILT12_MASK_REG, 379 MAC_ADDR_FILT00_MASK_REG, 380 MAC_HASH_TBL0_REG, 381 MAC_HASH_TBL1_REG, 382 MAC_HASH_TBL2_REG, 383 MAC_HASH_TBL3_REG, 384 MAC_HASH_TBL4_REG, 385 MAC_HASH_TBL5_REG, 386 MAC_HASH_TBL6_REG, 387 MAC_HASH_TBL7_REG, 388 MAC_HASH_TBL8_REG, 389 MAC_HASH_TBL9_REG, 390 MAC_HASH_TBL10_REG, 391 MAC_HASH_TBL11_REG, 392 MAC_HASH_TBL12_REG, 393 MAC_HASH_TBL13_REG, 394 MAC_HASH_TBL14_REG, 395 MAC_HASH_TBL15_REG, 396 RXMAC_FRM_CNT_REG, 397 MAC_LEN_ER_CNT_REG, 398 BMAC_AL_ER_CNT_REG, 399 BMAC_CRC_ER_CNT_REG, 400 BMAC_CD_VIO_CNT_REG, 401 BMAC_SM_REG, 402 BMAC_ALTAD_CMPEN_REG, 403 BMAC_HOST_INF0_REG, 404 BMAC_HOST_INF1_REG, 405 BMAC_HOST_INF2_REG, 406 BMAC_HOST_INF3_REG, 407 BMAC_HOST_INF4_REG, 408 BMAC_HOST_INF5_REG, 409 BMAC_HOST_INF6_REG, 410 BMAC_HOST_INF7_REG, 411 BMAC_HOST_INF8_REG, 412 BTXMAC_BYTE_CNT_REG, 413 BTXMAC_FRM_CNT_REG, 414 BRXMAC_BYTE_CNT_REG, 415 }; 416 417 const char *bmac_name[] = { 418 "BTXMAC_SW_RST_REG", 419 "BRXMAC_SW_RST_REG", 420 "MAC_SEND_PAUSE_REG", 421 "BTXMAC_STATUS_REG", 422 "BRXMAC_STATUS_REG", 423 "BMAC_CTRL_STAT_REG", 424 "BTXMAC_STAT_MSK_REG", 425 "BRXMAC_STAT_MSK_REG", 426 "BMAC_C_S_MSK_REG", 427 "TXMAC_CONFIG_REG", 428 "RXMAC_CONFIG_REG", 429 "MAC_CTRL_CONFIG_REG", 430 "MAC_XIF_CONFIG_REG", 431 "BMAC_MIN_REG", 432 "BMAC_MAX_REG", 433 "MAC_PA_SIZE_REG", 434 "MAC_CTRL_TYPE_REG", 435 "BMAC_ADDR0_REG", 436 "BMAC_ADDR1_REG", 437 "BMAC_ADDR2_REG", 438 "BMAC_ADDR3_REG", 439 "BMAC_ADDR4_REG", 440 "BMAC_ADDR5_REG", 441 "BMAC_ADDR6_REG", 442 "BMAC_ADDR7_REG", 443 "BMAC_ADDR8_REG", 444 "BMAC_ADDR9_REG", 445 "BMAC_ADDR10_REG", 446 "BMAC_ADDR11_REG", 447 "BMAC_ADDR12_REG", 448 "BMAC_ADDR13_REG", 449 "BMAC_ADDR14_REG", 450 "BMAC_ADDR15_REG", 451 "BMAC_ADDR16_REG", 452 "BMAC_ADDR17_REG", 453 "BMAC_ADDR18_REG", 454 "BMAC_ADDR19_REG", 455 "BMAC_ADDR20_REG", 456 "BMAC_ADDR21_REG", 457 "BMAC_ADDR22_REG", 458 "BMAC_ADDR23_REG", 459 "MAC_FC_ADDR0_REG", 460 "MAC_FC_ADDR1_REG", 461 "MAC_FC_ADDR2_REG", 462 "MAC_ADDR_FILT0_REG", 463 "MAC_ADDR_FILT1_REG", 464 "MAC_ADDR_FILT2_REG", 465 "MAC_ADDR_FILT12_MASK_REG", 466 "MAC_ADDR_FILT00_MASK_REG", 467 "MAC_HASH_TBL0_REG", 468 "MAC_HASH_TBL1_REG", 469 "MAC_HASH_TBL2_REG", 470 "MAC_HASH_TBL3_REG", 471 "MAC_HASH_TBL4_REG", 472 "MAC_HASH_TBL5_REG", 473 "MAC_HASH_TBL6_REG", 474 "MAC_HASH_TBL7_REG", 475 "MAC_HASH_TBL8_REG", 476 "MAC_HASH_TBL9_REG", 477 "MAC_HASH_TBL10_REG", 478 "MAC_HASH_TBL11_REG", 479 "MAC_HASH_TBL12_REG", 480 "MAC_HASH_TBL13_REG", 481 "MAC_HASH_TBL14_REG", 482 "MAC_HASH_TBL15_REG", 483 "RXMAC_FRM_CNT_REG", 484 "MAC_LEN_ER_CNT_REG", 485 "BMAC_AL_ER_CNT_REG", 486 "BMAC_CRC_ER_CNT_REG", 487 "BMAC_CD_VIO_CNT_REG", 488 "BMAC_SM_REG", 489 "BMAC_ALTAD_CMPEN_REG", 490 "BMAC_HOST_INF0_REG", 491 "BMAC_HOST_INF1_REG", 492 "BMAC_HOST_INF2_REG", 493 "BMAC_HOST_INF3_REG", 494 "BMAC_HOST_INF4_REG", 495 "BMAC_HOST_INF5_REG", 496 "BMAC_HOST_INF6_REG", 497 "BMAC_HOST_INF7_REG", 498 "BMAC_HOST_INF8_REG", 499 "BTXMAC_BYTE_CNT_REG", 500 "BTXMAC_FRM_CNT_REG", 501 "BRXMAC_BYTE_CNT_REG", 502 }; 503 504 npi_status_t 505 npi_mac_dump_regs(npi_handle_t handle, uint8_t port) 506 { 507 508 uint64_t value; 509 int num_regs, i; 510 511 ASSERT(IS_PORT_NUM_VALID(port)); 512 513 switch (port) { 514 case 0: 515 case 1: 516 num_regs = sizeof (xmac_offset) / sizeof (uint64_t); 517 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 518 "\nXMAC Register Dump for port %d\n", 519 port)); 520 for (i = 0; i < num_regs; i++) { 521 #if defined(__i386) 522 XMAC_REG_RD(handle, port, (uint32_t)xmac_offset[i], 523 &value); 524 #else 525 XMAC_REG_RD(handle, port, xmac_offset[i], &value); 526 #endif 527 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 528 "%08llx %s\t %08llx \n", 529 (XMAC_REG_ADDR((port), (xmac_offset[i]))), 530 xmac_name[i], value)); 531 } 532 533 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 534 "\n XMAC Register Dump for port %d done\n", 535 port)); 536 break; 537 538 case 2: 539 case 3: 540 num_regs = sizeof (bmac_offset) / sizeof (uint64_t); 541 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 542 "\nBMAC Register Dump for port %d\n", 543 port)); 544 for (i = 0; i < num_regs; i++) { 545 #if defined(__i386) 546 BMAC_REG_RD(handle, port, (uint32_t)bmac_offset[i], 547 &value); 548 #else 549 BMAC_REG_RD(handle, port, bmac_offset[i], &value); 550 #endif 551 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 552 "%08llx %s\t %08llx \n", 553 (BMAC_REG_ADDR((port), (bmac_offset[i]))), 554 bmac_name[i], value)); 555 } 556 557 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 558 "\n BMAC Register Dump for port %d done\n", 559 port)); 560 break; 561 } 562 563 return (NPI_SUCCESS); 564 } 565 566 npi_status_t 567 npi_mac_pcs_link_intr_enable(npi_handle_t handle, uint8_t portn) 568 { 569 pcs_cfg_t pcs_cfg; 570 571 ASSERT(IS_PORT_NUM_VALID(portn)); 572 573 PCS_REG_RD(handle, portn, PCS_CONFIG_REG, &pcs_cfg.value); 574 pcs_cfg.bits.w0.mask = 0; 575 PCS_REG_WR(handle, portn, PCS_CONFIG_REG, pcs_cfg.value); 576 577 return (NPI_SUCCESS); 578 } 579 580 npi_status_t 581 npi_mac_pcs_link_intr_disable(npi_handle_t handle, uint8_t portn) 582 { 583 pcs_cfg_t pcs_cfg; 584 585 ASSERT(IS_PORT_NUM_VALID(portn)); 586 587 PCS_REG_RD(handle, portn, PCS_CONFIG_REG, &pcs_cfg.val.lsw); 588 pcs_cfg.bits.w0.mask = 1; 589 PCS_REG_WR(handle, portn, PCS_CONFIG_REG, pcs_cfg.val.lsw); 590 591 return (NPI_SUCCESS); 592 } 593 594 npi_status_t 595 npi_xmac_xpcs_link_intr_enable(npi_handle_t handle, uint8_t portn) 596 { 597 xpcs_stat1_t xpcs_mask1; 598 599 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 600 601 XPCS_REG_RD(handle, portn, XPCS_MASK_1_REG, &xpcs_mask1.val.lsw); 602 xpcs_mask1.bits.w0.csr_rx_link_stat = 1; 603 XPCS_REG_WR(handle, portn, XPCS_MASK_1_REG, xpcs_mask1.val.lsw); 604 605 return (NPI_SUCCESS); 606 } 607 608 npi_status_t 609 npi_xmac_xpcs_link_intr_disable(npi_handle_t handle, uint8_t portn) 610 { 611 xpcs_stat1_t xpcs_mask1; 612 613 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 614 615 XPCS_REG_RD(handle, portn, XPCS_MASK_1_REG, &xpcs_mask1.val.lsw); 616 xpcs_mask1.bits.w0.csr_rx_link_stat = 0; 617 XPCS_REG_WR(handle, portn, XPCS_MASK_1_REG, xpcs_mask1.val.lsw); 618 619 return (NPI_SUCCESS); 620 } 621 622 npi_status_t 623 npi_mac_mif_link_intr_disable(npi_handle_t handle, uint8_t portn) 624 { 625 mif_cfg_t mif_cfg; 626 627 ASSERT(IS_PORT_NUM_VALID(portn)); 628 629 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.val.lsw); 630 631 mif_cfg.bits.w0.phy_addr = portn; 632 mif_cfg.bits.w0.poll_en = 0; 633 634 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.val.lsw); 635 636 NXGE_DELAY(20); 637 638 return (NPI_SUCCESS); 639 } 640 641 npi_status_t 642 npi_mac_hashtab_entry(npi_handle_t handle, io_op_t op, uint8_t portn, 643 uint8_t entryn, uint16_t *data) 644 { 645 uint64_t val; 646 647 ASSERT((op == OP_GET) || (op == OP_SET)); 648 ASSERT(IS_PORT_NUM_VALID(portn)); 649 650 ASSERT(entryn < MAC_MAX_HASH_ENTRY); 651 if (entryn >= MAC_MAX_HASH_ENTRY) { 652 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 653 " npi_mac_hashtab_entry" 654 " Invalid Input: entryn <0x%x>", 655 entryn)); 656 return (NPI_FAILURE | NPI_MAC_HASHTAB_ENTRY_INVALID(portn)); 657 } 658 659 if (op == OP_SET) { 660 val = *data; 661 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 662 XMAC_REG_WR(handle, portn, 663 XMAC_HASH_TBLN_REG_ADDR(entryn), val); 664 } else { 665 BMAC_REG_WR(handle, portn, 666 BMAC_HASH_TBLN_REG_ADDR(entryn), val); 667 } 668 } else { 669 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 670 XMAC_REG_RD(handle, portn, 671 XMAC_HASH_TBLN_REG_ADDR(entryn), &val); 672 } else { 673 BMAC_REG_RD(handle, portn, 674 BMAC_HASH_TBLN_REG_ADDR(entryn), &val); 675 } 676 *data = val & 0xFFFF; 677 } 678 679 return (NPI_SUCCESS); 680 } 681 682 npi_status_t 683 npi_mac_hostinfo_entry(npi_handle_t handle, io_op_t op, uint8_t portn, 684 uint8_t entryn, hostinfo_t *hostinfo) 685 { 686 ASSERT((op == OP_GET) || (op == OP_SET)); 687 ASSERT(IS_PORT_NUM_VALID(portn)); 688 689 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 690 ASSERT(entryn < XMAC_MAX_HOST_INFO_ENTRY); 691 if (entryn >= XMAC_MAX_HOST_INFO_ENTRY) { 692 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 693 " npi_mac_hostinfo_entry" 694 " Invalid Input: entryn <0x%x>", 695 entryn)); 696 return (NPI_FAILURE | 697 NPI_MAC_HOSTINFO_ENTRY_INVALID(portn)); 698 } 699 } else { 700 ASSERT(entryn < BMAC_MAX_HOST_INFO_ENTRY); 701 if (entryn >= BMAC_MAX_HOST_INFO_ENTRY) { 702 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 703 " npi_mac_hostinfo_entry" 704 " Invalid Input: entryn <0x%x>", 705 entryn)); 706 return (NPI_FAILURE | 707 NPI_MAC_HOSTINFO_ENTRY_INVALID(portn)); 708 } 709 } 710 711 if (op == OP_SET) { 712 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 713 XMAC_REG_WR(handle, portn, 714 XMAC_HOST_INFN_REG_ADDR(entryn), 715 hostinfo->value); 716 } else { 717 BMAC_REG_WR(handle, portn, 718 BMAC_HOST_INFN_REG_ADDR(entryn), 719 hostinfo->value); 720 } 721 } else { 722 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 723 XMAC_REG_RD(handle, portn, 724 XMAC_HOST_INFN_REG_ADDR(entryn), 725 &hostinfo->value); 726 } else { 727 BMAC_REG_RD(handle, portn, 728 BMAC_HOST_INFN_REG_ADDR(entryn), 729 &hostinfo->value); 730 } 731 } 732 733 return (NPI_SUCCESS); 734 } 735 736 npi_status_t 737 npi_mac_altaddr_enable(npi_handle_t handle, uint8_t portn, uint8_t addrn) 738 { 739 uint64_t val; 740 741 ASSERT(IS_PORT_NUM_VALID(portn)); 742 743 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 744 ASSERT(addrn <= XMAC_MAX_ALT_ADDR_ENTRY); 745 if (addrn > XMAC_MAX_ALT_ADDR_ENTRY) { 746 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 747 " npi_mac_altaddr_enable" 748 " Invalid Input: addrn <0x%x>", 749 addrn)); 750 return (NPI_FAILURE | 751 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 752 } 753 XMAC_REG_RD(handle, portn, XMAC_ADDR_CMPEN_REG, &val); 754 val |= (1 << addrn); 755 XMAC_REG_WR(handle, portn, XMAC_ADDR_CMPEN_REG, val); 756 } else { 757 ASSERT(addrn <= BMAC_MAX_ALT_ADDR_ENTRY); 758 if (addrn > BMAC_MAX_ALT_ADDR_ENTRY) { 759 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 760 " npi_mac_altaddr_enable" 761 " Invalid Input: addrn <0x%x>", 762 addrn)); 763 return (NPI_FAILURE | 764 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 765 } 766 BMAC_REG_RD(handle, portn, BMAC_ALTAD_CMPEN_REG, &val); 767 val |= (1 << addrn); 768 BMAC_REG_WR(handle, portn, BMAC_ALTAD_CMPEN_REG, val); 769 } 770 771 return (NPI_SUCCESS); 772 } 773 774 /* 775 * While all bits of XMAC_ADDR_CMPEN_REG are for alternate MAC addresses, 776 * bit0 of BMAC_ALTAD_CMPEN_REG is for unique MAC address. 777 */ 778 npi_status_t 779 npi_mac_altaddr_disable(npi_handle_t handle, uint8_t portn, uint8_t addrn) 780 { 781 uint64_t val; 782 783 ASSERT(IS_PORT_NUM_VALID(portn)); 784 785 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 786 ASSERT(addrn <= XMAC_MAX_ALT_ADDR_ENTRY); 787 if (addrn > XMAC_MAX_ALT_ADDR_ENTRY) { 788 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 789 " npi_mac_altaddr_disable" 790 " Invalid Input: addrn <0x%x>", 791 addrn)); 792 return (NPI_FAILURE | 793 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 794 } 795 XMAC_REG_RD(handle, portn, XMAC_ADDR_CMPEN_REG, &val); 796 val &= ~(1 << addrn); 797 XMAC_REG_WR(handle, portn, XMAC_ADDR_CMPEN_REG, val); 798 } else { 799 ASSERT(addrn <= BMAC_MAX_ALT_ADDR_ENTRY); 800 if (addrn > BMAC_MAX_ALT_ADDR_ENTRY) { 801 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 802 " npi_mac_altaddr_disable" 803 " Invalid Input: addrn <0x%x>", 804 addrn)); 805 return (NPI_FAILURE | 806 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 807 } 808 BMAC_REG_RD(handle, portn, BMAC_ALTAD_CMPEN_REG, &val); 809 val &= ~(1 << addrn); 810 BMAC_REG_WR(handle, portn, BMAC_ALTAD_CMPEN_REG, val); 811 } 812 813 return (NPI_SUCCESS); 814 } 815 816 npi_status_t 817 npi_mac_altaddr_entry(npi_handle_t handle, io_op_t op, uint8_t portn, 818 uint8_t entryn, npi_mac_addr_t *data) 819 { 820 uint64_t val0, val1, val2; 821 822 ASSERT(IS_PORT_NUM_VALID(portn)); 823 ASSERT((op == OP_GET) || (op == OP_SET)); 824 825 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 826 ASSERT(entryn <= XMAC_MAX_ALT_ADDR_ENTRY); 827 if (entryn > XMAC_MAX_ALT_ADDR_ENTRY) { 828 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 829 " npi_mac_altaddr_entry" 830 " Invalid Input: entryn <0x%x>", 831 entryn)); 832 return (NPI_FAILURE | 833 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 834 } 835 if (op == OP_SET) { 836 val0 = data->w0; 837 val1 = data->w1; 838 val2 = data->w2; 839 XMAC_REG_WR(handle, portn, 840 XMAC_ALT_ADDR0N_REG_ADDR(entryn), val0); 841 XMAC_REG_WR(handle, portn, 842 XMAC_ALT_ADDR1N_REG_ADDR(entryn), val1); 843 XMAC_REG_WR(handle, portn, 844 XMAC_ALT_ADDR2N_REG_ADDR(entryn), val2); 845 } else { 846 XMAC_REG_RD(handle, portn, 847 XMAC_ALT_ADDR0N_REG_ADDR(entryn), &val0); 848 XMAC_REG_RD(handle, portn, 849 XMAC_ALT_ADDR1N_REG_ADDR(entryn), &val1); 850 XMAC_REG_RD(handle, portn, 851 XMAC_ALT_ADDR2N_REG_ADDR(entryn), &val2); 852 data->w0 = val0 & 0xFFFF; 853 data->w1 = val1 & 0xFFFF; 854 data->w2 = val2 & 0xFFFF; 855 } 856 } else { 857 ASSERT(entryn <= BMAC_MAX_ALT_ADDR_ENTRY); 858 if (entryn > BMAC_MAX_ALT_ADDR_ENTRY) { 859 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 860 " npi_mac_altaddr_entry" 861 " Invalid Input: entryn <0x%x>", 862 entryn)); 863 return (NPI_FAILURE | 864 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 865 } 866 if (op == OP_SET) { 867 val0 = data->w0; 868 val1 = data->w1; 869 val2 = data->w2; 870 BMAC_REG_WR(handle, portn, 871 BMAC_ALT_ADDR0N_REG_ADDR(entryn), val0); 872 BMAC_REG_WR(handle, portn, 873 BMAC_ALT_ADDR1N_REG_ADDR(entryn), val1); 874 BMAC_REG_WR(handle, portn, 875 BMAC_ALT_ADDR2N_REG_ADDR(entryn), val2); 876 } else { 877 BMAC_REG_RD(handle, portn, 878 BMAC_ALT_ADDR0N_REG_ADDR(entryn), &val0); 879 BMAC_REG_RD(handle, portn, 880 BMAC_ALT_ADDR1N_REG_ADDR(entryn), &val1); 881 BMAC_REG_RD(handle, portn, 882 BMAC_ALT_ADDR2N_REG_ADDR(entryn), &val2); 883 data->w0 = val0 & 0xFFFF; 884 data->w1 = val1 & 0xFFFF; 885 data->w2 = val2 & 0xFFFF; 886 } 887 } 888 889 return (NPI_SUCCESS); 890 } 891 892 npi_status_t 893 npi_mac_port_attr(npi_handle_t handle, io_op_t op, uint8_t portn, 894 npi_attr_t *attrp) 895 { 896 uint64_t val = 0; 897 uint32_t attr; 898 899 ASSERT(IS_PORT_NUM_VALID(portn)); 900 ASSERT((op == OP_GET) || (op == OP_SET)); 901 902 switch (attrp->type) { 903 case MAC_PORT_MODE: 904 switch (portn) { 905 case XMAC_PORT_0: 906 case XMAC_PORT_1: 907 if (op == OP_SET) { 908 attr = attrp->idata[0]; 909 ASSERT((attr == MAC_MII_MODE) || \ 910 (attr == MAC_GMII_MODE) || \ 911 (attr == MAC_XGMII_MODE)); 912 if ((attr != MAC_MII_MODE) && 913 (attr != MAC_GMII_MODE) && 914 (attr != MAC_XGMII_MODE)) { 915 NPI_ERROR_MSG((handle.function, 916 NPI_ERR_CTL, 917 " npi_mac_port_attr" 918 " Invalid Input:" 919 " MAC_PORT_MODE <0x%x>", 920 attr)); 921 return (NPI_FAILURE | 922 NPI_MAC_PORT_ATTR_INVALID(portn)); 923 } 924 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, 925 &val); 926 val &= ~XMAC_XIF_MII_MODE_MASK; 927 switch (attr) { 928 case MAC_MII_MODE: 929 val |= (XMAC_XIF_MII_MODE << 930 XMAC_XIF_MII_MODE_SHIFT); 931 break; 932 case MAC_GMII_MODE: 933 val |= (XMAC_XIF_GMII_MODE << 934 XMAC_XIF_MII_MODE_SHIFT); 935 break; 936 case MAC_XGMII_MODE: 937 val |= (XMAC_XIF_XGMII_MODE << 938 XMAC_XIF_MII_MODE_SHIFT); 939 break; 940 default: 941 return (NPI_FAILURE | 942 NPI_MAC_PORT_ATTR_INVALID(portn)); 943 } 944 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, 945 val); 946 } else { 947 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, 948 &val); 949 val &= XMAC_XIF_MII_MODE_MASK; 950 attr = val >> XMAC_XIF_MII_MODE_SHIFT; 951 attrp->odata[0] = attr; 952 } 953 break; 954 case BMAC_PORT_0: 955 case BMAC_PORT_1: 956 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 957 " npi_mac_port_attr" 958 " Invalid Input:" 959 " MAC_PORT_MODE <0x%x>", 960 attrp->type)); 961 return (NPI_FAILURE | 962 NPI_MAC_PORT_ATTR_INVALID(portn)); 963 default: 964 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 965 } 966 break; 967 968 case MAC_PORT_FRAME_SIZE: { 969 uint32_t min_fsize; 970 uint32_t max_fsize; 971 972 switch (portn) { 973 case XMAC_PORT_0: 974 case XMAC_PORT_1: 975 if (op == OP_SET) { 976 min_fsize = attrp->idata[0]; 977 max_fsize = attrp->idata[1]; 978 ASSERT((min_fsize & \ 979 ~XMAC_MIN_TX_FRM_SZ_MASK) == 0); 980 if ((min_fsize & ~XMAC_MIN_TX_FRM_SZ_MASK) 981 != 0) { 982 NPI_ERROR_MSG((handle.function, 983 NPI_ERR_CTL, 984 " npi_mac_port_attr" 985 " MAC_PORT_FRAME_SIZE:" 986 " Invalid Input:" 987 " xmac_min_fsize <0x%x>", 988 min_fsize)); 989 return (NPI_FAILURE | 990 NPI_MAC_PORT_ATTR_INVALID(portn)); 991 } 992 ASSERT((max_fsize & \ 993 ~XMAC_MAX_FRM_SZ_MASK) == 0); 994 if ((max_fsize & ~XMAC_MAX_FRM_SZ_MASK) 995 != 0) { 996 NPI_ERROR_MSG((handle.function, 997 NPI_ERR_CTL, 998 " npi_mac_port_attr" 999 " MAC_PORT_FRAME_SIZE:" 1000 " Invalid Input:" 1001 " xmac_max_fsize <0x%x>", 1002 max_fsize)); 1003 return (NPI_FAILURE | 1004 NPI_MAC_PORT_ATTR_INVALID(portn)); 1005 } 1006 XMAC_REG_RD(handle, portn, XMAC_MIN_REG, &val); 1007 val &= ~(XMAC_MIN_TX_FRM_SZ_MASK | 1008 XMAC_MIN_RX_FRM_SZ_MASK); 1009 val |= (min_fsize << XMAC_MIN_TX_FRM_SZ_SHIFT); 1010 val |= (min_fsize << XMAC_MIN_RX_FRM_SZ_SHIFT); 1011 XMAC_REG_WR(handle, portn, XMAC_MIN_REG, val); 1012 XMAC_REG_WR(handle, portn, XMAC_MAX_REG, 1013 max_fsize); 1014 } else { 1015 XMAC_REG_RD(handle, portn, XMAC_MIN_REG, &val); 1016 min_fsize = (val & XMAC_MIN_TX_FRM_SZ_MASK) 1017 >> XMAC_MIN_TX_FRM_SZ_SHIFT; 1018 XMAC_REG_RD(handle, portn, XMAC_MAX_REG, &val); 1019 attrp->odata[0] = min_fsize; 1020 attrp->odata[1] = max_fsize; 1021 } 1022 break; 1023 case BMAC_PORT_0: 1024 case BMAC_PORT_1: 1025 if (op == OP_SET) { 1026 min_fsize = attrp->idata[0]; 1027 max_fsize = attrp->idata[1]; 1028 ASSERT((min_fsize & ~BMAC_MIN_FRAME_MASK) == 0); 1029 if ((min_fsize & ~BMAC_MIN_FRAME_MASK) 1030 != 0) { 1031 NPI_ERROR_MSG((handle.function, 1032 NPI_ERR_CTL, 1033 " npi_mac_port_attr" 1034 " MAC_FRAME_SIZE:" 1035 " Invalid Input:" 1036 " bmac_min_fsize <0x%x>", 1037 min_fsize)); 1038 return (NPI_FAILURE | 1039 NPI_MAC_PORT_ATTR_INVALID(portn)); 1040 } 1041 ASSERT((max_fsize & ~BMAC_MAX_FRAME_MASK) == 0); 1042 if ((max_fsize & ~BMAC_MAX_FRAME_MASK) 1043 != 0) { 1044 NPI_ERROR_MSG((handle.function, 1045 NPI_ERR_CTL, 1046 " npi_mac_port_attr" 1047 " MAC_FRAME_SIZE:" 1048 " Invalid Input:" 1049 " bmac_max_fsize <0x%x>", 1050 max_fsize)); 1051 return (NPI_FAILURE | 1052 NPI_MAC_PORT_ATTR_INVALID(portn)); 1053 } 1054 BMAC_REG_RD(handle, portn, BMAC_MAX_REG, &val); 1055 val &= ~BMAC_MAX_FRAME_MASK; 1056 if (max_fsize <= MAX_FRAME_SZ1) 1057 val |= MAX_FRAME_SZ1; 1058 else if ((max_fsize > MAX_FRAME_SZ1) && 1059 (max_fsize <= MAX_FRAME_SZ2)) 1060 val |= MAX_FRAME_SZ2; 1061 else if ((max_fsize > MAX_FRAME_SZ2) && 1062 (max_fsize <= MAX_FRAME_SZ3)) 1063 val |= MAX_FRAME_SZ3; 1064 else if ((max_fsize > MAX_FRAME_SZ3) && 1065 (max_fsize <= MAX_FRAME_SZ4)) 1066 val |= MAX_FRAME_SZ4; 1067 else if ((max_fsize > MAX_FRAME_SZ4) && 1068 (max_fsize <= MAX_FRAME_SZ5)) 1069 val |= MAX_FRAME_SZ5; 1070 BMAC_REG_WR(handle, portn, BMAC_MAX_REG, val); 1071 BMAC_REG_WR(handle, portn, BMAC_MIN_REG, 1072 min_fsize); 1073 } else { 1074 BMAC_REG_RD(handle, portn, BMAC_MIN_REG, &val); 1075 min_fsize = val & BMAC_MIN_FRAME_MASK; 1076 BMAC_REG_RD(handle, portn, BMAC_MAX_REG, &val); 1077 max_fsize = val & BMAC_MAX_FRAME_MASK; 1078 attrp->odata[0] = min_fsize; 1079 attrp->odata[1] = max_fsize; 1080 } 1081 break; 1082 default: 1083 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1084 } 1085 } break; 1086 1087 case BMAC_PORT_MAX_BURST_SIZE: { 1088 uint32_t burst_size; 1089 switch (portn) { 1090 case XMAC_PORT_0: 1091 case XMAC_PORT_1: 1092 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1093 " npi_mac_port_attr" 1094 " BMAC_PORT_MAX_BURST_SIZE:" 1095 " Invalid Input: portn <%d>", 1096 portn)); 1097 return (NPI_FAILURE | NPI_MAC_PORT_ATTR_INVALID(portn)); 1098 case BMAC_PORT_0: 1099 case BMAC_PORT_1: 1100 /* NOTE: Not used in Full duplex mode */ 1101 if (op == OP_SET) { 1102 burst_size = attrp->idata[0]; 1103 ASSERT((burst_size & ~0x7FFF) == 0); 1104 if ((burst_size & ~0x7FFF) != 0) { 1105 NPI_ERROR_MSG((handle.function, 1106 NPI_ERR_CTL, 1107 " npi_mac_port_attr" 1108 " BMAC_MAX_BURST_SIZE:" 1109 " Invalid Input:" 1110 " burst_size <0x%x>", 1111 burst_size)); 1112 return (NPI_FAILURE | 1113 NPI_MAC_PORT_ATTR_INVALID(portn)); 1114 } 1115 BMAC_REG_RD(handle, portn, BMAC_MAX_REG, &val); 1116 val &= ~BMAC_MAX_BURST_MASK; 1117 val |= (burst_size << BMAC_MAX_BURST_SHIFT); 1118 BMAC_REG_WR(handle, portn, BMAC_MAX_REG, val); 1119 } else { 1120 BMAC_REG_RD(handle, portn, BMAC_MAX_REG, &val); 1121 burst_size = (val & BMAC_MAX_BURST_MASK) 1122 >> BMAC_MAX_BURST_SHIFT; 1123 attrp->odata[0] = burst_size; 1124 } 1125 break; 1126 default: 1127 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1128 } 1129 } break; 1130 1131 case BMAC_PORT_PA_SIZE: { 1132 uint32_t pa_size; 1133 switch (portn) { 1134 case XMAC_PORT_0: 1135 case XMAC_PORT_1: 1136 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1137 " npi_mac_port_attr" 1138 " BMAC_PORT_PA_SIZE:" 1139 " Invalid Input: portn <%d>", 1140 portn)); 1141 return (NPI_FAILURE | NPI_MAC_PORT_ATTR_INVALID(portn)); 1142 case BMAC_PORT_0: 1143 case BMAC_PORT_1: 1144 if (op == OP_SET) { 1145 pa_size = attrp->idata[0]; 1146 ASSERT((pa_size & ~0x3FF) == 0); 1147 if ((pa_size & ~0x3FF) != 0) { 1148 NPI_ERROR_MSG((handle.function, 1149 NPI_ERR_CTL, 1150 " npi_mac_port_attr" 1151 " BMAC_PORT_PA_SIZE:" 1152 " Invalid Input: pa_size <0x%x>", 1153 pa_size)); 1154 1155 return (NPI_FAILURE | 1156 NPI_MAC_PORT_ATTR_INVALID(portn)); 1157 } 1158 BMAC_REG_RD(handle, portn, MAC_PA_SIZE_REG, 1159 &val); 1160 val &= ~BMAC_PA_SIZE_MASK; 1161 val |= (pa_size << 0); 1162 BMAC_REG_WR(handle, portn, MAC_PA_SIZE_REG, 1163 val); 1164 } else { 1165 BMAC_REG_RD(handle, portn, MAC_PA_SIZE_REG, 1166 &val); 1167 pa_size = (val & BMAC_PA_SIZE_MASK) >> 0; 1168 attrp->odata[0] = pa_size; 1169 } 1170 break; 1171 default: 1172 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1173 } 1174 } break; 1175 1176 case BMAC_PORT_CTRL_TYPE: { 1177 uint32_t ctrl_type; 1178 switch (portn) { 1179 case XMAC_PORT_0: 1180 case XMAC_PORT_1: 1181 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1182 " npi_mac_port_attr" 1183 " BMAC_PORT_CTRL_TYPE:" 1184 " Invalid Input: portn <%d>", 1185 portn)); 1186 return (NPI_FAILURE | NPI_MAC_PORT_ATTR_INVALID(portn)); 1187 case BMAC_PORT_0: 1188 case BMAC_PORT_1: 1189 if (op == OP_SET) { 1190 ctrl_type = attrp->idata[0]; 1191 ASSERT((ctrl_type & ~0xFFFF) == 0); 1192 if ((ctrl_type & ~0xFFFF) != 0) { 1193 NPI_ERROR_MSG((handle.function, 1194 NPI_ERR_CTL, 1195 " npi_mac_port_attr" 1196 " BMAC_PORT_CTRL_TYPE:" 1197 " Invalid Input:" 1198 " ctrl_type <0x%x>", 1199 ctrl_type)); 1200 return (NPI_FAILURE | 1201 NPI_MAC_PORT_ATTR_INVALID(portn)); 1202 } 1203 BMAC_REG_WR(handle, portn, MAC_CTRL_TYPE_REG, 1204 val); 1205 } else { 1206 BMAC_REG_RD(handle, portn, MAC_CTRL_TYPE_REG, 1207 &val); 1208 ctrl_type = (val & 0xFFFF); 1209 attrp->odata[0] = ctrl_type; 1210 } 1211 break; 1212 default: 1213 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1214 } 1215 } break; 1216 1217 case XMAC_10G_PORT_IPG: 1218 { 1219 uint32_t ipg0; 1220 1221 switch (portn) { 1222 case XMAC_PORT_0: 1223 case XMAC_PORT_1: 1224 if (op == OP_SET) { 1225 ipg0 = attrp->idata[0]; 1226 ASSERT((ipg0 == XGMII_IPG_12_15) || \ 1227 (ipg0 == XGMII_IPG_16_19) || \ 1228 (ipg0 == XGMII_IPG_20_23)); 1229 if ((ipg0 != XGMII_IPG_12_15) && 1230 (ipg0 != XGMII_IPG_16_19) && 1231 (ipg0 != XGMII_IPG_20_23)) { 1232 NPI_ERROR_MSG((handle.function, 1233 NPI_ERR_CTL, 1234 " npi_mac_port_attr" 1235 " MAC_10G_PORT_IPG:" 1236 " Invalid Input:" 1237 " xgmii_ipg <0x%x>", 1238 ipg0)); 1239 return (NPI_FAILURE | 1240 NPI_MAC_PORT_ATTR_INVALID(portn)); 1241 } 1242 1243 XMAC_REG_RD(handle, portn, XMAC_IPG_REG, &val); 1244 val &= ~(XMAC_IPG_VALUE_MASK | 1245 XMAC_IPG_VALUE1_MASK); 1246 1247 switch (ipg0) { 1248 case XGMII_IPG_12_15: 1249 val |= (IPG_12_15_BYTE << 1250 XMAC_IPG_VALUE_SHIFT); 1251 break; 1252 case XGMII_IPG_16_19: 1253 val |= (IPG_16_19_BYTE << 1254 XMAC_IPG_VALUE_SHIFT); 1255 break; 1256 case XGMII_IPG_20_23: 1257 val |= (IPG_20_23_BYTE << 1258 XMAC_IPG_VALUE_SHIFT); 1259 break; 1260 default: 1261 return (NPI_FAILURE | 1262 NPI_MAC_PORT_ATTR_INVALID(portn)); 1263 } 1264 XMAC_REG_WR(handle, portn, XMAC_IPG_REG, val); 1265 } else { 1266 XMAC_REG_RD(handle, portn, XMAC_IPG_REG, &val); 1267 ipg0 = (val & XMAC_IPG_VALUE_MASK) >> 1268 XMAC_IPG_VALUE_SHIFT; 1269 switch (ipg0) { 1270 case IPG_12_15_BYTE: 1271 attrp->odata[0] = XGMII_IPG_12_15; 1272 break; 1273 case IPG_16_19_BYTE: 1274 attrp->odata[0] = XGMII_IPG_16_19; 1275 break; 1276 case IPG_20_23_BYTE: 1277 attrp->odata[0] = XGMII_IPG_20_23; 1278 break; 1279 default: 1280 return (NPI_FAILURE | 1281 NPI_MAC_PORT_ATTR_INVALID(portn)); 1282 } 1283 } 1284 break; 1285 case BMAC_PORT_0: 1286 case BMAC_PORT_1: 1287 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1288 " npi_mac_port_attr" "MAC_PORT_IPG:" 1289 " Invalid Input: portn <%d>", 1290 portn)); 1291 default: 1292 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1293 } 1294 break; 1295 } 1296 1297 case XMAC_PORT_IPG: 1298 { 1299 uint32_t ipg1; 1300 switch (portn) { 1301 case XMAC_PORT_0: 1302 case XMAC_PORT_1: 1303 if (op == OP_SET) { 1304 ipg1 = attrp->idata[0]; 1305 ASSERT((ipg1 == MII_GMII_IPG_12) || \ 1306 (ipg1 == MII_GMII_IPG_13) || \ 1307 (ipg1 == MII_GMII_IPG_14) || \ 1308 (ipg1 == MII_GMII_IPG_15) || \ 1309 (ipg1 == MII_GMII_IPG_16)); 1310 if ((ipg1 != MII_GMII_IPG_12) && 1311 (ipg1 != MII_GMII_IPG_13) && 1312 (ipg1 != MII_GMII_IPG_14) && 1313 (ipg1 != MII_GMII_IPG_15) && 1314 (ipg1 != MII_GMII_IPG_16)) { 1315 NPI_ERROR_MSG((handle.function, 1316 NPI_ERR_CTL, 1317 " npi_mac_port_attr" 1318 " XMAC_PORT_IPG:" 1319 " Invalid Input:" 1320 " mii_gmii_ipg <0x%x>", 1321 ipg1)); 1322 return (NPI_FAILURE | 1323 NPI_MAC_PORT_ATTR_INVALID(portn)); 1324 } 1325 1326 XMAC_REG_RD(handle, portn, XMAC_IPG_REG, &val); 1327 val &= ~(XMAC_IPG_VALUE_MASK | 1328 XMAC_IPG_VALUE1_MASK); 1329 1330 switch (ipg1) { 1331 case MII_GMII_IPG_12: 1332 val |= (IPG1_12_BYTES << 1333 XMAC_IPG_VALUE1_SHIFT); 1334 break; 1335 case MII_GMII_IPG_13: 1336 val |= (IPG1_13_BYTES << 1337 XMAC_IPG_VALUE1_SHIFT); 1338 break; 1339 case MII_GMII_IPG_14: 1340 val |= (IPG1_14_BYTES << 1341 XMAC_IPG_VALUE1_SHIFT); 1342 break; 1343 case MII_GMII_IPG_15: 1344 val |= (IPG1_15_BYTES << 1345 XMAC_IPG_VALUE1_SHIFT); 1346 break; 1347 case MII_GMII_IPG_16: 1348 val |= (IPG1_16_BYTES << 1349 XMAC_IPG_VALUE1_SHIFT); 1350 break; 1351 default: 1352 return (NPI_FAILURE | 1353 NPI_MAC_PORT_ATTR_INVALID(portn)); 1354 } 1355 XMAC_REG_WR(handle, portn, XMAC_IPG_REG, val); 1356 } else { 1357 XMAC_REG_RD(handle, portn, XMAC_IPG_REG, &val); 1358 ipg1 = (val & XMAC_IPG_VALUE1_MASK) >> 1359 XMAC_IPG_VALUE1_SHIFT; 1360 switch (ipg1) { 1361 case IPG1_12_BYTES: 1362 attrp->odata[1] = MII_GMII_IPG_12; 1363 break; 1364 case IPG1_13_BYTES: 1365 attrp->odata[1] = MII_GMII_IPG_13; 1366 break; 1367 case IPG1_14_BYTES: 1368 attrp->odata[1] = MII_GMII_IPG_14; 1369 break; 1370 case IPG1_15_BYTES: 1371 attrp->odata[1] = MII_GMII_IPG_15; 1372 break; 1373 case IPG1_16_BYTES: 1374 attrp->odata[1] = MII_GMII_IPG_16; 1375 break; 1376 default: 1377 return (NPI_FAILURE | 1378 NPI_MAC_PORT_ATTR_INVALID(portn)); 1379 } 1380 } 1381 break; 1382 case BMAC_PORT_0: 1383 case BMAC_PORT_1: 1384 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1385 " npi_mac_port_attr" 1386 " MAC_PORT_IPG:" 1387 " Invalid Input: portn <%d>", 1388 portn)); 1389 default: 1390 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1391 } 1392 break; 1393 } 1394 1395 case MAC_PORT_ADDR: { 1396 uint32_t addr0; 1397 uint32_t addr1; 1398 uint32_t addr2; 1399 1400 switch (portn) { 1401 case XMAC_PORT_0: 1402 case XMAC_PORT_1: 1403 if (op == OP_SET) { 1404 addr0 = attrp->idata[0]; 1405 addr1 = attrp->idata[1]; 1406 addr2 = attrp->idata[2]; 1407 ASSERT((addr0 & ~0xFFFF) == 0); 1408 if ((addr0 & ~0xFFFF) != 0) { 1409 NPI_ERROR_MSG((handle.function, 1410 NPI_ERR_CTL, 1411 " npi_mac_port_attr" 1412 " MAC_PORT_ADDR:" 1413 " Invalid Input:" 1414 " addr0 <0x%x>", addr0)); 1415 1416 return (NPI_FAILURE | 1417 NPI_MAC_PORT_ATTR_INVALID(portn)); 1418 } 1419 ASSERT((addr1 & ~0xFFFF) == 0); 1420 if ((addr1 & ~0xFFFF) != 0) { 1421 NPI_ERROR_MSG((handle.function, 1422 NPI_ERR_CTL, 1423 " npi_mac_port_attr" 1424 " MAC_PORT_ADDR:" 1425 " Invalid Input:" 1426 " addr1 <0x%x>", addr1)); 1427 return (NPI_FAILURE | 1428 NPI_MAC_PORT_ATTR_INVALID(portn)); 1429 } 1430 ASSERT((addr2 & ~0xFFFF) == 0); 1431 if ((addr2 & ~0xFFFF) != 0) { 1432 NPI_ERROR_MSG((handle.function, 1433 NPI_ERR_CTL, 1434 " npi_mac_port_attr" 1435 " MAC_PORT_ADDR:" 1436 " Invalid Input:" 1437 " addr2 <0x%x.", 1438 addr2)); 1439 1440 return (NPI_FAILURE | 1441 NPI_MAC_PORT_ATTR_INVALID(portn)); 1442 } 1443 XMAC_REG_WR(handle, portn, XMAC_ADDR0_REG, 1444 addr0); 1445 XMAC_REG_WR(handle, portn, XMAC_ADDR1_REG, 1446 addr1); 1447 XMAC_REG_WR(handle, portn, XMAC_ADDR2_REG, 1448 addr2); 1449 } else { 1450 XMAC_REG_RD(handle, portn, XMAC_ADDR0_REG, 1451 &addr0); 1452 XMAC_REG_RD(handle, portn, XMAC_ADDR1_REG, 1453 &addr1); 1454 XMAC_REG_RD(handle, portn, XMAC_ADDR2_REG, 1455 &addr2); 1456 attrp->odata[0] = addr0 & MAC_ADDR_REG_MASK; 1457 attrp->odata[1] = addr1 & MAC_ADDR_REG_MASK; 1458 attrp->odata[2] = addr2 & MAC_ADDR_REG_MASK; 1459 } 1460 break; 1461 case BMAC_PORT_0: 1462 case BMAC_PORT_1: 1463 if (op == OP_SET) { 1464 addr0 = attrp->idata[0]; 1465 addr1 = attrp->idata[1]; 1466 addr2 = attrp->idata[2]; 1467 ASSERT((addr0 & ~0xFFFF) == 0); 1468 if ((addr0 & ~0xFFFF) != 0) { 1469 NPI_ERROR_MSG((handle.function, 1470 NPI_ERR_CTL, 1471 " npi_mac_port_attr" 1472 " MAC_PORT_ADDR:" 1473 " Invalid Input:" 1474 " addr0 <0x%x>", 1475 addr0)); 1476 return (NPI_FAILURE | 1477 NPI_MAC_PORT_ATTR_INVALID(portn)); 1478 } 1479 ASSERT((addr1 & ~0xFFFF) == 0); 1480 if ((addr1 & ~0xFFFF) != 0) { 1481 NPI_ERROR_MSG((handle.function, 1482 NPI_ERR_CTL, 1483 " npi_mac_port_attr" 1484 " MAC_PORT_ADDR:" 1485 " Invalid Input:" 1486 " addr1 <0x%x>", 1487 addr1)); 1488 return (NPI_FAILURE | 1489 NPI_MAC_PORT_ATTR_INVALID(portn)); 1490 } 1491 ASSERT((addr2 & ~0xFFFF) == 0); 1492 if ((addr2 & ~0xFFFF) != 0) { 1493 NPI_ERROR_MSG((handle.function, 1494 NPI_ERR_CTL, 1495 " npi_mac_port_attr" 1496 " MAC_PORT_ADDR:" 1497 " Invalid Input:" 1498 " addr2 <0x%x>", 1499 addr2)); 1500 return (NPI_FAILURE | 1501 NPI_MAC_PORT_ATTR_INVALID(portn)); 1502 } 1503 BMAC_REG_WR(handle, portn, BMAC_ADDR0_REG, 1504 addr0); 1505 BMAC_REG_WR(handle, portn, BMAC_ADDR1_REG, 1506 addr1); 1507 BMAC_REG_WR(handle, portn, BMAC_ADDR2_REG, 1508 addr2); 1509 } else { 1510 BMAC_REG_RD(handle, portn, BMAC_ADDR0_REG, 1511 &addr0); 1512 BMAC_REG_RD(handle, portn, BMAC_ADDR1_REG, 1513 &addr1); 1514 BMAC_REG_RD(handle, portn, BMAC_ADDR2_REG, 1515 &addr2); 1516 attrp->odata[0] = addr0 & MAC_ADDR_REG_MASK; 1517 attrp->odata[1] = addr1 & MAC_ADDR_REG_MASK; 1518 attrp->odata[2] = addr2 & MAC_ADDR_REG_MASK; 1519 } 1520 break; 1521 default: 1522 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1523 } 1524 } break; 1525 1526 case MAC_PORT_ADDR_FILTER: { 1527 uint32_t addr0; 1528 uint32_t addr1; 1529 uint32_t addr2; 1530 1531 switch (portn) { 1532 case XMAC_PORT_0: 1533 case XMAC_PORT_1: 1534 if (op == OP_SET) { 1535 addr0 = attrp->idata[0]; 1536 addr1 = attrp->idata[1]; 1537 addr2 = attrp->idata[2]; 1538 ASSERT((addr0 & ~0xFFFF) == 0); 1539 if ((addr0 & ~0xFFFF) != 0) { 1540 NPI_ERROR_MSG((handle.function, 1541 NPI_ERR_CTL, 1542 " npi_mac_port_attr" 1543 " MAC_PORT_ADDR_FILTER:" 1544 " Invalid Input:" 1545 " addr0 <0x%x>", 1546 addr0)); 1547 return (NPI_FAILURE | 1548 NPI_MAC_PORT_ATTR_INVALID(portn)); 1549 } 1550 ASSERT((addr1 & ~0xFFFF) == 0); 1551 if ((addr1 & ~0xFFFF) != 0) { 1552 NPI_ERROR_MSG((handle.function, 1553 NPI_ERR_CTL, 1554 " npi_mac_port_attr" 1555 " MAC_PORT_ADDR_FILTER:" 1556 " Invalid Input:" 1557 " addr1 <0x%x>", 1558 addr1)); 1559 return (NPI_FAILURE | 1560 NPI_MAC_PORT_ATTR_INVALID(portn)); 1561 } 1562 ASSERT((addr2 & ~0xFFFF) == 0); 1563 if ((addr2 & ~0xFFFF) != 0) { 1564 NPI_ERROR_MSG((handle.function, 1565 NPI_ERR_CTL, 1566 " npi_mac_port_attr" 1567 " MAC_PORT_ADDR_FILTER:" 1568 " Invalid Input:" 1569 " addr2 <0x%x>", 1570 addr2)); 1571 return (NPI_FAILURE | 1572 NPI_MAC_PORT_ATTR_INVALID(portn)); 1573 } 1574 XMAC_REG_WR(handle, portn, 1575 XMAC_ADDR_FILT0_REG, addr0); 1576 XMAC_REG_WR(handle, portn, 1577 XMAC_ADDR_FILT1_REG, addr1); 1578 XMAC_REG_WR(handle, portn, 1579 XMAC_ADDR_FILT2_REG, addr2); 1580 } else { 1581 XMAC_REG_RD(handle, portn, 1582 XMAC_ADDR_FILT0_REG, &addr0); 1583 XMAC_REG_RD(handle, portn, 1584 XMAC_ADDR_FILT1_REG, &addr1); 1585 XMAC_REG_RD(handle, portn, 1586 XMAC_ADDR_FILT2_REG, &addr2); 1587 attrp->odata[0] = addr0 & MAC_ADDR_REG_MASK; 1588 attrp->odata[1] = addr1 & MAC_ADDR_REG_MASK; 1589 attrp->odata[2] = addr2 & MAC_ADDR_REG_MASK; 1590 } 1591 break; 1592 case BMAC_PORT_0: 1593 case BMAC_PORT_1: 1594 if (op == OP_SET) { 1595 addr0 = attrp->idata[0]; 1596 addr1 = attrp->idata[1]; 1597 addr2 = attrp->idata[2]; 1598 ASSERT((addr0 & ~0xFFFF) == 0); 1599 if ((addr0 & ~0xFFFF) != 0) { 1600 NPI_ERROR_MSG((handle.function, 1601 NPI_ERR_CTL, 1602 " npi_mac_port_attr" 1603 " MAC_PORT_ADDR_FILTER:" 1604 " addr0", 1605 addr0)); 1606 return (NPI_FAILURE | 1607 NPI_MAC_PORT_ATTR_INVALID(portn)); 1608 } 1609 ASSERT((addr1 & ~0xFFFF) == 0); 1610 if ((addr1 & ~0xFFFF) != 0) { 1611 NPI_ERROR_MSG((handle.function, 1612 NPI_ERR_CTL, 1613 " npi_mac_port_attr" 1614 " MAC_PORT_ADDR_FILTER:" 1615 " Invalid Input:" 1616 " addr1 <0x%x>", 1617 addr1)); 1618 return (NPI_FAILURE | 1619 NPI_MAC_PORT_ATTR_INVALID(portn)); 1620 } 1621 ASSERT((addr2 & ~0xFFFF) == 0); 1622 if ((addr2 & ~0xFFFF) != 0) { 1623 NPI_ERROR_MSG((handle.function, 1624 NPI_ERR_CTL, 1625 " npi_mac_port_attr" 1626 " MAC_PORT_ADDR_FILTER:" 1627 " Invalid Input:" 1628 " addr2 <0x%x>", 1629 addr2)); 1630 return (NPI_FAILURE | 1631 NPI_MAC_PORT_ATTR_INVALID(portn)); 1632 } 1633 BMAC_REG_WR(handle, portn, MAC_ADDR_FILT0_REG, 1634 addr0); 1635 BMAC_REG_WR(handle, portn, MAC_ADDR_FILT1_REG, 1636 addr1); 1637 BMAC_REG_WR(handle, portn, MAC_ADDR_FILT2_REG, 1638 addr2); 1639 } else { 1640 BMAC_REG_RD(handle, portn, MAC_ADDR_FILT0_REG, 1641 &addr0); 1642 BMAC_REG_RD(handle, portn, MAC_ADDR_FILT1_REG, 1643 &addr1); 1644 BMAC_REG_RD(handle, portn, MAC_ADDR_FILT2_REG, 1645 &addr2); 1646 attrp->odata[0] = addr0 & MAC_ADDR_REG_MASK; 1647 attrp->odata[1] = addr1 & MAC_ADDR_REG_MASK; 1648 attrp->odata[2] = addr2 & MAC_ADDR_REG_MASK; 1649 } 1650 break; 1651 default: 1652 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1653 } 1654 } break; 1655 1656 case MAC_PORT_ADDR_FILTER_MASK: { 1657 uint32_t mask_1_2; 1658 uint32_t mask_0; 1659 1660 switch (portn) { 1661 case XMAC_PORT_0: 1662 case XMAC_PORT_1: 1663 if (op == OP_SET) { 1664 mask_0 = attrp->idata[0]; 1665 mask_1_2 = attrp->idata[1]; 1666 ASSERT((mask_0 & ~0xFFFF) == 0); 1667 if ((mask_0 & ~0xFFFF) != 0) { 1668 NPI_ERROR_MSG((handle.function, 1669 NPI_ERR_CTL, 1670 " npi_mac_port_attr" 1671 " MAC_ADDR_FILTER_MASK:" 1672 " Invalid Input:" 1673 " mask_0 <0x%x>", 1674 mask_0)); 1675 return (NPI_FAILURE | 1676 NPI_MAC_PORT_ATTR_INVALID(portn)); 1677 } 1678 ASSERT((mask_1_2 & ~0xFF) == 0); 1679 if ((mask_1_2 & ~0xFF) != 0) { 1680 NPI_ERROR_MSG((handle.function, 1681 NPI_ERR_CTL, 1682 " npi_mac_port_attr" 1683 " MAC_ADDR_FILTER_MASK:" 1684 " Invalid Input:" 1685 " mask_1_2 <0x%x>", 1686 mask_1_2)); 1687 return (NPI_FAILURE | 1688 NPI_MAC_PORT_ATTR_INVALID(portn)); 1689 } 1690 XMAC_REG_WR(handle, portn, 1691 XMAC_ADDR_FILT0_MASK_REG, mask_0); 1692 XMAC_REG_WR(handle, portn, 1693 XMAC_ADDR_FILT12_MASK_REG, mask_1_2); 1694 } else { 1695 XMAC_REG_RD(handle, portn, 1696 XMAC_ADDR_FILT0_MASK_REG, &mask_0); 1697 XMAC_REG_RD(handle, portn, 1698 XMAC_ADDR_FILT12_MASK_REG, &mask_1_2); 1699 attrp->odata[0] = mask_0 & 0xFFFF; 1700 attrp->odata[1] = mask_1_2 & 0xFF; 1701 } 1702 break; 1703 case BMAC_PORT_0: 1704 case BMAC_PORT_1: 1705 if (op == OP_SET) { 1706 mask_0 = attrp->idata[0]; 1707 mask_1_2 = attrp->idata[1]; 1708 BMAC_REG_WR(handle, portn, 1709 MAC_ADDR_FILT00_MASK_REG, mask_0); 1710 BMAC_REG_WR(handle, portn, 1711 MAC_ADDR_FILT12_MASK_REG, mask_1_2); 1712 } else { 1713 BMAC_REG_RD(handle, portn, 1714 MAC_ADDR_FILT00_MASK_REG, &mask_0); 1715 BMAC_REG_RD(handle, portn, 1716 MAC_ADDR_FILT12_MASK_REG, &mask_1_2); 1717 attrp->odata[0] = mask_0; 1718 attrp->odata[1] = mask_1_2; 1719 } 1720 break; 1721 default: 1722 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1723 } 1724 } break; 1725 1726 default: 1727 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1728 " npi_mac_port_attr" 1729 " Invalid Input:" 1730 " attr <0x%x>", attrp->type)); 1731 return (NPI_FAILURE | NPI_MAC_PORT_ATTR_INVALID(portn)); 1732 } 1733 1734 return (NPI_SUCCESS); 1735 } 1736 1737 npi_status_t 1738 npi_xmac_reset(npi_handle_t handle, uint8_t portn, npi_mac_reset_t mode) 1739 { 1740 uint64_t val; 1741 boolean_t txmac = B_FALSE; 1742 1743 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 1744 1745 switch (mode) { 1746 case XTX_MAC_REG_RESET: 1747 XMAC_REG_WR(handle, portn, XTXMAC_SW_RST_REG, XTXMAC_REG_RST); 1748 XMAC_WAIT_REG(handle, portn, XTXMAC_SW_RST_REG, val); 1749 txmac = B_TRUE; 1750 break; 1751 case XRX_MAC_REG_RESET: 1752 XMAC_REG_WR(handle, portn, XRXMAC_SW_RST_REG, XRXMAC_REG_RST); 1753 XMAC_WAIT_REG(handle, portn, XRXMAC_SW_RST_REG, val); 1754 break; 1755 case XTX_MAC_LOGIC_RESET: 1756 XMAC_REG_WR(handle, portn, XTXMAC_SW_RST_REG, XTXMAC_SOFT_RST); 1757 XMAC_WAIT_REG(handle, portn, XTXMAC_SW_RST_REG, val); 1758 txmac = B_TRUE; 1759 break; 1760 case XRX_MAC_LOGIC_RESET: 1761 XMAC_REG_WR(handle, portn, XRXMAC_SW_RST_REG, XRXMAC_SOFT_RST); 1762 XMAC_WAIT_REG(handle, portn, XRXMAC_SW_RST_REG, val); 1763 break; 1764 case XTX_MAC_RESET_ALL: 1765 XMAC_REG_WR(handle, portn, XTXMAC_SW_RST_REG, 1766 XTXMAC_SOFT_RST | XTXMAC_REG_RST); 1767 XMAC_WAIT_REG(handle, portn, XTXMAC_SW_RST_REG, val); 1768 txmac = B_TRUE; 1769 break; 1770 case XRX_MAC_RESET_ALL: 1771 XMAC_REG_WR(handle, portn, XRXMAC_SW_RST_REG, 1772 XRXMAC_SOFT_RST | XRXMAC_REG_RST); 1773 XMAC_WAIT_REG(handle, portn, XRXMAC_SW_RST_REG, val); 1774 break; 1775 default: 1776 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1777 " npi_mac_reset" 1778 " Invalid Input: mode <0x%x>", 1779 mode)); 1780 return (NPI_FAILURE | NPI_MAC_RESET_MODE_INVALID(portn)); 1781 } 1782 1783 if (val != 0) { 1784 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1785 " npi_xmac_reset" 1786 " HW ERROR: MAC_RESET failed <0x%x>", 1787 val)); 1788 1789 if (txmac) 1790 return (NPI_FAILURE | NPI_TXMAC_RESET_FAILED(portn)); 1791 else 1792 return (NPI_FAILURE | NPI_RXMAC_RESET_FAILED(portn)); 1793 } 1794 1795 return (NPI_SUCCESS); 1796 } 1797 1798 npi_status_t 1799 npi_xmac_xif_config(npi_handle_t handle, config_op_t op, uint8_t portn, 1800 xmac_xif_config_t config) 1801 { 1802 uint64_t val = 0; 1803 1804 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 1805 1806 switch (op) { 1807 case ENABLE: 1808 case DISABLE: 1809 ASSERT((config != 0) && ((config & ~CFG_XMAC_XIF_ALL) == 0)); 1810 if ((config == 0) || (config & ~CFG_XMAC_XIF_ALL) != 0) { 1811 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1812 " npi_xmac_xif_config" 1813 " Invalid Input:" 1814 " config <0x%x>", config)); 1815 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 1816 } 1817 if (op == ENABLE) { 1818 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1819 if (config & CFG_XMAC_XIF_LED_FORCE) 1820 val |= XMAC_XIF_FORCE_LED_ON; 1821 if (config & CFG_XMAC_XIF_LED_POLARITY) 1822 val |= XMAC_XIF_LED_POLARITY; 1823 if (config & CFG_XMAC_XIF_SEL_POR_CLK_SRC) 1824 val |= XMAC_XIF_SEL_POR_CLK_SRC; 1825 if (config & CFG_XMAC_XIF_TX_OUTPUT) 1826 val |= XMAC_XIF_TX_OUTPUT_EN; 1827 1828 if (config & CFG_XMAC_XIF_LOOPBACK) { 1829 val &= ~XMAC_XIF_SEL_POR_CLK_SRC; 1830 val |= XMAC_XIF_LOOPBACK; 1831 } 1832 1833 if (config & CFG_XMAC_XIF_LFS) 1834 val &= ~XMAC_XIF_LFS_DISABLE; 1835 if (config & CFG_XMAC_XIF_XPCS_BYPASS) 1836 val |= XMAC_XIF_XPCS_BYPASS; 1837 if (config & CFG_XMAC_XIF_1G_PCS_BYPASS) 1838 val |= XMAC_XIF_1G_PCS_BYPASS; 1839 if (config & CFG_XMAC_XIF_SEL_CLK_25MHZ) 1840 val |= XMAC_XIF_SEL_CLK_25MHZ; 1841 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1842 1843 } else { 1844 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1845 if (config & CFG_XMAC_XIF_LED_FORCE) 1846 val &= ~XMAC_XIF_FORCE_LED_ON; 1847 if (config & CFG_XMAC_XIF_LED_POLARITY) 1848 val &= ~XMAC_XIF_LED_POLARITY; 1849 if (config & CFG_XMAC_XIF_SEL_POR_CLK_SRC) 1850 val &= ~XMAC_XIF_SEL_POR_CLK_SRC; 1851 if (config & CFG_XMAC_XIF_TX_OUTPUT) 1852 val &= ~XMAC_XIF_TX_OUTPUT_EN; 1853 if (config & CFG_XMAC_XIF_LOOPBACK) 1854 val &= ~XMAC_XIF_LOOPBACK; 1855 if (config & CFG_XMAC_XIF_LFS) 1856 val |= XMAC_XIF_LFS_DISABLE; 1857 if (config & CFG_XMAC_XIF_XPCS_BYPASS) 1858 val &= ~XMAC_XIF_XPCS_BYPASS; 1859 if (config & CFG_XMAC_XIF_1G_PCS_BYPASS) 1860 val &= ~XMAC_XIF_1G_PCS_BYPASS; 1861 if (config & CFG_XMAC_XIF_SEL_CLK_25MHZ) 1862 val &= ~XMAC_XIF_SEL_CLK_25MHZ; 1863 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1864 } 1865 break; 1866 case INIT: 1867 ASSERT((config & ~CFG_XMAC_XIF_ALL) == 0); 1868 if ((config & ~CFG_XMAC_XIF_ALL) != 0) { 1869 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1870 " npi_xmac_xif_config" 1871 " Invalid Input: config <0x%x>", 1872 config)); 1873 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 1874 } 1875 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1876 1877 if (config & CFG_XMAC_XIF_LED_FORCE) 1878 val |= XMAC_XIF_FORCE_LED_ON; 1879 else 1880 val &= ~XMAC_XIF_FORCE_LED_ON; 1881 if (config & CFG_XMAC_XIF_LED_POLARITY) 1882 val |= XMAC_XIF_LED_POLARITY; 1883 else 1884 val &= ~XMAC_XIF_LED_POLARITY; 1885 if (config & CFG_XMAC_XIF_SEL_POR_CLK_SRC) 1886 val |= XMAC_XIF_SEL_POR_CLK_SRC; 1887 else 1888 val &= ~XMAC_XIF_SEL_POR_CLK_SRC; 1889 if (config & CFG_XMAC_XIF_TX_OUTPUT) 1890 val |= XMAC_XIF_TX_OUTPUT_EN; 1891 else 1892 val &= ~XMAC_XIF_TX_OUTPUT_EN; 1893 1894 if (config & CFG_XMAC_XIF_LOOPBACK) { 1895 val &= ~XMAC_XIF_SEL_POR_CLK_SRC; 1896 val |= XMAC_XIF_LOOPBACK; 1897 #ifdef AXIS_DEBUG_LB 1898 val |= XMAC_RX_MAC2IPP_PKT_CNT_EN; 1899 #endif 1900 } else { 1901 val &= ~XMAC_XIF_LOOPBACK; 1902 } 1903 1904 if (config & CFG_XMAC_XIF_LFS) 1905 val &= ~XMAC_XIF_LFS_DISABLE; 1906 else 1907 val |= XMAC_XIF_LFS_DISABLE; 1908 if (config & CFG_XMAC_XIF_XPCS_BYPASS) 1909 val |= XMAC_XIF_XPCS_BYPASS; 1910 else 1911 val &= ~XMAC_XIF_XPCS_BYPASS; 1912 if (config & CFG_XMAC_XIF_1G_PCS_BYPASS) 1913 val |= XMAC_XIF_1G_PCS_BYPASS; 1914 else 1915 val &= ~XMAC_XIF_1G_PCS_BYPASS; 1916 if (config & CFG_XMAC_XIF_SEL_CLK_25MHZ) 1917 val |= XMAC_XIF_SEL_CLK_25MHZ; 1918 else 1919 val &= ~XMAC_XIF_SEL_CLK_25MHZ; 1920 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1921 1922 break; 1923 default: 1924 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1925 " npi_xmac_xif_config" 1926 " Invalid Input: op <0x%x>", op)); 1927 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 1928 } 1929 1930 return (NPI_SUCCESS); 1931 } 1932 1933 npi_status_t 1934 npi_xmac_tx_config(npi_handle_t handle, config_op_t op, uint8_t portn, 1935 xmac_tx_config_t config) 1936 { 1937 uint64_t val = 0; 1938 1939 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 1940 1941 switch (op) { 1942 case ENABLE: 1943 case DISABLE: 1944 ASSERT((config != 0) && ((config & ~CFG_XMAC_TX_ALL) == 0)); 1945 if ((config == 0) || (config & ~CFG_XMAC_TX_ALL) != 0) { 1946 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1947 " npi_xmac_tx_config" 1948 " Invalid Input: config <0x%x>", 1949 config)); 1950 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 1951 } 1952 if (op == ENABLE) { 1953 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1954 if (config & CFG_XMAC_TX) 1955 val |= XMAC_TX_CFG_TX_ENABLE; 1956 if (config & CFG_XMAC_TX_STRETCH_MODE) 1957 val |= XMAC_TX_CFG_STRETCH_MD; 1958 if (config & CFG_XMAC_VAR_IPG) 1959 val |= XMAC_TX_CFG_VAR_MIN_IPG_EN; 1960 if (config & CFG_XMAC_TX_CRC) 1961 val &= ~XMAC_TX_CFG_ALWAYS_NO_CRC; 1962 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1963 } else { 1964 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1965 if (config & CFG_XMAC_TX) 1966 val &= ~XMAC_TX_CFG_TX_ENABLE; 1967 if (config & CFG_XMAC_TX_STRETCH_MODE) 1968 val &= ~XMAC_TX_CFG_STRETCH_MD; 1969 if (config & CFG_XMAC_VAR_IPG) 1970 val &= ~XMAC_TX_CFG_VAR_MIN_IPG_EN; 1971 if (config & CFG_XMAC_TX_CRC) 1972 val |= XMAC_TX_CFG_ALWAYS_NO_CRC; 1973 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1974 } 1975 break; 1976 case INIT: 1977 ASSERT((config & ~CFG_XMAC_TX_ALL) == 0); 1978 if ((config & ~CFG_XMAC_TX_ALL) != 0) { 1979 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1980 " npi_xmac_tx_config" 1981 " Invalid Input: config <0x%x>", 1982 config)); 1983 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 1984 } 1985 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1986 if (config & CFG_XMAC_TX) 1987 val |= XMAC_TX_CFG_TX_ENABLE; 1988 else 1989 val &= ~XMAC_TX_CFG_TX_ENABLE; 1990 if (config & CFG_XMAC_TX_STRETCH_MODE) 1991 val |= XMAC_TX_CFG_STRETCH_MD; 1992 else 1993 val &= ~XMAC_TX_CFG_STRETCH_MD; 1994 if (config & CFG_XMAC_VAR_IPG) 1995 val |= XMAC_TX_CFG_VAR_MIN_IPG_EN; 1996 else 1997 val &= ~XMAC_TX_CFG_VAR_MIN_IPG_EN; 1998 if (config & CFG_XMAC_TX_CRC) 1999 val &= ~XMAC_TX_CFG_ALWAYS_NO_CRC; 2000 else 2001 val |= XMAC_TX_CFG_ALWAYS_NO_CRC; 2002 2003 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 2004 break; 2005 default: 2006 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2007 " npi_xmac_tx_config" 2008 " Invalid Input: op <0x%x>", 2009 op)); 2010 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2011 } 2012 2013 return (NPI_SUCCESS); 2014 } 2015 2016 npi_status_t 2017 npi_xmac_rx_config(npi_handle_t handle, config_op_t op, uint8_t portn, 2018 xmac_rx_config_t config) 2019 { 2020 uint64_t val = 0; 2021 2022 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2023 2024 switch (op) { 2025 case ENABLE: 2026 case DISABLE: 2027 ASSERT((config != 0) && ((config & ~CFG_XMAC_RX_ALL) == 0)); 2028 if ((config == 0) || (config & ~CFG_XMAC_RX_ALL) != 0) { 2029 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2030 " npi_xmac_rx_config" 2031 " Invalid Input: config <0x%x>", 2032 config)); 2033 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2034 } 2035 if (op == ENABLE) { 2036 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 2037 if (config & CFG_XMAC_RX) 2038 val |= XMAC_RX_CFG_RX_ENABLE; 2039 if (config & CFG_XMAC_RX_PROMISCUOUS) 2040 val |= XMAC_RX_CFG_PROMISC; 2041 if (config & CFG_XMAC_RX_PROMISCUOUSGROUP) 2042 val |= XMAC_RX_CFG_PROMISC_GROUP; 2043 if (config & CFG_XMAC_RX_ERRCHK) 2044 val &= ~XMAC_RX_CFG_ERR_CHK_DISABLE; 2045 if (config & CFG_XMAC_RX_CRC_CHK) 2046 val &= ~XMAC_RX_CFG_CRC_CHK_DISABLE; 2047 if (config & CFG_XMAC_RX_RESV_MULTICAST) 2048 val |= XMAC_RX_CFG_RESERVED_MCAST; 2049 if (config & CFG_XMAC_RX_CODE_VIO_CHK) 2050 val &= ~XMAC_RX_CFG_CD_VIO_CHK; 2051 if (config & CFG_XMAC_RX_HASH_FILTER) 2052 val |= XMAC_RX_CFG_HASH_FILTER_EN; 2053 if (config & CFG_XMAC_RX_ADDR_FILTER) 2054 val |= XMAC_RX_CFG_ADDR_FILTER_EN; 2055 if (config & CFG_XMAC_RX_STRIP_CRC) 2056 val |= XMAC_RX_CFG_STRIP_CRC; 2057 if (config & CFG_XMAC_RX_PAUSE) 2058 val |= XMAC_RX_CFG_RX_PAUSE_EN; 2059 if (config & CFG_XMAC_RX_PASS_FC_FRAME) 2060 val |= XMAC_RX_CFG_PASS_FLOW_CTRL; 2061 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 2062 } else { 2063 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 2064 if (config & CFG_XMAC_RX) 2065 val &= ~XMAC_RX_CFG_RX_ENABLE; 2066 if (config & CFG_XMAC_RX_PROMISCUOUS) 2067 val &= ~XMAC_RX_CFG_PROMISC; 2068 if (config & CFG_XMAC_RX_PROMISCUOUSGROUP) 2069 val &= ~XMAC_RX_CFG_PROMISC_GROUP; 2070 if (config & CFG_XMAC_RX_ERRCHK) 2071 val |= XMAC_RX_CFG_ERR_CHK_DISABLE; 2072 if (config & CFG_XMAC_RX_CRC_CHK) 2073 val |= XMAC_RX_CFG_CRC_CHK_DISABLE; 2074 if (config & CFG_XMAC_RX_RESV_MULTICAST) 2075 val &= ~XMAC_RX_CFG_RESERVED_MCAST; 2076 if (config & CFG_XMAC_RX_CODE_VIO_CHK) 2077 val |= XMAC_RX_CFG_CD_VIO_CHK; 2078 if (config & CFG_XMAC_RX_HASH_FILTER) 2079 val &= ~XMAC_RX_CFG_HASH_FILTER_EN; 2080 if (config & CFG_XMAC_RX_ADDR_FILTER) 2081 val &= ~XMAC_RX_CFG_ADDR_FILTER_EN; 2082 if (config & CFG_XMAC_RX_STRIP_CRC) 2083 val &= ~XMAC_RX_CFG_STRIP_CRC; 2084 if (config & CFG_XMAC_RX_PAUSE) 2085 val &= ~XMAC_RX_CFG_RX_PAUSE_EN; 2086 if (config & CFG_XMAC_RX_PASS_FC_FRAME) 2087 val &= ~XMAC_RX_CFG_PASS_FLOW_CTRL; 2088 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 2089 } 2090 break; 2091 case INIT: 2092 ASSERT((config & ~CFG_XMAC_RX_ALL) == 0); 2093 if ((config & ~CFG_XMAC_RX_ALL) != 0) { 2094 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2095 " npi_xmac_rx_config" 2096 " Invalid Input: config <0x%x>", 2097 config)); 2098 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2099 } 2100 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 2101 if (config & CFG_XMAC_RX) 2102 val |= XMAC_RX_CFG_RX_ENABLE; 2103 else 2104 val &= ~XMAC_RX_CFG_RX_ENABLE; 2105 if (config & CFG_XMAC_RX_PROMISCUOUS) 2106 val |= XMAC_RX_CFG_PROMISC; 2107 else 2108 val &= ~XMAC_RX_CFG_PROMISC; 2109 if (config & CFG_XMAC_RX_PROMISCUOUSGROUP) 2110 val |= XMAC_RX_CFG_PROMISC_GROUP; 2111 else 2112 val &= ~XMAC_RX_CFG_PROMISC_GROUP; 2113 if (config & CFG_XMAC_RX_ERRCHK) 2114 val &= ~XMAC_RX_CFG_ERR_CHK_DISABLE; 2115 else 2116 val |= XMAC_RX_CFG_ERR_CHK_DISABLE; 2117 if (config & CFG_XMAC_RX_CRC_CHK) 2118 val &= ~XMAC_RX_CFG_CRC_CHK_DISABLE; 2119 else 2120 val |= XMAC_RX_CFG_CRC_CHK_DISABLE; 2121 if (config & CFG_XMAC_RX_RESV_MULTICAST) 2122 val |= XMAC_RX_CFG_RESERVED_MCAST; 2123 else 2124 val &= ~XMAC_RX_CFG_RESERVED_MCAST; 2125 if (config & CFG_XMAC_RX_CODE_VIO_CHK) 2126 val &= ~XMAC_RX_CFG_CD_VIO_CHK; 2127 else 2128 val |= XMAC_RX_CFG_CD_VIO_CHK; 2129 if (config & CFG_XMAC_RX_HASH_FILTER) 2130 val |= XMAC_RX_CFG_HASH_FILTER_EN; 2131 else 2132 val &= ~XMAC_RX_CFG_HASH_FILTER_EN; 2133 if (config & CFG_XMAC_RX_ADDR_FILTER) 2134 val |= XMAC_RX_CFG_ADDR_FILTER_EN; 2135 else 2136 val &= ~XMAC_RX_CFG_ADDR_FILTER_EN; 2137 if (config & CFG_XMAC_RX_PAUSE) 2138 val |= XMAC_RX_CFG_RX_PAUSE_EN; 2139 else 2140 val &= ~XMAC_RX_CFG_RX_PAUSE_EN; 2141 if (config & CFG_XMAC_RX_STRIP_CRC) 2142 val |= XMAC_RX_CFG_STRIP_CRC; 2143 else 2144 val &= ~XMAC_RX_CFG_STRIP_CRC; 2145 if (config & CFG_XMAC_RX_PASS_FC_FRAME) 2146 val |= XMAC_RX_CFG_PASS_FLOW_CTRL; 2147 else 2148 val &= ~XMAC_RX_CFG_PASS_FLOW_CTRL; 2149 2150 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 2151 break; 2152 default: 2153 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2154 " npi_xmac_rx_config" 2155 " Invalid Input: op <0x%x>", op)); 2156 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2157 } 2158 2159 return (NPI_SUCCESS); 2160 } 2161 2162 npi_status_t 2163 npi_xmac_tx_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2164 xmac_tx_iconfig_t iconfig) 2165 { 2166 uint64_t val = 0; 2167 2168 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2169 2170 switch (op) { 2171 case ENABLE: 2172 case DISABLE: 2173 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_XMAC_TX_ALL) == 0)); 2174 if ((iconfig == 0) || (iconfig & ~ICFG_XMAC_TX_ALL) != 0) { 2175 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2176 " npi_xmac_tx_iconfig" 2177 " Invalid Input: iconfig <0x%x>", 2178 iconfig)); 2179 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2180 } 2181 XMAC_REG_RD(handle, portn, XTXMAC_STAT_MSK_REG, &val); 2182 if (op == ENABLE) 2183 val &= ~iconfig; 2184 else 2185 val |= iconfig; 2186 XMAC_REG_WR(handle, portn, XTXMAC_STAT_MSK_REG, val); 2187 2188 break; 2189 case INIT: 2190 ASSERT((iconfig & ~ICFG_XMAC_TX_ALL) == 0); 2191 if ((iconfig & ~ICFG_XMAC_TX_ALL) != 0) { 2192 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2193 " npi_xmac_tx_iconfig" 2194 " Invalid Input: iconfig <0x%x>", 2195 iconfig)); 2196 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2197 } 2198 XMAC_REG_WR(handle, portn, XTXMAC_STAT_MSK_REG, ~iconfig); 2199 2200 break; 2201 default: 2202 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2203 " npi_xmac_tx_iconfig" 2204 " Invalid Input: iconfig <0x%x>", 2205 iconfig)); 2206 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2207 } 2208 2209 return (NPI_SUCCESS); 2210 } 2211 2212 npi_status_t 2213 npi_xmac_rx_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2214 xmac_rx_iconfig_t iconfig) 2215 { 2216 uint64_t val = 0; 2217 2218 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2219 2220 switch (op) { 2221 case ENABLE: 2222 case DISABLE: 2223 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_XMAC_RX_ALL) == 0)); 2224 if ((iconfig == 0) || (iconfig & ~ICFG_XMAC_RX_ALL) != 0) { 2225 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2226 " npi_xmac_rx_iconfig" 2227 " Invalid Input: iconfig <0x%x>", 2228 iconfig)); 2229 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2230 } 2231 XMAC_REG_RD(handle, portn, XRXMAC_STAT_MSK_REG, &val); 2232 if (op == ENABLE) 2233 val &= ~iconfig; 2234 else 2235 val |= iconfig; 2236 XMAC_REG_WR(handle, portn, XRXMAC_STAT_MSK_REG, val); 2237 2238 break; 2239 case INIT: 2240 ASSERT((iconfig & ~ICFG_XMAC_RX_ALL) == 0); 2241 if ((iconfig & ~ICFG_XMAC_RX_ALL) != 0) { 2242 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2243 " npi_xmac_rx_iconfig" 2244 " Invalid Input: iconfig <0x%x>", 2245 iconfig)); 2246 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2247 } 2248 XMAC_REG_WR(handle, portn, XRXMAC_STAT_MSK_REG, ~iconfig); 2249 2250 break; 2251 default: 2252 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2253 " npi_xmac_rx_iconfig" 2254 " Invalid Input: iconfig <0x%x>", 2255 iconfig)); 2256 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2257 } 2258 2259 return (NPI_SUCCESS); 2260 } 2261 2262 npi_status_t 2263 npi_xmac_ctl_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2264 xmac_ctl_iconfig_t iconfig) 2265 { 2266 uint64_t val = 0; 2267 2268 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2269 2270 switch (op) { 2271 case ENABLE: 2272 case DISABLE: 2273 ASSERT((iconfig != 0) && \ 2274 ((iconfig & ~ICFG_XMAC_CTRL_ALL) == 0)); 2275 if ((iconfig == 0) || (iconfig & ~ICFG_XMAC_CTRL_ALL) != 0) { 2276 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2277 " npi_xmac_ctl_iconfig" 2278 " Invalid Input: iconfig <0x%x>", 2279 iconfig)); 2280 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2281 } 2282 XMAC_REG_RD(handle, portn, XMAC_C_S_MSK_REG, &val); 2283 if (op == ENABLE) 2284 val &= ~iconfig; 2285 else 2286 val |= iconfig; 2287 XMAC_REG_WR(handle, portn, XMAC_C_S_MSK_REG, val); 2288 2289 break; 2290 case INIT: 2291 ASSERT((iconfig & ~ICFG_XMAC_CTRL_ALL) == 0); 2292 if ((iconfig & ~ICFG_XMAC_CTRL_ALL) != 0) { 2293 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2294 " npi_xmac_ctl_iconfig" 2295 " Invalid Input: iconfig <0x%x>", 2296 iconfig)); 2297 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2298 } 2299 XMAC_REG_WR(handle, portn, XMAC_C_S_MSK_REG, ~iconfig); 2300 2301 break; 2302 default: 2303 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2304 " npi_xmac_ctl_iconfig" 2305 " Invalid Input: iconfig <0x%x>", 2306 iconfig)); 2307 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2308 } 2309 2310 return (NPI_SUCCESS); 2311 } 2312 2313 npi_status_t 2314 npi_xmac_tx_get_istatus(npi_handle_t handle, uint8_t portn, 2315 xmac_tx_iconfig_t *istatus) 2316 { 2317 uint64_t val; 2318 2319 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2320 2321 XMAC_REG_RD(handle, portn, XTXMAC_STATUS_REG, &val); 2322 *istatus = (uint32_t)val; 2323 2324 return (NPI_SUCCESS); 2325 } 2326 2327 npi_status_t 2328 npi_xmac_rx_get_istatus(npi_handle_t handle, uint8_t portn, 2329 xmac_rx_iconfig_t *istatus) 2330 { 2331 uint64_t val; 2332 2333 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2334 2335 XMAC_REG_RD(handle, portn, XRXMAC_STATUS_REG, &val); 2336 *istatus = (uint32_t)val; 2337 2338 return (NPI_SUCCESS); 2339 } 2340 2341 npi_status_t 2342 npi_xmac_ctl_get_istatus(npi_handle_t handle, uint8_t portn, 2343 xmac_ctl_iconfig_t *istatus) 2344 { 2345 uint64_t val; 2346 2347 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2348 2349 XMAC_REG_RD(handle, portn, XMAC_CTRL_STAT_REG, &val); 2350 *istatus = (uint32_t)val; 2351 2352 return (NPI_SUCCESS); 2353 } 2354 2355 npi_status_t 2356 npi_xmac_xpcs_reset(npi_handle_t handle, uint8_t portn) 2357 { 2358 uint64_t val; 2359 2360 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2361 2362 XPCS_REG_RD(handle, portn, XPCS_CTRL_1_REG, &val); 2363 val |= XPCS_CTRL1_RST; 2364 XPCS_REG_WR(handle, portn, XPCS_CTRL_1_REG, val); 2365 2366 return (NPI_SUCCESS); 2367 } 2368 2369 npi_status_t 2370 npi_xmac_xpcs_enable(npi_handle_t handle, uint8_t portn) 2371 { 2372 uint64_t val; 2373 2374 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2375 2376 XPCS_REG_RD(handle, portn, XPCS_CFG_VENDOR_1_REG, &val); 2377 val |= XPCS_CFG_XPCS_ENABLE; 2378 XPCS_REG_WR(handle, portn, XPCS_CFG_VENDOR_1_REG, val); 2379 2380 return (NPI_SUCCESS); 2381 } 2382 2383 npi_status_t 2384 npi_xmac_xpcs_disable(npi_handle_t handle, uint8_t portn) 2385 { 2386 uint64_t val; 2387 2388 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2389 2390 XPCS_REG_RD(handle, portn, XPCS_CFG_VENDOR_1_REG, &val); 2391 val &= ~XPCS_CFG_XPCS_ENABLE; 2392 XPCS_REG_WR(handle, portn, XPCS_CFG_VENDOR_1_REG, val); 2393 2394 return (NPI_SUCCESS); 2395 } 2396 2397 npi_status_t 2398 npi_xmac_xpcs_read(npi_handle_t handle, uint8_t portn, uint8_t xpcs_reg, 2399 uint32_t *value) 2400 { 2401 uint32_t reg; 2402 uint64_t val; 2403 2404 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2405 2406 switch (xpcs_reg) { 2407 case XPCS_REG_CONTROL1: 2408 reg = XPCS_CTRL_1_REG; 2409 break; 2410 case XPCS_REG_STATUS1: 2411 reg = XPCS_STATUS_1_REG; 2412 break; 2413 case XPCS_REG_DEVICE_ID: 2414 reg = XPCS_DEV_ID_REG; 2415 break; 2416 case XPCS_REG_SPEED_ABILITY: 2417 reg = XPCS_SPEED_ABILITY_REG; 2418 break; 2419 case XPCS_REG_DEVICE_IN_PKG: 2420 reg = XPCS_DEV_IN_PKG_REG; 2421 break; 2422 case XPCS_REG_CONTROL2: 2423 reg = XPCS_CTRL_2_REG; 2424 break; 2425 case XPCS_REG_STATUS2: 2426 reg = XPCS_STATUS_2_REG; 2427 break; 2428 case XPCS_REG_PKG_ID: 2429 reg = XPCS_PKG_ID_REG; 2430 break; 2431 case XPCS_REG_STATUS: 2432 reg = XPCS_STATUS_REG; 2433 break; 2434 case XPCS_REG_TEST_CONTROL: 2435 reg = XPCS_TEST_CTRL_REG; 2436 break; 2437 case XPCS_REG_CONFIG_VENDOR1: 2438 reg = XPCS_CFG_VENDOR_1_REG; 2439 break; 2440 case XPCS_REG_DIAG_VENDOR2: 2441 reg = XPCS_DIAG_VENDOR_2_REG; 2442 break; 2443 case XPCS_REG_MASK1: 2444 reg = XPCS_MASK_1_REG; 2445 break; 2446 case XPCS_REG_PACKET_COUNTER: 2447 reg = XPCS_PKT_CNTR_REG; 2448 break; 2449 case XPCS_REG_TX_STATEMACHINE: 2450 reg = XPCS_TX_STATE_MC_REG; 2451 break; 2452 case XPCS_REG_DESCWERR_COUNTER: 2453 reg = XPCS_DESKEW_ERR_CNTR_REG; 2454 break; 2455 case XPCS_REG_SYMBOL_ERR_L0_1_COUNTER: 2456 reg = XPCS_SYM_ERR_CNTR_L0_L1_REG; 2457 break; 2458 case XPCS_REG_SYMBOL_ERR_L2_3_COUNTER: 2459 reg = XPCS_SYM_ERR_CNTR_L2_L3_REG; 2460 break; 2461 case XPCS_REG_TRAINING_VECTOR: 2462 reg = XPCS_TRAINING_VECTOR_REG; 2463 break; 2464 default: 2465 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2466 " npi_xmac_xpcs_read" 2467 " Invalid Input: xpcs_reg <0x%x>", 2468 xpcs_reg)); 2469 return (NPI_FAILURE | NPI_MAC_REG_INVALID(portn)); 2470 } 2471 XPCS_REG_RD(handle, portn, reg, &val); 2472 *value = val & 0xFFFFFFFF; 2473 2474 return (NPI_SUCCESS); 2475 } 2476 2477 npi_status_t 2478 npi_xmac_xpcs_write(npi_handle_t handle, uint8_t portn, uint8_t xpcs_reg, 2479 uint32_t value) 2480 { 2481 uint32_t reg; 2482 uint64_t val; 2483 2484 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2485 2486 switch (xpcs_reg) { 2487 case XPCS_REG_CONTROL1: 2488 reg = XPCS_CTRL_1_REG; 2489 break; 2490 case XPCS_REG_TEST_CONTROL: 2491 reg = XPCS_TEST_CTRL_REG; 2492 break; 2493 case XPCS_REG_CONFIG_VENDOR1: 2494 reg = XPCS_CFG_VENDOR_1_REG; 2495 break; 2496 case XPCS_REG_DIAG_VENDOR2: 2497 reg = XPCS_DIAG_VENDOR_2_REG; 2498 break; 2499 case XPCS_REG_MASK1: 2500 reg = XPCS_MASK_1_REG; 2501 break; 2502 case XPCS_REG_PACKET_COUNTER: 2503 reg = XPCS_PKT_CNTR_REG; 2504 break; 2505 case XPCS_REG_DESCWERR_COUNTER: 2506 reg = XPCS_DESKEW_ERR_CNTR_REG; 2507 break; 2508 case XPCS_REG_TRAINING_VECTOR: 2509 reg = XPCS_TRAINING_VECTOR_REG; 2510 break; 2511 default: 2512 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2513 " npi_xmac_xpcs_write" 2514 " Invalid Input: xpcs_reg <0x%x>", 2515 xpcs_reg)); 2516 return (NPI_FAILURE | NPI_MAC_PCS_REG_INVALID(portn)); 2517 } 2518 val = value; 2519 2520 XPCS_REG_WR(handle, portn, reg, val); 2521 2522 return (NPI_SUCCESS); 2523 } 2524 2525 npi_status_t 2526 npi_bmac_reset(npi_handle_t handle, uint8_t portn, npi_mac_reset_t mode) 2527 { 2528 uint64_t val = 0; 2529 boolean_t txmac = B_FALSE; 2530 2531 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2532 2533 switch (mode) { 2534 case TX_MAC_RESET: 2535 BMAC_REG_WR(handle, portn, BTXMAC_SW_RST_REG, 0x1); 2536 BMAC_WAIT_REG(handle, portn, BTXMAC_SW_RST_REG, val); 2537 txmac = B_TRUE; 2538 break; 2539 case RX_MAC_RESET: 2540 BMAC_REG_WR(handle, portn, BRXMAC_SW_RST_REG, 0x1); 2541 BMAC_WAIT_REG(handle, portn, BRXMAC_SW_RST_REG, val); 2542 break; 2543 default: 2544 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2545 " npi_bmac_reset" 2546 " Invalid Input: mode <0x%x>", 2547 mode)); 2548 return (NPI_FAILURE | NPI_MAC_RESET_MODE_INVALID(portn)); 2549 } 2550 2551 if (val != 0) { 2552 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2553 " npi_bmac_reset" 2554 " BMAC_RESET HW Error: ret <0x%x>", 2555 val)); 2556 if (txmac) 2557 return (NPI_FAILURE | NPI_TXMAC_RESET_FAILED(portn)); 2558 else 2559 return (NPI_FAILURE | NPI_RXMAC_RESET_FAILED(portn)); 2560 } 2561 2562 return (NPI_SUCCESS); 2563 } 2564 2565 npi_status_t 2566 npi_mac_pcs_reset(npi_handle_t handle, uint8_t portn) 2567 { 2568 /* what to do here ? */ 2569 uint64_t val = 0; 2570 2571 ASSERT(IS_PORT_NUM_VALID(portn)); 2572 2573 PCS_REG_RD(handle, portn, PCS_MII_CTRL_REG, &val); 2574 val |= PCS_MII_RESET; 2575 PCS_REG_WR(handle, portn, PCS_MII_CTRL_REG, val); 2576 2577 return (NPI_SUCCESS); 2578 } 2579 2580 npi_status_t 2581 npi_mac_get_link_status(npi_handle_t handle, uint8_t portn, 2582 boolean_t *link_up) 2583 { 2584 uint64_t val; 2585 2586 ASSERT(IS_PORT_NUM_VALID(portn)); 2587 2588 PCS_REG_RD(handle, portn, PCS_MII_STATUS_REG, &val); 2589 2590 if (val & PCS_MII_STATUS_LINK_STATUS) { 2591 *link_up = B_TRUE; 2592 } else { 2593 *link_up = B_FALSE; 2594 } 2595 2596 return (NPI_SUCCESS); 2597 } 2598 2599 npi_status_t 2600 npi_bmac_tx_config(npi_handle_t handle, config_op_t op, uint8_t portn, 2601 bmac_tx_config_t config) 2602 { 2603 uint64_t val = 0; 2604 2605 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2606 2607 switch (op) { 2608 case ENABLE: 2609 case DISABLE: 2610 ASSERT((config != 0) && ((config & ~CFG_BMAC_TX_ALL) == 0)); 2611 if ((config == 0) || (config & ~CFG_BMAC_TX_ALL) != 0) { 2612 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2613 " npi_bmac_tx_config" 2614 " Invalid Input: config <0x%x>", 2615 config)); 2616 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2617 } 2618 if (op == ENABLE) { 2619 BMAC_REG_RD(handle, portn, TXMAC_CONFIG_REG, &val); 2620 if (config & CFG_BMAC_TX) 2621 val |= MAC_TX_CFG_TXMAC_ENABLE; 2622 if (config & CFG_BMAC_TX_CRC) 2623 val &= ~MAC_TX_CFG_NO_FCS; 2624 BMAC_REG_WR(handle, portn, TXMAC_CONFIG_REG, val); 2625 } else { 2626 BMAC_REG_RD(handle, portn, TXMAC_CONFIG_REG, &val); 2627 if (config & CFG_BMAC_TX) 2628 val &= ~MAC_TX_CFG_TXMAC_ENABLE; 2629 if (config & CFG_BMAC_TX_CRC) 2630 val |= MAC_TX_CFG_NO_FCS; 2631 BMAC_REG_WR(handle, portn, TXMAC_CONFIG_REG, val); 2632 } 2633 break; 2634 case INIT: 2635 ASSERT((config & ~CFG_BMAC_TX_ALL) == 0); 2636 if ((config & ~CFG_BMAC_TX_ALL) != 0) { 2637 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2638 " npi_bmac_tx_config" 2639 " Invalid Input: config <0x%x>", 2640 config)); 2641 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2642 } 2643 BMAC_REG_RD(handle, portn, TXMAC_CONFIG_REG, &val); 2644 if (config & CFG_BMAC_TX) 2645 val |= MAC_TX_CFG_TXMAC_ENABLE; 2646 else 2647 val &= ~MAC_TX_CFG_TXMAC_ENABLE; 2648 if (config & CFG_BMAC_TX_CRC) 2649 val &= ~MAC_TX_CFG_NO_FCS; 2650 else 2651 val |= MAC_TX_CFG_NO_FCS; 2652 BMAC_REG_WR(handle, portn, TXMAC_CONFIG_REG, val); 2653 break; 2654 default: 2655 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2656 " npi_bmac_tx_config" 2657 " Invalid Input: op <0x%x>", 2658 op)); 2659 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2660 } 2661 2662 return (NPI_SUCCESS); 2663 } 2664 2665 npi_status_t 2666 npi_bmac_rx_config(npi_handle_t handle, config_op_t op, uint8_t portn, 2667 bmac_rx_config_t config) 2668 { 2669 uint64_t val = 0; 2670 2671 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2672 2673 switch (op) { 2674 case ENABLE: 2675 case DISABLE: 2676 ASSERT((config != 0) && ((config & ~CFG_BMAC_RX_ALL) == 0)); 2677 if ((config == 0) || (config & ~CFG_BMAC_RX_ALL) != 0) { 2678 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2679 " npi_bmac_rx_config" 2680 " Invalid Input: config <0x%x>", 2681 config)); 2682 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2683 } 2684 if (op == ENABLE) { 2685 BMAC_REG_RD(handle, portn, RXMAC_CONFIG_REG, &val); 2686 if (config & CFG_BMAC_RX) 2687 val |= MAC_RX_CFG_RXMAC_ENABLE; 2688 if (config & CFG_BMAC_RX_STRIP_PAD) 2689 val |= MAC_RX_CFG_STRIP_PAD; 2690 if (config & CFG_BMAC_RX_STRIP_CRC) 2691 val |= MAC_RX_CFG_STRIP_FCS; 2692 if (config & CFG_BMAC_RX_PROMISCUOUS) 2693 val |= MAC_RX_CFG_PROMISC; 2694 if (config & CFG_BMAC_RX_PROMISCUOUSGROUP) 2695 val |= MAC_RX_CFG_PROMISC_GROUP; 2696 if (config & CFG_BMAC_RX_HASH_FILTER) 2697 val |= MAC_RX_CFG_HASH_FILTER_EN; 2698 if (config & CFG_BMAC_RX_ADDR_FILTER) 2699 val |= MAC_RX_CFG_ADDR_FILTER_EN; 2700 if (config & CFG_BMAC_RX_DISCARD_ON_ERR) 2701 val &= ~MAC_RX_CFG_DISABLE_DISCARD; 2702 BMAC_REG_WR(handle, portn, RXMAC_CONFIG_REG, val); 2703 } else { 2704 BMAC_REG_RD(handle, portn, RXMAC_CONFIG_REG, &val); 2705 if (config & CFG_BMAC_RX) 2706 val &= ~MAC_RX_CFG_RXMAC_ENABLE; 2707 if (config & CFG_BMAC_RX_STRIP_PAD) 2708 val &= ~MAC_RX_CFG_STRIP_PAD; 2709 if (config & CFG_BMAC_RX_STRIP_CRC) 2710 val &= ~MAC_RX_CFG_STRIP_FCS; 2711 if (config & CFG_BMAC_RX_PROMISCUOUS) 2712 val &= ~MAC_RX_CFG_PROMISC; 2713 if (config & CFG_BMAC_RX_PROMISCUOUSGROUP) 2714 val &= ~MAC_RX_CFG_PROMISC_GROUP; 2715 if (config & CFG_BMAC_RX_HASH_FILTER) 2716 val &= ~MAC_RX_CFG_HASH_FILTER_EN; 2717 if (config & CFG_BMAC_RX_ADDR_FILTER) 2718 val &= ~MAC_RX_CFG_ADDR_FILTER_EN; 2719 if (config & CFG_BMAC_RX_DISCARD_ON_ERR) 2720 val |= MAC_RX_CFG_DISABLE_DISCARD; 2721 BMAC_REG_WR(handle, portn, RXMAC_CONFIG_REG, val); 2722 } 2723 break; 2724 case INIT: 2725 ASSERT((config & ~CFG_BMAC_RX_ALL) == 0); 2726 if ((config & ~CFG_BMAC_RX_ALL) != 0) { 2727 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2728 " npi_bmac_rx_config" 2729 " Invalid Input: config <0x%x>", 2730 config)); 2731 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2732 } 2733 BMAC_REG_RD(handle, portn, RXMAC_CONFIG_REG, &val); 2734 if (config & CFG_BMAC_RX) 2735 val |= MAC_RX_CFG_RXMAC_ENABLE; 2736 else 2737 val &= ~MAC_RX_CFG_RXMAC_ENABLE; 2738 if (config & CFG_BMAC_RX_STRIP_PAD) 2739 val |= MAC_RX_CFG_STRIP_PAD; 2740 else 2741 val &= ~MAC_RX_CFG_STRIP_PAD; 2742 if (config & CFG_BMAC_RX_STRIP_CRC) 2743 val |= MAC_RX_CFG_STRIP_FCS; 2744 else 2745 val &= ~MAC_RX_CFG_STRIP_FCS; 2746 if (config & CFG_BMAC_RX_PROMISCUOUS) 2747 val |= MAC_RX_CFG_PROMISC; 2748 else 2749 val &= ~MAC_RX_CFG_PROMISC; 2750 if (config & CFG_BMAC_RX_PROMISCUOUSGROUP) 2751 val |= MAC_RX_CFG_PROMISC_GROUP; 2752 else 2753 val &= ~MAC_RX_CFG_PROMISC_GROUP; 2754 if (config & CFG_BMAC_RX_HASH_FILTER) 2755 val |= MAC_RX_CFG_HASH_FILTER_EN; 2756 else 2757 val &= ~MAC_RX_CFG_HASH_FILTER_EN; 2758 if (config & CFG_BMAC_RX_ADDR_FILTER) 2759 val |= MAC_RX_CFG_ADDR_FILTER_EN; 2760 else 2761 val &= ~MAC_RX_CFG_ADDR_FILTER_EN; 2762 if (config & CFG_BMAC_RX_DISCARD_ON_ERR) 2763 val &= ~MAC_RX_CFG_DISABLE_DISCARD; 2764 else 2765 val |= MAC_RX_CFG_DISABLE_DISCARD; 2766 2767 BMAC_REG_WR(handle, portn, RXMAC_CONFIG_REG, val); 2768 break; 2769 default: 2770 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2771 " npi_bmac_rx_config" 2772 " Invalid Input: op <0x%x>", op)); 2773 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2774 } 2775 2776 return (NPI_SUCCESS); 2777 } 2778 2779 npi_status_t 2780 npi_bmac_rx_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2781 bmac_rx_iconfig_t iconfig) 2782 { 2783 uint64_t val = 0; 2784 2785 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2786 2787 switch (op) { 2788 case ENABLE: 2789 case DISABLE: 2790 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_BMAC_RX_ALL) == 0)); 2791 if ((iconfig == 0) || (iconfig & ~ICFG_BMAC_RX_ALL) != 0) { 2792 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2793 " npi_bmac_rx_iconfig" 2794 " Invalid Input: iconfig <0x%x>", 2795 iconfig)); 2796 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2797 } 2798 BMAC_REG_RD(handle, portn, BRXMAC_STAT_MSK_REG, &val); 2799 if (op == ENABLE) 2800 val &= ~iconfig; 2801 else 2802 val |= iconfig; 2803 BMAC_REG_WR(handle, portn, BRXMAC_STAT_MSK_REG, val); 2804 2805 break; 2806 case INIT: 2807 ASSERT((iconfig & ~ICFG_BMAC_RX_ALL) == 0); 2808 if ((iconfig & ~ICFG_BMAC_RX_ALL) != 0) { 2809 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2810 " npi_bmac_rx_iconfig" 2811 " Invalid Input: iconfig <0x%x>", 2812 iconfig)); 2813 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2814 } 2815 BMAC_REG_WR(handle, portn, BRXMAC_STAT_MSK_REG, ~iconfig); 2816 2817 break; 2818 default: 2819 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2820 " npi_bmac_rx_iconfig" 2821 " Invalid Input: iconfig <0x%x>", 2822 iconfig)); 2823 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2824 } 2825 2826 return (NPI_SUCCESS); 2827 } 2828 2829 npi_status_t 2830 npi_bmac_xif_config(npi_handle_t handle, config_op_t op, uint8_t portn, 2831 bmac_xif_config_t config) 2832 { 2833 uint64_t val = 0; 2834 2835 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2836 2837 switch (op) { 2838 case ENABLE: 2839 case DISABLE: 2840 ASSERT((config != 0) && ((config & ~CFG_BMAC_XIF_ALL) == 0)); 2841 if ((config == 0) || (config & ~CFG_BMAC_XIF_ALL) != 0) { 2842 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2843 " npi_bmac_xif_config" 2844 " Invalid Input: config <0x%x>", 2845 config)); 2846 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2847 } 2848 if (op == ENABLE) { 2849 BMAC_REG_RD(handle, portn, MAC_XIF_CONFIG_REG, &val); 2850 if (config & CFG_BMAC_XIF_TX_OUTPUT) 2851 val |= MAC_XIF_TX_OUTPUT_EN; 2852 if (config & CFG_BMAC_XIF_LOOPBACK) 2853 val |= MAC_XIF_MII_INT_LOOPBACK; 2854 if (config & CFG_BMAC_XIF_GMII_MODE) 2855 val |= MAC_XIF_GMII_MODE; 2856 if (config & CFG_BMAC_XIF_LINKLED) 2857 val |= MAC_XIF_LINK_LED; 2858 if (config & CFG_BMAC_XIF_LED_POLARITY) 2859 val |= MAC_XIF_LED_POLARITY; 2860 if (config & CFG_BMAC_XIF_SEL_CLK_25MHZ) 2861 val |= MAC_XIF_SEL_CLK_25MHZ; 2862 BMAC_REG_WR(handle, portn, MAC_XIF_CONFIG_REG, val); 2863 } else { 2864 BMAC_REG_RD(handle, portn, MAC_XIF_CONFIG_REG, &val); 2865 if (config & CFG_BMAC_XIF_TX_OUTPUT) 2866 val &= ~MAC_XIF_TX_OUTPUT_EN; 2867 if (config & CFG_BMAC_XIF_LOOPBACK) 2868 val &= ~MAC_XIF_MII_INT_LOOPBACK; 2869 if (config & CFG_BMAC_XIF_GMII_MODE) 2870 val &= ~MAC_XIF_GMII_MODE; 2871 if (config & CFG_BMAC_XIF_LINKLED) 2872 val &= ~MAC_XIF_LINK_LED; 2873 if (config & CFG_BMAC_XIF_LED_POLARITY) 2874 val &= ~MAC_XIF_LED_POLARITY; 2875 if (config & CFG_BMAC_XIF_SEL_CLK_25MHZ) 2876 val &= ~MAC_XIF_SEL_CLK_25MHZ; 2877 BMAC_REG_WR(handle, portn, MAC_XIF_CONFIG_REG, val); 2878 } 2879 break; 2880 case INIT: 2881 ASSERT((config & ~CFG_BMAC_XIF_ALL) == 0); 2882 if ((config & ~CFG_BMAC_XIF_ALL) != 0) { 2883 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2884 " npi_bmac_xif_config" 2885 " Invalid Input: config <0x%x>", 2886 config)); 2887 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2888 } 2889 BMAC_REG_RD(handle, portn, MAC_XIF_CONFIG_REG, &val); 2890 if (config & CFG_BMAC_XIF_TX_OUTPUT) 2891 val |= MAC_XIF_TX_OUTPUT_EN; 2892 else 2893 val &= ~MAC_XIF_TX_OUTPUT_EN; 2894 if (config & CFG_BMAC_XIF_LOOPBACK) 2895 val |= MAC_XIF_MII_INT_LOOPBACK; 2896 else 2897 val &= ~MAC_XIF_MII_INT_LOOPBACK; 2898 if (config & CFG_BMAC_XIF_GMII_MODE) 2899 val |= MAC_XIF_GMII_MODE; 2900 else 2901 val &= ~MAC_XIF_GMII_MODE; 2902 if (config & CFG_BMAC_XIF_LINKLED) 2903 val |= MAC_XIF_LINK_LED; 2904 else 2905 val &= ~MAC_XIF_LINK_LED; 2906 if (config & CFG_BMAC_XIF_LED_POLARITY) 2907 val |= MAC_XIF_LED_POLARITY; 2908 else 2909 val &= ~MAC_XIF_LED_POLARITY; 2910 if (config & CFG_BMAC_XIF_SEL_CLK_25MHZ) 2911 val |= MAC_XIF_SEL_CLK_25MHZ; 2912 else 2913 val &= ~MAC_XIF_SEL_CLK_25MHZ; 2914 BMAC_REG_WR(handle, portn, MAC_XIF_CONFIG_REG, val); 2915 break; 2916 default: 2917 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2918 " npi_bmac_xif_config" 2919 " Invalid Input: op <0x%x>", 2920 op)); 2921 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2922 } 2923 2924 return (NPI_SUCCESS); 2925 } 2926 2927 npi_status_t 2928 npi_bmac_tx_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2929 bmac_tx_iconfig_t iconfig) 2930 { 2931 uint64_t val = 0; 2932 2933 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2934 2935 switch (op) { 2936 case ENABLE: 2937 case DISABLE: 2938 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_XMAC_TX_ALL) == 0)); 2939 if ((iconfig == 0) || (iconfig & ~ICFG_XMAC_TX_ALL) != 0) { 2940 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2941 " npi_bmac_tx_iconfig" 2942 " Invalid Input: iconfig <0x%x>", 2943 iconfig)); 2944 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2945 } 2946 BMAC_REG_RD(handle, portn, BTXMAC_STAT_MSK_REG, &val); 2947 if (op == ENABLE) 2948 val &= ~iconfig; 2949 else 2950 val |= iconfig; 2951 BMAC_REG_WR(handle, portn, BTXMAC_STAT_MSK_REG, val); 2952 2953 break; 2954 case INIT: 2955 ASSERT((iconfig & ~ICFG_XMAC_TX_ALL) == 0); 2956 if ((iconfig & ~ICFG_XMAC_TX_ALL) != 0) { 2957 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2958 " npi_bmac_tx_iconfig" 2959 " Invalid Input: iconfig <0x%x>", 2960 iconfig)); 2961 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2962 } 2963 BMAC_REG_WR(handle, portn, BTXMAC_STAT_MSK_REG, ~iconfig); 2964 2965 break; 2966 default: 2967 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2968 " npi_bmac_tx_iconfig" 2969 " Invalid Input: iconfig <0x%x>", 2970 iconfig)); 2971 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2972 } 2973 2974 return (NPI_SUCCESS); 2975 } 2976 2977 npi_status_t 2978 npi_bmac_ctl_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2979 bmac_ctl_iconfig_t iconfig) 2980 { 2981 uint64_t val = 0; 2982 2983 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2984 2985 switch (op) { 2986 case ENABLE: 2987 case DISABLE: 2988 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_BMAC_CTL_ALL) == 0)); 2989 if ((iconfig == 0) || (iconfig & ~ICFG_BMAC_CTL_ALL) != 0) { 2990 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2991 " npi_bmac_ctl_iconfig" 2992 " Invalid Input: iconfig <0x%x>", 2993 iconfig)); 2994 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2995 } 2996 BMAC_REG_RD(handle, portn, BMAC_C_S_MSK_REG, &val); 2997 if (op == ENABLE) 2998 val &= ~iconfig; 2999 else 3000 val |= iconfig; 3001 BMAC_REG_WR(handle, portn, BMAC_C_S_MSK_REG, val); 3002 3003 break; 3004 case INIT: 3005 ASSERT((iconfig & ~ICFG_BMAC_RX_ALL) == 0); 3006 if ((iconfig & ~ICFG_BMAC_RX_ALL) != 0) { 3007 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3008 " npi_bmac_ctl_iconfig" 3009 " Invalid Input: iconfig <0x%x>", 3010 iconfig)); 3011 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 3012 } 3013 BMAC_REG_WR(handle, portn, BMAC_C_S_MSK_REG, ~iconfig); 3014 3015 break; 3016 default: 3017 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3018 " npi_bmac_ctl_iconfig" 3019 " Invalid Input: iconfig <0x%x>", 3020 iconfig)); 3021 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 3022 } 3023 3024 return (NPI_SUCCESS); 3025 } 3026 3027 npi_status_t 3028 npi_bmac_tx_get_istatus(npi_handle_t handle, uint8_t portn, 3029 bmac_tx_iconfig_t *istatus) 3030 { 3031 uint64_t val = 0; 3032 3033 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 3034 3035 BMAC_REG_RD(handle, portn, BTXMAC_STATUS_REG, &val); 3036 *istatus = (uint32_t)val; 3037 3038 return (NPI_SUCCESS); 3039 } 3040 3041 npi_status_t 3042 npi_bmac_rx_get_istatus(npi_handle_t handle, uint8_t portn, 3043 bmac_rx_iconfig_t *istatus) 3044 { 3045 uint64_t val = 0; 3046 3047 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 3048 3049 BMAC_REG_RD(handle, portn, BRXMAC_STATUS_REG, &val); 3050 *istatus = (uint32_t)val; 3051 3052 return (NPI_SUCCESS); 3053 } 3054 3055 npi_status_t 3056 npi_bmac_ctl_get_istatus(npi_handle_t handle, uint8_t portn, 3057 bmac_ctl_iconfig_t *istatus) 3058 { 3059 uint64_t val = 0; 3060 3061 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 3062 3063 BMAC_REG_RD(handle, portn, BMAC_CTRL_STAT_REG, &val); 3064 *istatus = (uint32_t)val; 3065 3066 return (NPI_SUCCESS); 3067 } 3068 3069 npi_status_t 3070 npi_mac_mif_mdio_read(npi_handle_t handle, uint8_t portn, uint8_t device, 3071 uint16_t xcvr_reg, uint16_t *value) 3072 { 3073 mif_frame_t frame; 3074 uint_t delay; 3075 3076 frame.value = 0; 3077 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ 3078 frame.bits.w0.op = FRAME45_OP_ADDR; /* Select address */ 3079 frame.bits.w0.phyad = portn; /* Port number */ 3080 frame.bits.w0.regad = device; /* Device number */ 3081 frame.bits.w0.ta_msb = 1; 3082 frame.bits.w0.ta_lsb = 0; 3083 frame.bits.w0.data = xcvr_reg; /* register address */ 3084 3085 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3086 "mdio read port %d addr val=0x%x\n", portn, frame.value)); 3087 3088 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3089 3090 delay = 0; 3091 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); 3092 3093 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3094 "mdio read port %d addr poll=0x%x\n", portn, frame.value)); 3095 3096 if (delay == MIF_DELAY) { 3097 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3098 "mdio read no response1\n")); 3099 } 3100 3101 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ 3102 frame.bits.w0.op = FRAME45_OP_READ; /* Read */ 3103 frame.bits.w0.phyad = portn; /* Port Number */ 3104 frame.bits.w0.regad = device; /* Device Number */ 3105 frame.bits.w0.ta_msb = 1; 3106 frame.bits.w0.ta_lsb = 0; 3107 3108 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3109 "mdio read port %d data frame=0x%x\n", portn, frame.value)); 3110 3111 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3112 3113 delay = 0; 3114 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); 3115 3116 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3117 "mdio read port %d data poll=0x%x\n", portn, frame.value)); 3118 3119 *value = frame.bits.w0.data; 3120 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3121 "mdio read port=%d val=0x%x\n", portn, *value)); 3122 3123 if (delay == MIF_DELAY) { 3124 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3125 "mdio read no response2\n")); 3126 } 3127 3128 return (NPI_SUCCESS); 3129 } 3130 3131 npi_status_t 3132 npi_mac_mif_mii_read(npi_handle_t handle, uint8_t portn, uint8_t xcvr_reg, 3133 uint16_t *value) 3134 { 3135 mif_frame_t frame; 3136 uint_t delay; 3137 3138 frame.bits.w0.st = 0x1; /* Clause 22 */ 3139 frame.bits.w0.op = 0x2; 3140 frame.bits.w0.phyad = portn; 3141 frame.bits.w0.regad = xcvr_reg; 3142 frame.bits.w0.ta_msb = 1; 3143 frame.bits.w0.ta_lsb = 0; 3144 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3145 3146 delay = 0; 3147 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MAX_PIO_RETRIES); 3148 3149 if (delay == MAX_PIO_RETRIES) 3150 return (NPI_FAILURE | NPI_MAC_MII_READ_FAILED(portn)); 3151 3152 *value = frame.bits.w0.data; 3153 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3154 "mif mii read port %d reg=0x%x frame=0x%x\n", portn, 3155 xcvr_reg, frame.bits.w0.data)); 3156 3157 return (NPI_SUCCESS); 3158 } 3159 3160 npi_status_t 3161 npi_mac_mif_mdio_write(npi_handle_t handle, uint8_t portn, uint8_t device, 3162 uint16_t xcvr_reg, uint16_t value) 3163 { 3164 mif_frame_t frame; 3165 uint_t delay; 3166 3167 frame.value = 0; 3168 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ 3169 frame.bits.w0.op = FRAME45_OP_ADDR; /* Select Address */ 3170 frame.bits.w0.phyad = portn; /* Port Number */ 3171 frame.bits.w0.regad = device; /* Device Number */ 3172 frame.bits.w0.ta_msb = 1; 3173 frame.bits.w0.ta_lsb = 0; 3174 frame.bits.w0.data = xcvr_reg; /* register address */ 3175 3176 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3177 3178 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3179 "mdio write port %d addr val=0x%x\n", portn, frame.value)); 3180 3181 delay = 0; 3182 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); 3183 3184 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3185 "mdio write port %d addr poll=0x%x\n", portn, frame.value)); 3186 3187 if (delay == MIF_DELAY) { 3188 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3189 "mdio write no response1\n")); 3190 } 3191 3192 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ 3193 frame.bits.w0.op = FRAME45_OP_WRITE; /* Write */ 3194 frame.bits.w0.phyad = portn; /* Port number */ 3195 frame.bits.w0.regad = device; /* Device number */ 3196 frame.bits.w0.ta_msb = 1; 3197 frame.bits.w0.ta_lsb = 0; 3198 frame.bits.w0.data = value; 3199 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3200 3201 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3202 "mdio write port %d data val=0x%x\n", portn, frame.value)); 3203 3204 delay = 0; 3205 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); 3206 3207 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3208 "mdio write port %d data poll=0x%x\n", portn, frame.value)); 3209 3210 if (delay == MIF_DELAY) { 3211 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3212 "mdio write no response2\n")); 3213 } 3214 3215 return (NPI_SUCCESS); 3216 } 3217 3218 npi_status_t 3219 npi_mac_mif_mii_write(npi_handle_t handle, uint8_t portn, uint8_t xcvr_reg, 3220 uint16_t value) 3221 { 3222 mif_frame_t frame; 3223 uint_t delay; 3224 3225 frame.bits.w0.st = 0x1; /* Clause 22 */ 3226 frame.bits.w0.op = 0x1; 3227 frame.bits.w0.phyad = portn; 3228 frame.bits.w0.regad = xcvr_reg; 3229 frame.bits.w0.ta_msb = 1; 3230 frame.bits.w0.ta_lsb = 0; 3231 frame.bits.w0.data = value; 3232 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3233 3234 delay = 0; 3235 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MAX_PIO_RETRIES); 3236 3237 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3238 "mif mii write port %d reg=0x%x frame=0x%x\n", portn, 3239 xcvr_reg, frame.value)); 3240 3241 if (delay == MAX_PIO_RETRIES) 3242 return (NPI_FAILURE | NPI_MAC_MII_WRITE_FAILED(portn)); 3243 3244 return (NPI_SUCCESS); 3245 } 3246 3247 npi_status_t 3248 npi_mac_pcs_mii_read(npi_handle_t handle, uint8_t portn, uint8_t xcvr_reg, 3249 uint16_t *value) 3250 { 3251 pcs_anar_t pcs_anar; 3252 pcs_anar_t pcs_anlpar; 3253 pcs_stat_t pcs_stat; 3254 pcs_stat_mc_t pcs_stat_mc; 3255 mii_anar_t anar; 3256 mii_anar_t anlpar; 3257 mii_aner_t aner; 3258 mii_esr_t esr; 3259 mii_gsr_t gsr; 3260 uint64_t val = 0; 3261 3262 ASSERT(IS_PORT_NUM_VALID(portn)); 3263 3264 switch (xcvr_reg) { 3265 case MII_CONTROL: 3266 PCS_REG_RD(handle, portn, PCS_MII_CTRL_REG, &val); 3267 *value = (uint16_t)val; 3268 break; 3269 case MII_STATUS: 3270 PCS_REG_RD(handle, portn, PCS_MII_STATUS_REG, &val); 3271 pcs_stat.value = val; 3272 PCS_REG_RD(handle, portn, PCS_STATE_MACHINE_REG, &val); 3273 pcs_stat_mc.value = val; 3274 if ((pcs_stat_mc.bits.w0.link_cfg_stat == 0xB) && 3275 (pcs_stat_mc.bits.w0.word_sync != 0)) { 3276 pcs_stat.bits.w0.link_stat = 1; 3277 } else if (pcs_stat_mc.bits.w0.link_cfg_stat != 0xB) { 3278 pcs_stat.bits.w0.link_stat = 0; 3279 } 3280 *value = (uint16_t)pcs_stat.value; 3281 break; 3282 case NXGE_MII_ESR: 3283 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3284 pcs_anar.value = (uint16_t)val; 3285 esr.value = 0; 3286 esr.bits.link_1000fdx = pcs_anar.bits.w0.full_duplex; 3287 esr.bits.link_1000hdx = pcs_anar.bits.w0.half_duplex; 3288 *value = esr.value; 3289 break; 3290 case MII_AN_ADVERT: 3291 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3292 pcs_anar.value = (uint16_t)val; 3293 anar.value = 0; 3294 anar.bits.cap_pause = pcs_anar.bits.w0.pause; 3295 anar.bits.cap_asmpause = pcs_anar.bits.w0.asm_pause; 3296 *value = anar.value; 3297 break; 3298 case MII_AN_LPABLE: 3299 PCS_REG_RD(handle, portn, PCS_MII_LPA_REG, &val); 3300 pcs_anlpar.value = (uint16_t)val; 3301 anlpar.bits.cap_pause = pcs_anlpar.bits.w0.pause; 3302 anlpar.bits.cap_asmpause = pcs_anlpar.bits.w0.asm_pause; 3303 *value = anlpar.value; 3304 break; 3305 case MII_AN_EXPANSION: 3306 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3307 pcs_anar.value = (uint16_t)val; 3308 aner.value = 0; 3309 aner.bits.lp_an_able = pcs_anar.bits.w0.full_duplex | 3310 pcs_anar.bits.w0.half_duplex; 3311 *value = aner.value; 3312 break; 3313 case NXGE_MII_GSR: 3314 PCS_REG_RD(handle, portn, PCS_MII_LPA_REG, &val); 3315 pcs_anar.value = (uint16_t)val; 3316 gsr.value = 0; 3317 gsr.bits.link_1000fdx = pcs_anar.bits.w0.full_duplex; 3318 gsr.bits.link_1000hdx = pcs_anar.bits.w0.half_duplex; 3319 *value = gsr.value; 3320 break; 3321 default: 3322 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3323 " npi_mac_pcs_mii_read" 3324 " Invalid Input: xcvr_reg <0x%x>", 3325 xcvr_reg)); 3326 return (NPI_FAILURE | NPI_MAC_REG_INVALID(portn)); 3327 } 3328 3329 return (NPI_SUCCESS); 3330 } 3331 3332 npi_status_t 3333 npi_mac_pcs_mii_write(npi_handle_t handle, uint8_t portn, uint8_t xcvr_reg, 3334 uint16_t value) 3335 { 3336 pcs_anar_t pcs_anar; 3337 mii_anar_t anar; 3338 mii_gcr_t gcr; 3339 uint64_t val; 3340 3341 ASSERT(IS_PORT_NUM_VALID(portn)); 3342 3343 switch (xcvr_reg) { 3344 case MII_CONTROL: 3345 val = (uint16_t)value; 3346 PCS_REG_WR(handle, portn, PCS_MII_CTRL_REG, val); 3347 break; 3348 case MII_AN_ADVERT: 3349 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3350 pcs_anar.value = (uint16_t)val; 3351 anar.value = value; 3352 pcs_anar.bits.w0.asm_pause = anar.bits.cap_asmpause; 3353 pcs_anar.bits.w0.pause = anar.bits.cap_pause; 3354 val = pcs_anar.value; 3355 PCS_REG_WR(handle, portn, PCS_MII_ADVERT_REG, val); 3356 break; 3357 case NXGE_MII_GCR: 3358 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3359 pcs_anar.value = (uint16_t)val; 3360 gcr.value = value; 3361 pcs_anar.bits.w0.full_duplex = gcr.bits.link_1000fdx; 3362 pcs_anar.bits.w0.half_duplex = gcr.bits.link_1000hdx; 3363 val = pcs_anar.value; 3364 PCS_REG_WR(handle, portn, PCS_MII_ADVERT_REG, val); 3365 break; 3366 default: 3367 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3368 " npi_mac_pcs_mii_write" 3369 " Invalid Input: xcvr_reg <0x%x>", 3370 xcvr_reg)); 3371 return (NPI_FAILURE | NPI_MAC_REG_INVALID(portn)); 3372 } 3373 3374 return (NPI_SUCCESS); 3375 } 3376 3377 npi_status_t 3378 npi_mac_mif_link_intr_enable(npi_handle_t handle, uint8_t portn, 3379 uint8_t xcvr_reg, uint16_t mask) 3380 { 3381 mif_cfg_t mif_cfg; 3382 3383 ASSERT(IS_PORT_NUM_VALID(portn)); 3384 3385 ASSERT(xcvr_reg <= NXGE_MAX_MII_REGS); 3386 if (xcvr_reg > NXGE_MAX_MII_REGS) { 3387 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3388 " npi_mac_mif_link_intr_enable" 3389 " Invalid Input: xcvr_reg <0x%x>", 3390 xcvr_reg)); 3391 return (NPI_FAILURE | NPI_MAC_REG_INVALID(portn)); 3392 } 3393 3394 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.value); 3395 3396 mif_cfg.bits.w0.phy_addr = portn; /* Port number */ 3397 mif_cfg.bits.w0.reg_addr = xcvr_reg; /* Register address */ 3398 mif_cfg.bits.w0.indirect_md = 0; /* Clause 22 */ 3399 mif_cfg.bits.w0.poll_en = 1; 3400 3401 MIF_REG_WR(handle, MIF_MASK_REG, ~mask); 3402 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.value); 3403 3404 NXGE_DELAY(20); 3405 3406 return (NPI_SUCCESS); 3407 } 3408 3409 npi_status_t 3410 npi_mac_mif_mdio_link_intr_enable(npi_handle_t handle, uint8_t portn, 3411 uint8_t device, uint16_t xcvr_reg, uint16_t mask) 3412 { 3413 mif_cfg_t mif_cfg; 3414 mif_frame_t frame; 3415 uint_t delay; 3416 3417 ASSERT(IS_PORT_NUM_VALID(portn)); 3418 3419 frame.bits.w0.st = 0; /* Clause 45 */ 3420 frame.bits.w0.op = 0; /* Select address */ 3421 frame.bits.w0.phyad = portn; /* Port number */ 3422 frame.bits.w0.regad = device; /* Device number */ 3423 frame.bits.w0.ta_msb = 1; 3424 frame.bits.w0.ta_lsb = 0; 3425 frame.bits.w0.data = xcvr_reg; /* register address */ 3426 3427 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3428 3429 delay = 0; 3430 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MAX_PIO_RETRIES); 3431 if (delay == MAX_PIO_RETRIES) 3432 return (NPI_FAILURE); 3433 3434 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.value); 3435 3436 mif_cfg.bits.w0.phy_addr = portn; /* Port number */ 3437 mif_cfg.bits.w0.reg_addr = device; /* Register address */ 3438 mif_cfg.bits.w0.indirect_md = 1; /* Clause 45 */ 3439 mif_cfg.bits.w0.poll_en = 1; 3440 3441 MIF_REG_WR(handle, MIF_MASK_REG, ~mask); 3442 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.value); 3443 3444 NXGE_DELAY(20); 3445 3446 return (NPI_SUCCESS); 3447 } 3448 3449 void 3450 npi_mac_mif_set_indirect_mode(npi_handle_t handle, boolean_t on_off) 3451 { 3452 mif_cfg_t mif_cfg; 3453 3454 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.value); 3455 mif_cfg.bits.w0.indirect_md = on_off; 3456 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.value); 3457 } 3458 3459 void 3460 npi_mac_mif_set_atca_mode(npi_handle_t handle, boolean_t on_off) 3461 { 3462 mif_cfg_t mif_cfg; 3463 3464 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.value); 3465 mif_cfg.bits.w0.atca_ge = on_off; 3466 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.value); 3467 } 3468 3469 npi_status_t 3470 npi_bmac_send_pause(npi_handle_t handle, uint8_t portn, uint16_t pause_time) 3471 { 3472 uint64_t val; 3473 3474 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 3475 3476 val = MAC_SEND_PAUSE_SEND | pause_time; 3477 BMAC_REG_WR(handle, portn, MAC_SEND_PAUSE_REG, val); 3478 3479 return (NPI_SUCCESS); 3480 } 3481 3482 npi_status_t 3483 npi_xmac_xif_led(npi_handle_t handle, uint8_t portn, boolean_t on_off) 3484 { 3485 uint64_t val = 0; 3486 3487 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 3488 3489 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 3490 3491 if (on_off) { 3492 val |= XMAC_XIF_LED_POLARITY; 3493 val &= ~XMAC_XIF_FORCE_LED_ON; 3494 } else { 3495 val &= ~XMAC_XIF_LED_POLARITY; 3496 val |= XMAC_XIF_FORCE_LED_ON; 3497 } 3498 3499 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 3500 3501 return (NPI_SUCCESS); 3502 } 3503 3504 npi_status_t 3505 npi_xmac_zap_tx_counters(npi_handle_t handle, uint8_t portn) 3506 { 3507 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 3508 3509 XMAC_REG_WR(handle, portn, XTXMAC_FRM_CNT_REG, 0); 3510 XMAC_REG_WR(handle, portn, XTXMAC_BYTE_CNT_REG, 0); 3511 3512 return (NPI_SUCCESS); 3513 } 3514 3515 npi_status_t 3516 npi_xmac_zap_rx_counters(npi_handle_t handle, uint8_t portn) 3517 { 3518 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 3519 3520 XMAC_REG_WR(handle, portn, XRXMAC_BT_CNT_REG, 0); 3521 XMAC_REG_WR(handle, portn, XRXMAC_BC_FRM_CNT_REG, 0); 3522 XMAC_REG_WR(handle, portn, XRXMAC_MC_FRM_CNT_REG, 0); 3523 XMAC_REG_WR(handle, portn, XRXMAC_FRAG_CNT_REG, 0); 3524 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT1_REG, 0); 3525 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT2_REG, 0); 3526 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT3_REG, 0); 3527 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT4_REG, 0); 3528 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT5_REG, 0); 3529 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT6_REG, 0); 3530 XMAC_REG_WR(handle, portn, XRXMAC_MPSZER_CNT_REG, 0); 3531 XMAC_REG_WR(handle, portn, XRXMAC_CRC_ER_CNT_REG, 0); 3532 XMAC_REG_WR(handle, portn, XRXMAC_CD_VIO_CNT_REG, 0); 3533 XMAC_REG_WR(handle, portn, XRXMAC_AL_ER_CNT_REG, 0); 3534 XMAC_REG_WR(handle, portn, XMAC_LINK_FLT_CNT_REG, 0); 3535 3536 return (NPI_SUCCESS); 3537 } 3538