144961713Sgirish /*
244961713Sgirish  * CDDL HEADER START
344961713Sgirish  *
444961713Sgirish  * The contents of this file are subject to the terms of the
544961713Sgirish  * Common Development and Distribution License (the "License").
644961713Sgirish  * You may not use this file except in compliance with the License.
744961713Sgirish  *
844961713Sgirish  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
944961713Sgirish  * or http://www.opensolaris.org/os/licensing.
1044961713Sgirish  * See the License for the specific language governing permissions
1144961713Sgirish  * and limitations under the License.
1244961713Sgirish  *
1344961713Sgirish  * When distributing Covered Code, include this CDDL HEADER in each
1444961713Sgirish  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1544961713Sgirish  * If applicable, add the following below this CDDL HEADER, with the
1644961713Sgirish  * fields enclosed by brackets "[]" replaced with your own identifying
1744961713Sgirish  * information: Portions Copyright [yyyy] [name of copyright owner]
1844961713Sgirish  *
1944961713Sgirish  * CDDL HEADER END
2044961713Sgirish  */
2144961713Sgirish /*
2256d930aeSspeer  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
2344961713Sgirish  * Use is subject to license terms.
2444961713Sgirish  */
2544961713Sgirish 
2644961713Sgirish #ifndef _NPI_ESPC_H
2744961713Sgirish #define	_NPI_ESPC_H
2844961713Sgirish 
2944961713Sgirish #pragma ident	"%Z%%M%	%I%	%E% SMI"
3044961713Sgirish 
3144961713Sgirish #ifdef	__cplusplus
3244961713Sgirish extern "C" {
3344961713Sgirish #endif
3444961713Sgirish 
3544961713Sgirish #include <npi.h>
3644961713Sgirish #include <nxge_espc_hw.h>
3744961713Sgirish 
3844961713Sgirish #define	EPC_WAIT_RW_COMP(handle, val_p, comp_bit) {\
3944961713Sgirish 	uint32_t cnt = MAX_PIO_RETRIES;\
4044961713Sgirish 	do {\
4144961713Sgirish 		NXGE_DELAY(EPC_RW_WAIT);\
4244961713Sgirish 		NXGE_REG_RD64(handle, ESPC_REG_ADDR(ESPC_PIO_STATUS_REG),\
4344961713Sgirish 				val_p); cnt--;\
4444961713Sgirish 	} while (((val & comp_bit) == 0) && (cnt > 0));\
4544961713Sgirish }
4644961713Sgirish 
4744961713Sgirish /* ESPC specific errors */
4844961713Sgirish 
4944961713Sgirish #define	ESPC_EEPROM_ADDR_INVALID	0x51
5044961713Sgirish #define	ESPC_STR_LEN_INVALID		0x91
5144961713Sgirish 
5244961713Sgirish /* ESPC error return macros */
5344961713Sgirish 
5444961713Sgirish #define	NPI_ESPC_EEPROM_ADDR_INVALID	((ESPC_BLK_ID << 8) |\
5544961713Sgirish 					ESPC_EEPROM_ADDR_INVALID)
5644961713Sgirish #define	NPI_ESPC_EEPROM_WRITE_FAILED	((ESPC_BLK_ID << 8) | WRITE_FAILED)
5744961713Sgirish #define	NPI_ESPC_EEPROM_READ_FAILED	((ESPC_BLK_ID << 8) | READ_FAILED)
5844961713Sgirish #define	NPI_ESPC_OPCODE_INVALID		((ESPC_BLK_ID << 8) | OPCODE_INVALID)
5944961713Sgirish #define	NPI_ESPC_STR_LEN_INVALID	((ESPC_BLK_ID << 8) |\
6044961713Sgirish 					ESPC_STR_LEN_INVALID)
6144961713Sgirish #define	NPI_ESPC_PORT_INVALID		((ESPC_BLK_ID << 8) | PORT_INVALID)
6244961713Sgirish 
6356d930aeSspeer /* EEPROM size, Fcode and VPD definitions */
6456d930aeSspeer 
6556d930aeSspeer /*
6656d930aeSspeer  * VPD information.
6756d930aeSspeer  */
6856d930aeSspeer #define	NXGE_VPD_MOD_LEN	32
6956d930aeSspeer #define	NXGE_VPD_BD_MOD_LEN	16
7056d930aeSspeer #define	NXGE_VPD_PHY_LEN	5
7156d930aeSspeer #define	NXGE_VPD_VER_LEN	60
7256d930aeSspeer typedef struct _npi_vpd_info_t {
7356d930aeSspeer 	uint8_t		mac_addr[ETHERADDRL];
7456d930aeSspeer 	uint8_t		num_macs;
7556d930aeSspeer 	char		model[NXGE_VPD_MOD_LEN];
7656d930aeSspeer 	char		bd_model[NXGE_VPD_BD_MOD_LEN];
7756d930aeSspeer 	char		phy_type[NXGE_VPD_PHY_LEN];
7856d930aeSspeer 	char		ver[NXGE_VPD_VER_LEN];
7956d930aeSspeer 	boolean_t	ver_valid;
80*2e59129aSraghus 	boolean_t	present;
8156d930aeSspeer } npi_vpd_info_t, *p_npi_vpd_info_t;
8256d930aeSspeer 
8356d930aeSspeer #define	NXGE_FCODE_ID_STR	"FCode "
8456d930aeSspeer #define	NXGE_FCODE_VER_STR_LEN	5
8556d930aeSspeer #define	NXGE_VPD_VALID_VER_W	3
8656d930aeSspeer #define	NXGE_VPD_VALID_VER_F	4
8756d930aeSspeer #define	EXPANSION_ROM_SIZE	65536
8856d930aeSspeer #define	FD_MODEL		0x01
8956d930aeSspeer #define	FD_BD_MODEL		0x02
9056d930aeSspeer #define	FD_MAC_ADDR		0x04
9156d930aeSspeer #define	FD_NUM_MACS		0x08
9256d930aeSspeer #define	FD_PHY_TYPE		0x10
9356d930aeSspeer #define	FD_FW_VERSION		0x20
9456d930aeSspeer #define	FD_ALL			0x3f
9556d930aeSspeer 
9644961713Sgirish npi_status_t npi_espc_pio_enable(npi_handle_t);
9744961713Sgirish npi_status_t npi_espc_pio_disable(npi_handle_t);
9844961713Sgirish npi_status_t npi_espc_eeprom_entry(npi_handle_t, io_op_t,
9944961713Sgirish 				uint32_t, uint8_t *);
10044961713Sgirish npi_status_t npi_espc_mac_addr_get(npi_handle_t, uint8_t *);
10144961713Sgirish npi_status_t npi_espc_num_ports_get(npi_handle_t, uint8_t *);
10244961713Sgirish 	npi_status_t npi_espc_num_macs_get(npi_handle_t, uint8_t *);
10344961713Sgirish npi_status_t npi_espc_model_str_get(npi_handle_t, char *);
10444961713Sgirish npi_status_t npi_espc_bd_model_str_get(npi_handle_t, char *);
10544961713Sgirish npi_status_t npi_espc_phy_type_get(npi_handle_t, uint8_t *);
10644961713Sgirish npi_status_t npi_espc_port_phy_type_get(npi_handle_t, uint8_t *,
10744961713Sgirish 				uint8_t);
10844961713Sgirish npi_status_t npi_espc_max_frame_get(npi_handle_t, uint16_t *);
10944961713Sgirish npi_status_t npi_espc_version_get(npi_handle_t, uint16_t *);
11044961713Sgirish 	npi_status_t npi_espc_img_sz_get(npi_handle_t, uint16_t *);
11144961713Sgirish npi_status_t npi_espc_chksum_get(npi_handle_t, uint8_t *);
11244961713Sgirish npi_status_t npi_espc_intr_num_get(npi_handle_t, uint8_t *);
11344961713Sgirish uint32_t npi_espc_reg_get(npi_handle_t, int);
11444961713Sgirish void npi_espc_dump(npi_handle_t);
11556d930aeSspeer npi_status_t npi_espc_vpd_info_get(npi_handle_t, p_npi_vpd_info_t, uint32_t);
11644961713Sgirish 
11744961713Sgirish #ifdef	__cplusplus
11844961713Sgirish }
11944961713Sgirish #endif
12044961713Sgirish 
12144961713Sgirish #endif	/* _NPI_ESPC_H */
122