xref: /illumos-gate/usr/src/uts/common/io/nxge/npi/npi.h (revision 678453a8)
144961713Sgirish /*
244961713Sgirish  * CDDL HEADER START
344961713Sgirish  *
444961713Sgirish  * The contents of this file are subject to the terms of the
544961713Sgirish  * Common Development and Distribution License (the "License").
644961713Sgirish  * You may not use this file except in compliance with the License.
744961713Sgirish  *
844961713Sgirish  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
944961713Sgirish  * or http://www.opensolaris.org/os/licensing.
1044961713Sgirish  * See the License for the specific language governing permissions
1144961713Sgirish  * and limitations under the License.
1244961713Sgirish  *
1344961713Sgirish  * When distributing Covered Code, include this CDDL HEADER in each
1444961713Sgirish  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1544961713Sgirish  * If applicable, add the following below this CDDL HEADER, with the
1644961713Sgirish  * fields enclosed by brackets "[]" replaced with your own identifying
1744961713Sgirish  * information: Portions Copyright [yyyy] [name of copyright owner]
1844961713Sgirish  *
1944961713Sgirish  * CDDL HEADER END
2044961713Sgirish  */
2144961713Sgirish /*
22*678453a8Sspeer  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
2344961713Sgirish  * Use is subject to license terms.
2444961713Sgirish  */
2544961713Sgirish 
2644961713Sgirish #ifndef _NPI_H
2744961713Sgirish #define	_NPI_H
2844961713Sgirish 
2944961713Sgirish #pragma ident	"%Z%%M%	%I%	%E% SMI"
3044961713Sgirish 
3144961713Sgirish #ifdef	__cplusplus
3244961713Sgirish extern "C" {
3344961713Sgirish #endif
3444961713Sgirish 
3544961713Sgirish #include <nxge_common_impl.h>
3644961713Sgirish 
3744961713Sgirish typedef	uint32_t			npi_status_t;
3844961713Sgirish 
3944961713Sgirish /* Common Block ID */
4044961713Sgirish 
4144961713Sgirish #define	MAC_BLK_ID			0x1
4244961713Sgirish #define	TXMAC_BLK_ID			0x2
4344961713Sgirish #define	RXMAC_BLK_ID			0x3
4444961713Sgirish #define	MIF_BLK_ID			0x4
4544961713Sgirish #define	IPP_BLK_ID			0x5
4644961713Sgirish #define	TXC_BLK_ID			0x6
4744961713Sgirish #define	TXDMA_BLK_ID			0x7
4844961713Sgirish #define	RXDMA_BLK_ID			0x8
4944961713Sgirish #define	ZCP_BLK_ID			0x9
5044961713Sgirish #define	ESPC_BLK_ID			0xa
5144961713Sgirish #define	FFLP_BLK_ID			0xb
5244961713Sgirish #define	PHY_BLK_ID			0xc
5344961713Sgirish #define	ETHER_SERDES_BLK_ID		0xd
5444961713Sgirish #define	PCIE_SERDES_BLK_ID		0xe
5544961713Sgirish #define	VIR_BLK_ID			0xf
56ee5416c9Syc #define	XAUI_BLK_ID			0x10
57ee5416c9Syc #define	XFP_BLK_ID			0x11
5844961713Sgirish 
5944961713Sgirish /* Common HW error code */
6044961713Sgirish /* HW unable to exit from reset state. */
6144961713Sgirish #define	RESET_FAILED			0x81
6244961713Sgirish 
6344961713Sgirish /* Write operation failed on indirect write. */
6444961713Sgirish #define	WRITE_FAILED			0x82
6544961713Sgirish /* Read operation failed on indirect read.	 */
6644961713Sgirish #define	READ_FAILED			0x83
6744961713Sgirish 
6844961713Sgirish /* Error code boundary */
6944961713Sgirish 
7044961713Sgirish #define	COMMON_SW_ERR_START		0x40
7144961713Sgirish #define	COMMON_SW_ERR_END		0x4f
7244961713Sgirish #define	BLK_SPEC_SW_ERR_START		0x50
7344961713Sgirish #define	BLK_SPEC_SW_ERR_END		0x7f
7444961713Sgirish #define	COMMON_HW_ERR_START		0x80
7544961713Sgirish #define	COMMON_HW_ERR_END		0x8f
7644961713Sgirish #define	BLK_SPEC_HW_ERR_START		0x90
7744961713Sgirish #define	BLK_SPEC_HW_ERR_END		0xbf
7844961713Sgirish 
7944961713Sgirish #define	IS_PORT				0x00100000
8044961713Sgirish #define	IS_CHAN				0x00200000
8144961713Sgirish 
8244961713Sgirish /* Common SW errors code */
8344961713Sgirish 
8444961713Sgirish #define	PORT_INVALID			0x41	/* Invalid port number */
8544961713Sgirish #define	CHANNEL_INVALID			0x42	/* Invalid dma channel number */
8644961713Sgirish #define	OPCODE_INVALID			0x43	/* Invalid opcode */
8744961713Sgirish #define	REGISTER_INVALID		0x44	/* Invalid register number */
8844961713Sgirish #define	COUNTER_INVALID			0x45	/* Invalid counter number */
8944961713Sgirish #define	CONFIG_INVALID			0x46	/* Invalid config input */
9044961713Sgirish #define	LOGICAL_PAGE_INVALID		0x47	/* Invalid logical page # */
9144961713Sgirish #define	VLAN_INVALID			0x48	/* Invalid Vlan ID */
9244961713Sgirish #define	RDC_TAB_INVALID			0x49	/* Invalid RDC Group Number */
9344961713Sgirish #define	LOCATION_INVALID		0x4a	/* Invalid Entry Location */
9444961713Sgirish 
9544961713Sgirish #define	NPI_SUCCESS			0		/* Operation succeed */
9644961713Sgirish #define	NPI_FAILURE			0x80000000	/* Operation failed */
9744961713Sgirish 
9844961713Sgirish #define	NPI_CNT_CLR_VAL			0
9944961713Sgirish 
10044961713Sgirish /*
10144961713Sgirish  * Block identifier starts at bit 8.
10244961713Sgirish  */
10344961713Sgirish #define	NPI_BLOCK_ID_SHIFT		8
10444961713Sgirish 
10544961713Sgirish /*
10644961713Sgirish  * Port, channel and misc. information starts at bit 12.
10744961713Sgirish  */
10844961713Sgirish #define	NPI_PORT_CHAN_SHIFT			12
10944961713Sgirish 
11044961713Sgirish /*
11144961713Sgirish  * Software Block specific error codes start at 0x50.
11244961713Sgirish  */
11344961713Sgirish #define	NPI_BK_ERROR_START		0x50
11444961713Sgirish 
11544961713Sgirish /*
11644961713Sgirish  * Hardware block specific error codes start at 0x90.
11744961713Sgirish  */
11844961713Sgirish #define	NPI_BK_HW_ER_START		0x90
11944961713Sgirish 
12044961713Sgirish /* Structures for register tracing */
12144961713Sgirish 
12244961713Sgirish typedef struct _rt_buf {
12344961713Sgirish 	uint32_t	ctl_addr;
124*678453a8Sspeer 	uint32_t	align;
12544961713Sgirish 	uint32_t	val_h32;
126*678453a8Sspeer 	uint32_t	val_l32;
127*678453a8Sspeer 	char		name[16];
12844961713Sgirish } rt_buf_t;
12944961713Sgirish 
13044961713Sgirish /*
13144961713Sgirish  * Control Address field format
13244961713Sgirish  *
13344961713Sgirish  * Bit 0 - 23: Address
13444961713Sgirish  * Bit 24 - 25: Function Number
13544961713Sgirish  * Bit 26 - 29: Instance Number
13644961713Sgirish  * Bit 30: Read/Write Direction bit
13744961713Sgirish  * Bit 31: Invalid bit
13844961713Sgirish  */
13944961713Sgirish 
14044961713Sgirish #define	MAX_RTRACE_ENTRIES	1024
14144961713Sgirish #define	MAX_RTRACE_IOC_ENTRIES	64
14244961713Sgirish #define	TRACE_ADDR_MASK		0x00FFFFFF
14344961713Sgirish #define	TRACE_FUNC_MASK		0x03000000
14444961713Sgirish #define	TRACE_INST_MASK		0x3C000000
14544961713Sgirish #define	TRACE_CTL_WR		0x40000000
14644961713Sgirish #define	TRACE_CTL_INVALID	0x80000000
14744961713Sgirish #define	TRACE_FUNC_SHIFT	24
14844961713Sgirish #define	TRACE_INST_SHIFT	26
14944961713Sgirish #define	MSG_BUF_SIZE		1024
15044961713Sgirish 
15144961713Sgirish 
15244961713Sgirish typedef struct _rtrace {
15344961713Sgirish 	uint16_t	next_idx;
15444961713Sgirish 	uint16_t	last_idx;
15544961713Sgirish 	boolean_t	wrapped;
156*678453a8Sspeer 	uint64_t	align;
15744961713Sgirish 	rt_buf_t	buf[MAX_RTRACE_ENTRIES];
15844961713Sgirish } rtrace_t;
15944961713Sgirish 
16044961713Sgirish typedef struct _err_inject {
16144961713Sgirish 	uint8_t		blk_id;
16244961713Sgirish 	uint8_t		chan;
16344961713Sgirish 	uint32_t	err_id;
16444961713Sgirish 	uint32_t	control;
16544961713Sgirish } err_inject_t;
16644961713Sgirish 
16744961713Sgirish /* Configuration options */
16844961713Sgirish typedef enum config_op {
16944961713Sgirish 	DISABLE = 0,
17044961713Sgirish 	ENABLE,
17144961713Sgirish 	INIT
17244961713Sgirish } config_op_t;
17344961713Sgirish 
17444961713Sgirish /* I/O options */
17544961713Sgirish typedef enum io_op {
17644961713Sgirish 	OP_SET = 0,
17744961713Sgirish 	OP_GET,
17844961713Sgirish 	OP_UPDATE,
17944961713Sgirish 	OP_CLEAR
18044961713Sgirish } io_op_t;
18144961713Sgirish 
18244961713Sgirish /* Counter options */
18344961713Sgirish typedef enum counter_op {
18444961713Sgirish 	SNAP_STICKY = 0,
18544961713Sgirish 	SNAP_ACCUMULATE,
18644961713Sgirish 	CLEAR
18744961713Sgirish } counter_op_t;
18844961713Sgirish 
18944961713Sgirish /* NPI attribute */
19044961713Sgirish typedef struct _npi_attr_t {
19144961713Sgirish 	uint32_t type;
19244961713Sgirish 	uint32_t idata[16];
19344961713Sgirish 	uint32_t odata[16];
19444961713Sgirish } npi_attr_t;
19544961713Sgirish 
19644961713Sgirish /* NPI Handle */
19744961713Sgirish typedef	struct	_npi_handle_function {
19844961713Sgirish 	uint16_t		instance;
19944961713Sgirish 	uint16_t		function;
20044961713Sgirish } npi_handle_function_t;
20144961713Sgirish 
20244961713Sgirish /* NPI Handle */
20344961713Sgirish typedef	struct	_npi_handle {
20444961713Sgirish 	npi_reg_handle_t	regh;
20544961713Sgirish 	npi_reg_ptr_t		regp;
20644961713Sgirish 	boolean_t		is_vraddr; /* virtualization region address */
20744961713Sgirish 	npi_handle_function_t	function;
20844961713Sgirish 	void * nxgep;
20944961713Sgirish } npi_handle_t;
21044961713Sgirish 
21144961713Sgirish /* NPI Counter */
21244961713Sgirish typedef struct _npi_counter_t {
21344961713Sgirish 	uint32_t id;
21444961713Sgirish 	char *name;
21544961713Sgirish 	uint32_t val;
21644961713Sgirish } npi_counter_t;
21744961713Sgirish 
21844961713Sgirish /*
21944961713Sgirish  * Commmon definitions for NPI RXDMA and TXDMA functions.
22044961713Sgirish  */
22144961713Sgirish typedef struct _dma_log_page {
22244961713Sgirish 	uint8_t			page_num;
22344961713Sgirish 	boolean_t		valid;
22444961713Sgirish 	uint8_t			func_num;
22544961713Sgirish 	uint64_t		mask;
22644961713Sgirish 	uint64_t		value;
22744961713Sgirish 	uint64_t		reloc;
22844961713Sgirish } dma_log_page_t, *p_dma_log_page_t;
22944961713Sgirish 
23044961713Sgirish extern	rtrace_t npi_rtracebuf;
23144961713Sgirish void npi_rtrace_buf_init(rtrace_t *);
23244961713Sgirish void npi_rtrace_update(npi_handle_t, boolean_t, rtrace_t *,
233*678453a8Sspeer     uint32_t, uint64_t);
234*678453a8Sspeer void npi_trace_update(npi_handle_t, boolean_t, rtrace_t *,
235*678453a8Sspeer     const char *, uint32_t, uint64_t);
23644961713Sgirish void npi_rtrace_buf_init(rtrace_t *);
23744961713Sgirish 
23844961713Sgirish void npi_debug_msg(npi_handle_function_t, uint64_t,
23944961713Sgirish 	char *, ...);
24044961713Sgirish 
24144961713Sgirish #ifdef	NPI_DEBUG
24244961713Sgirish #define	NPI_DEBUG_MSG(params) npi_debug_msg params
24344961713Sgirish #else
24444961713Sgirish #define	NPI_DEBUG_MSG(params)
24544961713Sgirish #endif
24644961713Sgirish 
24744961713Sgirish #define	NPI_ERROR_MSG(params) npi_debug_msg params
24844961713Sgirish #define	NPI_REG_DUMP_MSG(params) npi_debug_msg params
24944961713Sgirish 
25044961713Sgirish #ifdef	__cplusplus
25144961713Sgirish }
25244961713Sgirish #endif
25344961713Sgirish 
25444961713Sgirish #endif	/* _NPI_H */
255