xref: /illumos-gate/usr/src/uts/common/io/ixgbe/ixgbe_sw.h (revision f2fe7aca)
19da57d7bSbt /*
29da57d7bSbt  * CDDL HEADER START
39da57d7bSbt  *
49da57d7bSbt  * The contents of this file are subject to the terms of the
59da57d7bSbt  * Common Development and Distribution License (the "License").
69da57d7bSbt  * You may not use this file except in compliance with the License.
79da57d7bSbt  *
8da14cebeSEric Cheng  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9da14cebeSEric Cheng  * or http://www.opensolaris.org/os/licensing.
109da57d7bSbt  * See the License for the specific language governing permissions
119da57d7bSbt  * and limitations under the License.
129da57d7bSbt  *
13da14cebeSEric Cheng  * When distributing Covered Code, include this CDDL HEADER in each
14da14cebeSEric Cheng  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
159da57d7bSbt  * If applicable, add the following below this CDDL HEADER, with the
169da57d7bSbt  * fields enclosed by brackets "[]" replaced with your own identifying
179da57d7bSbt  * information: Portions Copyright [yyyy] [name of copyright owner]
189da57d7bSbt  *
199da57d7bSbt  * CDDL HEADER END
209da57d7bSbt  */
229da57d7bSbt /*
235b6dd21fSchenlu chen - Sun Microsystems - Beijing China  * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
245b6dd21fSchenlu chen - Sun Microsystems - Beijing China  */
255b6dd21fSchenlu chen - Sun Microsystems - Beijing China 
265b6dd21fSchenlu chen - Sun Microsystems - Beijing China /*
275b6dd21fSchenlu chen - Sun Microsystems - Beijing China  * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
2843fab1a9SSaso Kiselkov  * Copyright (c) 2013 Saso Kiselkov. All rights reserved.
29dc0cb1cdSDale Ghent  * Copyright 2016 OmniTI Computer Consulting, Inc. All rights reserved.
30168e1ed4SRyan Zezeski  * Copyright 2019 Joyent, Inc.
31*f2fe7acaSRobert Mustacchi  * Copyright 2020 Oxide Computer Company
329da57d7bSbt  */
349da57d7bSbt #ifndef	_IXGBE_SW_H
359da57d7bSbt #define	_IXGBE_SW_H
379da57d7bSbt #ifdef __cplusplus
389da57d7bSbt extern "C" {
399da57d7bSbt #endif
419da57d7bSbt #include <sys/types.h>
429da57d7bSbt #include <sys/conf.h>
439da57d7bSbt #include <sys/debug.h>
449da57d7bSbt #include <sys/stropts.h>
459da57d7bSbt #include <sys/stream.h>
469da57d7bSbt #include <sys/strsun.h>
479da57d7bSbt #include <sys/strlog.h>
489da57d7bSbt #include <sys/kmem.h>
499da57d7bSbt #include <sys/stat.h>
509da57d7bSbt #include <sys/kstat.h>
519da57d7bSbt #include <sys/modctl.h>
529da57d7bSbt #include <sys/errno.h>
539da57d7bSbt #include <sys/dlpi.h>
54da14cebeSEric Cheng #include <sys/mac_provider.h>
559da57d7bSbt #include <sys/mac_ether.h>
569da57d7bSbt #include <sys/vlan.h>
579da57d7bSbt #include <sys/ddi.h>
589da57d7bSbt #include <sys/sunddi.h>
599da57d7bSbt #include <sys/pci.h>
609da57d7bSbt #include <sys/pcie.h>
619da57d7bSbt #include <sys/sdt.h>
629da57d7bSbt #include <sys/ethernet.h>
639da57d7bSbt #include <sys/pattr.h>
649da57d7bSbt #include <sys/strsubr.h>
659da57d7bSbt #include <sys/netlb.h>
669da57d7bSbt #include <sys/random.h>
679da57d7bSbt #include <inet/common.h>
68c971fb7eSgg #include <inet/tcp.h>
699da57d7bSbt #include <inet/ip.h>
709da57d7bSbt #include <inet/mi.h>
719da57d7bSbt #include <inet/nd.h>
729da57d7bSbt #include <sys/bitmap.h>
739da57d7bSbt #include <sys/ddifm.h>
749da57d7bSbt #include <sys/fm/protocol.h>
759da57d7bSbt #include <sys/fm/util.h>
7662e6e1adSPaul Guo #include <sys/disp.h>
779da57d7bSbt #include <sys/fm/io/ddi.h>
78*f2fe7acaSRobert Mustacchi #include <sys/ddi_ufm.h>
799da57d7bSbt #include "ixgbe_api.h"
819da57d7bSbt #define	MODULE_NAME			"ixgbe"	/* module name */
839da57d7bSbt #define	IXGBE_FAILURE			DDI_FAILURE
859da57d7bSbt #define	IXGBE_UNKNOWN			0x00
869da57d7bSbt #define	IXGBE_INITIALIZED		0x01
879da57d7bSbt #define	IXGBE_STARTED			0x02
889da57d7bSbt #define	IXGBE_SUSPENDED			0x04
8962e6e1adSPaul Guo #define	IXGBE_STALL			0x08
905b6dd21fSchenlu chen - Sun Microsystems - Beijing China #define	IXGBE_OVERTEMP			0x20
910dc2366fSVenugopal Iyer #define	IXGBE_INTR_ADJUST		0x40
9262e6e1adSPaul Guo #define	IXGBE_ERROR			0x80
94168e1ed4SRyan Zezeski #define	MAX_NUM_UNICAST_ADDRESSES	0x80
95168e1ed4SRyan Zezeski #define	MAX_NUM_MULTICAST_ADDRESSES	0x1000
9684de666eSRyan Zezeski #define	MAX_NUM_VLAN_FILTERS		0x40
9784de666eSRyan Zezeski 
989da57d7bSbt #define	IXGBE_INTR_NONE			0
999da57d7bSbt #define	IXGBE_INTR_MSIX			1
1009da57d7bSbt #define	IXGBE_INTR_MSI			2
1019da57d7bSbt #define	IXGBE_INTR_LEGACY		3
103da14cebeSEric Cheng #define	IXGBE_POLL_NULL			-1
104da14cebeSEric Cheng 
105c971fb7eSgg #define	MAX_COOKIE			18
1069da57d7bSbt #define	MIN_NUM_TX_DESC			2
108edf70dc9SPaul Guo #define	IXGBE_TX_DESC_LIMIT		32	/* tx desc limitation	*/
109edf70dc9SPaul Guo 
11073cd555cSBin Tu - Sun Microsystems - Beijing China #define	IXGBE_ADAPTER_REGSET		1	/* map adapter registers */
11173cd555cSBin Tu - Sun Microsystems - Beijing China 
112ea65739eSchenlu chen - Sun Microsystems - Beijing China #define	IXGBE_RX_STOPPED		0x1
113ea65739eSchenlu chen - Sun Microsystems - Beijing China 
114ffd8e883SWinson Wang - Sun Microsystems - Beijing China #define	IXGBE_PKG_BUF_16k		16384
115ffd8e883SWinson Wang - Sun Microsystems - Beijing China 
1169da57d7bSbt /*
11773cd555cSBin Tu - Sun Microsystems - Beijing China  * MAX_xx_QUEUE_NUM and MAX_INTR_VECTOR values need to be the maximum of all
11813740cb2SPaul Guo  * supported silicon types.
1199da57d7bSbt  */
12073cd555cSBin Tu - Sun Microsystems - Beijing China #define	MAX_TX_QUEUE_NUM		128
12173cd555cSBin Tu - Sun Microsystems - Beijing China #define	MAX_RX_QUEUE_NUM		128
12273cd555cSBin Tu - Sun Microsystems - Beijing China #define	MAX_INTR_VECTOR			64
1249da57d7bSbt /*
12513740cb2SPaul Guo  * Maximum values for user configurable parameters
1269da57d7bSbt  */
1279da57d7bSbt #define	MAX_TX_RING_SIZE		4096
1289da57d7bSbt #define	MAX_RX_RING_SIZE		4096
1309da57d7bSbt #define	MAX_RX_LIMIT_PER_INTR		4096
1329da57d7bSbt #define	MAX_RX_COPY_THRESHOLD		9216
1339da57d7bSbt #define	MAX_TX_COPY_THRESHOLD		9216
1389da57d7bSbt /*
1399da57d7bSbt  * Minimum values for user configurable parameters
1409da57d7bSbt  */
1419da57d7bSbt #define	MIN_TX_RING_SIZE		64
1429da57d7bSbt #define	MIN_RX_RING_SIZE		64
1449da57d7bSbt #define	MIN_MTU				ETHERMIN
1459da57d7bSbt #define	MIN_RX_LIMIT_PER_INTR		16
1469da57d7bSbt #define	MIN_TX_COPY_THRESHOLD		0
1479da57d7bSbt #define	MIN_RX_COPY_THRESHOLD		0
1529da57d7bSbt /*
1539da57d7bSbt  * Default values for user configurable parameters
1549da57d7bSbt  */
155da14cebeSEric Cheng #define	DEFAULT_TX_RING_SIZE		1024
156da14cebeSEric Cheng #define	DEFAULT_RX_RING_SIZE		1024
1589da57d7bSbt #define	DEFAULT_MTU			ETHERMTU
1599da57d7bSbt #define	DEFAULT_RX_LIMIT_PER_INTR	256
1609da57d7bSbt #define	DEFAULT_RX_COPY_THRESHOLD	128
1619da57d7bSbt #define	DEFAULT_TX_COPY_THRESHOLD	512
162da14cebeSEric Cheng #define	DEFAULT_TX_RECYCLE_THRESHOLD	(MAX_COOKIE + 1)
1649da57d7bSbt #define	DEFAULT_TX_RESCHED_THRESHOLD	128
1659da57d7bSbt #define	DEFAULT_FCRTH			0x20000
1669da57d7bSbt #define	DEFAULT_FCRTL			0x10000
1679da57d7bSbt #define	DEFAULT_FCPAUSE			0xFFFF
169da14cebeSEric Cheng #define	DEFAULT_TX_HCKSUM_ENABLE	B_TRUE
170da14cebeSEric Cheng #define	DEFAULT_RX_HCKSUM_ENABLE	B_TRUE
171da14cebeSEric Cheng #define	DEFAULT_LSO_ENABLE		B_TRUE
172ffd8e883SWinson Wang - Sun Microsystems - Beijing China #define	DEFAULT_LRO_ENABLE		B_FALSE
173da14cebeSEric Cheng #define	DEFAULT_MR_ENABLE		B_TRUE
174da14cebeSEric Cheng #define	DEFAULT_TX_HEAD_WB_ENABLE	B_TRUE
1755b6dd21fSchenlu chen - Sun Microsystems - Beijing China #define	DEFAULT_RELAX_ORDER_ENABLE	B_TRUE
17643fab1a9SSaso Kiselkov #define	DEFAULT_ALLOW_UNSUPPORTED_SFP	B_FALSE
177da14cebeSEric Cheng 
178da14cebeSEric Cheng #define	IXGBE_LSO_MAXLEN		65535
179da14cebeSEric Cheng 
1809da57d7bSbt #define	TX_DRAIN_TIME			200
1819da57d7bSbt #define	RX_DRAIN_TIME			200
1839da57d7bSbt #define	STALL_WATCHDOG_TIMEOUT		8	/* 8 seconds */
1849da57d7bSbt #define	MAX_LINK_DOWN_TIMEOUT		8	/* 8 seconds */
18662e6e1adSPaul Guo #define	IXGBE_CYCLIC_PERIOD		(1000000000)	/* 1s */
18762e6e1adSPaul Guo 
1889da57d7bSbt /*
1899da57d7bSbt  * Extra register bit masks for 82598
1909da57d7bSbt  */
1919da57d7bSbt #define	IXGBE_PCS1GANA_FDC	0x20
1929da57d7bSbt #define	IXGBE_PCS1GANLP_LPFD	0x20
1939da57d7bSbt #define	IXGBE_PCS1GANLP_LPHD	0x40
1959da57d7bSbt /*
1969da57d7bSbt  * Defined for IP header alignment.
1979da57d7bSbt  */
1989da57d7bSbt #define	IPHDR_ALIGN_ROOM		2
2009da57d7bSbt /*
2019da57d7bSbt  * Bit flags for attach_progress
2029da57d7bSbt  */
2039da57d7bSbt #define	ATTACH_PROGRESS_PCI_CONFIG	0x0001	/* PCI config setup */
2049da57d7bSbt #define	ATTACH_PROGRESS_REGS_MAP	0x0002	/* Registers mapped */
2059da57d7bSbt #define	ATTACH_PROGRESS_PROPS		0x0004	/* Properties initialized */
2069da57d7bSbt #define	ATTACH_PROGRESS_ALLOC_INTR	0x0008	/* Interrupts allocated */
2079da57d7bSbt #define	ATTACH_PROGRESS_ALLOC_RINGS	0x0010	/* Rings allocated */
2089da57d7bSbt #define	ATTACH_PROGRESS_ADD_INTR	0x0020	/* Intr handlers added */
2099da57d7bSbt #define	ATTACH_PROGRESS_LOCKS		0x0040	/* Locks initialized */
2109da57d7bSbt #define	ATTACH_PROGRESS_INIT		0x0080	/* Device initialized */
2119da57d7bSbt #define	ATTACH_PROGRESS_STATS		0x0200	/* Kstats created */
2129da57d7bSbt #define	ATTACH_PROGRESS_MAC		0x0800	/* MAC registered */
2139da57d7bSbt #define	ATTACH_PROGRESS_ENABLE_INTR	0x1000	/* DDI interrupts enabled */
2149da57d7bSbt #define	ATTACH_PROGRESS_FM_INIT		0x2000	/* FMA initialized */
21562e6e1adSPaul Guo #define	ATTACH_PROGRESS_SFP_TASKQ	0x4000	/* SFP taskq created */
21662e6e1adSPaul Guo #define	ATTACH_PROGRESS_LINK_TIMER	0x8000	/* link check timer */
2175b6dd21fSchenlu chen - Sun Microsystems - Beijing China #define	ATTACH_PROGRESS_OVERTEMP_TASKQ	0x10000 /* Over-temp taskq created */
218dc0cb1cdSDale Ghent #define	ATTACH_PROGRESS_PHY_TASKQ	0x20000 /* Ext. PHY taskq created */
219*f2fe7acaSRobert Mustacchi #define	ATTACH_PROGRESS_UFM		0x40000	/* UFM support */
2219da57d7bSbt #define	PROP_DEFAULT_MTU		"default_mtu"
2229da57d7bSbt #define	PROP_FLOW_CONTROL		"flow_control"
2239da57d7bSbt #define	PROP_TX_QUEUE_NUM		"tx_queue_number"
2249da57d7bSbt #define	PROP_TX_RING_SIZE		"tx_ring_size"
2259da57d7bSbt #define	PROP_RX_QUEUE_NUM		"rx_queue_number"
2269da57d7bSbt #define	PROP_RX_RING_SIZE		"rx_ring_size"
227da14cebeSEric Cheng #define	PROP_RX_GROUP_NUM		"rx_group_number"
2299da57d7bSbt #define	PROP_INTR_FORCE			"intr_force"
2309da57d7bSbt #define	PROP_TX_HCKSUM_ENABLE		"tx_hcksum_enable"
2319da57d7bSbt #define	PROP_RX_HCKSUM_ENABLE		"rx_hcksum_enable"
2329da57d7bSbt #define	PROP_LSO_ENABLE			"lso_enable"
233ffd8e883SWinson Wang - Sun Microsystems - Beijing China #define	PROP_LRO_ENABLE			"lro_enable"
234da14cebeSEric Cheng #define	PROP_MR_ENABLE			"mr_enable"
2355b6dd21fSchenlu chen - Sun Microsystems - Beijing China #define	PROP_RELAX_ORDER_ENABLE		"relax_order_enable"
2369da57d7bSbt #define	PROP_TX_HEAD_WB_ENABLE		"tx_head_wb_enable"
2379da57d7bSbt #define	PROP_TX_COPY_THRESHOLD		"tx_copy_threshold"
2389da57d7bSbt #define	PROP_TX_RECYCLE_THRESHOLD	"tx_recycle_threshold"
2399da57d7bSbt #define	PROP_TX_OVERLOAD_THRESHOLD	"tx_overload_threshold"
2409da57d7bSbt #define	PROP_TX_RESCHED_THRESHOLD	"tx_resched_threshold"
2419da57d7bSbt #define	PROP_RX_COPY_THRESHOLD		"rx_copy_threshold"
2429da57d7bSbt #define	PROP_RX_LIMIT_PER_INTR		"rx_limit_per_intr"
2439da57d7bSbt #define	PROP_INTR_THROTTLING		"intr_throttling"
2449da57d7bSbt #define	PROP_FM_CAPABLE			"fm_capable"
24543fab1a9SSaso Kiselkov #define	PROP_ALLOW_UNSUPPORTED_SFP	"allow_unsupported_sfp"
2479da57d7bSbt #define	IXGBE_LB_NONE			0
2489da57d7bSbt #define	IXGBE_LB_EXTERNAL		1
2499da57d7bSbt #define	IXGBE_LB_INTERNAL_MAC		2
2509da57d7bSbt #define	IXGBE_LB_INTERNAL_PHY		3
2519da57d7bSbt #define	IXGBE_LB_INTERNAL_SERDES	4
25313740cb2SPaul Guo /*
25413740cb2SPaul Guo  * capability/feature flags
25513740cb2SPaul Guo  * Flags named _CAPABLE are set when the NIC hardware is capable of the feature.
25613740cb2SPaul Guo  * Separately, the flag named _ENABLED is set when the feature is enabled.
25713740cb2SPaul Guo  */
25813740cb2SPaul Guo #define	IXGBE_FLAG_DCA_ENABLED		(u32)(1)
25913740cb2SPaul Guo #define	IXGBE_FLAG_DCA_CAPABLE		(u32)(1 << 1)
26013740cb2SPaul Guo #define	IXGBE_FLAG_DCB_ENABLED		(u32)(1 << 2)
26113740cb2SPaul Guo #define	IXGBE_FLAG_DCB_CAPABLE		(u32)(1 << 4)
26213740cb2SPaul Guo #define	IXGBE_FLAG_RSS_ENABLED		(u32)(1 << 4)
26313740cb2SPaul Guo #define	IXGBE_FLAG_RSS_CAPABLE		(u32)(1 << 5)
26413740cb2SPaul Guo #define	IXGBE_FLAG_VMDQ_CAPABLE		(u32)(1 << 6)
26513740cb2SPaul Guo #define	IXGBE_FLAG_VMDQ_ENABLED		(u32)(1 << 7)
26613740cb2SPaul Guo #define	IXGBE_FLAG_FAN_FAIL_CAPABLE	(u32)(1 << 8)
267ffd8e883SWinson Wang - Sun Microsystems - Beijing China #define	IXGBE_FLAG_RSC_CAPABLE		(u32)(1 << 9)
2685b6dd21fSchenlu chen - Sun Microsystems - Beijing China #define	IXGBE_FLAG_SFP_PLUG_CAPABLE	(u32)(1 << 10)
2695b6dd21fSchenlu chen - Sun Microsystems - Beijing China #define	IXGBE_FLAG_TEMP_SENSOR_CAPABLE	(u32)(1 << 11)
27013740cb2SPaul Guo 
2710dc2366fSVenugopal Iyer /*
2720dc2366fSVenugopal Iyer  * Classification mode
2730dc2366fSVenugopal Iyer  */
2740dc2366fSVenugopal Iyer #define	IXGBE_CLASSIFY_NONE		0
2750dc2366fSVenugopal Iyer #define	IXGBE_CLASSIFY_RSS		1
2760dc2366fSVenugopal Iyer #define	IXGBE_CLASSIFY_VMDQ		2
2770dc2366fSVenugopal Iyer #define	IXGBE_CLASSIFY_VMDQ_RSS		3
2780dc2366fSVenugopal Iyer 
27913740cb2SPaul Guo /* adapter-specific info for each supported device type */
28013740cb2SPaul Guo typedef struct adapter_info {
2810dc2366fSVenugopal Iyer 	uint32_t	max_rx_que_num; /* maximum number of rx queues */
2820dc2366fSVenugopal Iyer 	uint32_t	min_rx_que_num; /* minimum number of rx queues */
2830dc2366fSVenugopal Iyer 	uint32_t	def_rx_que_num; /* default number of rx queues */
2840dc2366fSVenugopal Iyer 	uint32_t	max_rx_grp_num; /* maximum number of rx groups */
2850dc2366fSVenugopal Iyer 	uint32_t	min_rx_grp_num; /* minimum number of rx groups */
2860dc2366fSVenugopal Iyer 	uint32_t	def_rx_grp_num; /* default number of rx groups */
28713740cb2SPaul Guo 	uint32_t	max_tx_que_num;	/* maximum number of tx queues */
28813740cb2SPaul Guo 	uint32_t	min_tx_que_num;	/* minimum number of tx queues */
28913740cb2SPaul Guo 	uint32_t	def_tx_que_num;	/* default number of tx queues */
2901fedc51fSWinson Wang - Sun Microsystems - Beijing China 	uint32_t	max_mtu;	/* maximum MTU size */
291ea65739eSchenlu chen - Sun Microsystems - Beijing China 	/*
292ea65739eSchenlu chen - Sun Microsystems - Beijing China 	 * Interrupt throttling is in unit of 256 nsec
293ea65739eSchenlu chen - Sun Microsystems - Beijing China 	 */
294ea65739eSchenlu chen - Sun Microsystems - Beijing China 	uint32_t	max_intr_throttle; /* maximum interrupt throttle */
295ea65739eSchenlu chen - Sun Microsystems - Beijing China 	uint32_t	min_intr_throttle; /* minimum interrupt throttle */
296ea65739eSchenlu chen - Sun Microsystems - Beijing China 	uint32_t	def_intr_throttle; /* default interrupt throttle */
297ea65739eSchenlu chen - Sun Microsystems - Beijing China 
29813740cb2SPaul Guo 	uint32_t	max_msix_vect;	/* maximum total msix vectors */
29913740cb2SPaul Guo 	uint32_t	max_ring_vect;	/* maximum number of ring vectors */
30013740cb2SPaul Guo 	uint32_t	max_other_vect;	/* maximum number of other vectors */
30113740cb2SPaul Guo 	uint32_t	other_intr;	/* "other" interrupt types handled */
3025b6dd21fSchenlu chen - Sun Microsystems - Beijing China 	uint32_t	other_gpie;	/* "other" interrupt types enabling */
30313740cb2SPaul Guo 	uint32_t	flags;		/* capability flags */
30413740cb2SPaul Guo } adapter_info_t;
30513740cb2SPaul Guo 
30613740cb2SPaul Guo /* bits representing all interrupt types other than tx & rx */
30713740cb2SPaul Guo #define	IXGBE_OTHER_INTR	0x3ff00000
30873cd555cSBin Tu - Sun Microsystems - Beijing China #define	IXGBE_82599_OTHER_INTR	0x86100000
30913740cb2SPaul Guo 
3109da57d7bSbt enum ioc_reply {
3119da57d7bSbt 	IOC_INVAL = -1,	/* bad, NAK with EINVAL */
312168e1ed4SRyan Zezeski 	IOC_DONE,	/* OK, reply sent */
3139da57d7bSbt 	IOC_ACK,	/* OK, just send ACK */
3149da57d7bSbt 	IOC_REPLY	/* OK, just send reply */
3159da57d7bSbt };
3179da57d7bSbt #define	DMA_SYNC(area, flag)	((void) ddi_dma_sync((area)->dma_handle, \
3189da57d7bSbt 				    0, 0, (flag)))
3209da57d7bSbt /*
3219da57d7bSbt  * Defined for ring index operations
3229da57d7bSbt  * ASSERT(index < limit)
3239da57d7bSbt  * ASSERT(step < limit)
3249da57d7bSbt  * ASSERT(index1 < limit)
3259da57d7bSbt  * ASSERT(index2 < limit)
3269da57d7bSbt  */
3279da57d7bSbt #define	NEXT_INDEX(index, step, limit)	(((index) + (step)) < (limit) ? \
3289da57d7bSbt 	(index) + (step) : (index) + (step) - (limit))
3299da57d7bSbt #define	PREV_INDEX(index, step, limit)	((index) >= (step) ? \
3309da57d7bSbt 	(index) - (step) : (index) + (limit) - (step))
3319da57d7bSbt #define	OFFSET(index1, index2, limit)	((index1) <= (index2) ? \
3329da57d7bSbt 	(index2) - (index1) : (index2) + (limit) - (index1))
3349da57d7bSbt #define	LINK_LIST_INIT(_LH)	\
3359da57d7bSbt 	(_LH)->head = (_LH)->tail = NULL
3379da57d7bSbt #define	LIST_GET_HEAD(_LH)	((single_link_t *)((_LH)->head))
3399da57d7bSbt #define	LIST_POP_HEAD(_LH)	\
3409da57d7bSbt 	(single_link_t *)(_LH)->head; \
3419da57d7bSbt 	{ \
3429da57d7bSbt 		if ((_LH)->head != NULL) { \
3439da57d7bSbt 			(_LH)->head = (_LH)->head->link; \
3449da57d7bSbt 			if ((_LH)->head == NULL) \
3459da57d7bSbt 				(_LH)->tail = NULL; \
3469da57d7bSbt 		} \
3479da57d7bSbt 	}
3499da57d7bSbt #define	LIST_GET_TAIL(_LH)	((single_link_t *)((_LH)->tail))
3519da57d7bSbt #define	LIST_PUSH_TAIL(_LH, _E)	\
3529da57d7bSbt 	if ((_LH)->tail != NULL) { \
3539da57d7bSbt 		(_LH)->tail->link = (single_link_t *)(_E); \
3549da57d7bSbt 		(_LH)->tail = (single_link_t *)(_E); \
3559da57d7bSbt 	} else { \
3569da57d7bSbt 		(_LH)->head = (_LH)->tail = (single_link_t *)(_E); \
3579da57d7bSbt 	} \
3589da57d7bSbt 	(_E)->link = NULL;
3609da57d7bSbt #define	LIST_GET_NEXT(_LH, _E)		\
3619da57d7bSbt 	(((_LH)->tail == (single_link_t *)(_E)) ? \
3629da57d7bSbt 	NULL : ((single_link_t *)(_E))->link)
3659da57d7bSbt typedef struct single_link {
3669da57d7bSbt 	struct single_link	*link;
3679da57d7bSbt } single_link_t;
3699da57d7bSbt typedef struct link_list {
3709da57d7bSbt 	single_link_t		*head;
3719da57d7bSbt 	single_link_t		*tail;
3729da57d7bSbt } link_list_t;
3749da57d7bSbt /*
3759da57d7bSbt  * Property lookups
3769da57d7bSbt  */
3779da57d7bSbt #define	IXGBE_PROP_EXISTS(d, n)	ddi_prop_exists(DDI_DEV_T_ANY, (d), \
3789da57d7bSbt 				    DDI_PROP_DONTPASS, (n))
3799da57d7bSbt #define	IXGBE_PROP_GET_INT(d, n)	ddi_prop_get_int(DDI_DEV_T_ANY, (d), \
3809da57d7bSbt 				    DDI_PROP_DONTPASS, (n), -1)
3839da57d7bSbt typedef union ixgbe_ether_addr {
3849da57d7bSbt 	struct {
3859da57d7bSbt 		uint32_t	high;
3869da57d7bSbt 		uint32_t	low;
3879da57d7bSbt 	} reg;
3889da57d7bSbt 	struct {
3899da57d7bSbt 		uint8_t		set;
3900dc2366fSVenugopal Iyer 		uint8_t		group_index;
3919da57d7bSbt 		uint8_t		addr[ETHERADDRL];
3929da57d7bSbt 	} mac;
3939da57d7bSbt } ixgbe_ether_addr_t;
39584de666eSRyan Zezeski /*
39684de666eSRyan Zezeski  * The list of VLANs an Rx group will accept.
39784de666eSRyan Zezeski  */
39884de666eSRyan Zezeski typedef struct ixgbe_vlan {
39984de666eSRyan Zezeski 	list_node_t		ixvl_link;
40084de666eSRyan Zezeski 	uint16_t		ixvl_vid;   /* The VLAN ID */
40184de666eSRyan Zezeski 	uint_t			ixvl_refs;  /* Number of users of this VLAN */
40284de666eSRyan Zezeski } ixgbe_vlan_t;
40384de666eSRyan Zezeski 
4049da57d7bSbt typedef enum {
4059da57d7bSbt 	USE_NONE,
4069da57d7bSbt 	USE_COPY,
4079da57d7bSbt 	USE_DMA
4089da57d7bSbt } tx_type_t;
410c971fb7eSgg typedef struct ixgbe_tx_context {
4119da57d7bSbt 	uint32_t		hcksum_flags;
4129da57d7bSbt 	uint32_t		ip_hdr_len;
4139da57d7bSbt 	uint32_t		mac_hdr_len;
41485f496faSRobert Mustacchi 	uint32_t		l3_proto;
4159da57d7bSbt 	uint32_t		l4_proto;
416c971fb7eSgg 	uint32_t		mss;
417c971fb7eSgg 	uint32_t		l4_hdr_len;
418c971fb7eSgg 	boolean_t		lso_flag;
419c971fb7eSgg } ixgbe_tx_context_t;
4219da57d7bSbt /*
4229da57d7bSbt  * Hold address/length of each DMA segment
4239da57d7bSbt  */
4249da57d7bSbt typedef struct sw_desc {
4259da57d7bSbt 	uint64_t		address;
4269da57d7bSbt 	size_t			length;
4279da57d7bSbt } sw_desc_t;
4299da57d7bSbt /*
4309da57d7bSbt  * Handles and addresses of DMA buffer
4319da57d7bSbt  */
4329da57d7bSbt typedef struct dma_buffer {
4339da57d7bSbt 	caddr_t			address;	/* Virtual address */
4349da57d7bSbt 	uint64_t		dma_address;	/* DMA (Hardware) address */
4359da57d7bSbt 	ddi_acc_handle_t	acc_handle;	/* Data access handle */
4369da57d7bSbt 	ddi_dma_handle_t	dma_handle;	/* DMA handle */
4379da57d7bSbt 	size_t			size;		/* Buffer size */
4389da57d7bSbt 	size_t			len;		/* Data length in the buffer */
4399da57d7bSbt } dma_buffer_t;
4419da57d7bSbt /*
4429da57d7bSbt  * Tx Control Block
4439da57d7bSbt  */
4449da57d7bSbt typedef struct tx_control_block {
4459da57d7bSbt 	single_link_t		link;
446edf70dc9SPaul Guo 	uint32_t		last_index; /* last descriptor of the pkt */
4479da57d7bSbt 	uint32_t		frag_num;
4489da57d7bSbt 	uint32_t		desc_num;
4499da57d7bSbt 	mblk_t			*mp;
4509da57d7bSbt 	tx_type_t		tx_type;
4519da57d7bSbt 	ddi_dma_handle_t	tx_dma_handle;
4529da57d7bSbt 	dma_buffer_t		tx_buf;
4539da57d7bSbt 	sw_desc_t		desc[MAX_COOKIE];
4549da57d7bSbt } tx_control_block_t;
4569da57d7bSbt /*
4579da57d7bSbt  * RX Control Block
4589da57d7bSbt  */
4599da57d7bSbt typedef struct rx_control_block {
4609da57d7bSbt 	mblk_t			*mp;
461ea65739eSchenlu chen - Sun Microsystems - Beijing China 	uint32_t		ref_cnt;
4629da57d7bSbt 	dma_buffer_t		rx_buf;
4639da57d7bSbt 	frtn_t			free_rtn;
464ea65739eSchenlu chen - Sun Microsystems - Beijing China 	struct ixgbe_rx_data	*rx_data;
465ffd8e883SWinson Wang - Sun Microsystems - Beijing China 	int			lro_next;	/* Index of next rcb */
466ffd8e883SWinson Wang - Sun Microsystems - Beijing China 	int			lro_prev;	/* Index of previous rcb */
467ffd8e883SWinson Wang - Sun Microsystems - Beijing China 	boolean_t		lro_pkt;	/* Flag for LRO rcb */
4689da57d7bSbt } rx_control_block_t;
4709da57d7bSbt /*
4719da57d7bSbt  * Software Data Structure for Tx Ring
4729da57d7bSbt  */
4739da57d7bSbt typedef struct ixgbe_tx_ring {
4749da57d7bSbt 	uint32_t		index;	/* Ring index */
4759da57d7bSbt 	uint32_t		intr_vector;	/* Interrupt vector index */
4769da57d7bSbt 	uint32_t		vect_bit;	/* vector's bit in register */
4789da57d7bSbt 	/*
4799da57d7bSbt 	 * Mutexes
4809da57d7bSbt 	 */
4819da57d7bSbt 	kmutex_t		tx_lock;
4829da57d7bSbt 	kmutex_t		recycle_lock;
4839da57d7bSbt 	kmutex_t		tcb_head_lock;
4849da57d7bSbt 	kmutex_t		tcb_tail_lock;
4869da57d7bSbt 	/*
4879da57d7bSbt 	 * Tx descriptor ring definitions
4889da57d7bSbt 	 */
4899da57d7bSbt 	dma_buffer_t		tbd_area;
4909da57d7bSbt 	union ixgbe_adv_tx_desc	*tbd_ring;
4919da57d7bSbt 	uint32_t		tbd_head; /* Index of next tbd to recycle */
4929da57d7bSbt 	uint32_t		tbd_tail; /* Index of next tbd to transmit */
4939da57d7bSbt 	uint32_t		tbd_free; /* Number of free tbd */
4959da57d7bSbt 	/*
4969da57d7bSbt 	 * Tx control block list definitions
4979da57d7bSbt 	 */
4989da57d7bSbt 	tx_control_block_t	*tcb_area;
4999da57d7bSbt 	tx_control_block_t	**work_list;
5009da57d7bSbt 	tx_control_block_t	**free_list;
5019da57d7bSbt 	uint32_t		tcb_head; /* Head index of free list */
5029da57d7bSbt 	uint32_t		tcb_tail; /* Tail index of free list */
5039da57d7bSbt 	uint32_t		tcb_free; /* Number of free tcb in free list */
5059da57d7bSbt 	uint32_t		*tbd_head_wb; /* Head write-back */
5069da57d7bSbt 	uint32_t		(*tx_recycle)(struct ixgbe_tx_ring *);
5089da57d7bSbt 	/*
509c971fb7eSgg 	 * s/w context structure for TCP/UDP checksum offload
510c971fb7eSgg 	 * and LSO.
5119da57d7bSbt 	 */
512c971fb7eSgg 	ixgbe_tx_context_t	tx_context;
5149da57d7bSbt 	/*
5159da57d7bSbt 	 * Tx ring settings and status
5169da57d7bSbt 	 */
5179da57d7bSbt 	uint32_t		ring_size; /* Tx descriptor ring size */
5189da57d7bSbt 	uint32_t		free_list_size;	/* Tx free list size */
5209da57d7bSbt 	boolean_t		reschedule;
5219da57d7bSbt 	uint32_t		recycle_fail;
5229da57d7bSbt 	uint32_t		stall_watchdog;
5249da57d7bSbt 	uint32_t		stat_overload;
5259da57d7bSbt 	uint32_t		stat_fail_no_tbd;
5269da57d7bSbt 	uint32_t		stat_fail_no_tcb;
5279da57d7bSbt 	uint32_t		stat_fail_dma_bind;
5289da57d7bSbt 	uint32_t		stat_reschedule;
529edf70dc9SPaul Guo 	uint32_t		stat_break_tbd_limit;
530da14cebeSEric Cheng 	uint32_t		stat_lso_header_fail;
53163efadf0SRyan Zezeski 
5320dc2366fSVenugopal Iyer 	uint64_t		stat_obytes;
5330dc2366fSVenugopal Iyer 	uint64_t		stat_opackets;
535da14cebeSEric Cheng 	mac_ring_handle_t	ring_handle;
536da14cebeSEric Cheng 
5379da57d7bSbt 	/*
5389da57d7bSbt 	 * Pointer to the ixgbe struct
5399da57d7bSbt 	 */
5409da57d7bSbt 	struct ixgbe		*ixgbe;
5419da57d7bSbt } ixgbe_tx_ring_t;
5439da57d7bSbt /*
5449da57d7bSbt  * Software Receive Ring
5459da57d7bSbt  */
546ea65739eSchenlu chen - Sun Microsystems - Beijing China typedef struct ixgbe_rx_data {
5479da57d7bSbt 	kmutex_t		recycle_lock;	/* Recycle lock, for rcb_tail */
5499da57d7bSbt 	/*
5509da57d7bSbt 	 * Rx descriptor ring definitions
5519da57d7bSbt 	 */
5529da57d7bSbt 	dma_buffer_t		rbd_area;	/* DMA buffer of rx desc ring */
5539da57d7bSbt 	union ixgbe_adv_rx_desc	*rbd_ring;	/* Rx desc ring */
5549da57d7bSbt 	uint32_t		rbd_next;	/* Index of next rx desc */
5569da57d7bSbt 	/*
5579da57d7bSbt 	 * Rx control block list definitions
5589da57d7bSbt 	 */
5599da57d7bSbt 	rx_control_block_t	*rcb_area;
5609da57d7bSbt 	rx_control_block_t	**work_list;	/* Work list of rcbs */
5619da57d7bSbt 	rx_control_block_t	**free_list;	/* Free list of rcbs */
5629da57d7bSbt 	uint32_t		rcb_head;	/* Index of next free rcb */
5639da57d7bSbt 	uint32_t		rcb_tail;	/* Index to put recycled rcb */
5649da57d7bSbt 	uint32_t		rcb_free;	/* Number of free rcbs */
5669da57d7bSbt 	/*
567ea65739eSchenlu chen - Sun Microsystems - Beijing China 	 * Rx sw ring settings and status
5689da57d7bSbt 	 */
5699da57d7bSbt 	uint32_t		ring_size;	/* Rx descriptor ring size */
5709da57d7bSbt 	uint32_t		free_list_size;	/* Rx free list size */
571ea65739eSchenlu chen - Sun Microsystems - Beijing China 
572ea65739eSchenlu chen - Sun Microsystems - Beijing China 	uint32_t		rcb_pending;
573ea65739eSchenlu chen - Sun Microsystems - Beijing China 	uint32_t		flag;
574ea65739eSchenlu chen - Sun Microsystems - Beijing China 
575ffd8e883SWinson Wang - Sun Microsystems - Beijing China 	uint32_t		lro_num;	/* Number of rcbs of one LRO */
576ffd8e883SWinson Wang - Sun Microsystems - Beijing China 	uint32_t		lro_first;	/* Index of first LRO rcb */
577ffd8e883SWinson Wang - Sun Microsystems - Beijing China 
578ea65739eSchenlu chen - Sun Microsystems - Beijing China 	struct ixgbe_rx_ring	*rx_ring;	/* Pointer to rx ring */
579ea65739eSchenlu chen - Sun Microsystems - Beijing China } ixgbe_rx_data_t;
580ea65739eSchenlu chen - Sun Microsystems - Beijing China 
581ea65739eSchenlu chen - Sun Microsystems - Beijing China /*
582ea65739eSchenlu chen - Sun Microsystems - Beijing China  * Software Data Structure for Rx Ring
583ea65739eSchenlu chen - Sun Microsystems - Beijing China  */
584ea65739eSchenlu chen - Sun Microsystems - Beijing China typedef struct ixgbe_rx_ring {
585ea65739eSchenlu chen - Sun Microsystems - Beijing China 	uint32_t		index;		/* Ring index */
5860dc2366fSVenugopal Iyer 	uint32_t		group_index;	/* Group index */
5870dc2366fSVenugopal Iyer 	uint32_t		hw_index;	/* h/w ring index */
588ea65739eSchenlu chen - Sun Microsystems - Beijing China 	uint32_t		intr_vector;	/* Interrupt vector index */
589ea65739eSchenlu chen - Sun Microsystems - Beijing China 	uint32_t		vect_bit;	/* vector's bit in register */
590ea65739eSchenlu chen - Sun Microsystems - Beijing China 
591ea65739eSchenlu chen - Sun Microsystems - Beijing China 	ixgbe_rx_data_t		*rx_data;	/* Rx software ring */
592ea65739eSchenlu chen - Sun Microsystems - Beijing China 
593ea65739eSchenlu chen - Sun Microsystems - Beijing China 	kmutex_t		rx_lock;	/* Rx access lock */
5959da57d7bSbt 	uint32_t		stat_frame_error;
5969da57d7bSbt 	uint32_t		stat_cksum_error;
5979da57d7bSbt 	uint32_t		stat_exceed_pkt;
598a9bfd41dSRyan Zezeski 
5990dc2366fSVenugopal Iyer 	uint64_t		stat_rbytes;
6000dc2366fSVenugopal Iyer 	uint64_t		stat_ipackets;
602da14cebeSEric Cheng 	mac_ring_handle_t	ring_handle;
603da14cebeSEric Cheng 	uint64_t		ring_gen_num;
605da14cebeSEric Cheng 	struct ixgbe		*ixgbe;		/* Pointer to ixgbe struct */
6069da57d7bSbt } ixgbe_rx_ring_t;
60784de666eSRyan Zezeski 
608da14cebeSEric Cheng /*
609da14cebeSEric Cheng  * Software Receive Ring Group
610da14cebeSEric Cheng  */
611da14cebeSEric Cheng typedef struct ixgbe_rx_group {
612da14cebeSEric Cheng 	uint32_t		index;		/* Group index */
613da14cebeSEric Cheng 	mac_group_handle_t	group_handle;   /* call back group handle */
614da14cebeSEric Cheng 	struct ixgbe		*ixgbe;		/* Pointer to ixgbe struct */
61584de666eSRyan Zezeski 	boolean_t		aupe;		/* AUPE bit */
61684de666eSRyan Zezeski 	list_t			vlans;		/* list of VLANs to allow */
617da14cebeSEric Cheng } ixgbe_rx_group_t;
618da14cebeSEric Cheng 
6199da57d7bSbt /*
62073cd555cSBin Tu - Sun Microsystems - Beijing China  * structure to map interrupt cleanup to msi-x vector
6219da57d7bSbt  */
62273cd555cSBin Tu - Sun Microsystems - Beijing China typedef struct ixgbe_intr_vector {
6239da57d7bSbt 	struct ixgbe *ixgbe;	/* point to my adapter */
6249da57d7bSbt 	ulong_t rx_map[BT_BITOUL(MAX_RX_QUEUE_NUM)];	/* bitmap of rx rings */
6259da57d7bSbt 	int	rxr_cnt;	/* count rx rings */
6269da57d7bSbt 	ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)];	/* bitmap of tx rings */
6279da57d7bSbt 	int	txr_cnt;	/* count tx rings */
62873cd555cSBin Tu - Sun Microsystems - Beijing China 	ulong_t other_map[BT_BITOUL(2)];		/* bitmap of other */
62973cd555cSBin Tu - Sun Microsystems - Beijing China 	int	other_cnt;	/* count other interrupt */
63073cd555cSBin Tu - Sun Microsystems - Beijing China } ixgbe_intr_vector_t;
6329da57d7bSbt /*
6339da57d7bSbt  * Software adapter state
6349da57d7bSbt  */
6359da57d7bSbt typedef struct ixgbe {
636168e1ed4SRyan Zezeski 	int			instance;
6379da57d7bSbt 	mac_handle_t		mac_hdl;
6389da57d7bSbt 	dev_info_t		*dip;
6399da57d7bSbt 	struct ixgbe_hw		hw;
6409da57d7bSbt 	struct ixgbe_osdep	osdep;
64213740cb2SPaul Guo 	adapter_info_t		*capab;	/* adapter hardware capabilities */
64362e6e1adSPaul Guo 	ddi_taskq_t		*sfp_taskq;	/* sfp-change taskq */
6445b6dd21fSchenlu chen - Sun Microsystems - Beijing China 	ddi_taskq_t		*overtemp_taskq; /* overtemp taskq */
645dc0cb1cdSDale Ghent 	ddi_taskq_t		*phy_taskq;	/* external PHY taskq */
64613740cb2SPaul Guo 	uint32_t		eims;		/* interrupt mask setting */
64773cd555cSBin Tu - Sun Microsystems - Beijing China 	uint32_t		eimc;		/* interrupt mask clear */
64873cd555cSBin Tu - Sun Microsystems - Beijing China 	uint32_t		eicr;		/* interrupt cause reg */
64913740cb2SPaul Guo 
6509da57d7bSbt 	uint32_t		ixgbe_state;
6519da57d7bSbt 	link_state_t		link_state;
6529da57d7bSbt 	uint32_t		link_speed;
6539da57d7bSbt 	uint32_t		link_duplex;
6559da57d7bSbt 	uint32_t		reset_count;
6569da57d7bSbt 	uint32_t		attach_progress;
6579da57d7bSbt 	uint32_t		loopback_mode;
6589da57d7bSbt 	uint32_t		default_mtu;
6599da57d7bSbt 	uint32_t		max_frame_size;
660dc0cb1cdSDale Ghent 	ixgbe_link_speed	speeds_supported;
662ea65739eSchenlu chen - Sun Microsystems - Beijing China 	uint32_t		rcb_pending;
663ea65739eSchenlu chen - Sun Microsystems - Beijing China 
6649da57d7bSbt 	/*
66573cd555cSBin Tu - Sun Microsystems - Beijing China 	 * Each msi-x vector: map vector to interrupt cleanup
6669da57d7bSbt 	 */
66773cd555cSBin Tu - Sun Microsystems - Beijing China 	ixgbe_intr_vector_t	vect_map[MAX_INTR_VECTOR];
6699da57d7bSbt 	/*
6709da57d7bSbt 	 * Receive Rings
6719da57d7bSbt 	 */
6729da57d7bSbt 	ixgbe_rx_ring_t		*rx_rings;	/* Array of rx rings */
6739da57d7bSbt 	uint32_t		num_rx_rings;	/* Number of rx rings in use */
6749da57d7bSbt 	uint32_t		rx_ring_size;	/* Rx descriptor ring size */
6759da57d7bSbt 	uint32_t		rx_buf_size;	/* Rx buffer size */
676ffd8e883SWinson Wang - Sun Microsystems - Beijing China 	boolean_t		lro_enable;	/* Large Receive Offload */
677ffd8e883SWinson Wang - Sun Microsystems - Beijing China 	uint64_t		lro_pkt_count;	/* LRO packet count */
678da14cebeSEric Cheng 	/*
679da14cebeSEric Cheng 	 * Receive Groups
680da14cebeSEric Cheng 	 */
681da14cebeSEric Cheng 	ixgbe_rx_group_t	*rx_groups;	/* Array of rx groups */
682da14cebeSEric Cheng 	uint32_t		num_rx_groups;	/* Number of rx groups in use */
68384de666eSRyan Zezeski 	uint32_t		rx_def_group;	/* Default Rx group index */
684da14cebeSEric Cheng 
6859da57d7bSbt 	/*
6869da57d7bSbt 	 * Transmit Rings
6879da57d7bSbt 	 */
6889da57d7bSbt 	ixgbe_tx_ring_t		*tx_rings;	/* Array of tx rings */
6899da57d7bSbt 	uint32_t		num_tx_rings;	/* Number of tx rings in use */
6909da57d7bSbt 	uint32_t		tx_ring_size;	/* Tx descriptor ring size */
6919da57d7bSbt 	uint32_t		tx_buf_size;	/* Tx buffer size */
693ea65739eSchenlu chen - Sun Microsystems - Beijing China 	boolean_t		tx_ring_init;
6949da57d7bSbt 	boolean_t		tx_head_wb_enable; /* Tx head wrtie-back */
6959da57d7bSbt 	boolean_t		tx_hcksum_enable; /* Tx h/w cksum offload */
696168e1ed4SRyan Zezeski 	boolean_t		lso_enable;	/* Large Segment Offload */
697168e1ed4SRyan Zezeski 	boolean_t		mr_enable;	/* Multiple Tx and Rx Ring */
6985b6dd21fSchenlu chen - Sun Microsystems - Beijing China 	boolean_t		relax_order_enable; /* Relax Order */
6990dc2366fSVenugopal Iyer 	uint32_t		classify_mode;	/* Classification mode */
7009da57d7bSbt 	uint32_t		tx_copy_thresh;	/* Tx copy threshold */
7019da57d7bSbt 	uint32_t		tx_recycle_thresh; /* Tx recycle threshold */
7029da57d7bSbt 	uint32_t		tx_overload_thresh; /* Tx overload threshold */
7039da57d7bSbt 	uint32_t		tx_resched_thresh; /* Tx reschedule threshold */
7049da57d7bSbt 	boolean_t		rx_hcksum_enable; /* Rx h/w cksum offload */
7059da57d7bSbt 	uint32_t		rx_copy_thresh; /* Rx copy threshold */
7069da57d7bSbt 	uint32_t		rx_limit_per_intr; /* Rx pkts per interrupt */
70773cd555cSBin Tu - Sun Microsystems - Beijing China 	uint32_t		intr_throttling[MAX_INTR_VECTOR];
7089da57d7bSbt 	uint32_t		intr_force;
7099da57d7bSbt 	int			fm_capabilities; /* FMA capabilities */
7119da57d7bSbt 	int			intr_type;
7129da57d7bSbt 	int			intr_cnt;
7130dc2366fSVenugopal Iyer 	uint32_t		intr_cnt_max;
7140dc2366fSVenugopal Iyer 	uint32_t		intr_cnt_min;
7159da57d7bSbt 	int			intr_cap;
7169da57d7bSbt 	size_t			intr_size;
7179da57d7bSbt 	uint_t			intr_pri;
7189da57d7bSbt 	ddi_intr_handle_t	*htable;
7199da57d7bSbt 	uint32_t		eims_mask;
7200dc2366fSVenugopal Iyer 	ddi_cb_handle_t		cb_hdl;		/* Interrupt callback handle */
7229da57d7bSbt 	kmutex_t		gen_lock; /* General lock for device access */
7239da57d7bSbt 	kmutex_t		watchdog_lock;
724ea65739eSchenlu chen - Sun Microsystems - Beijing China 	kmutex_t		rx_pending_lock;
7269da57d7bSbt 	boolean_t		watchdog_enable;
7279da57d7bSbt 	boolean_t		watchdog_start;
7289da57d7bSbt 	timeout_id_t		watchdog_tid;
7309da57d7bSbt 	boolean_t		unicst_init;
7319da57d7bSbt 	uint32_t		unicst_avail;
7329da57d7bSbt 	uint32_t		unicst_total;
7339da57d7bSbt 	ixgbe_ether_addr_t	unicst_addr[MAX_NUM_UNICAST_ADDRESSES];
7349da57d7bSbt 	uint32_t		mcast_count;
7359da57d7bSbt 	struct ether_addr	mcast_table[MAX_NUM_MULTICAST_ADDRESSES];
73784de666eSRyan Zezeski 	boolean_t		vlft_enabled; /* VLAN filtering enabled? */
73884de666eSRyan Zezeski 	boolean_t		vlft_init;    /* VLAN filtering initialized? */
73984de666eSRyan Zezeski 
740da14cebeSEric Cheng 	ulong_t			sys_page_size;
741da14cebeSEric Cheng 
74262e6e1adSPaul Guo 	boolean_t		link_check_complete;
74362e6e1adSPaul Guo 	hrtime_t		link_check_hrtime;
74462e6e1adSPaul Guo 	ddi_periodic_t		periodic_id; /* for link check timer func */
74562e6e1adSPaul Guo 
74637367bbaSRobert Mustacchi 	/*
74737367bbaSRobert Mustacchi 	 * LED related constants.
74837367bbaSRobert Mustacchi 	 */
74937367bbaSRobert Mustacchi 	boolean_t		ixgbe_led_active;
75037367bbaSRobert Mustacchi 	boolean_t		ixgbe_led_blink;
75137367bbaSRobert Mustacchi 	uint32_t		ixgbe_led_reg;
75237367bbaSRobert Mustacchi 	uint32_t		ixgbe_led_index;
75337367bbaSRobert Mustacchi 
754*f2fe7acaSRobert Mustacchi 	/*
755*f2fe7acaSRobert Mustacchi 	 * UFM state
756*f2fe7acaSRobert Mustacchi 	 */
757*f2fe7acaSRobert Mustacchi 	ddi_ufm_handle_t	*ixgbe_ufmh;
758*f2fe7acaSRobert Mustacchi 
7599da57d7bSbt 	/*
7609da57d7bSbt 	 * Kstat definitions
7619da57d7bSbt 	 */
7629da57d7bSbt 	kstat_t			*ixgbe_ks;
764ea65739eSchenlu chen - Sun Microsystems - Beijing China 	uint32_t		param_en_10000fdx_cap:1,
765dc0cb1cdSDale Ghent 				param_en_5000fdx_cap:1,
766dc0cb1cdSDale Ghent 				param_en_2500fdx_cap:1,
767ea65739eSchenlu chen - Sun Microsystems - Beijing China 				param_en_1000fdx_cap:1,
768ea65739eSchenlu chen - Sun Microsystems - Beijing China 				param_en_100fdx_cap:1,
769ea65739eSchenlu chen - Sun Microsystems - Beijing China 				param_adv_10000fdx_cap:1,
770dc0cb1cdSDale Ghent 				param_adv_5000fdx_cap:1,
771dc0cb1cdSDale Ghent 				param_adv_2500fdx_cap:1,