19da57d7bSbt /* 29da57d7bSbt * CDDL HEADER START 39da57d7bSbt * 473cd555cSBin Tu - Sun Microsystems - Beijing China * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 59da57d7bSbt * The contents of this file are subject to the terms of the 69da57d7bSbt * Common Development and Distribution License (the "License"). 79da57d7bSbt * You may not use this file except in compliance with the License. 89da57d7bSbt * 9da14cebeSEric Cheng * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10da14cebeSEric Cheng * or http://www.opensolaris.org/os/licensing. 119da57d7bSbt * See the License for the specific language governing permissions 129da57d7bSbt * and limitations under the License. 139da57d7bSbt * 14da14cebeSEric Cheng * When distributing Covered Code, include this CDDL HEADER in each 15da14cebeSEric Cheng * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 169da57d7bSbt * If applicable, add the following below this CDDL HEADER, with the 179da57d7bSbt * fields enclosed by brackets "[]" replaced with your own identifying 189da57d7bSbt * information: Portions Copyright [yyyy] [name of copyright owner] 199da57d7bSbt * 209da57d7bSbt * CDDL HEADER END 219da57d7bSbt */ 229da57d7bSbt 239da57d7bSbt /* 24*ffd8e883SWinson Wang - Sun Microsystems - Beijing China * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 25da14cebeSEric Cheng * Use is subject to license terms. 269da57d7bSbt */ 279da57d7bSbt 289da57d7bSbt #ifndef _IXGBE_SW_H 299da57d7bSbt #define _IXGBE_SW_H 309da57d7bSbt 319da57d7bSbt #ifdef __cplusplus 329da57d7bSbt extern "C" { 339da57d7bSbt #endif 349da57d7bSbt 359da57d7bSbt #include <sys/types.h> 369da57d7bSbt #include <sys/conf.h> 379da57d7bSbt #include <sys/debug.h> 389da57d7bSbt #include <sys/stropts.h> 399da57d7bSbt #include <sys/stream.h> 409da57d7bSbt #include <sys/strsun.h> 419da57d7bSbt #include <sys/strlog.h> 429da57d7bSbt #include <sys/kmem.h> 439da57d7bSbt #include <sys/stat.h> 449da57d7bSbt #include <sys/kstat.h> 459da57d7bSbt #include <sys/modctl.h> 469da57d7bSbt #include <sys/errno.h> 479da57d7bSbt #include <sys/dlpi.h> 48da14cebeSEric Cheng #include <sys/mac_provider.h> 499da57d7bSbt #include <sys/mac_ether.h> 509da57d7bSbt #include <sys/vlan.h> 519da57d7bSbt #include <sys/ddi.h> 529da57d7bSbt #include <sys/sunddi.h> 539da57d7bSbt #include <sys/pci.h> 549da57d7bSbt #include <sys/pcie.h> 559da57d7bSbt #include <sys/sdt.h> 569da57d7bSbt #include <sys/ethernet.h> 579da57d7bSbt #include <sys/pattr.h> 589da57d7bSbt #include <sys/strsubr.h> 599da57d7bSbt #include <sys/netlb.h> 609da57d7bSbt #include <sys/random.h> 619da57d7bSbt #include <inet/common.h> 62c971fb7eSgg #include <inet/tcp.h> 639da57d7bSbt #include <inet/ip.h> 649da57d7bSbt #include <inet/mi.h> 659da57d7bSbt #include <inet/nd.h> 669da57d7bSbt #include <sys/bitmap.h> 679da57d7bSbt #include <sys/ddifm.h> 689da57d7bSbt #include <sys/fm/protocol.h> 699da57d7bSbt #include <sys/fm/util.h> 7062e6e1adSPaul Guo #include <sys/disp.h> 719da57d7bSbt #include <sys/fm/io/ddi.h> 729da57d7bSbt #include "ixgbe_api.h" 739da57d7bSbt 749da57d7bSbt #define MODULE_NAME "ixgbe" /* module name */ 759da57d7bSbt 769da57d7bSbt #define IXGBE_FAILURE DDI_FAILURE 779da57d7bSbt 789da57d7bSbt #define IXGBE_UNKNOWN 0x00 799da57d7bSbt #define IXGBE_INITIALIZED 0x01 809da57d7bSbt #define IXGBE_STARTED 0x02 819da57d7bSbt #define IXGBE_SUSPENDED 0x04 8262e6e1adSPaul Guo #define IXGBE_STALL 0x08 8362e6e1adSPaul Guo #define IXGBE_ERROR 0x80 849da57d7bSbt 859da57d7bSbt #define MAX_NUM_UNICAST_ADDRESSES 0x10 869da57d7bSbt #define MAX_NUM_MULTICAST_ADDRESSES 0x1000 879da57d7bSbt #define IXGBE_INTR_NONE 0 889da57d7bSbt #define IXGBE_INTR_MSIX 1 899da57d7bSbt #define IXGBE_INTR_MSI 2 909da57d7bSbt #define IXGBE_INTR_LEGACY 3 919da57d7bSbt 92da14cebeSEric Cheng #define IXGBE_POLL_NULL -1 93da14cebeSEric Cheng 94c971fb7eSgg #define MAX_COOKIE 18 959da57d7bSbt #define MIN_NUM_TX_DESC 2 969da57d7bSbt 97edf70dc9SPaul Guo #define IXGBE_TX_DESC_LIMIT 32 /* tx desc limitation */ 98edf70dc9SPaul Guo 9973cd555cSBin Tu - Sun Microsystems - Beijing China #define IXGBE_ADAPTER_REGSET 1 /* map adapter registers */ 10073cd555cSBin Tu - Sun Microsystems - Beijing China 101ea65739eSchenlu chen - Sun Microsystems - Beijing China #define IXGBE_RX_STOPPED 0x1 102ea65739eSchenlu chen - Sun Microsystems - Beijing China 103*ffd8e883SWinson Wang - Sun Microsystems - Beijing China #define IXGBE_PKG_BUF_16k 16384 104*ffd8e883SWinson Wang - Sun Microsystems - Beijing China 1059da57d7bSbt /* 10673cd555cSBin Tu - Sun Microsystems - Beijing China * MAX_xx_QUEUE_NUM and MAX_INTR_VECTOR values need to be the maximum of all 10713740cb2SPaul Guo * supported silicon types. 1089da57d7bSbt */ 10973cd555cSBin Tu - Sun Microsystems - Beijing China #define MAX_TX_QUEUE_NUM 128 11073cd555cSBin Tu - Sun Microsystems - Beijing China #define MAX_RX_QUEUE_NUM 128 11173cd555cSBin Tu - Sun Microsystems - Beijing China #define MAX_INTR_VECTOR 64 1129da57d7bSbt 1139da57d7bSbt /* 11413740cb2SPaul Guo * Maximum values for user configurable parameters 1159da57d7bSbt */ 116da14cebeSEric Cheng #define MAX_RX_GROUP_NUM 1 1179da57d7bSbt #define MAX_TX_RING_SIZE 4096 1189da57d7bSbt #define MAX_RX_RING_SIZE 4096 1199da57d7bSbt 1209da57d7bSbt #define MAX_RX_LIMIT_PER_INTR 4096 1219da57d7bSbt 1229da57d7bSbt #define MAX_RX_COPY_THRESHOLD 9216 1239da57d7bSbt #define MAX_TX_COPY_THRESHOLD 9216 1249da57d7bSbt #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 1259da57d7bSbt #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 1269da57d7bSbt #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 1279da57d7bSbt 1289da57d7bSbt /* 1299da57d7bSbt * Minimum values for user configurable parameters 1309da57d7bSbt */ 131da14cebeSEric Cheng #define MIN_RX_GROUP_NUM 1 1329da57d7bSbt #define MIN_TX_RING_SIZE 64 1339da57d7bSbt #define MIN_RX_RING_SIZE 64 1349da57d7bSbt 1359da57d7bSbt #define MIN_MTU ETHERMIN 1369da57d7bSbt #define MIN_RX_LIMIT_PER_INTR 16 1379da57d7bSbt #define MIN_TX_COPY_THRESHOLD 0 1389da57d7bSbt #define MIN_RX_COPY_THRESHOLD 0 1399da57d7bSbt #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 1409da57d7bSbt #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 1419da57d7bSbt #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 1429da57d7bSbt 1439da57d7bSbt /* 1449da57d7bSbt * Default values for user configurable parameters 1459da57d7bSbt */ 146da14cebeSEric Cheng #define DEFAULT_RX_GROUP_NUM 1 147da14cebeSEric Cheng #define DEFAULT_TX_RING_SIZE 1024 148da14cebeSEric Cheng #define DEFAULT_RX_RING_SIZE 1024 1499da57d7bSbt 1509da57d7bSbt #define DEFAULT_MTU ETHERMTU 1519da57d7bSbt #define DEFAULT_RX_LIMIT_PER_INTR 256 1529da57d7bSbt #define DEFAULT_RX_COPY_THRESHOLD 128 1539da57d7bSbt #define DEFAULT_TX_COPY_THRESHOLD 512 154da14cebeSEric Cheng #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1) 1559da57d7bSbt #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 1569da57d7bSbt #define DEFAULT_TX_RESCHED_THRESHOLD 128 1579da57d7bSbt #define DEFAULT_FCRTH 0x20000 1589da57d7bSbt #define DEFAULT_FCRTL 0x10000 1599da57d7bSbt #define DEFAULT_FCPAUSE 0xFFFF 1609da57d7bSbt 161da14cebeSEric Cheng #define DEFAULT_TX_HCKSUM_ENABLE B_TRUE 162da14cebeSEric Cheng #define DEFAULT_RX_HCKSUM_ENABLE B_TRUE 163da14cebeSEric Cheng #define DEFAULT_LSO_ENABLE B_TRUE 164*ffd8e883SWinson Wang - Sun Microsystems - Beijing China #define DEFAULT_LRO_ENABLE B_FALSE 165da14cebeSEric Cheng #define DEFAULT_MR_ENABLE B_TRUE 166da14cebeSEric Cheng #define DEFAULT_TX_HEAD_WB_ENABLE B_TRUE 167da14cebeSEric Cheng 168da14cebeSEric Cheng #define IXGBE_LSO_MAXLEN 65535 169da14cebeSEric Cheng 1709da57d7bSbt #define TX_DRAIN_TIME 200 1719da57d7bSbt #define RX_DRAIN_TIME 200 1729da57d7bSbt 1739da57d7bSbt #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 1749da57d7bSbt #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */ 1759da57d7bSbt 17662e6e1adSPaul Guo #define IXGBE_CYCLIC_PERIOD (1000000000) /* 1s */ 17762e6e1adSPaul Guo 1789da57d7bSbt /* 1799da57d7bSbt * Extra register bit masks for 82598 1809da57d7bSbt */ 1819da57d7bSbt #define IXGBE_PCS1GANA_FDC 0x20 1829da57d7bSbt #define IXGBE_PCS1GANLP_LPFD 0x20 1839da57d7bSbt #define IXGBE_PCS1GANLP_LPHD 0x40 1849da57d7bSbt 1859da57d7bSbt /* 1869da57d7bSbt * Defined for IP header alignment. 1879da57d7bSbt */ 1889da57d7bSbt #define IPHDR_ALIGN_ROOM 2 1899da57d7bSbt 1909da57d7bSbt /* 1919da57d7bSbt * Bit flags for attach_progress 1929da57d7bSbt */ 1939da57d7bSbt #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 1949da57d7bSbt #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 1959da57d7bSbt #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 1969da57d7bSbt #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 1979da57d7bSbt #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 1989da57d7bSbt #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 1999da57d7bSbt #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 2009da57d7bSbt #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */ 2019da57d7bSbt #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 2029da57d7bSbt #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 2039da57d7bSbt #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 2049da57d7bSbt #define ATTACH_PROGRESS_FM_INIT 0x2000 /* FMA initialized */ 20562e6e1adSPaul Guo #define ATTACH_PROGRESS_SFP_TASKQ 0x4000 /* SFP taskq created */ 20662e6e1adSPaul Guo #define ATTACH_PROGRESS_LINK_TIMER 0x8000 /* link check timer */ 2079da57d7bSbt 2089da57d7bSbt #define PROP_DEFAULT_MTU "default_mtu" 2099da57d7bSbt #define PROP_FLOW_CONTROL "flow_control" 2109da57d7bSbt #define PROP_TX_QUEUE_NUM "tx_queue_number" 2119da57d7bSbt #define PROP_TX_RING_SIZE "tx_ring_size" 2129da57d7bSbt #define PROP_RX_QUEUE_NUM "rx_queue_number" 2139da57d7bSbt #define PROP_RX_RING_SIZE "rx_ring_size" 214da14cebeSEric Cheng #define PROP_RX_GROUP_NUM "rx_group_number" 2159da57d7bSbt 2169da57d7bSbt #define PROP_INTR_FORCE "intr_force" 2179da57d7bSbt #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 2189da57d7bSbt #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 2199da57d7bSbt #define PROP_LSO_ENABLE "lso_enable" 220*ffd8e883SWinson Wang - Sun Microsystems - Beijing China #define PROP_LRO_ENABLE "lro_enable" 221da14cebeSEric Cheng #define PROP_MR_ENABLE "mr_enable" 2229da57d7bSbt #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 2239da57d7bSbt #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 2249da57d7bSbt #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 2259da57d7bSbt #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 2269da57d7bSbt #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 2279da57d7bSbt #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 2289da57d7bSbt #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 2299da57d7bSbt #define PROP_INTR_THROTTLING "intr_throttling" 2309da57d7bSbt #define PROP_FM_CAPABLE "fm_capable" 2319da57d7bSbt 2329da57d7bSbt #define IXGBE_LB_NONE 0 2339da57d7bSbt #define IXGBE_LB_EXTERNAL 1 2349da57d7bSbt #define IXGBE_LB_INTERNAL_MAC 2 2359da57d7bSbt #define IXGBE_LB_INTERNAL_PHY 3 2369da57d7bSbt #define IXGBE_LB_INTERNAL_SERDES 4 2379da57d7bSbt 23813740cb2SPaul Guo /* 23913740cb2SPaul Guo * capability/feature flags 24013740cb2SPaul Guo * Flags named _CAPABLE are set when the NIC hardware is capable of the feature. 24113740cb2SPaul Guo * Separately, the flag named _ENABLED is set when the feature is enabled. 24213740cb2SPaul Guo */ 24313740cb2SPaul Guo #define IXGBE_FLAG_DCA_ENABLED (u32)(1) 24413740cb2SPaul Guo #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 1) 24513740cb2SPaul Guo #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 2) 24613740cb2SPaul Guo #define IXGBE_FLAG_DCB_CAPABLE (u32)(1 << 4) 24713740cb2SPaul Guo #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 4) 24813740cb2SPaul Guo #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 5) 24913740cb2SPaul Guo #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 6) 25013740cb2SPaul Guo #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 7) 25113740cb2SPaul Guo #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 8) 252*ffd8e883SWinson Wang - Sun Microsystems - Beijing China #define IXGBE_FLAG_RSC_CAPABLE (u32)(1 << 9) 25313740cb2SPaul Guo 25413740cb2SPaul Guo /* adapter-specific info for each supported device type */ 25513740cb2SPaul Guo typedef struct adapter_info { 25613740cb2SPaul Guo uint32_t max_rx_que_num; /* maximum number of rx queues */ 25713740cb2SPaul Guo uint32_t min_rx_que_num; /* minimum number of rx queues */ 25813740cb2SPaul Guo uint32_t def_rx_que_num; /* default number of rx queues */ 25913740cb2SPaul Guo uint32_t max_tx_que_num; /* maximum number of tx queues */ 26013740cb2SPaul Guo uint32_t min_tx_que_num; /* minimum number of tx queues */ 26113740cb2SPaul Guo uint32_t def_tx_que_num; /* default number of tx queues */ 2621fedc51fSWinson Wang - Sun Microsystems - Beijing China uint32_t max_mtu; /* maximum MTU size */ 263ea65739eSchenlu chen - Sun Microsystems - Beijing China /* 264ea65739eSchenlu chen - Sun Microsystems - Beijing China * Interrupt throttling is in unit of 256 nsec 265ea65739eSchenlu chen - Sun Microsystems - Beijing China */ 266ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t max_intr_throttle; /* maximum interrupt throttle */ 267ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t min_intr_throttle; /* minimum interrupt throttle */ 268ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t def_intr_throttle; /* default interrupt throttle */ 269ea65739eSchenlu chen - Sun Microsystems - Beijing China 27013740cb2SPaul Guo uint32_t max_msix_vect; /* maximum total msix vectors */ 27113740cb2SPaul Guo uint32_t max_ring_vect; /* maximum number of ring vectors */ 27213740cb2SPaul Guo uint32_t max_other_vect; /* maximum number of other vectors */ 27313740cb2SPaul Guo uint32_t other_intr; /* "other" interrupt types handled */ 27413740cb2SPaul Guo uint32_t flags; /* capability flags */ 27513740cb2SPaul Guo } adapter_info_t; 27613740cb2SPaul Guo 27713740cb2SPaul Guo /* bits representing all interrupt types other than tx & rx */ 27813740cb2SPaul Guo #define IXGBE_OTHER_INTR 0x3ff00000 27973cd555cSBin Tu - Sun Microsystems - Beijing China #define IXGBE_82599_OTHER_INTR 0x86100000 28013740cb2SPaul Guo 2819da57d7bSbt enum ioc_reply { 2829da57d7bSbt IOC_INVAL = -1, /* bad, NAK with EINVAL */ 2839da57d7bSbt IOC_DONE, /* OK, reply sent */ 2849da57d7bSbt IOC_ACK, /* OK, just send ACK */ 2859da57d7bSbt IOC_REPLY /* OK, just send reply */ 2869da57d7bSbt }; 2879da57d7bSbt 2889da57d7bSbt #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 2899da57d7bSbt 0, 0, (flag))) 2909da57d7bSbt 2919da57d7bSbt /* 2929da57d7bSbt * Defined for ring index operations 2939da57d7bSbt * ASSERT(index < limit) 2949da57d7bSbt * ASSERT(step < limit) 2959da57d7bSbt * ASSERT(index1 < limit) 2969da57d7bSbt * ASSERT(index2 < limit) 2979da57d7bSbt */ 2989da57d7bSbt #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 2999da57d7bSbt (index) + (step) : (index) + (step) - (limit)) 3009da57d7bSbt #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 3019da57d7bSbt (index) - (step) : (index) + (limit) - (step)) 3029da57d7bSbt #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 3039da57d7bSbt (index2) - (index1) : (index2) + (limit) - (index1)) 3049da57d7bSbt 3059da57d7bSbt #define LINK_LIST_INIT(_LH) \ 3069da57d7bSbt (_LH)->head = (_LH)->tail = NULL 3079da57d7bSbt 3089da57d7bSbt #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 3099da57d7bSbt 3109da57d7bSbt #define LIST_POP_HEAD(_LH) \ 3119da57d7bSbt (single_link_t *)(_LH)->head; \ 3129da57d7bSbt { \ 3139da57d7bSbt if ((_LH)->head != NULL) { \ 3149da57d7bSbt (_LH)->head = (_LH)->head->link; \ 3159da57d7bSbt if ((_LH)->head == NULL) \ 3169da57d7bSbt (_LH)->tail = NULL; \ 3179da57d7bSbt } \ 3189da57d7bSbt } 3199da57d7bSbt 3209da57d7bSbt #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 3219da57d7bSbt 3229da57d7bSbt #define LIST_PUSH_TAIL(_LH, _E) \ 3239da57d7bSbt if ((_LH)->tail != NULL) { \ 3249da57d7bSbt (_LH)->tail->link = (single_link_t *)(_E); \ 3259da57d7bSbt (_LH)->tail = (single_link_t *)(_E); \ 3269da57d7bSbt } else { \ 3279da57d7bSbt (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 3289da57d7bSbt } \ 3299da57d7bSbt (_E)->link = NULL; 3309da57d7bSbt 3319da57d7bSbt #define LIST_GET_NEXT(_LH, _E) \ 3329da57d7bSbt (((_LH)->tail == (single_link_t *)(_E)) ? \ 3339da57d7bSbt NULL : ((single_link_t *)(_E))->link) 3349da57d7bSbt 3359da57d7bSbt 3369da57d7bSbt typedef struct single_link { 3379da57d7bSbt struct single_link *link; 3389da57d7bSbt } single_link_t; 3399da57d7bSbt 3409da57d7bSbt typedef struct link_list { 3419da57d7bSbt single_link_t *head; 3429da57d7bSbt single_link_t *tail; 3439da57d7bSbt } link_list_t; 3449da57d7bSbt 3459da57d7bSbt /* 3469da57d7bSbt * Property lookups 3479da57d7bSbt */ 3489da57d7bSbt #define IXGBE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 3499da57d7bSbt DDI_PROP_DONTPASS, (n)) 3509da57d7bSbt #define IXGBE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 3519da57d7bSbt DDI_PROP_DONTPASS, (n), -1) 3529da57d7bSbt 3539da57d7bSbt 3549da57d7bSbt typedef union ixgbe_ether_addr { 3559da57d7bSbt struct { 3569da57d7bSbt uint32_t high; 3579da57d7bSbt uint32_t low; 3589da57d7bSbt } reg; 3599da57d7bSbt struct { 3609da57d7bSbt uint8_t set; 3619da57d7bSbt uint8_t redundant; 3629da57d7bSbt uint8_t addr[ETHERADDRL]; 3639da57d7bSbt } mac; 3649da57d7bSbt } ixgbe_ether_addr_t; 3659da57d7bSbt 3669da57d7bSbt typedef enum { 3679da57d7bSbt USE_NONE, 3689da57d7bSbt USE_COPY, 3699da57d7bSbt USE_DMA 3709da57d7bSbt } tx_type_t; 3719da57d7bSbt 372c971fb7eSgg typedef struct ixgbe_tx_context { 3739da57d7bSbt uint32_t hcksum_flags; 3749da57d7bSbt uint32_t ip_hdr_len; 3759da57d7bSbt uint32_t mac_hdr_len; 3769da57d7bSbt uint32_t l4_proto; 377c971fb7eSgg uint32_t mss; 378c971fb7eSgg uint32_t l4_hdr_len; 379c971fb7eSgg boolean_t lso_flag; 380c971fb7eSgg } ixgbe_tx_context_t; 3819da57d7bSbt 3829da57d7bSbt /* 3839da57d7bSbt * Hold address/length of each DMA segment 3849da57d7bSbt */ 3859da57d7bSbt typedef struct sw_desc { 3869da57d7bSbt uint64_t address; 3879da57d7bSbt size_t length; 3889da57d7bSbt } sw_desc_t; 3899da57d7bSbt 3909da57d7bSbt /* 3919da57d7bSbt * Handles and addresses of DMA buffer 3929da57d7bSbt */ 3939da57d7bSbt typedef struct dma_buffer { 3949da57d7bSbt caddr_t address; /* Virtual address */ 3959da57d7bSbt uint64_t dma_address; /* DMA (Hardware) address */ 3969da57d7bSbt ddi_acc_handle_t acc_handle; /* Data access handle */ 3979da57d7bSbt ddi_dma_handle_t dma_handle; /* DMA handle */ 3989da57d7bSbt size_t size; /* Buffer size */ 3999da57d7bSbt size_t len; /* Data length in the buffer */ 4009da57d7bSbt } dma_buffer_t; 4019da57d7bSbt 4029da57d7bSbt /* 4039da57d7bSbt * Tx Control Block 4049da57d7bSbt */ 4059da57d7bSbt typedef struct tx_control_block { 4069da57d7bSbt single_link_t link; 407edf70dc9SPaul Guo uint32_t last_index; /* last descriptor of the pkt */ 4089da57d7bSbt uint32_t frag_num; 4099da57d7bSbt uint32_t desc_num; 4109da57d7bSbt mblk_t *mp; 4119da57d7bSbt tx_type_t tx_type; 4129da57d7bSbt ddi_dma_handle_t tx_dma_handle; 4139da57d7bSbt dma_buffer_t tx_buf; 4149da57d7bSbt sw_desc_t desc[MAX_COOKIE]; 4159da57d7bSbt } tx_control_block_t; 4169da57d7bSbt 4179da57d7bSbt /* 4189da57d7bSbt * RX Control Block 4199da57d7bSbt */ 4209da57d7bSbt typedef struct rx_control_block { 4219da57d7bSbt mblk_t *mp; 422ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t ref_cnt; 4239da57d7bSbt dma_buffer_t rx_buf; 4249da57d7bSbt frtn_t free_rtn; 425ea65739eSchenlu chen - Sun Microsystems - Beijing China struct ixgbe_rx_data *rx_data; 426*ffd8e883SWinson Wang - Sun Microsystems - Beijing China int lro_next; /* Index of next rcb */ 427*ffd8e883SWinson Wang - Sun Microsystems - Beijing China int lro_prev; /* Index of previous rcb */ 428*ffd8e883SWinson Wang - Sun Microsystems - Beijing China boolean_t lro_pkt; /* Flag for LRO rcb */ 4299da57d7bSbt } rx_control_block_t; 4309da57d7bSbt 4319da57d7bSbt /* 4329da57d7bSbt * Software Data Structure for Tx Ring 4339da57d7bSbt */ 4349da57d7bSbt typedef struct ixgbe_tx_ring { 4359da57d7bSbt uint32_t index; /* Ring index */ 4369da57d7bSbt uint32_t intr_vector; /* Interrupt vector index */ 4379da57d7bSbt uint32_t vect_bit; /* vector's bit in register */ 4389da57d7bSbt 4399da57d7bSbt /* 4409da57d7bSbt * Mutexes 4419da57d7bSbt */ 4429da57d7bSbt kmutex_t tx_lock; 4439da57d7bSbt kmutex_t recycle_lock; 4449da57d7bSbt kmutex_t tcb_head_lock; 4459da57d7bSbt kmutex_t tcb_tail_lock; 4469da57d7bSbt 4479da57d7bSbt /* 4489da57d7bSbt * Tx descriptor ring definitions 4499da57d7bSbt */ 4509da57d7bSbt dma_buffer_t tbd_area; 4519da57d7bSbt union ixgbe_adv_tx_desc *tbd_ring; 4529da57d7bSbt uint32_t tbd_head; /* Index of next tbd to recycle */ 4539da57d7bSbt uint32_t tbd_tail; /* Index of next tbd to transmit */ 4549da57d7bSbt uint32_t tbd_free; /* Number of free tbd */ 4559da57d7bSbt 4569da57d7bSbt /* 4579da57d7bSbt * Tx control block list definitions 4589da57d7bSbt */ 4599da57d7bSbt tx_control_block_t *tcb_area; 4609da57d7bSbt tx_control_block_t **work_list; 4619da57d7bSbt tx_control_block_t **free_list; 4629da57d7bSbt uint32_t tcb_head; /* Head index of free list */ 4639da57d7bSbt uint32_t tcb_tail; /* Tail index of free list */ 4649da57d7bSbt uint32_t tcb_free; /* Number of free tcb in free list */ 4659da57d7bSbt 4669da57d7bSbt uint32_t *tbd_head_wb; /* Head write-back */ 4679da57d7bSbt uint32_t (*tx_recycle)(struct ixgbe_tx_ring *); 4689da57d7bSbt 4699da57d7bSbt /* 470c971fb7eSgg * s/w context structure for TCP/UDP checksum offload 471c971fb7eSgg * and LSO. 4729da57d7bSbt */ 473c971fb7eSgg ixgbe_tx_context_t tx_context; 4749da57d7bSbt 4759da57d7bSbt /* 4769da57d7bSbt * Tx ring settings and status 4779da57d7bSbt */ 4789da57d7bSbt uint32_t ring_size; /* Tx descriptor ring size */ 4799da57d7bSbt uint32_t free_list_size; /* Tx free list size */ 4809da57d7bSbt 4819da57d7bSbt boolean_t reschedule; 4829da57d7bSbt uint32_t recycle_fail; 4839da57d7bSbt uint32_t stall_watchdog; 4849da57d7bSbt 4859da57d7bSbt #ifdef IXGBE_DEBUG 4869da57d7bSbt /* 4879da57d7bSbt * Debug statistics 4889da57d7bSbt */ 4899da57d7bSbt uint32_t stat_overload; 4909da57d7bSbt uint32_t stat_fail_no_tbd; 4919da57d7bSbt uint32_t stat_fail_no_tcb; 4929da57d7bSbt uint32_t stat_fail_dma_bind; 4939da57d7bSbt uint32_t stat_reschedule; 494edf70dc9SPaul Guo uint32_t stat_break_tbd_limit; 495da14cebeSEric Cheng uint32_t stat_lso_header_fail; 4969da57d7bSbt #endif 4979da57d7bSbt 498da14cebeSEric Cheng mac_ring_handle_t ring_handle; 499da14cebeSEric Cheng 5009da57d7bSbt /* 5019da57d7bSbt * Pointer to the ixgbe struct 5029da57d7bSbt */ 5039da57d7bSbt struct ixgbe *ixgbe; 5049da57d7bSbt } ixgbe_tx_ring_t; 5059da57d7bSbt 5069da57d7bSbt /* 5079da57d7bSbt * Software Receive Ring 5089da57d7bSbt */ 509ea65739eSchenlu chen - Sun Microsystems - Beijing China typedef struct ixgbe_rx_data { 5109da57d7bSbt kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 5119da57d7bSbt 5129da57d7bSbt /* 5139da57d7bSbt * Rx descriptor ring definitions 5149da57d7bSbt */ 5159da57d7bSbt dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 5169da57d7bSbt union ixgbe_adv_rx_desc *rbd_ring; /* Rx desc ring */ 5179da57d7bSbt uint32_t rbd_next; /* Index of next rx desc */ 5189da57d7bSbt 5199da57d7bSbt /* 5209da57d7bSbt * Rx control block list definitions 5219da57d7bSbt */ 5229da57d7bSbt rx_control_block_t *rcb_area; 5239da57d7bSbt rx_control_block_t **work_list; /* Work list of rcbs */ 5249da57d7bSbt rx_control_block_t **free_list; /* Free list of rcbs */ 5259da57d7bSbt uint32_t rcb_head; /* Index of next free rcb */ 5269da57d7bSbt uint32_t rcb_tail; /* Index to put recycled rcb */ 5279da57d7bSbt uint32_t rcb_free; /* Number of free rcbs */ 5289da57d7bSbt 5299da57d7bSbt /* 530ea65739eSchenlu chen - Sun Microsystems - Beijing China * Rx sw ring settings and status 5319da57d7bSbt */ 5329da57d7bSbt uint32_t ring_size; /* Rx descriptor ring size */ 5339da57d7bSbt uint32_t free_list_size; /* Rx free list size */ 534ea65739eSchenlu chen - Sun Microsystems - Beijing China 535ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t rcb_pending; 536ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t flag; 537ea65739eSchenlu chen - Sun Microsystems - Beijing China 538*ffd8e883SWinson Wang - Sun Microsystems - Beijing China uint32_t lro_num; /* Number of rcbs of one LRO */ 539*ffd8e883SWinson Wang - Sun Microsystems - Beijing China uint32_t lro_first; /* Index of first LRO rcb */ 540*ffd8e883SWinson Wang - Sun Microsystems - Beijing China 541ea65739eSchenlu chen - Sun Microsystems - Beijing China struct ixgbe_rx_ring *rx_ring; /* Pointer to rx ring */ 542ea65739eSchenlu chen - Sun Microsystems - Beijing China } ixgbe_rx_data_t; 543ea65739eSchenlu chen - Sun Microsystems - Beijing China 544ea65739eSchenlu chen - Sun Microsystems - Beijing China /* 545ea65739eSchenlu chen - Sun Microsystems - Beijing China * Software Data Structure for Rx Ring 546ea65739eSchenlu chen - Sun Microsystems - Beijing China */ 547ea65739eSchenlu chen - Sun Microsystems - Beijing China typedef struct ixgbe_rx_ring { 548ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t index; /* Ring index */ 549ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t intr_vector; /* Interrupt vector index */ 550ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t vect_bit; /* vector's bit in register */ 551ea65739eSchenlu chen - Sun Microsystems - Beijing China 552ea65739eSchenlu chen - Sun Microsystems - Beijing China ixgbe_rx_data_t *rx_data; /* Rx software ring */ 553ea65739eSchenlu chen - Sun Microsystems - Beijing China 554ea65739eSchenlu chen - Sun Microsystems - Beijing China kmutex_t rx_lock; /* Rx access lock */ 5559da57d7bSbt 5569da57d7bSbt #ifdef IXGBE_DEBUG 5579da57d7bSbt /* 5589da57d7bSbt * Debug statistics 5599da57d7bSbt */ 5609da57d7bSbt uint32_t stat_frame_error; 5619da57d7bSbt uint32_t stat_cksum_error; 5629da57d7bSbt uint32_t stat_exceed_pkt; 5639da57d7bSbt #endif 5649da57d7bSbt 565da14cebeSEric Cheng mac_ring_handle_t ring_handle; 566da14cebeSEric Cheng uint64_t ring_gen_num; 5679da57d7bSbt 568da14cebeSEric Cheng struct ixgbe *ixgbe; /* Pointer to ixgbe struct */ 5699da57d7bSbt } ixgbe_rx_ring_t; 570da14cebeSEric Cheng /* 571da14cebeSEric Cheng * Software Receive Ring Group 572da14cebeSEric Cheng */ 573da14cebeSEric Cheng typedef struct ixgbe_rx_group { 574da14cebeSEric Cheng uint32_t index; /* Group index */ 575da14cebeSEric Cheng mac_group_handle_t group_handle; /* call back group handle */ 576da14cebeSEric Cheng struct ixgbe *ixgbe; /* Pointer to ixgbe struct */ 577da14cebeSEric Cheng } ixgbe_rx_group_t; 578da14cebeSEric Cheng 5799da57d7bSbt /* 58073cd555cSBin Tu - Sun Microsystems - Beijing China * structure to map interrupt cleanup to msi-x vector 5819da57d7bSbt */ 58273cd555cSBin Tu - Sun Microsystems - Beijing China typedef struct ixgbe_intr_vector { 5839da57d7bSbt struct ixgbe *ixgbe; /* point to my adapter */ 5849da57d7bSbt ulong_t rx_map[BT_BITOUL(MAX_RX_QUEUE_NUM)]; /* bitmap of rx rings */ 5859da57d7bSbt int rxr_cnt; /* count rx rings */ 5869da57d7bSbt ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)]; /* bitmap of tx rings */ 5879da57d7bSbt int txr_cnt; /* count tx rings */ 58873cd555cSBin Tu - Sun Microsystems - Beijing China ulong_t other_map[BT_BITOUL(2)]; /* bitmap of other */ 58973cd555cSBin Tu - Sun Microsystems - Beijing China int other_cnt; /* count other interrupt */ 59073cd555cSBin Tu - Sun Microsystems - Beijing China } ixgbe_intr_vector_t; 5919da57d7bSbt 5929da57d7bSbt /* 5939da57d7bSbt * Software adapter state 5949da57d7bSbt */ 5959da57d7bSbt typedef struct ixgbe { 5969da57d7bSbt int instance; 5979da57d7bSbt mac_handle_t mac_hdl; 5989da57d7bSbt dev_info_t *dip; 5999da57d7bSbt struct ixgbe_hw hw; 6009da57d7bSbt struct ixgbe_osdep osdep; 6019da57d7bSbt 60213740cb2SPaul Guo adapter_info_t *capab; /* adapter hardware capabilities */ 60362e6e1adSPaul Guo ddi_taskq_t *sfp_taskq; /* sfp-change taskq */ 60413740cb2SPaul Guo uint32_t eims; /* interrupt mask setting */ 60573cd555cSBin Tu - Sun Microsystems - Beijing China uint32_t eimc; /* interrupt mask clear */ 60673cd555cSBin Tu - Sun Microsystems - Beijing China uint32_t eicr; /* interrupt cause reg */ 60713740cb2SPaul Guo 6089da57d7bSbt uint32_t ixgbe_state; 6099da57d7bSbt link_state_t link_state; 6109da57d7bSbt uint32_t link_speed; 6119da57d7bSbt uint32_t link_duplex; 6129da57d7bSbt 6139da57d7bSbt uint32_t reset_count; 6149da57d7bSbt uint32_t attach_progress; 6159da57d7bSbt uint32_t loopback_mode; 6169da57d7bSbt uint32_t default_mtu; 6179da57d7bSbt uint32_t max_frame_size; 6189da57d7bSbt 619ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t rcb_pending; 620ea65739eSchenlu chen - Sun Microsystems - Beijing China 6219da57d7bSbt /* 62273cd555cSBin Tu - Sun Microsystems - Beijing China * Each msi-x vector: map vector to interrupt cleanup 6239da57d7bSbt */ 62473cd555cSBin Tu - Sun Microsystems - Beijing China ixgbe_intr_vector_t vect_map[MAX_INTR_VECTOR]; 6259da57d7bSbt 6269da57d7bSbt /* 6279da57d7bSbt * Receive Rings 6289da57d7bSbt */ 6299da57d7bSbt ixgbe_rx_ring_t *rx_rings; /* Array of rx rings */ 6309da57d7bSbt uint32_t num_rx_rings; /* Number of rx rings in use */ 6319da57d7bSbt uint32_t rx_ring_size; /* Rx descriptor ring size */ 6329da57d7bSbt uint32_t rx_buf_size; /* Rx buffer size */ 633*ffd8e883SWinson Wang - Sun Microsystems - Beijing China boolean_t lro_enable; /* Large Receive Offload */ 634*ffd8e883SWinson Wang - Sun Microsystems - Beijing China uint64_t lro_pkt_count; /* LRO packet count */ 635da14cebeSEric Cheng /* 636da14cebeSEric Cheng * Receive Groups 637da14cebeSEric Cheng */ 638da14cebeSEric Cheng ixgbe_rx_group_t *rx_groups; /* Array of rx groups */ 639da14cebeSEric Cheng uint32_t num_rx_groups; /* Number of rx groups in use */ 640da14cebeSEric Cheng 6419da57d7bSbt /* 6429da57d7bSbt * Transmit Rings 6439da57d7bSbt */ 6449da57d7bSbt ixgbe_tx_ring_t *tx_rings; /* Array of tx rings */ 6459da57d7bSbt uint32_t num_tx_rings; /* Number of tx rings in use */ 6469da57d7bSbt uint32_t tx_ring_size; /* Tx descriptor ring size */ 6479da57d7bSbt uint32_t tx_buf_size; /* Tx buffer size */ 6489da57d7bSbt 649ea65739eSchenlu chen - Sun Microsystems - Beijing China boolean_t tx_ring_init; 6509da57d7bSbt boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 6519da57d7bSbt boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 6529da57d7bSbt boolean_t lso_enable; /* Large Segment Offload */ 653da14cebeSEric Cheng boolean_t mr_enable; /* Multiple Tx and Rx Ring */ 6549da57d7bSbt uint32_t tx_copy_thresh; /* Tx copy threshold */ 6559da57d7bSbt uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 6569da57d7bSbt uint32_t tx_overload_thresh; /* Tx overload threshold */ 6579da57d7bSbt uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 6589da57d7bSbt boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 6599da57d7bSbt uint32_t rx_copy_thresh; /* Rx copy threshold */ 6609da57d7bSbt uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 66173cd555cSBin Tu - Sun Microsystems - Beijing China uint32_t intr_throttling[MAX_INTR_VECTOR]; 6629da57d7bSbt uint32_t intr_force; 6639da57d7bSbt int fm_capabilities; /* FMA capabilities */ 6649da57d7bSbt 6659da57d7bSbt int intr_type; 6669da57d7bSbt int intr_cnt; 6679da57d7bSbt int intr_cap; 6689da57d7bSbt size_t intr_size; 6699da57d7bSbt uint_t intr_pri; 6709da57d7bSbt ddi_intr_handle_t *htable; 6719da57d7bSbt uint32_t eims_mask; 6729da57d7bSbt 6739da57d7bSbt kmutex_t gen_lock; /* General lock for device access */ 6749da57d7bSbt kmutex_t watchdog_lock; 675ea65739eSchenlu chen - Sun Microsystems - Beijing China kmutex_t rx_pending_lock; 6769da57d7bSbt 6779da57d7bSbt boolean_t watchdog_enable; 6789da57d7bSbt boolean_t watchdog_start; 6799da57d7bSbt timeout_id_t watchdog_tid; 6809da57d7bSbt 6819da57d7bSbt boolean_t unicst_init; 6829da57d7bSbt uint32_t unicst_avail; 6839da57d7bSbt uint32_t unicst_total; 6849da57d7bSbt ixgbe_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 6859da57d7bSbt uint32_t mcast_count; 6869da57d7bSbt struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 6879da57d7bSbt 688da14cebeSEric Cheng ulong_t sys_page_size; 689da14cebeSEric Cheng 69062e6e1adSPaul Guo boolean_t link_check_complete; 69162e6e1adSPaul Guo hrtime_t link_check_hrtime; 69262e6e1adSPaul Guo ddi_periodic_t periodic_id; /* for link check timer func */ 69362e6e1adSPaul Guo 6949da57d7bSbt /* 6959da57d7bSbt * Kstat definitions 6969da57d7bSbt */ 6979da57d7bSbt kstat_t *ixgbe_ks; 6989da57d7bSbt 699ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t param_en_10000fdx_cap:1, 700ea65739eSchenlu chen - Sun Microsystems - Beijing China param_en_1000fdx_cap:1, 701ea65739eSchenlu chen - Sun Microsystems - Beijing China param_en_100fdx_cap:1, 702ea65739eSchenlu chen - Sun Microsystems - Beijing China param_adv_10000fdx_cap:1, 703ea65739eSchenlu chen - Sun Microsystems - Beijing China param_adv_1000fdx_cap:1, 704ea65739eSchenlu chen - Sun Microsystems - Beijing China param_adv_100fdx_cap:1, 705ea65739eSchenlu chen - Sun Microsystems - Beijing China param_pause_cap:1, 706ea65739eSchenlu chen - Sun Microsystems - Beijing China param_asym_pause_cap:1, 707ea65739eSchenlu chen - Sun Microsystems - Beijing China param_rem_fault:1, 708ea65739eSchenlu chen - Sun Microsystems - Beijing China param_adv_autoneg_cap:1, 709ea65739eSchenlu chen - Sun Microsystems - Beijing China param_adv_pause_cap:1, 710ea65739eSchenlu chen - Sun Microsystems - Beijing China param_adv_asym_pause_cap:1, 711ea65739eSchenlu chen - Sun Microsystems - Beijing China param_adv_rem_fault:1, 712ea65739eSchenlu chen - Sun Microsystems - Beijing China param_lp_10000fdx_cap:1, 713ea65739eSchenlu chen - Sun Microsystems - Beijing China param_lp_1000fdx_cap:1, 714ea65739eSchenlu chen - Sun Microsystems - Beijing China param_lp_100fdx_cap:1, 715ea65739eSchenlu chen - Sun Microsystems - Beijing China param_lp_autoneg_cap:1, 716ea65739eSchenlu chen - Sun Microsystems - Beijing China param_lp_pause_cap:1, 717ea65739eSchenlu chen - Sun Microsystems - Beijing China param_lp_asym_pause_cap:1, 7181fedc51fSWinson Wang - Sun Microsystems - Beijing China param_lp_rem_fault:1, 719ea65739eSchenlu chen - Sun Microsystems - Beijing China param_pad_to_32:12; 7209da57d7bSbt } ixgbe_t; 7219da57d7bSbt 7229da57d7bSbt typedef struct ixgbe_stat { 7239da57d7bSbt kstat_named_t link_speed; /* Link Speed */ 724da14cebeSEric Cheng 7259da57d7bSbt kstat_named_t reset_count; /* Reset Count */ 7269da57d7bSbt 7279da57d7bSbt kstat_named_t rx_frame_error; /* Rx Error in Packet */ 7289da57d7bSbt kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 7299da57d7bSbt kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 7309da57d7bSbt 7319da57d7bSbt kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 7329da57d7bSbt kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 7339da57d7bSbt kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 7349da57d7bSbt kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 7359da57d7bSbt kstat_named_t tx_reschedule; /* Tx Reschedule */ 7369da57d7bSbt 7379da57d7bSbt kstat_named_t gprc; /* Good Packets Received Count */ 7389da57d7bSbt kstat_named_t gptc; /* Good Packets Xmitted Count */ 7399da57d7bSbt kstat_named_t gor; /* Good Octets Received Count */ 7409da57d7bSbt kstat_named_t got; /* Good Octets Xmitd Count */ 7419da57d7bSbt kstat_named_t prc64; /* Packets Received - 64b */ 7429da57d7bSbt kstat_named_t prc127; /* Packets Received - 65-127b */ 7439da57d7bSbt kstat_named_t prc255; /* Packets Received - 127-255b */ 7449da57d7bSbt kstat_named_t prc511; /* Packets Received - 256-511b */ 7459da57d7bSbt kstat_named_t prc1023; /* Packets Received - 511-1023b */ 7469da57d7bSbt kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 7479da57d7bSbt kstat_named_t ptc64; /* Packets Xmitted (64b) */ 7489da57d7bSbt kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 7499da57d7bSbt kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 7509da57d7bSbt kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 7519da57d7bSbt kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 7529da57d7bSbt kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 753da14cebeSEric Cheng kstat_named_t qprc[16]; /* Queue Packets Received Count */ 754da14cebeSEric Cheng kstat_named_t qptc[16]; /* Queue Packets Transmitted Count */ 755da14cebeSEric Cheng kstat_named_t qbrc[16]; /* Queue Bytes Received Count */ 756da14cebeSEric Cheng kstat_named_t qbtc[16]; /* Queue Bytes Transmitted Count */ 757da14cebeSEric Cheng 7589da57d7bSbt kstat_named_t crcerrs; /* CRC Error Count */ 7599da57d7bSbt kstat_named_t illerrc; /* Illegal Byte Error Count */ 7609da57d7bSbt kstat_named_t errbc; /* Error Byte Count */ 7619da57d7bSbt kstat_named_t mspdc; /* MAC Short Packet Discard Count */ 7629da57d7bSbt kstat_named_t mpc; /* Missed Packets Count */ 7639da57d7bSbt kstat_named_t mlfc; /* MAC Local Fault Count */ 7649da57d7bSbt kstat_named_t mrfc; /* MAC Remote Fault Count */ 7659da57d7bSbt kstat_named_t rlec; /* Receive Length Error Count */ 7669da57d7bSbt kstat_named_t lxontxc; /* Link XON Transmitted Count */ 7679da57d7bSbt kstat_named_t lxonrxc; /* Link XON Received Count */ 7689da57d7bSbt kstat_named_t lxofftxc; /* Link XOFF Transmitted Count */ 7699da57d7bSbt kstat_named_t lxoffrxc; /* Link XOFF Received Count */ 7709da57d7bSbt kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 7719da57d7bSbt kstat_named_t mprc; /* Multicast Pkts Received Count */ 7729da57d7bSbt kstat_named_t rnbc; /* Receive No Buffers Count */ 7739da57d7bSbt kstat_named_t ruc; /* Receive Undersize Count */ 7749da57d7bSbt kstat_named_t rfc; /* Receive Frag Count */ 7759da57d7bSbt kstat_named_t roc; /* Receive Oversize Count */ 7769da57d7bSbt kstat_named_t rjc; /* Receive Jabber Count */ 7779da57d7bSbt kstat_named_t tor; /* Total Octets Recvd Count */ 778f27d3025Sgg kstat_named_t tot; /* Total Octets Xmitted Count */ 7799da57d7bSbt kstat_named_t tpr; /* Total Packets Received */ 7809da57d7bSbt kstat_named_t tpt; /* Total Packets Xmitted */ 7819da57d7bSbt kstat_named_t mptc; /* Multicast Packets Xmited Count */ 7829da57d7bSbt kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 783*ffd8e883SWinson Wang - Sun Microsystems - Beijing China kstat_named_t lroc; /* LRO Packets Received Count */ 7849da57d7bSbt } ixgbe_stat_t; 7859da57d7bSbt 7869da57d7bSbt /* 7879da57d7bSbt * Function prototypes in ixgbe_buf.c 7889da57d7bSbt */ 7899da57d7bSbt int ixgbe_alloc_dma(ixgbe_t *); 7909da57d7bSbt void ixgbe_free_dma(ixgbe_t *); 791837c1ac4SStephen Hanson void ixgbe_set_fma_flags(int); 792ea65739eSchenlu chen - Sun Microsystems - Beijing China void ixgbe_free_dma_buffer(dma_buffer_t *); 793ea65739eSchenlu chen - Sun Microsystems - Beijing China int ixgbe_alloc_rx_ring_data(ixgbe_rx_ring_t *rx_ring); 794ea65739eSchenlu chen - Sun Microsystems - Beijing China void ixgbe_free_rx_ring_data(ixgbe_rx_data_t *rx_data); 7959da57d7bSbt 7969da57d7bSbt /* 7979da57d7bSbt * Function prototypes in ixgbe_main.c 7989da57d7bSbt */ 799ea65739eSchenlu chen - Sun Microsystems - Beijing China int ixgbe_start(ixgbe_t *, boolean_t); 800ea65739eSchenlu chen - Sun Microsystems - Beijing China void ixgbe_stop(ixgbe_t *, boolean_t); 8019da57d7bSbt int ixgbe_driver_setup_link(ixgbe_t *, boolean_t); 8029da57d7bSbt int ixgbe_multicst_add(ixgbe_t *, const uint8_t *); 8039da57d7bSbt int ixgbe_multicst_remove(ixgbe_t *, const uint8_t *); 8049da57d7bSbt enum ioc_reply ixgbe_loopback_ioctl(ixgbe_t *, struct iocblk *, mblk_t *); 8059da57d7bSbt 8069da57d7bSbt void ixgbe_enable_watchdog_timer(ixgbe_t *); 8079da57d7bSbt void ixgbe_disable_watchdog_timer(ixgbe_t *); 8089da57d7bSbt int ixgbe_atomic_reserve(uint32_t *, uint32_t); 8099da57d7bSbt 8109da57d7bSbt int ixgbe_check_acc_handle(ddi_acc_handle_t handle); 8119da57d7bSbt int ixgbe_check_dma_handle(ddi_dma_handle_t handle); 8129da57d7bSbt void ixgbe_fm_ereport(ixgbe_t *, char *); 8139da57d7bSbt 814da14cebeSEric Cheng void ixgbe_fill_ring(void *, mac_ring_type_t, const int, const int, 815da14cebeSEric Cheng mac_ring_info_t *, mac_ring_handle_t); 816da14cebeSEric Cheng void ixgbe_fill_group(void *arg, mac_ring_type_t, const int, 817da14cebeSEric Cheng mac_group_info_t *, mac_group_handle_t); 818da14cebeSEric Cheng int ixgbe_rx_ring_intr_enable(mac_intr_handle_t); 819da14cebeSEric Cheng int ixgbe_rx_ring_intr_disable(mac_intr_handle_t); 820da14cebeSEric Cheng 8219da57d7bSbt /* 8229da57d7bSbt * Function prototypes in ixgbe_gld.c 8239da57d7bSbt */ 8249da57d7bSbt int ixgbe_m_start(void *); 8259da57d7bSbt void ixgbe_m_stop(void *); 8269da57d7bSbt int ixgbe_m_promisc(void *, boolean_t); 8279da57d7bSbt int ixgbe_m_multicst(void *, boolean_t, const uint8_t *); 8289da57d7bSbt int ixgbe_m_stat(void *, uint_t, uint64_t *); 8299da57d7bSbt void ixgbe_m_resources(void *); 8309da57d7bSbt void ixgbe_m_ioctl(void *, queue_t *, mblk_t *); 8319da57d7bSbt boolean_t ixgbe_m_getcapab(void *, mac_capab_t, void *); 832ea65739eSchenlu chen - Sun Microsystems - Beijing China int ixgbe_m_setprop(void *, const char *, mac_prop_id_t, uint_t, const void *); 833ea65739eSchenlu chen - Sun Microsystems - Beijing China int ixgbe_m_getprop(void *, const char *, mac_prop_id_t, 834ea65739eSchenlu chen - Sun Microsystems - Beijing China uint_t, uint_t, void *, uint_t *); 835ea65739eSchenlu chen - Sun Microsystems - Beijing China int ixgbe_set_priv_prop(ixgbe_t *, const char *, uint_t, const void *); 836ea65739eSchenlu chen - Sun Microsystems - Beijing China int ixgbe_get_priv_prop(ixgbe_t *, const char *, 837ea65739eSchenlu chen - Sun Microsystems - Beijing China uint_t, uint_t, void *, uint_t *); 838ea65739eSchenlu chen - Sun Microsystems - Beijing China boolean_t ixgbe_param_locked(mac_prop_id_t); 8399da57d7bSbt 8409da57d7bSbt /* 8419da57d7bSbt * Function prototypes in ixgbe_rx.c 8429da57d7bSbt */ 843da14cebeSEric Cheng mblk_t *ixgbe_ring_rx(ixgbe_rx_ring_t *, int); 8449da57d7bSbt void ixgbe_rx_recycle(caddr_t arg); 845da14cebeSEric Cheng mblk_t *ixgbe_ring_rx_poll(void *, int); 8469da57d7bSbt 8479da57d7bSbt /* 8489da57d7bSbt * Function prototypes in ixgbe_tx.c 8499da57d7bSbt */ 850da14cebeSEric Cheng mblk_t *ixgbe_ring_tx(void *, mblk_t *); 8519da57d7bSbt void ixgbe_free_tcb(tx_control_block_t *); 8529da57d7bSbt void ixgbe_put_free_list(ixgbe_tx_ring_t *, link_list_t *); 8539da57d7bSbt uint32_t ixgbe_tx_recycle_legacy(ixgbe_tx_ring_t *); 8549da57d7bSbt uint32_t ixgbe_tx_recycle_head_wb(ixgbe_tx_ring_t *); 8559da57d7bSbt 8569da57d7bSbt /* 8579da57d7bSbt * Function prototypes in ixgbe_log.c 8589da57d7bSbt */ 8599da57d7bSbt void ixgbe_notice(void *, const char *, ...); 8609da57d7bSbt void ixgbe_log(void *, const char *, ...); 8619da57d7bSbt void ixgbe_error(void *, const char *, ...); 8629da57d7bSbt 8639da57d7bSbt /* 8649da57d7bSbt * Function prototypes in ixgbe_stat.c 8659da57d7bSbt */ 8669da57d7bSbt int ixgbe_init_stats(ixgbe_t *); 8679da57d7bSbt 8689da57d7bSbt #ifdef __cplusplus 8699da57d7bSbt } 8709da57d7bSbt #endif 8719da57d7bSbt 8729da57d7bSbt #endif /* _IXGBE_SW_H */ 873