19da57d7bSbt /* 29da57d7bSbt * CDDL HEADER START 39da57d7bSbt * 49da57d7bSbt * The contents of this file are subject to the terms of the 59da57d7bSbt * Common Development and Distribution License (the "License"). 69da57d7bSbt * You may not use this file except in compliance with the License. 79da57d7bSbt * 8da14cebeSEric Cheng * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9da14cebeSEric Cheng * or http://www.opensolaris.org/os/licensing. 109da57d7bSbt * See the License for the specific language governing permissions 119da57d7bSbt * and limitations under the License. 129da57d7bSbt * 13da14cebeSEric Cheng * When distributing Covered Code, include this CDDL HEADER in each 14da14cebeSEric Cheng * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 159da57d7bSbt * If applicable, add the following below this CDDL HEADER, with the 169da57d7bSbt * fields enclosed by brackets "[]" replaced with your own identifying 179da57d7bSbt * information: Portions Copyright [yyyy] [name of copyright owner] 189da57d7bSbt * 199da57d7bSbt * CDDL HEADER END 209da57d7bSbt */ 219da57d7bSbt 229da57d7bSbt /* 235b6dd21fSchenlu chen - Sun Microsystems - Beijing China * Copyright(c) 2007-2010 Intel Corporation. All rights reserved. 245b6dd21fSchenlu chen - Sun Microsystems - Beijing China */ 255b6dd21fSchenlu chen - Sun Microsystems - Beijing China 265b6dd21fSchenlu chen - Sun Microsystems - Beijing China /* 275b6dd21fSchenlu chen - Sun Microsystems - Beijing China * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 2843fab1a9SSaso Kiselkov * Copyright (c) 2013 Saso Kiselkov. All rights reserved. 29dc0cb1cdSDale Ghent * Copyright 2016 OmniTI Computer Consulting, Inc. All rights reserved. 30168e1ed4SRyan Zezeski * Copyright 2019 Joyent, Inc. 31*f2fe7acaSRobert Mustacchi * Copyright 2020 Oxide Computer Company 329da57d7bSbt */ 339da57d7bSbt 349da57d7bSbt #ifndef _IXGBE_SW_H 359da57d7bSbt #define _IXGBE_SW_H 369da57d7bSbt 379da57d7bSbt #ifdef __cplusplus 389da57d7bSbt extern "C" { 399da57d7bSbt #endif 409da57d7bSbt 419da57d7bSbt #include <sys/types.h> 429da57d7bSbt #include <sys/conf.h> 439da57d7bSbt #include <sys/debug.h> 449da57d7bSbt #include <sys/stropts.h> 459da57d7bSbt #include <sys/stream.h> 469da57d7bSbt #include <sys/strsun.h> 479da57d7bSbt #include <sys/strlog.h> 489da57d7bSbt #include <sys/kmem.h> 499da57d7bSbt #include <sys/stat.h> 509da57d7bSbt #include <sys/kstat.h> 519da57d7bSbt #include <sys/modctl.h> 529da57d7bSbt #include <sys/errno.h> 539da57d7bSbt #include <sys/dlpi.h> 54da14cebeSEric Cheng #include <sys/mac_provider.h> 559da57d7bSbt #include <sys/mac_ether.h> 569da57d7bSbt #include <sys/vlan.h> 579da57d7bSbt #include <sys/ddi.h> 589da57d7bSbt #include <sys/sunddi.h> 599da57d7bSbt #include <sys/pci.h> 609da57d7bSbt #include <sys/pcie.h> 619da57d7bSbt #include <sys/sdt.h> 629da57d7bSbt #include <sys/ethernet.h> 639da57d7bSbt #include <sys/pattr.h> 649da57d7bSbt #include <sys/strsubr.h> 659da57d7bSbt #include <sys/netlb.h> 669da57d7bSbt #include <sys/random.h> 679da57d7bSbt #include <inet/common.h> 68c971fb7eSgg #include <inet/tcp.h> 699da57d7bSbt #include <inet/ip.h> 709da57d7bSbt #include <inet/mi.h> 719da57d7bSbt #include <inet/nd.h> 729da57d7bSbt #include <sys/bitmap.h> 739da57d7bSbt #include <sys/ddifm.h> 749da57d7bSbt #include <sys/fm/protocol.h> 759da57d7bSbt #include <sys/fm/util.h> 7662e6e1adSPaul Guo #include <sys/disp.h> 779da57d7bSbt #include <sys/fm/io/ddi.h> 78*f2fe7acaSRobert Mustacchi #include <sys/ddi_ufm.h> 799da57d7bSbt #include "ixgbe_api.h" 809da57d7bSbt 819da57d7bSbt #define MODULE_NAME "ixgbe" /* module name */ 829da57d7bSbt 839da57d7bSbt #define IXGBE_FAILURE DDI_FAILURE 849da57d7bSbt 859da57d7bSbt #define IXGBE_UNKNOWN 0x00 869da57d7bSbt #define IXGBE_INITIALIZED 0x01 879da57d7bSbt #define IXGBE_STARTED 0x02 889da57d7bSbt #define IXGBE_SUSPENDED 0x04 8962e6e1adSPaul Guo #define IXGBE_STALL 0x08 905b6dd21fSchenlu chen - Sun Microsystems - Beijing China #define IXGBE_OVERTEMP 0x20 910dc2366fSVenugopal Iyer #define IXGBE_INTR_ADJUST 0x40 9262e6e1adSPaul Guo #define IXGBE_ERROR 0x80 939da57d7bSbt 94168e1ed4SRyan Zezeski #define MAX_NUM_UNICAST_ADDRESSES 0x80 95168e1ed4SRyan Zezeski #define MAX_NUM_MULTICAST_ADDRESSES 0x1000 9684de666eSRyan Zezeski #define MAX_NUM_VLAN_FILTERS 0x40 9784de666eSRyan Zezeski 989da57d7bSbt #define IXGBE_INTR_NONE 0 999da57d7bSbt #define IXGBE_INTR_MSIX 1 1009da57d7bSbt #define IXGBE_INTR_MSI 2 1019da57d7bSbt #define IXGBE_INTR_LEGACY 3 1029da57d7bSbt 103da14cebeSEric Cheng #define IXGBE_POLL_NULL -1 104da14cebeSEric Cheng 105c971fb7eSgg #define MAX_COOKIE 18 1069da57d7bSbt #define MIN_NUM_TX_DESC 2 1079da57d7bSbt 108edf70dc9SPaul Guo #define IXGBE_TX_DESC_LIMIT 32 /* tx desc limitation */ 109edf70dc9SPaul Guo 11073cd555cSBin Tu - Sun Microsystems - Beijing China #define IXGBE_ADAPTER_REGSET 1 /* map adapter registers */ 11173cd555cSBin Tu - Sun Microsystems - Beijing China 112ea65739eSchenlu chen - Sun Microsystems - Beijing China #define IXGBE_RX_STOPPED 0x1 113ea65739eSchenlu chen - Sun Microsystems - Beijing China 114ffd8e883SWinson Wang - Sun Microsystems - Beijing China #define IXGBE_PKG_BUF_16k 16384 115ffd8e883SWinson Wang - Sun Microsystems - Beijing China 1169da57d7bSbt /* 11773cd555cSBin Tu - Sun Microsystems - Beijing China * MAX_xx_QUEUE_NUM and MAX_INTR_VECTOR values need to be the maximum of all 11813740cb2SPaul Guo * supported silicon types. 1199da57d7bSbt */ 12073cd555cSBin Tu - Sun Microsystems - Beijing China #define MAX_TX_QUEUE_NUM 128 12173cd555cSBin Tu - Sun Microsystems - Beijing China #define MAX_RX_QUEUE_NUM 128 12273cd555cSBin Tu - Sun Microsystems - Beijing China #define MAX_INTR_VECTOR 64 1239da57d7bSbt 1249da57d7bSbt /* 12513740cb2SPaul Guo * Maximum values for user configurable parameters 1269da57d7bSbt */ 1279da57d7bSbt #define MAX_TX_RING_SIZE 4096 1289da57d7bSbt #define MAX_RX_RING_SIZE 4096 1299da57d7bSbt 1309da57d7bSbt #define MAX_RX_LIMIT_PER_INTR 4096 1319da57d7bSbt 1329da57d7bSbt #define MAX_RX_COPY_THRESHOLD 9216 1339da57d7bSbt #define MAX_TX_COPY_THRESHOLD 9216 1349da57d7bSbt #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 1359da57d7bSbt #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 1369da57d7bSbt #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 1379da57d7bSbt 1389da57d7bSbt /* 1399da57d7bSbt * Minimum values for user configurable parameters 1409da57d7bSbt */ 1419da57d7bSbt #define MIN_TX_RING_SIZE 64 1429da57d7bSbt #define MIN_RX_RING_SIZE 64 1439da57d7bSbt 1449da57d7bSbt #define MIN_MTU ETHERMIN 1459da57d7bSbt #define MIN_RX_LIMIT_PER_INTR 16 1469da57d7bSbt #define MIN_TX_COPY_THRESHOLD 0 1479da57d7bSbt #define MIN_RX_COPY_THRESHOLD 0 1489da57d7bSbt #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 1499da57d7bSbt #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 1509da57d7bSbt #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 1519da57d7bSbt 1529da57d7bSbt /* 1539da57d7bSbt * Default values for user configurable parameters 1549da57d7bSbt */ 155da14cebeSEric Cheng #define DEFAULT_TX_RING_SIZE 1024 156da14cebeSEric Cheng #define DEFAULT_RX_RING_SIZE 1024 1579da57d7bSbt 1589da57d7bSbt #define DEFAULT_MTU ETHERMTU 1599da57d7bSbt #define DEFAULT_RX_LIMIT_PER_INTR 256 1609da57d7bSbt #define DEFAULT_RX_COPY_THRESHOLD 128 1619da57d7bSbt #define DEFAULT_TX_COPY_THRESHOLD 512 162da14cebeSEric Cheng #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1) 1639da57d7bSbt #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 1649da57d7bSbt #define DEFAULT_TX_RESCHED_THRESHOLD 128 1659da57d7bSbt #define DEFAULT_FCRTH 0x20000 1669da57d7bSbt #define DEFAULT_FCRTL 0x10000 1679da57d7bSbt #define DEFAULT_FCPAUSE 0xFFFF 1689da57d7bSbt 169da14cebeSEric Cheng #define DEFAULT_TX_HCKSUM_ENABLE B_TRUE 170da14cebeSEric Cheng #define DEFAULT_RX_HCKSUM_ENABLE B_TRUE 171da14cebeSEric Cheng #define DEFAULT_LSO_ENABLE B_TRUE 172ffd8e883SWinson Wang - Sun Microsystems - Beijing China #define DEFAULT_LRO_ENABLE B_FALSE 173da14cebeSEric Cheng #define DEFAULT_MR_ENABLE B_TRUE 174da14cebeSEric Cheng #define DEFAULT_TX_HEAD_WB_ENABLE B_TRUE 1755b6dd21fSchenlu chen - Sun Microsystems - Beijing China #define DEFAULT_RELAX_ORDER_ENABLE B_TRUE 17643fab1a9SSaso Kiselkov #define DEFAULT_ALLOW_UNSUPPORTED_SFP B_FALSE 177da14cebeSEric Cheng 178da14cebeSEric Cheng #define IXGBE_LSO_MAXLEN 65535 179da14cebeSEric Cheng 1809da57d7bSbt #define TX_DRAIN_TIME 200 1819da57d7bSbt #define RX_DRAIN_TIME 200 1829da57d7bSbt 1839da57d7bSbt #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 1849da57d7bSbt #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */ 1859da57d7bSbt 18662e6e1adSPaul Guo #define IXGBE_CYCLIC_PERIOD (1000000000) /* 1s */ 18762e6e1adSPaul Guo 1889da57d7bSbt /* 1899da57d7bSbt * Extra register bit masks for 82598 1909da57d7bSbt */ 1919da57d7bSbt #define IXGBE_PCS1GANA_FDC 0x20 1929da57d7bSbt #define IXGBE_PCS1GANLP_LPFD 0x20 1939da57d7bSbt #define IXGBE_PCS1GANLP_LPHD 0x40 1949da57d7bSbt 1959da57d7bSbt /* 1969da57d7bSbt * Defined for IP header alignment. 1979da57d7bSbt */ 1989da57d7bSbt #define IPHDR_ALIGN_ROOM 2 1999da57d7bSbt 2009da57d7bSbt /* 2019da57d7bSbt * Bit flags for attach_progress 2029da57d7bSbt */ 2039da57d7bSbt #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 2049da57d7bSbt #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 2059da57d7bSbt #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 2069da57d7bSbt #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 2079da57d7bSbt #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 2089da57d7bSbt #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 2099da57d7bSbt #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 2109da57d7bSbt #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */ 2119da57d7bSbt #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 2129da57d7bSbt #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 2139da57d7bSbt #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 2149da57d7bSbt #define ATTACH_PROGRESS_FM_INIT 0x2000 /* FMA initialized */ 21562e6e1adSPaul Guo #define ATTACH_PROGRESS_SFP_TASKQ 0x4000 /* SFP taskq created */ 21662e6e1adSPaul Guo #define ATTACH_PROGRESS_LINK_TIMER 0x8000 /* link check timer */ 2175b6dd21fSchenlu chen - Sun Microsystems - Beijing China #define ATTACH_PROGRESS_OVERTEMP_TASKQ 0x10000 /* Over-temp taskq created */ 218dc0cb1cdSDale Ghent #define ATTACH_PROGRESS_PHY_TASKQ 0x20000 /* Ext. PHY taskq created */ 219*f2fe7acaSRobert Mustacchi #define ATTACH_PROGRESS_UFM 0x40000 /* UFM support */ 2209da57d7bSbt 2219da57d7bSbt #define PROP_DEFAULT_MTU "default_mtu" 2229da57d7bSbt #define PROP_FLOW_CONTROL "flow_control" 2239da57d7bSbt #define PROP_TX_QUEUE_NUM "tx_queue_number" 2249da57d7bSbt #define PROP_TX_RING_SIZE "tx_ring_size" 2259da57d7bSbt #define PROP_RX_QUEUE_NUM "rx_queue_number" 2269da57d7bSbt #define PROP_RX_RING_SIZE "rx_ring_size" 227da14cebeSEric Cheng #define PROP_RX_GROUP_NUM "rx_group_number" 2289da57d7bSbt 2299da57d7bSbt #define PROP_INTR_FORCE "intr_force" 2309da57d7bSbt #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 2319da57d7bSbt #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 2329da57d7bSbt #define PROP_LSO_ENABLE "lso_enable" 233ffd8e883SWinson Wang - Sun Microsystems - Beijing China #define PROP_LRO_ENABLE "lro_enable" 234da14cebeSEric Cheng #define PROP_MR_ENABLE "mr_enable" 2355b6dd21fSchenlu chen - Sun Microsystems - Beijing China #define PROP_RELAX_ORDER_ENABLE "relax_order_enable" 2369da57d7bSbt #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 2379da57d7bSbt #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 2389da57d7bSbt #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 2399da57d7bSbt #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 2409da57d7bSbt #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 2419da57d7bSbt #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 2429da57d7bSbt #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 2439da57d7bSbt #define PROP_INTR_THROTTLING "intr_throttling" 2449da57d7bSbt #define PROP_FM_CAPABLE "fm_capable" 24543fab1a9SSaso Kiselkov #define PROP_ALLOW_UNSUPPORTED_SFP "allow_unsupported_sfp" 2469da57d7bSbt 2479da57d7bSbt #define IXGBE_LB_NONE 0 2489da57d7bSbt #define IXGBE_LB_EXTERNAL 1 2499da57d7bSbt #define IXGBE_LB_INTERNAL_MAC 2 2509da57d7bSbt #define IXGBE_LB_INTERNAL_PHY 3 2519da57d7bSbt #define IXGBE_LB_INTERNAL_SERDES 4 2529da57d7bSbt 25313740cb2SPaul Guo /* 25413740cb2SPaul Guo * capability/feature flags 25513740cb2SPaul Guo * Flags named _CAPABLE are set when the NIC hardware is capable of the feature. 25613740cb2SPaul Guo * Separately, the flag named _ENABLED is set when the feature is enabled. 25713740cb2SPaul Guo */ 25813740cb2SPaul Guo #define IXGBE_FLAG_DCA_ENABLED (u32)(1) 25913740cb2SPaul Guo #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 1) 26013740cb2SPaul Guo #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 2) 26113740cb2SPaul Guo #define IXGBE_FLAG_DCB_CAPABLE (u32)(1 << 4) 26213740cb2SPaul Guo #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 4) 26313740cb2SPaul Guo #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 5) 26413740cb2SPaul Guo #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 6) 26513740cb2SPaul Guo #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 7) 26613740cb2SPaul Guo #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 8) 267ffd8e883SWinson Wang - Sun Microsystems - Beijing China #define IXGBE_FLAG_RSC_CAPABLE (u32)(1 << 9) 2685b6dd21fSchenlu chen - Sun Microsystems - Beijing China #define IXGBE_FLAG_SFP_PLUG_CAPABLE (u32)(1 << 10) 2695b6dd21fSchenlu chen - Sun Microsystems - Beijing China #define IXGBE_FLAG_TEMP_SENSOR_CAPABLE (u32)(1 << 11) 27013740cb2SPaul Guo 2710dc2366fSVenugopal Iyer /* 2720dc2366fSVenugopal Iyer * Classification mode 2730dc2366fSVenugopal Iyer */ 2740dc2366fSVenugopal Iyer #define IXGBE_CLASSIFY_NONE 0 2750dc2366fSVenugopal Iyer #define IXGBE_CLASSIFY_RSS 1 2760dc2366fSVenugopal Iyer #define IXGBE_CLASSIFY_VMDQ 2 2770dc2366fSVenugopal Iyer #define IXGBE_CLASSIFY_VMDQ_RSS 3 2780dc2366fSVenugopal Iyer 27913740cb2SPaul Guo /* adapter-specific info for each supported device type */ 28013740cb2SPaul Guo typedef struct adapter_info { 2810dc2366fSVenugopal Iyer uint32_t max_rx_que_num; /* maximum number of rx queues */ 2820dc2366fSVenugopal Iyer uint32_t min_rx_que_num; /* minimum number of rx queues */ 2830dc2366fSVenugopal Iyer uint32_t def_rx_que_num; /* default number of rx queues */ 2840dc2366fSVenugopal Iyer uint32_t max_rx_grp_num; /* maximum number of rx groups */ 2850dc2366fSVenugopal Iyer uint32_t min_rx_grp_num; /* minimum number of rx groups */ 2860dc2366fSVenugopal Iyer uint32_t def_rx_grp_num; /* default number of rx groups */ 28713740cb2SPaul Guo uint32_t max_tx_que_num; /* maximum number of tx queues */ 28813740cb2SPaul Guo uint32_t min_tx_que_num; /* minimum number of tx queues */ 28913740cb2SPaul Guo uint32_t def_tx_que_num; /* default number of tx queues */ 2901fedc51fSWinson Wang - Sun Microsystems - Beijing China uint32_t max_mtu; /* maximum MTU size */ 291ea65739eSchenlu chen - Sun Microsystems - Beijing China /* 292ea65739eSchenlu chen - Sun Microsystems - Beijing China * Interrupt throttling is in unit of 256 nsec 293ea65739eSchenlu chen - Sun Microsystems - Beijing China */ 294ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t max_intr_throttle; /* maximum interrupt throttle */ 295ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t min_intr_throttle; /* minimum interrupt throttle */ 296ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t def_intr_throttle; /* default interrupt throttle */ 297ea65739eSchenlu chen - Sun Microsystems - Beijing China 29813740cb2SPaul Guo uint32_t max_msix_vect; /* maximum total msix vectors */ 29913740cb2SPaul Guo uint32_t max_ring_vect; /* maximum number of ring vectors */ 30013740cb2SPaul Guo uint32_t max_other_vect; /* maximum number of other vectors */ 30113740cb2SPaul Guo uint32_t other_intr; /* "other" interrupt types handled */ 3025b6dd21fSchenlu chen - Sun Microsystems - Beijing China uint32_t other_gpie; /* "other" interrupt types enabling */ 30313740cb2SPaul Guo uint32_t flags; /* capability flags */ 30413740cb2SPaul Guo } adapter_info_t; 30513740cb2SPaul Guo 30613740cb2SPaul Guo /* bits representing all interrupt types other than tx & rx */ 30713740cb2SPaul Guo #define IXGBE_OTHER_INTR 0x3ff00000 30873cd555cSBin Tu - Sun Microsystems - Beijing China #define IXGBE_82599_OTHER_INTR 0x86100000 30913740cb2SPaul Guo 3109da57d7bSbt enum ioc_reply { 3119da57d7bSbt IOC_INVAL = -1, /* bad, NAK with EINVAL */ 312168e1ed4SRyan Zezeski IOC_DONE, /* OK, reply sent */ 3139da57d7bSbt IOC_ACK, /* OK, just send ACK */ 3149da57d7bSbt IOC_REPLY /* OK, just send reply */ 3159da57d7bSbt }; 3169da57d7bSbt 3179da57d7bSbt #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 3189da57d7bSbt 0, 0, (flag))) 3199da57d7bSbt 3209da57d7bSbt /* 3219da57d7bSbt * Defined for ring index operations 3229da57d7bSbt * ASSERT(index < limit) 3239da57d7bSbt * ASSERT(step < limit) 3249da57d7bSbt * ASSERT(index1 < limit) 3259da57d7bSbt * ASSERT(index2 < limit) 3269da57d7bSbt */ 3279da57d7bSbt #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 3289da57d7bSbt (index) + (step) : (index) + (step) - (limit)) 3299da57d7bSbt #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 3309da57d7bSbt (index) - (step) : (index) + (limit) - (step)) 3319da57d7bSbt #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 3329da57d7bSbt (index2) - (index1) : (index2) + (limit) - (index1)) 3339da57d7bSbt 3349da57d7bSbt #define LINK_LIST_INIT(_LH) \ 3359da57d7bSbt (_LH)->head = (_LH)->tail = NULL 3369da57d7bSbt 3379da57d7bSbt #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 3389da57d7bSbt 3399da57d7bSbt #define LIST_POP_HEAD(_LH) \ 3409da57d7bSbt (single_link_t *)(_LH)->head; \ 3419da57d7bSbt { \ 3429da57d7bSbt if ((_LH)->head != NULL) { \ 3439da57d7bSbt (_LH)->head = (_LH)->head->link; \ 3449da57d7bSbt if ((_LH)->head == NULL) \ 3459da57d7bSbt (_LH)->tail = NULL; \ 3469da57d7bSbt } \ 3479da57d7bSbt } 3489da57d7bSbt 3499da57d7bSbt #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 3509da57d7bSbt 3519da57d7bSbt #define LIST_PUSH_TAIL(_LH, _E) \ 3529da57d7bSbt if ((_LH)->tail != NULL) { \ 3539da57d7bSbt (_LH)->tail->link = (single_link_t *)(_E); \ 3549da57d7bSbt (_LH)->tail = (single_link_t *)(_E); \ 3559da57d7bSbt } else { \ 3569da57d7bSbt (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 3579da57d7bSbt } \ 3589da57d7bSbt (_E)->link = NULL; 3599da57d7bSbt 3609da57d7bSbt #define LIST_GET_NEXT(_LH, _E) \ 3619da57d7bSbt (((_LH)->tail == (single_link_t *)(_E)) ? \ 3629da57d7bSbt NULL : ((single_link_t *)(_E))->link) 3639da57d7bSbt 3649da57d7bSbt 3659da57d7bSbt typedef struct single_link { 3669da57d7bSbt struct single_link *link; 3679da57d7bSbt } single_link_t; 3689da57d7bSbt 3699da57d7bSbt typedef struct link_list { 3709da57d7bSbt single_link_t *head; 3719da57d7bSbt single_link_t *tail; 3729da57d7bSbt } link_list_t; 3739da57d7bSbt 3749da57d7bSbt /* 3759da57d7bSbt * Property lookups 3769da57d7bSbt */ 3779da57d7bSbt #define IXGBE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 3789da57d7bSbt DDI_PROP_DONTPASS, (n)) 3799da57d7bSbt #define IXGBE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 3809da57d7bSbt DDI_PROP_DONTPASS, (n), -1) 3819da57d7bSbt 3829da57d7bSbt 3839da57d7bSbt typedef union ixgbe_ether_addr { 3849da57d7bSbt struct { 3859da57d7bSbt uint32_t high; 3869da57d7bSbt uint32_t low; 3879da57d7bSbt } reg; 3889da57d7bSbt struct { 3899da57d7bSbt uint8_t set; 3900dc2366fSVenugopal Iyer uint8_t group_index; 3919da57d7bSbt uint8_t addr[ETHERADDRL]; 3929da57d7bSbt } mac; 3939da57d7bSbt } ixgbe_ether_addr_t; 3949da57d7bSbt 39584de666eSRyan Zezeski /* 39684de666eSRyan Zezeski * The list of VLANs an Rx group will accept. 39784de666eSRyan Zezeski */ 39884de666eSRyan Zezeski typedef struct ixgbe_vlan { 39984de666eSRyan Zezeski list_node_t ixvl_link; 40084de666eSRyan Zezeski uint16_t ixvl_vid; /* The VLAN ID */ 40184de666eSRyan Zezeski uint_t ixvl_refs; /* Number of users of this VLAN */ 40284de666eSRyan Zezeski } ixgbe_vlan_t; 40384de666eSRyan Zezeski 4049da57d7bSbt typedef enum { 4059da57d7bSbt USE_NONE, 4069da57d7bSbt USE_COPY, 4079da57d7bSbt USE_DMA 4089da57d7bSbt } tx_type_t; 4099da57d7bSbt 410c971fb7eSgg typedef struct ixgbe_tx_context { 4119da57d7bSbt uint32_t hcksum_flags; 4129da57d7bSbt uint32_t ip_hdr_len; 4139da57d7bSbt uint32_t mac_hdr_len; 41485f496faSRobert Mustacchi uint32_t l3_proto; 4159da57d7bSbt uint32_t l4_proto; 416c971fb7eSgg uint32_t mss; 417c971fb7eSgg uint32_t l4_hdr_len; 418c971fb7eSgg boolean_t lso_flag; 419c971fb7eSgg } ixgbe_tx_context_t; 4209da57d7bSbt 4219da57d7bSbt /* 4229da57d7bSbt * Hold address/length of each DMA segment 4239da57d7bSbt */ 4249da57d7bSbt typedef struct sw_desc { 4259da57d7bSbt uint64_t address; 4269da57d7bSbt size_t length; 4279da57d7bSbt } sw_desc_t; 4289da57d7bSbt 4299da57d7bSbt /* 4309da57d7bSbt * Handles and addresses of DMA buffer 4319da57d7bSbt */ 4329da57d7bSbt typedef struct dma_buffer { 4339da57d7bSbt caddr_t address; /* Virtual address */ 4349da57d7bSbt uint64_t dma_address; /* DMA (Hardware) address */ 4359da57d7bSbt ddi_acc_handle_t acc_handle; /* Data access handle */ 4369da57d7bSbt ddi_dma_handle_t dma_handle; /* DMA handle */ 4379da57d7bSbt size_t size; /* Buffer size */ 4389da57d7bSbt size_t len; /* Data length in the buffer */ 4399da57d7bSbt } dma_buffer_t; 4409da57d7bSbt 4419da57d7bSbt /* 4429da57d7bSbt * Tx Control Block 4439da57d7bSbt */ 4449da57d7bSbt typedef struct tx_control_block { 4459da57d7bSbt single_link_t link; 446edf70dc9SPaul Guo uint32_t last_index; /* last descriptor of the pkt */ 4479da57d7bSbt uint32_t frag_num; 4489da57d7bSbt uint32_t desc_num; 4499da57d7bSbt mblk_t *mp; 4509da57d7bSbt tx_type_t tx_type; 4519da57d7bSbt ddi_dma_handle_t tx_dma_handle; 4529da57d7bSbt dma_buffer_t tx_buf; 4539da57d7bSbt sw_desc_t desc[MAX_COOKIE]; 4549da57d7bSbt } tx_control_block_t; 4559da57d7bSbt 4569da57d7bSbt /* 4579da57d7bSbt * RX Control Block 4589da57d7bSbt */ 4599da57d7bSbt typedef struct rx_control_block { 4609da57d7bSbt mblk_t *mp; 461ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t ref_cnt; 4629da57d7bSbt dma_buffer_t rx_buf; 4639da57d7bSbt frtn_t free_rtn; 464ea65739eSchenlu chen - Sun Microsystems - Beijing China struct ixgbe_rx_data *rx_data; 465ffd8e883SWinson Wang - Sun Microsystems - Beijing China int lro_next; /* Index of next rcb */ 466ffd8e883SWinson Wang - Sun Microsystems - Beijing China int lro_prev; /* Index of previous rcb */ 467ffd8e883SWinson Wang - Sun Microsystems - Beijing China boolean_t lro_pkt; /* Flag for LRO rcb */ 4689da57d7bSbt } rx_control_block_t; 4699da57d7bSbt 4709da57d7bSbt /* 4719da57d7bSbt * Software Data Structure for Tx Ring 4729da57d7bSbt */ 4739da57d7bSbt typedef struct ixgbe_tx_ring { 4749da57d7bSbt uint32_t index; /* Ring index */ 4759da57d7bSbt uint32_t intr_vector; /* Interrupt vector index */ 4769da57d7bSbt uint32_t vect_bit; /* vector's bit in register */ 4779da57d7bSbt 4789da57d7bSbt /* 4799da57d7bSbt * Mutexes 4809da57d7bSbt */ 4819da57d7bSbt kmutex_t tx_lock; 4829da57d7bSbt kmutex_t recycle_lock; 4839da57d7bSbt kmutex_t tcb_head_lock; 4849da57d7bSbt kmutex_t tcb_tail_lock; 4859da57d7bSbt 4869da57d7bSbt /* 4879da57d7bSbt * Tx descriptor ring definitions 4889da57d7bSbt */ 4899da57d7bSbt dma_buffer_t tbd_area; 4909da57d7bSbt union ixgbe_adv_tx_desc *tbd_ring; 4919da57d7bSbt uint32_t tbd_head; /* Index of next tbd to recycle */ 4929da57d7bSbt uint32_t tbd_tail; /* Index of next tbd to transmit */ 4939da57d7bSbt uint32_t tbd_free; /* Number of free tbd */ 4949da57d7bSbt 4959da57d7bSbt /* 4969da57d7bSbt * Tx control block list definitions 4979da57d7bSbt */ 4989da57d7bSbt tx_control_block_t *tcb_area; 4999da57d7bSbt tx_control_block_t **work_list; 5009da57d7bSbt tx_control_block_t **free_list; 5019da57d7bSbt uint32_t tcb_head; /* Head index of free list */ 5029da57d7bSbt uint32_t tcb_tail; /* Tail index of free list */ 5039da57d7bSbt uint32_t tcb_free; /* Number of free tcb in free list */ 5049da57d7bSbt 5059da57d7bSbt uint32_t *tbd_head_wb; /* Head write-back */ 5069da57d7bSbt uint32_t (*tx_recycle)(struct ixgbe_tx_ring *); 5079da57d7bSbt 5089da57d7bSbt /* 509c971fb7eSgg * s/w context structure for TCP/UDP checksum offload 510c971fb7eSgg * and LSO. 5119da57d7bSbt */ 512c971fb7eSgg ixgbe_tx_context_t tx_context; 5139da57d7bSbt 5149da57d7bSbt /* 5159da57d7bSbt * Tx ring settings and status 5169da57d7bSbt */ 5179da57d7bSbt uint32_t ring_size; /* Tx descriptor ring size */ 5189da57d7bSbt uint32_t free_list_size; /* Tx free list size */ 5199da57d7bSbt 5209da57d7bSbt boolean_t reschedule; 5219da57d7bSbt uint32_t recycle_fail; 5229da57d7bSbt uint32_t stall_watchdog; 5239da57d7bSbt 5249da57d7bSbt uint32_t stat_overload; 5259da57d7bSbt uint32_t stat_fail_no_tbd; 5269da57d7bSbt uint32_t stat_fail_no_tcb; 5279da57d7bSbt uint32_t stat_fail_dma_bind; 5289da57d7bSbt uint32_t stat_reschedule; 529edf70dc9SPaul Guo uint32_t stat_break_tbd_limit; 530da14cebeSEric Cheng uint32_t stat_lso_header_fail; 53163efadf0SRyan Zezeski 5320dc2366fSVenugopal Iyer uint64_t stat_obytes; 5330dc2366fSVenugopal Iyer uint64_t stat_opackets; 5349da57d7bSbt 535da14cebeSEric Cheng mac_ring_handle_t ring_handle; 536da14cebeSEric Cheng 5379da57d7bSbt /* 5389da57d7bSbt * Pointer to the ixgbe struct 5399da57d7bSbt */ 5409da57d7bSbt struct ixgbe *ixgbe; 5419da57d7bSbt } ixgbe_tx_ring_t; 5429da57d7bSbt 5439da57d7bSbt /* 5449da57d7bSbt * Software Receive Ring 5459da57d7bSbt */ 546ea65739eSchenlu chen - Sun Microsystems - Beijing China typedef struct ixgbe_rx_data { 5479da57d7bSbt kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 5489da57d7bSbt 5499da57d7bSbt /* 5509da57d7bSbt * Rx descriptor ring definitions 5519da57d7bSbt */ 5529da57d7bSbt dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 5539da57d7bSbt union ixgbe_adv_rx_desc *rbd_ring; /* Rx desc ring */ 5549da57d7bSbt uint32_t rbd_next; /* Index of next rx desc */ 5559da57d7bSbt 5569da57d7bSbt /* 5579da57d7bSbt * Rx control block list definitions 5589da57d7bSbt */ 5599da57d7bSbt rx_control_block_t *rcb_area; 5609da57d7bSbt rx_control_block_t **work_list; /* Work list of rcbs */ 5619da57d7bSbt rx_control_block_t **free_list; /* Free list of rcbs */ 5629da57d7bSbt uint32_t rcb_head; /* Index of next free rcb */ 5639da57d7bSbt uint32_t rcb_tail; /* Index to put recycled rcb */ 5649da57d7bSbt uint32_t rcb_free; /* Number of free rcbs */ 5659da57d7bSbt 5669da57d7bSbt /* 567ea65739eSchenlu chen - Sun Microsystems - Beijing China * Rx sw ring settings and status 5689da57d7bSbt */ 5699da57d7bSbt uint32_t ring_size; /* Rx descriptor ring size */ 5709da57d7bSbt uint32_t free_list_size; /* Rx free list size */ 571ea65739eSchenlu chen - Sun Microsystems - Beijing China 572ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t rcb_pending; 573ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t flag; 574ea65739eSchenlu chen - Sun Microsystems - Beijing China 575ffd8e883SWinson Wang - Sun Microsystems - Beijing China uint32_t lro_num; /* Number of rcbs of one LRO */ 576ffd8e883SWinson Wang - Sun Microsystems - Beijing China uint32_t lro_first; /* Index of first LRO rcb */ 577ffd8e883SWinson Wang - Sun Microsystems - Beijing China 578ea65739eSchenlu chen - Sun Microsystems - Beijing China struct ixgbe_rx_ring *rx_ring; /* Pointer to rx ring */ 579ea65739eSchenlu chen - Sun Microsystems - Beijing China } ixgbe_rx_data_t; 580ea65739eSchenlu chen - Sun Microsystems - Beijing China 581ea65739eSchenlu chen - Sun Microsystems - Beijing China /* 582ea65739eSchenlu chen - Sun Microsystems - Beijing China * Software Data Structure for Rx Ring 583ea65739eSchenlu chen - Sun Microsystems - Beijing China */ 584ea65739eSchenlu chen - Sun Microsystems - Beijing China typedef struct ixgbe_rx_ring { 585ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t index; /* Ring index */ 5860dc2366fSVenugopal Iyer uint32_t group_index; /* Group index */ 5870dc2366fSVenugopal Iyer uint32_t hw_index; /* h/w ring index */ 588ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t intr_vector; /* Interrupt vector index */ 589ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t vect_bit; /* vector's bit in register */ 590ea65739eSchenlu chen - Sun Microsystems - Beijing China 591ea65739eSchenlu chen - Sun Microsystems - Beijing China ixgbe_rx_data_t *rx_data; /* Rx software ring */ 592ea65739eSchenlu chen - Sun Microsystems - Beijing China 593ea65739eSchenlu chen - Sun Microsystems - Beijing China kmutex_t rx_lock; /* Rx access lock */ 5949da57d7bSbt 5959da57d7bSbt uint32_t stat_frame_error; 5969da57d7bSbt uint32_t stat_cksum_error; 5979da57d7bSbt uint32_t stat_exceed_pkt; 598a9bfd41dSRyan Zezeski 5990dc2366fSVenugopal Iyer uint64_t stat_rbytes; 6000dc2366fSVenugopal Iyer uint64_t stat_ipackets; 6019da57d7bSbt 602da14cebeSEric Cheng mac_ring_handle_t ring_handle; 603da14cebeSEric Cheng uint64_t ring_gen_num; 6049da57d7bSbt 605da14cebeSEric Cheng struct ixgbe *ixgbe; /* Pointer to ixgbe struct */ 6069da57d7bSbt } ixgbe_rx_ring_t; 60784de666eSRyan Zezeski 608da14cebeSEric Cheng /* 609da14cebeSEric Cheng * Software Receive Ring Group 610da14cebeSEric Cheng */ 611da14cebeSEric Cheng typedef struct ixgbe_rx_group { 612da14cebeSEric Cheng uint32_t index; /* Group index */ 613da14cebeSEric Cheng mac_group_handle_t group_handle; /* call back group handle */ 614da14cebeSEric Cheng struct ixgbe *ixgbe; /* Pointer to ixgbe struct */ 61584de666eSRyan Zezeski boolean_t aupe; /* AUPE bit */ 61684de666eSRyan Zezeski list_t vlans; /* list of VLANs to allow */ 617da14cebeSEric Cheng } ixgbe_rx_group_t; 618da14cebeSEric Cheng 6199da57d7bSbt /* 62073cd555cSBin Tu - Sun Microsystems - Beijing China * structure to map interrupt cleanup to msi-x vector 6219da57d7bSbt */ 62273cd555cSBin Tu - Sun Microsystems - Beijing China typedef struct ixgbe_intr_vector { 6239da57d7bSbt struct ixgbe *ixgbe; /* point to my adapter */ 6249da57d7bSbt ulong_t rx_map[BT_BITOUL(MAX_RX_QUEUE_NUM)]; /* bitmap of rx rings */ 6259da57d7bSbt int rxr_cnt; /* count rx rings */ 6269da57d7bSbt ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)]; /* bitmap of tx rings */ 6279da57d7bSbt int txr_cnt; /* count tx rings */ 62873cd555cSBin Tu - Sun Microsystems - Beijing China ulong_t other_map[BT_BITOUL(2)]; /* bitmap of other */ 62973cd555cSBin Tu - Sun Microsystems - Beijing China int other_cnt; /* count other interrupt */ 63073cd555cSBin Tu - Sun Microsystems - Beijing China } ixgbe_intr_vector_t; 6319da57d7bSbt 6329da57d7bSbt /* 6339da57d7bSbt * Software adapter state 6349da57d7bSbt */ 6359da57d7bSbt typedef struct ixgbe { 636168e1ed4SRyan Zezeski int instance; 6379da57d7bSbt mac_handle_t mac_hdl; 6389da57d7bSbt dev_info_t *dip; 6399da57d7bSbt struct ixgbe_hw hw; 6409da57d7bSbt struct ixgbe_osdep osdep; 6419da57d7bSbt 64213740cb2SPaul Guo adapter_info_t *capab; /* adapter hardware capabilities */ 64362e6e1adSPaul Guo ddi_taskq_t *sfp_taskq; /* sfp-change taskq */ 6445b6dd21fSchenlu chen - Sun Microsystems - Beijing China ddi_taskq_t *overtemp_taskq; /* overtemp taskq */ 645dc0cb1cdSDale Ghent ddi_taskq_t *phy_taskq; /* external PHY taskq */ 64613740cb2SPaul Guo uint32_t eims; /* interrupt mask setting */ 64773cd555cSBin Tu - Sun Microsystems - Beijing China uint32_t eimc; /* interrupt mask clear */ 64873cd555cSBin Tu - Sun Microsystems - Beijing China uint32_t eicr; /* interrupt cause reg */ 64913740cb2SPaul Guo 6509da57d7bSbt uint32_t ixgbe_state; 6519da57d7bSbt link_state_t link_state; 6529da57d7bSbt uint32_t link_speed; 6539da57d7bSbt uint32_t link_duplex; 6549da57d7bSbt 6559da57d7bSbt uint32_t reset_count; 6569da57d7bSbt uint32_t attach_progress; 6579da57d7bSbt uint32_t loopback_mode; 6589da57d7bSbt uint32_t default_mtu; 6599da57d7bSbt uint32_t max_frame_size; 660dc0cb1cdSDale Ghent ixgbe_link_speed speeds_supported; 6619da57d7bSbt 662ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t rcb_pending; 663ea65739eSchenlu chen - Sun Microsystems - Beijing China 6649da57d7bSbt /* 66573cd555cSBin Tu - Sun Microsystems - Beijing China * Each msi-x vector: map vector to interrupt cleanup 6669da57d7bSbt */ 66773cd555cSBin Tu - Sun Microsystems - Beijing China ixgbe_intr_vector_t vect_map[MAX_INTR_VECTOR]; 6689da57d7bSbt 6699da57d7bSbt /* 6709da57d7bSbt * Receive Rings 6719da57d7bSbt */ 6729da57d7bSbt ixgbe_rx_ring_t *rx_rings; /* Array of rx rings */ 6739da57d7bSbt uint32_t num_rx_rings; /* Number of rx rings in use */ 6749da57d7bSbt uint32_t rx_ring_size; /* Rx descriptor ring size */ 6759da57d7bSbt uint32_t rx_buf_size; /* Rx buffer size */ 676ffd8e883SWinson Wang - Sun Microsystems - Beijing China boolean_t lro_enable; /* Large Receive Offload */ 677ffd8e883SWinson Wang - Sun Microsystems - Beijing China uint64_t lro_pkt_count; /* LRO packet count */ 678da14cebeSEric Cheng /* 679da14cebeSEric Cheng * Receive Groups 680da14cebeSEric Cheng */ 681da14cebeSEric Cheng ixgbe_rx_group_t *rx_groups; /* Array of rx groups */ 682da14cebeSEric Cheng uint32_t num_rx_groups; /* Number of rx groups in use */ 68384de666eSRyan Zezeski uint32_t rx_def_group; /* Default Rx group index */ 684da14cebeSEric Cheng 6859da57d7bSbt /* 6869da57d7bSbt * Transmit Rings 6879da57d7bSbt */ 6889da57d7bSbt ixgbe_tx_ring_t *tx_rings; /* Array of tx rings */ 6899da57d7bSbt uint32_t num_tx_rings; /* Number of tx rings in use */ 6909da57d7bSbt uint32_t tx_ring_size; /* Tx descriptor ring size */ 6919da57d7bSbt uint32_t tx_buf_size; /* Tx buffer size */ 6929da57d7bSbt 693ea65739eSchenlu chen - Sun Microsystems - Beijing China boolean_t tx_ring_init; 6949da57d7bSbt boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 6959da57d7bSbt boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 696168e1ed4SRyan Zezeski boolean_t lso_enable; /* Large Segment Offload */ 697168e1ed4SRyan Zezeski boolean_t mr_enable; /* Multiple Tx and Rx Ring */ 6985b6dd21fSchenlu chen - Sun Microsystems - Beijing China boolean_t relax_order_enable; /* Relax Order */ 6990dc2366fSVenugopal Iyer uint32_t classify_mode; /* Classification mode */ 7009da57d7bSbt uint32_t tx_copy_thresh; /* Tx copy threshold */ 7019da57d7bSbt uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 7029da57d7bSbt uint32_t tx_overload_thresh; /* Tx overload threshold */ 7039da57d7bSbt uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 7049da57d7bSbt boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 7059da57d7bSbt uint32_t rx_copy_thresh; /* Rx copy threshold */ 7069da57d7bSbt uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 70773cd555cSBin Tu - Sun Microsystems - Beijing China uint32_t intr_throttling[MAX_INTR_VECTOR]; 7089da57d7bSbt uint32_t intr_force; 7099da57d7bSbt int fm_capabilities; /* FMA capabilities */ 7109da57d7bSbt 7119da57d7bSbt int intr_type; 7129da57d7bSbt int intr_cnt; 7130dc2366fSVenugopal Iyer uint32_t intr_cnt_max; 7140dc2366fSVenugopal Iyer uint32_t intr_cnt_min; 7159da57d7bSbt int intr_cap; 7169da57d7bSbt size_t intr_size; 7179da57d7bSbt uint_t intr_pri; 7189da57d7bSbt ddi_intr_handle_t *htable; 7199da57d7bSbt uint32_t eims_mask; 7200dc2366fSVenugopal Iyer ddi_cb_handle_t cb_hdl; /* Interrupt callback handle */ 7219da57d7bSbt 7229da57d7bSbt kmutex_t gen_lock; /* General lock for device access */ 7239da57d7bSbt kmutex_t watchdog_lock; 724ea65739eSchenlu chen - Sun Microsystems - Beijing China kmutex_t rx_pending_lock; 7259da57d7bSbt 7269da57d7bSbt boolean_t watchdog_enable; 7279da57d7bSbt boolean_t watchdog_start; 7289da57d7bSbt timeout_id_t watchdog_tid; 7299da57d7bSbt 7309da57d7bSbt boolean_t unicst_init; 7319da57d7bSbt uint32_t unicst_avail; 7329da57d7bSbt uint32_t unicst_total; 7339da57d7bSbt ixgbe_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 7349da57d7bSbt uint32_t mcast_count; 7359da57d7bSbt struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 7369da57d7bSbt 73784de666eSRyan Zezeski boolean_t vlft_enabled; /* VLAN filtering enabled? */ 73884de666eSRyan Zezeski boolean_t vlft_init; /* VLAN filtering initialized? */ 73984de666eSRyan Zezeski 740da14cebeSEric Cheng ulong_t sys_page_size; 741da14cebeSEric Cheng 74262e6e1adSPaul Guo boolean_t link_check_complete; 74362e6e1adSPaul Guo hrtime_t link_check_hrtime; 74462e6e1adSPaul Guo ddi_periodic_t periodic_id; /* for link check timer func */ 74562e6e1adSPaul Guo 74637367bbaSRobert Mustacchi /* 74737367bbaSRobert Mustacchi * LED related constants. 74837367bbaSRobert Mustacchi */ 74937367bbaSRobert Mustacchi boolean_t ixgbe_led_active; 75037367bbaSRobert Mustacchi boolean_t ixgbe_led_blink; 75137367bbaSRobert Mustacchi uint32_t ixgbe_led_reg; 75237367bbaSRobert Mustacchi uint32_t ixgbe_led_index; 75337367bbaSRobert Mustacchi 754*f2fe7acaSRobert Mustacchi /* 755*f2fe7acaSRobert Mustacchi * UFM state 756*f2fe7acaSRobert Mustacchi */ 757*f2fe7acaSRobert Mustacchi ddi_ufm_handle_t *ixgbe_ufmh; 758*f2fe7acaSRobert Mustacchi 7599da57d7bSbt /* 7609da57d7bSbt * Kstat definitions 7619da57d7bSbt */ 7629da57d7bSbt kstat_t *ixgbe_ks; 7639da57d7bSbt 764ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t param_en_10000fdx_cap:1, 765dc0cb1cdSDale Ghent param_en_5000fdx_cap:1, 766dc0cb1cdSDale Ghent param_en_2500fdx_cap:1, 767ea65739eSchenlu chen - Sun Microsystems - Beijing China param_en_1000fdx_cap:1, 768ea65739eSchenlu chen - Sun Microsystems - Beijing China param_en_100fdx_cap:1, 769ea65739eSchenlu chen - Sun Microsystems - Beijing China param_adv_10000fdx_cap:1, 770dc0cb1cdSDale Ghent param_adv_5000fdx_cap:1, 771dc0cb1cdSDale Ghent param_adv_2500fdx_cap:1, 772ea65739eSchenlu chen - Sun Microsystems - Beijing China param_adv_1000fdx_cap:1, 773ea65739eSchenlu chen - Sun Microsystems - Beijing China param_adv_100fdx_cap:1, 774ea65739eSchenlu chen - Sun Microsystems - Beijing China param_pause_cap:1, 775ea65739eSchenlu chen - Sun Microsystems - Beijing China param_asym_pause_cap:1, 776ea65739eSchenlu chen - Sun Microsystems - Beijing China param_rem_fault:1, 777ea65739eSchenlu chen - Sun Microsystems - Beijing China param_adv_autoneg_cap:1, 778ea65739eSchenlu chen - Sun Microsystems - Beijing China param_adv_pause_cap:1, 779ea65739eSchenlu chen - Sun Microsystems - Beijing China param_adv_asym_pause_cap:1, 780ea65739eSchenlu chen - Sun Microsystems - Beijing China param_adv_rem_fault:1, 781ea65739eSchenlu chen - Sun Microsystems - Beijing China param_lp_10000fdx_cap:1, 782dc0cb1cdSDale Ghent param_lp_5000fdx_cap:1, 783dc0cb1cdSDale Ghent param_lp_2500fdx_cap:1, 784ea65739eSchenlu chen - Sun Microsystems - Beijing China param_lp_1000fdx_cap:1, 785ea65739eSchenlu chen - Sun Microsystems - Beijing China param_lp_100fdx_cap:1, 786ea65739eSchenlu chen - Sun Microsystems - Beijing China param_lp_autoneg_cap:1, 787ea65739eSchenlu chen - Sun Microsystems - Beijing China param_lp_pause_cap:1, 788ea65739eSchenlu chen - Sun Microsystems - Beijing China param_lp_asym_pause_cap:1, 7891fedc51fSWinson Wang - Sun Microsystems - Beijing China param_lp_rem_fault:1, 790dc0cb1cdSDale Ghent param_pad_to_32:6; 7919da57d7bSbt } ixgbe_t; 7929da57d7bSbt 7939da57d7bSbt typedef struct ixgbe_stat { 7949da57d7bSbt kstat_named_t link_speed; /* Link Speed */ 795da14cebeSEric Cheng 7969da57d7bSbt kstat_named_t reset_count; /* Reset Count */ 7979da57d7bSbt 7989da57d7bSbt kstat_named_t rx_frame_error; /* Rx Error in Packet */ 7999da57d7bSbt kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 8009da57d7bSbt kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 8019da57d7bSbt 8029da57d7bSbt kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 8039da57d7bSbt kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 8049da57d7bSbt kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 8059da57d7bSbt kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 8069da57d7bSbt kstat_named_t tx_reschedule; /* Tx Reschedule */ 80763efadf0SRyan Zezeski kstat_named_t tx_break_tbd_limit; /* Reached single xmit desc limit */ 80863efadf0SRyan Zezeski kstat_named_t tx_lso_header_fail; /* New mblk for last LSO hdr frag */ 8099da57d7bSbt 8109da57d7bSbt kstat_named_t gprc; /* Good Packets Received Count */ 8119da57d7bSbt kstat_named_t gptc; /* Good Packets Xmitted Count */ 8129da57d7bSbt kstat_named_t gor; /* Good Octets Received Count */ 8139da57d7bSbt kstat_named_t got; /* Good Octets Xmitd Count */ 814168e1ed4SRyan Zezeski kstat_named_t qor; /* Queue Octets Received */ 815168e1ed4SRyan Zezeski kstat_named_t qot; /* Queue Octets Transmitted */ 816168e1ed4SRyan Zezeski kstat_named_t qpr; /* Queue Packets Received */ 817168e1ed4SRyan Zezeski kstat_named_t qpt; /* Queue Packets Transmitted */ 8189da57d7bSbt kstat_named_t prc64; /* Packets Received - 64b */ 8199da57d7bSbt kstat_named_t prc127; /* Packets Received - 65-127b */ 8209da57d7bSbt kstat_named_t prc255; /* Packets Received - 127-255b */ 8219da57d7bSbt kstat_named_t prc511; /* Packets Received - 256-511b */ 8229da57d7bSbt kstat_named_t prc1023; /* Packets Received - 511-1023b */ 8239da57d7bSbt kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 8249da57d7bSbt kstat_named_t ptc64; /* Packets Xmitted (64b) */ 8259da57d7bSbt kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 8269da57d7bSbt kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 8279da57d7bSbt kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 8289da57d7bSbt kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 8299da57d7bSbt kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 830da14cebeSEric Cheng 8319da57d7bSbt kstat_named_t crcerrs; /* CRC Error Count */ 8329da57d7bSbt kstat_named_t illerrc; /* Illegal Byte Error Count */ 8339da57d7bSbt kstat_named_t errbc; /* Error Byte Count */ 8349da57d7bSbt kstat_named_t mspdc; /* MAC Short Packet Discard Count */ 8359da57d7bSbt kstat_named_t mpc; /* Missed Packets Count */ 8369da57d7bSbt kstat_named_t mlfc; /* MAC Local Fault Count */ 8379da57d7bSbt kstat_named_t mrfc; /* MAC Remote Fault Count */ 8389da57d7bSbt kstat_named_t rlec; /* Receive Length Error Count */ 8399da57d7bSbt kstat_named_t lxontxc; /* Link XON Transmitted Count */ 8409da57d7bSbt kstat_named_t lxonrxc; /* Link XON Received Count */ 8419da57d7bSbt kstat_named_t lxofftxc; /* Link XOFF Transmitted Count */ 8429da57d7bSbt kstat_named_t lxoffrxc; /* Link XOFF Received Count */ 8439da57d7bSbt kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 8449da57d7bSbt kstat_named_t mprc; /* Multicast Pkts Received Count */ 8459da57d7bSbt kstat_named_t rnbc; /* Receive No Buffers Count */ 8469da57d7bSbt kstat_named_t ruc; /* Receive Undersize Count */ 8479da57d7bSbt kstat_named_t rfc; /* Receive Frag Count */ 8489da57d7bSbt kstat_named_t roc; /* Receive Oversize Count */ 8499da57d7bSbt kstat_named_t rjc; /* Receive Jabber Count */ 8509da57d7bSbt kstat_named_t tor; /* Total Octets Recvd Count */ 851f27d3025Sgg kstat_named_t tot; /* Total Octets Xmitted Count */ 8529da57d7bSbt kstat_named_t tpr; /* Total Packets Received */ 8539da57d7bSbt kstat_named_t tpt; /* Total Packets Xmitted */ 8549da57d7bSbt kstat_named_t mptc; /* Multicast Packets Xmited Count */ 8559da57d7bSbt kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 856ffd8e883SWinson Wang - Sun Microsystems - Beijing China kstat_named_t lroc; /* LRO Packets Received Count */ 85774b989c3SRobert Mustacchi kstat_named_t dev_gone; /* Number of device gone events encountered */ 8589da57d7bSbt } ixgbe_stat_t; 8599da57d7bSbt 8609da57d7bSbt /* 8619da57d7bSbt * Function prototypes in ixgbe_buf.c 8629da57d7bSbt */ 8639da57d7bSbt int ixgbe_alloc_dma(ixgbe_t *); 8649da57d7bSbt void ixgbe_free_dma(ixgbe_t *); 865837c1ac4SStephen Hanson void ixgbe_set_fma_flags(int); 866ea65739eSchenlu chen - Sun Microsystems - Beijing China void ixgbe_free_dma_buffer(dma_buffer_t *); 867ea65739eSchenlu chen - Sun Microsystems - Beijing China int ixgbe_alloc_rx_ring_data(ixgbe_rx_ring_t *rx_ring); 868ea65739eSchenlu chen - Sun Microsystems - Beijing China void ixgbe_free_rx_ring_data(ixgbe_rx_data_t *rx_data); 8699da57d7bSbt 8709da57d7bSbt /* 8719da57d7bSbt * Function prototypes in ixgbe_main.c 8729da57d7bSbt */ 873ea65739eSchenlu chen - Sun Microsystems - Beijing China int ixgbe_start(ixgbe_t *, boolean_t); 874ea65739eSchenlu chen - Sun Microsystems - Beijing China void ixgbe_stop(ixgbe_t *, boolean_t); 8759da57d7bSbt int ixgbe_driver_setup_link(ixgbe_t *, boolean_t); 8769da57d7bSbt int ixgbe_multicst_add(ixgbe_t *, const uint8_t *); 8779da57d7bSbt int ixgbe_multicst_remove(ixgbe_t *, const uint8_t *); 8789da57d7bSbt enum ioc_reply ixgbe_loopback_ioctl(ixgbe_t *, struct iocblk *, mblk_t *); 8799da57d7bSbt 8809da57d7bSbt void ixgbe_enable_watchdog_timer(ixgbe_t *); 8819da57d7bSbt void ixgbe_disable_watchdog_timer(ixgbe_t *); 8829da57d7bSbt int ixgbe_atomic_reserve(uint32_t *, uint32_t); 8839da57d7bSbt 8849da57d7bSbt int ixgbe_check_acc_handle(ddi_acc_handle_t handle); 8859da57d7bSbt int ixgbe_check_dma_handle(ddi_dma_handle_t handle); 8869da57d7bSbt void ixgbe_fm_ereport(ixgbe_t *, char *); 8879da57d7bSbt 888da14cebeSEric Cheng void ixgbe_fill_ring(void *, mac_ring_type_t, const int, const int, 889da14cebeSEric Cheng mac_ring_info_t *, mac_ring_handle_t); 890da14cebeSEric Cheng void ixgbe_fill_group(void *arg, mac_ring_type_t, const int, 891da14cebeSEric Cheng mac_group_info_t *, mac_group_handle_t); 892da14cebeSEric Cheng int ixgbe_rx_ring_intr_enable(mac_intr_handle_t); 893da14cebeSEric Cheng int ixgbe_rx_ring_intr_disable(mac_intr_handle_t); 894da14cebeSEric Cheng 89545d3dd98SRobert Mustacchi int ixgbe_transceiver_info(void *, uint_t, mac_transceiver_info_t *); 89645d3dd98SRobert Mustacchi int ixgbe_transceiver_read(void *, uint_t, uint_t, void *, size_t, off_t, 89745d3dd98SRobert Mustacchi size_t *); 89845d3dd98SRobert Mustacchi 8999da57d7bSbt /* 9009da57d7bSbt * Function prototypes in ixgbe_gld.c 9019da57d7bSbt */ 9029da57d7bSbt int ixgbe_m_start(void *); 9039da57d7bSbt void ixgbe_m_stop(void *); 9049da57d7bSbt int ixgbe_m_promisc(void *, boolean_t); 9059da57d7bSbt int ixgbe_m_multicst(void *, boolean_t, const uint8_t *); 9069da57d7bSbt void ixgbe_m_resources(void *); 9079da57d7bSbt void ixgbe_m_ioctl(void *, queue_t *, mblk_t *); 9089da57d7bSbt boolean_t ixgbe_m_getcapab(void *, mac_capab_t, void *); 909ea65739eSchenlu chen - Sun Microsystems - Beijing China int ixgbe_m_setprop(void *, const char *, mac_prop_id_t, uint_t, const void *); 9100dc2366fSVenugopal Iyer int ixgbe_m_getprop(void *, const char *, mac_prop_id_t, uint_t, void *); 9110dc2366fSVenugopal Iyer void ixgbe_m_propinfo(void *, const char *, mac_prop_id_t, 9120dc2366fSVenugopal Iyer mac_prop_info_handle_t); 913ea65739eSchenlu chen - Sun Microsystems - Beijing China int ixgbe_set_priv_prop(ixgbe_t *, const char *, uint_t, const void *); 9140dc2366fSVenugopal Iyer int ixgbe_get_priv_prop(ixgbe_t *, const char *, uint_t, void *); 915ea65739eSchenlu chen - Sun Microsystems - Beijing China boolean_t ixgbe_param_locked(mac_prop_id_t); 9169da57d7bSbt 9179da57d7bSbt /* 9189da57d7bSbt * Function prototypes in ixgbe_rx.c 9199da57d7bSbt */ 920da14cebeSEric Cheng mblk_t *ixgbe_ring_rx(ixgbe_rx_ring_t *, int); 9219da57d7bSbt void ixgbe_rx_recycle(caddr_t arg); 922da14cebeSEric Cheng mblk_t *ixgbe_ring_rx_poll(void *, int); 9239da57d7bSbt 9249da57d7bSbt /* 9259da57d7bSbt * Function prototypes in ixgbe_tx.c 9269da57d7bSbt */ 927da14cebeSEric Cheng mblk_t *ixgbe_ring_tx(void *, mblk_t *); 9289da57d7bSbt void ixgbe_free_tcb(tx_control_block_t *); 9299da57d7bSbt void ixgbe_put_free_list(ixgbe_tx_ring_t *, link_list_t *); 9309da57d7bSbt uint32_t ixgbe_tx_recycle_legacy(ixgbe_tx_ring_t *); 9319da57d7bSbt uint32_t ixgbe_tx_recycle_head_wb(ixgbe_tx_ring_t *); 9329da57d7bSbt 9339da57d7bSbt /* 9349da57d7bSbt * Function prototypes in ixgbe_log.c 9359da57d7bSbt */ 9369da57d7bSbt void ixgbe_notice(void *, const char *, ...); 9379da57d7bSbt void ixgbe_log(void *, const char *, ...); 9389da57d7bSbt void ixgbe_error(void *, const char *, ...); 9399da57d7bSbt 9409da57d7bSbt /* 9419da57d7bSbt * Function prototypes in ixgbe_stat.c 9429da57d7bSbt */ 9439da57d7bSbt int ixgbe_init_stats(ixgbe_t *); 9440dc2366fSVenugopal Iyer int ixgbe_m_stat(void *, uint_t, uint64_t *); 9450dc2366fSVenugopal Iyer int ixgbe_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 9460dc2366fSVenugopal Iyer int ixgbe_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 9479da57d7bSbt 9489da57d7bSbt #ifdef __cplusplus 9499da57d7bSbt } 9509da57d7bSbt #endif 9519da57d7bSbt 9529da57d7bSbt #endif /* _IXGBE_SW_H */ 953