19da57d7bSbt /* 29da57d7bSbt * CDDL HEADER START 39da57d7bSbt * 49da57d7bSbt * The contents of this file are subject to the terms of the 59da57d7bSbt * Common Development and Distribution License (the "License"). 69da57d7bSbt * You may not use this file except in compliance with the License. 79da57d7bSbt * 8da14cebeSEric Cheng * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9da14cebeSEric Cheng * or http://www.opensolaris.org/os/licensing. 109da57d7bSbt * See the License for the specific language governing permissions 119da57d7bSbt * and limitations under the License. 129da57d7bSbt * 13da14cebeSEric Cheng * When distributing Covered Code, include this CDDL HEADER in each 14da14cebeSEric Cheng * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 159da57d7bSbt * If applicable, add the following below this CDDL HEADER, with the 169da57d7bSbt * fields enclosed by brackets "[]" replaced with your own identifying 179da57d7bSbt * information: Portions Copyright [yyyy] [name of copyright owner] 189da57d7bSbt * 199da57d7bSbt * CDDL HEADER END 209da57d7bSbt */ 219da57d7bSbt 229da57d7bSbt /* 235b6dd21fSchenlu chen - Sun Microsystems - Beijing China * Copyright(c) 2007-2010 Intel Corporation. All rights reserved. 245b6dd21fSchenlu chen - Sun Microsystems - Beijing China */ 255b6dd21fSchenlu chen - Sun Microsystems - Beijing China 265b6dd21fSchenlu chen - Sun Microsystems - Beijing China /* 275b6dd21fSchenlu chen - Sun Microsystems - Beijing China * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 2843fab1a9SSaso Kiselkov * Copyright (c) 2013 Saso Kiselkov. All rights reserved. 29*dc0cb1cdSDale Ghent * Copyright 2016 OmniTI Computer Consulting, Inc. All rights reserved. 309da57d7bSbt */ 319da57d7bSbt 329da57d7bSbt #ifndef _IXGBE_SW_H 339da57d7bSbt #define _IXGBE_SW_H 349da57d7bSbt 359da57d7bSbt #ifdef __cplusplus 369da57d7bSbt extern "C" { 379da57d7bSbt #endif 389da57d7bSbt 399da57d7bSbt #include <sys/types.h> 409da57d7bSbt #include <sys/conf.h> 419da57d7bSbt #include <sys/debug.h> 429da57d7bSbt #include <sys/stropts.h> 439da57d7bSbt #include <sys/stream.h> 449da57d7bSbt #include <sys/strsun.h> 459da57d7bSbt #include <sys/strlog.h> 469da57d7bSbt #include <sys/kmem.h> 479da57d7bSbt #include <sys/stat.h> 489da57d7bSbt #include <sys/kstat.h> 499da57d7bSbt #include <sys/modctl.h> 509da57d7bSbt #include <sys/errno.h> 519da57d7bSbt #include <sys/dlpi.h> 52da14cebeSEric Cheng #include <sys/mac_provider.h> 539da57d7bSbt #include <sys/mac_ether.h> 549da57d7bSbt #include <sys/vlan.h> 559da57d7bSbt #include <sys/ddi.h> 569da57d7bSbt #include <sys/sunddi.h> 579da57d7bSbt #include <sys/pci.h> 589da57d7bSbt #include <sys/pcie.h> 599da57d7bSbt #include <sys/sdt.h> 609da57d7bSbt #include <sys/ethernet.h> 619da57d7bSbt #include <sys/pattr.h> 629da57d7bSbt #include <sys/strsubr.h> 639da57d7bSbt #include <sys/netlb.h> 649da57d7bSbt #include <sys/random.h> 659da57d7bSbt #include <inet/common.h> 66c971fb7eSgg #include <inet/tcp.h> 679da57d7bSbt #include <inet/ip.h> 689da57d7bSbt #include <inet/mi.h> 699da57d7bSbt #include <inet/nd.h> 709da57d7bSbt #include <sys/bitmap.h> 719da57d7bSbt #include <sys/ddifm.h> 729da57d7bSbt #include <sys/fm/protocol.h> 739da57d7bSbt #include <sys/fm/util.h> 7462e6e1adSPaul Guo #include <sys/disp.h> 759da57d7bSbt #include <sys/fm/io/ddi.h> 769da57d7bSbt #include "ixgbe_api.h" 779da57d7bSbt 789da57d7bSbt #define MODULE_NAME "ixgbe" /* module name */ 799da57d7bSbt 809da57d7bSbt #define IXGBE_FAILURE DDI_FAILURE 819da57d7bSbt 829da57d7bSbt #define IXGBE_UNKNOWN 0x00 839da57d7bSbt #define IXGBE_INITIALIZED 0x01 849da57d7bSbt #define IXGBE_STARTED 0x02 859da57d7bSbt #define IXGBE_SUSPENDED 0x04 8662e6e1adSPaul Guo #define IXGBE_STALL 0x08 875b6dd21fSchenlu chen - Sun Microsystems - Beijing China #define IXGBE_OVERTEMP 0x20 880dc2366fSVenugopal Iyer #define IXGBE_INTR_ADJUST 0x40 8962e6e1adSPaul Guo #define IXGBE_ERROR 0x80 909da57d7bSbt 910dc2366fSVenugopal Iyer #define MAX_NUM_UNICAST_ADDRESSES 0x80 929da57d7bSbt #define MAX_NUM_MULTICAST_ADDRESSES 0x1000 939da57d7bSbt #define IXGBE_INTR_NONE 0 949da57d7bSbt #define IXGBE_INTR_MSIX 1 959da57d7bSbt #define IXGBE_INTR_MSI 2 969da57d7bSbt #define IXGBE_INTR_LEGACY 3 979da57d7bSbt 98da14cebeSEric Cheng #define IXGBE_POLL_NULL -1 99da14cebeSEric Cheng 100c971fb7eSgg #define MAX_COOKIE 18 1019da57d7bSbt #define MIN_NUM_TX_DESC 2 1029da57d7bSbt 103edf70dc9SPaul Guo #define IXGBE_TX_DESC_LIMIT 32 /* tx desc limitation */ 104edf70dc9SPaul Guo 10573cd555cSBin Tu - Sun Microsystems - Beijing China #define IXGBE_ADAPTER_REGSET 1 /* map adapter registers */ 10673cd555cSBin Tu - Sun Microsystems - Beijing China 107ea65739eSchenlu chen - Sun Microsystems - Beijing China #define IXGBE_RX_STOPPED 0x1 108ea65739eSchenlu chen - Sun Microsystems - Beijing China 109ffd8e883SWinson Wang - Sun Microsystems - Beijing China #define IXGBE_PKG_BUF_16k 16384 110ffd8e883SWinson Wang - Sun Microsystems - Beijing China 1119da57d7bSbt /* 11273cd555cSBin Tu - Sun Microsystems - Beijing China * MAX_xx_QUEUE_NUM and MAX_INTR_VECTOR values need to be the maximum of all 11313740cb2SPaul Guo * supported silicon types. 1149da57d7bSbt */ 11573cd555cSBin Tu - Sun Microsystems - Beijing China #define MAX_TX_QUEUE_NUM 128 11673cd555cSBin Tu - Sun Microsystems - Beijing China #define MAX_RX_QUEUE_NUM 128 11773cd555cSBin Tu - Sun Microsystems - Beijing China #define MAX_INTR_VECTOR 64 1189da57d7bSbt 1199da57d7bSbt /* 12013740cb2SPaul Guo * Maximum values for user configurable parameters 1219da57d7bSbt */ 1229da57d7bSbt #define MAX_TX_RING_SIZE 4096 1239da57d7bSbt #define MAX_RX_RING_SIZE 4096 1249da57d7bSbt 1259da57d7bSbt #define MAX_RX_LIMIT_PER_INTR 4096 1269da57d7bSbt 1279da57d7bSbt #define MAX_RX_COPY_THRESHOLD 9216 1289da57d7bSbt #define MAX_TX_COPY_THRESHOLD 9216 1299da57d7bSbt #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 1309da57d7bSbt #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 1319da57d7bSbt #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 1329da57d7bSbt 1339da57d7bSbt /* 1349da57d7bSbt * Minimum values for user configurable parameters 1359da57d7bSbt */ 1369da57d7bSbt #define MIN_TX_RING_SIZE 64 1379da57d7bSbt #define MIN_RX_RING_SIZE 64 1389da57d7bSbt 1399da57d7bSbt #define MIN_MTU ETHERMIN 1409da57d7bSbt #define MIN_RX_LIMIT_PER_INTR 16 1419da57d7bSbt #define MIN_TX_COPY_THRESHOLD 0 1429da57d7bSbt #define MIN_RX_COPY_THRESHOLD 0 1439da57d7bSbt #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 1449da57d7bSbt #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 1459da57d7bSbt #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 1469da57d7bSbt 1479da57d7bSbt /* 1489da57d7bSbt * Default values for user configurable parameters 1499da57d7bSbt */ 150da14cebeSEric Cheng #define DEFAULT_TX_RING_SIZE 1024 151da14cebeSEric Cheng #define DEFAULT_RX_RING_SIZE 1024 1529da57d7bSbt 1539da57d7bSbt #define DEFAULT_MTU ETHERMTU 1549da57d7bSbt #define DEFAULT_RX_LIMIT_PER_INTR 256 1559da57d7bSbt #define DEFAULT_RX_COPY_THRESHOLD 128 1569da57d7bSbt #define DEFAULT_TX_COPY_THRESHOLD 512 157da14cebeSEric Cheng #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1) 1589da57d7bSbt #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 1599da57d7bSbt #define DEFAULT_TX_RESCHED_THRESHOLD 128 1609da57d7bSbt #define DEFAULT_FCRTH 0x20000 1619da57d7bSbt #define DEFAULT_FCRTL 0x10000 1629da57d7bSbt #define DEFAULT_FCPAUSE 0xFFFF 1639da57d7bSbt 164da14cebeSEric Cheng #define DEFAULT_TX_HCKSUM_ENABLE B_TRUE 165da14cebeSEric Cheng #define DEFAULT_RX_HCKSUM_ENABLE B_TRUE 166da14cebeSEric Cheng #define DEFAULT_LSO_ENABLE B_TRUE 167ffd8e883SWinson Wang - Sun Microsystems - Beijing China #define DEFAULT_LRO_ENABLE B_FALSE 168da14cebeSEric Cheng #define DEFAULT_MR_ENABLE B_TRUE 169da14cebeSEric Cheng #define DEFAULT_TX_HEAD_WB_ENABLE B_TRUE 1705b6dd21fSchenlu chen - Sun Microsystems - Beijing China #define DEFAULT_RELAX_ORDER_ENABLE B_TRUE 17143fab1a9SSaso Kiselkov #define DEFAULT_ALLOW_UNSUPPORTED_SFP B_FALSE 172da14cebeSEric Cheng 173da14cebeSEric Cheng #define IXGBE_LSO_MAXLEN 65535 174da14cebeSEric Cheng 1759da57d7bSbt #define TX_DRAIN_TIME 200 1769da57d7bSbt #define RX_DRAIN_TIME 200 1779da57d7bSbt 1789da57d7bSbt #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 1799da57d7bSbt #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */ 1809da57d7bSbt 18162e6e1adSPaul Guo #define IXGBE_CYCLIC_PERIOD (1000000000) /* 1s */ 18262e6e1adSPaul Guo 1839da57d7bSbt /* 1849da57d7bSbt * Extra register bit masks for 82598 1859da57d7bSbt */ 1869da57d7bSbt #define IXGBE_PCS1GANA_FDC 0x20 1879da57d7bSbt #define IXGBE_PCS1GANLP_LPFD 0x20 1889da57d7bSbt #define IXGBE_PCS1GANLP_LPHD 0x40 1899da57d7bSbt 1909da57d7bSbt /* 1919da57d7bSbt * Defined for IP header alignment. 1929da57d7bSbt */ 1939da57d7bSbt #define IPHDR_ALIGN_ROOM 2 1949da57d7bSbt 1959da57d7bSbt /* 1969da57d7bSbt * Bit flags for attach_progress 1979da57d7bSbt */ 1989da57d7bSbt #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 1999da57d7bSbt #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 2009da57d7bSbt #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 2019da57d7bSbt #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 2029da57d7bSbt #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 2039da57d7bSbt #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 2049da57d7bSbt #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 2059da57d7bSbt #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */ 2069da57d7bSbt #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 2079da57d7bSbt #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 2089da57d7bSbt #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 2099da57d7bSbt #define ATTACH_PROGRESS_FM_INIT 0x2000 /* FMA initialized */ 21062e6e1adSPaul Guo #define ATTACH_PROGRESS_SFP_TASKQ 0x4000 /* SFP taskq created */ 21162e6e1adSPaul Guo #define ATTACH_PROGRESS_LINK_TIMER 0x8000 /* link check timer */ 2125b6dd21fSchenlu chen - Sun Microsystems - Beijing China #define ATTACH_PROGRESS_OVERTEMP_TASKQ 0x10000 /* Over-temp taskq created */ 213*dc0cb1cdSDale Ghent #define ATTACH_PROGRESS_PHY_TASKQ 0x20000 /* Ext. PHY taskq created */ 2149da57d7bSbt 2159da57d7bSbt #define PROP_DEFAULT_MTU "default_mtu" 2169da57d7bSbt #define PROP_FLOW_CONTROL "flow_control" 2179da57d7bSbt #define PROP_TX_QUEUE_NUM "tx_queue_number" 2189da57d7bSbt #define PROP_TX_RING_SIZE "tx_ring_size" 2199da57d7bSbt #define PROP_RX_QUEUE_NUM "rx_queue_number" 2209da57d7bSbt #define PROP_RX_RING_SIZE "rx_ring_size" 221da14cebeSEric Cheng #define PROP_RX_GROUP_NUM "rx_group_number" 2229da57d7bSbt 2239da57d7bSbt #define PROP_INTR_FORCE "intr_force" 2249da57d7bSbt #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 2259da57d7bSbt #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 2269da57d7bSbt #define PROP_LSO_ENABLE "lso_enable" 227ffd8e883SWinson Wang - Sun Microsystems - Beijing China #define PROP_LRO_ENABLE "lro_enable" 228da14cebeSEric Cheng #define PROP_MR_ENABLE "mr_enable" 2295b6dd21fSchenlu chen - Sun Microsystems - Beijing China #define PROP_RELAX_ORDER_ENABLE "relax_order_enable" 2309da57d7bSbt #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 2319da57d7bSbt #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 2329da57d7bSbt #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 2339da57d7bSbt #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 2349da57d7bSbt #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 2359da57d7bSbt #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 2369da57d7bSbt #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 2379da57d7bSbt #define PROP_INTR_THROTTLING "intr_throttling" 2389da57d7bSbt #define PROP_FM_CAPABLE "fm_capable" 23943fab1a9SSaso Kiselkov #define PROP_ALLOW_UNSUPPORTED_SFP "allow_unsupported_sfp" 2409da57d7bSbt 2419da57d7bSbt #define IXGBE_LB_NONE 0 2429da57d7bSbt #define IXGBE_LB_EXTERNAL 1 2439da57d7bSbt #define IXGBE_LB_INTERNAL_MAC 2 2449da57d7bSbt #define IXGBE_LB_INTERNAL_PHY 3 2459da57d7bSbt #define IXGBE_LB_INTERNAL_SERDES 4 2469da57d7bSbt 24713740cb2SPaul Guo /* 24813740cb2SPaul Guo * capability/feature flags 24913740cb2SPaul Guo * Flags named _CAPABLE are set when the NIC hardware is capable of the feature. 25013740cb2SPaul Guo * Separately, the flag named _ENABLED is set when the feature is enabled. 25113740cb2SPaul Guo */ 25213740cb2SPaul Guo #define IXGBE_FLAG_DCA_ENABLED (u32)(1) 25313740cb2SPaul Guo #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 1) 25413740cb2SPaul Guo #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 2) 25513740cb2SPaul Guo #define IXGBE_FLAG_DCB_CAPABLE (u32)(1 << 4) 25613740cb2SPaul Guo #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 4) 25713740cb2SPaul Guo #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 5) 25813740cb2SPaul Guo #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 6) 25913740cb2SPaul Guo #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 7) 26013740cb2SPaul Guo #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 8) 261ffd8e883SWinson Wang - Sun Microsystems - Beijing China #define IXGBE_FLAG_RSC_CAPABLE (u32)(1 << 9) 2625b6dd21fSchenlu chen - Sun Microsystems - Beijing China #define IXGBE_FLAG_SFP_PLUG_CAPABLE (u32)(1 << 10) 2635b6dd21fSchenlu chen - Sun Microsystems - Beijing China #define IXGBE_FLAG_TEMP_SENSOR_CAPABLE (u32)(1 << 11) 26413740cb2SPaul Guo 2650dc2366fSVenugopal Iyer /* 2660dc2366fSVenugopal Iyer * Classification mode 2670dc2366fSVenugopal Iyer */ 2680dc2366fSVenugopal Iyer #define IXGBE_CLASSIFY_NONE 0 2690dc2366fSVenugopal Iyer #define IXGBE_CLASSIFY_RSS 1 2700dc2366fSVenugopal Iyer #define IXGBE_CLASSIFY_VMDQ 2 2710dc2366fSVenugopal Iyer #define IXGBE_CLASSIFY_VMDQ_RSS 3 2720dc2366fSVenugopal Iyer 27313740cb2SPaul Guo /* adapter-specific info for each supported device type */ 27413740cb2SPaul Guo typedef struct adapter_info { 2750dc2366fSVenugopal Iyer uint32_t max_rx_que_num; /* maximum number of rx queues */ 2760dc2366fSVenugopal Iyer uint32_t min_rx_que_num; /* minimum number of rx queues */ 2770dc2366fSVenugopal Iyer uint32_t def_rx_que_num; /* default number of rx queues */ 2780dc2366fSVenugopal Iyer uint32_t max_rx_grp_num; /* maximum number of rx groups */ 2790dc2366fSVenugopal Iyer uint32_t min_rx_grp_num; /* minimum number of rx groups */ 2800dc2366fSVenugopal Iyer uint32_t def_rx_grp_num; /* default number of rx groups */ 28113740cb2SPaul Guo uint32_t max_tx_que_num; /* maximum number of tx queues */ 28213740cb2SPaul Guo uint32_t min_tx_que_num; /* minimum number of tx queues */ 28313740cb2SPaul Guo uint32_t def_tx_que_num; /* default number of tx queues */ 2841fedc51fSWinson Wang - Sun Microsystems - Beijing China uint32_t max_mtu; /* maximum MTU size */ 285ea65739eSchenlu chen - Sun Microsystems - Beijing China /* 286ea65739eSchenlu chen - Sun Microsystems - Beijing China * Interrupt throttling is in unit of 256 nsec 287ea65739eSchenlu chen - Sun Microsystems - Beijing China */ 288ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t max_intr_throttle; /* maximum interrupt throttle */ 289ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t min_intr_throttle; /* minimum interrupt throttle */ 290ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t def_intr_throttle; /* default interrupt throttle */ 291ea65739eSchenlu chen - Sun Microsystems - Beijing China 29213740cb2SPaul Guo uint32_t max_msix_vect; /* maximum total msix vectors */ 29313740cb2SPaul Guo uint32_t max_ring_vect; /* maximum number of ring vectors */ 29413740cb2SPaul Guo uint32_t max_other_vect; /* maximum number of other vectors */ 29513740cb2SPaul Guo uint32_t other_intr; /* "other" interrupt types handled */ 2965b6dd21fSchenlu chen - Sun Microsystems - Beijing China uint32_t other_gpie; /* "other" interrupt types enabling */ 29713740cb2SPaul Guo uint32_t flags; /* capability flags */ 29813740cb2SPaul Guo } adapter_info_t; 29913740cb2SPaul Guo 30013740cb2SPaul Guo /* bits representing all interrupt types other than tx & rx */ 30113740cb2SPaul Guo #define IXGBE_OTHER_INTR 0x3ff00000 30273cd555cSBin Tu - Sun Microsystems - Beijing China #define IXGBE_82599_OTHER_INTR 0x86100000 30313740cb2SPaul Guo 3049da57d7bSbt enum ioc_reply { 3059da57d7bSbt IOC_INVAL = -1, /* bad, NAK with EINVAL */ 3069da57d7bSbt IOC_DONE, /* OK, reply sent */ 3079da57d7bSbt IOC_ACK, /* OK, just send ACK */ 3089da57d7bSbt IOC_REPLY /* OK, just send reply */ 3099da57d7bSbt }; 3109da57d7bSbt 3119da57d7bSbt #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 3129da57d7bSbt 0, 0, (flag))) 3139da57d7bSbt 3149da57d7bSbt /* 3159da57d7bSbt * Defined for ring index operations 3169da57d7bSbt * ASSERT(index < limit) 3179da57d7bSbt * ASSERT(step < limit) 3189da57d7bSbt * ASSERT(index1 < limit) 3199da57d7bSbt * ASSERT(index2 < limit) 3209da57d7bSbt */ 3219da57d7bSbt #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 3229da57d7bSbt (index) + (step) : (index) + (step) - (limit)) 3239da57d7bSbt #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 3249da57d7bSbt (index) - (step) : (index) + (limit) - (step)) 3259da57d7bSbt #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 3269da57d7bSbt (index2) - (index1) : (index2) + (limit) - (index1)) 3279da57d7bSbt 3289da57d7bSbt #define LINK_LIST_INIT(_LH) \ 3299da57d7bSbt (_LH)->head = (_LH)->tail = NULL 3309da57d7bSbt 3319da57d7bSbt #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 3329da57d7bSbt 3339da57d7bSbt #define LIST_POP_HEAD(_LH) \ 3349da57d7bSbt (single_link_t *)(_LH)->head; \ 3359da57d7bSbt { \ 3369da57d7bSbt if ((_LH)->head != NULL) { \ 3379da57d7bSbt (_LH)->head = (_LH)->head->link; \ 3389da57d7bSbt if ((_LH)->head == NULL) \ 3399da57d7bSbt (_LH)->tail = NULL; \ 3409da57d7bSbt } \ 3419da57d7bSbt } 3429da57d7bSbt 3439da57d7bSbt #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 3449da57d7bSbt 3459da57d7bSbt #define LIST_PUSH_TAIL(_LH, _E) \ 3469da57d7bSbt if ((_LH)->tail != NULL) { \ 3479da57d7bSbt (_LH)->tail->link = (single_link_t *)(_E); \ 3489da57d7bSbt (_LH)->tail = (single_link_t *)(_E); \ 3499da57d7bSbt } else { \ 3509da57d7bSbt (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 3519da57d7bSbt } \ 3529da57d7bSbt (_E)->link = NULL; 3539da57d7bSbt 3549da57d7bSbt #define LIST_GET_NEXT(_LH, _E) \ 3559da57d7bSbt (((_LH)->tail == (single_link_t *)(_E)) ? \ 3569da57d7bSbt NULL : ((single_link_t *)(_E))->link) 3579da57d7bSbt 3589da57d7bSbt 3599da57d7bSbt typedef struct single_link { 3609da57d7bSbt struct single_link *link; 3619da57d7bSbt } single_link_t; 3629da57d7bSbt 3639da57d7bSbt typedef struct link_list { 3649da57d7bSbt single_link_t *head; 3659da57d7bSbt single_link_t *tail; 3669da57d7bSbt } link_list_t; 3679da57d7bSbt 3689da57d7bSbt /* 3699da57d7bSbt * Property lookups 3709da57d7bSbt */ 3719da57d7bSbt #define IXGBE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 3729da57d7bSbt DDI_PROP_DONTPASS, (n)) 3739da57d7bSbt #define IXGBE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 3749da57d7bSbt DDI_PROP_DONTPASS, (n), -1) 3759da57d7bSbt 3769da57d7bSbt 3779da57d7bSbt typedef union ixgbe_ether_addr { 3789da57d7bSbt struct { 3799da57d7bSbt uint32_t high; 3809da57d7bSbt uint32_t low; 3819da57d7bSbt } reg; 3829da57d7bSbt struct { 3839da57d7bSbt uint8_t set; 3840dc2366fSVenugopal Iyer uint8_t group_index; 3859da57d7bSbt uint8_t addr[ETHERADDRL]; 3869da57d7bSbt } mac; 3879da57d7bSbt } ixgbe_ether_addr_t; 3889da57d7bSbt 3899da57d7bSbt typedef enum { 3909da57d7bSbt USE_NONE, 3919da57d7bSbt USE_COPY, 3929da57d7bSbt USE_DMA 3939da57d7bSbt } tx_type_t; 3949da57d7bSbt 395c971fb7eSgg typedef struct ixgbe_tx_context { 3969da57d7bSbt uint32_t hcksum_flags; 3979da57d7bSbt uint32_t ip_hdr_len; 3989da57d7bSbt uint32_t mac_hdr_len; 3999da57d7bSbt uint32_t l4_proto; 400c971fb7eSgg uint32_t mss; 401c971fb7eSgg uint32_t l4_hdr_len; 402c971fb7eSgg boolean_t lso_flag; 403c971fb7eSgg } ixgbe_tx_context_t; 4049da57d7bSbt 4059da57d7bSbt /* 4069da57d7bSbt * Hold address/length of each DMA segment 4079da57d7bSbt */ 4089da57d7bSbt typedef struct sw_desc { 4099da57d7bSbt uint64_t address; 4109da57d7bSbt size_t length; 4119da57d7bSbt } sw_desc_t; 4129da57d7bSbt 4139da57d7bSbt /* 4149da57d7bSbt * Handles and addresses of DMA buffer 4159da57d7bSbt */ 4169da57d7bSbt typedef struct dma_buffer { 4179da57d7bSbt caddr_t address; /* Virtual address */ 4189da57d7bSbt uint64_t dma_address; /* DMA (Hardware) address */ 4199da57d7bSbt ddi_acc_handle_t acc_handle; /* Data access handle */ 4209da57d7bSbt ddi_dma_handle_t dma_handle; /* DMA handle */ 4219da57d7bSbt size_t size; /* Buffer size */ 4229da57d7bSbt size_t len; /* Data length in the buffer */ 4239da57d7bSbt } dma_buffer_t; 4249da57d7bSbt 4259da57d7bSbt /* 4269da57d7bSbt * Tx Control Block 4279da57d7bSbt */ 4289da57d7bSbt typedef struct tx_control_block { 4299da57d7bSbt single_link_t link; 430edf70dc9SPaul Guo uint32_t last_index; /* last descriptor of the pkt */ 4319da57d7bSbt uint32_t frag_num; 4329da57d7bSbt uint32_t desc_num; 4339da57d7bSbt mblk_t *mp; 4349da57d7bSbt tx_type_t tx_type; 4359da57d7bSbt ddi_dma_handle_t tx_dma_handle; 4369da57d7bSbt dma_buffer_t tx_buf; 4379da57d7bSbt sw_desc_t desc[MAX_COOKIE]; 4389da57d7bSbt } tx_control_block_t; 4399da57d7bSbt 4409da57d7bSbt /* 4419da57d7bSbt * RX Control Block 4429da57d7bSbt */ 4439da57d7bSbt typedef struct rx_control_block { 4449da57d7bSbt mblk_t *mp; 445ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t ref_cnt; 4469da57d7bSbt dma_buffer_t rx_buf; 4479da57d7bSbt frtn_t free_rtn; 448ea65739eSchenlu chen - Sun Microsystems - Beijing China struct ixgbe_rx_data *rx_data; 449ffd8e883SWinson Wang - Sun Microsystems - Beijing China int lro_next; /* Index of next rcb */ 450ffd8e883SWinson Wang - Sun Microsystems - Beijing China int lro_prev; /* Index of previous rcb */ 451ffd8e883SWinson Wang - Sun Microsystems - Beijing China boolean_t lro_pkt; /* Flag for LRO rcb */ 4529da57d7bSbt } rx_control_block_t; 4539da57d7bSbt 4549da57d7bSbt /* 4559da57d7bSbt * Software Data Structure for Tx Ring 4569da57d7bSbt */ 4579da57d7bSbt typedef struct ixgbe_tx_ring { 4589da57d7bSbt uint32_t index; /* Ring index */ 4599da57d7bSbt uint32_t intr_vector; /* Interrupt vector index */ 4609da57d7bSbt uint32_t vect_bit; /* vector's bit in register */ 4619da57d7bSbt 4629da57d7bSbt /* 4639da57d7bSbt * Mutexes 4649da57d7bSbt */ 4659da57d7bSbt kmutex_t tx_lock; 4669da57d7bSbt kmutex_t recycle_lock; 4679da57d7bSbt kmutex_t tcb_head_lock; 4689da57d7bSbt kmutex_t tcb_tail_lock; 4699da57d7bSbt 4709da57d7bSbt /* 4719da57d7bSbt * Tx descriptor ring definitions 4729da57d7bSbt */ 4739da57d7bSbt dma_buffer_t tbd_area; 4749da57d7bSbt union ixgbe_adv_tx_desc *tbd_ring; 4759da57d7bSbt uint32_t tbd_head; /* Index of next tbd to recycle */ 4769da57d7bSbt uint32_t tbd_tail; /* Index of next tbd to transmit */ 4779da57d7bSbt uint32_t tbd_free; /* Number of free tbd */ 4789da57d7bSbt 4799da57d7bSbt /* 4809da57d7bSbt * Tx control block list definitions 4819da57d7bSbt */ 4829da57d7bSbt tx_control_block_t *tcb_area; 4839da57d7bSbt tx_control_block_t **work_list; 4849da57d7bSbt tx_control_block_t **free_list; 4859da57d7bSbt uint32_t tcb_head; /* Head index of free list */ 4869da57d7bSbt uint32_t tcb_tail; /* Tail index of free list */ 4879da57d7bSbt uint32_t tcb_free; /* Number of free tcb in free list */ 4889da57d7bSbt 4899da57d7bSbt uint32_t *tbd_head_wb; /* Head write-back */ 4909da57d7bSbt uint32_t (*tx_recycle)(struct ixgbe_tx_ring *); 4919da57d7bSbt 4929da57d7bSbt /* 493c971fb7eSgg * s/w context structure for TCP/UDP checksum offload 494c971fb7eSgg * and LSO. 4959da57d7bSbt */ 496c971fb7eSgg ixgbe_tx_context_t tx_context; 4979da57d7bSbt 4989da57d7bSbt /* 4999da57d7bSbt * Tx ring settings and status 5009da57d7bSbt */ 5019da57d7bSbt uint32_t ring_size; /* Tx descriptor ring size */ 5029da57d7bSbt uint32_t free_list_size; /* Tx free list size */ 5039da57d7bSbt 5049da57d7bSbt boolean_t reschedule; 5059da57d7bSbt uint32_t recycle_fail; 5069da57d7bSbt uint32_t stall_watchdog; 5079da57d7bSbt 5089da57d7bSbt #ifdef IXGBE_DEBUG 5099da57d7bSbt /* 5109da57d7bSbt * Debug statistics 5119da57d7bSbt */ 5129da57d7bSbt uint32_t stat_overload; 5139da57d7bSbt uint32_t stat_fail_no_tbd; 5149da57d7bSbt uint32_t stat_fail_no_tcb; 5159da57d7bSbt uint32_t stat_fail_dma_bind; 5169da57d7bSbt uint32_t stat_reschedule; 517edf70dc9SPaul Guo uint32_t stat_break_tbd_limit; 518da14cebeSEric Cheng uint32_t stat_lso_header_fail; 5199da57d7bSbt #endif 5200dc2366fSVenugopal Iyer uint64_t stat_obytes; 5210dc2366fSVenugopal Iyer uint64_t stat_opackets; 5229da57d7bSbt 523da14cebeSEric Cheng mac_ring_handle_t ring_handle; 524da14cebeSEric Cheng 5259da57d7bSbt /* 5269da57d7bSbt * Pointer to the ixgbe struct 5279da57d7bSbt */ 5289da57d7bSbt struct ixgbe *ixgbe; 5299da57d7bSbt } ixgbe_tx_ring_t; 5309da57d7bSbt 5319da57d7bSbt /* 5329da57d7bSbt * Software Receive Ring 5339da57d7bSbt */ 534ea65739eSchenlu chen - Sun Microsystems - Beijing China typedef struct ixgbe_rx_data { 5359da57d7bSbt kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 5369da57d7bSbt 5379da57d7bSbt /* 5389da57d7bSbt * Rx descriptor ring definitions 5399da57d7bSbt */ 5409da57d7bSbt dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 5419da57d7bSbt union ixgbe_adv_rx_desc *rbd_ring; /* Rx desc ring */ 5429da57d7bSbt uint32_t rbd_next; /* Index of next rx desc */ 5439da57d7bSbt 5449da57d7bSbt /* 5459da57d7bSbt * Rx control block list definitions 5469da57d7bSbt */ 5479da57d7bSbt rx_control_block_t *rcb_area; 5489da57d7bSbt rx_control_block_t **work_list; /* Work list of rcbs */ 5499da57d7bSbt rx_control_block_t **free_list; /* Free list of rcbs */ 5509da57d7bSbt uint32_t rcb_head; /* Index of next free rcb */ 5519da57d7bSbt uint32_t rcb_tail; /* Index to put recycled rcb */ 5529da57d7bSbt uint32_t rcb_free; /* Number of free rcbs */ 5539da57d7bSbt 5549da57d7bSbt /* 555ea65739eSchenlu chen - Sun Microsystems - Beijing China * Rx sw ring settings and status 5569da57d7bSbt */ 5579da57d7bSbt uint32_t ring_size; /* Rx descriptor ring size */ 5589da57d7bSbt uint32_t free_list_size; /* Rx free list size */ 559ea65739eSchenlu chen - Sun Microsystems - Beijing China 560ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t rcb_pending; 561ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t flag; 562ea65739eSchenlu chen - Sun Microsystems - Beijing China 563ffd8e883SWinson Wang - Sun Microsystems - Beijing China uint32_t lro_num; /* Number of rcbs of one LRO */ 564ffd8e883SWinson Wang - Sun Microsystems - Beijing China uint32_t lro_first; /* Index of first LRO rcb */ 565ffd8e883SWinson Wang - Sun Microsystems - Beijing China 566ea65739eSchenlu chen - Sun Microsystems - Beijing China struct ixgbe_rx_ring *rx_ring; /* Pointer to rx ring */ 567ea65739eSchenlu chen - Sun Microsystems - Beijing China } ixgbe_rx_data_t; 568ea65739eSchenlu chen - Sun Microsystems - Beijing China 569ea65739eSchenlu chen - Sun Microsystems - Beijing China /* 570ea65739eSchenlu chen - Sun Microsystems - Beijing China * Software Data Structure for Rx Ring 571ea65739eSchenlu chen - Sun Microsystems - Beijing China */ 572ea65739eSchenlu chen - Sun Microsystems - Beijing China typedef struct ixgbe_rx_ring { 573ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t index; /* Ring index */ 5740dc2366fSVenugopal Iyer uint32_t group_index; /* Group index */ 5750dc2366fSVenugopal Iyer uint32_t hw_index; /* h/w ring index */ 576ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t intr_vector; /* Interrupt vector index */ 577ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t vect_bit; /* vector's bit in register */ 578ea65739eSchenlu chen - Sun Microsystems - Beijing China 579ea65739eSchenlu chen - Sun Microsystems - Beijing China ixgbe_rx_data_t *rx_data; /* Rx software ring */ 580ea65739eSchenlu chen - Sun Microsystems - Beijing China 581ea65739eSchenlu chen - Sun Microsystems - Beijing China kmutex_t rx_lock; /* Rx access lock */ 5829da57d7bSbt 5839da57d7bSbt #ifdef IXGBE_DEBUG 5849da57d7bSbt /* 5859da57d7bSbt * Debug statistics 5869da57d7bSbt */ 5879da57d7bSbt uint32_t stat_frame_error; 5889da57d7bSbt uint32_t stat_cksum_error; 5899da57d7bSbt uint32_t stat_exceed_pkt; 5909da57d7bSbt #endif 5910dc2366fSVenugopal Iyer uint64_t stat_rbytes; 5920dc2366fSVenugopal Iyer uint64_t stat_ipackets; 5939da57d7bSbt 594da14cebeSEric Cheng mac_ring_handle_t ring_handle; 595da14cebeSEric Cheng uint64_t ring_gen_num; 5969da57d7bSbt 597da14cebeSEric Cheng struct ixgbe *ixgbe; /* Pointer to ixgbe struct */ 5989da57d7bSbt } ixgbe_rx_ring_t; 599da14cebeSEric Cheng /* 600da14cebeSEric Cheng * Software Receive Ring Group 601da14cebeSEric Cheng */ 602da14cebeSEric Cheng typedef struct ixgbe_rx_group { 603da14cebeSEric Cheng uint32_t index; /* Group index */ 604da14cebeSEric Cheng mac_group_handle_t group_handle; /* call back group handle */ 605da14cebeSEric Cheng struct ixgbe *ixgbe; /* Pointer to ixgbe struct */ 606da14cebeSEric Cheng } ixgbe_rx_group_t; 607da14cebeSEric Cheng 6089da57d7bSbt /* 60973cd555cSBin Tu - Sun Microsystems - Beijing China * structure to map interrupt cleanup to msi-x vector 6109da57d7bSbt */ 61173cd555cSBin Tu - Sun Microsystems - Beijing China typedef struct ixgbe_intr_vector { 6129da57d7bSbt struct ixgbe *ixgbe; /* point to my adapter */ 6139da57d7bSbt ulong_t rx_map[BT_BITOUL(MAX_RX_QUEUE_NUM)]; /* bitmap of rx rings */ 6149da57d7bSbt int rxr_cnt; /* count rx rings */ 6159da57d7bSbt ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)]; /* bitmap of tx rings */ 6169da57d7bSbt int txr_cnt; /* count tx rings */ 61773cd555cSBin Tu - Sun Microsystems - Beijing China ulong_t other_map[BT_BITOUL(2)]; /* bitmap of other */ 61873cd555cSBin Tu - Sun Microsystems - Beijing China int other_cnt; /* count other interrupt */ 61973cd555cSBin Tu - Sun Microsystems - Beijing China } ixgbe_intr_vector_t; 6209da57d7bSbt 6219da57d7bSbt /* 6229da57d7bSbt * Software adapter state 6239da57d7bSbt */ 6249da57d7bSbt typedef struct ixgbe { 6259da57d7bSbt int instance; 6269da57d7bSbt mac_handle_t mac_hdl; 6279da57d7bSbt dev_info_t *dip; 6289da57d7bSbt struct ixgbe_hw hw; 6299da57d7bSbt struct ixgbe_osdep osdep; 6309da57d7bSbt 63113740cb2SPaul Guo adapter_info_t *capab; /* adapter hardware capabilities */ 63262e6e1adSPaul Guo ddi_taskq_t *sfp_taskq; /* sfp-change taskq */ 6335b6dd21fSchenlu chen - Sun Microsystems - Beijing China ddi_taskq_t *overtemp_taskq; /* overtemp taskq */ 634*dc0cb1cdSDale Ghent ddi_taskq_t *phy_taskq; /* external PHY taskq */ 63513740cb2SPaul Guo uint32_t eims; /* interrupt mask setting */ 63673cd555cSBin Tu - Sun Microsystems - Beijing China uint32_t eimc; /* interrupt mask clear */ 63773cd555cSBin Tu - Sun Microsystems - Beijing China uint32_t eicr; /* interrupt cause reg */ 63813740cb2SPaul Guo 6399da57d7bSbt uint32_t ixgbe_state; 6409da57d7bSbt link_state_t link_state; 6419da57d7bSbt uint32_t link_speed; 6429da57d7bSbt uint32_t link_duplex; 6439da57d7bSbt 6449da57d7bSbt uint32_t reset_count; 6459da57d7bSbt uint32_t attach_progress; 6469da57d7bSbt uint32_t loopback_mode; 6479da57d7bSbt uint32_t default_mtu; 6489da57d7bSbt uint32_t max_frame_size; 649*dc0cb1cdSDale Ghent ixgbe_link_speed speeds_supported; 6509da57d7bSbt 651ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t rcb_pending; 652ea65739eSchenlu chen - Sun Microsystems - Beijing China 6539da57d7bSbt /* 65473cd555cSBin Tu - Sun Microsystems - Beijing China * Each msi-x vector: map vector to interrupt cleanup 6559da57d7bSbt */ 65673cd555cSBin Tu - Sun Microsystems - Beijing China ixgbe_intr_vector_t vect_map[MAX_INTR_VECTOR]; 6579da57d7bSbt 6589da57d7bSbt /* 6599da57d7bSbt * Receive Rings 6609da57d7bSbt */ 6619da57d7bSbt ixgbe_rx_ring_t *rx_rings; /* Array of rx rings */ 6629da57d7bSbt uint32_t num_rx_rings; /* Number of rx rings in use */ 6639da57d7bSbt uint32_t rx_ring_size; /* Rx descriptor ring size */ 6649da57d7bSbt uint32_t rx_buf_size; /* Rx buffer size */ 665ffd8e883SWinson Wang - Sun Microsystems - Beijing China boolean_t lro_enable; /* Large Receive Offload */ 666ffd8e883SWinson Wang - Sun Microsystems - Beijing China uint64_t lro_pkt_count; /* LRO packet count */ 667da14cebeSEric Cheng /* 668da14cebeSEric Cheng * Receive Groups 669da14cebeSEric Cheng */ 670da14cebeSEric Cheng ixgbe_rx_group_t *rx_groups; /* Array of rx groups */ 671da14cebeSEric Cheng uint32_t num_rx_groups; /* Number of rx groups in use */ 672da14cebeSEric Cheng 6739da57d7bSbt /* 6749da57d7bSbt * Transmit Rings 6759da57d7bSbt */ 6769da57d7bSbt ixgbe_tx_ring_t *tx_rings; /* Array of tx rings */ 6779da57d7bSbt uint32_t num_tx_rings; /* Number of tx rings in use */ 6789da57d7bSbt uint32_t tx_ring_size; /* Tx descriptor ring size */ 6799da57d7bSbt uint32_t tx_buf_size; /* Tx buffer size */ 6809da57d7bSbt 681ea65739eSchenlu chen - Sun Microsystems - Beijing China boolean_t tx_ring_init; 6829da57d7bSbt boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 6839da57d7bSbt boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 6849da57d7bSbt boolean_t lso_enable; /* Large Segment Offload */ 685da14cebeSEric Cheng boolean_t mr_enable; /* Multiple Tx and Rx Ring */ 6865b6dd21fSchenlu chen - Sun Microsystems - Beijing China boolean_t relax_order_enable; /* Relax Order */ 6870dc2366fSVenugopal Iyer uint32_t classify_mode; /* Classification mode */ 6889da57d7bSbt uint32_t tx_copy_thresh; /* Tx copy threshold */ 6899da57d7bSbt uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 6909da57d7bSbt uint32_t tx_overload_thresh; /* Tx overload threshold */ 6919da57d7bSbt uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 6929da57d7bSbt boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 6939da57d7bSbt uint32_t rx_copy_thresh; /* Rx copy threshold */ 6949da57d7bSbt uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 69573cd555cSBin Tu - Sun Microsystems - Beijing China uint32_t intr_throttling[MAX_INTR_VECTOR]; 6969da57d7bSbt uint32_t intr_force; 6979da57d7bSbt int fm_capabilities; /* FMA capabilities */ 6989da57d7bSbt 6999da57d7bSbt int intr_type; 7009da57d7bSbt int intr_cnt; 7010dc2366fSVenugopal Iyer uint32_t intr_cnt_max; 7020dc2366fSVenugopal Iyer uint32_t intr_cnt_min; 7039da57d7bSbt int intr_cap; 7049da57d7bSbt size_t intr_size; 7059da57d7bSbt uint_t intr_pri; 7069da57d7bSbt ddi_intr_handle_t *htable; 7079da57d7bSbt uint32_t eims_mask; 7080dc2366fSVenugopal Iyer ddi_cb_handle_t cb_hdl; /* Interrupt callback handle */ 7099da57d7bSbt 7109da57d7bSbt kmutex_t gen_lock; /* General lock for device access */ 7119da57d7bSbt kmutex_t watchdog_lock; 712ea65739eSchenlu chen - Sun Microsystems - Beijing China kmutex_t rx_pending_lock; 7139da57d7bSbt 7149da57d7bSbt boolean_t watchdog_enable; 7159da57d7bSbt boolean_t watchdog_start; 7169da57d7bSbt timeout_id_t watchdog_tid; 7179da57d7bSbt 7189da57d7bSbt boolean_t unicst_init; 7199da57d7bSbt uint32_t unicst_avail; 7209da57d7bSbt uint32_t unicst_total; 7219da57d7bSbt ixgbe_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 7229da57d7bSbt uint32_t mcast_count; 7239da57d7bSbt struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 7249da57d7bSbt 725da14cebeSEric Cheng ulong_t sys_page_size; 726da14cebeSEric Cheng 72762e6e1adSPaul Guo boolean_t link_check_complete; 72862e6e1adSPaul Guo hrtime_t link_check_hrtime; 72962e6e1adSPaul Guo ddi_periodic_t periodic_id; /* for link check timer func */ 73062e6e1adSPaul Guo 7319da57d7bSbt /* 7329da57d7bSbt * Kstat definitions 7339da57d7bSbt */ 7349da57d7bSbt kstat_t *ixgbe_ks; 7359da57d7bSbt 736ea65739eSchenlu chen - Sun Microsystems - Beijing China uint32_t param_en_10000fdx_cap:1, 737*dc0cb1cdSDale Ghent param_en_5000fdx_cap:1, 738*dc0cb1cdSDale Ghent param_en_2500fdx_cap:1, 739ea65739eSchenlu chen - Sun Microsystems - Beijing China param_en_1000fdx_cap:1, 740ea65739eSchenlu chen - Sun Microsystems - Beijing China param_en_100fdx_cap:1, 741ea65739eSchenlu chen - Sun Microsystems - Beijing China param_adv_10000fdx_cap:1, 742*dc0cb1cdSDale Ghent param_adv_5000fdx_cap:1, 743*dc0cb1cdSDale Ghent param_adv_2500fdx_cap:1, 744ea65739eSchenlu chen - Sun Microsystems - Beijing China param_adv_1000fdx_cap:1, 745ea65739eSchenlu chen - Sun Microsystems - Beijing China param_adv_100fdx_cap:1, 746ea65739eSchenlu chen - Sun Microsystems - Beijing China param_pause_cap:1, 747ea65739eSchenlu chen - Sun Microsystems - Beijing China param_asym_pause_cap:1, 748ea65739eSchenlu chen - Sun Microsystems - Beijing China param_rem_fault:1, 749ea65739eSchenlu chen - Sun Microsystems - Beijing China param_adv_autoneg_cap:1, 750ea65739eSchenlu chen - Sun Microsystems - Beijing China param_adv_pause_cap:1, 751ea65739eSchenlu chen - Sun Microsystems - Beijing China param_adv_asym_pause_cap:1, 752ea65739eSchenlu chen - Sun Microsystems - Beijing China param_adv_rem_fault:1, 753ea65739eSchenlu chen - Sun Microsystems - Beijing China param_lp_10000fdx_cap:1, 754*dc0cb1cdSDale Ghent param_lp_5000fdx_cap:1, 755*dc0cb1cdSDale Ghent param_lp_2500fdx_cap:1, 756ea65739eSchenlu chen - Sun Microsystems - Beijing China param_lp_1000fdx_cap:1, 757ea65739eSchenlu chen - Sun Microsystems - Beijing China param_lp_100fdx_cap:1, 758ea65739eSchenlu chen - Sun Microsystems - Beijing China param_lp_autoneg_cap:1, 759ea65739eSchenlu chen - Sun Microsystems - Beijing China param_lp_pause_cap:1, 760ea65739eSchenlu chen - Sun Microsystems - Beijing China param_lp_asym_pause_cap:1, 7611fedc51fSWinson Wang - Sun Microsystems - Beijing China param_lp_rem_fault:1, 762*dc0cb1cdSDale Ghent param_pad_to_32:6; 7639da57d7bSbt } ixgbe_t; 7649da57d7bSbt 7659da57d7bSbt typedef struct ixgbe_stat { 7669da57d7bSbt kstat_named_t link_speed; /* Link Speed */ 767da14cebeSEric Cheng 7689da57d7bSbt kstat_named_t reset_count; /* Reset Count */ 7699da57d7bSbt 7709da57d7bSbt kstat_named_t rx_frame_error; /* Rx Error in Packet */ 7719da57d7bSbt kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 7729da57d7bSbt kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 7739da57d7bSbt 7749da57d7bSbt kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 7759da57d7bSbt kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 7769da57d7bSbt kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 7779da57d7bSbt kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 7789da57d7bSbt kstat_named_t tx_reschedule; /* Tx Reschedule */ 7799da57d7bSbt 7809da57d7bSbt kstat_named_t gprc; /* Good Packets Received Count */ 7819da57d7bSbt kstat_named_t gptc; /* Good Packets Xmitted Count */ 7829da57d7bSbt kstat_named_t gor; /* Good Octets Received Count */ 7839da57d7bSbt kstat_named_t got; /* Good Octets Xmitd Count */ 7849da57d7bSbt kstat_named_t prc64; /* Packets Received - 64b */ 7859da57d7bSbt kstat_named_t prc127; /* Packets Received - 65-127b */ 7869da57d7bSbt kstat_named_t prc255; /* Packets Received - 127-255b */ 7879da57d7bSbt kstat_named_t prc511; /* Packets Received - 256-511b */ 7889da57d7bSbt kstat_named_t prc1023; /* Packets Received - 511-1023b */ 7899da57d7bSbt kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 7909da57d7bSbt kstat_named_t ptc64; /* Packets Xmitted (64b) */ 7919da57d7bSbt kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 7929da57d7bSbt kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 7939da57d7bSbt kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 7949da57d7bSbt kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 7959da57d7bSbt kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 796da14cebeSEric Cheng kstat_named_t qprc[16]; /* Queue Packets Received Count */ 797da14cebeSEric Cheng kstat_named_t qptc[16]; /* Queue Packets Transmitted Count */ 798da14cebeSEric Cheng kstat_named_t qbrc[16]; /* Queue Bytes Received Count */ 799da14cebeSEric Cheng kstat_named_t qbtc[16]; /* Queue Bytes Transmitted Count */ 800da14cebeSEric Cheng 8019da57d7bSbt kstat_named_t crcerrs; /* CRC Error Count */ 8029da57d7bSbt kstat_named_t illerrc; /* Illegal Byte Error Count */ 8039da57d7bSbt kstat_named_t errbc; /* Error Byte Count */ 8049da57d7bSbt kstat_named_t mspdc; /* MAC Short Packet Discard Count */ 8059da57d7bSbt kstat_named_t mpc; /* Missed Packets Count */ 8069da57d7bSbt kstat_named_t mlfc; /* MAC Local Fault Count */ 8079da57d7bSbt kstat_named_t mrfc; /* MAC Remote Fault Count */ 8089da57d7bSbt kstat_named_t rlec; /* Receive Length Error Count */ 8099da57d7bSbt kstat_named_t lxontxc; /* Link XON Transmitted Count */ 8109da57d7bSbt kstat_named_t lxonrxc; /* Link XON Received Count */ 8119da57d7bSbt kstat_named_t lxofftxc; /* Link XOFF Transmitted Count */ 8129da57d7bSbt kstat_named_t lxoffrxc; /* Link XOFF Received Count */ 8139da57d7bSbt kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 8149da57d7bSbt kstat_named_t mprc; /* Multicast Pkts Received Count */ 8159da57d7bSbt kstat_named_t rnbc; /* Receive No Buffers Count */ 8169da57d7bSbt kstat_named_t ruc; /* Receive Undersize Count */ 8179da57d7bSbt kstat_named_t rfc; /* Receive Frag Count */ 8189da57d7bSbt kstat_named_t roc; /* Receive Oversize Count */ 8199da57d7bSbt kstat_named_t rjc; /* Receive Jabber Count */ 8209da57d7bSbt kstat_named_t tor; /* Total Octets Recvd Count */ 821f27d3025Sgg kstat_named_t tot; /* Total Octets Xmitted Count */ 8229da57d7bSbt kstat_named_t tpr; /* Total Packets Received */ 8239da57d7bSbt kstat_named_t tpt; /* Total Packets Xmitted */ 8249da57d7bSbt kstat_named_t mptc; /* Multicast Packets Xmited Count */ 8259da57d7bSbt kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 826ffd8e883SWinson Wang - Sun Microsystems - Beijing China kstat_named_t lroc; /* LRO Packets Received Count */ 8279da57d7bSbt } ixgbe_stat_t; 8289da57d7bSbt 8299da57d7bSbt /* 8309da57d7bSbt * Function prototypes in ixgbe_buf.c 8319da57d7bSbt */ 8329da57d7bSbt int ixgbe_alloc_dma(ixgbe_t *); 8339da57d7bSbt void ixgbe_free_dma(ixgbe_t *); 834837c1ac4SStephen Hanson void ixgbe_set_fma_flags(int); 835ea65739eSchenlu chen - Sun Microsystems - Beijing China void ixgbe_free_dma_buffer(dma_buffer_t *); 836ea65739eSchenlu chen - Sun Microsystems - Beijing China int ixgbe_alloc_rx_ring_data(ixgbe_rx_ring_t *rx_ring); 837ea65739eSchenlu chen - Sun Microsystems - Beijing China void ixgbe_free_rx_ring_data(ixgbe_rx_data_t *rx_data); 8389da57d7bSbt 8399da57d7bSbt /* 8409da57d7bSbt * Function prototypes in ixgbe_main.c 8419da57d7bSbt */ 842ea65739eSchenlu chen - Sun Microsystems - Beijing China int ixgbe_start(ixgbe_t *, boolean_t); 843ea65739eSchenlu chen - Sun Microsystems - Beijing China void ixgbe_stop(ixgbe_t *, boolean_t); 8449da57d7bSbt int ixgbe_driver_setup_link(ixgbe_t *, boolean_t); 8459da57d7bSbt int ixgbe_multicst_add(ixgbe_t *, const uint8_t *); 8469da57d7bSbt int ixgbe_multicst_remove(ixgbe_t *, const uint8_t *); 8479da57d7bSbt enum ioc_reply ixgbe_loopback_ioctl(ixgbe_t *, struct iocblk *, mblk_t *); 8489da57d7bSbt 8499da57d7bSbt void ixgbe_enable_watchdog_timer(ixgbe_t *); 8509da57d7bSbt void ixgbe_disable_watchdog_timer(ixgbe_t *); 8519da57d7bSbt int ixgbe_atomic_reserve(uint32_t *, uint32_t); 8529da57d7bSbt 8539da57d7bSbt int ixgbe_check_acc_handle(ddi_acc_handle_t handle); 8549da57d7bSbt int ixgbe_check_dma_handle(ddi_dma_handle_t handle); 8559da57d7bSbt void ixgbe_fm_ereport(ixgbe_t *, char *); 8569da57d7bSbt 857da14cebeSEric Cheng void ixgbe_fill_ring(void *, mac_ring_type_t, const int, const int, 858da14cebeSEric Cheng mac_ring_info_t *, mac_ring_handle_t); 859da14cebeSEric Cheng void ixgbe_fill_group(void *arg, mac_ring_type_t, const int, 860da14cebeSEric Cheng mac_group_info_t *, mac_group_handle_t); 861da14cebeSEric Cheng int ixgbe_rx_ring_intr_enable(mac_intr_handle_t); 862da14cebeSEric Cheng int ixgbe_rx_ring_intr_disable(mac_intr_handle_t); 863da14cebeSEric Cheng 8649da57d7bSbt /* 8659da57d7bSbt * Function prototypes in ixgbe_gld.c 8669da57d7bSbt */ 8679da57d7bSbt int ixgbe_m_start(void *); 8689da57d7bSbt void ixgbe_m_stop(void *); 8699da57d7bSbt int ixgbe_m_promisc(void *, boolean_t); 8709da57d7bSbt int ixgbe_m_multicst(void *, boolean_t, const uint8_t *); 8719da57d7bSbt void ixgbe_m_resources(void *); 8729da57d7bSbt void ixgbe_m_ioctl(void *, queue_t *, mblk_t *); 8739da57d7bSbt boolean_t ixgbe_m_getcapab(void *, mac_capab_t, void *); 874ea65739eSchenlu chen - Sun Microsystems - Beijing China int ixgbe_m_setprop(void *, const char *, mac_prop_id_t, uint_t, const void *); 8750dc2366fSVenugopal Iyer int ixgbe_m_getprop(void *, const char *, mac_prop_id_t, uint_t, void *); 8760dc2366fSVenugopal Iyer void ixgbe_m_propinfo(void *, const char *, mac_prop_id_t, 8770dc2366fSVenugopal Iyer mac_prop_info_handle_t); 878ea65739eSchenlu chen - Sun Microsystems - Beijing China int ixgbe_set_priv_prop(ixgbe_t *, const char *, uint_t, const void *); 8790dc2366fSVenugopal Iyer int ixgbe_get_priv_prop(ixgbe_t *, const char *, uint_t, void *); 880ea65739eSchenlu chen - Sun Microsystems - Beijing China boolean_t ixgbe_param_locked(mac_prop_id_t); 8819da57d7bSbt 8829da57d7bSbt /* 8839da57d7bSbt * Function prototypes in ixgbe_rx.c 8849da57d7bSbt */ 885da14cebeSEric Cheng mblk_t *ixgbe_ring_rx(ixgbe_rx_ring_t *, int); 8869da57d7bSbt void ixgbe_rx_recycle(caddr_t arg); 887da14cebeSEric Cheng mblk_t *ixgbe_ring_rx_poll(void *, int); 8889da57d7bSbt 8899da57d7bSbt /* 8909da57d7bSbt * Function prototypes in ixgbe_tx.c 8919da57d7bSbt */ 892da14cebeSEric Cheng mblk_t *ixgbe_ring_tx(void *, mblk_t *); 8939da57d7bSbt void ixgbe_free_tcb(tx_control_block_t *); 8949da57d7bSbt void ixgbe_put_free_list(ixgbe_tx_ring_t *, link_list_t *); 8959da57d7bSbt uint32_t ixgbe_tx_recycle_legacy(ixgbe_tx_ring_t *); 8969da57d7bSbt uint32_t ixgbe_tx_recycle_head_wb(ixgbe_tx_ring_t *); 8979da57d7bSbt 8989da57d7bSbt /* 8999da57d7bSbt * Function prototypes in ixgbe_log.c 9009da57d7bSbt */ 9019da57d7bSbt void ixgbe_notice(void *, const char *, ...); 9029da57d7bSbt void ixgbe_log(void *, const char *, ...); 9039da57d7bSbt void ixgbe_error(void *, const char *, ...); 9049da57d7bSbt 9059da57d7bSbt /* 9069da57d7bSbt * Function prototypes in ixgbe_stat.c 9079da57d7bSbt */ 9089da57d7bSbt int ixgbe_init_stats(ixgbe_t *); 9090dc2366fSVenugopal Iyer int ixgbe_m_stat(void *, uint_t, uint64_t *); 9100dc2366fSVenugopal Iyer int ixgbe_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 9110dc2366fSVenugopal Iyer int ixgbe_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 9129da57d7bSbt 9139da57d7bSbt #ifdef __cplusplus 9149da57d7bSbt } 9159da57d7bSbt #endif 9169da57d7bSbt 9179da57d7bSbt #endif /* _IXGBE_SW_H */ 918