19da57d7bSbt /*
29da57d7bSbt  * CDDL HEADER START
39da57d7bSbt  *
473cd555cSBin Tu - Sun Microsystems - Beijing China  * Copyright(c) 2007-2009 Intel Corporation. All rights reserved.
59da57d7bSbt  * The contents of this file are subject to the terms of the
69da57d7bSbt  * Common Development and Distribution License (the "License").
79da57d7bSbt  * You may not use this file except in compliance with the License.
89da57d7bSbt  *
9*0dc2366fSVenugopal Iyer  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10*0dc2366fSVenugopal Iyer  * or http://www.opensolaris.org/os/licensing.
119da57d7bSbt  * See the License for the specific language governing permissions
129da57d7bSbt  * and limitations under the License.
139da57d7bSbt  *
14*0dc2366fSVenugopal Iyer  * When distributing Covered Code, include this CDDL HEADER in each
15*0dc2366fSVenugopal Iyer  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
169da57d7bSbt  * If applicable, add the following below this CDDL HEADER, with the
179da57d7bSbt  * fields enclosed by brackets "[]" replaced with your own identifying
189da57d7bSbt  * information: Portions Copyright [yyyy] [name of copyright owner]
199da57d7bSbt  *
209da57d7bSbt  * CDDL HEADER END
219da57d7bSbt  */
229da57d7bSbt 
239da57d7bSbt /*
24*0dc2366fSVenugopal Iyer  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
2573cd555cSBin Tu - Sun Microsystems - Beijing China  * Use is subject to license terms.
269da57d7bSbt  */
279da57d7bSbt 
289da57d7bSbt #include "ixgbe_sw.h"
299da57d7bSbt #include "ixgbe_debug.h"
309da57d7bSbt 
319da57d7bSbt #ifdef IXGBE_DEBUG
329da57d7bSbt extern ddi_device_acc_attr_t ixgbe_regs_acc_attr;
339da57d7bSbt 
349da57d7bSbt /*
359da57d7bSbt  * Dump interrupt-related registers & structures
369da57d7bSbt  */
379da57d7bSbt void
ixgbe_dump_interrupt(void * adapter,char * tag)389da57d7bSbt ixgbe_dump_interrupt(void *adapter, char *tag)
399da57d7bSbt {
409da57d7bSbt 	ixgbe_t *ixgbe = (ixgbe_t *)adapter;
419da57d7bSbt 	struct ixgbe_hw	*hw = &ixgbe->hw;
42*0dc2366fSVenugopal Iyer 	ixgbe_intr_vector_t *vect;
43*0dc2366fSVenugopal Iyer 	uint32_t ivar, reg, hw_index;
449da57d7bSbt 	int i, j;
459da57d7bSbt 
469da57d7bSbt 	/*
479da57d7bSbt 	 * interrupt control registers
489da57d7bSbt 	 */
499da57d7bSbt 	ixgbe_log(ixgbe, "interrupt: %s\n", tag);
509da57d7bSbt 	ixgbe_log(ixgbe, "..eims: 0x%x\n", IXGBE_READ_REG(hw, IXGBE_EIMS));
519da57d7bSbt 	ixgbe_log(ixgbe, "..eimc: 0x%x\n", IXGBE_READ_REG(hw, IXGBE_EIMC));
529da57d7bSbt 	ixgbe_log(ixgbe, "..eiac: 0x%x\n", IXGBE_READ_REG(hw, IXGBE_EIAC));
539da57d7bSbt 	ixgbe_log(ixgbe, "..eiam: 0x%x\n", IXGBE_READ_REG(hw, IXGBE_EIAM));
549da57d7bSbt 	ixgbe_log(ixgbe, "..gpie: 0x%x\n", IXGBE_READ_REG(hw, IXGBE_GPIE));
5513740cb2SPaul Guo 	ixgbe_log(ixgbe, "otherflag: 0x%x\n", ixgbe->capab->other_intr);
5613740cb2SPaul Guo 	ixgbe_log(ixgbe, "eims_mask: 0x%x\n", ixgbe->eims);
579da57d7bSbt 
589da57d7bSbt 	/* ivar: interrupt vector allocation registers */
599da57d7bSbt 	for (i = 0; i < IXGBE_IVAR_REG_NUM; i++) {
609da57d7bSbt 		if (ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(i))) {
619da57d7bSbt 			ixgbe_log(ixgbe, "ivar[%d]: 0x%x\n", i, ivar);
629da57d7bSbt 		}
639da57d7bSbt 	}
649da57d7bSbt 
659da57d7bSbt 	/* each allocated vector */
669da57d7bSbt 	for (i = 0; i < ixgbe->intr_cnt; i++) {
679da57d7bSbt 	vect =  &ixgbe->vect_map[i];
689da57d7bSbt 	ixgbe_log(ixgbe,
699da57d7bSbt 	    "vector %d  rx rings %d  tx rings %d  eitr: 0x%x\n",
709da57d7bSbt 	    i, vect->rxr_cnt, vect->txr_cnt,
719da57d7bSbt 	    IXGBE_READ_REG(hw, IXGBE_EITR(i)));
729da57d7bSbt 
739da57d7bSbt 	/* for each rx ring bit set */
749da57d7bSbt 	j = bt_getlowbit(vect->rx_map, 0, (ixgbe->num_rx_rings - 1));
759da57d7bSbt 	while (j >= 0) {
76*0dc2366fSVenugopal Iyer 		hw_index = ixgbe->rx_rings[j].hw_index;
779da57d7bSbt 		ixgbe_log(ixgbe, "rx %d  ivar %d  rxdctl: 0x%x  srrctl: 0x%x\n",
78*0dc2366fSVenugopal Iyer 		    hw_index, IXGBE_IVAR_RX_QUEUE(hw_index),
79*0dc2366fSVenugopal Iyer 		    IXGBE_READ_REG(hw, IXGBE_RXDCTL(hw_index)),
80*0dc2366fSVenugopal Iyer 		    IXGBE_READ_REG(hw, IXGBE_SRRCTL(hw_index)));
819da57d7bSbt 		j = bt_getlowbit(vect->rx_map, (j + 1),
829da57d7bSbt 		    (ixgbe->num_rx_rings - 1));
839da57d7bSbt 	}
849da57d7bSbt 
859da57d7bSbt 	/* for each tx ring bit set */
869da57d7bSbt 	j = bt_getlowbit(vect->tx_map, 0, (ixgbe->num_tx_rings - 1));
879da57d7bSbt 	while (j >= 0) {
889da57d7bSbt 		ixgbe_log(ixgbe, "tx %d  ivar %d  txdctl: 0x%x\n",
899da57d7bSbt 		    j, IXGBE_IVAR_TX_QUEUE(j),
909da57d7bSbt 		    IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)));
919da57d7bSbt 		j = bt_getlowbit(vect->tx_map, (j + 1),
929da57d7bSbt 		    (ixgbe->num_tx_rings - 1));
939da57d7bSbt 	}
949da57d7bSbt 	}
959da57d7bSbt 
969da57d7bSbt 	/* reta: RSS redirection table */
979da57d7bSbt 	for (i = 0; i < 32; i++) {
989da57d7bSbt 		ixgbe_log(ixgbe, "reta(%d): 0x%x\n",
999da57d7bSbt 		    i, IXGBE_READ_REG(hw, IXGBE_RETA(i)));
1009da57d7bSbt 	}
1019da57d7bSbt 
1029da57d7bSbt 	/* rssrk: RSS random key */
1039da57d7bSbt 	for (i = 0; i < 10; i++) {
1049da57d7bSbt 		ixgbe_log(ixgbe, "rssrk(%d): 0x%x\n",
1059da57d7bSbt 		    i, IXGBE_READ_REG(hw, IXGBE_RSSRK(i)));
1069da57d7bSbt 	}
1079da57d7bSbt 
1089da57d7bSbt 	/* check ral/rah */
1099da57d7bSbt 	ixgbe_log(ixgbe, "-- ral/rah --\n");
1109da57d7bSbt 	for (i = 0; i < 16; i++) {
1119da57d7bSbt 		if (reg = IXGBE_READ_REG(hw, IXGBE_RAL(i))) {
1129da57d7bSbt 			ixgbe_log(ixgbe, "ral(%d): 0x%x  rah(%d): 0x%x\n",
1139da57d7bSbt 			    i, reg, i, IXGBE_READ_REG(hw, IXGBE_RAH(i)));
1149da57d7bSbt 		}
1159da57d7bSbt 	}
1169da57d7bSbt 
1179da57d7bSbt 	/* check mta */
1189da57d7bSbt 	ixgbe_log(ixgbe, "-- mta --\n");
1199da57d7bSbt 	for (i = 0; i < 128; i++) {
1209da57d7bSbt 		if (reg = IXGBE_READ_REG(hw, IXGBE_MTA(i))) {
1219da57d7bSbt 			ixgbe_log(ixgbe, "mta(%d): 0x%x\n", i, reg);
1229da57d7bSbt 		}
1239da57d7bSbt 	}
1249da57d7bSbt 
1259da57d7bSbt 	/* check vfta */
1269da57d7bSbt 	{
1279da57d7bSbt 	uint32_t off = IXGBE_VFTA(0);
1289da57d7bSbt 	ixgbe_log(ixgbe, "-- vfta --\n");
1299da57d7bSbt 	for (i = 0; i < 640; i++) {
1309da57d7bSbt 		if (reg = IXGBE_READ_REG(hw, off)) {
1319da57d7bSbt 			ixgbe_log(ixgbe, "vfta(0x%x): 0x%x\n", off, reg);
1329da57d7bSbt 		}
1339da57d7bSbt 		off += 4;
1349da57d7bSbt 	}
1359da57d7bSbt 	}
1369da57d7bSbt 
1379da57d7bSbt 	/* check mdef */
1389da57d7bSbt 	ixgbe_log(ixgbe, "-- mdef --\n");
1399da57d7bSbt 	for (i = 0; i < 8; i++) {
1409da57d7bSbt 		if (reg = IXGBE_READ_REG(hw, IXGBE_MDEF(i))) {
1419da57d7bSbt 			ixgbe_log(ixgbe, "mdef(%d): 0x%x\n", i, reg);
1429da57d7bSbt 		}
1439da57d7bSbt 	}
1449da57d7bSbt }
1459da57d7bSbt 
1469da57d7bSbt /*
1479da57d7bSbt  * Dump an ethernet address
1489da57d7bSbt  */
1499da57d7bSbt void
ixgbe_dump_addr(void * adapter,char * tag,const uint8_t * addr)1509da57d7bSbt ixgbe_dump_addr(void *adapter, char *tag, const uint8_t *addr)
1519da57d7bSbt {
1529da57d7bSbt 	ixgbe_t *ixgbe = (ixgbe_t *)adapter;
1539da57d7bSbt 	char		form[25];
1549da57d7bSbt 
1559da57d7bSbt 	(void) sprintf(form, "%02x:%02x:%02x:%02x:%02x:%02x",
1569da57d7bSbt 	    *addr, *(addr + 1), *(addr + 2),
1579da57d7bSbt 	    *(addr + 3), *(addr + 4), *(addr + 5));
1589da57d7bSbt 
1599da57d7bSbt 	ixgbe_log(ixgbe, "%s %s\n", tag, form);
1609da57d7bSbt }
1619da57d7bSbt 
1629da57d7bSbt void
ixgbe_pci_dump(void * arg)1639da57d7bSbt ixgbe_pci_dump(void *arg)
1649da57d7bSbt {
1659da57d7bSbt 	ixgbe_t *ixgbe = (ixgbe_t *)arg;
1669da57d7bSbt 	ddi_acc_handle_t handle;
1679da57d7bSbt 	uint8_t cap_ptr;
1689da57d7bSbt 	uint8_t next_ptr;
1699da57d7bSbt 	uint32_t msix_bar;
1709da57d7bSbt 	uint32_t msix_ctrl;
1719da57d7bSbt 	uint32_t msix_tbl_sz;
1729da57d7bSbt 	uint32_t tbl_offset;
1739da57d7bSbt 	uint32_t tbl_bir;
1749da57d7bSbt 	uint32_t pba_offset;
1759da57d7bSbt 	uint32_t pba_bir;
1769da57d7bSbt 	off_t offset;
1779da57d7bSbt 	off_t mem_size;
1789da57d7bSbt 	uintptr_t base;
1799da57d7bSbt 	ddi_acc_handle_t acc_hdl;
1809da57d7bSbt 	int i;
1819da57d7bSbt 
1829da57d7bSbt 	handle = ixgbe->osdep.cfg_handle;
1839da57d7bSbt 
1849da57d7bSbt 	ixgbe_log(ixgbe, "Begin dump PCI config space");
1859da57d7bSbt 
1869da57d7bSbt 	ixgbe_log(ixgbe,
1879da57d7bSbt 	    "PCI_CONF_VENID:\t0x%x\n",
1889da57d7bSbt 	    pci_config_get16(handle, PCI_CONF_VENID));
1899da57d7bSbt 	ixgbe_log(ixgbe,
1909da57d7bSbt 	    "PCI_CONF_DEVID:\t0x%x\n",
1919da57d7bSbt 	    pci_config_get16(handle, PCI_CONF_DEVID));
1929da57d7bSbt 	ixgbe_log(ixgbe,
1939da57d7bSbt 	    "PCI_CONF_COMMAND:\t0x%x\n",
1949da57d7bSbt 	    pci_config_get16(handle, PCI_CONF_COMM));
1959da57d7bSbt 	ixgbe_log(ixgbe,
1969da57d7bSbt 	    "PCI_CONF_STATUS:\t0x%x\n",
1979da57d7bSbt 	    pci_config_get16(handle, PCI_CONF_STAT));
1989da57d7bSbt 	ixgbe_log(ixgbe,
1999da57d7bSbt 	    "PCI_CONF_REVID:\t0x%x\n",
2009da57d7bSbt 	    pci_config_get8(handle, PCI_CONF_REVID));
2019da57d7bSbt 	ixgbe_log(ixgbe,
2029da57d7bSbt 	    "PCI_CONF_PROG_CLASS:\t0x%x\n",
2039da57d7bSbt 	    pci_config_get8(handle, PCI_CONF_PROGCLASS));
2049da57d7bSbt 	ixgbe_log(ixgbe,
2059da57d7bSbt 	    "PCI_CONF_SUB_CLASS:\t0x%x\n",
2069da57d7bSbt 	    pci_config_get8(handle, PCI_CONF_SUBCLASS));
2079da57d7bSbt 	ixgbe_log(ixgbe,
2089da57d7bSbt 	    "PCI_CONF_BAS_CLASS:\t0x%x\n",
2099da57d7bSbt 	    pci_config_get8(handle, PCI_CONF_BASCLASS));
2109da57d7bSbt 	ixgbe_log(ixgbe,
2119da57d7bSbt 	    "PCI_CONF_CACHE_LINESZ:\t0x%x\n",
2129da57d7bSbt 	    pci_config_get8(handle, PCI_CONF_CACHE_LINESZ));
2139da57d7bSbt 	ixgbe_log(ixgbe,
2149da57d7bSbt 	    "PCI_CONF_LATENCY_TIMER:\t0x%x\n",
2159da57d7bSbt 	    pci_config_get8(handle, PCI_CONF_LATENCY_TIMER));
2169da57d7bSbt 	ixgbe_log(ixgbe,
2179da57d7bSbt 	    "PCI_CONF_HEADER_TYPE:\t0x%x\n",
2189da57d7bSbt 	    pci_config_get8(handle, PCI_CONF_HEADER));
2199da57d7bSbt 	ixgbe_log(ixgbe,
2209da57d7bSbt 	    "PCI_CONF_BIST:\t0x%x\n",
2219da57d7bSbt 	    pci_config_get8(handle, PCI_CONF_BIST));
2229da57d7bSbt 	ixgbe_log(ixgbe,
2239da57d7bSbt 	    "PCI_CONF_BASE0:\t0x%x\n",
2249da57d7bSbt 	    pci_config_get32(handle, PCI_CONF_BASE0));
2259da57d7bSbt 	ixgbe_log(ixgbe,
2269da57d7bSbt 	    "PCI_CONF_BASE1:\t0x%x\n",
2279da57d7bSbt 	    pci_config_get32(handle, PCI_CONF_BASE1));
2289da57d7bSbt 	ixgbe_log(ixgbe,
2299da57d7bSbt 	    "PCI_CONF_BASE2:\t0x%x\n",
2309da57d7bSbt 	    pci_config_get32(handle, PCI_CONF_BASE2));
2319da57d7bSbt 
2329da57d7bSbt 	/* MSI-X BAR */
2339da57d7bSbt 	msix_bar = pci_config_get32(handle, PCI_CONF_BASE3);
2349da57d7bSbt 	ixgbe_log(ixgbe,
2359da57d7bSbt 	    "PCI_CONF_BASE3:\t0x%x\n", msix_bar);
2369da57d7bSbt 
2379da57d7bSbt 	ixgbe_log(ixgbe,
2389da57d7bSbt 	    "PCI_CONF_BASE4:\t0x%x\n",
2399da57d7bSbt 	    pci_config_get32(handle, PCI_CONF_BASE4));
2409da57d7bSbt 	ixgbe_log(ixgbe,
2419da57d7bSbt 	    "PCI_CONF_BASE5:\t0x%x\n",
2429da57d7bSbt 	    pci_config_get32(handle, PCI_CONF_BASE5));
2439da57d7bSbt 	ixgbe_log(ixgbe,
2449da57d7bSbt 	    "PCI_CONF_CIS:\t0x%x\n",
2459da57d7bSbt 	    pci_config_get32(handle, PCI_CONF_CIS));
2469da57d7bSbt 	ixgbe_log(ixgbe,
2479da57d7bSbt 	    "PCI_CONF_SUBVENID:\t0x%x\n",
2489da57d7bSbt 	    pci_config_get16(handle, PCI_CONF_SUBVENID));
2499da57d7bSbt 	ixgbe_log(ixgbe,
2509da57d7bSbt 	    "PCI_CONF_SUBSYSID:\t0x%x\n",
2519da57d7bSbt 	    pci_config_get16(handle, PCI_CONF_SUBSYSID));
2529da57d7bSbt 	ixgbe_log(ixgbe,
2539da57d7bSbt 	    "PCI_CONF_ROM:\t0x%x\n",
2549da57d7bSbt 	    pci_config_get32(handle, PCI_CONF_ROM));
2559da57d7bSbt 
2569da57d7bSbt 	cap_ptr = pci_config_get8(handle, PCI_CONF_CAP_PTR);
2579da57d7bSbt 
2589da57d7bSbt 	ixgbe_log(ixgbe,
2599da57d7bSbt 	    "PCI_CONF_CAP_PTR:\t0x%x\n", cap_ptr);
2609da57d7bSbt 	ixgbe_log(ixgbe,
2619da57d7bSbt 	    "PCI_CONF_ILINE:\t0x%x\n",
2629da57d7bSbt 	    pci_config_get8(handle, PCI_CONF_ILINE));
2639da57d7bSbt 	ixgbe_log(ixgbe,
2649da57d7bSbt 	    "PCI_CONF_IPIN:\t0x%x\n",
2659da57d7bSbt 	    pci_config_get8(handle, PCI_CONF_IPIN));
2669da57d7bSbt 	ixgbe_log(ixgbe,
2679da57d7bSbt 	    "PCI_CONF_MIN_G:\t0x%x\n",
2689da57d7bSbt 	    pci_config_get8(handle, PCI_CONF_MIN_G));
2699da57d7bSbt 	ixgbe_log(ixgbe,
2709da57d7bSbt 	    "PCI_CONF_MAX_L:\t0x%x\n",
2719da57d7bSbt 	    pci_config_get8(handle, PCI_CONF_MAX_L));
2729da57d7bSbt 
2739da57d7bSbt 	/* Power Management */
2749da57d7bSbt 	offset = cap_ptr;
2759da57d7bSbt 
2769da57d7bSbt 	ixgbe_log(ixgbe,
2779da57d7bSbt 	    "PCI_PM_CAP_ID:\t0x%x\n",
2789da57d7bSbt 	    pci_config_get8(handle, offset));
2799da57d7bSbt 
2809da57d7bSbt 	next_ptr = pci_config_get8(handle, offset + 1);
2819da57d7bSbt 
2829da57d7bSbt 	ixgbe_log(ixgbe,
2839da57d7bSbt 	    "PCI_PM_NEXT_PTR:\t0x%x\n", next_ptr);
2849da57d7bSbt 	ixgbe_log(ixgbe,
2859da57d7bSbt 	    "PCI_PM_CAP:\t0x%x\n",
2869da57d7bSbt 	    pci_config_get16(handle, offset + PCI_PMCAP));
2879da57d7bSbt 	ixgbe_log(ixgbe,
2889da57d7bSbt 	    "PCI_PM_CSR:\t0x%x\n",
2899da57d7bSbt 	    pci_config_get16(handle, offset + PCI_PMCSR));
2909da57d7bSbt 	ixgbe_log(ixgbe,
2919da57d7bSbt 	    "PCI_PM_CSR_BSE:\t0x%x\n",
2929da57d7bSbt 	    pci_config_get8(handle, offset + PCI_PMCSR_BSE));
2939da57d7bSbt 	ixgbe_log(ixgbe,
2949da57d7bSbt 	    "PCI_PM_DATA:\t0x%x\n",
2959da57d7bSbt 	    pci_config_get8(handle, offset + PCI_PMDATA));
2969da57d7bSbt 
2979da57d7bSbt 	/* MSI Configuration */
2989da57d7bSbt 	offset = next_ptr;
2999da57d7bSbt 
3009da57d7bSbt 	ixgbe_log(ixgbe,
3019da57d7bSbt 	    "PCI_MSI_CAP_ID:\t0x%x\n",
3029da57d7bSbt 	    pci_config_get8(handle, offset));
3039da57d7bSbt 
3049da57d7bSbt 	next_ptr = pci_config_get8(handle, offset + 1);
3059da57d7bSbt 
3069da57d7bSbt 	ixgbe_log(ixgbe,
3079da57d7bSbt 	    "PCI_MSI_NEXT_PTR:\t0x%x\n", next_ptr);
3089da57d7bSbt 	ixgbe_log(ixgbe,
3099da57d7bSbt 	    "PCI_MSI_CTRL:\t0x%x\n",
3109da57d7bSbt 	    pci_config_get16(handle, offset + PCI_MSI_CTRL));
3119da57d7bSbt 	ixgbe_log(ixgbe,
3129da57d7bSbt 	    "PCI_MSI_ADDR:\t0x%x\n",
3139da57d7bSbt 	    pci_config_get32(handle, offset + PCI_MSI_ADDR_OFFSET));
3149da57d7bSbt 	ixgbe_log(ixgbe,
3159da57d7bSbt 	    "PCI_MSI_ADDR_HI:\t0x%x\n",
3169da57d7bSbt 	    pci_config_get32(handle, offset + 0x8));
3179da57d7bSbt 	ixgbe_log(ixgbe,
3189da57d7bSbt 	    "PCI_MSI_DATA:\t0x%x\n",
3199da57d7bSbt 	    pci_config_get16(handle, offset + 0xC));
3209da57d7bSbt 
3219da57d7bSbt 	/* MSI-X Configuration */
3229da57d7bSbt 	offset = next_ptr;
3239da57d7bSbt 
3249da57d7bSbt 	ixgbe_log(ixgbe,
3259da57d7bSbt 	    "PCI_MSIX_CAP_ID:\t0x%x\n",
3269da57d7bSbt 	    pci_config_get8(handle, offset));
3279da57d7bSbt 
3289da57d7bSbt 	next_ptr = pci_config_get8(handle, offset + 1);
3299da57d7bSbt 	ixgbe_log(ixgbe,
3309da57d7bSbt 	    "PCI_MSIX_NEXT_PTR:\t0x%x\n", next_ptr);
3319da57d7bSbt 
3329da57d7bSbt 	msix_ctrl = pci_config_get16(handle, offset + PCI_MSIX_CTRL);
3339da57d7bSbt 	msix_tbl_sz = msix_ctrl & 0x7ff;
3349da57d7bSbt 	ixgbe_log(ixgbe,
3359da57d7bSbt 	    "PCI_MSIX_CTRL:\t0x%x\n", msix_ctrl);
3369da57d7bSbt 
3379da57d7bSbt 	tbl_offset = pci_config_get32(handle, offset + PCI_MSIX_TBL_OFFSET);
3389da57d7bSbt 	tbl_bir = tbl_offset & PCI_MSIX_TBL_BIR_MASK;
3399da57d7bSbt 	tbl_offset = tbl_offset & ~PCI_MSIX_TBL_BIR_MASK;
3409da57d7bSbt 	ixgbe_log(ixgbe,
3419da57d7bSbt 	    "PCI_MSIX_TBL_OFFSET:\t0x%x\n", tbl_offset);
3429da57d7bSbt 	ixgbe_log(ixgbe,
3439da57d7bSbt 	    "PCI_MSIX_TBL_BIR:\t0x%x\n", tbl_bir);
3449da57d7bSbt 
3459da57d7bSbt 	pba_offset = pci_config_get32(handle, offset + PCI_MSIX_PBA_OFFSET);
3469da57d7bSbt 	pba_bir = pba_offset & PCI_MSIX_PBA_BIR_MASK;
3479da57d7bSbt 	pba_offset = pba_offset & ~PCI_MSIX_PBA_BIR_MASK;
3489da57d7bSbt 	ixgbe_log(ixgbe,
3499da57d7bSbt 	    "PCI_MSIX_PBA_OFFSET:\t0x%x\n", pba_offset);
3509da57d7bSbt 	ixgbe_log(ixgbe,
3519da57d7bSbt 	    "PCI_MSIX_PBA_BIR:\t0x%x\n", pba_bir);
3529da57d7bSbt 
3539da57d7bSbt 	/* PCI Express Configuration */
3549da57d7bSbt 	offset = next_ptr;
3559da57d7bSbt 
3569da57d7bSbt 	ixgbe_log(ixgbe,
3579da57d7bSbt 	    "PCIE_CAP_ID:\t0x%x\n",
3589da57d7bSbt 	    pci_config_get8(handle, offset + PCIE_CAP_ID));
3599da57d7bSbt 
3609da57d7bSbt 	next_ptr = pci_config_get8(handle, offset + PCIE_CAP_NEXT_PTR);
3619da57d7bSbt 
3629da57d7bSbt 	ixgbe_log(ixgbe,
3639da57d7bSbt 	    "PCIE_CAP_NEXT_PTR:\t0x%x\n", next_ptr);
3649da57d7bSbt 	ixgbe_log(ixgbe,
3659da57d7bSbt 	    "PCIE_PCIECAP:\t0x%x\n",
3669da57d7bSbt 	    pci_config_get16(handle, offset + PCIE_PCIECAP));
3679da57d7bSbt 	ixgbe_log(ixgbe,
3689da57d7bSbt 	    "PCIE_DEVCAP:\t0x%x\n",
3699da57d7bSbt 	    pci_config_get32(handle, offset + PCIE_DEVCAP));
3709da57d7bSbt 	ixgbe_log(ixgbe,
3719da57d7bSbt 	    "PCIE_DEVCTL:\t0x%x\n",
3729da57d7bSbt 	    pci_config_get16(handle, offset + PCIE_DEVCTL));
3739da57d7bSbt 	ixgbe_log(ixgbe,
3749da57d7bSbt 	    "PCIE_DEVSTS:\t0x%x\n",
3759da57d7bSbt 	    pci_config_get16(handle, offset + PCIE_DEVSTS));
3769da57d7bSbt 	ixgbe_log(ixgbe,
3779da57d7bSbt 	    "PCIE_LINKCAP:\t0x%x\n",
3789da57d7bSbt 	    pci_config_get32(handle, offset + PCIE_LINKCAP));
3799da57d7bSbt 	ixgbe_log(ixgbe,
3809da57d7bSbt 	    "PCIE_LINKCTL:\t0x%x\n",
3819da57d7bSbt 	    pci_config_get16(handle, offset + PCIE_LINKCTL));
3829da57d7bSbt 	ixgbe_log(ixgbe,
3839da57d7bSbt 	    "PCIE_LINKSTS:\t0x%x\n",
3849da57d7bSbt 	    pci_config_get16(handle, offset + PCIE_LINKSTS));
3859da57d7bSbt 
3869da57d7bSbt 	/* MSI-X Memory Space */
3879da57d7bSbt 	if (ddi_dev_regsize(ixgbe->dip, 4, &mem_size) != DDI_SUCCESS) {
3889da57d7bSbt 		ixgbe_log(ixgbe, "ddi_dev_regsize() failed");
3899da57d7bSbt 		return;
3909da57d7bSbt 	}
3919da57d7bSbt 
3929da57d7bSbt 	if ((ddi_regs_map_setup(ixgbe->dip, 4, (caddr_t *)&base, 0, mem_size,
3939da57d7bSbt 	    &ixgbe_regs_acc_attr, &acc_hdl)) != DDI_SUCCESS) {
3949da57d7bSbt 		ixgbe_log(ixgbe, "ddi_regs_map_setup() failed");
3959da57d7bSbt 		return;
3969da57d7bSbt 	}
3979da57d7bSbt 
3989da57d7bSbt 	ixgbe_log(ixgbe, "MSI-X Memory Space: (mem_size = %d, base = %x)",
3999da57d7bSbt 	    mem_size, base);
4009da57d7bSbt 
4019da57d7bSbt 	for (i = 0; i <= msix_tbl_sz; i++) {
4029da57d7bSbt 		ixgbe_log(ixgbe, "MSI-X Table Entry(%d):", i);
4039da57d7bSbt 		ixgbe_log(ixgbe, "lo_addr:\t%x",
4049da57d7bSbt 		    ddi_get32(acc_hdl,
4059da57d7bSbt 		    (uint32_t *)(base + tbl_offset + (i * 16))));
4069da57d7bSbt 		ixgbe_log(ixgbe, "up_addr:\t%x",
4079da57d7bSbt 		    ddi_get32(acc_hdl,
4089da57d7bSbt 		    (uint32_t *)(base + tbl_offset + (i * 16) + 4)));
4099da57d7bSbt 		ixgbe_log(ixgbe, "msg_data:\t%x",
4109da57d7bSbt 		    ddi_get32(acc_hdl,
4119da57d7bSbt 		    (uint32_t *)(base + tbl_offset + (i * 16) + 8)));
4129da57d7bSbt 		ixgbe_log(ixgbe, "vct_ctrl:\t%x",
4139da57d7bSbt 		    ddi_get32(acc_hdl,
4149da57d7bSbt 		    (uint32_t *)(base + tbl_offset + (i * 16) + 12)));
4159da57d7bSbt 	}
4169da57d7bSbt 
4179da57d7bSbt 	ixgbe_log(ixgbe, "MSI-X Pending Bits:\t%x",
4189da57d7bSbt 	    ddi_get32(acc_hdl, (uint32_t *)(base + pba_offset)));
4199da57d7bSbt 
4209da57d7bSbt 	ddi_regs_map_free(&acc_hdl);
4219da57d7bSbt }
42273cd555cSBin Tu - Sun Microsystems - Beijing China 
42373cd555cSBin Tu - Sun Microsystems - Beijing China /*
42473cd555cSBin Tu - Sun Microsystems - Beijing China  * Dump registers
42573cd555cSBin Tu - Sun Microsystems - Beijing China  */
42673cd555cSBin Tu - Sun Microsystems - Beijing China void
ixgbe_dump_regs(void * adapter)42773cd555cSBin Tu - Sun Microsystems - Beijing China ixgbe_dump_regs(void *adapter)
42873cd555cSBin Tu - Sun Microsystems - Beijing China {
42973cd555cSBin Tu - Sun Microsystems - Beijing China 	ixgbe_t *ixgbe = (ixgbe_t *)adapter;
430*0dc2366fSVenugopal Iyer 	uint32_t reg_val, hw_index;
43173cd555cSBin Tu - Sun Microsystems - Beijing China 	struct ixgbe_hw *hw = &ixgbe->hw;
43273cd555cSBin Tu - Sun Microsystems - Beijing China 	int i;
43373cd555cSBin Tu - Sun Microsystems - Beijing China 	DEBUGFUNC("ixgbe_dump_regs");
43473cd555cSBin Tu - Sun Microsystems - Beijing China 
43573cd555cSBin Tu - Sun Microsystems - Beijing China 	/* Dump basic's like CTRL, STATUS, CTRL_EXT. */
43673cd555cSBin Tu - Sun Microsystems - Beijing China 	ixgbe_log(ixgbe, "Basic IXGBE registers..");
43773cd555cSBin Tu - Sun Microsystems - Beijing China 	reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
43873cd555cSBin Tu - Sun Microsystems - Beijing China 	ixgbe_log(ixgbe, "\tCTRL=%x\n", reg_val);
43973cd555cSBin Tu - Sun Microsystems - Beijing China 	reg_val = IXGBE_READ_REG(hw, IXGBE_STATUS);
44073cd555cSBin Tu - Sun Microsystems - Beijing China 	ixgbe_log(ixgbe, "\tSTATUS=%x\n", reg_val);
44173cd555cSBin Tu - Sun Microsystems - Beijing China 	reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
44273cd555cSBin Tu - Sun Microsystems - Beijing China 	ixgbe_log(ixgbe, "\tCTRL_EXT=%x\n", reg_val);
44373cd555cSBin Tu - Sun Microsystems - Beijing China 	reg_val = IXGBE_READ_REG(hw, IXGBE_FCTRL);
44473cd555cSBin Tu - Sun Microsystems - Beijing China 	ixgbe_log(ixgbe, "\tFCTRL=%x\n", reg_val);
44573cd555cSBin Tu - Sun Microsystems - Beijing China 
44673cd555cSBin Tu - Sun Microsystems - Beijing China 	/* Misc Interrupt regs */
44773cd555cSBin Tu - Sun Microsystems - Beijing China 	ixgbe_log(ixgbe, "Some IXGBE interrupt registers..");
44873cd555cSBin Tu - Sun Microsystems - Beijing China 
44973cd555cSBin Tu - Sun Microsystems - Beijing China 	reg_val = IXGBE_READ_REG(hw, IXGBE_GPIE);
45073cd555cSBin Tu - Sun Microsystems - Beijing China 	ixgbe_log(ixgbe, "\tGPIE=%x\n", reg_val);
45173cd555cSBin Tu - Sun Microsystems - Beijing China 
45273cd555cSBin Tu - Sun Microsystems - Beijing China 	reg_val = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
45373cd555cSBin Tu - Sun Microsystems - Beijing China 	ixgbe_log(ixgbe, "\tIVAR(0)=%x\n", reg_val);
45473cd555cSBin Tu - Sun Microsystems - Beijing China 
45573cd555cSBin Tu - Sun Microsystems - Beijing China 	reg_val = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
45673cd555cSBin Tu - Sun Microsystems - Beijing China 	ixgbe_log(ixgbe, "\tIVAR_MISC=%x\n", reg_val);
45773cd555cSBin Tu - Sun Microsystems - Beijing China 
45873cd555cSBin Tu - Sun Microsystems - Beijing China 	/* Dump RX related reg's */
45973cd555cSBin Tu - Sun Microsystems - Beijing China 	ixgbe_log(ixgbe, "Receive registers...");
46073cd555cSBin Tu - Sun Microsystems - Beijing China 	reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
46173cd555cSBin Tu - Sun Microsystems - Beijing China 	ixgbe_log(ixgbe, "\tRXCTRL=%x\n", reg_val);
46273cd555cSBin Tu - Sun Microsystems - Beijing China 	for (i = 0; i < ixgbe->num_rx_rings; i++) {
463*0dc2366fSVenugopal Iyer 		hw_index = ixgbe->rx_rings[i].hw_index;
464*0dc2366fSVenugopal Iyer 		reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(hw_index));
465*0dc2366fSVenugopal Iyer 		ixgbe_log(ixgbe, "\tRXDCTL(%d)=%x\n", hw_index, reg_val);
466*0dc2366fSVenugopal Iyer 		reg_val = IXGBE_READ_REG(hw, IXGBE_SRRCTL(hw_index));
467*0dc2366fSVenugopal Iyer 		ixgbe_log(ixgbe, "\tSRRCTL(%d)=%x\n", hw_index, reg_val);
46873cd555cSBin Tu - Sun Microsystems - Beijing China 	}
46973cd555cSBin Tu - Sun Microsystems - Beijing China 	reg_val = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
47073cd555cSBin Tu - Sun Microsystems - Beijing China 	ixgbe_log(ixgbe, "\tRXCSUM=%x\n", reg_val);
47173cd555cSBin Tu - Sun Microsystems - Beijing China 	reg_val = IXGBE_READ_REG(hw, IXGBE_MRQC);
47273cd555cSBin Tu - Sun Microsystems - Beijing China 	ixgbe_log(ixgbe, "\tMRQC=%x\n", reg_val);
47373cd555cSBin Tu - Sun Microsystems - Beijing China 	reg_val = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
47473cd555cSBin Tu - Sun Microsystems - Beijing China 	ixgbe_log(ixgbe, "\tRDRXCTL=%x\n", reg_val);
47573cd555cSBin Tu - Sun Microsystems - Beijing China 
47673cd555cSBin Tu - Sun Microsystems - Beijing China 	/* Dump TX related regs */
47773cd555cSBin Tu - Sun Microsystems - Beijing China 	ixgbe_log(ixgbe, "Some transmit registers..");
47873cd555cSBin Tu - Sun Microsystems - Beijing China 	reg_val = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
47973cd555cSBin Tu - Sun Microsystems - Beijing China 	ixgbe_log(ixgbe, "\tDMATXCTL=%x\n", reg_val);
48073cd555cSBin Tu - Sun Microsystems - Beijing China 	for (i = 0; i < ixgbe->num_tx_rings; i++) {
48173cd555cSBin Tu - Sun Microsystems - Beijing China 		reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
48273cd555cSBin Tu - Sun Microsystems - Beijing China 		ixgbe_log(ixgbe, "\tTXDCTL(%d)=%x\n", i, reg_val);
48373cd555cSBin Tu - Sun Microsystems - Beijing China 		reg_val = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
48473cd555cSBin Tu - Sun Microsystems - Beijing China 		ixgbe_log(ixgbe, "\tTDWBAL(%d)=%x\n", i, reg_val);
48573cd555cSBin Tu - Sun Microsystems - Beijing China 		reg_val = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
48673cd555cSBin Tu - Sun Microsystems - Beijing China 		ixgbe_log(ixgbe, "\tTDWBAH(%d)=%x\n", i, reg_val);
48773cd555cSBin Tu - Sun Microsystems - Beijing China 		reg_val = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
48873cd555cSBin Tu - Sun Microsystems - Beijing China 		ixgbe_log(ixgbe, "\tTXPBSIZE(%d)=%x\n", i, reg_val);
48973cd555cSBin Tu - Sun Microsystems - Beijing China 	}
49073cd555cSBin Tu - Sun Microsystems - Beijing China }
49173cd555cSBin Tu - Sun Microsystems - Beijing China 
4929da57d7bSbt #endif
493