1dc0cb1cdSDale Ghent /****************************************************************************** 2*48ed61a7SRobert Mustacchi SPDX-License-Identifier: BSD-3-Clause 3dc0cb1cdSDale Ghent 4*48ed61a7SRobert Mustacchi Copyright (c) 2001-2017, Intel Corporation 5dc0cb1cdSDale Ghent All rights reserved. 6*48ed61a7SRobert Mustacchi 7*48ed61a7SRobert Mustacchi Redistribution and use in source and binary forms, with or without 8dc0cb1cdSDale Ghent modification, are permitted provided that the following conditions are met: 9*48ed61a7SRobert Mustacchi 10*48ed61a7SRobert Mustacchi 1. Redistributions of source code must retain the above copyright notice, 11dc0cb1cdSDale Ghent this list of conditions and the following disclaimer. 12*48ed61a7SRobert Mustacchi 13*48ed61a7SRobert Mustacchi 2. Redistributions in binary form must reproduce the above copyright 14*48ed61a7SRobert Mustacchi notice, this list of conditions and the following disclaimer in the 15dc0cb1cdSDale Ghent documentation and/or other materials provided with the distribution. 16*48ed61a7SRobert Mustacchi 17*48ed61a7SRobert Mustacchi 3. Neither the name of the Intel Corporation nor the names of its 18*48ed61a7SRobert Mustacchi contributors may be used to endorse or promote products derived from 19dc0cb1cdSDale Ghent this software without specific prior written permission. 20*48ed61a7SRobert Mustacchi 21dc0cb1cdSDale Ghent THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22*48ed61a7SRobert Mustacchi AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23*48ed61a7SRobert Mustacchi IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24*48ed61a7SRobert Mustacchi ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25*48ed61a7SRobert Mustacchi LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26*48ed61a7SRobert Mustacchi CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27*48ed61a7SRobert Mustacchi SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28*48ed61a7SRobert Mustacchi INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29*48ed61a7SRobert Mustacchi CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30dc0cb1cdSDale Ghent ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31dc0cb1cdSDale Ghent POSSIBILITY OF SUCH DAMAGE. 32dc0cb1cdSDale Ghent 33dc0cb1cdSDale Ghent ******************************************************************************/ 34dc0cb1cdSDale Ghent /*$FreeBSD$*/ 35dc0cb1cdSDale Ghent 36dc0cb1cdSDale Ghent #ifndef _IXGBE_DCB_82599_H_ 37dc0cb1cdSDale Ghent #define _IXGBE_DCB_82599_H_ 38dc0cb1cdSDale Ghent 39dc0cb1cdSDale Ghent /* DCB register definitions */ 40dc0cb1cdSDale Ghent #define IXGBE_RTTDCS_TDPAC 0x00000001 /* 0 Round Robin, 41dc0cb1cdSDale Ghent * 1 WSP - Weighted Strict Priority 42dc0cb1cdSDale Ghent */ 43dc0cb1cdSDale Ghent #define IXGBE_RTTDCS_VMPAC 0x00000002 /* 0 Round Robin, 44dc0cb1cdSDale Ghent * 1 WRR - Weighted Round Robin 45dc0cb1cdSDale Ghent */ 46dc0cb1cdSDale Ghent #define IXGBE_RTTDCS_TDRM 0x00000010 /* Transmit Recycle Mode */ 47dc0cb1cdSDale Ghent #define IXGBE_RTTDCS_BDPM 0x00400000 /* Bypass Data Pipe - must clear! */ 48dc0cb1cdSDale Ghent #define IXGBE_RTTDCS_BPBFSM 0x00800000 /* Bypass PB Free Space - must 49dc0cb1cdSDale Ghent * clear! 50dc0cb1cdSDale Ghent */ 51dc0cb1cdSDale Ghent #define IXGBE_RTTDCS_SPEED_CHG 0x80000000 /* Link speed change */ 52dc0cb1cdSDale Ghent 53dc0cb1cdSDale Ghent /* Receive UP2TC mapping */ 54dc0cb1cdSDale Ghent #define IXGBE_RTRUP2TC_UP_SHIFT 3 55dc0cb1cdSDale Ghent #define IXGBE_RTRUP2TC_UP_MASK 7 56dc0cb1cdSDale Ghent /* Transmit UP2TC mapping */ 57dc0cb1cdSDale Ghent #define IXGBE_RTTUP2TC_UP_SHIFT 3 58dc0cb1cdSDale Ghent 59dc0cb1cdSDale Ghent #define IXGBE_RTRPT4C_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */ 60dc0cb1cdSDale Ghent #define IXGBE_RTRPT4C_BWG_SHIFT 9 /* Offset to BWG index */ 61dc0cb1cdSDale Ghent #define IXGBE_RTRPT4C_GSP 0x40000000 /* GSP enable bit */ 62dc0cb1cdSDale Ghent #define IXGBE_RTRPT4C_LSP 0x80000000 /* LSP enable bit */ 63dc0cb1cdSDale Ghent 64dc0cb1cdSDale Ghent #define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet 65dc0cb1cdSDale Ghent * buffers enable 66dc0cb1cdSDale Ghent */ 67dc0cb1cdSDale Ghent #define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores 68dc0cb1cdSDale Ghent * (RSS) enable 69dc0cb1cdSDale Ghent */ 70dc0cb1cdSDale Ghent 71dc0cb1cdSDale Ghent /* RTRPCS Bit Masks */ 72dc0cb1cdSDale Ghent #define IXGBE_RTRPCS_RRM 0x00000002 /* Receive Recycle Mode enable */ 73dc0cb1cdSDale Ghent /* Receive Arbitration Control: 0 Round Robin, 1 DFP */ 74dc0cb1cdSDale Ghent #define IXGBE_RTRPCS_RAC 0x00000004 75dc0cb1cdSDale Ghent #define IXGBE_RTRPCS_ARBDIS 0x00000040 /* Arbitration disable bit */ 76dc0cb1cdSDale Ghent 77dc0cb1cdSDale Ghent /* RTTDT2C Bit Masks */ 78dc0cb1cdSDale Ghent #define IXGBE_RTTDT2C_MCL_SHIFT 12 79dc0cb1cdSDale Ghent #define IXGBE_RTTDT2C_BWG_SHIFT 9 80dc0cb1cdSDale Ghent #define IXGBE_RTTDT2C_GSP 0x40000000 81dc0cb1cdSDale Ghent #define IXGBE_RTTDT2C_LSP 0x80000000 82dc0cb1cdSDale Ghent 83dc0cb1cdSDale Ghent #define IXGBE_RTTPT2C_MCL_SHIFT 12 84dc0cb1cdSDale Ghent #define IXGBE_RTTPT2C_BWG_SHIFT 9 85dc0cb1cdSDale Ghent #define IXGBE_RTTPT2C_GSP 0x40000000 86dc0cb1cdSDale Ghent #define IXGBE_RTTPT2C_LSP 0x80000000 87dc0cb1cdSDale Ghent 88dc0cb1cdSDale Ghent /* RTTPCS Bit Masks */ 89dc0cb1cdSDale Ghent #define IXGBE_RTTPCS_TPPAC 0x00000020 /* 0 Round Robin, 90dc0cb1cdSDale Ghent * 1 SP - Strict Priority 91dc0cb1cdSDale Ghent */ 92dc0cb1cdSDale Ghent #define IXGBE_RTTPCS_ARBDIS 0x00000040 /* Arbiter disable */ 93dc0cb1cdSDale Ghent #define IXGBE_RTTPCS_TPRM 0x00000100 /* Transmit Recycle Mode enable */ 94dc0cb1cdSDale Ghent #define IXGBE_RTTPCS_ARBD_SHIFT 22 95dc0cb1cdSDale Ghent #define IXGBE_RTTPCS_ARBD_DCB 0x4 /* Arbitration delay in DCB mode */ 96dc0cb1cdSDale Ghent 97dc0cb1cdSDale Ghent #define IXGBE_TXPBTHRESH_DCB 0xA /* THRESH value for DCB mode */ 98dc0cb1cdSDale Ghent 99dc0cb1cdSDale Ghent /* SECTXMINIFG DCB */ 100dc0cb1cdSDale Ghent #define IXGBE_SECTX_DCB 0x00001F00 /* DCB TX Buffer SEC IFG */ 101dc0cb1cdSDale Ghent 102dc0cb1cdSDale Ghent /* BCN register definitions */ 103dc0cb1cdSDale Ghent #define IXGBE_RTTBCNRC_RF_INT_SHIFT 14 104dc0cb1cdSDale Ghent #define IXGBE_RTTBCNRC_RS_ENA 0x80000000 105dc0cb1cdSDale Ghent 106dc0cb1cdSDale Ghent #define IXGBE_RTTBCNCR_MNG_CMTGI 0x00000001 107dc0cb1cdSDale Ghent #define IXGBE_RTTBCNCR_MGN_BCNA_MODE 0x00000002 108dc0cb1cdSDale Ghent #define IXGBE_RTTBCNCR_RSV7_11_SHIFT 5 109dc0cb1cdSDale Ghent #define IXGBE_RTTBCNCR_G 0x00000400 110dc0cb1cdSDale Ghent #define IXGBE_RTTBCNCR_I 0x00000800 111dc0cb1cdSDale Ghent #define IXGBE_RTTBCNCR_H 0x00001000 112dc0cb1cdSDale Ghent #define IXGBE_RTTBCNCR_VER_SHIFT 14 113dc0cb1cdSDale Ghent #define IXGBE_RTTBCNCR_CMT_ETH_SHIFT 16 114dc0cb1cdSDale Ghent 115dc0cb1cdSDale Ghent #define IXGBE_RTTBCNACL_SMAC_L_SHIFT 16 116dc0cb1cdSDale Ghent 117dc0cb1cdSDale Ghent #define IXGBE_RTTBCNTG_BCNA_MODE 0x80000000 118dc0cb1cdSDale Ghent 119dc0cb1cdSDale Ghent #define IXGBE_RTTBCNRTT_TS_SHIFT 3 120dc0cb1cdSDale Ghent #define IXGBE_RTTBCNRTT_TXQ_IDX_SHIFT 16 121dc0cb1cdSDale Ghent 122dc0cb1cdSDale Ghent #define IXGBE_RTTBCNRD_BCN_CLEAR_ALL 0x00000002 123dc0cb1cdSDale Ghent #define IXGBE_RTTBCNRD_DRIFT_FAC_SHIFT 2 124dc0cb1cdSDale Ghent #define IXGBE_RTTBCNRD_DRIFT_INT_SHIFT 16 125dc0cb1cdSDale Ghent #define IXGBE_RTTBCNRD_DRIFT_ENA 0x80000000 126dc0cb1cdSDale Ghent 127dc0cb1cdSDale Ghent 128dc0cb1cdSDale Ghent /* DCB driver APIs */ 129dc0cb1cdSDale Ghent 130dc0cb1cdSDale Ghent /* DCB PFC */ 131dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *, u8, u8 *); 132dc0cb1cdSDale Ghent 133dc0cb1cdSDale Ghent /* DCB stats */ 134dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *, 135dc0cb1cdSDale Ghent struct ixgbe_dcb_config *); 136dc0cb1cdSDale Ghent s32 ixgbe_dcb_get_tc_stats_82599(struct ixgbe_hw *, 137dc0cb1cdSDale Ghent struct ixgbe_hw_stats *, u8); 138dc0cb1cdSDale Ghent s32 ixgbe_dcb_get_pfc_stats_82599(struct ixgbe_hw *, 139dc0cb1cdSDale Ghent struct ixgbe_hw_stats *, u8); 140dc0cb1cdSDale Ghent 141dc0cb1cdSDale Ghent /* DCB config arbiters */ 142dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *, 143dc0cb1cdSDale Ghent u8 *, u8 *); 144dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *, 145dc0cb1cdSDale Ghent u8 *, u8 *, u8 *); 146dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *, u8 *, 147dc0cb1cdSDale Ghent u8 *, u8 *); 148dc0cb1cdSDale Ghent 149dc0cb1cdSDale Ghent /* DCB initialization */ 150dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_82599(struct ixgbe_hw *, 151dc0cb1cdSDale Ghent struct ixgbe_dcb_config *); 152dc0cb1cdSDale Ghent 153dc0cb1cdSDale Ghent s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *, int, u16 *, u16 *, u8 *, 154dc0cb1cdSDale Ghent u8 *, u8 *); 155dc0cb1cdSDale Ghent #endif /* _IXGBE_DCB_82959_H_ */ 156