1dc0cb1cdSDale Ghent /******************************************************************************
2*48ed61a7SRobert Mustacchi SPDX-License-Identifier: BSD-3-Clause
3dc0cb1cdSDale Ghent
4*48ed61a7SRobert Mustacchi Copyright (c) 2001-2017, Intel Corporation
5dc0cb1cdSDale Ghent All rights reserved.
6*48ed61a7SRobert Mustacchi
7*48ed61a7SRobert Mustacchi Redistribution and use in source and binary forms, with or without
8dc0cb1cdSDale Ghent modification, are permitted provided that the following conditions are met:
9*48ed61a7SRobert Mustacchi
10*48ed61a7SRobert Mustacchi 1. Redistributions of source code must retain the above copyright notice,
11dc0cb1cdSDale Ghent this list of conditions and the following disclaimer.
12*48ed61a7SRobert Mustacchi
13*48ed61a7SRobert Mustacchi 2. Redistributions in binary form must reproduce the above copyright
14*48ed61a7SRobert Mustacchi notice, this list of conditions and the following disclaimer in the
15dc0cb1cdSDale Ghent documentation and/or other materials provided with the distribution.
16*48ed61a7SRobert Mustacchi
17*48ed61a7SRobert Mustacchi 3. Neither the name of the Intel Corporation nor the names of its
18*48ed61a7SRobert Mustacchi contributors may be used to endorse or promote products derived from
19dc0cb1cdSDale Ghent this software without specific prior written permission.
20*48ed61a7SRobert Mustacchi
21dc0cb1cdSDale Ghent THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22*48ed61a7SRobert Mustacchi AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23*48ed61a7SRobert Mustacchi IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24*48ed61a7SRobert Mustacchi ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25*48ed61a7SRobert Mustacchi LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26*48ed61a7SRobert Mustacchi CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27*48ed61a7SRobert Mustacchi SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28*48ed61a7SRobert Mustacchi INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29*48ed61a7SRobert Mustacchi CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30dc0cb1cdSDale Ghent ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31dc0cb1cdSDale Ghent POSSIBILITY OF SUCH DAMAGE.
32dc0cb1cdSDale Ghent
33dc0cb1cdSDale Ghent ******************************************************************************/
34dc0cb1cdSDale Ghent /*$FreeBSD$*/
35dc0cb1cdSDale Ghent
36dc0cb1cdSDale Ghent
37dc0cb1cdSDale Ghent #include "ixgbe_type.h"
38dc0cb1cdSDale Ghent #include "ixgbe_dcb.h"
39dc0cb1cdSDale Ghent #include "ixgbe_dcb_82599.h"
40dc0cb1cdSDale Ghent
41dc0cb1cdSDale Ghent /**
42dc0cb1cdSDale Ghent * ixgbe_dcb_get_tc_stats_82599 - Returns status for each traffic class
43dc0cb1cdSDale Ghent * @hw: pointer to hardware structure
44dc0cb1cdSDale Ghent * @stats: pointer to statistics structure
45dc0cb1cdSDale Ghent * @tc_count: Number of elements in bwg_array.
46dc0cb1cdSDale Ghent *
47dc0cb1cdSDale Ghent * This function returns the status data for each of the Traffic Classes in use.
48dc0cb1cdSDale Ghent */
ixgbe_dcb_get_tc_stats_82599(struct ixgbe_hw * hw,struct ixgbe_hw_stats * stats,u8 tc_count)49dc0cb1cdSDale Ghent s32 ixgbe_dcb_get_tc_stats_82599(struct ixgbe_hw *hw,
50dc0cb1cdSDale Ghent struct ixgbe_hw_stats *stats,
51dc0cb1cdSDale Ghent u8 tc_count)
52dc0cb1cdSDale Ghent {
53dc0cb1cdSDale Ghent int tc;
54dc0cb1cdSDale Ghent
55dc0cb1cdSDale Ghent DEBUGFUNC("dcb_get_tc_stats");
56dc0cb1cdSDale Ghent
57dc0cb1cdSDale Ghent if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)
58dc0cb1cdSDale Ghent return IXGBE_ERR_PARAM;
59dc0cb1cdSDale Ghent
60dc0cb1cdSDale Ghent /* Statistics pertaining to each traffic class */
61dc0cb1cdSDale Ghent for (tc = 0; tc < tc_count; tc++) {
62dc0cb1cdSDale Ghent /* Transmitted Packets */
63dc0cb1cdSDale Ghent stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc));
64dc0cb1cdSDale Ghent /* Transmitted Bytes (read low first to prevent missed carry) */
65dc0cb1cdSDale Ghent stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(tc));
66dc0cb1cdSDale Ghent stats->qbtc[tc] +=
67dc0cb1cdSDale Ghent (((u64)(IXGBE_READ_REG(hw, IXGBE_QBTC_H(tc)))) << 32);
68dc0cb1cdSDale Ghent /* Received Packets */
69dc0cb1cdSDale Ghent stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc));
70dc0cb1cdSDale Ghent /* Received Bytes (read low first to prevent missed carry) */
71dc0cb1cdSDale Ghent stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(tc));
72dc0cb1cdSDale Ghent stats->qbrc[tc] +=
73dc0cb1cdSDale Ghent (((u64)(IXGBE_READ_REG(hw, IXGBE_QBRC_H(tc)))) << 32);
74dc0cb1cdSDale Ghent
75dc0cb1cdSDale Ghent /* Received Dropped Packet */
76dc0cb1cdSDale Ghent stats->qprdc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRDC(tc));
77dc0cb1cdSDale Ghent }
78dc0cb1cdSDale Ghent
79dc0cb1cdSDale Ghent return IXGBE_SUCCESS;
80dc0cb1cdSDale Ghent }
81dc0cb1cdSDale Ghent
82dc0cb1cdSDale Ghent /**
83dc0cb1cdSDale Ghent * ixgbe_dcb_get_pfc_stats_82599 - Return CBFC status data
84dc0cb1cdSDale Ghent * @hw: pointer to hardware structure
85dc0cb1cdSDale Ghent * @stats: pointer to statistics structure
86dc0cb1cdSDale Ghent * @tc_count: Number of elements in bwg_array.
87dc0cb1cdSDale Ghent *
88dc0cb1cdSDale Ghent * This function returns the CBFC status data for each of the Traffic Classes.
89dc0cb1cdSDale Ghent */
ixgbe_dcb_get_pfc_stats_82599(struct ixgbe_hw * hw,struct ixgbe_hw_stats * stats,u8 tc_count)90dc0cb1cdSDale Ghent s32 ixgbe_dcb_get_pfc_stats_82599(struct ixgbe_hw *hw,
91dc0cb1cdSDale Ghent struct ixgbe_hw_stats *stats,
92dc0cb1cdSDale Ghent u8 tc_count)
93dc0cb1cdSDale Ghent {
94dc0cb1cdSDale Ghent int tc;
95dc0cb1cdSDale Ghent
96dc0cb1cdSDale Ghent DEBUGFUNC("dcb_get_pfc_stats");
97dc0cb1cdSDale Ghent
98dc0cb1cdSDale Ghent if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)
99dc0cb1cdSDale Ghent return IXGBE_ERR_PARAM;
100dc0cb1cdSDale Ghent
101dc0cb1cdSDale Ghent for (tc = 0; tc < tc_count; tc++) {
102dc0cb1cdSDale Ghent /* Priority XOFF Transmitted */
103dc0cb1cdSDale Ghent stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc));
104dc0cb1cdSDale Ghent /* Priority XOFF Received */
105dc0cb1cdSDale Ghent stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(tc));
106dc0cb1cdSDale Ghent }
107dc0cb1cdSDale Ghent
108dc0cb1cdSDale Ghent return IXGBE_SUCCESS;
109dc0cb1cdSDale Ghent }
110dc0cb1cdSDale Ghent
111dc0cb1cdSDale Ghent /**
112dc0cb1cdSDale Ghent * ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter
113dc0cb1cdSDale Ghent * @hw: pointer to hardware structure
114*48ed61a7SRobert Mustacchi * @refill: refill credits index by traffic class
115*48ed61a7SRobert Mustacchi * @max: max credits index by traffic class
116*48ed61a7SRobert Mustacchi * @bwg_id: bandwidth grouping indexed by traffic class
117*48ed61a7SRobert Mustacchi * @tsa: transmission selection algorithm indexed by traffic class
118*48ed61a7SRobert Mustacchi * @map: priority to tc assignments indexed by priority
119dc0cb1cdSDale Ghent *
120dc0cb1cdSDale Ghent * Configure Rx Packet Arbiter and credits for each traffic class.
121dc0cb1cdSDale Ghent */
ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw * hw,u16 * refill,u16 * max,u8 * bwg_id,u8 * tsa,u8 * map)122dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
123dc0cb1cdSDale Ghent u16 *max, u8 *bwg_id, u8 *tsa,
124dc0cb1cdSDale Ghent u8 *map)
125dc0cb1cdSDale Ghent {
126dc0cb1cdSDale Ghent u32 reg = 0;
127dc0cb1cdSDale Ghent u32 credit_refill = 0;
128dc0cb1cdSDale Ghent u32 credit_max = 0;
129dc0cb1cdSDale Ghent u8 i = 0;
130dc0cb1cdSDale Ghent
131dc0cb1cdSDale Ghent /*
132dc0cb1cdSDale Ghent * Disable the arbiter before changing parameters
133dc0cb1cdSDale Ghent * (always enable recycle mode; WSP)
134dc0cb1cdSDale Ghent */
135dc0cb1cdSDale Ghent reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
136dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
137dc0cb1cdSDale Ghent
138dc0cb1cdSDale Ghent /*
139dc0cb1cdSDale Ghent * map all UPs to TCs. up_to_tc_bitmap for each TC has corresponding
140dc0cb1cdSDale Ghent * bits sets for the UPs that needs to be mappped to that TC.
141dc0cb1cdSDale Ghent * e.g if priorities 6 and 7 are to be mapped to a TC then the
142dc0cb1cdSDale Ghent * up_to_tc_bitmap value for that TC will be 11000000 in binary.
143dc0cb1cdSDale Ghent */
144dc0cb1cdSDale Ghent reg = 0;
145dc0cb1cdSDale Ghent for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
146dc0cb1cdSDale Ghent reg |= (map[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT));
147dc0cb1cdSDale Ghent
148dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
149dc0cb1cdSDale Ghent
150dc0cb1cdSDale Ghent /* Configure traffic class credits and priority */
151dc0cb1cdSDale Ghent for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
152dc0cb1cdSDale Ghent credit_refill = refill[i];
153dc0cb1cdSDale Ghent credit_max = max[i];
154dc0cb1cdSDale Ghent reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT);
155dc0cb1cdSDale Ghent
156dc0cb1cdSDale Ghent reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT;
157dc0cb1cdSDale Ghent
158dc0cb1cdSDale Ghent if (tsa[i] == ixgbe_dcb_tsa_strict)
159dc0cb1cdSDale Ghent reg |= IXGBE_RTRPT4C_LSP;
160dc0cb1cdSDale Ghent
161dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg);
162dc0cb1cdSDale Ghent }
163dc0cb1cdSDale Ghent
164dc0cb1cdSDale Ghent /*
165dc0cb1cdSDale Ghent * Configure Rx packet plane (recycle mode; WSP) and
166dc0cb1cdSDale Ghent * enable arbiter
167dc0cb1cdSDale Ghent */
168dc0cb1cdSDale Ghent reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
169dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
170dc0cb1cdSDale Ghent
171dc0cb1cdSDale Ghent return IXGBE_SUCCESS;
172dc0cb1cdSDale Ghent }
173dc0cb1cdSDale Ghent
174dc0cb1cdSDale Ghent /**
175dc0cb1cdSDale Ghent * ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter
176dc0cb1cdSDale Ghent * @hw: pointer to hardware structure
177*48ed61a7SRobert Mustacchi * @refill: refill credits index by traffic class
178*48ed61a7SRobert Mustacchi * @max: max credits index by traffic class
179*48ed61a7SRobert Mustacchi * @bwg_id: bandwidth grouping indexed by traffic class
180*48ed61a7SRobert Mustacchi * @tsa: transmission selection algorithm indexed by traffic class
181dc0cb1cdSDale Ghent *
182dc0cb1cdSDale Ghent * Configure Tx Descriptor Arbiter and credits for each traffic class.
183dc0cb1cdSDale Ghent */
ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw * hw,u16 * refill,u16 * max,u8 * bwg_id,u8 * tsa)184dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
185dc0cb1cdSDale Ghent u16 *max, u8 *bwg_id, u8 *tsa)
186dc0cb1cdSDale Ghent {
187dc0cb1cdSDale Ghent u32 reg, max_credits;
188dc0cb1cdSDale Ghent u8 i;
189dc0cb1cdSDale Ghent
190dc0cb1cdSDale Ghent /* Clear the per-Tx queue credits; we use per-TC instead */
191dc0cb1cdSDale Ghent for (i = 0; i < 128; i++) {
192dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
193dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0);
194dc0cb1cdSDale Ghent }
195dc0cb1cdSDale Ghent
196dc0cb1cdSDale Ghent /* Configure traffic class credits and priority */
197dc0cb1cdSDale Ghent for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
198dc0cb1cdSDale Ghent max_credits = max[i];
199dc0cb1cdSDale Ghent reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT;
200dc0cb1cdSDale Ghent reg |= refill[i];
201dc0cb1cdSDale Ghent reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT;
202dc0cb1cdSDale Ghent
203dc0cb1cdSDale Ghent if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
204dc0cb1cdSDale Ghent reg |= IXGBE_RTTDT2C_GSP;
205dc0cb1cdSDale Ghent
206dc0cb1cdSDale Ghent if (tsa[i] == ixgbe_dcb_tsa_strict)
207dc0cb1cdSDale Ghent reg |= IXGBE_RTTDT2C_LSP;
208dc0cb1cdSDale Ghent
209dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg);
210dc0cb1cdSDale Ghent }
211dc0cb1cdSDale Ghent
212dc0cb1cdSDale Ghent /*
213dc0cb1cdSDale Ghent * Configure Tx descriptor plane (recycle mode; WSP) and
214dc0cb1cdSDale Ghent * enable arbiter
215dc0cb1cdSDale Ghent */
216dc0cb1cdSDale Ghent reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM;
217dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
218dc0cb1cdSDale Ghent
219dc0cb1cdSDale Ghent return IXGBE_SUCCESS;
220dc0cb1cdSDale Ghent }
221dc0cb1cdSDale Ghent
222dc0cb1cdSDale Ghent /**
223dc0cb1cdSDale Ghent * ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter
224dc0cb1cdSDale Ghent * @hw: pointer to hardware structure
225*48ed61a7SRobert Mustacchi * @refill: refill credits index by traffic class
226*48ed61a7SRobert Mustacchi * @max: max credits index by traffic class
227*48ed61a7SRobert Mustacchi * @bwg_id: bandwidth grouping indexed by traffic class
228*48ed61a7SRobert Mustacchi * @tsa: transmission selection algorithm indexed by traffic class
229*48ed61a7SRobert Mustacchi * @map: priority to tc assignments indexed by priority
230dc0cb1cdSDale Ghent *
231dc0cb1cdSDale Ghent * Configure Tx Packet Arbiter and credits for each traffic class.
232dc0cb1cdSDale Ghent */
ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw * hw,u16 * refill,u16 * max,u8 * bwg_id,u8 * tsa,u8 * map)233dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
234dc0cb1cdSDale Ghent u16 *max, u8 *bwg_id, u8 *tsa,
235dc0cb1cdSDale Ghent u8 *map)
236dc0cb1cdSDale Ghent {
237dc0cb1cdSDale Ghent u32 reg;
238dc0cb1cdSDale Ghent u8 i;
239dc0cb1cdSDale Ghent
240dc0cb1cdSDale Ghent /*
241dc0cb1cdSDale Ghent * Disable the arbiter before changing parameters
242dc0cb1cdSDale Ghent * (always enable recycle mode; SP; arb delay)
243dc0cb1cdSDale Ghent */
244dc0cb1cdSDale Ghent reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
245dc0cb1cdSDale Ghent (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT) |
246dc0cb1cdSDale Ghent IXGBE_RTTPCS_ARBDIS;
247dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
248dc0cb1cdSDale Ghent
249dc0cb1cdSDale Ghent /*
250dc0cb1cdSDale Ghent * map all UPs to TCs. up_to_tc_bitmap for each TC has corresponding
251dc0cb1cdSDale Ghent * bits sets for the UPs that needs to be mappped to that TC.
252dc0cb1cdSDale Ghent * e.g if priorities 6 and 7 are to be mapped to a TC then the
253dc0cb1cdSDale Ghent * up_to_tc_bitmap value for that TC will be 11000000 in binary.
254dc0cb1cdSDale Ghent */
255dc0cb1cdSDale Ghent reg = 0;
256dc0cb1cdSDale Ghent for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
257dc0cb1cdSDale Ghent reg |= (map[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT));
258dc0cb1cdSDale Ghent
259dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);
260dc0cb1cdSDale Ghent
261dc0cb1cdSDale Ghent /* Configure traffic class credits and priority */
262dc0cb1cdSDale Ghent for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
263dc0cb1cdSDale Ghent reg = refill[i];
264dc0cb1cdSDale Ghent reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT;
265dc0cb1cdSDale Ghent reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT;
266dc0cb1cdSDale Ghent
267dc0cb1cdSDale Ghent if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
268dc0cb1cdSDale Ghent reg |= IXGBE_RTTPT2C_GSP;
269dc0cb1cdSDale Ghent
270dc0cb1cdSDale Ghent if (tsa[i] == ixgbe_dcb_tsa_strict)
271dc0cb1cdSDale Ghent reg |= IXGBE_RTTPT2C_LSP;
272dc0cb1cdSDale Ghent
273dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg);
274dc0cb1cdSDale Ghent }
275dc0cb1cdSDale Ghent
276dc0cb1cdSDale Ghent /*
277dc0cb1cdSDale Ghent * Configure Tx packet plane (recycle mode; SP; arb delay) and
278dc0cb1cdSDale Ghent * enable arbiter
279dc0cb1cdSDale Ghent */
280dc0cb1cdSDale Ghent reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
281dc0cb1cdSDale Ghent (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT);
282dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
283dc0cb1cdSDale Ghent
284dc0cb1cdSDale Ghent return IXGBE_SUCCESS;
285dc0cb1cdSDale Ghent }
286dc0cb1cdSDale Ghent
287dc0cb1cdSDale Ghent /**
288dc0cb1cdSDale Ghent * ixgbe_dcb_config_pfc_82599 - Configure priority flow control
289dc0cb1cdSDale Ghent * @hw: pointer to hardware structure
290dc0cb1cdSDale Ghent * @pfc_en: enabled pfc bitmask
291dc0cb1cdSDale Ghent * @map: priority to tc assignments indexed by priority
292dc0cb1cdSDale Ghent *
293dc0cb1cdSDale Ghent * Configure Priority Flow Control (PFC) for each traffic class.
294dc0cb1cdSDale Ghent */
ixgbe_dcb_config_pfc_82599(struct ixgbe_hw * hw,u8 pfc_en,u8 * map)295dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *map)
296dc0cb1cdSDale Ghent {
297dc0cb1cdSDale Ghent u32 i, j, fcrtl, reg;
298dc0cb1cdSDale Ghent u8 max_tc = 0;
299dc0cb1cdSDale Ghent
300dc0cb1cdSDale Ghent /* Enable Transmit Priority Flow Control */
301dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_FCCFG, IXGBE_FCCFG_TFCE_PRIORITY);
302dc0cb1cdSDale Ghent
303dc0cb1cdSDale Ghent /* Enable Receive Priority Flow Control */
304dc0cb1cdSDale Ghent reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
305dc0cb1cdSDale Ghent reg |= IXGBE_MFLCN_DPF;
306dc0cb1cdSDale Ghent
307dc0cb1cdSDale Ghent /*
308dc0cb1cdSDale Ghent * X540 supports per TC Rx priority flow control. So
309dc0cb1cdSDale Ghent * clear all TCs and only enable those that should be
310dc0cb1cdSDale Ghent * enabled.
311dc0cb1cdSDale Ghent */
312dc0cb1cdSDale Ghent reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
313dc0cb1cdSDale Ghent
314dc0cb1cdSDale Ghent if (hw->mac.type >= ixgbe_mac_X540)
315dc0cb1cdSDale Ghent reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;
316dc0cb1cdSDale Ghent
317dc0cb1cdSDale Ghent if (pfc_en)
318dc0cb1cdSDale Ghent reg |= IXGBE_MFLCN_RPFCE;
319dc0cb1cdSDale Ghent
320dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
321dc0cb1cdSDale Ghent
322dc0cb1cdSDale Ghent for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++) {
323dc0cb1cdSDale Ghent if (map[i] > max_tc)
324dc0cb1cdSDale Ghent max_tc = map[i];
325dc0cb1cdSDale Ghent }
326dc0cb1cdSDale Ghent
327dc0cb1cdSDale Ghent
328dc0cb1cdSDale Ghent /* Configure PFC Tx thresholds per TC */
329dc0cb1cdSDale Ghent for (i = 0; i <= max_tc; i++) {
330dc0cb1cdSDale Ghent int enabled = 0;
331dc0cb1cdSDale Ghent
332dc0cb1cdSDale Ghent for (j = 0; j < IXGBE_DCB_MAX_USER_PRIORITY; j++) {
333dc0cb1cdSDale Ghent if ((map[j] == i) && (pfc_en & (1 << j))) {
334dc0cb1cdSDale Ghent enabled = 1;
335dc0cb1cdSDale Ghent break;
336dc0cb1cdSDale Ghent }
337dc0cb1cdSDale Ghent }
338dc0cb1cdSDale Ghent
339dc0cb1cdSDale Ghent if (enabled) {
340dc0cb1cdSDale Ghent reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
341dc0cb1cdSDale Ghent fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
342dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
343dc0cb1cdSDale Ghent } else {
344dc0cb1cdSDale Ghent /*
345dc0cb1cdSDale Ghent * In order to prevent Tx hangs when the internal Tx
346dc0cb1cdSDale Ghent * switch is enabled we must set the high water mark
347dc0cb1cdSDale Ghent * to the Rx packet buffer size - 24KB. This allows
348dc0cb1cdSDale Ghent * the Tx switch to function even under heavy Rx
349dc0cb1cdSDale Ghent * workloads.
350dc0cb1cdSDale Ghent */
351dc0cb1cdSDale Ghent reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
352dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
353dc0cb1cdSDale Ghent }
354dc0cb1cdSDale Ghent
355dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
356dc0cb1cdSDale Ghent }
357dc0cb1cdSDale Ghent
358dc0cb1cdSDale Ghent for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
359dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
360dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), 0);
361dc0cb1cdSDale Ghent }
362dc0cb1cdSDale Ghent
363dc0cb1cdSDale Ghent /* Configure pause time (2 TCs per register) */
364dc0cb1cdSDale Ghent reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
365dc0cb1cdSDale Ghent for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
366dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
367dc0cb1cdSDale Ghent
368dc0cb1cdSDale Ghent /* Configure flow control refresh threshold value */
369dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
370dc0cb1cdSDale Ghent
371dc0cb1cdSDale Ghent return IXGBE_SUCCESS;
372dc0cb1cdSDale Ghent }
373dc0cb1cdSDale Ghent
374dc0cb1cdSDale Ghent /**
375dc0cb1cdSDale Ghent * ixgbe_dcb_config_tc_stats_82599 - Config traffic class statistics
376dc0cb1cdSDale Ghent * @hw: pointer to hardware structure
377*48ed61a7SRobert Mustacchi * @dcb_config: pointer to ixgbe_dcb_config structure
378dc0cb1cdSDale Ghent *
379dc0cb1cdSDale Ghent * Configure queue statistics registers, all queues belonging to same traffic
380dc0cb1cdSDale Ghent * class uses a single set of queue statistics counters.
381dc0cb1cdSDale Ghent */
ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw * hw,struct ixgbe_dcb_config * dcb_config)382dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw,
383dc0cb1cdSDale Ghent struct ixgbe_dcb_config *dcb_config)
384dc0cb1cdSDale Ghent {
385dc0cb1cdSDale Ghent u32 reg = 0;
386dc0cb1cdSDale Ghent u8 i = 0;
387dc0cb1cdSDale Ghent u8 tc_count = 8;
388dc0cb1cdSDale Ghent bool vt_mode = FALSE;
389dc0cb1cdSDale Ghent
390dc0cb1cdSDale Ghent if (dcb_config != NULL) {
391dc0cb1cdSDale Ghent tc_count = dcb_config->num_tcs.pg_tcs;
392dc0cb1cdSDale Ghent vt_mode = dcb_config->vt_mode;
393dc0cb1cdSDale Ghent }
394dc0cb1cdSDale Ghent
395dc0cb1cdSDale Ghent if (!((tc_count == 8 && vt_mode == FALSE) || tc_count == 4))
396dc0cb1cdSDale Ghent return IXGBE_ERR_PARAM;
397dc0cb1cdSDale Ghent
398dc0cb1cdSDale Ghent if (tc_count == 8 && vt_mode == FALSE) {
399dc0cb1cdSDale Ghent /*
400dc0cb1cdSDale Ghent * Receive Queues stats setting
401dc0cb1cdSDale Ghent * 32 RQSMR registers, each configuring 4 queues.
402dc0cb1cdSDale Ghent *
403dc0cb1cdSDale Ghent * Set all 16 queues of each TC to the same stat
404dc0cb1cdSDale Ghent * with TC 'n' going to stat 'n'.
405dc0cb1cdSDale Ghent */
406dc0cb1cdSDale Ghent for (i = 0; i < 32; i++) {
407dc0cb1cdSDale Ghent reg = 0x01010101 * (i / 4);
408dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
409dc0cb1cdSDale Ghent }
410dc0cb1cdSDale Ghent /*
411dc0cb1cdSDale Ghent * Transmit Queues stats setting
412dc0cb1cdSDale Ghent * 32 TQSM registers, each controlling 4 queues.
413dc0cb1cdSDale Ghent *
414dc0cb1cdSDale Ghent * Set all queues of each TC to the same stat
415dc0cb1cdSDale Ghent * with TC 'n' going to stat 'n'.
416dc0cb1cdSDale Ghent * Tx queues are allocated non-uniformly to TCs:
417dc0cb1cdSDale Ghent * 32, 32, 16, 16, 8, 8, 8, 8.
418dc0cb1cdSDale Ghent */
419dc0cb1cdSDale Ghent for (i = 0; i < 32; i++) {
420dc0cb1cdSDale Ghent if (i < 8)
421dc0cb1cdSDale Ghent reg = 0x00000000;
422dc0cb1cdSDale Ghent else if (i < 16)
423dc0cb1cdSDale Ghent reg = 0x01010101;
424dc0cb1cdSDale Ghent else if (i < 20)
425dc0cb1cdSDale Ghent reg = 0x02020202;
426dc0cb1cdSDale Ghent else if (i < 24)
427dc0cb1cdSDale Ghent reg = 0x03030303;
428dc0cb1cdSDale Ghent else if (i < 26)
429dc0cb1cdSDale Ghent reg = 0x04040404;
430dc0cb1cdSDale Ghent else if (i < 28)
431dc0cb1cdSDale Ghent reg = 0x05050505;
432dc0cb1cdSDale Ghent else if (i < 30)
433dc0cb1cdSDale Ghent reg = 0x06060606;
434dc0cb1cdSDale Ghent else
435dc0cb1cdSDale Ghent reg = 0x07070707;
436dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
437dc0cb1cdSDale Ghent }
438dc0cb1cdSDale Ghent } else if (tc_count == 4 && vt_mode == FALSE) {
439dc0cb1cdSDale Ghent /*
440dc0cb1cdSDale Ghent * Receive Queues stats setting
441dc0cb1cdSDale Ghent * 32 RQSMR registers, each configuring 4 queues.
442dc0cb1cdSDale Ghent *
443dc0cb1cdSDale Ghent * Set all 16 queues of each TC to the same stat
444dc0cb1cdSDale Ghent * with TC 'n' going to stat 'n'.
445dc0cb1cdSDale Ghent */
446dc0cb1cdSDale Ghent for (i = 0; i < 32; i++) {
447dc0cb1cdSDale Ghent if (i % 8 > 3)
448dc0cb1cdSDale Ghent /* In 4 TC mode, odd 16-queue ranges are
449dc0cb1cdSDale Ghent * not used.
450dc0cb1cdSDale Ghent */
451dc0cb1cdSDale Ghent continue;
452dc0cb1cdSDale Ghent reg = 0x01010101 * (i / 8);
453dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
454dc0cb1cdSDale Ghent }
455dc0cb1cdSDale Ghent /*
456dc0cb1cdSDale Ghent * Transmit Queues stats setting
457dc0cb1cdSDale Ghent * 32 TQSM registers, each controlling 4 queues.
458dc0cb1cdSDale Ghent *
459dc0cb1cdSDale Ghent * Set all queues of each TC to the same stat
460dc0cb1cdSDale Ghent * with TC 'n' going to stat 'n'.
461dc0cb1cdSDale Ghent * Tx queues are allocated non-uniformly to TCs:
462dc0cb1cdSDale Ghent * 64, 32, 16, 16.
463dc0cb1cdSDale Ghent */
464dc0cb1cdSDale Ghent for (i = 0; i < 32; i++) {
465dc0cb1cdSDale Ghent if (i < 16)
466dc0cb1cdSDale Ghent reg = 0x00000000;
467dc0cb1cdSDale Ghent else if (i < 24)
468dc0cb1cdSDale Ghent reg = 0x01010101;
469dc0cb1cdSDale Ghent else if (i < 28)
470dc0cb1cdSDale Ghent reg = 0x02020202;
471dc0cb1cdSDale Ghent else
472dc0cb1cdSDale Ghent reg = 0x03030303;
473dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
474dc0cb1cdSDale Ghent }
475dc0cb1cdSDale Ghent } else if (tc_count == 4 && vt_mode == TRUE) {
476dc0cb1cdSDale Ghent /*
477dc0cb1cdSDale Ghent * Receive Queues stats setting
478dc0cb1cdSDale Ghent * 32 RQSMR registers, each configuring 4 queues.
479dc0cb1cdSDale Ghent *
480dc0cb1cdSDale Ghent * Queue Indexing in 32 VF with DCB mode maps 4 TC's to each
481dc0cb1cdSDale Ghent * pool. Set all 32 queues of each TC across pools to the same
482dc0cb1cdSDale Ghent * stat with TC 'n' going to stat 'n'.
483dc0cb1cdSDale Ghent */
484dc0cb1cdSDale Ghent for (i = 0; i < 32; i++)
485dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0x03020100);
486dc0cb1cdSDale Ghent /*
487dc0cb1cdSDale Ghent * Transmit Queues stats setting
488dc0cb1cdSDale Ghent * 32 TQSM registers, each controlling 4 queues.
489dc0cb1cdSDale Ghent *
490dc0cb1cdSDale Ghent * Queue Indexing in 32 VF with DCB mode maps 4 TC's to each
491dc0cb1cdSDale Ghent * pool. Set all 32 queues of each TC across pools to the same
492dc0cb1cdSDale Ghent * stat with TC 'n' going to stat 'n'.
493dc0cb1cdSDale Ghent */
494dc0cb1cdSDale Ghent for (i = 0; i < 32; i++)
495dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0x03020100);
496dc0cb1cdSDale Ghent }
497dc0cb1cdSDale Ghent
498dc0cb1cdSDale Ghent return IXGBE_SUCCESS;
499dc0cb1cdSDale Ghent }
500dc0cb1cdSDale Ghent
501dc0cb1cdSDale Ghent /**
502dc0cb1cdSDale Ghent * ixgbe_dcb_config_82599 - Configure general DCB parameters
503dc0cb1cdSDale Ghent * @hw: pointer to hardware structure
504dc0cb1cdSDale Ghent * @dcb_config: pointer to ixgbe_dcb_config structure
505dc0cb1cdSDale Ghent *
506dc0cb1cdSDale Ghent * Configure general DCB parameters.
507dc0cb1cdSDale Ghent */
ixgbe_dcb_config_82599(struct ixgbe_hw * hw,struct ixgbe_dcb_config * dcb_config)508dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_82599(struct ixgbe_hw *hw,
509dc0cb1cdSDale Ghent struct ixgbe_dcb_config *dcb_config)
510dc0cb1cdSDale Ghent {
511dc0cb1cdSDale Ghent u32 reg;
512dc0cb1cdSDale Ghent u32 q;
513dc0cb1cdSDale Ghent
514dc0cb1cdSDale Ghent /* Disable the Tx desc arbiter so that MTQC can be changed */
515dc0cb1cdSDale Ghent reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
516dc0cb1cdSDale Ghent reg |= IXGBE_RTTDCS_ARBDIS;
517dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
518dc0cb1cdSDale Ghent
519dc0cb1cdSDale Ghent reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
520dc0cb1cdSDale Ghent if (dcb_config->num_tcs.pg_tcs == 8) {
521dc0cb1cdSDale Ghent /* Enable DCB for Rx with 8 TCs */
522dc0cb1cdSDale Ghent switch (reg & IXGBE_MRQC_MRQE_MASK) {
523dc0cb1cdSDale Ghent case 0:
524dc0cb1cdSDale Ghent case IXGBE_MRQC_RT4TCEN:
525dc0cb1cdSDale Ghent /* RSS disabled cases */
526dc0cb1cdSDale Ghent reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
527dc0cb1cdSDale Ghent IXGBE_MRQC_RT8TCEN;
528dc0cb1cdSDale Ghent break;
529dc0cb1cdSDale Ghent case IXGBE_MRQC_RSSEN:
530dc0cb1cdSDale Ghent case IXGBE_MRQC_RTRSS4TCEN:
531dc0cb1cdSDale Ghent /* RSS enabled cases */
532dc0cb1cdSDale Ghent reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
533dc0cb1cdSDale Ghent IXGBE_MRQC_RTRSS8TCEN;
534dc0cb1cdSDale Ghent break;
535dc0cb1cdSDale Ghent default:
536dc0cb1cdSDale Ghent /*
537dc0cb1cdSDale Ghent * Unsupported value, assume stale data,
538dc0cb1cdSDale Ghent * overwrite no RSS
539dc0cb1cdSDale Ghent */
540dc0cb1cdSDale Ghent ASSERT(0);
541dc0cb1cdSDale Ghent reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
542dc0cb1cdSDale Ghent IXGBE_MRQC_RT8TCEN;
543dc0cb1cdSDale Ghent }
544dc0cb1cdSDale Ghent }
545dc0cb1cdSDale Ghent if (dcb_config->num_tcs.pg_tcs == 4) {
546dc0cb1cdSDale Ghent /* We support both VT-on and VT-off with 4 TCs. */
547dc0cb1cdSDale Ghent if (dcb_config->vt_mode)
548dc0cb1cdSDale Ghent reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
549dc0cb1cdSDale Ghent IXGBE_MRQC_VMDQRT4TCEN;
550dc0cb1cdSDale Ghent else
551dc0cb1cdSDale Ghent reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
552dc0cb1cdSDale Ghent IXGBE_MRQC_RTRSS4TCEN;
553dc0cb1cdSDale Ghent }
554dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
555dc0cb1cdSDale Ghent
556dc0cb1cdSDale Ghent /* Enable DCB for Tx with 8 TCs */
557dc0cb1cdSDale Ghent if (dcb_config->num_tcs.pg_tcs == 8)
558dc0cb1cdSDale Ghent reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
559dc0cb1cdSDale Ghent else {
560dc0cb1cdSDale Ghent /* We support both VT-on and VT-off with 4 TCs. */
561dc0cb1cdSDale Ghent reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
562dc0cb1cdSDale Ghent if (dcb_config->vt_mode)
563dc0cb1cdSDale Ghent reg |= IXGBE_MTQC_VT_ENA;
564dc0cb1cdSDale Ghent }
565dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
566dc0cb1cdSDale Ghent
567dc0cb1cdSDale Ghent /* Disable drop for all queues */
568dc0cb1cdSDale Ghent for (q = 0; q < 128; q++)
569dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_QDE,
570dc0cb1cdSDale Ghent (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
571dc0cb1cdSDale Ghent
572dc0cb1cdSDale Ghent /* Enable the Tx desc arbiter */
573dc0cb1cdSDale Ghent reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
574dc0cb1cdSDale Ghent reg &= ~IXGBE_RTTDCS_ARBDIS;
575dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
576dc0cb1cdSDale Ghent
577dc0cb1cdSDale Ghent /* Enable Security TX Buffer IFG for DCB */
578dc0cb1cdSDale Ghent reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
579dc0cb1cdSDale Ghent reg |= IXGBE_SECTX_DCB;
580dc0cb1cdSDale Ghent IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
581dc0cb1cdSDale Ghent
582dc0cb1cdSDale Ghent return IXGBE_SUCCESS;
583dc0cb1cdSDale Ghent }
584dc0cb1cdSDale Ghent
585dc0cb1cdSDale Ghent /**
586dc0cb1cdSDale Ghent * ixgbe_dcb_hw_config_82599 - Configure and enable DCB
587dc0cb1cdSDale Ghent * @hw: pointer to hardware structure
588*48ed61a7SRobert Mustacchi * @link_speed: unused
589*48ed61a7SRobert Mustacchi * @refill: refill credits index by traffic class
590*48ed61a7SRobert Mustacchi * @max: max credits index by traffic class
591*48ed61a7SRobert Mustacchi * @bwg_id: bandwidth grouping indexed by traffic class
592*48ed61a7SRobert Mustacchi * @tsa: transmission selection algorithm indexed by traffic class
593*48ed61a7SRobert Mustacchi * @map: priority to tc assignments indexed by priority
594dc0cb1cdSDale Ghent *
595dc0cb1cdSDale Ghent * Configure dcb settings and enable dcb mode.
596dc0cb1cdSDale Ghent */
ixgbe_dcb_hw_config_82599(struct ixgbe_hw * hw,int link_speed,u16 * refill,u16 * max,u8 * bwg_id,u8 * tsa,u8 * map)597dc0cb1cdSDale Ghent s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, int link_speed,
598dc0cb1cdSDale Ghent u16 *refill, u16 *max, u8 *bwg_id, u8 *tsa,
599dc0cb1cdSDale Ghent u8 *map)
600dc0cb1cdSDale Ghent {
601dc0cb1cdSDale Ghent UNREFERENCED_1PARAMETER(link_speed);
602dc0cb1cdSDale Ghent
603dc0cb1cdSDale Ghent ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, tsa,
604dc0cb1cdSDale Ghent map);
605dc0cb1cdSDale Ghent ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,
606dc0cb1cdSDale Ghent tsa);
607dc0cb1cdSDale Ghent ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,
608dc0cb1cdSDale Ghent tsa, map);
609dc0cb1cdSDale Ghent
610dc0cb1cdSDale Ghent return IXGBE_SUCCESS;
611dc0cb1cdSDale Ghent }
612dc0cb1cdSDale Ghent
613