1dc0cb1cdSDale Ghent /******************************************************************************
2*48ed61a7SRobert Mustacchi   SPDX-License-Identifier: BSD-3-Clause
3dc0cb1cdSDale Ghent 
4*48ed61a7SRobert Mustacchi   Copyright (c) 2001-2017, Intel Corporation
5dc0cb1cdSDale Ghent   All rights reserved.
6*48ed61a7SRobert Mustacchi 
7*48ed61a7SRobert Mustacchi   Redistribution and use in source and binary forms, with or without
8dc0cb1cdSDale Ghent   modification, are permitted provided that the following conditions are met:
9*48ed61a7SRobert Mustacchi 
10*48ed61a7SRobert Mustacchi    1. Redistributions of source code must retain the above copyright notice,
11dc0cb1cdSDale Ghent       this list of conditions and the following disclaimer.
12*48ed61a7SRobert Mustacchi 
13*48ed61a7SRobert Mustacchi    2. Redistributions in binary form must reproduce the above copyright
14*48ed61a7SRobert Mustacchi       notice, this list of conditions and the following disclaimer in the
15dc0cb1cdSDale Ghent       documentation and/or other materials provided with the distribution.
16*48ed61a7SRobert Mustacchi 
17*48ed61a7SRobert Mustacchi    3. Neither the name of the Intel Corporation nor the names of its
18*48ed61a7SRobert Mustacchi       contributors may be used to endorse or promote products derived from
19dc0cb1cdSDale Ghent       this software without specific prior written permission.
20*48ed61a7SRobert Mustacchi 
21dc0cb1cdSDale Ghent   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22*48ed61a7SRobert Mustacchi   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23*48ed61a7SRobert Mustacchi   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24*48ed61a7SRobert Mustacchi   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25*48ed61a7SRobert Mustacchi   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26*48ed61a7SRobert Mustacchi   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27*48ed61a7SRobert Mustacchi   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28*48ed61a7SRobert Mustacchi   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29*48ed61a7SRobert Mustacchi   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30dc0cb1cdSDale Ghent   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31dc0cb1cdSDale Ghent   POSSIBILITY OF SUCH DAMAGE.
32dc0cb1cdSDale Ghent 
33dc0cb1cdSDale Ghent ******************************************************************************/
34dc0cb1cdSDale Ghent /*$FreeBSD$*/
35dc0cb1cdSDale Ghent 
36dc0cb1cdSDale Ghent 
37dc0cb1cdSDale Ghent #include "ixgbe_type.h"
38dc0cb1cdSDale Ghent #include "ixgbe_dcb.h"
39dc0cb1cdSDale Ghent #include "ixgbe_dcb_82598.h"
40dc0cb1cdSDale Ghent 
41dc0cb1cdSDale Ghent /**
42dc0cb1cdSDale Ghent  * ixgbe_dcb_get_tc_stats_82598 - Return status data for each traffic class
43dc0cb1cdSDale Ghent  * @hw: pointer to hardware structure
44dc0cb1cdSDale Ghent  * @stats: pointer to statistics structure
45dc0cb1cdSDale Ghent  * @tc_count:  Number of elements in bwg_array.
46dc0cb1cdSDale Ghent  *
47dc0cb1cdSDale Ghent  * This function returns the status data for each of the Traffic Classes in use.
48dc0cb1cdSDale Ghent  */
ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw * hw,struct ixgbe_hw_stats * stats,u8 tc_count)49dc0cb1cdSDale Ghent s32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *hw,
50dc0cb1cdSDale Ghent 				 struct ixgbe_hw_stats *stats,
51dc0cb1cdSDale Ghent 				 u8 tc_count)
52dc0cb1cdSDale Ghent {
53dc0cb1cdSDale Ghent 	int tc;
54dc0cb1cdSDale Ghent 
55dc0cb1cdSDale Ghent 	DEBUGFUNC("dcb_get_tc_stats");
56dc0cb1cdSDale Ghent 
57dc0cb1cdSDale Ghent 	if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)
58dc0cb1cdSDale Ghent 		return IXGBE_ERR_PARAM;
59dc0cb1cdSDale Ghent 
60dc0cb1cdSDale Ghent 	/* Statistics pertaining to each traffic class */
61dc0cb1cdSDale Ghent 	for (tc = 0; tc < tc_count; tc++) {
62dc0cb1cdSDale Ghent 		/* Transmitted Packets */
63dc0cb1cdSDale Ghent 		stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc));
64dc0cb1cdSDale Ghent 		/* Transmitted Bytes */
65dc0cb1cdSDale Ghent 		stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC(tc));
66dc0cb1cdSDale Ghent 		/* Received Packets */
67dc0cb1cdSDale Ghent 		stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc));
68dc0cb1cdSDale Ghent 		/* Received Bytes */
69dc0cb1cdSDale Ghent 		stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC(tc));
70dc0cb1cdSDale Ghent 
71dc0cb1cdSDale Ghent #if 0
72dc0cb1cdSDale Ghent 		/* Can we get rid of these??  Consequently, getting rid
73dc0cb1cdSDale Ghent 		 * of the tc_stats structure.
74dc0cb1cdSDale Ghent 		 */
75dc0cb1cdSDale Ghent 		tc_stats_array[up]->in_overflow_discards = 0;
76dc0cb1cdSDale Ghent 		tc_stats_array[up]->out_overflow_discards = 0;
77dc0cb1cdSDale Ghent #endif
78dc0cb1cdSDale Ghent 	}
79dc0cb1cdSDale Ghent 
80dc0cb1cdSDale Ghent 	return IXGBE_SUCCESS;
81dc0cb1cdSDale Ghent }
82dc0cb1cdSDale Ghent 
83dc0cb1cdSDale Ghent /**
84dc0cb1cdSDale Ghent  * ixgbe_dcb_get_pfc_stats_82598 - Returns CBFC status data
85dc0cb1cdSDale Ghent  * @hw: pointer to hardware structure
86dc0cb1cdSDale Ghent  * @stats: pointer to statistics structure
87dc0cb1cdSDale Ghent  * @tc_count:  Number of elements in bwg_array.
88dc0cb1cdSDale Ghent  *
89dc0cb1cdSDale Ghent  * This function returns the CBFC status data for each of the Traffic Classes.
90dc0cb1cdSDale Ghent  */
ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw * hw,struct ixgbe_hw_stats * stats,u8 tc_count)91dc0cb1cdSDale Ghent s32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *hw,
92dc0cb1cdSDale Ghent 				  struct ixgbe_hw_stats *stats,
93dc0cb1cdSDale Ghent 				  u8 tc_count)
94dc0cb1cdSDale Ghent {
95dc0cb1cdSDale Ghent 	int tc;
96dc0cb1cdSDale Ghent 
97dc0cb1cdSDale Ghent 	DEBUGFUNC("dcb_get_pfc_stats");
98dc0cb1cdSDale Ghent 
99dc0cb1cdSDale Ghent 	if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)
100dc0cb1cdSDale Ghent 		return IXGBE_ERR_PARAM;
101dc0cb1cdSDale Ghent 
102dc0cb1cdSDale Ghent 	for (tc = 0; tc < tc_count; tc++) {
103dc0cb1cdSDale Ghent 		/* Priority XOFF Transmitted */
104dc0cb1cdSDale Ghent 		stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc));
105dc0cb1cdSDale Ghent 		/* Priority XOFF Received */
106dc0cb1cdSDale Ghent 		stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(tc));
107dc0cb1cdSDale Ghent 	}
108dc0cb1cdSDale Ghent 
109dc0cb1cdSDale Ghent 	return IXGBE_SUCCESS;
110dc0cb1cdSDale Ghent }
111dc0cb1cdSDale Ghent 
112dc0cb1cdSDale Ghent /**
113dc0cb1cdSDale Ghent  * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter
114dc0cb1cdSDale Ghent  * @hw: pointer to hardware structure
115*48ed61a7SRobert Mustacchi  * @refill: refill credits index by traffic class
116*48ed61a7SRobert Mustacchi  * @max: max credits index by traffic class
117*48ed61a7SRobert Mustacchi  * @tsa: transmission selection algorithm indexed by traffic class
118dc0cb1cdSDale Ghent  *
119dc0cb1cdSDale Ghent  * Configure Rx Data Arbiter and credits for each traffic class.
120dc0cb1cdSDale Ghent  */
ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw * hw,u16 * refill,u16 * max,u8 * tsa)121dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, u16 *refill,
122dc0cb1cdSDale Ghent 				      u16 *max, u8 *tsa)
123dc0cb1cdSDale Ghent {
124dc0cb1cdSDale Ghent 	u32 reg = 0;
125dc0cb1cdSDale Ghent 	u32 credit_refill = 0;
126dc0cb1cdSDale Ghent 	u32 credit_max = 0;
127dc0cb1cdSDale Ghent 	u8 i = 0;
128dc0cb1cdSDale Ghent 
129dc0cb1cdSDale Ghent 	reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA;
130dc0cb1cdSDale Ghent 	IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);
131dc0cb1cdSDale Ghent 
132dc0cb1cdSDale Ghent 	reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
133dc0cb1cdSDale Ghent 	/* Enable Arbiter */
134dc0cb1cdSDale Ghent 	reg &= ~IXGBE_RMCS_ARBDIS;
135dc0cb1cdSDale Ghent 	/* Enable Receive Recycle within the BWG */
136dc0cb1cdSDale Ghent 	reg |= IXGBE_RMCS_RRM;
137dc0cb1cdSDale Ghent 	/* Enable Deficit Fixed Priority arbitration*/
138dc0cb1cdSDale Ghent 	reg |= IXGBE_RMCS_DFP;
139dc0cb1cdSDale Ghent 
140dc0cb1cdSDale Ghent 	IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
141dc0cb1cdSDale Ghent 
142dc0cb1cdSDale Ghent 	/* Configure traffic class credits and priority */
143dc0cb1cdSDale Ghent 	for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
144dc0cb1cdSDale Ghent 		credit_refill = refill[i];
145dc0cb1cdSDale Ghent 		credit_max = max[i];
146dc0cb1cdSDale Ghent 
147dc0cb1cdSDale Ghent 		reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);
148dc0cb1cdSDale Ghent 
149dc0cb1cdSDale Ghent 		if (tsa[i] == ixgbe_dcb_tsa_strict)
150dc0cb1cdSDale Ghent 			reg |= IXGBE_RT2CR_LSP;
151dc0cb1cdSDale Ghent 
152dc0cb1cdSDale Ghent 		IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);
153dc0cb1cdSDale Ghent 	}
154dc0cb1cdSDale Ghent 
155dc0cb1cdSDale Ghent 	reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
156dc0cb1cdSDale Ghent 	reg |= IXGBE_RDRXCTL_RDMTS_1_2;
157dc0cb1cdSDale Ghent 	reg |= IXGBE_RDRXCTL_MPBEN;
158dc0cb1cdSDale Ghent 	reg |= IXGBE_RDRXCTL_MCEN;
159dc0cb1cdSDale Ghent 	IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
160dc0cb1cdSDale Ghent 
161dc0cb1cdSDale Ghent 	reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
162dc0cb1cdSDale Ghent 	/* Make sure there is enough descriptors before arbitration */
163dc0cb1cdSDale Ghent 	reg &= ~IXGBE_RXCTRL_DMBYPS;
164dc0cb1cdSDale Ghent 	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg);
165dc0cb1cdSDale Ghent 
166dc0cb1cdSDale Ghent 	return IXGBE_SUCCESS;
167dc0cb1cdSDale Ghent }
168dc0cb1cdSDale Ghent 
169dc0cb1cdSDale Ghent /**
170dc0cb1cdSDale Ghent  * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter
171dc0cb1cdSDale Ghent  * @hw: pointer to hardware structure
172*48ed61a7SRobert Mustacchi  * @refill: refill credits index by traffic class
173*48ed61a7SRobert Mustacchi  * @max: max credits index by traffic class
174*48ed61a7SRobert Mustacchi  * @bwg_id: bandwidth grouping indexed by traffic class
175*48ed61a7SRobert Mustacchi  * @tsa: transmission selection algorithm indexed by traffic class
176dc0cb1cdSDale Ghent  *
177dc0cb1cdSDale Ghent  * Configure Tx Descriptor Arbiter and credits for each traffic class.
178dc0cb1cdSDale Ghent  */
ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw * hw,u16 * refill,u16 * max,u8 * bwg_id,u8 * tsa)179dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
180dc0cb1cdSDale Ghent 					   u16 *refill, u16 *max, u8 *bwg_id,
181dc0cb1cdSDale Ghent 					   u8 *tsa)
182dc0cb1cdSDale Ghent {
183dc0cb1cdSDale Ghent 	u32 reg, max_credits;
184dc0cb1cdSDale Ghent 	u8 i;
185dc0cb1cdSDale Ghent 
186dc0cb1cdSDale Ghent 	reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);
187dc0cb1cdSDale Ghent 
188dc0cb1cdSDale Ghent 	/* Enable arbiter */
189dc0cb1cdSDale Ghent 	reg &= ~IXGBE_DPMCS_ARBDIS;
190dc0cb1cdSDale Ghent 	reg |= IXGBE_DPMCS_TSOEF;
191dc0cb1cdSDale Ghent 
192dc0cb1cdSDale Ghent 	/* Configure Max TSO packet size 34KB including payload and headers */
193dc0cb1cdSDale Ghent 	reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);
194dc0cb1cdSDale Ghent 
195dc0cb1cdSDale Ghent 	IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);
196dc0cb1cdSDale Ghent 
197dc0cb1cdSDale Ghent 	/* Configure traffic class credits and priority */
198dc0cb1cdSDale Ghent 	for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
199dc0cb1cdSDale Ghent 		max_credits = max[i];
200dc0cb1cdSDale Ghent 		reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
201dc0cb1cdSDale Ghent 		reg |= refill[i];
202dc0cb1cdSDale Ghent 		reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
203dc0cb1cdSDale Ghent 
204dc0cb1cdSDale Ghent 		if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
205dc0cb1cdSDale Ghent 			reg |= IXGBE_TDTQ2TCCR_GSP;
206dc0cb1cdSDale Ghent 
207dc0cb1cdSDale Ghent 		if (tsa[i] == ixgbe_dcb_tsa_strict)
208dc0cb1cdSDale Ghent 			reg |= IXGBE_TDTQ2TCCR_LSP;
209dc0cb1cdSDale Ghent 
210dc0cb1cdSDale Ghent 		IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
211dc0cb1cdSDale Ghent 	}
212dc0cb1cdSDale Ghent 
213dc0cb1cdSDale Ghent 	return IXGBE_SUCCESS;
214dc0cb1cdSDale Ghent }
215dc0cb1cdSDale Ghent 
216dc0cb1cdSDale Ghent /**
217dc0cb1cdSDale Ghent  * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter
218dc0cb1cdSDale Ghent  * @hw: pointer to hardware structure
219*48ed61a7SRobert Mustacchi  * @refill: refill credits index by traffic class
220*48ed61a7SRobert Mustacchi  * @max: max credits index by traffic class
221*48ed61a7SRobert Mustacchi  * @bwg_id: bandwidth grouping indexed by traffic class
222*48ed61a7SRobert Mustacchi  * @tsa: transmission selection algorithm indexed by traffic class
223dc0cb1cdSDale Ghent  *
224dc0cb1cdSDale Ghent  * Configure Tx Data Arbiter and credits for each traffic class.
225dc0cb1cdSDale Ghent  */
ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw * hw,u16 * refill,u16 * max,u8 * bwg_id,u8 * tsa)226dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
227dc0cb1cdSDale Ghent 					   u16 *refill, u16 *max, u8 *bwg_id,
228dc0cb1cdSDale Ghent 					   u8 *tsa)
229dc0cb1cdSDale Ghent {
230dc0cb1cdSDale Ghent 	u32 reg;
231dc0cb1cdSDale Ghent 	u8 i;
232dc0cb1cdSDale Ghent 
233dc0cb1cdSDale Ghent 	reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
234dc0cb1cdSDale Ghent 	/* Enable Data Plane Arbiter */
235dc0cb1cdSDale Ghent 	reg &= ~IXGBE_PDPMCS_ARBDIS;
236dc0cb1cdSDale Ghent 	/* Enable DFP and Transmit Recycle Mode */
237dc0cb1cdSDale Ghent 	reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM);
238dc0cb1cdSDale Ghent 
239dc0cb1cdSDale Ghent 	IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);
240dc0cb1cdSDale Ghent 
241dc0cb1cdSDale Ghent 	/* Configure traffic class credits and priority */
242dc0cb1cdSDale Ghent 	for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
243dc0cb1cdSDale Ghent 		reg = refill[i];
244dc0cb1cdSDale Ghent 		reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;
245dc0cb1cdSDale Ghent 		reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;
246dc0cb1cdSDale Ghent 
247dc0cb1cdSDale Ghent 		if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
248dc0cb1cdSDale Ghent 			reg |= IXGBE_TDPT2TCCR_GSP;
249dc0cb1cdSDale Ghent 
250dc0cb1cdSDale Ghent 		if (tsa[i] == ixgbe_dcb_tsa_strict)
251dc0cb1cdSDale Ghent 			reg |= IXGBE_TDPT2TCCR_LSP;
252dc0cb1cdSDale Ghent 
253dc0cb1cdSDale Ghent 		IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);
254dc0cb1cdSDale Ghent 	}
255dc0cb1cdSDale Ghent 
256dc0cb1cdSDale Ghent 	/* Enable Tx packet buffer division */
257dc0cb1cdSDale Ghent 	reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
258dc0cb1cdSDale Ghent 	reg |= IXGBE_DTXCTL_ENDBUBD;
259dc0cb1cdSDale Ghent 	IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);
260dc0cb1cdSDale Ghent 
261dc0cb1cdSDale Ghent 	return IXGBE_SUCCESS;
262dc0cb1cdSDale Ghent }
263dc0cb1cdSDale Ghent 
264dc0cb1cdSDale Ghent /**
265dc0cb1cdSDale Ghent  * ixgbe_dcb_config_pfc_82598 - Config priority flow control
266dc0cb1cdSDale Ghent  * @hw: pointer to hardware structure
267*48ed61a7SRobert Mustacchi  * @pfc_en: enabled pfc bitmask
268dc0cb1cdSDale Ghent  *
269dc0cb1cdSDale Ghent  * Configure Priority Flow Control for each traffic class.
270dc0cb1cdSDale Ghent  */
ixgbe_dcb_config_pfc_82598(struct ixgbe_hw * hw,u8 pfc_en)271dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en)
272dc0cb1cdSDale Ghent {
273dc0cb1cdSDale Ghent 	u32 fcrtl, reg;
274dc0cb1cdSDale Ghent 	u8 i;
275dc0cb1cdSDale Ghent 
276dc0cb1cdSDale Ghent 	/* Enable Transmit Priority Flow Control */
277dc0cb1cdSDale Ghent 	reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
278dc0cb1cdSDale Ghent 	reg &= ~IXGBE_RMCS_TFCE_802_3X;
279dc0cb1cdSDale Ghent 	reg |= IXGBE_RMCS_TFCE_PRIORITY;
280dc0cb1cdSDale Ghent 	IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
281dc0cb1cdSDale Ghent 
282dc0cb1cdSDale Ghent 	/* Enable Receive Priority Flow Control */
283dc0cb1cdSDale Ghent 	reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
284dc0cb1cdSDale Ghent 	reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE);
285dc0cb1cdSDale Ghent 
286dc0cb1cdSDale Ghent 	if (pfc_en)
287dc0cb1cdSDale Ghent 		reg |= IXGBE_FCTRL_RPFCE;
288dc0cb1cdSDale Ghent 
289dc0cb1cdSDale Ghent 	IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);
290dc0cb1cdSDale Ghent 
291dc0cb1cdSDale Ghent 	/* Configure PFC Tx thresholds per TC */
292dc0cb1cdSDale Ghent 	for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
293dc0cb1cdSDale Ghent 		if (!(pfc_en & (1 << i))) {
294dc0cb1cdSDale Ghent 			IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
295dc0cb1cdSDale Ghent 			IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
296dc0cb1cdSDale Ghent 			continue;
297dc0cb1cdSDale Ghent 		}
298dc0cb1cdSDale Ghent 
299dc0cb1cdSDale Ghent 		fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
300dc0cb1cdSDale Ghent 		reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
301dc0cb1cdSDale Ghent 		IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
302dc0cb1cdSDale Ghent 		IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
303dc0cb1cdSDale Ghent 	}
304dc0cb1cdSDale Ghent 
305dc0cb1cdSDale Ghent 	/* Configure pause time */
306dc0cb1cdSDale Ghent 	reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
307dc0cb1cdSDale Ghent 	for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
308dc0cb1cdSDale Ghent 		IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
309dc0cb1cdSDale Ghent 
310dc0cb1cdSDale Ghent 	/* Configure flow control refresh threshold value */
311dc0cb1cdSDale Ghent 	IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
312dc0cb1cdSDale Ghent 
313dc0cb1cdSDale Ghent 	return IXGBE_SUCCESS;
314dc0cb1cdSDale Ghent }
315dc0cb1cdSDale Ghent 
316dc0cb1cdSDale Ghent /**
317dc0cb1cdSDale Ghent  * ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics
318dc0cb1cdSDale Ghent  * @hw: pointer to hardware structure
319dc0cb1cdSDale Ghent  *
320dc0cb1cdSDale Ghent  * Configure queue statistics registers, all queues belonging to same traffic
321dc0cb1cdSDale Ghent  * class uses a single set of queue statistics counters.
322dc0cb1cdSDale Ghent  */
ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw * hw)323dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw)
324dc0cb1cdSDale Ghent {
325dc0cb1cdSDale Ghent 	u32 reg = 0;
326dc0cb1cdSDale Ghent 	u8 i = 0;
327dc0cb1cdSDale Ghent 	u8 j = 0;
328dc0cb1cdSDale Ghent 
329dc0cb1cdSDale Ghent 	/* Receive Queues stats setting -  8 queues per statistics reg */
330dc0cb1cdSDale Ghent 	for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) {
331dc0cb1cdSDale Ghent 		reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));
332dc0cb1cdSDale Ghent 		reg |= ((0x1010101) * j);
333dc0cb1cdSDale Ghent 		IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
334dc0cb1cdSDale Ghent 		reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));
335dc0cb1cdSDale Ghent 		reg |= ((0x1010101) * j);
336dc0cb1cdSDale Ghent 		IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);
337dc0cb1cdSDale Ghent 	}
338dc0cb1cdSDale Ghent 	/* Transmit Queues stats setting -  4 queues per statistics reg*/
339dc0cb1cdSDale Ghent 	for (i = 0; i < 8; i++) {
340dc0cb1cdSDale Ghent 		reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));
341dc0cb1cdSDale Ghent 		reg |= ((0x1010101) * i);
342dc0cb1cdSDale Ghent 		IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);
343dc0cb1cdSDale Ghent 	}
344dc0cb1cdSDale Ghent 
345dc0cb1cdSDale Ghent 	return IXGBE_SUCCESS;
346dc0cb1cdSDale Ghent }
347dc0cb1cdSDale Ghent 
348dc0cb1cdSDale Ghent /**
349dc0cb1cdSDale Ghent  * ixgbe_dcb_hw_config_82598 - Config and enable DCB
350dc0cb1cdSDale Ghent  * @hw: pointer to hardware structure
351*48ed61a7SRobert Mustacchi  * @link_speed: unused
352*48ed61a7SRobert Mustacchi  * @refill: refill credits index by traffic class
353*48ed61a7SRobert Mustacchi  * @max: max credits index by traffic class
354*48ed61a7SRobert Mustacchi  * @bwg_id: bandwidth grouping indexed by traffic class
355*48ed61a7SRobert Mustacchi  * @tsa: transmission selection algorithm indexed by traffic class
356dc0cb1cdSDale Ghent  *
357dc0cb1cdSDale Ghent  * Configure dcb settings and enable dcb mode.
358dc0cb1cdSDale Ghent  */
ixgbe_dcb_hw_config_82598(struct ixgbe_hw * hw,int link_speed,u16 * refill,u16 * max,u8 * bwg_id,u8 * tsa)359dc0cb1cdSDale Ghent s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, int link_speed,
360dc0cb1cdSDale Ghent 			      u16 *refill, u16 *max, u8 *bwg_id,
361dc0cb1cdSDale Ghent 			      u8 *tsa)
362dc0cb1cdSDale Ghent {
363dc0cb1cdSDale Ghent 	UNREFERENCED_1PARAMETER(link_speed);
364dc0cb1cdSDale Ghent 
365dc0cb1cdSDale Ghent 	ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
366dc0cb1cdSDale Ghent 	ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,
367dc0cb1cdSDale Ghent 					       tsa);
368dc0cb1cdSDale Ghent 	ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,
369dc0cb1cdSDale Ghent 					       tsa);
370dc0cb1cdSDale Ghent 	ixgbe_dcb_config_tc_stats_82598(hw);
371dc0cb1cdSDale Ghent 
372dc0cb1cdSDale Ghent 
373dc0cb1cdSDale Ghent 	return IXGBE_SUCCESS;
374dc0cb1cdSDale Ghent }
375