1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 /* IntelVersion: 1.144 v2-9-1-1_2009-6-10_NSW1 */ 30 31 #include "ixgbe_type.h" 32 #include "ixgbe_api.h" 33 #include "ixgbe_common.h" 34 #include "ixgbe_phy.h" 35 36 u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw); 37 s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw); 38 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 39 ixgbe_link_speed *speed, bool *autoneg); 40 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw); 41 s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num); 42 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw); 43 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 44 ixgbe_link_speed *speed, bool *link_up, bool link_up_wait_to_complete); 45 static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw, 46 ixgbe_link_speed speed, bool autoneg, 47 bool autoneg_wait_to_complete); 48 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw); 49 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, 50 ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete); 51 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw); 52 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 53 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 54 s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, 55 u32 vind, bool vlan_on); 56 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw); 57 s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val); 58 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val); 59 s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 60 u8 *eeprom_data); 61 u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw); 62 s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw); 63 void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw); 64 65 /* 66 * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count 67 * @hw: pointer to hardware structure 68 * 69 * Read PCIe configuration space, and get the MSI-X vector count from 70 * the capabilities table. 71 */ 72 u32 73 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw) 74 { 75 u32 msix_count = 18; 76 77 if (hw->mac.msix_vectors_from_pcie) { 78 msix_count = IXGBE_READ_PCIE_WORD(hw, 79 IXGBE_PCIE_MSIX_82598_CAPS); 80 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 81 82 /* 83 * MSI-X count is zero-based in HW, so increment to give 84 * proper value 85 */ 86 msix_count++; 87 } 88 return (msix_count); 89 } 90 91 /* 92 * ixgbe_init_ops_82598 - Inits func ptrs and MAC type 93 * @hw: pointer to hardware structure 94 * 95 * Initialize the function pointers and assign the MAC type for 82598. 96 * Does not touch the hardware. 97 */ 98 s32 99 ixgbe_init_ops_82598(struct ixgbe_hw *hw) 100 { 101 struct ixgbe_mac_info *mac = &hw->mac; 102 struct ixgbe_phy_info *phy = &hw->phy; 103 s32 ret_val; 104 105 ret_val = ixgbe_init_phy_ops_generic(hw); 106 ret_val = ixgbe_init_ops_generic(hw); 107 108 /* PHY */ 109 phy->ops.init = &ixgbe_init_phy_ops_82598; 110 111 /* MAC */ 112 mac->ops.reset_hw = &ixgbe_reset_hw_82598; 113 mac->ops.get_media_type = &ixgbe_get_media_type_82598; 114 mac->ops.get_supported_physical_layer = 115 &ixgbe_get_supported_physical_layer_82598; 116 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598; 117 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598; 118 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598; 119 120 /* RAR, Multicast, VLAN */ 121 mac->ops.set_vmdq = &ixgbe_set_vmdq_82598; 122 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82598; 123 mac->ops.set_vfta = &ixgbe_set_vfta_82598; 124 mac->ops.clear_vfta = &ixgbe_clear_vfta_82598; 125 126 /* Flow Control */ 127 mac->ops.fc_enable = &ixgbe_fc_enable_82598; 128 129 mac->mcft_size = 128; 130 mac->vft_size = 128; 131 mac->num_rar_entries = 16; 132 mac->max_tx_queues = 32; 133 mac->max_rx_queues = 64; 134 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw); 135 136 /* SFP+ Module */ 137 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598; 138 139 /* Link */ 140 mac->ops.check_link = &ixgbe_check_mac_link_82598; 141 mac->ops.setup_link = &ixgbe_setup_mac_link_82598; 142 mac->ops.setup_link_speed = &ixgbe_setup_mac_link_speed_82598; 143 mac->ops.get_link_capabilities = 144 &ixgbe_get_link_capabilities_82598; 145 146 return (ret_val); 147 } 148 149 /* 150 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init 151 * @hw: pointer to hardware structure 152 * 153 * Initialize any function pointers that were not able to be 154 * set during init_shared_code because the PHY/SFP type was 155 * not known. Perform the SFP init if necessary. 156 * 157 */ 158 s32 159 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) 160 { 161 struct ixgbe_mac_info *mac = &hw->mac; 162 struct ixgbe_phy_info *phy = &hw->phy; 163 s32 ret_val = IXGBE_SUCCESS; 164 u16 list_offset, data_offset; 165 166 /* Identify the PHY */ 167 phy->ops.identify(hw); 168 169 /* Overwrite the link function pointers if copper PHY */ 170 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 171 mac->ops.setup_link = &ixgbe_setup_copper_link_82598; 172 mac->ops.setup_link_speed = 173 &ixgbe_setup_copper_link_speed_82598; 174 mac->ops.get_link_capabilities = 175 &ixgbe_get_copper_link_capabilities_generic; 176 } 177 178 switch (hw->phy.type) { 179 case ixgbe_phy_tn: 180 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 181 phy->ops.get_firmware_version = 182 &ixgbe_get_phy_firmware_version_tnx; 183 break; 184 case ixgbe_phy_aq: 185 phy->ops.get_firmware_version = 186 &ixgbe_get_phy_firmware_version_aq; 187 break; 188 case ixgbe_phy_nl: 189 phy->ops.reset = &ixgbe_reset_phy_nl; 190 191 /* Call SFP+ identify routine to get the SFP+ module type */ 192 ret_val = phy->ops.identify_sfp(hw); 193 if (ret_val != IXGBE_SUCCESS) 194 goto out; 195 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) { 196 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 197 goto out; 198 } 199 200 /* Check to see if SFP+ module is supported */ 201 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, 202 &list_offset, &data_offset); 203 if (ret_val != IXGBE_SUCCESS) { 204 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 205 goto out; 206 } 207 break; 208 default: 209 break; 210 } 211 out: 212 return (ret_val); 213 } 214 215 /* 216 * ixgbe_get_link_capabilities_82598 - Determines link capabilities 217 * @hw: pointer to hardware structure 218 * @speed: pointer to link speed 219 * @autoneg: boolean auto-negotiation value 220 * 221 * Determines the link capabilities by reading the AUTOC register. 222 */ 223 static s32 224 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 225 ixgbe_link_speed *speed, bool *autoneg) 226 { 227 s32 status = IXGBE_SUCCESS; 228 u32 autoc = 0; 229 230 /* 231 * Determine link capabilities based on the stored value of AUTOC, 232 * which represents EEPROM defaults. If AUTOC value has not been 233 * stored, use the current register value. 234 */ 235 if (hw->mac.orig_link_settings_stored) 236 autoc = hw->mac.orig_autoc; 237 else 238 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 239 240 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 241 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 242 *speed = IXGBE_LINK_SPEED_1GB_FULL; 243 *autoneg = false; 244 break; 245 246 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 247 *speed = IXGBE_LINK_SPEED_10GB_FULL; 248 *autoneg = false; 249 break; 250 251 case IXGBE_AUTOC_LMS_1G_AN: 252 *speed = IXGBE_LINK_SPEED_1GB_FULL; 253 *autoneg = true; 254 break; 255 256 case IXGBE_AUTOC_LMS_KX4_AN: 257 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 258 *speed = IXGBE_LINK_SPEED_UNKNOWN; 259 if (autoc & IXGBE_AUTOC_KX4_SUPP) 260 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 261 if (autoc & IXGBE_AUTOC_KX_SUPP) 262 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 263 *autoneg = true; 264 break; 265 266 default: 267 status = IXGBE_ERR_LINK_SETUP; 268 break; 269 } 270 271 return (status); 272 } 273 274 /* 275 * ixgbe_get_media_type_82598 - Determines media type 276 * @hw: pointer to hardware structure 277 * 278 * Returns the media type (fiber, copper, backplane) 279 */ 280 static enum ixgbe_media_type 281 ixgbe_get_media_type_82598(struct ixgbe_hw *hw) 282 { 283 enum ixgbe_media_type media_type; 284 285 /* Detect if there is a copper PHY attached. */ 286 if (hw->phy.type == ixgbe_phy_cu_unknown || 287 hw->phy.type == ixgbe_phy_tn || 288 hw->phy.type == ixgbe_phy_aq) { 289 media_type = ixgbe_media_type_copper; 290 goto out; 291 } 292 293 /* Media type for I82598 is based on device ID */ 294 switch (hw->device_id) { 295 case IXGBE_DEV_ID_82598: 296 case IXGBE_DEV_ID_82598_BX: 297 /* Default device ID is mezzanine card KX/KX4 */ 298 media_type = ixgbe_media_type_backplane; 299 break; 300 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 301 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 302 case IXGBE_DEV_ID_82598EB_CX4: 303 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 304 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 305 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 306 case IXGBE_DEV_ID_82598EB_XF_LR: 307 case IXGBE_DEV_ID_82598EB_SFP_LOM: 308 media_type = ixgbe_media_type_fiber; 309 break; 310 case IXGBE_DEV_ID_82598AT: 311 media_type = ixgbe_media_type_copper; 312 break; 313 default: 314 media_type = ixgbe_media_type_unknown; 315 break; 316 } 317 out: 318 return (media_type); 319 } 320 321 /* 322 * ixgbe_fc_enable_82598 - Enable flow control 323 * @hw: pointer to hardware structure 324 * @packetbuf_num: packet buffer number (0-7) 325 * 326 * Enable flow control according to the current settings. 327 */ 328 s32 329 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num) 330 { 331 s32 ret_val = IXGBE_SUCCESS; 332 u32 fctrl_reg; 333 u32 rmcs_reg; 334 u32 reg; 335 336 DEBUGFUNC("ixgbe_fc_enable_82598"); 337 338 /* Negotiate the fc mode to use */ 339 ret_val = ixgbe_fc_autoneg(hw); 340 if (ret_val) 341 goto out; 342 343 /* Disable any previous flow control settings */ 344 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 345 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); 346 347 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 348 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); 349 350 /* 351 * The possible values of fc.current_mode are: 352 * 0: Flow control is completely disabled 353 * 1: Rx flow control is enabled (we can receive pause frames, 354 * but not send pause frames). 355 * 2: Tx flow control is enabled (we can send pause frames but 356 * we do not support receiving pause frames). 357 * 3: Both Rx and Tx flow control (symmetric) are enabled. 358 * other: Invalid. 359 */ 360 switch (hw->fc.current_mode) { 361 case ixgbe_fc_none: 362 /* 363 * Flow control is disabled by software override or autoneg. 364 * The code below will actually disable it in the HW. 365 */ 366 break; 367 case ixgbe_fc_rx_pause: 368 /* 369 * Rx Flow control is enabled and Tx Flow control is 370 * disabled by software override. Since there really 371 * isn't a way to advertise that we are capable of RX 372 * Pause ONLY, we will advertise that we support both 373 * symmetric and asymmetric Rx PAUSE. Later, we will 374 * disable the adapter's ability to send PAUSE frames. 375 */ 376 fctrl_reg |= IXGBE_FCTRL_RFCE; 377 break; 378 case ixgbe_fc_tx_pause: 379 /* 380 * Tx Flow control is enabled, and Rx Flow control is 381 * disabled by software override. 382 */ 383 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 384 break; 385 case ixgbe_fc_full: 386 /* Flow control (both Rx and Tx) is enabled by SW override. */ 387 fctrl_reg |= IXGBE_FCTRL_RFCE; 388 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 389 break; 390 default: 391 DEBUGOUT("Flow control param set incorrectly\n"); 392 ret_val = -IXGBE_ERR_CONFIG; 393 goto out; 394 } 395 396 /* Set 802.3x based flow control settings. */ 397 fctrl_reg |= IXGBE_FCTRL_DPF; 398 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg); 399 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); 400 401 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 402 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 403 if (hw->fc.send_xon) { 404 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), 405 (hw->fc.low_water | IXGBE_FCRTL_XONE)); 406 } else { 407 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), 408 hw->fc.low_water); 409 } 410 411 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), 412 (hw->fc.high_water | IXGBE_FCRTH_FCEN)); 413 } 414 415 /* Configure pause time (2 TCs per register) */ 416 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2)); 417 if ((packetbuf_num & 1) == 0) 418 reg = (reg & 0xFFFF0000) | hw->fc.pause_time; 419 else 420 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16); 421 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg); 422 423 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); 424 425 out: 426 return (ret_val); 427 } 428 429 /* 430 * ixgbe_setup_mac_link_82598 - Configures MAC link settings 431 * @hw: pointer to hardware structure 432 * 433 * Configures link settings based on values in the ixgbe_hw struct. 434 * Restarts the link. Performs autonegotiation if needed. 435 */ 436 static s32 437 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw) 438 { 439 u32 autoc_reg; 440 u32 links_reg; 441 u32 i; 442 s32 status = IXGBE_SUCCESS; 443 444 /* Restart link */ 445 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 446 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 447 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 448 449 /* Only poll for autoneg to complete if specified to do so */ 450 if (hw->phy.autoneg_wait_to_complete) { 451 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 452 IXGBE_AUTOC_LMS_KX4_AN || 453 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 454 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 455 links_reg = 0; /* Just in case Autoneg time = 0 */ 456 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 457 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 458 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 459 break; 460 msec_delay(100); 461 } 462 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 463 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 464 DEBUGOUT("Autonegotiation did not complete.\n"); 465 } 466 } 467 } 468 469 /* Add delay to filter out noises during initial link setup */ 470 msec_delay(50); 471 472 return (status); 473 } 474 475 /* 476 * ixgbe_check_mac_link_82598 - Get link/speed status 477 * @hw: pointer to hardware structure 478 * @speed: pointer to link speed 479 * @link_up: true is link is up, false otherwise 480 * @link_up_wait_to_complete: bool used to wait for link up or not 481 * 482 * Reads the links register to determine if link is up and the current speed 483 */ 484 static s32 485 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 486 bool *link_up, bool link_up_wait_to_complete) 487 { 488 u32 links_reg; 489 u32 i; 490 u16 link_reg, adapt_comp_reg; 491 492 /* 493 * SERDES PHY requires us to read link status from undocumented 494 * register 0xC79F. Bit 0 set indicates link is up/ready; clear 495 * indicates link down. OxC00C is read to check that the XAUI lanes 496 * are active. Bit 0 clear indicates active; set indicates inactive. 497 */ 498 if (hw->phy.type == ixgbe_phy_nl) { 499 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); 500 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); 501 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV, 502 &adapt_comp_reg); 503 if (link_up_wait_to_complete) { 504 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 505 if ((link_reg & 1) && 506 ((adapt_comp_reg & 1) == 0)) { 507 *link_up = true; 508 break; 509 } else { 510 *link_up = false; 511 } 512 msec_delay(100); 513 hw->phy.ops.read_reg(hw, 0xC79F, 514 IXGBE_TWINAX_DEV, &link_reg); 515 hw->phy.ops.read_reg(hw, 0xC00C, 516 IXGBE_TWINAX_DEV, &adapt_comp_reg); 517 } 518 } else { 519 if ((link_reg & 1) && 520 ((adapt_comp_reg & 1) == 0)) 521 *link_up = true; 522 else 523 *link_up = false; 524 } 525 526 if (*link_up == false) 527 goto out; 528 } 529 530 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 531 if (link_up_wait_to_complete) { 532 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 533 if (links_reg & IXGBE_LINKS_UP) { 534 *link_up = true; 535 break; 536 } else { 537 *link_up = false; 538 } 539 msec_delay(100); 540 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 541 } 542 } else { 543 if (links_reg & IXGBE_LINKS_UP) 544 *link_up = true; 545 else 546 *link_up = false; 547 } 548 549 if (links_reg & IXGBE_LINKS_SPEED) 550 *speed = IXGBE_LINK_SPEED_10GB_FULL; 551 else 552 *speed = IXGBE_LINK_SPEED_1GB_FULL; 553 554 /* if link is down, zero out the current_mode */ 555 if (*link_up == false) { 556 hw->fc.current_mode = ixgbe_fc_none; 557 hw->fc.fc_was_autonegged = false; 558 } 559 out: 560 return (IXGBE_SUCCESS); 561 } 562 563 /* 564 * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed 565 * @hw: pointer to hardware structure 566 * @speed: new link speed 567 * @autoneg: true if autonegotiation enabled 568 * @autoneg_wait_to_complete: true when waiting for completion is needed 569 * 570 * Set the link speed in the AUTOC register and restarts link. 571 */ 572 static s32 573 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw, 574 ixgbe_link_speed speed, bool autoneg, 575 bool autoneg_wait_to_complete) 576 { 577 s32 status = IXGBE_SUCCESS; 578 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 579 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 580 u32 autoc = curr_autoc; 581 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 582 583 /* Check to see if speed passed in is supported. */ 584 (void) ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg); 585 speed &= link_capabilities; 586 587 if (speed == IXGBE_LINK_SPEED_UNKNOWN) { 588 status = IXGBE_ERR_LINK_SETUP; 589 } else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN || 590 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 591 /* Set KX4/KX support according to speed requested */ 592 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK; 593 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 594 autoc |= IXGBE_AUTOC_KX4_SUPP; 595 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 596 autoc |= IXGBE_AUTOC_KX_SUPP; 597 if (autoc != curr_autoc) 598 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 599 } 600 601 if (status == IXGBE_SUCCESS) { 602 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete; 603 604 /* 605 * Setup and restart the link based on the new values in 606 * ixgbe_hw This will write the AUTOC register based on the new 607 * stored values 608 */ 609 status = ixgbe_setup_mac_link_82598(hw); 610 } 611 612 return (status); 613 } 614 615 616 /* 617 * ixgbe_setup_copper_link_82598 - Setup copper link settings 618 * @hw: pointer to hardware structure 619 * 620 * Configures link settings based on values in the ixgbe_hw struct. 621 * Restarts the link. Performs autonegotiation if needed. Restart 622 * phy and wait for autonegotiate to finish. Then synchronize the 623 * MAC and PHY. 624 */ 625 static s32 626 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw) 627 { 628 s32 status; 629 630 /* Restart autonegotiation on PHY */ 631 status = hw->phy.ops.setup_link(hw); 632 633 /* Set up MAC */ 634 (void) ixgbe_setup_mac_link_82598(hw); 635 636 return (status); 637 } 638 639 /* 640 * ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field 641 * @hw: pointer to hardware structure 642 * @speed: new link speed 643 * @autoneg: true if autonegotiation enabled 644 * @autoneg_wait_to_complete: true if waiting is needed to complete 645 * 646 * Sets the link speed in the AUTOC register in the MAC and restarts link. 647 */ 648 static s32 649 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, 650 ixgbe_link_speed speed, 651 bool autoneg, 652 bool autoneg_wait_to_complete) 653 { 654 s32 status; 655 656 /* Setup the PHY according to input speed */ 657 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, 658 autoneg_wait_to_complete); 659 660 /* Set up MAC */ 661 (void) ixgbe_setup_mac_link_82598(hw); 662 663 return (status); 664 } 665 666 /* 667 * ixgbe_reset_hw_82598 - Performs hardware reset 668 * @hw: pointer to hardware structure 669 * 670 * Resets the hardware by resetting the transmit and receive units, masks and 671 * clears all interrupts, performing a PHY reset, and performing a link (MAC) 672 * reset. 673 */ 674 static s32 675 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) 676 { 677 s32 status = IXGBE_SUCCESS; 678 s32 phy_status = IXGBE_SUCCESS; 679 u32 ctrl; 680 u32 gheccr; 681 u32 i; 682 u32 autoc; 683 u8 analog_val; 684 685 /* Call adapter stop to disable tx/rx and clear interrupts */ 686 hw->mac.ops.stop_adapter(hw); 687 688 /* 689 * Power up the Atlas Tx lanes if they are currently powered down. 690 * Atlas Tx lanes are powered down for MAC loopback tests, but 691 * they are not automatically restored on reset. 692 */ 693 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); 694 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { 695 /* Enable Tx Atlas so packets can be transmitted again */ 696 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 697 &analog_val); 698 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; 699 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 700 analog_val); 701 702 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 703 &analog_val); 704 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 705 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 706 analog_val); 707 708 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 709 &analog_val); 710 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 711 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 712 analog_val); 713 714 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 715 &analog_val); 716 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 717 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 718 analog_val); 719 } 720 721 /* Reset PHY */ 722 if (hw->phy.reset_disable == false) { 723 /* PHY ops must be identified and initialized prior to reset */ 724 725 /* Init PHY and function pointers, perform SFP setup */ 726 phy_status = hw->phy.ops.init(hw); 727 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED) 728 goto reset_hw_out; 729 else if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT) 730 goto no_phy_reset; 731 732 hw->phy.ops.reset(hw); 733 } 734 735 no_phy_reset: 736 /* 737 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 738 * access and verify no pending requests before reset 739 */ 740 status = ixgbe_disable_pcie_master(hw); 741 if (status != IXGBE_SUCCESS) { 742 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 743 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 744 } 745 746 /* 747 * Issue global reset to the MAC. This needs to be a SW reset. 748 * If link reset is used, it might reset the MAC when mng is using it 749 */ 750 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 751 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); 752 IXGBE_WRITE_FLUSH(hw); 753 754 /* Poll for reset bit to self-clear indicating reset is complete */ 755 for (i = 0; i < 10; i++) { 756 usec_delay(1); 757 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 758 if (!(ctrl & IXGBE_CTRL_RST)) 759 break; 760 } 761 if (ctrl & IXGBE_CTRL_RST) { 762 status = IXGBE_ERR_RESET_FAILED; 763 DEBUGOUT("Reset polling failed to complete.\n"); 764 } 765 766 msec_delay(50); 767 768 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); 769 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); 770 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); 771 772 /* 773 * Store the original AUTOC value if it has not been 774 * stored off yet. Otherwise restore the stored original 775 * AUTOC value since the reset operation sets back to deaults. 776 */ 777 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 778 if (hw->mac.orig_link_settings_stored == false) { 779 hw->mac.orig_autoc = autoc; 780 hw->mac.orig_link_settings_stored = true; 781 } else if (autoc != hw->mac.orig_autoc) { 782 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); 783 } 784 785 /* Store the permanent mac address */ 786 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 787 788 /* 789 * Store MAC address from RAR0, clear receive address registers, and 790 * clear the multicast table 791 */ 792 hw->mac.ops.init_rx_addrs(hw); 793 794 reset_hw_out: 795 if (phy_status != IXGBE_SUCCESS) 796 status = phy_status; 797 798 return (status); 799 } 800 801 /* 802 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address 803 * @hw: pointer to hardware struct 804 * @rar: receive address register index to associate with a VMDq index 805 * @vmdq: VMDq set index 806 */ 807 s32 808 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 809 { 810 u32 rar_high; 811 812 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 813 rar_high &= ~IXGBE_RAH_VIND_MASK; 814 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); 815 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 816 return (IXGBE_SUCCESS); 817 } 818 819 /* 820 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address 821 * @hw: pointer to hardware struct 822 * @rar: receive address register index to associate with a VMDq index 823 * @vmdq: VMDq clear index (not used in 82598, but elsewhere) 824 */ 825 static s32 826 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 827 { 828 u32 rar_high; 829 u32 rar_entries = hw->mac.num_rar_entries; 830 831 UNREFERENCED_PARAMETER(vmdq); 832 833 if (rar < rar_entries) { 834 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 835 if (rar_high & IXGBE_RAH_VIND_MASK) { 836 rar_high &= ~IXGBE_RAH_VIND_MASK; 837 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 838 } 839 } else { 840 DEBUGOUT1("RAR index %d is out of range.\n", rar); 841 } 842 843 return (IXGBE_SUCCESS); 844 } 845 846 /* 847 * ixgbe_set_vfta_82598 - Set VLAN filter table 848 * @hw: pointer to hardware structure 849 * @vlan: VLAN id to write to VLAN filter 850 * @vind: VMDq output index that maps queue to VLAN id in VFTA 851 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 852 * 853 * Turn on/off specified VLAN in the VLAN filter table. 854 */ 855 s32 856 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on) 857 { 858 u32 regindex; 859 u32 bitindex; 860 u32 bits; 861 u32 vftabyte; 862 863 if (vlan > 4095) 864 return (IXGBE_ERR_PARAM); 865 866 /* Determine 32-bit word position in array */ 867 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */ 868 869 /* Determine the location of the (VMD) queue index */ 870 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ 871 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ 872 873 /* Set the nibble for VMD queue index */ 874 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex)); 875 bits &= (~(0x0F << bitindex)); 876 bits |= (vind << bitindex); 877 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits); 878 879 /* Determine the location of the bit for this VLAN id */ 880 bitindex = vlan & 0x1F; /* lower five bits */ 881 882 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 883 if (vlan_on) 884 /* Turn on this VLAN id */ 885 bits |= (1 << bitindex); 886 else 887 /* Turn off this VLAN id */ 888 bits &= ~(1 << bitindex); 889 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); 890 891 return (IXGBE_SUCCESS); 892 } 893 894 /* 895 * ixgbe_clear_vfta_82598 - Clear VLAN filter table 896 * @hw: pointer to hardware structure 897 * 898 * Clears the VLAN filer table, and the VMDq index associated with the filter 899 */ 900 static s32 901 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) 902 { 903 u32 offset; 904 u32 vlanbyte; 905 906 for (offset = 0; offset < hw->mac.vft_size; offset++) 907 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 908 909 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) 910 for (offset = 0; offset < hw->mac.vft_size; offset++) 911 IXGBE_WRITE_REG(hw, 912 IXGBE_VFTAVIND(vlanbyte, offset), 0); 913 914 return (IXGBE_SUCCESS); 915 } 916 917 /* 918 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register 919 * @hw: pointer to hardware structure 920 * @reg: analog register to read 921 * @val: read value 922 * 923 * Performs read operation to Atlas analog register specified. 924 */ 925 s32 926 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) 927 { 928 u32 atlas_ctl; 929 930 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, 931 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); 932 IXGBE_WRITE_FLUSH(hw); 933 usec_delay(10); 934 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 935 *val = (u8)atlas_ctl; 936 937 return (IXGBE_SUCCESS); 938 } 939 940 /* 941 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register 942 * @hw: pointer to hardware structure 943 * @reg: atlas register to write 944 * @val: value to write 945 * 946 * Performs write operation to Atlas analog register specified. 947 */ 948 s32 949 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) 950 { 951 u32 atlas_ctl; 952 953 atlas_ctl = (reg << 8) | val; 954 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); 955 IXGBE_WRITE_FLUSH(hw); 956 usec_delay(10); 957 958 return (IXGBE_SUCCESS); 959 } 960 961 /* 962 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface. 963 * @hw: pointer to hardware structure 964 * @byte_offset: EEPROM byte offset to read 965 * @eeprom_data: value read 966 * 967 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface. 968 */ 969 s32 970 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 971 u8 *eeprom_data) 972 { 973 s32 status = IXGBE_SUCCESS; 974 u16 sfp_addr = 0; 975 u16 sfp_data = 0; 976 u16 sfp_stat = 0; 977 u32 i; 978 979 if (hw->phy.type == ixgbe_phy_nl) { 980 /* 981 * NetLogic phy SDA/SCL registers are at addresses 0xC30A to 982 * 0xC30D. These registers are used to talk to the SFP+ 983 * module's EEPROM through the SDA/SCL (I2C) interface. 984 */ 985 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset; 986 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); 987 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, 988 IXGBE_MDIO_PMA_PMD_DEV_TYPE, sfp_addr); 989 990 /* Poll status */ 991 for (i = 0; i < 100; i++) { 992 hw->phy.ops.read_reg(hw, 993 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, 994 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_stat); 995 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK; 996 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS) 997 break; 998 msec_delay(10); 999 } 1000 1001 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) { 1002 DEBUGOUT("EEPROM read did not pass.\n"); 1003 status = IXGBE_ERR_SFP_NOT_PRESENT; 1004 goto out; 1005 } 1006 1007 /* Read data */ 1008 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, 1009 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data); 1010 1011 *eeprom_data = (u8)(sfp_data >> 8); 1012 } else { 1013 status = IXGBE_ERR_PHY; 1014 goto out; 1015 } 1016 1017 out: 1018 return (status); 1019 } 1020 1021 /* 1022 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type 1023 * @hw: pointer to hardware structure 1024 * 1025 * Determines physical layer capabilities of the current configuration. 1026 */ 1027 u32 1028 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw) 1029 { 1030 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1031 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1032 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 1033 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 1034 u16 ext_ability = 0; 1035 1036 hw->phy.ops.identify(hw); 1037 1038 /* 1039 * Copper PHY must be checked before AUTOC LMS to determine correct 1040 * physical layer because 10GBase-T PHYs use LMS = KX4/KX 1041 */ 1042 if (hw->phy.type == ixgbe_phy_tn || 1043 hw->phy.type == ixgbe_phy_cu_unknown) { 1044 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 1045 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 1046 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 1047 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 1048 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 1049 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 1050 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 1051 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 1052 goto out; 1053 } 1054 1055 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 1056 case IXGBE_AUTOC_LMS_1G_AN: 1057 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 1058 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX) 1059 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1060 else 1061 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX; 1062 break; 1063 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 1064 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4) 1065 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 1066 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4) 1067 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1068 else /* XAUI */ 1069 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1070 break; 1071 case IXGBE_AUTOC_LMS_KX4_AN: 1072 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 1073 if (autoc & IXGBE_AUTOC_KX_SUPP) 1074 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1075 if (autoc & IXGBE_AUTOC_KX4_SUPP) 1076 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1077 break; 1078 default: 1079 break; 1080 } 1081 1082 if (hw->phy.type == ixgbe_phy_nl) { 1083 hw->phy.ops.identify_sfp(hw); 1084 1085 switch (hw->phy.sfp_type) { 1086 case ixgbe_sfp_type_da_cu: 1087 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1088 break; 1089 case ixgbe_sfp_type_sr: 1090 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1091 break; 1092 case ixgbe_sfp_type_lr: 1093 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1094 break; 1095 default: 1096 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1097 break; 1098 } 1099 } 1100 1101 switch (hw->device_id) { 1102 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 1103 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1104 break; 1105 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 1106 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 1107 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 1108 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1109 break; 1110 case IXGBE_DEV_ID_82598EB_XF_LR: 1111 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1112 break; 1113 default: 1114 break; 1115 } 1116 1117 out: 1118 return (physical_layer); 1119 } 1120 1121 /* 1122 * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple 1123 * port devices. 1124 * @hw: pointer to the HW structure 1125 * 1126 * Calls common function and corrects issue with some single port devices 1127 * that enable LAN1 but not LAN0. 1128 */ 1129 void 1130 ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw) 1131 { 1132 struct ixgbe_bus_info *bus = &hw->bus; 1133 u16 pci_gen, pci_ctrl2; 1134 1135 ixgbe_set_lan_id_multi_port_pcie(hw); 1136 1137 /* check if LAN0 is disabled */ 1138 hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen); 1139 if ((pci_gen != 0) && (pci_gen != 0xFFFF)) { 1140 hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2); 1141 1142 /* if LAN0 is completely disabled force function to 0 */ 1143 if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) && 1144 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) && 1145 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) { 1146 bus->func = 0; 1147 } 1148 } 1149 } 1150