1*22a84b8dSQuaker Fang /* 2*22a84b8dSQuaker Fang * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 3*22a84b8dSQuaker Fang * Use is subject to license terms. 4*22a84b8dSQuaker Fang */ 5*22a84b8dSQuaker Fang 6*22a84b8dSQuaker Fang /* 7*22a84b8dSQuaker Fang * Copyright (c) 2009, Intel Corporation 8*22a84b8dSQuaker Fang * All rights reserved. 9*22a84b8dSQuaker Fang */ 10*22a84b8dSQuaker Fang 11*22a84b8dSQuaker Fang /* 12*22a84b8dSQuaker Fang * Copyright (c) 2006 13*22a84b8dSQuaker Fang * Copyright (c) 2007 14*22a84b8dSQuaker Fang * Damien Bergamini <damien.bergamini@free.fr> 15*22a84b8dSQuaker Fang * 16*22a84b8dSQuaker Fang * Permission to use, copy, modify, and distribute this software for any 17*22a84b8dSQuaker Fang * purpose with or without fee is hereby granted, provided that the above 18*22a84b8dSQuaker Fang * copyright notice and this permission notice appear in all copies. 19*22a84b8dSQuaker Fang * 20*22a84b8dSQuaker Fang * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 21*22a84b8dSQuaker Fang * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 22*22a84b8dSQuaker Fang * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 23*22a84b8dSQuaker Fang * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 24*22a84b8dSQuaker Fang * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 25*22a84b8dSQuaker Fang * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 26*22a84b8dSQuaker Fang * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 27*22a84b8dSQuaker Fang */ 28*22a84b8dSQuaker Fang 29*22a84b8dSQuaker Fang #ifndef _IWP_VAR_H 30*22a84b8dSQuaker Fang #define _IWP_VAR_H 31*22a84b8dSQuaker Fang 32*22a84b8dSQuaker Fang #ifdef __cplusplus 33*22a84b8dSQuaker Fang extern "C" { 34*22a84b8dSQuaker Fang #endif 35*22a84b8dSQuaker Fang 36*22a84b8dSQuaker Fang #define IWP_DMA_SYNC(area, flag) \ 37*22a84b8dSQuaker Fang (void) ddi_dma_sync((area).dma_hdl, (area).offset, \ 38*22a84b8dSQuaker Fang (area).alength, (flag)) 39*22a84b8dSQuaker Fang 40*22a84b8dSQuaker Fang #define IWP_CHK_FAST_RECOVER(sc) \ 41*22a84b8dSQuaker Fang (sc->sc_ic.ic_state == IEEE80211_S_RUN && \ 42*22a84b8dSQuaker Fang sc->sc_ic.ic_opmode == IEEE80211_M_STA) 43*22a84b8dSQuaker Fang 44*22a84b8dSQuaker Fang typedef struct iwp_dma_area { 45*22a84b8dSQuaker Fang ddi_acc_handle_t acc_hdl; /* handle for memory */ 46*22a84b8dSQuaker Fang caddr_t mem_va; /* CPU VA of memory */ 47*22a84b8dSQuaker Fang uint32_t nslots; /* number of slots */ 48*22a84b8dSQuaker Fang uint32_t size; /* size per slot */ 49*22a84b8dSQuaker Fang size_t alength; /* allocated size */ 50*22a84b8dSQuaker Fang /* >= product of above */ 51*22a84b8dSQuaker Fang ddi_dma_handle_t dma_hdl; /* DMA handle */ 52*22a84b8dSQuaker Fang offset_t offset; /* relative to handle */ 53*22a84b8dSQuaker Fang ddi_dma_cookie_t cookie; /* associated cookie */ 54*22a84b8dSQuaker Fang uint32_t ncookies; 55*22a84b8dSQuaker Fang uint32_t token; /* arbitrary identifier */ 56*22a84b8dSQuaker Fang } iwp_dma_t; 57*22a84b8dSQuaker Fang 58*22a84b8dSQuaker Fang typedef struct iwp_tx_data { 59*22a84b8dSQuaker Fang iwp_dma_t dma_data; /* for sending frames */ 60*22a84b8dSQuaker Fang iwp_tx_desc_t *desc; 61*22a84b8dSQuaker Fang uint32_t paddr_desc; 62*22a84b8dSQuaker Fang iwp_cmd_t *cmd; 63*22a84b8dSQuaker Fang uint32_t paddr_cmd; 64*22a84b8dSQuaker Fang } iwp_tx_data_t; 65*22a84b8dSQuaker Fang 66*22a84b8dSQuaker Fang typedef struct iwp_tx_ring { 67*22a84b8dSQuaker Fang iwp_dma_t dma_desc; /* for descriptor itself */ 68*22a84b8dSQuaker Fang iwp_dma_t dma_cmd; /* for command to ucode */ 69*22a84b8dSQuaker Fang iwp_tx_data_t *data; 70*22a84b8dSQuaker Fang int qid; /* ID of queue */ 71*22a84b8dSQuaker Fang int count; 72*22a84b8dSQuaker Fang int window; 73*22a84b8dSQuaker Fang int queued; 74*22a84b8dSQuaker Fang int cur; 75*22a84b8dSQuaker Fang int desc_cur; 76*22a84b8dSQuaker Fang } iwp_tx_ring_t; 77*22a84b8dSQuaker Fang 78*22a84b8dSQuaker Fang typedef struct iwp_rx_data { 79*22a84b8dSQuaker Fang iwp_dma_t dma_data; 80*22a84b8dSQuaker Fang } iwp_rx_data_t; 81*22a84b8dSQuaker Fang 82*22a84b8dSQuaker Fang typedef struct iwp_rx_ring { 83*22a84b8dSQuaker Fang iwp_dma_t dma_desc; 84*22a84b8dSQuaker Fang uint32_t *desc; 85*22a84b8dSQuaker Fang iwp_rx_data_t data[RX_QUEUE_SIZE]; 86*22a84b8dSQuaker Fang int cur; 87*22a84b8dSQuaker Fang } iwp_rx_ring_t; 88*22a84b8dSQuaker Fang 89*22a84b8dSQuaker Fang 90*22a84b8dSQuaker Fang typedef struct iwp_amrr { 91*22a84b8dSQuaker Fang ieee80211_node_t in; 92*22a84b8dSQuaker Fang uint32_t txcnt; 93*22a84b8dSQuaker Fang uint32_t retrycnt; 94*22a84b8dSQuaker Fang uint32_t success; 95*22a84b8dSQuaker Fang uint32_t success_threshold; 96*22a84b8dSQuaker Fang int recovery; 97*22a84b8dSQuaker Fang volatile uint32_t ht_mcs_idx; 98*22a84b8dSQuaker Fang } iwp_amrr_t; 99*22a84b8dSQuaker Fang 100*22a84b8dSQuaker Fang struct iwp_phy_rx { 101*22a84b8dSQuaker Fang uint8_t flag; 102*22a84b8dSQuaker Fang uint8_t reserved[3]; 103*22a84b8dSQuaker Fang uint8_t buf[128]; 104*22a84b8dSQuaker Fang }; 105*22a84b8dSQuaker Fang 106*22a84b8dSQuaker Fang struct iwp_beacon_missed { 107*22a84b8dSQuaker Fang uint32_t consecutive; 108*22a84b8dSQuaker Fang uint32_t total; 109*22a84b8dSQuaker Fang uint32_t expected; 110*22a84b8dSQuaker Fang uint32_t received; 111*22a84b8dSQuaker Fang }; 112*22a84b8dSQuaker Fang 113*22a84b8dSQuaker Fang #define PHY_MODE_G (0x1) 114*22a84b8dSQuaker Fang #define PHY_MODE_A (0x2) 115*22a84b8dSQuaker Fang #define PHY_MODE_N (0x4) 116*22a84b8dSQuaker Fang 117*22a84b8dSQuaker Fang #define ANT_A (0x1) 118*22a84b8dSQuaker Fang #define ANT_B (0x2) 119*22a84b8dSQuaker Fang #define ANT_C (0x4) 120*22a84b8dSQuaker Fang 121*22a84b8dSQuaker Fang #define PA_TYPE_SYSTEM (0) 122*22a84b8dSQuaker Fang #define PA_TYPE_MIX (1) 123*22a84b8dSQuaker Fang #define PA_TYPE_INTER (2) 124*22a84b8dSQuaker Fang 125*22a84b8dSQuaker Fang struct iwp_chip_param { 126*22a84b8dSQuaker Fang uint32_t phy_mode; 127*22a84b8dSQuaker Fang uint8_t tx_ant; 128*22a84b8dSQuaker Fang uint8_t rx_ant; 129*22a84b8dSQuaker Fang uint16_t pa_type; 130*22a84b8dSQuaker Fang }; 131*22a84b8dSQuaker Fang 132*22a84b8dSQuaker Fang typedef struct iwp_softc { 133*22a84b8dSQuaker Fang struct ieee80211com sc_ic; 134*22a84b8dSQuaker Fang dev_info_t *sc_dip; 135*22a84b8dSQuaker Fang int (*sc_newstate)(struct ieee80211com *, 136*22a84b8dSQuaker Fang enum ieee80211_state, int); 137*22a84b8dSQuaker Fang void (*sc_recv_action)(ieee80211_node_t *, 138*22a84b8dSQuaker Fang const uint8_t *, const uint8_t *); 139*22a84b8dSQuaker Fang int (*sc_send_action)(ieee80211_node_t *, 140*22a84b8dSQuaker Fang int, int, uint16_t[4]); 141*22a84b8dSQuaker Fang volatile uint32_t sc_cmd_flag; 142*22a84b8dSQuaker Fang volatile uint32_t sc_cmd_accum; 143*22a84b8dSQuaker Fang 144*22a84b8dSQuaker Fang enum ieee80211_state sc_ostate; 145*22a84b8dSQuaker Fang kmutex_t sc_glock; 146*22a84b8dSQuaker Fang kmutex_t sc_mt_lock; 147*22a84b8dSQuaker Fang kmutex_t sc_tx_lock; 148*22a84b8dSQuaker Fang kcondvar_t sc_mt_cv; 149*22a84b8dSQuaker Fang kcondvar_t sc_tx_cv; 150*22a84b8dSQuaker Fang kcondvar_t sc_cmd_cv; 151*22a84b8dSQuaker Fang kcondvar_t sc_fw_cv; 152*22a84b8dSQuaker Fang kcondvar_t sc_put_seg_cv; 153*22a84b8dSQuaker Fang kcondvar_t sc_ucode_cv; 154*22a84b8dSQuaker Fang 155*22a84b8dSQuaker Fang kthread_t *sc_mf_thread; 156*22a84b8dSQuaker Fang volatile uint32_t sc_mf_thread_switch; 157*22a84b8dSQuaker Fang 158*22a84b8dSQuaker Fang volatile uint32_t sc_flags; 159*22a84b8dSQuaker Fang uint32_t sc_dmabuf_sz; 160*22a84b8dSQuaker Fang uint16_t sc_clsz; 161*22a84b8dSQuaker Fang uint8_t sc_rev; 162*22a84b8dSQuaker Fang uint8_t sc_resv; 163*22a84b8dSQuaker Fang uint16_t sc_assoc_id; 164*22a84b8dSQuaker Fang uint16_t sc_reserved0; 165*22a84b8dSQuaker Fang 166*22a84b8dSQuaker Fang /* shared area */ 167*22a84b8dSQuaker Fang iwp_dma_t sc_dma_sh; 168*22a84b8dSQuaker Fang iwp_shared_t *sc_shared; 169*22a84b8dSQuaker Fang /* keep warm area */ 170*22a84b8dSQuaker Fang iwp_dma_t sc_dma_kw; 171*22a84b8dSQuaker Fang /* tx scheduler base address */ 172*22a84b8dSQuaker Fang uint32_t sc_scd_base_addr; 173*22a84b8dSQuaker Fang 174*22a84b8dSQuaker Fang uint32_t sc_hw_rev; 175*22a84b8dSQuaker Fang struct iwp_phy_rx sc_rx_phy_res; 176*22a84b8dSQuaker Fang 177*22a84b8dSQuaker Fang iwp_tx_ring_t sc_txq[IWP_NUM_QUEUES]; 178*22a84b8dSQuaker Fang iwp_rx_ring_t sc_rxq; 179*22a84b8dSQuaker Fang 180*22a84b8dSQuaker Fang /* firmware dma */ 181*22a84b8dSQuaker Fang iwp_firmware_hdr_t *sc_hdr; 182*22a84b8dSQuaker Fang char *sc_boot; 183*22a84b8dSQuaker Fang iwp_dma_t sc_dma_fw_text; 184*22a84b8dSQuaker Fang iwp_dma_t sc_dma_fw_init_text; 185*22a84b8dSQuaker Fang iwp_dma_t sc_dma_fw_data; 186*22a84b8dSQuaker Fang iwp_dma_t sc_dma_fw_data_bak; 187*22a84b8dSQuaker Fang iwp_dma_t sc_dma_fw_init_data; 188*22a84b8dSQuaker Fang 189*22a84b8dSQuaker Fang ddi_acc_handle_t sc_cfg_handle; 190*22a84b8dSQuaker Fang caddr_t sc_cfg_base; 191*22a84b8dSQuaker Fang ddi_acc_handle_t sc_handle; 192*22a84b8dSQuaker Fang caddr_t sc_base; 193*22a84b8dSQuaker Fang ddi_intr_handle_t *sc_intr_htable; 194*22a84b8dSQuaker Fang uint_t sc_intr_pri; 195*22a84b8dSQuaker Fang 196*22a84b8dSQuaker Fang iwp_rxon_cmd_t sc_config; 197*22a84b8dSQuaker Fang iwp_rxon_cmd_t sc_config_save; 198*22a84b8dSQuaker Fang 199*22a84b8dSQuaker Fang uint8_t sc_eep_map[IWP_SP_EEPROM_SIZE]; 200*22a84b8dSQuaker Fang struct iwp_eep_calibration *sc_eep_calib; 201*22a84b8dSQuaker Fang struct iwp_calib_results sc_calib_results; 202*22a84b8dSQuaker Fang uint32_t sc_scd_base; 203*22a84b8dSQuaker Fang 204*22a84b8dSQuaker Fang struct iwp_alive_resp sc_card_alive_run; 205*22a84b8dSQuaker Fang struct iwp_init_alive_resp sc_card_alive_init; 206*22a84b8dSQuaker Fang iwp_ht_conf_t sc_ht_conf; 207*22a84b8dSQuaker Fang uint16_t sc_dev_id; 208*22a84b8dSQuaker Fang 209*22a84b8dSQuaker Fang uint32_t sc_tx_timer; 210*22a84b8dSQuaker Fang uint32_t sc_scan_pending; 211*22a84b8dSQuaker Fang uint8_t *sc_fw_bin; 212*22a84b8dSQuaker Fang 213*22a84b8dSQuaker Fang ddi_softint_handle_t sc_soft_hdl; 214*22a84b8dSQuaker Fang 215*22a84b8dSQuaker Fang uint32_t sc_rx_softint_pending; 216*22a84b8dSQuaker Fang uint32_t sc_need_reschedule; 217*22a84b8dSQuaker Fang 218*22a84b8dSQuaker Fang clock_t sc_clk; 219*22a84b8dSQuaker Fang 220*22a84b8dSQuaker Fang struct iwp_chip_param sc_chip_param; 221*22a84b8dSQuaker Fang 222*22a84b8dSQuaker Fang /* kstats */ 223*22a84b8dSQuaker Fang uint32_t sc_tx_nobuf; 224*22a84b8dSQuaker Fang uint32_t sc_rx_nobuf; 225*22a84b8dSQuaker Fang uint32_t sc_tx_err; 226*22a84b8dSQuaker Fang uint32_t sc_rx_err; 227*22a84b8dSQuaker Fang uint32_t sc_tx_retries; 228*22a84b8dSQuaker Fang } iwp_sc_t; 229*22a84b8dSQuaker Fang 230*22a84b8dSQuaker Fang #define SC_CMD_FLG_NONE (0) 231*22a84b8dSQuaker Fang #define SC_CMD_FLG_PENDING (1) 232*22a84b8dSQuaker Fang #define SC_CMD_FLG_DONE (2) 233*22a84b8dSQuaker Fang 234*22a84b8dSQuaker Fang #define IWP_F_ATTACHED (1 << 0) 235*22a84b8dSQuaker Fang #define IWP_F_CMD_DONE (1 << 1) 236*22a84b8dSQuaker Fang #define IWP_F_FW_INIT (1 << 2) 237*22a84b8dSQuaker Fang #define IWP_F_HW_ERR_RECOVER (1 << 3) 238*22a84b8dSQuaker Fang #define IWP_F_RATE_AUTO_CTL (1 << 4) 239*22a84b8dSQuaker Fang #define IWP_F_RUNNING (1 << 5) 240*22a84b8dSQuaker Fang #define IWP_F_SCANNING (1 << 6) 241*22a84b8dSQuaker Fang #define IWP_F_SUSPEND (1 << 7) 242*22a84b8dSQuaker Fang #define IWP_F_RADIO_OFF (1 << 8) 243*22a84b8dSQuaker Fang #define IWP_F_STATISTICS (1 << 9) 244*22a84b8dSQuaker Fang #define IWP_F_READY (1 << 10) 245*22a84b8dSQuaker Fang #define IWP_F_PUT_SEG (1 << 11) 246*22a84b8dSQuaker Fang #define IWP_F_QUIESCED (1 << 12) 247*22a84b8dSQuaker Fang #define IWP_F_LAZY_RESUME (1 << 13) 248*22a84b8dSQuaker Fang 249*22a84b8dSQuaker Fang #define IWP_SUCCESS 0 250*22a84b8dSQuaker Fang #define IWP_FAIL EIO 251*22a84b8dSQuaker Fang 252*22a84b8dSQuaker Fang 253*22a84b8dSQuaker Fang #ifdef __cplusplus 254*22a84b8dSQuaker Fang } 255*22a84b8dSQuaker Fang #endif 256*22a84b8dSQuaker Fang 257*22a84b8dSQuaker Fang #endif /* _IWP_VAR_H */ 258