xref: /illumos-gate/usr/src/uts/common/io/iwn/if_iwnreg.h (revision b302a200)
1fd43cf6eSHans Rosenfeld /*	$NetBSD: if_iwnreg.h,v 1.15 2014/11/09 14:40:54 nonaka Exp $	*/
2fd43cf6eSHans Rosenfeld /*	$OpenBSD: if_iwnreg.h,v 1.49 2014/09/09 18:56:24 sthen Exp $	*/
3fd43cf6eSHans Rosenfeld 
4fd43cf6eSHans Rosenfeld /*-
5fd43cf6eSHans Rosenfeld  * Copyright (c) 2007, 2008
6fd43cf6eSHans Rosenfeld  *	Damien Bergamini <damien.bergamini@free.fr>
7fd43cf6eSHans Rosenfeld  *
8fd43cf6eSHans Rosenfeld  * Permission to use, copy, modify, and distribute this software for any
9fd43cf6eSHans Rosenfeld  * purpose with or without fee is hereby granted, provided that the above
10fd43cf6eSHans Rosenfeld  * copyright notice and this permission notice appear in all copies.
11fd43cf6eSHans Rosenfeld  *
12fd43cf6eSHans Rosenfeld  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13fd43cf6eSHans Rosenfeld  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14fd43cf6eSHans Rosenfeld  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15fd43cf6eSHans Rosenfeld  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16fd43cf6eSHans Rosenfeld  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17fd43cf6eSHans Rosenfeld  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18fd43cf6eSHans Rosenfeld  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19fd43cf6eSHans Rosenfeld  */
20fd43cf6eSHans Rosenfeld 
21fd43cf6eSHans Rosenfeld /*
22fd43cf6eSHans Rosenfeld  * Copyright 2016 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
23fd43cf6eSHans Rosenfeld  */
24fd43cf6eSHans Rosenfeld 
25fd43cf6eSHans Rosenfeld #ifndef _IF_IWNREG_H
26fd43cf6eSHans Rosenfeld #define _IF_IWNREG_H
27fd43cf6eSHans Rosenfeld 
28fd43cf6eSHans Rosenfeld /* XXX Added for NetBSD */
29fd43cf6eSHans Rosenfeld #define IEEE80211_TKIP_MICLEN	8
30fd43cf6eSHans Rosenfeld 
31fd43cf6eSHans Rosenfeld #define IWN_TX_RING_COUNT	256
32fd43cf6eSHans Rosenfeld #define IWN_TX_RING_LOMARK	192
33fd43cf6eSHans Rosenfeld #define IWN_TX_RING_HIMARK	224
34fd43cf6eSHans Rosenfeld #define IWN_RX_RING_COUNT_LOG	6
35fd43cf6eSHans Rosenfeld #define IWN_RX_RING_COUNT	(1 << IWN_RX_RING_COUNT_LOG)
36fd43cf6eSHans Rosenfeld 
37fd43cf6eSHans Rosenfeld #define IWN4965_NTXQUEUES	16
38fd43cf6eSHans Rosenfeld #define IWN5000_NTXQUEUES	20
39fd43cf6eSHans Rosenfeld 
40fd43cf6eSHans Rosenfeld #define IWN_CMD_QUEUE_NUM	4
41fd43cf6eSHans Rosenfeld 
42fd43cf6eSHans Rosenfeld #define IWN4965_NDMACHNLS	7
43fd43cf6eSHans Rosenfeld #define IWN5000_NDMACHNLS	8
44fd43cf6eSHans Rosenfeld 
45fd43cf6eSHans Rosenfeld #define IWN_SRVC_DMACHNL	9
46fd43cf6eSHans Rosenfeld 
47fd43cf6eSHans Rosenfeld #define IWN_KW_SIZE		4096
48fd43cf6eSHans Rosenfeld 
49fd43cf6eSHans Rosenfeld #define IWN_ICT_SIZE		4096
50fd43cf6eSHans Rosenfeld #define IWN_ICT_COUNT		(IWN_ICT_SIZE / sizeof (uint32_t))
51fd43cf6eSHans Rosenfeld 
52fd43cf6eSHans Rosenfeld /* Maximum number of DMA segments for TX. */
53fd43cf6eSHans Rosenfeld #define IWN_MAX_SCATTER	20
54fd43cf6eSHans Rosenfeld 
55fd43cf6eSHans Rosenfeld /* RX buffers must be large enough to hold a full 4K A-MPDU. */
56fd43cf6eSHans Rosenfeld #define IWN_RBUF_SIZE	(4 * 1024)
57fd43cf6eSHans Rosenfeld 
58fd43cf6eSHans Rosenfeld #define IWN_TBUF_SIZE	(4 * 1024)
59fd43cf6eSHans Rosenfeld 
60fd43cf6eSHans Rosenfeld 
61fd43cf6eSHans Rosenfeld #if defined(_LP64)
62fd43cf6eSHans Rosenfeld /* HW supports 36-bit DMA addresses. */
63fd43cf6eSHans Rosenfeld #define IWN_LOADDR(paddr)	((uint32_t)(paddr))
64fd43cf6eSHans Rosenfeld #define IWN_HIADDR(paddr)	(((paddr) >> 32) & 0xf)
65fd43cf6eSHans Rosenfeld #else
66fd43cf6eSHans Rosenfeld #define IWN_LOADDR(paddr)	(paddr)
67fd43cf6eSHans Rosenfeld #define IWN_HIADDR(paddr)	(0)
68fd43cf6eSHans Rosenfeld #endif
69fd43cf6eSHans Rosenfeld 
70fd43cf6eSHans Rosenfeld /* Base Address Register. */
71fd43cf6eSHans Rosenfeld #define IWN_PCI_BAR0	PCI_MAPREG_START
72fd43cf6eSHans Rosenfeld 
73fd43cf6eSHans Rosenfeld /*
74fd43cf6eSHans Rosenfeld  * Control and status registers.
75fd43cf6eSHans Rosenfeld  */
76fd43cf6eSHans Rosenfeld #define IWN_HW_IF_CONFIG	0x000
77fd43cf6eSHans Rosenfeld #define IWN_INT_COALESCING	0x004
78fd43cf6eSHans Rosenfeld #define IWN_INT_PERIODIC	0x005	/* use IWN_WRITE_1 */
79fd43cf6eSHans Rosenfeld #define IWN_INT			0x008
80fd43cf6eSHans Rosenfeld #define IWN_INT_MASK		0x00c
81fd43cf6eSHans Rosenfeld #define IWN_FH_INT		0x010
82fd43cf6eSHans Rosenfeld #define IWN_RESET		0x020
83fd43cf6eSHans Rosenfeld #define IWN_GP_CNTRL		0x024
84fd43cf6eSHans Rosenfeld #define IWN_HW_REV		0x028
85fd43cf6eSHans Rosenfeld #define IWN_EEPROM		0x02c
86fd43cf6eSHans Rosenfeld #define IWN_EEPROM_GP		0x030
87fd43cf6eSHans Rosenfeld #define IWN_OTP_GP		0x034
88fd43cf6eSHans Rosenfeld #define IWN_GIO			0x03c
89fd43cf6eSHans Rosenfeld #define IWN_GP_DRIVER		0x050
90fd43cf6eSHans Rosenfeld #define IWN_UCODE_GP1_CLR	0x05c
91fd43cf6eSHans Rosenfeld #define IWN_LED			0x094
92fd43cf6eSHans Rosenfeld #define IWN_DRAM_INT_TBL	0x0a0
93fd43cf6eSHans Rosenfeld #define IWN_SHADOW_REG_CTRL	0x0a8
94fd43cf6eSHans Rosenfeld #define IWN_GIO_CHICKEN		0x100
95fd43cf6eSHans Rosenfeld #define IWN_ANA_PLL		0x20c
96fd43cf6eSHans Rosenfeld #define IWN_HW_REV_WA		0x22c
97fd43cf6eSHans Rosenfeld #define IWN_DBG_HPET_MEM	0x240
98fd43cf6eSHans Rosenfeld #define IWN_DBG_LINK_PWR_MGMT	0x250
99fd43cf6eSHans Rosenfeld #define IWN_MEM_RADDR		0x40c
100fd43cf6eSHans Rosenfeld #define IWN_MEM_WADDR		0x410
101fd43cf6eSHans Rosenfeld #define IWN_MEM_WDATA		0x418
102fd43cf6eSHans Rosenfeld #define IWN_MEM_RDATA		0x41c
103*b302a200SToomas Soome #define IWN_PRPH_WADDR		0x444
104*b302a200SToomas Soome #define IWN_PRPH_RADDR		0x448
105*b302a200SToomas Soome #define IWN_PRPH_WDATA		0x44c
106*b302a200SToomas Soome #define IWN_PRPH_RDATA		0x450
107fd43cf6eSHans Rosenfeld #define IWN_HBUS_TARG_WRPTR	0x460
108fd43cf6eSHans Rosenfeld 
109fd43cf6eSHans Rosenfeld /*
110fd43cf6eSHans Rosenfeld  * Flow-Handler registers.
111fd43cf6eSHans Rosenfeld  */
112fd43cf6eSHans Rosenfeld #define IWN_FH_TFBD_CTRL0(qid)		(0x1900 + (qid) * 8)
113fd43cf6eSHans Rosenfeld #define IWN_FH_TFBD_CTRL1(qid)		(0x1904 + (qid) * 8)
114fd43cf6eSHans Rosenfeld #define IWN_FH_KW_ADDR			0x197c
115fd43cf6eSHans Rosenfeld #define IWN_FH_SRAM_ADDR(qid)		(0x19a4 + (qid) * 4)
116fd43cf6eSHans Rosenfeld #define IWN_FH_CBBC_QUEUE(qid)		(0x19d0 + (qid) * 4)
117fd43cf6eSHans Rosenfeld #define IWN_FH_STATUS_WPTR		0x1bc0
118fd43cf6eSHans Rosenfeld #define IWN_FH_RX_BASE			0x1bc4
119fd43cf6eSHans Rosenfeld #define IWN_FH_RX_WPTR			0x1bc8
120fd43cf6eSHans Rosenfeld #define IWN_FH_RX_CONFIG		0x1c00
121fd43cf6eSHans Rosenfeld #define IWN_FH_RX_STATUS		0x1c44
122fd43cf6eSHans Rosenfeld #define IWN_FH_TX_CONFIG(qid)		(0x1d00 + (qid) * 32)
123fd43cf6eSHans Rosenfeld #define IWN_FH_TXBUF_STATUS(qid)	(0x1d08 + (qid) * 32)
124fd43cf6eSHans Rosenfeld #define IWN_FH_TX_CHICKEN		0x1e98
125fd43cf6eSHans Rosenfeld #define IWN_FH_TX_STATUS		0x1eb0
126fd43cf6eSHans Rosenfeld 
127fd43cf6eSHans Rosenfeld /*
128fd43cf6eSHans Rosenfeld  * TX scheduler registers.
129fd43cf6eSHans Rosenfeld  */
130fd43cf6eSHans Rosenfeld #define IWN_SCHED_BASE			0xa02c00
131fd43cf6eSHans Rosenfeld #define IWN_SCHED_SRAM_ADDR		(IWN_SCHED_BASE + 0x000)
132fd43cf6eSHans Rosenfeld #define IWN5000_SCHED_DRAM_ADDR		(IWN_SCHED_BASE + 0x008)
133fd43cf6eSHans Rosenfeld #define IWN4965_SCHED_DRAM_ADDR		(IWN_SCHED_BASE + 0x010)
134fd43cf6eSHans Rosenfeld #define IWN5000_SCHED_TXFACT		(IWN_SCHED_BASE + 0x010)
135fd43cf6eSHans Rosenfeld #define IWN4965_SCHED_TXFACT		(IWN_SCHED_BASE + 0x01c)
136fd43cf6eSHans Rosenfeld #define IWN4965_SCHED_QUEUE_RDPTR(qid)	(IWN_SCHED_BASE + 0x064 + (qid) * 4)
137fd43cf6eSHans Rosenfeld #define IWN5000_SCHED_QUEUE_RDPTR(qid)	(IWN_SCHED_BASE + 0x068 + (qid) * 4)
138fd43cf6eSHans Rosenfeld #define IWN4965_SCHED_QCHAIN_SEL	(IWN_SCHED_BASE + 0x0d0)
139fd43cf6eSHans Rosenfeld #define IWN4965_SCHED_INTR_MASK		(IWN_SCHED_BASE + 0x0e4)
140fd43cf6eSHans Rosenfeld #define IWN5000_SCHED_QCHAIN_SEL	(IWN_SCHED_BASE + 0x0e8)
141fd43cf6eSHans Rosenfeld #define IWN4965_SCHED_QUEUE_STATUS(qid)	(IWN_SCHED_BASE + 0x104 + (qid) * 4)
142fd43cf6eSHans Rosenfeld #define IWN5000_SCHED_INTR_MASK		(IWN_SCHED_BASE + 0x108)
143fd43cf6eSHans Rosenfeld #define IWN5000_SCHED_QUEUE_STATUS(qid)	(IWN_SCHED_BASE + 0x10c + (qid) * 4)
144fd43cf6eSHans Rosenfeld #define IWN5000_SCHED_AGGR_SEL		(IWN_SCHED_BASE + 0x248)
145fd43cf6eSHans Rosenfeld 
146fd43cf6eSHans Rosenfeld /*
147fd43cf6eSHans Rosenfeld  * Offsets in TX scheduler's SRAM.
148fd43cf6eSHans Rosenfeld  */
149fd43cf6eSHans Rosenfeld #define IWN4965_SCHED_CTX_OFF		0x380
150fd43cf6eSHans Rosenfeld #define IWN4965_SCHED_CTX_LEN		416
151fd43cf6eSHans Rosenfeld #define IWN4965_SCHED_QUEUE_OFFSET(qid)	(0x380 + (qid) * 8)
152fd43cf6eSHans Rosenfeld #define IWN4965_SCHED_TRANS_TBL(qid)	(0x500 + (qid) * 2)
153fd43cf6eSHans Rosenfeld #define IWN5000_SCHED_CTX_OFF		0x600
154fd43cf6eSHans Rosenfeld #define IWN5000_SCHED_CTX_LEN		520
155fd43cf6eSHans Rosenfeld #define IWN5000_SCHED_QUEUE_OFFSET(qid)	(0x600 + (qid) * 8)
156fd43cf6eSHans Rosenfeld #define IWN5000_SCHED_TRANS_TBL(qid)	(0x7e0 + (qid) * 2)
157fd43cf6eSHans Rosenfeld 
158fd43cf6eSHans Rosenfeld /*
159fd43cf6eSHans Rosenfeld  * NIC internal memory offsets.
160fd43cf6eSHans Rosenfeld  */
161fd43cf6eSHans Rosenfeld #define IWN_APMG_CLK_CTRL	0x3000
162fd43cf6eSHans Rosenfeld #define IWN_APMG_CLK_EN		0x3004
163fd43cf6eSHans Rosenfeld #define IWN_APMG_CLK_DIS	0x3008
164fd43cf6eSHans Rosenfeld #define IWN_APMG_PS		0x300c
165fd43cf6eSHans Rosenfeld #define IWN_APMG_DIGITAL_SVR	0x3058
166fd43cf6eSHans Rosenfeld #define IWN_APMG_ANALOG_SVR	0x306c
167fd43cf6eSHans Rosenfeld #define IWN_APMG_PCI_STT	0x3010
168fd43cf6eSHans Rosenfeld #define IWN_BSM_WR_CTRL		0x3400
169fd43cf6eSHans Rosenfeld #define IWN_BSM_WR_MEM_SRC	0x3404
170fd43cf6eSHans Rosenfeld #define IWN_BSM_WR_MEM_DST	0x3408
171fd43cf6eSHans Rosenfeld #define IWN_BSM_WR_DWCOUNT	0x340c
172fd43cf6eSHans Rosenfeld #define IWN_BSM_DRAM_TEXT_ADDR	0x3490
173fd43cf6eSHans Rosenfeld #define IWN_BSM_DRAM_TEXT_SIZE	0x3494
174fd43cf6eSHans Rosenfeld #define IWN_BSM_DRAM_DATA_ADDR	0x3498
175fd43cf6eSHans Rosenfeld #define IWN_BSM_DRAM_DATA_SIZE	0x349c
176fd43cf6eSHans Rosenfeld #define IWN_BSM_SRAM_BASE	0x3800
177fd43cf6eSHans Rosenfeld 
178fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_HW_IF_CONFIG. */
179fd43cf6eSHans Rosenfeld #define IWN_HW_IF_CONFIG_4965_R		(1 <<  4)
180fd43cf6eSHans Rosenfeld #define IWN_HW_IF_CONFIG_MAC_SI		(1 <<  8)
181fd43cf6eSHans Rosenfeld #define IWN_HW_IF_CONFIG_RADIO_SI	(1 <<  9)
182fd43cf6eSHans Rosenfeld #define IWN_HW_IF_CONFIG_EEPROM_LOCKED	(1 << 21)
183fd43cf6eSHans Rosenfeld #define IWN_HW_IF_CONFIG_NIC_READY	(1 << 22)
184fd43cf6eSHans Rosenfeld #define IWN_HW_IF_CONFIG_HAP_WAKE_L1A	(1 << 23)
185fd43cf6eSHans Rosenfeld #define IWN_HW_IF_CONFIG_PREPARE_DONE	(1 << 25)
186fd43cf6eSHans Rosenfeld #define IWN_HW_IF_CONFIG_PREPARE	(1 << 27)
187fd43cf6eSHans Rosenfeld 
188fd43cf6eSHans Rosenfeld /* Possible values for register IWN_INT_PERIODIC. */
189fd43cf6eSHans Rosenfeld #define IWN_INT_PERIODIC_DIS	0x00
190fd43cf6eSHans Rosenfeld #define IWN_INT_PERIODIC_ENA	0xff
191fd43cf6eSHans Rosenfeld 
192fd43cf6eSHans Rosenfeld /* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */
193fd43cf6eSHans Rosenfeld #define IWN_PRPH_DWORD	((sizeof (uint32_t) - 1) << 24)
194fd43cf6eSHans Rosenfeld 
195fd43cf6eSHans Rosenfeld /* Possible values for IWN_BSM_WR_MEM_DST. */
196fd43cf6eSHans Rosenfeld #define IWN_FW_TEXT_BASE	0x00000000
197fd43cf6eSHans Rosenfeld #define IWN_FW_DATA_BASE	0x00800000
198fd43cf6eSHans Rosenfeld 
199fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_RESET. */
200fd43cf6eSHans Rosenfeld #define IWN_RESET_NEVO			(1U << 0)
201fd43cf6eSHans Rosenfeld #define IWN_RESET_SW			(1U << 7)
202fd43cf6eSHans Rosenfeld #define IWN_RESET_MASTER_DISABLED	(1U << 8)
203fd43cf6eSHans Rosenfeld #define IWN_RESET_STOP_MASTER		(1U << 9)
204fd43cf6eSHans Rosenfeld #define IWN_RESET_LINK_PWR_MGMT_DIS	(1U << 31)
205fd43cf6eSHans Rosenfeld 
206fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_GP_CNTRL. */
207fd43cf6eSHans Rosenfeld #define IWN_GP_CNTRL_MAC_ACCESS_ENA	(1 << 0)
208fd43cf6eSHans Rosenfeld #define IWN_GP_CNTRL_MAC_CLOCK_READY	(1 << 0)
209fd43cf6eSHans Rosenfeld #define IWN_GP_CNTRL_INIT_DONE		(1 << 2)
210fd43cf6eSHans Rosenfeld #define IWN_GP_CNTRL_MAC_ACCESS_REQ	(1 << 3)
211fd43cf6eSHans Rosenfeld #define IWN_GP_CNTRL_SLEEP		(1 << 4)
212fd43cf6eSHans Rosenfeld #define IWN_GP_CNTRL_RFKILL		(1 << 27)
213fd43cf6eSHans Rosenfeld 
214fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_HW_REV. */
215fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_SHIFT	4
216fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_MASK	0x000001f0
217fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_4965	0
218fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_5300	2
219fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_5350	3
220fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_5150	4
221fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_5100	5
222fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_1000	6
223fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_6000	7
224fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_6050	8
225fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_6005	11
226fd43cf6eSHans Rosenfeld /* Types 6030 and 6035 also return 11 */
227fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_2030	12
228fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_2000	16
229fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_105	17
230fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_135	18
231fd43cf6eSHans Rosenfeld 
232fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_GIO_CHICKEN. */
233fd43cf6eSHans Rosenfeld #define IWN_GIO_CHICKEN_L1A_NO_L0S_RX	(1 << 23)
234fd43cf6eSHans Rosenfeld #define IWN_GIO_CHICKEN_DIS_L0S_TIMER	(1 << 29)
235fd43cf6eSHans Rosenfeld 
236fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_GIO. */
237fd43cf6eSHans Rosenfeld #define IWN_GIO_L0S_ENA		(1 << 1)
238fd43cf6eSHans Rosenfeld 
239fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_GP_DRIVER. */
240fd43cf6eSHans Rosenfeld #define IWN_GP_DRIVER_RADIO_3X3_HYB	(0 << 0)
241fd43cf6eSHans Rosenfeld #define IWN_GP_DRIVER_RADIO_2X2_HYB	(1 << 0)
242fd43cf6eSHans Rosenfeld #define IWN_GP_DRIVER_RADIO_2X2_IPA	(2 << 0)
243fd43cf6eSHans Rosenfeld #define IWN_GP_DRIVER_CALIB_VER6	(1 << 2)
244fd43cf6eSHans Rosenfeld #define IWN_GP_DRIVER_6050_1X2		(1 << 3)
245fd43cf6eSHans Rosenfeld #define IWN_GP_DRIVER_RADIO_IQ_INVERT	(1 << 7)
246fd43cf6eSHans Rosenfeld 
247fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_UCODE_GP1_CLR. */
248fd43cf6eSHans Rosenfeld #define IWN_UCODE_GP1_RFKILL		(1 << 1)
249fd43cf6eSHans Rosenfeld #define IWN_UCODE_GP1_CMD_BLOCKED	(1 << 2)
250fd43cf6eSHans Rosenfeld #define IWN_UCODE_GP1_CTEMP_STOP_RF	(1 << 3)
251fd43cf6eSHans Rosenfeld 
252fd43cf6eSHans Rosenfeld /* Possible flags/values for register IWN_LED. */
253fd43cf6eSHans Rosenfeld #define IWN_LED_BSM_CTRL	(1 << 5)
254fd43cf6eSHans Rosenfeld #define IWN_LED_OFF		0x00000038
255fd43cf6eSHans Rosenfeld #define IWN_LED_ON		0x00000078
256fd43cf6eSHans Rosenfeld 
257fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_DRAM_INT_TBL. */
258fd43cf6eSHans Rosenfeld #define IWN_DRAM_INT_TBL_WRAP_CHECK	(1 << 27)
259fd43cf6eSHans Rosenfeld #define IWN_DRAM_INT_TBL_ENABLE		(1 << 31)
260fd43cf6eSHans Rosenfeld 
261fd43cf6eSHans Rosenfeld /* Possible values for register IWN_ANA_PLL. */
262fd43cf6eSHans Rosenfeld #define IWN_ANA_PLL_INIT	0x00880300
263fd43cf6eSHans Rosenfeld 
264fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_FH_RX_STATUS. */
265fd43cf6eSHans Rosenfeld #define	IWN_FH_RX_STATUS_IDLE	(1 << 24)
266fd43cf6eSHans Rosenfeld 
267fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_BSM_WR_CTRL. */
268fd43cf6eSHans Rosenfeld #define IWN_BSM_WR_CTRL_START_EN	(1 << 30)
269fd43cf6eSHans Rosenfeld #define IWN_BSM_WR_CTRL_START		(1 << 31)
270fd43cf6eSHans Rosenfeld 
271fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_INT. */
272fd43cf6eSHans Rosenfeld #define IWN_INT_ALIVE		(1 <<  0)
273fd43cf6eSHans Rosenfeld #define IWN_INT_WAKEUP		(1 <<  1)
274fd43cf6eSHans Rosenfeld #define IWN_INT_SW_RX		(1 <<  3)
275fd43cf6eSHans Rosenfeld #define IWN_INT_CT_REACHED	(1 <<  6)
276fd43cf6eSHans Rosenfeld #define IWN_INT_RF_TOGGLED	(1 <<  7)
277fd43cf6eSHans Rosenfeld #define IWN_INT_SW_ERR		(1 << 25)
278fd43cf6eSHans Rosenfeld #define IWN_INT_SCHED		(1 << 26)
279fd43cf6eSHans Rosenfeld #define IWN_INT_FH_TX		(1 << 27)
280fd43cf6eSHans Rosenfeld #define IWN_INT_RX_PERIODIC	(1 << 28)
281fd43cf6eSHans Rosenfeld #define IWN_INT_HW_ERR		(1 << 29)
282fd43cf6eSHans Rosenfeld #define IWN_INT_FH_RX		(1U << 31)
283fd43cf6eSHans Rosenfeld 
284fd43cf6eSHans Rosenfeld /* Shortcut. */
285fd43cf6eSHans Rosenfeld #define IWN_INT_MASK_DEF						\
286fd43cf6eSHans Rosenfeld 	(IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX |		\
287fd43cf6eSHans Rosenfeld 	 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP |		\
288fd43cf6eSHans Rosenfeld 	 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED)
289fd43cf6eSHans Rosenfeld 
290fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_FH_INT. */
291fd43cf6eSHans Rosenfeld #define IWN_FH_INT_TX_CHNL(x)	(1 << (x))
292fd43cf6eSHans Rosenfeld #define IWN_FH_INT_RX_CHNL(x)	(1 << ((x) + 16))
293fd43cf6eSHans Rosenfeld #define IWN_FH_INT_HI_PRIOR	(1 << 30)
294fd43cf6eSHans Rosenfeld /* Shortcuts for the above. */
295fd43cf6eSHans Rosenfeld #define IWN_FH_INT_TX							\
296fd43cf6eSHans Rosenfeld 	(IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1))
297fd43cf6eSHans Rosenfeld #define IWN_FH_INT_RX							\
298fd43cf6eSHans Rosenfeld 	(IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR)
299fd43cf6eSHans Rosenfeld 
300fd43cf6eSHans Rosenfeld /* Possible flags/values for register IWN_FH_TX_CONFIG. */
301fd43cf6eSHans Rosenfeld #define IWN_FH_TX_CONFIG_DMA_PAUSE		0
302fd43cf6eSHans Rosenfeld #define IWN_FH_TX_CONFIG_DMA_ENA		(1U << 31)
303fd43cf6eSHans Rosenfeld #define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD	(1U << 20)
304fd43cf6eSHans Rosenfeld 
305fd43cf6eSHans Rosenfeld /* Possible flags/values for register IWN_FH_TXBUF_STATUS. */
306fd43cf6eSHans Rosenfeld #define IWN_FH_TXBUF_STATUS_TBNUM(x)	((x) << 20)
307fd43cf6eSHans Rosenfeld #define IWN_FH_TXBUF_STATUS_TBIDX(x)	((x) << 12)
308fd43cf6eSHans Rosenfeld #define IWN_FH_TXBUF_STATUS_TFBD_VALID	3
309fd43cf6eSHans Rosenfeld 
310fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_FH_TX_CHICKEN. */
311fd43cf6eSHans Rosenfeld #define IWN_FH_TX_CHICKEN_SCHED_RETRY	(1 << 1)
312fd43cf6eSHans Rosenfeld 
313fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_FH_TX_STATUS. */
314fd43cf6eSHans Rosenfeld #define IWN_FH_TX_STATUS_IDLE(chnl)	(1 << ((chnl) + 16))
315fd43cf6eSHans Rosenfeld 
316fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_FH_RX_CONFIG. */
317fd43cf6eSHans Rosenfeld #define IWN_FH_RX_CONFIG_ENA		(1U << 31)
318fd43cf6eSHans Rosenfeld #define IWN_FH_RX_CONFIG_NRBD(x)	((x) << 20)
319fd43cf6eSHans Rosenfeld #define IWN_FH_RX_CONFIG_RB_SIZE_8K	(1U << 16)
320fd43cf6eSHans Rosenfeld #define IWN_FH_RX_CONFIG_SINGLE_FRAME	(1U << 15)
321fd43cf6eSHans Rosenfeld #define IWN_FH_RX_CONFIG_IRQ_DST_HOST	(1U << 12)
322fd43cf6eSHans Rosenfeld #define IWN_FH_RX_CONFIG_RB_TIMEOUT(x)	((x) << 4)
323fd43cf6eSHans Rosenfeld #define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY	(1U <<  2)
324fd43cf6eSHans Rosenfeld 
325fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_FH_TX_CONFIG. */
326fd43cf6eSHans Rosenfeld #define IWN_FH_TX_CONFIG_DMA_ENA	(1U << 31)
327fd43cf6eSHans Rosenfeld #define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA	(1U <<  3)
328fd43cf6eSHans Rosenfeld 
329fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_EEPROM. */
330fd43cf6eSHans Rosenfeld #define IWN_EEPROM_READ_VALID	(1 << 0)
331fd43cf6eSHans Rosenfeld #define IWN_EEPROM_CMD		(1 << 1)
332fd43cf6eSHans Rosenfeld 
333fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_EEPROM_GP. */
334fd43cf6eSHans Rosenfeld #define IWN_EEPROM_GP_IF_OWNER	0x00000180
335fd43cf6eSHans Rosenfeld 
336fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_OTP_GP. */
337fd43cf6eSHans Rosenfeld #define IWN_OTP_GP_DEV_SEL_OTP		(1 << 16)
338fd43cf6eSHans Rosenfeld #define IWN_OTP_GP_RELATIVE_ACCESS	(1 << 17)
339fd43cf6eSHans Rosenfeld #define IWN_OTP_GP_ECC_CORR_STTS	(1 << 20)
340fd43cf6eSHans Rosenfeld #define IWN_OTP_GP_ECC_UNCORR_STTS	(1 << 21)
341fd43cf6eSHans Rosenfeld 
342fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_SCHED_QUEUE_STATUS. */
343fd43cf6eSHans Rosenfeld #define IWN4965_TXQ_STATUS_ACTIVE	0x0007fc01
344fd43cf6eSHans Rosenfeld #define IWN4965_TXQ_STATUS_INACTIVE	0x0007fc00
345fd43cf6eSHans Rosenfeld #define IWN4965_TXQ_STATUS_AGGR_ENA	(1 << 5 | 1 << 8)
346fd43cf6eSHans Rosenfeld #define IWN4965_TXQ_STATUS_CHGACT	(1 << 10)
347fd43cf6eSHans Rosenfeld #define IWN5000_TXQ_STATUS_ACTIVE	0x00ff0018
348fd43cf6eSHans Rosenfeld #define IWN5000_TXQ_STATUS_INACTIVE	0x00ff0010
349fd43cf6eSHans Rosenfeld #define IWN5000_TXQ_STATUS_CHGACT	(1 << 19)
350fd43cf6eSHans Rosenfeld 
351fd43cf6eSHans Rosenfeld /* Possible flags for registers IWN_APMG_CLK_*. */
352fd43cf6eSHans Rosenfeld #define IWN_APMG_CLK_CTRL_DMA_CLK_RQT	(1 <<  9)
353fd43cf6eSHans Rosenfeld #define IWN_APMG_CLK_CTRL_BSM_CLK_RQT	(1 << 11)
354fd43cf6eSHans Rosenfeld 
355fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_APMG_PS. */
356fd43cf6eSHans Rosenfeld #define IWN_APMG_PS_EARLY_PWROFF_DIS	(1 << 22)
357fd43cf6eSHans Rosenfeld #define IWN_APMG_PS_PWR_SRC(x)		((x) << 24)
358fd43cf6eSHans Rosenfeld #define IWN_APMG_PS_PWR_SRC_VMAIN	0
359fd43cf6eSHans Rosenfeld #define IWN_APMG_PS_PWR_SRC_VAUX	2
360fd43cf6eSHans Rosenfeld #define IWN_APMG_PS_PWR_SRC_MASK	IWN_APMG_PS_PWR_SRC(3)
361fd43cf6eSHans Rosenfeld #define IWN_APMG_PS_RESET_REQ		(1 << 26)
362fd43cf6eSHans Rosenfeld 
363fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_APMG_DIGITAL_SVR. */
364fd43cf6eSHans Rosenfeld #define IWN_APMG_DIGITAL_SVR_VOLTAGE(x)		(((x) & 0xf) << 5)
365fd43cf6eSHans Rosenfeld #define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK	\
366fd43cf6eSHans Rosenfeld 	IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf)
367fd43cf6eSHans Rosenfeld #define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32	\
368fd43cf6eSHans Rosenfeld 	IWN_APMG_DIGITAL_SVR_VOLTAGE(3)
369fd43cf6eSHans Rosenfeld 
370fd43cf6eSHans Rosenfeld /* Possible flags for IWN_APMG_PCI_STT. */
371fd43cf6eSHans Rosenfeld #define IWN_APMG_PCI_STT_L1A_DIS	(1 << 11)
372fd43cf6eSHans Rosenfeld 
373fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */
374fd43cf6eSHans Rosenfeld #define IWN_FW_UPDATED	(1U << 31)
375fd43cf6eSHans Rosenfeld 
376fd43cf6eSHans Rosenfeld #define IWN_SCHED_WINSZ		64
377fd43cf6eSHans Rosenfeld #define IWN_SCHED_LIMIT		64
378fd43cf6eSHans Rosenfeld #define IWN4965_SCHED_COUNT	512
379fd43cf6eSHans Rosenfeld #define IWN5000_SCHED_COUNT	(IWN_TX_RING_COUNT + IWN_SCHED_WINSZ)
380fd43cf6eSHans Rosenfeld #define IWN4965_SCHEDSZ		(IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2)
381fd43cf6eSHans Rosenfeld #define IWN5000_SCHEDSZ		(IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2)
382fd43cf6eSHans Rosenfeld 
383fd43cf6eSHans Rosenfeld struct iwn_tx_desc {
384fd43cf6eSHans Rosenfeld 	uint8_t		reserved1[3];
385fd43cf6eSHans Rosenfeld 	uint8_t		nsegs;
386fd43cf6eSHans Rosenfeld 	struct {
387fd43cf6eSHans Rosenfeld 		uint32_t	addr;
388fd43cf6eSHans Rosenfeld 		uint16_t	len;
389fd43cf6eSHans Rosenfeld 	} __packed	segs[IWN_MAX_SCATTER];
390fd43cf6eSHans Rosenfeld 	/* Pad to 128 bytes. */
391fd43cf6eSHans Rosenfeld 	uint32_t	reserved2;
392fd43cf6eSHans Rosenfeld } __packed;
393fd43cf6eSHans Rosenfeld 
394fd43cf6eSHans Rosenfeld struct iwn_rx_status {
395fd43cf6eSHans Rosenfeld 	uint16_t	closed_count;
396fd43cf6eSHans Rosenfeld 	uint16_t	closed_rx_count;
397fd43cf6eSHans Rosenfeld 	uint16_t	finished_count;
398fd43cf6eSHans Rosenfeld 	uint16_t	finished_rx_count;
399fd43cf6eSHans Rosenfeld 	uint32_t	reserved[2];
400fd43cf6eSHans Rosenfeld } __packed;
401fd43cf6eSHans Rosenfeld 
402fd43cf6eSHans Rosenfeld struct iwn_rx_desc {
403fd43cf6eSHans Rosenfeld 	uint32_t	len;
404fd43cf6eSHans Rosenfeld 	uint8_t		type;
405fd43cf6eSHans Rosenfeld #define IWN_UC_READY			  1
406fd43cf6eSHans Rosenfeld #define IWN_ADD_NODE_DONE		 24
407fd43cf6eSHans Rosenfeld #define IWN_TX_DONE			 28
408fd43cf6eSHans Rosenfeld #define IWN5000_CALIBRATION_RESULT	102
409fd43cf6eSHans Rosenfeld #define IWN5000_CALIBRATION_DONE	103
410fd43cf6eSHans Rosenfeld #define IWN_START_SCAN			130
411fd43cf6eSHans Rosenfeld #define IWN_STOP_SCAN			132
412fd43cf6eSHans Rosenfeld #define IWN_RX_STATISTICS		156
413fd43cf6eSHans Rosenfeld #define IWN_BEACON_STATISTICS		157
414fd43cf6eSHans Rosenfeld #define IWN_STATE_CHANGED		161
415fd43cf6eSHans Rosenfeld #define IWN_BEACON_MISSED		162
416fd43cf6eSHans Rosenfeld #define IWN_RX_PHY			192
417fd43cf6eSHans Rosenfeld #define IWN_MPDU_RX_DONE		193
418fd43cf6eSHans Rosenfeld #define IWN_RX_DONE			195
419fd43cf6eSHans Rosenfeld #define IWN_RX_COMPRESSED_BA		197
420fd43cf6eSHans Rosenfeld 
421fd43cf6eSHans Rosenfeld 	uint8_t		flags;
422fd43cf6eSHans Rosenfeld 	uint8_t		idx;
423fd43cf6eSHans Rosenfeld 	uint8_t		qid;
424fd43cf6eSHans Rosenfeld } __packed;
425fd43cf6eSHans Rosenfeld 
426fd43cf6eSHans Rosenfeld /* Possible RX status flags. */
427fd43cf6eSHans Rosenfeld #define IWN_RX_NO_CRC_ERR	(1 <<  0)
428fd43cf6eSHans Rosenfeld #define IWN_RX_NO_OVFL_ERR	(1 <<  1)
429fd43cf6eSHans Rosenfeld /* Shortcut for the above. */
430fd43cf6eSHans Rosenfeld #define IWN_RX_NOERROR	(IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR)
431fd43cf6eSHans Rosenfeld #define IWN_RX_MPDU_MIC_OK	(1 <<  6)
432fd43cf6eSHans Rosenfeld #define IWN_RX_CIPHER_MASK	(7 <<  8)
433fd43cf6eSHans Rosenfeld #define IWN_RX_CIPHER_CCMP	(2 <<  8)
434fd43cf6eSHans Rosenfeld #define IWN_RX_MPDU_DEC		(1 << 11)
435fd43cf6eSHans Rosenfeld #define IWN_RX_DECRYPT_MASK	(3 << 11)
436fd43cf6eSHans Rosenfeld #define IWN_RX_DECRYPT_OK	(3 << 11)
437fd43cf6eSHans Rosenfeld 
438fd43cf6eSHans Rosenfeld struct iwn_tx_cmd {
439fd43cf6eSHans Rosenfeld 	uint8_t	code;
440fd43cf6eSHans Rosenfeld #define IWN_CMD_RXON			 16
441fd43cf6eSHans Rosenfeld #define IWN_CMD_RXON_ASSOC		 17
442fd43cf6eSHans Rosenfeld #define IWN_CMD_EDCA_PARAMS		 19
443fd43cf6eSHans Rosenfeld #define IWN_CMD_TIMING			 20
444fd43cf6eSHans Rosenfeld #define IWN_CMD_ADD_NODE		 24
445fd43cf6eSHans Rosenfeld #define IWN_CMD_TX_DATA			 28
446fd43cf6eSHans Rosenfeld #define IWN_CMD_SET_LED			 72
447fd43cf6eSHans Rosenfeld #define IWN_CMD_LINK_QUALITY		 78
448fd43cf6eSHans Rosenfeld #define IWN5000_CMD_WIMAX_COEX		 90
449fd43cf6eSHans Rosenfeld #define IWN5000_CMD_CALIB_CONFIG	101
450fd43cf6eSHans Rosenfeld #define IWN_CMD_SET_POWER_MODE		119
451fd43cf6eSHans Rosenfeld #define IWN_CMD_SCAN			128
452fd43cf6eSHans Rosenfeld #define IWN_CMD_TXPOWER_DBM		149
453fd43cf6eSHans Rosenfeld #define IWN_CMD_TXPOWER			151
454fd43cf6eSHans Rosenfeld #define IWN5000_CMD_TX_ANT_CONFIG	152
455fd43cf6eSHans Rosenfeld #define IWN_CMD_BT_COEX			155
456fd43cf6eSHans Rosenfeld #define IWN_CMD_GET_STATISTICS		156
457fd43cf6eSHans Rosenfeld #define IWN_CMD_SET_CRITICAL_TEMP	164
458fd43cf6eSHans Rosenfeld #define IWN_CMD_SET_SENSITIVITY		168
459fd43cf6eSHans Rosenfeld #define IWN_CMD_PHY_CALIB		176
460fd43cf6eSHans Rosenfeld #define IWN_CMD_BT_COEX_PRIO_TABLE	204
461fd43cf6eSHans Rosenfeld #define IWN_CMD_BT_COEX_PROT		205
462fd43cf6eSHans Rosenfeld 
463fd43cf6eSHans Rosenfeld 	uint8_t	flags;
464fd43cf6eSHans Rosenfeld 	uint8_t	idx;
465fd43cf6eSHans Rosenfeld 	uint8_t	qid;
466fd43cf6eSHans Rosenfeld 	uint8_t	data[136];
467fd43cf6eSHans Rosenfeld } __packed;
468fd43cf6eSHans Rosenfeld 
469fd43cf6eSHans Rosenfeld /* Antenna flags, used in various commands. */
470fd43cf6eSHans Rosenfeld #define IWN_ANT_A	(1 << 0)
471fd43cf6eSHans Rosenfeld #define IWN_ANT_B	(1 << 1)
472fd43cf6eSHans Rosenfeld #define IWN_ANT_C	(1 << 2)
473fd43cf6eSHans Rosenfeld /* Shortcuts. */
474fd43cf6eSHans Rosenfeld #define IWN_ANT_AB	(IWN_ANT_A | IWN_ANT_B)
475fd43cf6eSHans Rosenfeld #define IWN_ANT_BC	(IWN_ANT_B | IWN_ANT_C)
476fd43cf6eSHans Rosenfeld #define IWN_ANT_ABC	(IWN_ANT_A | IWN_ANT_B | IWN_ANT_C)
477fd43cf6eSHans Rosenfeld 
478fd43cf6eSHans Rosenfeld /* Structure for command IWN_CMD_RXON. */
479fd43cf6eSHans Rosenfeld struct iwn_rxon {
480fd43cf6eSHans Rosenfeld 	uint8_t		myaddr[IEEE80211_ADDR_LEN];
481fd43cf6eSHans Rosenfeld 	uint16_t	reserved1;
482fd43cf6eSHans Rosenfeld 	uint8_t		bssid[IEEE80211_ADDR_LEN];
483fd43cf6eSHans Rosenfeld 	uint16_t	reserved2;
484fd43cf6eSHans Rosenfeld 	uint8_t		wlap[IEEE80211_ADDR_LEN];
485fd43cf6eSHans Rosenfeld 	uint16_t	reserved3;
486fd43cf6eSHans Rosenfeld 	uint8_t		mode;
487fd43cf6eSHans Rosenfeld #define IWN_MODE_HOSTAP		1
488fd43cf6eSHans Rosenfeld #define IWN_MODE_STA		3
489fd43cf6eSHans Rosenfeld #define IWN_MODE_IBSS		4
490fd43cf6eSHans Rosenfeld #define IWN_MODE_MONITOR	6
491fd43cf6eSHans Rosenfeld 
492fd43cf6eSHans Rosenfeld 	uint8_t		air;
493fd43cf6eSHans Rosenfeld 	uint16_t	rxchain;
494fd43cf6eSHans Rosenfeld #define IWN_RXCHAIN_DRIVER_FORCE	(1 << 0)
495fd43cf6eSHans Rosenfeld #define IWN_RXCHAIN_VALID(x)		(((x) & IWN_ANT_ABC) << 1)
496fd43cf6eSHans Rosenfeld #define IWN_RXCHAIN_FORCE_SEL(x)	(((x) & IWN_ANT_ABC) << 4)
497fd43cf6eSHans Rosenfeld #define IWN_RXCHAIN_FORCE_MIMO_SEL(x)	(((x) & IWN_ANT_ABC) << 7)
498fd43cf6eSHans Rosenfeld #define IWN_RXCHAIN_IDLE_COUNT(x)	((x) << 10)
499fd43cf6eSHans Rosenfeld #define IWN_RXCHAIN_MIMO_COUNT(x)	((x) << 12)
500fd43cf6eSHans Rosenfeld #define IWN_RXCHAIN_MIMO_FORCE		(1 << 14)
501fd43cf6eSHans Rosenfeld 
502fd43cf6eSHans Rosenfeld 	uint8_t		ofdm_mask;
503fd43cf6eSHans Rosenfeld 	uint8_t		cck_mask;
504fd43cf6eSHans Rosenfeld 	uint16_t	associd;
505fd43cf6eSHans Rosenfeld 	uint32_t	flags;
506fd43cf6eSHans Rosenfeld #define IWN_RXON_24GHZ		(1 <<  0)
507fd43cf6eSHans Rosenfeld #define IWN_RXON_CCK		(1 <<  1)
508fd43cf6eSHans Rosenfeld #define IWN_RXON_AUTO		(1 <<  2)
509fd43cf6eSHans Rosenfeld #define IWN_RXON_SHSLOT		(1 <<  4)
510fd43cf6eSHans Rosenfeld #define IWN_RXON_SHPREAMBLE	(1 <<  5)
511fd43cf6eSHans Rosenfeld #define IWN_RXON_NODIVERSITY	(1 <<  7)
512fd43cf6eSHans Rosenfeld #define IWN_RXON_ANTENNA_A	(1 <<  8)
513fd43cf6eSHans Rosenfeld #define IWN_RXON_ANTENNA_B	(1 <<  9)
514fd43cf6eSHans Rosenfeld #define IWN_RXON_TSF		(1 << 15)
515fd43cf6eSHans Rosenfeld #define IWN_RXON_CTS_TO_SELF	(1 << 30)
516fd43cf6eSHans Rosenfeld 
517fd43cf6eSHans Rosenfeld 	uint32_t	filter;
518fd43cf6eSHans Rosenfeld #define IWN_FILTER_PROMISC	(1 << 0)
519fd43cf6eSHans Rosenfeld #define IWN_FILTER_CTL		(1 << 1)
520fd43cf6eSHans Rosenfeld #define IWN_FILTER_MULTICAST	(1 << 2)
521fd43cf6eSHans Rosenfeld #define IWN_FILTER_NODECRYPT	(1 << 3)
522fd43cf6eSHans Rosenfeld #define IWN_FILTER_MC_NODECRYPT	(1 << 4)
523fd43cf6eSHans Rosenfeld #define IWN_FILTER_BSS		(1 << 5)
524fd43cf6eSHans Rosenfeld #define IWN_FILTER_BEACON	(1 << 6)
525fd43cf6eSHans Rosenfeld 
526fd43cf6eSHans Rosenfeld 	uint8_t		chan;
527fd43cf6eSHans Rosenfeld 	uint8_t		reserved4;
528fd43cf6eSHans Rosenfeld 	uint8_t		ht_single_mask;
529fd43cf6eSHans Rosenfeld 	uint8_t		ht_dual_mask;
530fd43cf6eSHans Rosenfeld 	/* The following fields are for >=5000 Series only. */
531fd43cf6eSHans Rosenfeld 	uint8_t		ht_triple_mask;
532fd43cf6eSHans Rosenfeld 	uint8_t		reserved5;
533fd43cf6eSHans Rosenfeld 	uint16_t	acquisition;
534fd43cf6eSHans Rosenfeld 	uint16_t	reserved6;
535fd43cf6eSHans Rosenfeld } __packed;
536fd43cf6eSHans Rosenfeld 
537fd43cf6eSHans Rosenfeld #define IWN4965_RXONSZ	(sizeof (struct iwn_rxon) - 6)
538fd43cf6eSHans Rosenfeld #define IWN5000_RXONSZ	(sizeof (struct iwn_rxon))
539fd43cf6eSHans Rosenfeld 
540fd43cf6eSHans Rosenfeld /* Structure for command IWN_CMD_ASSOCIATE. */
541fd43cf6eSHans Rosenfeld struct iwn_assoc {
542fd43cf6eSHans Rosenfeld 	uint32_t	flags;
543fd43cf6eSHans Rosenfeld 	uint32_t	filter;
544fd43cf6eSHans Rosenfeld 	uint8_t		ofdm_mask;
545fd43cf6eSHans Rosenfeld 	uint8_t		cck_mask;
546fd43cf6eSHans Rosenfeld 	uint16_t	reserved;
547fd43cf6eSHans Rosenfeld } __packed;
548fd43cf6eSHans Rosenfeld 
549fd43cf6eSHans Rosenfeld /* Structure for command IWN_CMD_EDCA_PARAMS. */
550fd43cf6eSHans Rosenfeld struct iwn_edca_params {
551fd43cf6eSHans Rosenfeld 	uint32_t	flags;
552fd43cf6eSHans Rosenfeld #define IWN_EDCA_UPDATE	(1 << 0)
553fd43cf6eSHans Rosenfeld #define IWN_EDCA_TXOP	(1 << 4)
554fd43cf6eSHans Rosenfeld 
555fd43cf6eSHans Rosenfeld 	struct {
556fd43cf6eSHans Rosenfeld 		uint16_t	cwmin;
557fd43cf6eSHans Rosenfeld 		uint16_t	cwmax;
558fd43cf6eSHans Rosenfeld 		uint8_t		aifsn;
559fd43cf6eSHans Rosenfeld 		uint8_t		reserved;
560fd43cf6eSHans Rosenfeld 		uint16_t	txoplimit;
561fd43cf6eSHans Rosenfeld 	} __packed	ac[WME_NUM_AC];
562fd43cf6eSHans Rosenfeld } __packed;
563fd43cf6eSHans Rosenfeld 
564fd43cf6eSHans Rosenfeld /* Structure for command IWN_CMD_TIMING. */
565fd43cf6eSHans Rosenfeld struct iwn_cmd_timing {
566fd43cf6eSHans Rosenfeld 	uint64_t	tstamp;
567fd43cf6eSHans Rosenfeld 	uint16_t	bintval;
568fd43cf6eSHans Rosenfeld 	uint16_t	atim;
569fd43cf6eSHans Rosenfeld 	uint32_t	binitval;
570fd43cf6eSHans Rosenfeld 	uint16_t	lintval;
571fd43cf6eSHans Rosenfeld 	uint16_t	reserved;
572fd43cf6eSHans Rosenfeld } __packed;
573fd43cf6eSHans Rosenfeld 
574fd43cf6eSHans Rosenfeld /* Structure for command IWN_CMD_ADD_NODE. */
575fd43cf6eSHans Rosenfeld struct iwn_node_info {
576fd43cf6eSHans Rosenfeld 	uint8_t		control;
577fd43cf6eSHans Rosenfeld #define IWN_NODE_UPDATE		(1 << 0)
578fd43cf6eSHans Rosenfeld 
579fd43cf6eSHans Rosenfeld 	uint8_t		reserved1[3];
580fd43cf6eSHans Rosenfeld 
581fd43cf6eSHans Rosenfeld 	uint8_t		macaddr[IEEE80211_ADDR_LEN];
582fd43cf6eSHans Rosenfeld 	uint16_t	reserved2;
583fd43cf6eSHans Rosenfeld 	uint8_t		id;
584fd43cf6eSHans Rosenfeld #define IWN_ID_BSS		 0
585fd43cf6eSHans Rosenfeld #define IWN5000_ID_BROADCAST	15
586fd43cf6eSHans Rosenfeld #define IWN4965_ID_BROADCAST	31
587fd43cf6eSHans Rosenfeld 
588fd43cf6eSHans Rosenfeld 	uint8_t		flags;
589fd43cf6eSHans Rosenfeld #define IWN_FLAG_SET_KEY		(1 << 0)
590fd43cf6eSHans Rosenfeld #define IWN_FLAG_SET_DISABLE_TID	(1 << 1)
591fd43cf6eSHans Rosenfeld #define IWN_FLAG_SET_TXRATE		(1 << 2)
592fd43cf6eSHans Rosenfeld #define IWN_FLAG_SET_ADDBA		(1 << 3)
593fd43cf6eSHans Rosenfeld #define IWN_FLAG_SET_DELBA		(1 << 4)
594fd43cf6eSHans Rosenfeld 
595fd43cf6eSHans Rosenfeld 	uint16_t	reserved3;
596fd43cf6eSHans Rosenfeld 	uint16_t	kflags;
597fd43cf6eSHans Rosenfeld #define IWN_KFLAG_CCMP		(1 <<  1)
598fd43cf6eSHans Rosenfeld #define IWN_KFLAG_MAP		(1 <<  3)
599fd43cf6eSHans Rosenfeld #define IWN_KFLAG_KID(kid)	((kid) << 8)
600fd43cf6eSHans Rosenfeld #define IWN_KFLAG_INVALID	(1 << 11)
601fd43cf6eSHans Rosenfeld #define IWN_KFLAG_GROUP		(1 << 14)
602fd43cf6eSHans Rosenfeld 
603fd43cf6eSHans Rosenfeld 	uint8_t		tsc2;	/* TKIP TSC2 */
604fd43cf6eSHans Rosenfeld 	uint8_t		reserved4;
605fd43cf6eSHans Rosenfeld 	uint16_t	ttak[5];
606fd43cf6eSHans Rosenfeld 	uint8_t		kid;
607fd43cf6eSHans Rosenfeld 	uint8_t		reserved5;
608fd43cf6eSHans Rosenfeld 	uint8_t		key[16];
609fd43cf6eSHans Rosenfeld 	/* The following 3 fields are for 5000 Series only. */
610fd43cf6eSHans Rosenfeld 	uint64_t	tsc;
611fd43cf6eSHans Rosenfeld 	uint8_t		rxmic[IEEE80211_TKIP_MICLEN];
612fd43cf6eSHans Rosenfeld 	uint8_t		txmic[IEEE80211_TKIP_MICLEN];
613fd43cf6eSHans Rosenfeld 
614fd43cf6eSHans Rosenfeld 	uint32_t	htflags;
615fd43cf6eSHans Rosenfeld #define IWN_AMDPU_SIZE_FACTOR(x)	((x) << 19)
616fd43cf6eSHans Rosenfeld #define IWN_AMDPU_DENSITY(x)		((x) << 23)
617fd43cf6eSHans Rosenfeld 
618fd43cf6eSHans Rosenfeld 	uint32_t	mask;
619fd43cf6eSHans Rosenfeld 	uint16_t	disable_tid;
620fd43cf6eSHans Rosenfeld 	uint16_t	reserved6;
621fd43cf6eSHans Rosenfeld 	uint8_t		addba_tid;
622fd43cf6eSHans Rosenfeld 	uint8_t		delba_tid;
623fd43cf6eSHans Rosenfeld 	uint16_t	addba_ssn;
624fd43cf6eSHans Rosenfeld 	uint32_t	reserved7;
625fd43cf6eSHans Rosenfeld } __packed;
626fd43cf6eSHans Rosenfeld 
627fd43cf6eSHans Rosenfeld struct iwn4965_node_info {
628fd43cf6eSHans Rosenfeld 	uint8_t		control;
629fd43cf6eSHans Rosenfeld 	uint8_t		reserved1[3];
630fd43cf6eSHans Rosenfeld 	uint8_t		macaddr[IEEE80211_ADDR_LEN];
631fd43cf6eSHans Rosenfeld 	uint16_t	reserved2;
632fd43cf6eSHans Rosenfeld 	uint8_t		id;
633fd43cf6eSHans Rosenfeld 	uint8_t		flags;
634fd43cf6eSHans Rosenfeld 	uint16_t	reserved3;
635fd43cf6eSHans Rosenfeld 	uint16_t	kflags;
636fd43cf6eSHans Rosenfeld 	uint8_t		tsc2;	/* TKIP TSC2 */
637fd43cf6eSHans Rosenfeld 	uint8_t		reserved4;
638fd43cf6eSHans Rosenfeld 	uint16_t	ttak[5];
639fd43cf6eSHans Rosenfeld 	uint8_t		kid;
640fd43cf6eSHans Rosenfeld 	uint8_t		reserved5;
641fd43cf6eSHans Rosenfeld 	uint8_t		key[16];
642fd43cf6eSHans Rosenfeld 	uint32_t	htflags;
643fd43cf6eSHans Rosenfeld 	uint32_t	mask;
644fd43cf6eSHans Rosenfeld 	uint16_t	disable_tid;
645fd43cf6eSHans Rosenfeld 	uint16_t	reserved6;
646fd43cf6eSHans Rosenfeld 	uint8_t		addba_tid;
647fd43cf6eSHans Rosenfeld 	uint8_t		delba_tid;
648fd43cf6eSHans Rosenfeld 	uint16_t	addba_ssn;
649fd43cf6eSHans Rosenfeld 	uint32_t	reserved7;
650fd43cf6eSHans Rosenfeld } __packed;
651fd43cf6eSHans Rosenfeld 
652fd43cf6eSHans Rosenfeld #define IWN_RFLAG_CCK		(1 << 1)
653fd43cf6eSHans Rosenfeld #define IWN_RFLAG_ANT(x)	((x) << 6)
654fd43cf6eSHans Rosenfeld 
655fd43cf6eSHans Rosenfeld /* Structure for command IWN_CMD_TX_DATA. */
656fd43cf6eSHans Rosenfeld struct iwn_cmd_data {
657fd43cf6eSHans Rosenfeld 	uint16_t	len;
658fd43cf6eSHans Rosenfeld 	uint16_t	lnext;
659fd43cf6eSHans Rosenfeld 	uint32_t	flags;
660fd43cf6eSHans Rosenfeld #define IWN_TX_NEED_PROTECTION	(1 <<  0)	/* 5000 only */
661fd43cf6eSHans Rosenfeld #define IWN_TX_NEED_RTS		(1 <<  1)
662fd43cf6eSHans Rosenfeld #define IWN_TX_NEED_CTS		(1 <<  2)
663fd43cf6eSHans Rosenfeld #define IWN_TX_NEED_ACK		(1 <<  3)
664fd43cf6eSHans Rosenfeld #define IWN_TX_LINKQ		(1 <<  4)
665fd43cf6eSHans Rosenfeld #define IWN_TX_IMM_BA		(1 <<  6)
666fd43cf6eSHans Rosenfeld #define IWN_TX_FULL_TXOP	(1 <<  7)
667fd43cf6eSHans Rosenfeld #define IWN_TX_BT_DISABLE	(1 << 12)	/* bluetooth coexistence */
668fd43cf6eSHans Rosenfeld #define IWN_TX_AUTO_SEQ		(1 << 13)
669fd43cf6eSHans Rosenfeld #define IWN_TX_MORE_FRAG	(1 << 14)
670fd43cf6eSHans Rosenfeld #define IWN_TX_INSERT_TSTAMP	(1 << 16)
671fd43cf6eSHans Rosenfeld #define IWN_TX_NEED_PADDING	(1 << 20)
672fd43cf6eSHans Rosenfeld 
673fd43cf6eSHans Rosenfeld 	uint32_t	scratch;
674fd43cf6eSHans Rosenfeld 	uint8_t		plcp;
675fd43cf6eSHans Rosenfeld 	uint8_t		rflags;
676fd43cf6eSHans Rosenfeld 	uint16_t	xrflags;
677fd43cf6eSHans Rosenfeld 
678fd43cf6eSHans Rosenfeld 	uint8_t		id;
679fd43cf6eSHans Rosenfeld 	uint8_t		security;
680fd43cf6eSHans Rosenfeld #define IWN_CIPHER_WEP40	1
681fd43cf6eSHans Rosenfeld #define IWN_CIPHER_CCMP		2
682fd43cf6eSHans Rosenfeld #define IWN_CIPHER_TKIP		3
683fd43cf6eSHans Rosenfeld #define IWN_CIPHER_WEP104	9
684fd43cf6eSHans Rosenfeld 
685fd43cf6eSHans Rosenfeld 	uint8_t		linkq;
686fd43cf6eSHans Rosenfeld 	uint8_t		reserved2;
687fd43cf6eSHans Rosenfeld 	uint8_t		key[16];
688fd43cf6eSHans Rosenfeld 	uint16_t	fnext;
689fd43cf6eSHans Rosenfeld 	uint16_t	reserved3;
690fd43cf6eSHans Rosenfeld 	uint32_t	lifetime;
691fd43cf6eSHans Rosenfeld #define IWN_LIFETIME_INFINITE	0xffffffff
692fd43cf6eSHans Rosenfeld 
693fd43cf6eSHans Rosenfeld 	uint32_t	loaddr;
694fd43cf6eSHans Rosenfeld 	uint8_t		hiaddr;
695fd43cf6eSHans Rosenfeld 	uint8_t		rts_ntries;
696fd43cf6eSHans Rosenfeld 	uint8_t		data_ntries;
697fd43cf6eSHans Rosenfeld 	uint8_t		tid;
698fd43cf6eSHans Rosenfeld 	uint16_t	timeout;
699fd43cf6eSHans Rosenfeld 	uint16_t	txop;
700fd43cf6eSHans Rosenfeld } __packed;
701fd43cf6eSHans Rosenfeld 
702fd43cf6eSHans Rosenfeld /* Structure for command IWN_CMD_LINK_QUALITY. */
703fd43cf6eSHans Rosenfeld #define IWN_MAX_TX_RETRIES	16
704fd43cf6eSHans Rosenfeld struct iwn_cmd_link_quality {
705fd43cf6eSHans Rosenfeld 	uint8_t		id;
706fd43cf6eSHans Rosenfeld 	uint8_t		reserved1;
707fd43cf6eSHans Rosenfeld 	uint16_t	ctl;
708fd43cf6eSHans Rosenfeld 	uint8_t		flags;
709fd43cf6eSHans Rosenfeld 	uint8_t		mimo;
710fd43cf6eSHans Rosenfeld 	uint8_t		antmsk_1stream;
711fd43cf6eSHans Rosenfeld 	uint8_t		antmsk_2stream;
712fd43cf6eSHans Rosenfeld 	uint8_t		ridx[WME_NUM_AC];
713fd43cf6eSHans Rosenfeld 	uint16_t	ampdu_limit;
714fd43cf6eSHans Rosenfeld 	uint8_t		ampdu_threshold;
715fd43cf6eSHans Rosenfeld 	uint8_t		ampdu_max;
716fd43cf6eSHans Rosenfeld 	uint32_t	reserved2;
717fd43cf6eSHans Rosenfeld 	struct {
718fd43cf6eSHans Rosenfeld 		uint8_t		plcp;
719fd43cf6eSHans Rosenfeld 		uint8_t		rflags;
720fd43cf6eSHans Rosenfeld 		uint16_t	xrflags;
721fd43cf6eSHans Rosenfeld 	} __packed	retry[IWN_MAX_TX_RETRIES];
722fd43cf6eSHans Rosenfeld 	uint32_t	reserved3;
723fd43cf6eSHans Rosenfeld } __packed;
724fd43cf6eSHans Rosenfeld 
725fd43cf6eSHans Rosenfeld /* Structure for command IWN_CMD_SET_LED. */
726fd43cf6eSHans Rosenfeld struct iwn_cmd_led {
727fd43cf6eSHans Rosenfeld 	uint32_t	unit;	/* multiplier (in usecs) */
728fd43cf6eSHans Rosenfeld 	uint8_t		which;
729fd43cf6eSHans Rosenfeld #define IWN_LED_ACTIVITY	1
730fd43cf6eSHans Rosenfeld #define IWN_LED_LINK		2
731fd43cf6eSHans Rosenfeld 
732fd43cf6eSHans Rosenfeld 	uint8_t		off;
733fd43cf6eSHans Rosenfeld 	uint8_t		on;
734fd43cf6eSHans Rosenfeld 	uint8_t		reserved;
735fd43cf6eSHans Rosenfeld } __packed;
736fd43cf6eSHans Rosenfeld 
737fd43cf6eSHans Rosenfeld /* Structure for command IWN5000_CMD_WIMAX_COEX. */
738fd43cf6eSHans Rosenfeld struct iwn5000_wimax_coex {
739fd43cf6eSHans Rosenfeld 	uint32_t	flags;
740fd43cf6eSHans Rosenfeld #define IWN_WIMAX_COEX_STA_TABLE_VALID		(1 << 0)
741fd43cf6eSHans Rosenfeld #define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK	(1 << 2)
742fd43cf6eSHans Rosenfeld #define IWN_WIMAX_COEX_ASSOC_WA_UNMASK		(1 << 3)
743fd43cf6eSHans Rosenfeld #define IWN_WIMAX_COEX_ENABLE			(1 << 7)
744fd43cf6eSHans Rosenfeld 
745fd43cf6eSHans Rosenfeld 	struct iwn5000_wimax_event {
746fd43cf6eSHans Rosenfeld 		uint8_t	request;
747fd43cf6eSHans Rosenfeld 		uint8_t	window;
748fd43cf6eSHans Rosenfeld 		uint8_t	reserved;
749fd43cf6eSHans Rosenfeld 		uint8_t	flags;
750fd43cf6eSHans Rosenfeld 	} __packed	events[16];
751fd43cf6eSHans Rosenfeld } __packed;
752fd43cf6eSHans Rosenfeld 
753fd43cf6eSHans Rosenfeld /* Structures for command IWN5000_CMD_CALIB_CONFIG. */
754fd43cf6eSHans Rosenfeld struct iwn5000_calib_elem {
755fd43cf6eSHans Rosenfeld 	uint32_t	enable;
756fd43cf6eSHans Rosenfeld 	uint32_t	start;
757fd43cf6eSHans Rosenfeld #define IWN5000_CALIB_DC	(1 << 1)
758fd43cf6eSHans Rosenfeld 	uint32_t	send;
759fd43cf6eSHans Rosenfeld 	uint32_t	apply;
760fd43cf6eSHans Rosenfeld 	uint32_t	reserved;
761fd43cf6eSHans Rosenfeld } __packed;
762fd43cf6eSHans Rosenfeld 
763fd43cf6eSHans Rosenfeld struct iwn5000_calib_status {
764fd43cf6eSHans Rosenfeld 	struct iwn5000_calib_elem	once;
765fd43cf6eSHans Rosenfeld 	struct iwn5000_calib_elem	perd;
766fd43cf6eSHans Rosenfeld 	uint32_t			flags;
767fd43cf6eSHans Rosenfeld } __packed;
768fd43cf6eSHans Rosenfeld 
769fd43cf6eSHans Rosenfeld struct iwn5000_calib_config {
770