1*6bbbd442SRobert Mustacchi /*- 2*6bbbd442SRobert Mustacchi * Copyright 2021 Intel Corp 3*6bbbd442SRobert Mustacchi * Copyright 2021 Rubicon Communications, LLC (Netgate) 4*6bbbd442SRobert Mustacchi * SPDX-License-Identifier: BSD-3-Clause 5*6bbbd442SRobert Mustacchi */ 6*6bbbd442SRobert Mustacchi 7*6bbbd442SRobert Mustacchi #ifndef _IGC_PHY_H_ 8*6bbbd442SRobert Mustacchi #define _IGC_PHY_H_ 9*6bbbd442SRobert Mustacchi 10*6bbbd442SRobert Mustacchi void igc_init_phy_ops_generic(struct igc_hw *hw); 11*6bbbd442SRobert Mustacchi s32 igc_null_read_reg(struct igc_hw *hw, u32 offset, u16 *data); 12*6bbbd442SRobert Mustacchi void igc_null_phy_generic(struct igc_hw *hw); 13*6bbbd442SRobert Mustacchi s32 igc_null_lplu_state(struct igc_hw *hw, bool active); 14*6bbbd442SRobert Mustacchi s32 igc_null_write_reg(struct igc_hw *hw, u32 offset, u16 data); 15*6bbbd442SRobert Mustacchi s32 igc_null_set_page(struct igc_hw *hw, u16 data); 16*6bbbd442SRobert Mustacchi s32 igc_check_downshift_generic(struct igc_hw *hw); 17*6bbbd442SRobert Mustacchi s32 igc_check_reset_block_generic(struct igc_hw *hw); 18*6bbbd442SRobert Mustacchi s32 igc_get_phy_id(struct igc_hw *hw); 19*6bbbd442SRobert Mustacchi void igc_phy_force_speed_duplex_setup(struct igc_hw *hw, u16 *phy_ctrl); 20*6bbbd442SRobert Mustacchi s32 igc_phy_hw_reset_generic(struct igc_hw *hw); 21*6bbbd442SRobert Mustacchi s32 igc_phy_reset_dsp_generic(struct igc_hw *hw); 22*6bbbd442SRobert Mustacchi s32 igc_set_d3_lplu_state_generic(struct igc_hw *hw, bool active); 23*6bbbd442SRobert Mustacchi s32 igc_setup_copper_link_generic(struct igc_hw *hw); 24*6bbbd442SRobert Mustacchi s32 igc_phy_has_link_generic(struct igc_hw *hw, u32 iterations, 25*6bbbd442SRobert Mustacchi u32 usec_interval, bool *success); 26*6bbbd442SRobert Mustacchi enum igc_phy_type igc_get_phy_type_from_id(u32 phy_id); 27*6bbbd442SRobert Mustacchi s32 igc_determine_phy_address(struct igc_hw *hw); 28*6bbbd442SRobert Mustacchi s32 igc_enable_phy_wakeup_reg_access_bm(struct igc_hw *hw, u16 *phy_reg); 29*6bbbd442SRobert Mustacchi s32 igc_disable_phy_wakeup_reg_access_bm(struct igc_hw *hw, u16 *phy_reg); 30*6bbbd442SRobert Mustacchi void igc_power_up_phy_copper(struct igc_hw *hw); 31*6bbbd442SRobert Mustacchi void igc_power_down_phy_copper(struct igc_hw *hw); 32*6bbbd442SRobert Mustacchi s32 igc_read_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 *data); 33*6bbbd442SRobert Mustacchi s32 igc_write_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 data); 34*6bbbd442SRobert Mustacchi 35*6bbbd442SRobert Mustacchi s32 igc_read_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr, 36*6bbbd442SRobert Mustacchi u16 *data); 37*6bbbd442SRobert Mustacchi s32 igc_write_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr, 38*6bbbd442SRobert Mustacchi u16 data); 39*6bbbd442SRobert Mustacchi s32 igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data); 40*6bbbd442SRobert Mustacchi s32 igc_read_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 *data); 41*6bbbd442SRobert Mustacchi 42*6bbbd442SRobert Mustacchi #define IGC_MAX_PHY_ADDR 8 43*6bbbd442SRobert Mustacchi 44*6bbbd442SRobert Mustacchi /* IGP01IGC Specific Registers */ 45*6bbbd442SRobert Mustacchi #define IGP01IGC_PHY_PORT_CONFIG 0x10 /* Port Config */ 46*6bbbd442SRobert Mustacchi #define IGP01IGC_PHY_PORT_STATUS 0x11 /* Status */ 47*6bbbd442SRobert Mustacchi #define IGP01IGC_PHY_PORT_CTRL 0x12 /* Control */ 48*6bbbd442SRobert Mustacchi #define IGP01IGC_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ 49*6bbbd442SRobert Mustacchi #define IGP02IGC_PHY_POWER_MGMT 0x19 /* Power Management */ 50*6bbbd442SRobert Mustacchi #define IGP01IGC_PHY_PAGE_SELECT 0x1F /* Page Select */ 51*6bbbd442SRobert Mustacchi #define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */ 52*6bbbd442SRobert Mustacchi #define IGP_PAGE_SHIFT 5 53*6bbbd442SRobert Mustacchi #define PHY_REG_MASK 0x1F 54*6bbbd442SRobert Mustacchi #define IGC_I225_PHPM 0x0E14 /* I225 PHY Power Management */ 55*6bbbd442SRobert Mustacchi #define IGC_I225_PHPM_DIS_1000_D3 0x0008 /* Disable 1G in D3 */ 56*6bbbd442SRobert Mustacchi #define IGC_I225_PHPM_LINK_ENERGY 0x0010 /* Link Energy Detect */ 57*6bbbd442SRobert Mustacchi #define IGC_I225_PHPM_GO_LINKD 0x0020 /* Go Link Disconnect */ 58*6bbbd442SRobert Mustacchi #define IGC_I225_PHPM_DIS_1000 0x0040 /* Disable 1G globally */ 59*6bbbd442SRobert Mustacchi #define IGC_I225_PHPM_SPD_B2B_EN 0x0080 /* Smart Power Down Back2Back */ 60*6bbbd442SRobert Mustacchi #define IGC_I225_PHPM_RST_COMPL 0x0100 /* PHY Reset Completed */ 61*6bbbd442SRobert Mustacchi #define IGC_I225_PHPM_DIS_100_D3 0x0200 /* Disable 100M in D3 */ 62*6bbbd442SRobert Mustacchi #define IGC_I225_PHPM_ULP 0x0400 /* Ultra Low-Power Mode */ 63*6bbbd442SRobert Mustacchi #define IGC_I225_PHPM_DIS_2500 0x0800 /* Disable 2.5G globally */ 64*6bbbd442SRobert Mustacchi #define IGC_I225_PHPM_DIS_2500_D3 0x1000 /* Disable 2.5G in D3 */ 65*6bbbd442SRobert Mustacchi /* GPY211 - I225 defines */ 66*6bbbd442SRobert Mustacchi #define GPY_MMD_MASK 0xFFFF0000 67*6bbbd442SRobert Mustacchi #define GPY_MMD_SHIFT 16 68*6bbbd442SRobert Mustacchi #define GPY_REG_MASK 0x0000FFFF 69*6bbbd442SRobert Mustacchi #define IGP01IGC_PHY_PCS_INIT_REG 0x00B4 70*6bbbd442SRobert Mustacchi #define IGP01IGC_PHY_POLARITY_MASK 0x0078 71*6bbbd442SRobert Mustacchi 72*6bbbd442SRobert Mustacchi #define IGP01IGC_PSCR_AUTO_MDIX 0x1000 73*6bbbd442SRobert Mustacchi #define IGP01IGC_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ 74*6bbbd442SRobert Mustacchi 75*6bbbd442SRobert Mustacchi #define IGP01IGC_PSCFR_SMART_SPEED 0x0080 76*6bbbd442SRobert Mustacchi 77*6bbbd442SRobert Mustacchi #define IGP02IGC_PM_SPD 0x0001 /* Smart Power Down */ 78*6bbbd442SRobert Mustacchi #define IGP02IGC_PM_D0_LPLU 0x0002 /* For D0a states */ 79*6bbbd442SRobert Mustacchi #define IGP02IGC_PM_D3_LPLU 0x0004 /* For all other states */ 80*6bbbd442SRobert Mustacchi 81*6bbbd442SRobert Mustacchi #define IGP01IGC_PLHR_SS_DOWNGRADE 0x8000 82*6bbbd442SRobert Mustacchi 83*6bbbd442SRobert Mustacchi #define IGP01IGC_PSSR_POLARITY_REVERSED 0x0002 84*6bbbd442SRobert Mustacchi #define IGP01IGC_PSSR_MDIX 0x0800 85*6bbbd442SRobert Mustacchi #define IGP01IGC_PSSR_SPEED_MASK 0xC000 86*6bbbd442SRobert Mustacchi #define IGP01IGC_PSSR_SPEED_1000MBPS 0xC000 87*6bbbd442SRobert Mustacchi 88*6bbbd442SRobert Mustacchi #define IGP02IGC_PHY_CHANNEL_NUM 4 89*6bbbd442SRobert Mustacchi #define IGP02IGC_PHY_AGC_A 0x11B1 90*6bbbd442SRobert Mustacchi #define IGP02IGC_PHY_AGC_B 0x12B1 91*6bbbd442SRobert Mustacchi #define IGP02IGC_PHY_AGC_C 0x14B1 92*6bbbd442SRobert Mustacchi #define IGP02IGC_PHY_AGC_D 0x18B1 93*6bbbd442SRobert Mustacchi 94*6bbbd442SRobert Mustacchi #define IGP02IGC_AGC_LENGTH_SHIFT 9 /* Course=15:13, Fine=12:9 */ 95*6bbbd442SRobert Mustacchi #define IGP02IGC_AGC_LENGTH_MASK 0x7F 96*6bbbd442SRobert Mustacchi #define IGP02IGC_AGC_RANGE 15 97*6bbbd442SRobert Mustacchi 98*6bbbd442SRobert Mustacchi #define IGC_CABLE_LENGTH_UNDEFINED 0xFF 99*6bbbd442SRobert Mustacchi 100*6bbbd442SRobert Mustacchi #define IGC_KMRNCTRLSTA_OFFSET 0x001F0000 101*6bbbd442SRobert Mustacchi #define IGC_KMRNCTRLSTA_OFFSET_SHIFT 16 102*6bbbd442SRobert Mustacchi #define IGC_KMRNCTRLSTA_REN 0x00200000 103*6bbbd442SRobert Mustacchi #define IGC_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */ 104*6bbbd442SRobert Mustacchi #define IGC_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */ 105*6bbbd442SRobert Mustacchi #define IGC_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */ 106*6bbbd442SRobert Mustacchi #define IGC_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */ 107*6bbbd442SRobert Mustacchi #define IGC_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */ 108*6bbbd442SRobert Mustacchi 109*6bbbd442SRobert Mustacchi #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 110*6bbbd442SRobert Mustacchi #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Ctrl */ 111*6bbbd442SRobert Mustacchi #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Ctrl */ 112*6bbbd442SRobert Mustacchi #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */ 113*6bbbd442SRobert Mustacchi 114*6bbbd442SRobert Mustacchi /* IFE PHY Extended Status Control */ 115*6bbbd442SRobert Mustacchi #define IFE_PESC_POLARITY_REVERSED 0x0100 116*6bbbd442SRobert Mustacchi 117*6bbbd442SRobert Mustacchi /* IFE PHY Special Control */ 118*6bbbd442SRobert Mustacchi #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 119*6bbbd442SRobert Mustacchi #define IFE_PSC_FORCE_POLARITY 0x0020 120*6bbbd442SRobert Mustacchi 121*6bbbd442SRobert Mustacchi /* IFE PHY Special Control and LED Control */ 122*6bbbd442SRobert Mustacchi #define IFE_PSCL_PROBE_MODE 0x0020 123*6bbbd442SRobert Mustacchi #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ 124*6bbbd442SRobert Mustacchi #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ 125*6bbbd442SRobert Mustacchi 126*6bbbd442SRobert Mustacchi /* IFE PHY MDIX Control */ 127*6bbbd442SRobert Mustacchi #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ 128*6bbbd442SRobert Mustacchi #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */ 129*6bbbd442SRobert Mustacchi #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto, 0=disable */ 130*6bbbd442SRobert Mustacchi 131*6bbbd442SRobert Mustacchi #endif 132